Andy K / MODDMA

MODDMA GPDMA Controller New features: transfer pins to memory buffer under periodic timer control and send double buffers to DAC

Dependents:   FirstTest WaveSim IO-dma-memmem DACDMAfuncgenlib ... more

SETUP.cpp@17:97a16bf2ff43, 2013-03-02 (annotated)

Committer:
AjK
Date:
Sat Mar 02 19:27:12 2013 +0000
Revision:
17:97a16bf2ff43
Parent:
16:cb10aec6feb1 
1.13 See ChangeLog.c

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AjK 8:cb4d323ce6fd 1 /*
AjK 8:cb4d323ce6fd 2 Copyright (c) 2010 Andy Kirkham
AjK 8:cb4d323ce6fd 3
AjK 8:cb4d323ce6fd 4 Permission is hereby granted, free of charge, to any person obtaining a copy
AjK 8:cb4d323ce6fd 5 of this software and associated documentation files (the "Software"), to deal
AjK 8:cb4d323ce6fd 6 in the Software without restriction, including without limitation the rights
AjK 8:cb4d323ce6fd 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
AjK 8:cb4d323ce6fd 8 copies of the Software, and to permit persons to whom the Software is
AjK 8:cb4d323ce6fd 9 furnished to do so, subject to the following conditions:
AjK 8:cb4d323ce6fd 10
AjK 8:cb4d323ce6fd 11 The above copyright notice and this permission notice shall be included in
AjK 8:cb4d323ce6fd 12 all copies or substantial portions of the Software.
AjK 8:cb4d323ce6fd 13
AjK 8:cb4d323ce6fd 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
AjK 8:cb4d323ce6fd 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
AjK 8:cb4d323ce6fd 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AjK 8:cb4d323ce6fd 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
AjK 8:cb4d323ce6fd 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
AjK 8:cb4d323ce6fd 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
AjK 8:cb4d323ce6fd 20 THE SOFTWARE.
AjK 8:cb4d323ce6fd 21 */
AjK 8:cb4d323ce6fd 22
AjK 8:cb4d323ce6fd 23 #include "MODDMA.h"
AjK 8:cb4d323ce6fd 24
AjK 8:cb4d323ce6fd 25 namespace AjK {
AjK 8:cb4d323ce6fd 26
AjK 8:cb4d323ce6fd 27 uint32_t
AjK 8:cb4d323ce6fd 28 MODDMA::Setup(MODDMA_Config *config)
AjK 8:cb4d323ce6fd 29 {
AjK 8:cb4d323ce6fd 30 LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( config->channelNum() );
AjK 8:cb4d323ce6fd 31
AjK 8:cb4d323ce6fd 32 setups[config->channelNum() & 0x7] = config;
AjK 8:cb4d323ce6fd 33
AjK 8:cb4d323ce6fd 34 // Reset the Interrupt status
AjK 8:cb4d323ce6fd 35 LPC_GPDMA->DMACIntTCClear = IntTCClear_Ch( config->channelNum() );
AjK 8:cb4d323ce6fd 36 LPC_GPDMA->DMACIntErrClr = IntErrClr_Ch ( config->channelNum() );
AjK 8:cb4d323ce6fd 37
AjK 8:cb4d323ce6fd 38 // Clear DMA configure
AjK 8:cb4d323ce6fd 39 pChannel->DMACCControl = 0x00;
AjK 8:cb4d323ce6fd 40 pChannel->DMACCConfig = 0x00;
AjK 8:cb4d323ce6fd 41
AjK 8:cb4d323ce6fd 42 // Assign Linker List Item value
AjK 8:cb4d323ce6fd 43 pChannel->DMACCLLI = config->dmaLLI();
AjK 8:cb4d323ce6fd 44
AjK 8:cb4d323ce6fd 45 // Set value to Channel Control Registers
AjK 8:cb4d323ce6fd 46 switch (config->transferType()) {
AjK 8:cb4d323ce6fd 47
AjK 8:cb4d323ce6fd 48 // Memory to memory
AjK 8:cb4d323ce6fd 49 case m2m:
AjK 8:cb4d323ce6fd 50 // Assign physical source and destination address
AjK 8:cb4d323ce6fd 51 pChannel->DMACCSrcAddr = config->srcMemAddr();
AjK 8:cb4d323ce6fd 52 pChannel->DMACCDestAddr = config->dstMemAddr();
AjK 8:cb4d323ce6fd 53 pChannel->DMACCControl
AjK 8:cb4d323ce6fd 54 = CxControl_TransferSize(config->transferSize())
AjK 8:cb4d323ce6fd 55 | CxControl_SBSize(_32)
AjK 8:cb4d323ce6fd 56 | CxControl_DBSize(_32)
AjK 8:cb4d323ce6fd 57 | CxControl_SWidth(config->transferWidth())
AjK 8:cb4d323ce6fd 58 | CxControl_DWidth(config->transferWidth())
AjK 8:cb4d323ce6fd 59 | CxControl_SI()
AjK 8:cb4d323ce6fd 60 | CxControl_DI()
AjK 8:cb4d323ce6fd 61 | CxControl_I();
AjK 8:cb4d323ce6fd 62 break;
AjK 16:cb10aec6feb1 63
AjK 8:cb4d323ce6fd 64 // Memory to peripheral
AjK 8:cb4d323ce6fd 65 case m2p:
AjK 8:cb4d323ce6fd 66 // Assign physical source
AjK 8:cb4d323ce6fd 67 pChannel->DMACCSrcAddr = config->srcMemAddr();
AjK 8:cb4d323ce6fd 68 // Assign peripheral destination address
AjK 8:cb4d323ce6fd 69 pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());
AjK 8:cb4d323ce6fd 70 pChannel->DMACCControl
AjK 8:cb4d323ce6fd 71 = CxControl_TransferSize((uint32_t)config->transferSize())
AjK 8:cb4d323ce6fd 72 | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn()))
AjK 8:cb4d323ce6fd 73 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn()))
AjK 8:cb4d323ce6fd 74 | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn()))
AjK 8:cb4d323ce6fd 75 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn()))
AjK 8:cb4d323ce6fd 76 | CxControl_SI()
AjK 8:cb4d323ce6fd 77 | CxControl_I();
AjK 8:cb4d323ce6fd 78 break;
AjK 8:cb4d323ce6fd 79
AjK 8:cb4d323ce6fd 80 // Peripheral to memory
AjK 8:cb4d323ce6fd 81 case p2m:
AjK 8:cb4d323ce6fd 82 // Assign peripheral source address
AjK 8:cb4d323ce6fd 83 pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());
AjK 8:cb4d323ce6fd 84 // Assign memory destination address
AjK 8:cb4d323ce6fd 85 pChannel->DMACCDestAddr = config->dstMemAddr();
AjK 8:cb4d323ce6fd 86 pChannel->DMACCControl
AjK 8:cb4d323ce6fd 87 = CxControl_TransferSize((uint32_t)config->transferSize())
AjK 8:cb4d323ce6fd 88 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn()))
AjK 8:cb4d323ce6fd 89 | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn()))
AjK 8:cb4d323ce6fd 90 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn()))
AjK 8:cb4d323ce6fd 91 | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn()))
AjK 8:cb4d323ce6fd 92 | CxControl_DI()
AjK 8:cb4d323ce6fd 93 | CxControl_I();
AjK 8:cb4d323ce6fd 94 break;
AjK 8:cb4d323ce6fd 95
AjK 8:cb4d323ce6fd 96 // Peripheral to peripheral
AjK 8:cb4d323ce6fd 97 case p2p:
AjK 8:cb4d323ce6fd 98 // Assign peripheral source address
AjK 8:cb4d323ce6fd 99 pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());
AjK 8:cb4d323ce6fd 100 // Assign peripheral destination address
AjK 8:cb4d323ce6fd 101 pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());
AjK 8:cb4d323ce6fd 102 pChannel->DMACCControl
AjK 8:cb4d323ce6fd 103 = CxControl_TransferSize((uint32_t)config->transferSize())
AjK 8:cb4d323ce6fd 104 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn()))
AjK 8:cb4d323ce6fd 105 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn()))
AjK 8:cb4d323ce6fd 106 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn()))
AjK 8:cb4d323ce6fd 107 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn()))
AjK 8:cb4d323ce6fd 108 | CxControl_I();
AjK 8:cb4d323ce6fd 109 break;
AjK 8:cb4d323ce6fd 110
AjK 12:1dfee7208043 111 // GPIO to memory
AjK 12:1dfee7208043 112 case g2m:
AjK 12:1dfee7208043 113 // Assign GPIO source address
AjK 12:1dfee7208043 114 pChannel->DMACCSrcAddr = config->srcMemAddr();
AjK 12:1dfee7208043 115 // Assign memory destination address
AjK 12:1dfee7208043 116 pChannel->DMACCDestAddr = config->dstMemAddr();
AjK 12:1dfee7208043 117 pChannel->DMACCControl
AjK 12:1dfee7208043 118 = CxControl_TransferSize((uint32_t)config->transferSize())
AjK 12:1dfee7208043 119 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn()))
AjK 12:1dfee7208043 120 | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn()))
AjK 12:1dfee7208043 121 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn()))
AjK 12:1dfee7208043 122 | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn()))
AjK 12:1dfee7208043 123 | CxControl_DI()
AjK 12:1dfee7208043 124 | CxControl_I();
AjK 12:1dfee7208043 125 break;
AjK 12:1dfee7208043 126
AjK 12:1dfee7208043 127 // Memory to GPIO
AjK 12:1dfee7208043 128 case m2g:
AjK 12:1dfee7208043 129 // Assign physical source
AjK 12:1dfee7208043 130 pChannel->DMACCSrcAddr = config->srcMemAddr();
AjK 12:1dfee7208043 131 // Assign peripheral destination address
AjK 12:1dfee7208043 132 pChannel->DMACCDestAddr = config->dstMemAddr();
AjK 12:1dfee7208043 133 pChannel->DMACCControl
AjK 12:1dfee7208043 134 = CxControl_TransferSize((uint32_t)config->transferSize())
AjK 12:1dfee7208043 135 | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn()))
AjK 12:1dfee7208043 136 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn()))
AjK 12:1dfee7208043 137 | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn()))
AjK 12:1dfee7208043 138 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn()))
AjK 12:1dfee7208043 139 | CxControl_SI()
AjK 12:1dfee7208043 140 | CxControl_I();
AjK 12:1dfee7208043 141 break;
AjK 12:1dfee7208043 142
AjK 8:cb4d323ce6fd 143 // Do not support any more transfer type, return ERROR
AjK 8:cb4d323ce6fd 144 default:
AjK 8:cb4d323ce6fd 145 return 0;
AjK 8:cb4d323ce6fd 146 }
AjK 8:cb4d323ce6fd 147
AjK 8:cb4d323ce6fd 148 // Re-Configure DMA Request Select for source peripheral
AjK 8:cb4d323ce6fd 149 if (config->srcConn() > 15) {
AjK 17:97a16bf2ff43 150 LPC_SC->DMAREQSEL |= (1 << (config->srcConn() - 16));
AjK 8:cb4d323ce6fd 151 }
AjK 8:cb4d323ce6fd 152 else {
AjK 17:97a16bf2ff43 153 LPC_SC->DMAREQSEL &= ~(1 << (config->srcConn() - 8));
AjK 8:cb4d323ce6fd 154 }
AjK 8:cb4d323ce6fd 155
AjK 12:1dfee7208043 156 // Re-Configure DMA Request Select for destination peripheral
AjK 8:cb4d323ce6fd 157 if (config->dstConn() > 15) {
AjK 17:97a16bf2ff43 158 LPC_SC->DMAREQSEL |= (1 << (config->dstConn() - 16));
AjK 8:cb4d323ce6fd 159 }
AjK 8:cb4d323ce6fd 160 else {
AjK 17:97a16bf2ff43 161 LPC_SC->DMAREQSEL &= ~(1 << (config->dstConn() - 8));
AjK 8:cb4d323ce6fd 162 }
AjK 8:cb4d323ce6fd 163
AjK 8:cb4d323ce6fd 164 // Enable DMA channels, little endian
AjK 8:cb4d323ce6fd 165 LPC_GPDMA->DMACConfig = _E;
AjK 8:cb4d323ce6fd 166 while (!(LPC_GPDMA->DMACConfig & _E));
AjK 8:cb4d323ce6fd 167
AjK 8:cb4d323ce6fd 168 // Calculate absolute value for Connection number
AjK 8:cb4d323ce6fd 169 uint32_t tmp1 = config->srcConn(); tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
AjK 8:cb4d323ce6fd 170 uint32_t tmp2 = config->dstConn(); tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
AjK 8:cb4d323ce6fd 171
AjK 12:1dfee7208043 172 if (config->dmacSync()) {
AjK 12:1dfee7208043 173 uint32_t tmp3 = config->dmacSync(); tmp3 = ((tmp3 > 15) ? (tmp3 - 8) : tmp3);
AjK 12:1dfee7208043 174 LPC_GPDMA->DMACSync |= Sync_Src( tmp3 );
AjK 12:1dfee7208043 175 }
AjK 12:1dfee7208043 176
AjK 12:1dfee7208043 177 uint32_t tfer_type = (uint32_t)config->transferType();
AjK 12:1dfee7208043 178 if (tfer_type == g2m || tfer_type == m2g) {
AjK 12:1dfee7208043 179 tfer_type -= 2; // Adjust psuedo transferType to a real transferType.
AjK 12:1dfee7208043 180 }
AjK 12:1dfee7208043 181
AjK 8:cb4d323ce6fd 182 // Configure DMA Channel, enable Error Counter and Terminate counter
AjK 8:cb4d323ce6fd 183 pChannel->DMACCConfig
AjK 8:cb4d323ce6fd 184 = CxConfig_IE()
AjK 8:cb4d323ce6fd 185 | CxConfig_ITC()
AjK 12:1dfee7208043 186 | CxConfig_TransferType(tfer_type)
AjK 8:cb4d323ce6fd 187 | CxConfig_SrcPeripheral(tmp1)
AjK 8:cb4d323ce6fd 188 | CxConfig_DestPeripheral(tmp2);
AjK 8:cb4d323ce6fd 189
AjK 8:cb4d323ce6fd 190 return pChannel->DMACCControl;
AjK 8:cb4d323ce6fd 191 }
AjK 8:cb4d323ce6fd 192
AjK 8:cb4d323ce6fd 193 }; // namespace AjK ends
AjK 8:cb4d323ce6fd 194