Mikis Wöhrmann
Just a test...
system_stm32f4xx.c@0:6b1a8c783fef, 2018-07-23 (annotated)
- Committer:
- Airdevelopments
- Date:
- Mon Jul 23 23:09:43 2018 +0000
- Revision:
- 0:6b1a8c783fef
Just a test, no real use...
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Airdevelopments | 0:6b1a8c783fef | 1 | /** |
| Airdevelopments | 0:6b1a8c783fef | 2 | ****************************************************************************** |
| Airdevelopments | 0:6b1a8c783fef | 3 | * @file system_stm32f4xx.c |
| Airdevelopments | 0:6b1a8c783fef | 4 | * @author MCD Application Team |
| Airdevelopments | 0:6b1a8c783fef | 5 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. |
| Airdevelopments | 0:6b1a8c783fef | 6 | * |
| Airdevelopments | 0:6b1a8c783fef | 7 | * This file provides two functions and one global variable to be called from |
| Airdevelopments | 0:6b1a8c783fef | 8 | * user application: |
| Airdevelopments | 0:6b1a8c783fef | 9 | * - SystemInit(): This function is called at startup just after reset and |
| Airdevelopments | 0:6b1a8c783fef | 10 | * before branch to main program. This call is made inside |
| Airdevelopments | 0:6b1a8c783fef | 11 | * the "startup_stm32f4xx.s" file. |
| Airdevelopments | 0:6b1a8c783fef | 12 | * |
| Airdevelopments | 0:6b1a8c783fef | 13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
| Airdevelopments | 0:6b1a8c783fef | 14 | * by the user application to setup the SysTick |
| Airdevelopments | 0:6b1a8c783fef | 15 | * timer or configure other parameters. |
| Airdevelopments | 0:6b1a8c783fef | 16 | * |
| Airdevelopments | 0:6b1a8c783fef | 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
| Airdevelopments | 0:6b1a8c783fef | 18 | * be called whenever the core clock is changed |
| Airdevelopments | 0:6b1a8c783fef | 19 | * during program execution. |
| Airdevelopments | 0:6b1a8c783fef | 20 | * |
| Airdevelopments | 0:6b1a8c783fef | 21 | * |
| Airdevelopments | 0:6b1a8c783fef | 22 | ****************************************************************************** |
| Airdevelopments | 0:6b1a8c783fef | 23 | * @attention |
| Airdevelopments | 0:6b1a8c783fef | 24 | * |
| Airdevelopments | 0:6b1a8c783fef | 25 | * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> |
| Airdevelopments | 0:6b1a8c783fef | 26 | * |
| Airdevelopments | 0:6b1a8c783fef | 27 | * Redistribution and use in source and binary forms, with or without modification, |
| Airdevelopments | 0:6b1a8c783fef | 28 | * are permitted provided that the following conditions are met: |
| Airdevelopments | 0:6b1a8c783fef | 29 | * 1. Redistributions of source code must retain the above copyright notice, |
| Airdevelopments | 0:6b1a8c783fef | 30 | * this list of conditions and the following disclaimer. |
| Airdevelopments | 0:6b1a8c783fef | 31 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Airdevelopments | 0:6b1a8c783fef | 32 | * this list of conditions and the following disclaimer in the documentation |
| Airdevelopments | 0:6b1a8c783fef | 33 | * and/or other materials provided with the distribution. |
| Airdevelopments | 0:6b1a8c783fef | 34 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| Airdevelopments | 0:6b1a8c783fef | 35 | * may be used to endorse or promote products derived from this software |
| Airdevelopments | 0:6b1a8c783fef | 36 | * without specific prior written permission. |
| Airdevelopments | 0:6b1a8c783fef | 37 | * |
| Airdevelopments | 0:6b1a8c783fef | 38 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| Airdevelopments | 0:6b1a8c783fef | 39 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| Airdevelopments | 0:6b1a8c783fef | 40 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Airdevelopments | 0:6b1a8c783fef | 41 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| Airdevelopments | 0:6b1a8c783fef | 42 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Airdevelopments | 0:6b1a8c783fef | 43 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| Airdevelopments | 0:6b1a8c783fef | 44 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| Airdevelopments | 0:6b1a8c783fef | 45 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| Airdevelopments | 0:6b1a8c783fef | 46 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| Airdevelopments | 0:6b1a8c783fef | 47 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Airdevelopments | 0:6b1a8c783fef | 48 | * |
| Airdevelopments | 0:6b1a8c783fef | 49 | ****************************************************************************** |
| Airdevelopments | 0:6b1a8c783fef | 50 | */ |
| Airdevelopments | 0:6b1a8c783fef | 51 | |
| Airdevelopments | 0:6b1a8c783fef | 52 | /** @addtogroup CMSIS |
| Airdevelopments | 0:6b1a8c783fef | 53 | * @{ |
| Airdevelopments | 0:6b1a8c783fef | 54 | */ |
| Airdevelopments | 0:6b1a8c783fef | 55 | |
| Airdevelopments | 0:6b1a8c783fef | 56 | /** @addtogroup stm32f4xx_system |
| Airdevelopments | 0:6b1a8c783fef | 57 | * @{ |
| Airdevelopments | 0:6b1a8c783fef | 58 | */ |
| Airdevelopments | 0:6b1a8c783fef | 59 | |
| Airdevelopments | 0:6b1a8c783fef | 60 | /** @addtogroup STM32F4xx_System_Private_Includes |
| Airdevelopments | 0:6b1a8c783fef | 61 | * @{ |
| Airdevelopments | 0:6b1a8c783fef | 62 | */ |
| Airdevelopments | 0:6b1a8c783fef | 63 | |
| Airdevelopments | 0:6b1a8c783fef | 64 | |
| Airdevelopments | 0:6b1a8c783fef | 65 | #include "stm32f4xx.h" |
| Airdevelopments | 0:6b1a8c783fef | 66 | |
| Airdevelopments | 0:6b1a8c783fef | 67 | #if !defined (HSE_VALUE) |
| Airdevelopments | 0:6b1a8c783fef | 68 | #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ |
| Airdevelopments | 0:6b1a8c783fef | 69 | #endif /* HSE_VALUE */ |
| Airdevelopments | 0:6b1a8c783fef | 70 | |
| Airdevelopments | 0:6b1a8c783fef | 71 | #if !defined (HSI_VALUE) |
| Airdevelopments | 0:6b1a8c783fef | 72 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ |
| Airdevelopments | 0:6b1a8c783fef | 73 | #endif /* HSI_VALUE */ |
| Airdevelopments | 0:6b1a8c783fef | 74 | |
| Airdevelopments | 0:6b1a8c783fef | 75 | /** |
| Airdevelopments | 0:6b1a8c783fef | 76 | * @} |
| Airdevelopments | 0:6b1a8c783fef | 77 | */ |
| Airdevelopments | 0:6b1a8c783fef | 78 | |
| Airdevelopments | 0:6b1a8c783fef | 79 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions |
| Airdevelopments | 0:6b1a8c783fef | 80 | * @{ |
| Airdevelopments | 0:6b1a8c783fef | 81 | */ |
| Airdevelopments | 0:6b1a8c783fef | 82 | |
| Airdevelopments | 0:6b1a8c783fef | 83 | /** |
| Airdevelopments | 0:6b1a8c783fef | 84 | * @} |
| Airdevelopments | 0:6b1a8c783fef | 85 | */ |
| Airdevelopments | 0:6b1a8c783fef | 86 | |
| Airdevelopments | 0:6b1a8c783fef | 87 | /** @addtogroup STM32F4xx_System_Private_Defines |
| Airdevelopments | 0:6b1a8c783fef | 88 | * @{ |
| Airdevelopments | 0:6b1a8c783fef | 89 | */ |
| Airdevelopments | 0:6b1a8c783fef | 90 | |
| Airdevelopments | 0:6b1a8c783fef | 91 | /************************* Miscellaneous Configuration ************************/ |
| Airdevelopments | 0:6b1a8c783fef | 92 | /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ |
| Airdevelopments | 0:6b1a8c783fef | 93 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ |
| Airdevelopments | 0:6b1a8c783fef | 94 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| Airdevelopments | 0:6b1a8c783fef | 95 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) |
| Airdevelopments | 0:6b1a8c783fef | 96 | /* #define DATA_IN_ExtSRAM */ |
| Airdevelopments | 0:6b1a8c783fef | 97 | #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ |
| Airdevelopments | 0:6b1a8c783fef | 98 | STM32F412Zx || STM32F412Vx */ |
| Airdevelopments | 0:6b1a8c783fef | 99 | |
| Airdevelopments | 0:6b1a8c783fef | 100 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| Airdevelopments | 0:6b1a8c783fef | 101 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| Airdevelopments | 0:6b1a8c783fef | 102 | /* #define DATA_IN_ExtSDRAM */ |
| Airdevelopments | 0:6b1a8c783fef | 103 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ |
| Airdevelopments | 0:6b1a8c783fef | 104 | STM32F479xx */ |
| Airdevelopments | 0:6b1a8c783fef | 105 | |
| Airdevelopments | 0:6b1a8c783fef | 106 | /*!< Uncomment the following line if you need to relocate your vector Table in |
| Airdevelopments | 0:6b1a8c783fef | 107 | Internal SRAM. */ |
| Airdevelopments | 0:6b1a8c783fef | 108 | /* #define VECT_TAB_SRAM */ |
| Airdevelopments | 0:6b1a8c783fef | 109 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
| Airdevelopments | 0:6b1a8c783fef | 110 | This value must be a multiple of 0x200. */ |
| Airdevelopments | 0:6b1a8c783fef | 111 | /******************************************************************************/ |
| Airdevelopments | 0:6b1a8c783fef | 112 | |
| Airdevelopments | 0:6b1a8c783fef | 113 | /** |
| Airdevelopments | 0:6b1a8c783fef | 114 | * @} |
| Airdevelopments | 0:6b1a8c783fef | 115 | */ |
| Airdevelopments | 0:6b1a8c783fef | 116 | |
| Airdevelopments | 0:6b1a8c783fef | 117 | /** @addtogroup STM32F4xx_System_Private_Macros |
| Airdevelopments | 0:6b1a8c783fef | 118 | * @{ |
| Airdevelopments | 0:6b1a8c783fef | 119 | */ |
| Airdevelopments | 0:6b1a8c783fef | 120 | |
| Airdevelopments | 0:6b1a8c783fef | 121 | /** |
| Airdevelopments | 0:6b1a8c783fef | 122 | * @} |
| Airdevelopments | 0:6b1a8c783fef | 123 | */ |
| Airdevelopments | 0:6b1a8c783fef | 124 | |
| Airdevelopments | 0:6b1a8c783fef | 125 | /** @addtogroup STM32F4xx_System_Private_Variables |
| Airdevelopments | 0:6b1a8c783fef | 126 | * @{ |
| Airdevelopments | 0:6b1a8c783fef | 127 | */ |
| Airdevelopments | 0:6b1a8c783fef | 128 | /* This variable is updated in three ways: |
| Airdevelopments | 0:6b1a8c783fef | 129 | 1) by calling CMSIS function SystemCoreClockUpdate() |
| Airdevelopments | 0:6b1a8c783fef | 130 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
| Airdevelopments | 0:6b1a8c783fef | 131 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
| Airdevelopments | 0:6b1a8c783fef | 132 | Note: If you use this function to configure the system clock; then there |
| Airdevelopments | 0:6b1a8c783fef | 133 | is no need to call the 2 first functions listed above, since SystemCoreClock |
| Airdevelopments | 0:6b1a8c783fef | 134 | variable is updated automatically. |
| Airdevelopments | 0:6b1a8c783fef | 135 | */ |
| Airdevelopments | 0:6b1a8c783fef | 136 | uint32_t SystemCoreClock = 16000000; |
| Airdevelopments | 0:6b1a8c783fef | 137 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
| Airdevelopments | 0:6b1a8c783fef | 138 | const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; |
| Airdevelopments | 0:6b1a8c783fef | 139 | /** |
| Airdevelopments | 0:6b1a8c783fef | 140 | * @} |
| Airdevelopments | 0:6b1a8c783fef | 141 | */ |
| Airdevelopments | 0:6b1a8c783fef | 142 | |
| Airdevelopments | 0:6b1a8c783fef | 143 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes |
| Airdevelopments | 0:6b1a8c783fef | 144 | * @{ |
| Airdevelopments | 0:6b1a8c783fef | 145 | */ |
| Airdevelopments | 0:6b1a8c783fef | 146 | |
| Airdevelopments | 0:6b1a8c783fef | 147 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| Airdevelopments | 0:6b1a8c783fef | 148 | static void SystemInit_ExtMemCtl(void); |
| Airdevelopments | 0:6b1a8c783fef | 149 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| Airdevelopments | 0:6b1a8c783fef | 150 | |
| Airdevelopments | 0:6b1a8c783fef | 151 | /** |
| Airdevelopments | 0:6b1a8c783fef | 152 | * @} |
| Airdevelopments | 0:6b1a8c783fef | 153 | */ |
| Airdevelopments | 0:6b1a8c783fef | 154 | |
| Airdevelopments | 0:6b1a8c783fef | 155 | /** @addtogroup STM32F4xx_System_Private_Functions |
| Airdevelopments | 0:6b1a8c783fef | 156 | * @{ |
| Airdevelopments | 0:6b1a8c783fef | 157 | */ |
| Airdevelopments | 0:6b1a8c783fef | 158 | |
| Airdevelopments | 0:6b1a8c783fef | 159 | /** |
| Airdevelopments | 0:6b1a8c783fef | 160 | * @brief Setup the microcontroller system |
| Airdevelopments | 0:6b1a8c783fef | 161 | * Initialize the FPU setting, vector table location and External memory |
| Airdevelopments | 0:6b1a8c783fef | 162 | * configuration. |
| Airdevelopments | 0:6b1a8c783fef | 163 | * @param None |
| Airdevelopments | 0:6b1a8c783fef | 164 | * @retval None |
| Airdevelopments | 0:6b1a8c783fef | 165 | */ |
| Airdevelopments | 0:6b1a8c783fef | 166 | void SystemInit(void) |
| Airdevelopments | 0:6b1a8c783fef | 167 | { |
| Airdevelopments | 0:6b1a8c783fef | 168 | /* FPU settings ------------------------------------------------------------*/ |
| Airdevelopments | 0:6b1a8c783fef | 169 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
| Airdevelopments | 0:6b1a8c783fef | 170 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
| Airdevelopments | 0:6b1a8c783fef | 171 | #endif |
| Airdevelopments | 0:6b1a8c783fef | 172 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
| Airdevelopments | 0:6b1a8c783fef | 173 | /* Set HSION bit */ |
| Airdevelopments | 0:6b1a8c783fef | 174 | RCC->CR |= (uint32_t)0x00000001; |
| Airdevelopments | 0:6b1a8c783fef | 175 | |
| Airdevelopments | 0:6b1a8c783fef | 176 | /* Reset CFGR register */ |
| Airdevelopments | 0:6b1a8c783fef | 177 | RCC->CFGR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 178 | |
| Airdevelopments | 0:6b1a8c783fef | 179 | /* Reset HSEON, CSSON and PLLON bits */ |
| Airdevelopments | 0:6b1a8c783fef | 180 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
| Airdevelopments | 0:6b1a8c783fef | 181 | |
| Airdevelopments | 0:6b1a8c783fef | 182 | /* Reset PLLCFGR register */ |
| Airdevelopments | 0:6b1a8c783fef | 183 | RCC->PLLCFGR = 0x24003010; |
| Airdevelopments | 0:6b1a8c783fef | 184 | |
| Airdevelopments | 0:6b1a8c783fef | 185 | /* Reset HSEBYP bit */ |
| Airdevelopments | 0:6b1a8c783fef | 186 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
| Airdevelopments | 0:6b1a8c783fef | 187 | |
| Airdevelopments | 0:6b1a8c783fef | 188 | /* Disable all interrupts */ |
| Airdevelopments | 0:6b1a8c783fef | 189 | RCC->CIR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 190 | |
| Airdevelopments | 0:6b1a8c783fef | 191 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| Airdevelopments | 0:6b1a8c783fef | 192 | SystemInit_ExtMemCtl(); |
| Airdevelopments | 0:6b1a8c783fef | 193 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| Airdevelopments | 0:6b1a8c783fef | 194 | |
| Airdevelopments | 0:6b1a8c783fef | 195 | /* Configure the Vector Table location add offset address ------------------*/ |
| Airdevelopments | 0:6b1a8c783fef | 196 | #ifdef VECT_TAB_SRAM |
| Airdevelopments | 0:6b1a8c783fef | 197 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
| Airdevelopments | 0:6b1a8c783fef | 198 | #else |
| Airdevelopments | 0:6b1a8c783fef | 199 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
| Airdevelopments | 0:6b1a8c783fef | 200 | #endif |
| Airdevelopments | 0:6b1a8c783fef | 201 | } |
| Airdevelopments | 0:6b1a8c783fef | 202 | |
| Airdevelopments | 0:6b1a8c783fef | 203 | /** |
| Airdevelopments | 0:6b1a8c783fef | 204 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
| Airdevelopments | 0:6b1a8c783fef | 205 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
| Airdevelopments | 0:6b1a8c783fef | 206 | * be used by the user application to setup the SysTick timer or configure |
| Airdevelopments | 0:6b1a8c783fef | 207 | * other parameters. |
| Airdevelopments | 0:6b1a8c783fef | 208 | * |
| Airdevelopments | 0:6b1a8c783fef | 209 | * @note Each time the core clock (HCLK) changes, this function must be called |
| Airdevelopments | 0:6b1a8c783fef | 210 | * to update SystemCoreClock variable value. Otherwise, any configuration |
| Airdevelopments | 0:6b1a8c783fef | 211 | * based on this variable will be incorrect. |
| Airdevelopments | 0:6b1a8c783fef | 212 | * |
| Airdevelopments | 0:6b1a8c783fef | 213 | * @note - The system frequency computed by this function is not the real |
| Airdevelopments | 0:6b1a8c783fef | 214 | * frequency in the chip. It is calculated based on the predefined |
| Airdevelopments | 0:6b1a8c783fef | 215 | * constant and the selected clock source: |
| Airdevelopments | 0:6b1a8c783fef | 216 | * |
| Airdevelopments | 0:6b1a8c783fef | 217 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
| Airdevelopments | 0:6b1a8c783fef | 218 | * |
| Airdevelopments | 0:6b1a8c783fef | 219 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
| Airdevelopments | 0:6b1a8c783fef | 220 | * |
| Airdevelopments | 0:6b1a8c783fef | 221 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
| Airdevelopments | 0:6b1a8c783fef | 222 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
| Airdevelopments | 0:6b1a8c783fef | 223 | * |
| Airdevelopments | 0:6b1a8c783fef | 224 | * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value |
| Airdevelopments | 0:6b1a8c783fef | 225 | * 16 MHz) but the real value may vary depending on the variations |
| Airdevelopments | 0:6b1a8c783fef | 226 | * in voltage and temperature. |
| Airdevelopments | 0:6b1a8c783fef | 227 | * |
| Airdevelopments | 0:6b1a8c783fef | 228 | * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value |
| Airdevelopments | 0:6b1a8c783fef | 229 | * depends on the application requirements), user has to ensure that HSE_VALUE |
| Airdevelopments | 0:6b1a8c783fef | 230 | * is same as the real frequency of the crystal used. Otherwise, this function |
| Airdevelopments | 0:6b1a8c783fef | 231 | * may have wrong result. |
| Airdevelopments | 0:6b1a8c783fef | 232 | * |
| Airdevelopments | 0:6b1a8c783fef | 233 | * - The result of this function could be not correct when using fractional |
| Airdevelopments | 0:6b1a8c783fef | 234 | * value for HSE crystal. |
| Airdevelopments | 0:6b1a8c783fef | 235 | * |
| Airdevelopments | 0:6b1a8c783fef | 236 | * @param None |
| Airdevelopments | 0:6b1a8c783fef | 237 | * @retval None |
| Airdevelopments | 0:6b1a8c783fef | 238 | */ |
| Airdevelopments | 0:6b1a8c783fef | 239 | void SystemCoreClockUpdate(void) |
| Airdevelopments | 0:6b1a8c783fef | 240 | { |
| Airdevelopments | 0:6b1a8c783fef | 241 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; |
| Airdevelopments | 0:6b1a8c783fef | 242 | |
| Airdevelopments | 0:6b1a8c783fef | 243 | /* Get SYSCLK source -------------------------------------------------------*/ |
| Airdevelopments | 0:6b1a8c783fef | 244 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
| Airdevelopments | 0:6b1a8c783fef | 245 | |
| Airdevelopments | 0:6b1a8c783fef | 246 | switch (tmp) |
| Airdevelopments | 0:6b1a8c783fef | 247 | { |
| Airdevelopments | 0:6b1a8c783fef | 248 | case 0x00: /* HSI used as system clock source */ |
| Airdevelopments | 0:6b1a8c783fef | 249 | SystemCoreClock = HSI_VALUE; |
| Airdevelopments | 0:6b1a8c783fef | 250 | break; |
| Airdevelopments | 0:6b1a8c783fef | 251 | case 0x04: /* HSE used as system clock source */ |
| Airdevelopments | 0:6b1a8c783fef | 252 | SystemCoreClock = HSE_VALUE; |
| Airdevelopments | 0:6b1a8c783fef | 253 | break; |
| Airdevelopments | 0:6b1a8c783fef | 254 | case 0x08: /* PLL used as system clock source */ |
| Airdevelopments | 0:6b1a8c783fef | 255 | |
| Airdevelopments | 0:6b1a8c783fef | 256 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N |
| Airdevelopments | 0:6b1a8c783fef | 257 | SYSCLK = PLL_VCO / PLL_P |
| Airdevelopments | 0:6b1a8c783fef | 258 | */ |
| Airdevelopments | 0:6b1a8c783fef | 259 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; |
| Airdevelopments | 0:6b1a8c783fef | 260 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; |
| Airdevelopments | 0:6b1a8c783fef | 261 | |
| Airdevelopments | 0:6b1a8c783fef | 262 | if (pllsource != 0) |
| Airdevelopments | 0:6b1a8c783fef | 263 | { |
| Airdevelopments | 0:6b1a8c783fef | 264 | /* HSE used as PLL clock source */ |
| Airdevelopments | 0:6b1a8c783fef | 265 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| Airdevelopments | 0:6b1a8c783fef | 266 | } |
| Airdevelopments | 0:6b1a8c783fef | 267 | else |
| Airdevelopments | 0:6b1a8c783fef | 268 | { |
| Airdevelopments | 0:6b1a8c783fef | 269 | /* HSI used as PLL clock source */ |
| Airdevelopments | 0:6b1a8c783fef | 270 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| Airdevelopments | 0:6b1a8c783fef | 271 | } |
| Airdevelopments | 0:6b1a8c783fef | 272 | |
| Airdevelopments | 0:6b1a8c783fef | 273 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; |
| Airdevelopments | 0:6b1a8c783fef | 274 | SystemCoreClock = pllvco/pllp; |
| Airdevelopments | 0:6b1a8c783fef | 275 | break; |
| Airdevelopments | 0:6b1a8c783fef | 276 | default: |
| Airdevelopments | 0:6b1a8c783fef | 277 | SystemCoreClock = HSI_VALUE; |
| Airdevelopments | 0:6b1a8c783fef | 278 | break; |
| Airdevelopments | 0:6b1a8c783fef | 279 | } |
| Airdevelopments | 0:6b1a8c783fef | 280 | /* Compute HCLK frequency --------------------------------------------------*/ |
| Airdevelopments | 0:6b1a8c783fef | 281 | /* Get HCLK prescaler */ |
| Airdevelopments | 0:6b1a8c783fef | 282 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
| Airdevelopments | 0:6b1a8c783fef | 283 | /* HCLK frequency */ |
| Airdevelopments | 0:6b1a8c783fef | 284 | SystemCoreClock >>= tmp; |
| Airdevelopments | 0:6b1a8c783fef | 285 | } |
| Airdevelopments | 0:6b1a8c783fef | 286 | |
| Airdevelopments | 0:6b1a8c783fef | 287 | #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) |
| Airdevelopments | 0:6b1a8c783fef | 288 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| Airdevelopments | 0:6b1a8c783fef | 289 | || defined(STM32F469xx) || defined(STM32F479xx) |
| Airdevelopments | 0:6b1a8c783fef | 290 | /** |
| Airdevelopments | 0:6b1a8c783fef | 291 | * @brief Setup the external memory controller. |
| Airdevelopments | 0:6b1a8c783fef | 292 | * Called in startup_stm32f4xx.s before jump to main. |
| Airdevelopments | 0:6b1a8c783fef | 293 | * This function configures the external memories (SRAM/SDRAM) |
| Airdevelopments | 0:6b1a8c783fef | 294 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). |
| Airdevelopments | 0:6b1a8c783fef | 295 | * @param None |
| Airdevelopments | 0:6b1a8c783fef | 296 | * @retval None |
| Airdevelopments | 0:6b1a8c783fef | 297 | */ |
| Airdevelopments | 0:6b1a8c783fef | 298 | void SystemInit_ExtMemCtl(void) |
| Airdevelopments | 0:6b1a8c783fef | 299 | { |
| Airdevelopments | 0:6b1a8c783fef | 300 | __IO uint32_t tmp = 0x00; |
| Airdevelopments | 0:6b1a8c783fef | 301 | |
| Airdevelopments | 0:6b1a8c783fef | 302 | register uint32_t tmpreg = 0, timeout = 0xFFFF; |
| Airdevelopments | 0:6b1a8c783fef | 303 | register __IO uint32_t index; |
| Airdevelopments | 0:6b1a8c783fef | 304 | |
| Airdevelopments | 0:6b1a8c783fef | 305 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ |
| Airdevelopments | 0:6b1a8c783fef | 306 | RCC->AHB1ENR |= 0x000001F8; |
| Airdevelopments | 0:6b1a8c783fef | 307 | |
| Airdevelopments | 0:6b1a8c783fef | 308 | /* Delay after an RCC peripheral clock enabling */ |
| Airdevelopments | 0:6b1a8c783fef | 309 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); |
| Airdevelopments | 0:6b1a8c783fef | 310 | |
| Airdevelopments | 0:6b1a8c783fef | 311 | /* Connect PDx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 312 | GPIOD->AFR[0] = 0x00CCC0CC; |
| Airdevelopments | 0:6b1a8c783fef | 313 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 314 | /* Configure PDx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 315 | GPIOD->MODER = 0xAAAA0A8A; |
| Airdevelopments | 0:6b1a8c783fef | 316 | /* Configure PDx pins speed to 100 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 317 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
| Airdevelopments | 0:6b1a8c783fef | 318 | /* Configure PDx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 319 | GPIOD->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 320 | /* No pull-up, pull-down for PDx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 321 | GPIOD->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 322 | |
| Airdevelopments | 0:6b1a8c783fef | 323 | /* Connect PEx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 324 | GPIOE->AFR[0] = 0xC00CC0CC; |
| Airdevelopments | 0:6b1a8c783fef | 325 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 326 | /* Configure PEx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 327 | GPIOE->MODER = 0xAAAA828A; |
| Airdevelopments | 0:6b1a8c783fef | 328 | /* Configure PEx pins speed to 100 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 329 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
| Airdevelopments | 0:6b1a8c783fef | 330 | /* Configure PEx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 331 | GPIOE->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 332 | /* No pull-up, pull-down for PEx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 333 | GPIOE->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 334 | |
| Airdevelopments | 0:6b1a8c783fef | 335 | /* Connect PFx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 336 | GPIOF->AFR[0] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 337 | GPIOF->AFR[1] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 338 | /* Configure PFx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 339 | GPIOF->MODER = 0xAA800AAA; |
| Airdevelopments | 0:6b1a8c783fef | 340 | /* Configure PFx pins speed to 50 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 341 | GPIOF->OSPEEDR = 0xAA800AAA; |
| Airdevelopments | 0:6b1a8c783fef | 342 | /* Configure PFx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 343 | GPIOF->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 344 | /* No pull-up, pull-down for PFx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 345 | GPIOF->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 346 | |
| Airdevelopments | 0:6b1a8c783fef | 347 | /* Connect PGx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 348 | GPIOG->AFR[0] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 349 | GPIOG->AFR[1] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 350 | /* Configure PGx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 351 | GPIOG->MODER = 0xAAAAAAAA; |
| Airdevelopments | 0:6b1a8c783fef | 352 | /* Configure PGx pins speed to 50 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 353 | GPIOG->OSPEEDR = 0xAAAAAAAA; |
| Airdevelopments | 0:6b1a8c783fef | 354 | /* Configure PGx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 355 | GPIOG->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 356 | /* No pull-up, pull-down for PGx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 357 | GPIOG->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 358 | |
| Airdevelopments | 0:6b1a8c783fef | 359 | /* Connect PHx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 360 | GPIOH->AFR[0] = 0x00C0CC00; |
| Airdevelopments | 0:6b1a8c783fef | 361 | GPIOH->AFR[1] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 362 | /* Configure PHx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 363 | GPIOH->MODER = 0xAAAA08A0; |
| Airdevelopments | 0:6b1a8c783fef | 364 | /* Configure PHx pins speed to 50 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 365 | GPIOH->OSPEEDR = 0xAAAA08A0; |
| Airdevelopments | 0:6b1a8c783fef | 366 | /* Configure PHx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 367 | GPIOH->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 368 | /* No pull-up, pull-down for PHx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 369 | GPIOH->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 370 | |
| Airdevelopments | 0:6b1a8c783fef | 371 | /* Connect PIx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 372 | GPIOI->AFR[0] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 373 | GPIOI->AFR[1] = 0x00000CC0; |
| Airdevelopments | 0:6b1a8c783fef | 374 | /* Configure PIx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 375 | GPIOI->MODER = 0x0028AAAA; |
| Airdevelopments | 0:6b1a8c783fef | 376 | /* Configure PIx pins speed to 50 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 377 | GPIOI->OSPEEDR = 0x0028AAAA; |
| Airdevelopments | 0:6b1a8c783fef | 378 | /* Configure PIx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 379 | GPIOI->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 380 | /* No pull-up, pull-down for PIx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 381 | GPIOI->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 382 | |
| Airdevelopments | 0:6b1a8c783fef | 383 | /*-- FMC Configuration -------------------------------------------------------*/ |
| Airdevelopments | 0:6b1a8c783fef | 384 | /* Enable the FMC interface clock */ |
| Airdevelopments | 0:6b1a8c783fef | 385 | RCC->AHB3ENR |= 0x00000001; |
| Airdevelopments | 0:6b1a8c783fef | 386 | /* Delay after an RCC peripheral clock enabling */ |
| Airdevelopments | 0:6b1a8c783fef | 387 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| Airdevelopments | 0:6b1a8c783fef | 388 | |
| Airdevelopments | 0:6b1a8c783fef | 389 | FMC_Bank5_6->SDCR[0] = 0x000019E4; |
| Airdevelopments | 0:6b1a8c783fef | 390 | FMC_Bank5_6->SDTR[0] = 0x01115351; |
| Airdevelopments | 0:6b1a8c783fef | 391 | |
| Airdevelopments | 0:6b1a8c783fef | 392 | /* SDRAM initialization sequence */ |
| Airdevelopments | 0:6b1a8c783fef | 393 | /* Clock enable command */ |
| Airdevelopments | 0:6b1a8c783fef | 394 | FMC_Bank5_6->SDCMR = 0x00000011; |
| Airdevelopments | 0:6b1a8c783fef | 395 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Airdevelopments | 0:6b1a8c783fef | 396 | while((tmpreg != 0) && (timeout-- > 0)) |
| Airdevelopments | 0:6b1a8c783fef | 397 | { |
| Airdevelopments | 0:6b1a8c783fef | 398 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Airdevelopments | 0:6b1a8c783fef | 399 | } |
| Airdevelopments | 0:6b1a8c783fef | 400 | |
| Airdevelopments | 0:6b1a8c783fef | 401 | /* Delay */ |
| Airdevelopments | 0:6b1a8c783fef | 402 | for (index = 0; index<1000; index++); |
| Airdevelopments | 0:6b1a8c783fef | 403 | |
| Airdevelopments | 0:6b1a8c783fef | 404 | /* PALL command */ |
| Airdevelopments | 0:6b1a8c783fef | 405 | FMC_Bank5_6->SDCMR = 0x00000012; |
| Airdevelopments | 0:6b1a8c783fef | 406 | timeout = 0xFFFF; |
| Airdevelopments | 0:6b1a8c783fef | 407 | while((tmpreg != 0) && (timeout-- > 0)) |
| Airdevelopments | 0:6b1a8c783fef | 408 | { |
| Airdevelopments | 0:6b1a8c783fef | 409 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Airdevelopments | 0:6b1a8c783fef | 410 | } |
| Airdevelopments | 0:6b1a8c783fef | 411 | |
| Airdevelopments | 0:6b1a8c783fef | 412 | /* Auto refresh command */ |
| Airdevelopments | 0:6b1a8c783fef | 413 | FMC_Bank5_6->SDCMR = 0x00000073; |
| Airdevelopments | 0:6b1a8c783fef | 414 | timeout = 0xFFFF; |
| Airdevelopments | 0:6b1a8c783fef | 415 | while((tmpreg != 0) && (timeout-- > 0)) |
| Airdevelopments | 0:6b1a8c783fef | 416 | { |
| Airdevelopments | 0:6b1a8c783fef | 417 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Airdevelopments | 0:6b1a8c783fef | 418 | } |
| Airdevelopments | 0:6b1a8c783fef | 419 | |
| Airdevelopments | 0:6b1a8c783fef | 420 | /* MRD register program */ |
| Airdevelopments | 0:6b1a8c783fef | 421 | FMC_Bank5_6->SDCMR = 0x00046014; |
| Airdevelopments | 0:6b1a8c783fef | 422 | timeout = 0xFFFF; |
| Airdevelopments | 0:6b1a8c783fef | 423 | while((tmpreg != 0) && (timeout-- > 0)) |
| Airdevelopments | 0:6b1a8c783fef | 424 | { |
| Airdevelopments | 0:6b1a8c783fef | 425 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Airdevelopments | 0:6b1a8c783fef | 426 | } |
| Airdevelopments | 0:6b1a8c783fef | 427 | |
| Airdevelopments | 0:6b1a8c783fef | 428 | /* Set refresh count */ |
| Airdevelopments | 0:6b1a8c783fef | 429 | tmpreg = FMC_Bank5_6->SDRTR; |
| Airdevelopments | 0:6b1a8c783fef | 430 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); |
| Airdevelopments | 0:6b1a8c783fef | 431 | |
| Airdevelopments | 0:6b1a8c783fef | 432 | /* Disable write protection */ |
| Airdevelopments | 0:6b1a8c783fef | 433 | tmpreg = FMC_Bank5_6->SDCR[0]; |
| Airdevelopments | 0:6b1a8c783fef | 434 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
| Airdevelopments | 0:6b1a8c783fef | 435 | |
| Airdevelopments | 0:6b1a8c783fef | 436 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| Airdevelopments | 0:6b1a8c783fef | 437 | /* Configure and enable Bank1_SRAM2 */ |
| Airdevelopments | 0:6b1a8c783fef | 438 | FMC_Bank1->BTCR[2] = 0x00001011; |
| Airdevelopments | 0:6b1a8c783fef | 439 | FMC_Bank1->BTCR[3] = 0x00000201; |
| Airdevelopments | 0:6b1a8c783fef | 440 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| Airdevelopments | 0:6b1a8c783fef | 441 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| Airdevelopments | 0:6b1a8c783fef | 442 | #if defined(STM32F469xx) || defined(STM32F479xx) |
| Airdevelopments | 0:6b1a8c783fef | 443 | /* Configure and enable Bank1_SRAM2 */ |
| Airdevelopments | 0:6b1a8c783fef | 444 | FMC_Bank1->BTCR[2] = 0x00001091; |
| Airdevelopments | 0:6b1a8c783fef | 445 | FMC_Bank1->BTCR[3] = 0x00110212; |
| Airdevelopments | 0:6b1a8c783fef | 446 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| Airdevelopments | 0:6b1a8c783fef | 447 | #endif /* STM32F469xx || STM32F479xx */ |
| Airdevelopments | 0:6b1a8c783fef | 448 | |
| Airdevelopments | 0:6b1a8c783fef | 449 | (void)(tmp); |
| Airdevelopments | 0:6b1a8c783fef | 450 | } |
| Airdevelopments | 0:6b1a8c783fef | 451 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| Airdevelopments | 0:6b1a8c783fef | 452 | #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| Airdevelopments | 0:6b1a8c783fef | 453 | /** |
| Airdevelopments | 0:6b1a8c783fef | 454 | * @brief Setup the external memory controller. |
| Airdevelopments | 0:6b1a8c783fef | 455 | * Called in startup_stm32f4xx.s before jump to main. |
| Airdevelopments | 0:6b1a8c783fef | 456 | * This function configures the external memories (SRAM/SDRAM) |
| Airdevelopments | 0:6b1a8c783fef | 457 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). |
| Airdevelopments | 0:6b1a8c783fef | 458 | * @param None |
| Airdevelopments | 0:6b1a8c783fef | 459 | * @retval None |
| Airdevelopments | 0:6b1a8c783fef | 460 | */ |
| Airdevelopments | 0:6b1a8c783fef | 461 | void SystemInit_ExtMemCtl(void) |
| Airdevelopments | 0:6b1a8c783fef | 462 | { |
| Airdevelopments | 0:6b1a8c783fef | 463 | __IO uint32_t tmp = 0x00; |
| Airdevelopments | 0:6b1a8c783fef | 464 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| Airdevelopments | 0:6b1a8c783fef | 465 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| Airdevelopments | 0:6b1a8c783fef | 466 | #if defined (DATA_IN_ExtSDRAM) |
| Airdevelopments | 0:6b1a8c783fef | 467 | register uint32_t tmpreg = 0, timeout = 0xFFFF; |
| Airdevelopments | 0:6b1a8c783fef | 468 | register __IO uint32_t index; |
| Airdevelopments | 0:6b1a8c783fef | 469 | |
| Airdevelopments | 0:6b1a8c783fef | 470 | #if defined(STM32F446xx) |
| Airdevelopments | 0:6b1a8c783fef | 471 | /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface |
| Airdevelopments | 0:6b1a8c783fef | 472 | clock */ |
| Airdevelopments | 0:6b1a8c783fef | 473 | RCC->AHB1ENR |= 0x0000007D; |
| Airdevelopments | 0:6b1a8c783fef | 474 | #else |
| Airdevelopments | 0:6b1a8c783fef | 475 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface |
| Airdevelopments | 0:6b1a8c783fef | 476 | clock */ |
| Airdevelopments | 0:6b1a8c783fef | 477 | RCC->AHB1ENR |= 0x000001F8; |
| Airdevelopments | 0:6b1a8c783fef | 478 | #endif /* STM32F446xx */ |
| Airdevelopments | 0:6b1a8c783fef | 479 | /* Delay after an RCC peripheral clock enabling */ |
| Airdevelopments | 0:6b1a8c783fef | 480 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); |
| Airdevelopments | 0:6b1a8c783fef | 481 | |
| Airdevelopments | 0:6b1a8c783fef | 482 | #if defined(STM32F446xx) |
| Airdevelopments | 0:6b1a8c783fef | 483 | /* Connect PAx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 484 | GPIOA->AFR[0] |= 0xC0000000; |
| Airdevelopments | 0:6b1a8c783fef | 485 | GPIOA->AFR[1] |= 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 486 | /* Configure PDx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 487 | GPIOA->MODER |= 0x00008000; |
| Airdevelopments | 0:6b1a8c783fef | 488 | /* Configure PDx pins speed to 50 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 489 | GPIOA->OSPEEDR |= 0x00008000; |
| Airdevelopments | 0:6b1a8c783fef | 490 | /* Configure PDx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 491 | GPIOA->OTYPER |= 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 492 | /* No pull-up, pull-down for PDx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 493 | GPIOA->PUPDR |= 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 494 | |
| Airdevelopments | 0:6b1a8c783fef | 495 | /* Connect PCx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 496 | GPIOC->AFR[0] |= 0x00CC0000; |
| Airdevelopments | 0:6b1a8c783fef | 497 | GPIOC->AFR[1] |= 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 498 | /* Configure PDx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 499 | GPIOC->MODER |= 0x00000A00; |
| Airdevelopments | 0:6b1a8c783fef | 500 | /* Configure PDx pins speed to 50 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 501 | GPIOC->OSPEEDR |= 0x00000A00; |
| Airdevelopments | 0:6b1a8c783fef | 502 | /* Configure PDx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 503 | GPIOC->OTYPER |= 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 504 | /* No pull-up, pull-down for PDx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 505 | GPIOC->PUPDR |= 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 506 | #endif /* STM32F446xx */ |
| Airdevelopments | 0:6b1a8c783fef | 507 | |
| Airdevelopments | 0:6b1a8c783fef | 508 | /* Connect PDx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 509 | GPIOD->AFR[0] = 0x000000CC; |
| Airdevelopments | 0:6b1a8c783fef | 510 | GPIOD->AFR[1] = 0xCC000CCC; |
| Airdevelopments | 0:6b1a8c783fef | 511 | /* Configure PDx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 512 | GPIOD->MODER = 0xA02A000A; |
| Airdevelopments | 0:6b1a8c783fef | 513 | /* Configure PDx pins speed to 50 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 514 | GPIOD->OSPEEDR = 0xA02A000A; |
| Airdevelopments | 0:6b1a8c783fef | 515 | /* Configure PDx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 516 | GPIOD->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 517 | /* No pull-up, pull-down for PDx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 518 | GPIOD->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 519 | |
| Airdevelopments | 0:6b1a8c783fef | 520 | /* Connect PEx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 521 | GPIOE->AFR[0] = 0xC00000CC; |
| Airdevelopments | 0:6b1a8c783fef | 522 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 523 | /* Configure PEx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 524 | GPIOE->MODER = 0xAAAA800A; |
| Airdevelopments | 0:6b1a8c783fef | 525 | /* Configure PEx pins speed to 50 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 526 | GPIOE->OSPEEDR = 0xAAAA800A; |
| Airdevelopments | 0:6b1a8c783fef | 527 | /* Configure PEx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 528 | GPIOE->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 529 | /* No pull-up, pull-down for PEx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 530 | GPIOE->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 531 | |
| Airdevelopments | 0:6b1a8c783fef | 532 | /* Connect PFx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 533 | GPIOF->AFR[0] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 534 | GPIOF->AFR[1] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 535 | /* Configure PFx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 536 | GPIOF->MODER = 0xAA800AAA; |
| Airdevelopments | 0:6b1a8c783fef | 537 | /* Configure PFx pins speed to 50 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 538 | GPIOF->OSPEEDR = 0xAA800AAA; |
| Airdevelopments | 0:6b1a8c783fef | 539 | /* Configure PFx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 540 | GPIOF->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 541 | /* No pull-up, pull-down for PFx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 542 | GPIOF->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 543 | |
| Airdevelopments | 0:6b1a8c783fef | 544 | /* Connect PGx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 545 | GPIOG->AFR[0] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 546 | GPIOG->AFR[1] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 547 | /* Configure PGx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 548 | GPIOG->MODER = 0xAAAAAAAA; |
| Airdevelopments | 0:6b1a8c783fef | 549 | /* Configure PGx pins speed to 50 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 550 | GPIOG->OSPEEDR = 0xAAAAAAAA; |
| Airdevelopments | 0:6b1a8c783fef | 551 | /* Configure PGx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 552 | GPIOG->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 553 | /* No pull-up, pull-down for PGx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 554 | GPIOG->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 555 | |
| Airdevelopments | 0:6b1a8c783fef | 556 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| Airdevelopments | 0:6b1a8c783fef | 557 | || defined(STM32F469xx) || defined(STM32F479xx) |
| Airdevelopments | 0:6b1a8c783fef | 558 | /* Connect PHx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 559 | GPIOH->AFR[0] = 0x00C0CC00; |
| Airdevelopments | 0:6b1a8c783fef | 560 | GPIOH->AFR[1] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 561 | /* Configure PHx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 562 | GPIOH->MODER = 0xAAAA08A0; |
| Airdevelopments | 0:6b1a8c783fef | 563 | /* Configure PHx pins speed to 50 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 564 | GPIOH->OSPEEDR = 0xAAAA08A0; |
| Airdevelopments | 0:6b1a8c783fef | 565 | /* Configure PHx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 566 | GPIOH->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 567 | /* No pull-up, pull-down for PHx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 568 | GPIOH->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 569 | |
| Airdevelopments | 0:6b1a8c783fef | 570 | /* Connect PIx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 571 | GPIOI->AFR[0] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 572 | GPIOI->AFR[1] = 0x00000CC0; |
| Airdevelopments | 0:6b1a8c783fef | 573 | /* Configure PIx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 574 | GPIOI->MODER = 0x0028AAAA; |
| Airdevelopments | 0:6b1a8c783fef | 575 | /* Configure PIx pins speed to 50 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 576 | GPIOI->OSPEEDR = 0x0028AAAA; |
| Airdevelopments | 0:6b1a8c783fef | 577 | /* Configure PIx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 578 | GPIOI->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 579 | /* No pull-up, pull-down for PIx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 580 | GPIOI->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 581 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| Airdevelopments | 0:6b1a8c783fef | 582 | |
| Airdevelopments | 0:6b1a8c783fef | 583 | /*-- FMC Configuration -------------------------------------------------------*/ |
| Airdevelopments | 0:6b1a8c783fef | 584 | /* Enable the FMC interface clock */ |
| Airdevelopments | 0:6b1a8c783fef | 585 | RCC->AHB3ENR |= 0x00000001; |
| Airdevelopments | 0:6b1a8c783fef | 586 | /* Delay after an RCC peripheral clock enabling */ |
| Airdevelopments | 0:6b1a8c783fef | 587 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| Airdevelopments | 0:6b1a8c783fef | 588 | |
| Airdevelopments | 0:6b1a8c783fef | 589 | /* Configure and enable SDRAM bank1 */ |
| Airdevelopments | 0:6b1a8c783fef | 590 | #if defined(STM32F446xx) |
| Airdevelopments | 0:6b1a8c783fef | 591 | FMC_Bank5_6->SDCR[0] = 0x00001954; |
| Airdevelopments | 0:6b1a8c783fef | 592 | #else |
| Airdevelopments | 0:6b1a8c783fef | 593 | FMC_Bank5_6->SDCR[0] = 0x000019E4; |
| Airdevelopments | 0:6b1a8c783fef | 594 | #endif /* STM32F446xx */ |
| Airdevelopments | 0:6b1a8c783fef | 595 | FMC_Bank5_6->SDTR[0] = 0x01115351; |
| Airdevelopments | 0:6b1a8c783fef | 596 | |
| Airdevelopments | 0:6b1a8c783fef | 597 | /* SDRAM initialization sequence */ |
| Airdevelopments | 0:6b1a8c783fef | 598 | /* Clock enable command */ |
| Airdevelopments | 0:6b1a8c783fef | 599 | FMC_Bank5_6->SDCMR = 0x00000011; |
| Airdevelopments | 0:6b1a8c783fef | 600 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Airdevelopments | 0:6b1a8c783fef | 601 | while((tmpreg != 0) && (timeout-- > 0)) |
| Airdevelopments | 0:6b1a8c783fef | 602 | { |
| Airdevelopments | 0:6b1a8c783fef | 603 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Airdevelopments | 0:6b1a8c783fef | 604 | } |
| Airdevelopments | 0:6b1a8c783fef | 605 | |
| Airdevelopments | 0:6b1a8c783fef | 606 | /* Delay */ |
| Airdevelopments | 0:6b1a8c783fef | 607 | for (index = 0; index<1000; index++); |
| Airdevelopments | 0:6b1a8c783fef | 608 | |
| Airdevelopments | 0:6b1a8c783fef | 609 | /* PALL command */ |
| Airdevelopments | 0:6b1a8c783fef | 610 | FMC_Bank5_6->SDCMR = 0x00000012; |
| Airdevelopments | 0:6b1a8c783fef | 611 | timeout = 0xFFFF; |
| Airdevelopments | 0:6b1a8c783fef | 612 | while((tmpreg != 0) && (timeout-- > 0)) |
| Airdevelopments | 0:6b1a8c783fef | 613 | { |
| Airdevelopments | 0:6b1a8c783fef | 614 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Airdevelopments | 0:6b1a8c783fef | 615 | } |
| Airdevelopments | 0:6b1a8c783fef | 616 | |
| Airdevelopments | 0:6b1a8c783fef | 617 | /* Auto refresh command */ |
| Airdevelopments | 0:6b1a8c783fef | 618 | #if defined(STM32F446xx) |
| Airdevelopments | 0:6b1a8c783fef | 619 | FMC_Bank5_6->SDCMR = 0x000000F3; |
| Airdevelopments | 0:6b1a8c783fef | 620 | #else |
| Airdevelopments | 0:6b1a8c783fef | 621 | FMC_Bank5_6->SDCMR = 0x00000073; |
| Airdevelopments | 0:6b1a8c783fef | 622 | #endif /* STM32F446xx */ |
| Airdevelopments | 0:6b1a8c783fef | 623 | timeout = 0xFFFF; |
| Airdevelopments | 0:6b1a8c783fef | 624 | while((tmpreg != 0) && (timeout-- > 0)) |
| Airdevelopments | 0:6b1a8c783fef | 625 | { |
| Airdevelopments | 0:6b1a8c783fef | 626 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Airdevelopments | 0:6b1a8c783fef | 627 | } |
| Airdevelopments | 0:6b1a8c783fef | 628 | |
| Airdevelopments | 0:6b1a8c783fef | 629 | /* MRD register program */ |
| Airdevelopments | 0:6b1a8c783fef | 630 | #if defined(STM32F446xx) |
| Airdevelopments | 0:6b1a8c783fef | 631 | FMC_Bank5_6->SDCMR = 0x00044014; |
| Airdevelopments | 0:6b1a8c783fef | 632 | #else |
| Airdevelopments | 0:6b1a8c783fef | 633 | FMC_Bank5_6->SDCMR = 0x00046014; |
| Airdevelopments | 0:6b1a8c783fef | 634 | #endif /* STM32F446xx */ |
| Airdevelopments | 0:6b1a8c783fef | 635 | timeout = 0xFFFF; |
| Airdevelopments | 0:6b1a8c783fef | 636 | while((tmpreg != 0) && (timeout-- > 0)) |
| Airdevelopments | 0:6b1a8c783fef | 637 | { |
| Airdevelopments | 0:6b1a8c783fef | 638 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Airdevelopments | 0:6b1a8c783fef | 639 | } |
| Airdevelopments | 0:6b1a8c783fef | 640 | |
| Airdevelopments | 0:6b1a8c783fef | 641 | /* Set refresh count */ |
| Airdevelopments | 0:6b1a8c783fef | 642 | tmpreg = FMC_Bank5_6->SDRTR; |
| Airdevelopments | 0:6b1a8c783fef | 643 | #if defined(STM32F446xx) |
| Airdevelopments | 0:6b1a8c783fef | 644 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); |
| Airdevelopments | 0:6b1a8c783fef | 645 | #else |
| Airdevelopments | 0:6b1a8c783fef | 646 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); |
| Airdevelopments | 0:6b1a8c783fef | 647 | #endif /* STM32F446xx */ |
| Airdevelopments | 0:6b1a8c783fef | 648 | |
| Airdevelopments | 0:6b1a8c783fef | 649 | /* Disable write protection */ |
| Airdevelopments | 0:6b1a8c783fef | 650 | tmpreg = FMC_Bank5_6->SDCR[0]; |
| Airdevelopments | 0:6b1a8c783fef | 651 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
| Airdevelopments | 0:6b1a8c783fef | 652 | #endif /* DATA_IN_ExtSDRAM */ |
| Airdevelopments | 0:6b1a8c783fef | 653 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
| Airdevelopments | 0:6b1a8c783fef | 654 | |
| Airdevelopments | 0:6b1a8c783fef | 655 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ |
| Airdevelopments | 0:6b1a8c783fef | 656 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| Airdevelopments | 0:6b1a8c783fef | 657 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) |
| Airdevelopments | 0:6b1a8c783fef | 658 | |
| Airdevelopments | 0:6b1a8c783fef | 659 | #if defined(DATA_IN_ExtSRAM) |
| Airdevelopments | 0:6b1a8c783fef | 660 | /*-- GPIOs Configuration -----------------------------------------------------*/ |
| Airdevelopments | 0:6b1a8c783fef | 661 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ |
| Airdevelopments | 0:6b1a8c783fef | 662 | RCC->AHB1ENR |= 0x00000078; |
| Airdevelopments | 0:6b1a8c783fef | 663 | /* Delay after an RCC peripheral clock enabling */ |
| Airdevelopments | 0:6b1a8c783fef | 664 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); |
| Airdevelopments | 0:6b1a8c783fef | 665 | |
| Airdevelopments | 0:6b1a8c783fef | 666 | /* Connect PDx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 667 | GPIOD->AFR[0] = 0x00CCC0CC; |
| Airdevelopments | 0:6b1a8c783fef | 668 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 669 | /* Configure PDx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 670 | GPIOD->MODER = 0xAAAA0A8A; |
| Airdevelopments | 0:6b1a8c783fef | 671 | /* Configure PDx pins speed to 100 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 672 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
| Airdevelopments | 0:6b1a8c783fef | 673 | /* Configure PDx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 674 | GPIOD->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 675 | /* No pull-up, pull-down for PDx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 676 | GPIOD->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 677 | |
| Airdevelopments | 0:6b1a8c783fef | 678 | /* Connect PEx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 679 | GPIOE->AFR[0] = 0xC00CC0CC; |
| Airdevelopments | 0:6b1a8c783fef | 680 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 681 | /* Configure PEx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 682 | GPIOE->MODER = 0xAAAA828A; |
| Airdevelopments | 0:6b1a8c783fef | 683 | /* Configure PEx pins speed to 100 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 684 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
| Airdevelopments | 0:6b1a8c783fef | 685 | /* Configure PEx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 686 | GPIOE->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 687 | /* No pull-up, pull-down for PEx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 688 | GPIOE->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 689 | |
| Airdevelopments | 0:6b1a8c783fef | 690 | /* Connect PFx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 691 | GPIOF->AFR[0] = 0x00CCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 692 | GPIOF->AFR[1] = 0xCCCC0000; |
| Airdevelopments | 0:6b1a8c783fef | 693 | /* Configure PFx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 694 | GPIOF->MODER = 0xAA000AAA; |
| Airdevelopments | 0:6b1a8c783fef | 695 | /* Configure PFx pins speed to 100 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 696 | GPIOF->OSPEEDR = 0xFF000FFF; |
| Airdevelopments | 0:6b1a8c783fef | 697 | /* Configure PFx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 698 | GPIOF->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 699 | /* No pull-up, pull-down for PFx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 700 | GPIOF->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 701 | |
| Airdevelopments | 0:6b1a8c783fef | 702 | /* Connect PGx pins to FMC Alternate function */ |
| Airdevelopments | 0:6b1a8c783fef | 703 | GPIOG->AFR[0] = 0x00CCCCCC; |
| Airdevelopments | 0:6b1a8c783fef | 704 | GPIOG->AFR[1] = 0x000000C0; |
| Airdevelopments | 0:6b1a8c783fef | 705 | /* Configure PGx pins in Alternate function mode */ |
| Airdevelopments | 0:6b1a8c783fef | 706 | GPIOG->MODER = 0x00085AAA; |
| Airdevelopments | 0:6b1a8c783fef | 707 | /* Configure PGx pins speed to 100 MHz */ |
| Airdevelopments | 0:6b1a8c783fef | 708 | GPIOG->OSPEEDR = 0x000CAFFF; |
| Airdevelopments | 0:6b1a8c783fef | 709 | /* Configure PGx pins Output type to push-pull */ |
| Airdevelopments | 0:6b1a8c783fef | 710 | GPIOG->OTYPER = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 711 | /* No pull-up, pull-down for PGx pins */ |
| Airdevelopments | 0:6b1a8c783fef | 712 | GPIOG->PUPDR = 0x00000000; |
| Airdevelopments | 0:6b1a8c783fef | 713 | |
| Airdevelopments | 0:6b1a8c783fef | 714 | /*-- FMC/FSMC Configuration --------------------------------------------------*/ |
| Airdevelopments | 0:6b1a8c783fef | 715 | /* Enable the FMC/FSMC interface clock */ |
| Airdevelopments | 0:6b1a8c783fef | 716 | RCC->AHB3ENR |= 0x00000001; |
| Airdevelopments | 0:6b1a8c783fef | 717 | |
| Airdevelopments | 0:6b1a8c783fef | 718 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| Airdevelopments | 0:6b1a8c783fef | 719 | /* Delay after an RCC peripheral clock enabling */ |
| Airdevelopments | 0:6b1a8c783fef | 720 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| Airdevelopments | 0:6b1a8c783fef | 721 | /* Configure and enable Bank1_SRAM2 */ |
| Airdevelopments | 0:6b1a8c783fef | 722 | FMC_Bank1->BTCR[2] = 0x00001011; |
| Airdevelopments | 0:6b1a8c783fef | 723 | FMC_Bank1->BTCR[3] = 0x00000201; |
| Airdevelopments | 0:6b1a8c783fef | 724 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| Airdevelopments | 0:6b1a8c783fef | 725 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| Airdevelopments | 0:6b1a8c783fef | 726 | #if defined(STM32F469xx) || defined(STM32F479xx) |
| Airdevelopments | 0:6b1a8c783fef | 727 | /* Delay after an RCC peripheral clock enabling */ |
| Airdevelopments | 0:6b1a8c783fef | 728 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| Airdevelopments | 0:6b1a8c783fef | 729 | /* Configure and enable Bank1_SRAM2 */ |
| Airdevelopments | 0:6b1a8c783fef | 730 | FMC_Bank1->BTCR[2] = 0x00001091; |
| Airdevelopments | 0:6b1a8c783fef | 731 | FMC_Bank1->BTCR[3] = 0x00110212; |
| Airdevelopments | 0:6b1a8c783fef | 732 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| Airdevelopments | 0:6b1a8c783fef | 733 | #endif /* STM32F469xx || STM32F479xx */ |
| Airdevelopments | 0:6b1a8c783fef | 734 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ |
| Airdevelopments | 0:6b1a8c783fef | 735 | || defined(STM32F412Zx) || defined(STM32F412Vx) |
| Airdevelopments | 0:6b1a8c783fef | 736 | /* Delay after an RCC peripheral clock enabling */ |
| Airdevelopments | 0:6b1a8c783fef | 737 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); |
| Airdevelopments | 0:6b1a8c783fef | 738 | /* Configure and enable Bank1_SRAM2 */ |
| Airdevelopments | 0:6b1a8c783fef | 739 | FSMC_Bank1->BTCR[2] = 0x00001011; |
| Airdevelopments | 0:6b1a8c783fef | 740 | FSMC_Bank1->BTCR[3] = 0x00000201; |
| Airdevelopments | 0:6b1a8c783fef | 741 | FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; |
| Airdevelopments | 0:6b1a8c783fef | 742 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ |
| Airdevelopments | 0:6b1a8c783fef | 743 | |
| Airdevelopments | 0:6b1a8c783fef | 744 | #endif /* DATA_IN_ExtSRAM */ |
| Airdevelopments | 0:6b1a8c783fef | 745 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ |
| Airdevelopments | 0:6b1a8c783fef | 746 | STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ |
| Airdevelopments | 0:6b1a8c783fef | 747 | (void)(tmp); |
| Airdevelopments | 0:6b1a8c783fef | 748 | } |
| Airdevelopments | 0:6b1a8c783fef | 749 | #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ |
| Airdevelopments | 0:6b1a8c783fef | 750 | /** |
| Airdevelopments | 0:6b1a8c783fef | 751 | * @} |
| Airdevelopments | 0:6b1a8c783fef | 752 | */ |
| Airdevelopments | 0:6b1a8c783fef | 753 | |
| Airdevelopments | 0:6b1a8c783fef | 754 | /** |
| Airdevelopments | 0:6b1a8c783fef | 755 | * @} |
| Airdevelopments | 0:6b1a8c783fef | 756 | */ |
| Airdevelopments | 0:6b1a8c783fef | 757 | |
| Airdevelopments | 0:6b1a8c783fef | 758 | /** |
| Airdevelopments | 0:6b1a8c783fef | 759 | * @} |
| Airdevelopments | 0:6b1a8c783fef | 760 | */ |
| Airdevelopments | 0:6b1a8c783fef | 761 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| Airdevelopments | 0:6b1a8c783fef | 762 |