wanjun chen / Mbed 2 deprecated Nucleo_BLE_Demo

IOTIO

Dependencies:   Nucleo_BLE_API_IOTIO Nucleo_BLE_BlueNRG Nucleo_BLE_DemoApp Nucleo_Sensor_Shield mbed

Dependents:   Nucleo_BLE_Demo_IOTIO

Fork of Nucleo_BLE_Demo by Cortex Challenge Team

mbed/spi_api.h@2:c69117fc79da, 2017-03-08 (annotated)

Committer:
16038618
Date:
Wed Mar 08 10:24:56 2017 +0000
Revision:
2:c69117fc79da
Parent:
1:4bdfa7d7e8bf 
IOTIO

Who changed what in which revision?

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16038618 1:4bdfa7d7e8bf 1 /* mbed Microcontroller Library
16038618 1:4bdfa7d7e8bf 2 * Copyright (c) 2006-2013 ARM Limited
16038618 1:4bdfa7d7e8bf 3 *
16038618 1:4bdfa7d7e8bf 4 * Licensed under the Apache License, Version 2.0 (the "License");
16038618 1:4bdfa7d7e8bf 5 * you may not use this file except in compliance with the License.
16038618 1:4bdfa7d7e8bf 6 * You may obtain a copy of the License at
16038618 1:4bdfa7d7e8bf 7 *
16038618 1:4bdfa7d7e8bf 8 * http://www.apache.org/licenses/LICENSE-2.0
16038618 1:4bdfa7d7e8bf 9 *
16038618 1:4bdfa7d7e8bf 10 * Unless required by applicable law or agreed to in writing, software
16038618 1:4bdfa7d7e8bf 11 * distributed under the License is distributed on an "AS IS" BASIS,
16038618 1:4bdfa7d7e8bf 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16038618 1:4bdfa7d7e8bf 13 * See the License for the specific language governing permissions and
16038618 1:4bdfa7d7e8bf 14 * limitations under the License.
16038618 1:4bdfa7d7e8bf 15 */
16038618 1:4bdfa7d7e8bf 16 #ifndef MBED_SPI_API_H
16038618 1:4bdfa7d7e8bf 17 #define MBED_SPI_API_H
16038618 1:4bdfa7d7e8bf 18
16038618 1:4bdfa7d7e8bf 19 #include "device.h"
16038618 1:4bdfa7d7e8bf 20 #include "dma_api.h"
16038618 1:4bdfa7d7e8bf 21 #include "buffer.h"
16038618 1:4bdfa7d7e8bf 22
16038618 1:4bdfa7d7e8bf 23 #if DEVICE_SPI
16038618 1:4bdfa7d7e8bf 24
16038618 1:4bdfa7d7e8bf 25 #define SPI_EVENT_ERROR (1 << 1)
16038618 1:4bdfa7d7e8bf 26 #define SPI_EVENT_COMPLETE (1 << 2)
16038618 1:4bdfa7d7e8bf 27 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
16038618 1:4bdfa7d7e8bf 28 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
16038618 1:4bdfa7d7e8bf 29
16038618 1:4bdfa7d7e8bf 30 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // internal flag to report an event occurred
16038618 1:4bdfa7d7e8bf 31
16038618 1:4bdfa7d7e8bf 32 #define SPI_FILL_WORD (0xFFFF)
16038618 1:4bdfa7d7e8bf 33
16038618 1:4bdfa7d7e8bf 34 #if DEVICE_SPI_ASYNCH
16038618 1:4bdfa7d7e8bf 35 /** Asynch spi hal structure
16038618 1:4bdfa7d7e8bf 36 */
16038618 1:4bdfa7d7e8bf 37 typedef struct {
16038618 1:4bdfa7d7e8bf 38 struct spi_s spi; /**< Target specific spi structure */
16038618 1:4bdfa7d7e8bf 39 struct buffer_s tx_buff; /**< Tx buffer */
16038618 1:4bdfa7d7e8bf 40 struct buffer_s rx_buff; /**< Rx buffer */
16038618 1:4bdfa7d7e8bf 41 } spi_t;
16038618 1:4bdfa7d7e8bf 42
16038618 1:4bdfa7d7e8bf 43 #else
16038618 1:4bdfa7d7e8bf 44 /** Non-asynch spi hal structure
16038618 1:4bdfa7d7e8bf 45 */
16038618 1:4bdfa7d7e8bf 46 typedef struct spi_s spi_t;
16038618 1:4bdfa7d7e8bf 47
16038618 1:4bdfa7d7e8bf 48 #endif
16038618 1:4bdfa7d7e8bf 49
16038618 1:4bdfa7d7e8bf 50 #ifdef __cplusplus
16038618 1:4bdfa7d7e8bf 51 extern "C" {
16038618 1:4bdfa7d7e8bf 52 #endif
16038618 1:4bdfa7d7e8bf 53
16038618 1:4bdfa7d7e8bf 54 /**
16038618 1:4bdfa7d7e8bf 55 * \defgroup GeneralSPI SPI Configuration Functions
16038618 1:4bdfa7d7e8bf 56 * @{
16038618 1:4bdfa7d7e8bf 57 */
16038618 1:4bdfa7d7e8bf 58
16038618 1:4bdfa7d7e8bf 59 /** Initialize the SPI peripheral
16038618 1:4bdfa7d7e8bf 60 *
16038618 1:4bdfa7d7e8bf 61 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
16038618 1:4bdfa7d7e8bf 62 * @param[out] obj The SPI object to initialize
16038618 1:4bdfa7d7e8bf 63 * @param[in] mosi The pin to use for MOSI
16038618 1:4bdfa7d7e8bf 64 * @param[in] miso The pin to use for MISO
16038618 1:4bdfa7d7e8bf 65 * @param[in] sclk The pin to use for SCLK
16038618 1:4bdfa7d7e8bf 66 * @param[in] ssel The pin to use for SSEL
16038618 1:4bdfa7d7e8bf 67 */
16038618 1:4bdfa7d7e8bf 68 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
16038618 1:4bdfa7d7e8bf 69
16038618 1:4bdfa7d7e8bf 70 /** Release a SPI object
16038618 1:4bdfa7d7e8bf 71 *
16038618 1:4bdfa7d7e8bf 72 * TODO: spi_free is currently unimplemented
16038618 1:4bdfa7d7e8bf 73 * This will require reference counting at the C++ level to be safe
16038618 1:4bdfa7d7e8bf 74 *
16038618 1:4bdfa7d7e8bf 75 * Return the pins owned by the SPI object to their reset state
16038618 1:4bdfa7d7e8bf 76 * Disable the SPI peripheral
16038618 1:4bdfa7d7e8bf 77 * Disable the SPI clock
16038618 1:4bdfa7d7e8bf 78 * @param[in] obj The SPI object to deinitialize
16038618 1:4bdfa7d7e8bf 79 */
16038618 1:4bdfa7d7e8bf 80 void spi_free(spi_t *obj);
16038618 1:4bdfa7d7e8bf 81
16038618 1:4bdfa7d7e8bf 82 /** Configure the SPI format
16038618 1:4bdfa7d7e8bf 83 *
16038618 1:4bdfa7d7e8bf 84 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode
16038618 1:4bdfa7d7e8bf 85 * @param[in,out] obj The SPI object to configure
16038618 1:4bdfa7d7e8bf 86 * @param[in] bits The number of bits per frame
16038618 1:4bdfa7d7e8bf 87 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
16038618 1:4bdfa7d7e8bf 88 * @param[in] slave Zero for master mode or non-zero for slave mode
16038618 1:4bdfa7d7e8bf 89 */
16038618 1:4bdfa7d7e8bf 90 void spi_format(spi_t *obj, int bits, int mode, int slave);
16038618 1:4bdfa7d7e8bf 91
16038618 1:4bdfa7d7e8bf 92 /** Set the SPI baud rate
16038618 1:4bdfa7d7e8bf 93 *
16038618 1:4bdfa7d7e8bf 94 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
16038618 1:4bdfa7d7e8bf 95 * Configures the SPI peripheral's baud rate
16038618 1:4bdfa7d7e8bf 96 * @param[in,out] obj The SPI object to configure
16038618 1:4bdfa7d7e8bf 97 * @param[in] hz The baud rate in Hz
16038618 1:4bdfa7d7e8bf 98 */
16038618 1:4bdfa7d7e8bf 99 void spi_frequency(spi_t *obj, int hz);
16038618 1:4bdfa7d7e8bf 100
16038618 1:4bdfa7d7e8bf 101 /**@}*/
16038618 1:4bdfa7d7e8bf 102 /**
16038618 1:4bdfa7d7e8bf 103 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
16038618 1:4bdfa7d7e8bf 104 * @{
16038618 1:4bdfa7d7e8bf 105 */
16038618 1:4bdfa7d7e8bf 106
16038618 1:4bdfa7d7e8bf 107 /** Write a byte out in master mode and receive a value
16038618 1:4bdfa7d7e8bf 108 *
16038618 1:4bdfa7d7e8bf 109 * @param[in] obj The SPI peripheral to use for sending
16038618 1:4bdfa7d7e8bf 110 * @param[in] value The value to send
16038618 1:4bdfa7d7e8bf 111 * @return Returns the value received during send
16038618 1:4bdfa7d7e8bf 112 */
16038618 1:4bdfa7d7e8bf 113 int spi_master_write(spi_t *obj, int value);
16038618 1:4bdfa7d7e8bf 114
16038618 1:4bdfa7d7e8bf 115 /** Check if a value is available to read
16038618 1:4bdfa7d7e8bf 116 *
16038618 1:4bdfa7d7e8bf 117 * @param[in] obj The SPI peripheral to check
16038618 1:4bdfa7d7e8bf 118 * @return non-zero if a value is available
16038618 1:4bdfa7d7e8bf 119 */
16038618 1:4bdfa7d7e8bf 120 int spi_slave_receive(spi_t *obj);
16038618 1:4bdfa7d7e8bf 121
16038618 1:4bdfa7d7e8bf 122 /** Get a received value out of the SPI receive buffer in slave mode
16038618 1:4bdfa7d7e8bf 123 *
16038618 1:4bdfa7d7e8bf 124 * Blocks until a value is available
16038618 1:4bdfa7d7e8bf 125 * @param[in] obj The SPI peripheral to read
16038618 1:4bdfa7d7e8bf 126 * @return The value received
16038618 1:4bdfa7d7e8bf 127 */
16038618 1:4bdfa7d7e8bf 128 int spi_slave_read(spi_t *obj);
16038618 1:4bdfa7d7e8bf 129
16038618 1:4bdfa7d7e8bf 130 /** Write a value to the SPI peripheral in slave mode
16038618 1:4bdfa7d7e8bf 131 *
16038618 1:4bdfa7d7e8bf 132 * Blocks until the SPI peripheral can be written to
16038618 1:4bdfa7d7e8bf 133 * @param[in] obj The SPI peripheral to write
16038618 1:4bdfa7d7e8bf 134 * @param[in] value The value to write
16038618 1:4bdfa7d7e8bf 135 */
16038618 1:4bdfa7d7e8bf 136 void spi_slave_write(spi_t *obj, int value);
16038618 1:4bdfa7d7e8bf 137
16038618 1:4bdfa7d7e8bf 138 /** Checks if the specified SPI peripheral is in use
16038618 1:4bdfa7d7e8bf 139 *
16038618 1:4bdfa7d7e8bf 140 * @param[in] obj The SPI peripheral to check
16038618 1:4bdfa7d7e8bf 141 * @return non-zero if the peripheral is currently transmitting
16038618 1:4bdfa7d7e8bf 142 */
16038618 1:4bdfa7d7e8bf 143 int spi_busy(spi_t *obj);
16038618 1:4bdfa7d7e8bf 144
16038618 1:4bdfa7d7e8bf 145 /** Get the module number
16038618 1:4bdfa7d7e8bf 146 *
16038618 1:4bdfa7d7e8bf 147 * @param[in] obj The SPI peripheral to check
16038618 1:4bdfa7d7e8bf 148 * @return The module number
16038618 1:4bdfa7d7e8bf 149 */
16038618 1:4bdfa7d7e8bf 150 uint8_t spi_get_module(spi_t *obj);
16038618 1:4bdfa7d7e8bf 151
16038618 1:4bdfa7d7e8bf 152 /**@}*/
16038618 1:4bdfa7d7e8bf 153
16038618 1:4bdfa7d7e8bf 154 #if DEVICE_SPI_ASYNCH
16038618 1:4bdfa7d7e8bf 155 /**
16038618 1:4bdfa7d7e8bf 156 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
16038618 1:4bdfa7d7e8bf 157 * @{
16038618 1:4bdfa7d7e8bf 158 */
16038618 1:4bdfa7d7e8bf 159
16038618 1:4bdfa7d7e8bf 160 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
16038618 1:4bdfa7d7e8bf 161 *
16038618 1:4bdfa7d7e8bf 162 * @param[in] obj The SPI object which holds the transfer information
16038618 1:4bdfa7d7e8bf 163 * @param[in] tx The buffer to send
16038618 1:4bdfa7d7e8bf 164 * @param[in] tx_length The number of words to transmit
16038618 1:4bdfa7d7e8bf 165 * @param[in] rx The buffer to receive
16038618 1:4bdfa7d7e8bf 166 * @param[in] rx_length The number of words to receive
16038618 1:4bdfa7d7e8bf 167 * @param[in] bit_width The bit width of buffer words
16038618 1:4bdfa7d7e8bf 168 * @param[in] event The logical OR of events to be registered
16038618 1:4bdfa7d7e8bf 169 * @param[in] handler SPI interrupt handler
16038618 1:4bdfa7d7e8bf 170 * @param[in] hint A suggestion for how to use DMA with this transfer
16038618 1:4bdfa7d7e8bf 171 */
16038618 1:4bdfa7d7e8bf 172 void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
16038618 1:4bdfa7d7e8bf 173
16038618 1:4bdfa7d7e8bf 174 /** The asynchronous IRQ handler
16038618 1:4bdfa7d7e8bf 175 *
16038618 1:4bdfa7d7e8bf 176 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
16038618 1:4bdfa7d7e8bf 177 * conditions, such as buffer overflows or transfer complete.
16038618 1:4bdfa7d7e8bf 178 * @param[in] obj The SPI object which holds the transfer information
16038618 1:4bdfa7d7e8bf 179 * @return event flags if a transfer termination condition was met or 0 otherwise.
16038618 1:4bdfa7d7e8bf 180 */
16038618 1:4bdfa7d7e8bf 181 uint32_t spi_irq_handler_asynch(spi_t *obj);
16038618 1:4bdfa7d7e8bf 182
16038618 1:4bdfa7d7e8bf 183 /** Attempts to determine if the SPI peripheral is already in use.
16038618 1:4bdfa7d7e8bf 184 *
16038618 1:4bdfa7d7e8bf 185 * If a temporary DMA channel has been allocated, peripheral is in use.
16038618 1:4bdfa7d7e8bf 186 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
16038618 1:4bdfa7d7e8bf 187 * channel were allocated.
16038618 1:4bdfa7d7e8bf 188 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
16038618 1:4bdfa7d7e8bf 189 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
16038618 1:4bdfa7d7e8bf 190 * there are any bytes in the FIFOs.
16038618 1:4bdfa7d7e8bf 191 * @param[in] obj The SPI object to check for activity
16038618 1:4bdfa7d7e8bf 192 * @return non-zero if the SPI port is active or zero if it is not.
16038618 1:4bdfa7d7e8bf 193 */
16038618 1:4bdfa7d7e8bf 194 uint8_t spi_active(spi_t *obj);
16038618 1:4bdfa7d7e8bf 195
16038618 1:4bdfa7d7e8bf 196 /** Abort an SPI transfer
16038618 1:4bdfa7d7e8bf 197 *
16038618 1:4bdfa7d7e8bf 198 * @param obj The SPI peripheral to stop
16038618 1:4bdfa7d7e8bf 199 */
16038618 1:4bdfa7d7e8bf 200 void spi_abort_asynch(spi_t *obj);
16038618 1:4bdfa7d7e8bf 201
16038618 1:4bdfa7d7e8bf 202
16038618 1:4bdfa7d7e8bf 203 #endif
16038618 1:4bdfa7d7e8bf 204
16038618 1:4bdfa7d7e8bf 205 /**@}*/
16038618 1:4bdfa7d7e8bf 206
16038618 1:4bdfa7d7e8bf 207 #ifdef __cplusplus
16038618 1:4bdfa7d7e8bf 208 }
16038618 1:4bdfa7d7e8bf 209 #endif // __cplusplus
16038618 1:4bdfa7d7e8bf 210
16038618 1:4bdfa7d7e8bf 211 #endif // SPI_DEVICE
16038618 1:4bdfa7d7e8bf 212
16038618 1:4bdfa7d7e8bf 213 #endif // MBED_SPI_API_H