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stm32746g_discovery_qspi.c@1:ee089790cdbb, 2016-01-04 (annotated)

Committer:
bcostm
Date:
Mon Jan 04 15:19:15 2016 +0000
Revision:
1:ee089790cdbb
Add missing files

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bcostm 1:ee089790cdbb 1 /**
bcostm 1:ee089790cdbb 2 ******************************************************************************
bcostm 1:ee089790cdbb 3 * @file stm32746g_discovery_qspi.c
bcostm 1:ee089790cdbb 4 * @author MCD Application Team
bcostm 1:ee089790cdbb 5 * @version V1.0.0
bcostm 1:ee089790cdbb 6 * @date 25-June-2015
bcostm 1:ee089790cdbb 7 * @brief This file includes a standard driver for the N25Q128A QSPI
bcostm 1:ee089790cdbb 8 * memory mounted on STM32746G-Discovery board.
bcostm 1:ee089790cdbb 9 @verbatim
bcostm 1:ee089790cdbb 10 ==============================================================================
bcostm 1:ee089790cdbb 11 ##### How to use this driver #####
bcostm 1:ee089790cdbb 12 ==============================================================================
bcostm 1:ee089790cdbb 13 [..]
bcostm 1:ee089790cdbb 14 (#) This driver is used to drive the N25Q128A QSPI external
bcostm 1:ee089790cdbb 15 memory mounted on STM32746G-Discovery board.
bcostm 1:ee089790cdbb 16
bcostm 1:ee089790cdbb 17 (#) This driver need a specific component driver (N25Q128A) to be included with.
bcostm 1:ee089790cdbb 18
bcostm 1:ee089790cdbb 19 (#) Initialization steps:
bcostm 1:ee089790cdbb 20 (++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This
bcostm 1:ee089790cdbb 21 function includes the MSP layer hardware resources initialization and the
bcostm 1:ee089790cdbb 22 QSPI interface with the external memory.
bcostm 1:ee089790cdbb 23
bcostm 1:ee089790cdbb 24 (#) QSPI memory operations
bcostm 1:ee089790cdbb 25 (++) QSPI memory can be accessed with read/write operations once it is
bcostm 1:ee089790cdbb 26 initialized.
bcostm 1:ee089790cdbb 27 Read/write operation can be performed with AHB access using the functions
bcostm 1:ee089790cdbb 28 BSP_QSPI_Read()/BSP_QSPI_Write().
bcostm 1:ee089790cdbb 29 (++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory.
bcostm 1:ee089790cdbb 30 (see the QSPI memory data sheet)
bcostm 1:ee089790cdbb 31 (++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by
bcostm 1:ee089790cdbb 32 specifying the block address. You can perform an erase operation of the whole
bcostm 1:ee089790cdbb 33 chip by calling the function BSP_QSPI_Erase_Chip().
bcostm 1:ee089790cdbb 34 (++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory.
bcostm 1:ee089790cdbb 35 (see the QSPI memory data sheet)
bcostm 1:ee089790cdbb 36 @endverbatim
bcostm 1:ee089790cdbb 37 ******************************************************************************
bcostm 1:ee089790cdbb 38 * @attention
bcostm 1:ee089790cdbb 39 *
bcostm 1:ee089790cdbb 40 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bcostm 1:ee089790cdbb 41 *
bcostm 1:ee089790cdbb 42 * Redistribution and use in source and binary forms, with or without modification,
bcostm 1:ee089790cdbb 43 * are permitted provided that the following conditions are met:
bcostm 1:ee089790cdbb 44 * 1. Redistributions of source code must retain the above copyright notice,
bcostm 1:ee089790cdbb 45 * this list of conditions and the following disclaimer.
bcostm 1:ee089790cdbb 46 * 2. Redistributions in binary form must reproduce the above copyright notice,
bcostm 1:ee089790cdbb 47 * this list of conditions and the following disclaimer in the documentation
bcostm 1:ee089790cdbb 48 * and/or other materials provided with the distribution.
bcostm 1:ee089790cdbb 49 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bcostm 1:ee089790cdbb 50 * may be used to endorse or promote products derived from this software
bcostm 1:ee089790cdbb 51 * without specific prior written permission.
bcostm 1:ee089790cdbb 52 *
bcostm 1:ee089790cdbb 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bcostm 1:ee089790cdbb 54 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bcostm 1:ee089790cdbb 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bcostm 1:ee089790cdbb 56 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bcostm 1:ee089790cdbb 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bcostm 1:ee089790cdbb 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bcostm 1:ee089790cdbb 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bcostm 1:ee089790cdbb 60 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bcostm 1:ee089790cdbb 61 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bcostm 1:ee089790cdbb 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bcostm 1:ee089790cdbb 63 *
bcostm 1:ee089790cdbb 64 ******************************************************************************
bcostm 1:ee089790cdbb 65 */
bcostm 1:ee089790cdbb 66
bcostm 1:ee089790cdbb 67 /* Includes ------------------------------------------------------------------*/
bcostm 1:ee089790cdbb 68 #include "stm32746g_discovery_qspi.h"
bcostm 1:ee089790cdbb 69
bcostm 1:ee089790cdbb 70 /** @addtogroup BSP
bcostm 1:ee089790cdbb 71 * @{
bcostm 1:ee089790cdbb 72 */
bcostm 1:ee089790cdbb 73
bcostm 1:ee089790cdbb 74 /** @addtogroup STM32746G_DISCOVERY
bcostm 1:ee089790cdbb 75 * @{
bcostm 1:ee089790cdbb 76 */
bcostm 1:ee089790cdbb 77
bcostm 1:ee089790cdbb 78 /** @defgroup STM32746G_DISCOVERY_QSPI STM32746G-Discovery QSPI
bcostm 1:ee089790cdbb 79 * @{
bcostm 1:ee089790cdbb 80 */
bcostm 1:ee089790cdbb 81
bcostm 1:ee089790cdbb 82
bcostm 1:ee089790cdbb 83 /* Private variables ---------------------------------------------------------*/
bcostm 1:ee089790cdbb 84
bcostm 1:ee089790cdbb 85 /** @defgroup STM32746G_DISCOVERY_QSPI_Private_Variables STM32746G_DISCOVERY QSPI Private Variables
bcostm 1:ee089790cdbb 86 * @{
bcostm 1:ee089790cdbb 87 */
bcostm 1:ee089790cdbb 88 QSPI_HandleTypeDef QSPIHandle;
bcostm 1:ee089790cdbb 89
bcostm 1:ee089790cdbb 90 /**
bcostm 1:ee089790cdbb 91 * @}
bcostm 1:ee089790cdbb 92 */
bcostm 1:ee089790cdbb 93
bcostm 1:ee089790cdbb 94
bcostm 1:ee089790cdbb 95
bcostm 1:ee089790cdbb 96 /* Private functions ---------------------------------------------------------*/
bcostm 1:ee089790cdbb 97
bcostm 1:ee089790cdbb 98 /** @defgroup STM32746G_DISCOVERY_QSPI_Private_Functions STM32746G_DISCOVERY QSPI Private Functions
bcostm 1:ee089790cdbb 99 * @{
bcostm 1:ee089790cdbb 100 */
bcostm 1:ee089790cdbb 101 static uint8_t QSPI_ResetMemory (QSPI_HandleTypeDef *hqspi);
bcostm 1:ee089790cdbb 102 static uint8_t QSPI_DummyCyclesCfg (QSPI_HandleTypeDef *hqspi);
bcostm 1:ee089790cdbb 103 static uint8_t QSPI_WriteEnable (QSPI_HandleTypeDef *hqspi);
bcostm 1:ee089790cdbb 104 static uint8_t QSPI_AutoPollingMemReady (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
bcostm 1:ee089790cdbb 105
bcostm 1:ee089790cdbb 106 /**
bcostm 1:ee089790cdbb 107 * @}
bcostm 1:ee089790cdbb 108 */
bcostm 1:ee089790cdbb 109
bcostm 1:ee089790cdbb 110 /** @defgroup STM32746G_DISCOVERY_QSPI_Exported_Functions STM32746G_DISCOVERY QSPI Exported Functions
bcostm 1:ee089790cdbb 111 * @{
bcostm 1:ee089790cdbb 112 */
bcostm 1:ee089790cdbb 113
bcostm 1:ee089790cdbb 114 /**
bcostm 1:ee089790cdbb 115 * @brief Initializes the QSPI interface.
bcostm 1:ee089790cdbb 116 * @retval QSPI memory status
bcostm 1:ee089790cdbb 117 */
bcostm 1:ee089790cdbb 118 uint8_t BSP_QSPI_Init(void)
bcostm 1:ee089790cdbb 119 {
bcostm 1:ee089790cdbb 120 QSPIHandle.Instance = QUADSPI;
bcostm 1:ee089790cdbb 121
bcostm 1:ee089790cdbb 122 /* Call the DeInit function to reset the driver */
bcostm 1:ee089790cdbb 123 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
bcostm 1:ee089790cdbb 124 {
bcostm 1:ee089790cdbb 125 return QSPI_ERROR;
bcostm 1:ee089790cdbb 126 }
bcostm 1:ee089790cdbb 127
bcostm 1:ee089790cdbb 128 /* System level initialization */
bcostm 1:ee089790cdbb 129 BSP_QSPI_MspInit(&QSPIHandle, NULL);
bcostm 1:ee089790cdbb 130
bcostm 1:ee089790cdbb 131 /* QSPI initialization */
bcostm 1:ee089790cdbb 132 QSPIHandle.Init.ClockPrescaler = 1; /* QSPI freq = 216 MHz/(1+1) = 108 Mhz */
bcostm 1:ee089790cdbb 133 QSPIHandle.Init.FifoThreshold = 4;
bcostm 1:ee089790cdbb 134 QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
bcostm 1:ee089790cdbb 135 QSPIHandle.Init.FlashSize = POSITION_VAL(N25Q128A_FLASH_SIZE) - 1;
bcostm 1:ee089790cdbb 136 QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_2_CYCLE;
bcostm 1:ee089790cdbb 137 QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0;
bcostm 1:ee089790cdbb 138 QSPIHandle.Init.FlashID = QSPI_FLASH_ID_1;
bcostm 1:ee089790cdbb 139 QSPIHandle.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
bcostm 1:ee089790cdbb 140
bcostm 1:ee089790cdbb 141 if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)
bcostm 1:ee089790cdbb 142 {
bcostm 1:ee089790cdbb 143 return QSPI_ERROR;
bcostm 1:ee089790cdbb 144 }
bcostm 1:ee089790cdbb 145
bcostm 1:ee089790cdbb 146 /* QSPI memory reset */
bcostm 1:ee089790cdbb 147 if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK)
bcostm 1:ee089790cdbb 148 {
bcostm 1:ee089790cdbb 149 return QSPI_NOT_SUPPORTED;
bcostm 1:ee089790cdbb 150 }
bcostm 1:ee089790cdbb 151
bcostm 1:ee089790cdbb 152 /* Configuration of the dummy cycles on QSPI memory side */
bcostm 1:ee089790cdbb 153 if (QSPI_DummyCyclesCfg(&QSPIHandle) != QSPI_OK)
bcostm 1:ee089790cdbb 154 {
bcostm 1:ee089790cdbb 155 return QSPI_NOT_SUPPORTED;
bcostm 1:ee089790cdbb 156 }
bcostm 1:ee089790cdbb 157
bcostm 1:ee089790cdbb 158 return QSPI_OK;
bcostm 1:ee089790cdbb 159 }
bcostm 1:ee089790cdbb 160
bcostm 1:ee089790cdbb 161 /**
bcostm 1:ee089790cdbb 162 * @brief De-Initializes the QSPI interface.
bcostm 1:ee089790cdbb 163 * @retval QSPI memory status
bcostm 1:ee089790cdbb 164 */
bcostm 1:ee089790cdbb 165 uint8_t BSP_QSPI_DeInit(void)
bcostm 1:ee089790cdbb 166 {
bcostm 1:ee089790cdbb 167 QSPIHandle.Instance = QUADSPI;
bcostm 1:ee089790cdbb 168
bcostm 1:ee089790cdbb 169 /* Call the DeInit function to reset the driver */
bcostm 1:ee089790cdbb 170 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
bcostm 1:ee089790cdbb 171 {
bcostm 1:ee089790cdbb 172 return QSPI_ERROR;
bcostm 1:ee089790cdbb 173 }
bcostm 1:ee089790cdbb 174
bcostm 1:ee089790cdbb 175 /* System level De-initialization */
bcostm 1:ee089790cdbb 176 BSP_QSPI_MspDeInit(&QSPIHandle, NULL);
bcostm 1:ee089790cdbb 177
bcostm 1:ee089790cdbb 178 return QSPI_OK;
bcostm 1:ee089790cdbb 179 }
bcostm 1:ee089790cdbb 180
bcostm 1:ee089790cdbb 181 /**
bcostm 1:ee089790cdbb 182 * @brief Reads an amount of data from the QSPI memory.
bcostm 1:ee089790cdbb 183 * @param pData: Pointer to data to be read
bcostm 1:ee089790cdbb 184 * @param ReadAddr: Read start address
bcostm 1:ee089790cdbb 185 * @param Size: Size of data to read
bcostm 1:ee089790cdbb 186 * @retval QSPI memory status
bcostm 1:ee089790cdbb 187 */
bcostm 1:ee089790cdbb 188 uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size)
bcostm 1:ee089790cdbb 189 {
bcostm 1:ee089790cdbb 190 QSPI_CommandTypeDef s_command;
bcostm 1:ee089790cdbb 191
bcostm 1:ee089790cdbb 192 /* Initialize the read command */
bcostm 1:ee089790cdbb 193 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 1:ee089790cdbb 194 s_command.Instruction = QUAD_INOUT_FAST_READ_CMD;
bcostm 1:ee089790cdbb 195 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
bcostm 1:ee089790cdbb 196 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 1:ee089790cdbb 197 s_command.Address = ReadAddr;
bcostm 1:ee089790cdbb 198 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 1:ee089790cdbb 199 s_command.DataMode = QSPI_DATA_4_LINES;
bcostm 1:ee089790cdbb 200 s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD;
bcostm 1:ee089790cdbb 201 s_command.NbData = Size;
bcostm 1:ee089790cdbb 202 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 1:ee089790cdbb 203 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 1:ee089790cdbb 204 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 1:ee089790cdbb 205
bcostm 1:ee089790cdbb 206 /* Configure the command */
bcostm 1:ee089790cdbb 207 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 208 {
bcostm 1:ee089790cdbb 209 return QSPI_ERROR;
bcostm 1:ee089790cdbb 210 }
bcostm 1:ee089790cdbb 211
bcostm 1:ee089790cdbb 212 /* Reception of the data */
bcostm 1:ee089790cdbb 213 if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 214 {
bcostm 1:ee089790cdbb 215 return QSPI_ERROR;
bcostm 1:ee089790cdbb 216 }
bcostm 1:ee089790cdbb 217
bcostm 1:ee089790cdbb 218 return QSPI_OK;
bcostm 1:ee089790cdbb 219 }
bcostm 1:ee089790cdbb 220
bcostm 1:ee089790cdbb 221 /**
bcostm 1:ee089790cdbb 222 * @brief Writes an amount of data to the QSPI memory.
bcostm 1:ee089790cdbb 223 * @param pData: Pointer to data to be written
bcostm 1:ee089790cdbb 224 * @param WriteAddr: Write start address
bcostm 1:ee089790cdbb 225 * @param Size: Size of data to write
bcostm 1:ee089790cdbb 226 * @retval QSPI memory status
bcostm 1:ee089790cdbb 227 */
bcostm 1:ee089790cdbb 228 uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size)
bcostm 1:ee089790cdbb 229 {
bcostm 1:ee089790cdbb 230 QSPI_CommandTypeDef s_command;
bcostm 1:ee089790cdbb 231 uint32_t end_addr, current_size, current_addr;
bcostm 1:ee089790cdbb 232
bcostm 1:ee089790cdbb 233 /* Calculation of the size between the write address and the end of the page */
bcostm 1:ee089790cdbb 234 current_addr = 0;
bcostm 1:ee089790cdbb 235
bcostm 1:ee089790cdbb 236 while (current_addr <= WriteAddr)
bcostm 1:ee089790cdbb 237 {
bcostm 1:ee089790cdbb 238 current_addr += N25Q128A_PAGE_SIZE;
bcostm 1:ee089790cdbb 239 }
bcostm 1:ee089790cdbb 240 current_size = current_addr - WriteAddr;
bcostm 1:ee089790cdbb 241
bcostm 1:ee089790cdbb 242 /* Check if the size of the data is less than the remaining place in the page */
bcostm 1:ee089790cdbb 243 if (current_size > Size)
bcostm 1:ee089790cdbb 244 {
bcostm 1:ee089790cdbb 245 current_size = Size;
bcostm 1:ee089790cdbb 246 }
bcostm 1:ee089790cdbb 247
bcostm 1:ee089790cdbb 248 /* Initialize the adress variables */
bcostm 1:ee089790cdbb 249 current_addr = WriteAddr;
bcostm 1:ee089790cdbb 250 end_addr = WriteAddr + Size;
bcostm 1:ee089790cdbb 251
bcostm 1:ee089790cdbb 252 /* Initialize the program command */
bcostm 1:ee089790cdbb 253 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 1:ee089790cdbb 254 s_command.Instruction = EXT_QUAD_IN_FAST_PROG_CMD;
bcostm 1:ee089790cdbb 255 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
bcostm 1:ee089790cdbb 256 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 1:ee089790cdbb 257 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 1:ee089790cdbb 258 s_command.DataMode = QSPI_DATA_4_LINES;
bcostm 1:ee089790cdbb 259 s_command.DummyCycles = 0;
bcostm 1:ee089790cdbb 260 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 1:ee089790cdbb 261 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 1:ee089790cdbb 262 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 1:ee089790cdbb 263
bcostm 1:ee089790cdbb 264 /* Perform the write page by page */
bcostm 1:ee089790cdbb 265 do
bcostm 1:ee089790cdbb 266 {
bcostm 1:ee089790cdbb 267 s_command.Address = current_addr;
bcostm 1:ee089790cdbb 268 s_command.NbData = current_size;
bcostm 1:ee089790cdbb 269
bcostm 1:ee089790cdbb 270 /* Enable write operations */
bcostm 1:ee089790cdbb 271 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 1:ee089790cdbb 272 {
bcostm 1:ee089790cdbb 273 return QSPI_ERROR;
bcostm 1:ee089790cdbb 274 }
bcostm 1:ee089790cdbb 275
bcostm 1:ee089790cdbb 276 /* Configure the command */
bcostm 1:ee089790cdbb 277 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 278 {
bcostm 1:ee089790cdbb 279 return QSPI_ERROR;
bcostm 1:ee089790cdbb 280 }
bcostm 1:ee089790cdbb 281
bcostm 1:ee089790cdbb 282 /* Transmission of the data */
bcostm 1:ee089790cdbb 283 if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 284 {
bcostm 1:ee089790cdbb 285 return QSPI_ERROR;
bcostm 1:ee089790cdbb 286 }
bcostm 1:ee089790cdbb 287
bcostm 1:ee089790cdbb 288 /* Configure automatic polling mode to wait for end of program */
bcostm 1:ee089790cdbb 289 if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
bcostm 1:ee089790cdbb 290 {
bcostm 1:ee089790cdbb 291 return QSPI_ERROR;
bcostm 1:ee089790cdbb 292 }
bcostm 1:ee089790cdbb 293
bcostm 1:ee089790cdbb 294 /* Update the address and size variables for next page programming */
bcostm 1:ee089790cdbb 295 current_addr += current_size;
bcostm 1:ee089790cdbb 296 pData += current_size;
bcostm 1:ee089790cdbb 297 current_size = ((current_addr + N25Q128A_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : N25Q128A_PAGE_SIZE;
bcostm 1:ee089790cdbb 298 } while (current_addr < end_addr);
bcostm 1:ee089790cdbb 299
bcostm 1:ee089790cdbb 300 return QSPI_OK;
bcostm 1:ee089790cdbb 301 }
bcostm 1:ee089790cdbb 302
bcostm 1:ee089790cdbb 303 /**
bcostm 1:ee089790cdbb 304 * @brief Erases the specified block of the QSPI memory.
bcostm 1:ee089790cdbb 305 * @param BlockAddress: Block address to erase
bcostm 1:ee089790cdbb 306 * @retval QSPI memory status
bcostm 1:ee089790cdbb 307 */
bcostm 1:ee089790cdbb 308 uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress)
bcostm 1:ee089790cdbb 309 {
bcostm 1:ee089790cdbb 310 QSPI_CommandTypeDef s_command;
bcostm 1:ee089790cdbb 311
bcostm 1:ee089790cdbb 312 /* Initialize the erase command */
bcostm 1:ee089790cdbb 313 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 1:ee089790cdbb 314 s_command.Instruction = SUBSECTOR_ERASE_CMD;
bcostm 1:ee089790cdbb 315 s_command.AddressMode = QSPI_ADDRESS_1_LINE;
bcostm 1:ee089790cdbb 316 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 1:ee089790cdbb 317 s_command.Address = BlockAddress;
bcostm 1:ee089790cdbb 318 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 1:ee089790cdbb 319 s_command.DataMode = QSPI_DATA_NONE;
bcostm 1:ee089790cdbb 320 s_command.DummyCycles = 0;
bcostm 1:ee089790cdbb 321 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 1:ee089790cdbb 322 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 1:ee089790cdbb 323 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 1:ee089790cdbb 324
bcostm 1:ee089790cdbb 325 /* Enable write operations */
bcostm 1:ee089790cdbb 326 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 1:ee089790cdbb 327 {
bcostm 1:ee089790cdbb 328 return QSPI_ERROR;
bcostm 1:ee089790cdbb 329 }
bcostm 1:ee089790cdbb 330
bcostm 1:ee089790cdbb 331 /* Send the command */
bcostm 1:ee089790cdbb 332 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 333 {
bcostm 1:ee089790cdbb 334 return QSPI_ERROR;
bcostm 1:ee089790cdbb 335 }
bcostm 1:ee089790cdbb 336
bcostm 1:ee089790cdbb 337 /* Configure automatic polling mode to wait for end of erase */
bcostm 1:ee089790cdbb 338 if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_SUBSECTOR_ERASE_MAX_TIME) != QSPI_OK)
bcostm 1:ee089790cdbb 339 {
bcostm 1:ee089790cdbb 340 return QSPI_ERROR;
bcostm 1:ee089790cdbb 341 }
bcostm 1:ee089790cdbb 342
bcostm 1:ee089790cdbb 343 return QSPI_OK;
bcostm 1:ee089790cdbb 344 }
bcostm 1:ee089790cdbb 345
bcostm 1:ee089790cdbb 346 /**
bcostm 1:ee089790cdbb 347 * @brief Erases the entire QSPI memory.
bcostm 1:ee089790cdbb 348 * @retval QSPI memory status
bcostm 1:ee089790cdbb 349 */
bcostm 1:ee089790cdbb 350 uint8_t BSP_QSPI_Erase_Chip(void)
bcostm 1:ee089790cdbb 351 {
bcostm 1:ee089790cdbb 352 QSPI_CommandTypeDef s_command;
bcostm 1:ee089790cdbb 353
bcostm 1:ee089790cdbb 354 /* Initialize the erase command */
bcostm 1:ee089790cdbb 355 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 1:ee089790cdbb 356 s_command.Instruction = BULK_ERASE_CMD;
bcostm 1:ee089790cdbb 357 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 1:ee089790cdbb 358 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 1:ee089790cdbb 359 s_command.DataMode = QSPI_DATA_NONE;
bcostm 1:ee089790cdbb 360 s_command.DummyCycles = 0;
bcostm 1:ee089790cdbb 361 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 1:ee089790cdbb 362 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 1:ee089790cdbb 363 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 1:ee089790cdbb 364
bcostm 1:ee089790cdbb 365 /* Enable write operations */
bcostm 1:ee089790cdbb 366 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 1:ee089790cdbb 367 {
bcostm 1:ee089790cdbb 368 return QSPI_ERROR;
bcostm 1:ee089790cdbb 369 }
bcostm 1:ee089790cdbb 370
bcostm 1:ee089790cdbb 371 /* Send the command */
bcostm 1:ee089790cdbb 372 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 373 {
bcostm 1:ee089790cdbb 374 return QSPI_ERROR;
bcostm 1:ee089790cdbb 375 }
bcostm 1:ee089790cdbb 376
bcostm 1:ee089790cdbb 377 /* Configure automatic polling mode to wait for end of erase */
bcostm 1:ee089790cdbb 378 if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_BULK_ERASE_MAX_TIME) != QSPI_OK)
bcostm 1:ee089790cdbb 379 {
bcostm 1:ee089790cdbb 380 return QSPI_ERROR;
bcostm 1:ee089790cdbb 381 }
bcostm 1:ee089790cdbb 382
bcostm 1:ee089790cdbb 383 return QSPI_OK;
bcostm 1:ee089790cdbb 384 }
bcostm 1:ee089790cdbb 385
bcostm 1:ee089790cdbb 386 /**
bcostm 1:ee089790cdbb 387 * @brief Reads current status of the QSPI memory.
bcostm 1:ee089790cdbb 388 * @retval QSPI memory status
bcostm 1:ee089790cdbb 389 */
bcostm 1:ee089790cdbb 390 uint8_t BSP_QSPI_GetStatus(void)
bcostm 1:ee089790cdbb 391 {
bcostm 1:ee089790cdbb 392 QSPI_CommandTypeDef s_command;
bcostm 1:ee089790cdbb 393 uint8_t reg;
bcostm 1:ee089790cdbb 394
bcostm 1:ee089790cdbb 395 /* Initialize the read flag status register command */
bcostm 1:ee089790cdbb 396 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 1:ee089790cdbb 397 s_command.Instruction = READ_FLAG_STATUS_REG_CMD;
bcostm 1:ee089790cdbb 398 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 1:ee089790cdbb 399 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 1:ee089790cdbb 400 s_command.DataMode = QSPI_DATA_1_LINE;
bcostm 1:ee089790cdbb 401 s_command.DummyCycles = 0;
bcostm 1:ee089790cdbb 402 s_command.NbData = 1;
bcostm 1:ee089790cdbb 403 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 1:ee089790cdbb 404 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 1:ee089790cdbb 405 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 1:ee089790cdbb 406
bcostm 1:ee089790cdbb 407 /* Configure the command */
bcostm 1:ee089790cdbb 408 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 409 {
bcostm 1:ee089790cdbb 410 return QSPI_ERROR;
bcostm 1:ee089790cdbb 411 }
bcostm 1:ee089790cdbb 412
bcostm 1:ee089790cdbb 413 /* Reception of the data */
bcostm 1:ee089790cdbb 414 if (HAL_QSPI_Receive(&QSPIHandle, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 415 {
bcostm 1:ee089790cdbb 416 return QSPI_ERROR;
bcostm 1:ee089790cdbb 417 }
bcostm 1:ee089790cdbb 418
bcostm 1:ee089790cdbb 419 /* Check the value of the register */
bcostm 1:ee089790cdbb 420 if ((reg & (N25Q128A_FSR_PRERR | N25Q128A_FSR_VPPERR | N25Q128A_FSR_PGERR | N25Q128A_FSR_ERERR)) != 0)
bcostm 1:ee089790cdbb 421 {
bcostm 1:ee089790cdbb 422 return QSPI_ERROR;
bcostm 1:ee089790cdbb 423 }
bcostm 1:ee089790cdbb 424 else if ((reg & (N25Q128A_FSR_PGSUS | N25Q128A_FSR_ERSUS)) != 0)
bcostm 1:ee089790cdbb 425 {
bcostm 1:ee089790cdbb 426 return QSPI_SUSPENDED;
bcostm 1:ee089790cdbb 427 }
bcostm 1:ee089790cdbb 428 else if ((reg & N25Q128A_FSR_READY) != 0)
bcostm 1:ee089790cdbb 429 {
bcostm 1:ee089790cdbb 430 return QSPI_OK;
bcostm 1:ee089790cdbb 431 }
bcostm 1:ee089790cdbb 432 else
bcostm 1:ee089790cdbb 433 {
bcostm 1:ee089790cdbb 434 return QSPI_BUSY;
bcostm 1:ee089790cdbb 435 }
bcostm 1:ee089790cdbb 436 }
bcostm 1:ee089790cdbb 437
bcostm 1:ee089790cdbb 438 /**
bcostm 1:ee089790cdbb 439 * @brief Return the configuration of the QSPI memory.
bcostm 1:ee089790cdbb 440 * @param pInfo: pointer on the configuration structure
bcostm 1:ee089790cdbb 441 * @retval QSPI memory status
bcostm 1:ee089790cdbb 442 */
bcostm 1:ee089790cdbb 443 uint8_t BSP_QSPI_GetInfo(QSPI_Info* pInfo)
bcostm 1:ee089790cdbb 444 {
bcostm 1:ee089790cdbb 445 /* Configure the structure with the memory configuration */
bcostm 1:ee089790cdbb 446 pInfo->FlashSize = N25Q128A_FLASH_SIZE;
bcostm 1:ee089790cdbb 447 pInfo->EraseSectorSize = N25Q128A_SUBSECTOR_SIZE;
bcostm 1:ee089790cdbb 448 pInfo->EraseSectorsNumber = (N25Q128A_FLASH_SIZE/N25Q128A_SUBSECTOR_SIZE);
bcostm 1:ee089790cdbb 449 pInfo->ProgPageSize = N25Q128A_PAGE_SIZE;
bcostm 1:ee089790cdbb 450 pInfo->ProgPagesNumber = (N25Q128A_FLASH_SIZE/N25Q128A_PAGE_SIZE);
bcostm 1:ee089790cdbb 451
bcostm 1:ee089790cdbb 452 return QSPI_OK;
bcostm 1:ee089790cdbb 453 }
bcostm 1:ee089790cdbb 454
bcostm 1:ee089790cdbb 455 /**
bcostm 1:ee089790cdbb 456 * @brief Configure the QSPI in memory-mapped mode
bcostm 1:ee089790cdbb 457 * @retval QSPI memory status
bcostm 1:ee089790cdbb 458 */
bcostm 1:ee089790cdbb 459 uint8_t BSP_QSPI_MemoryMappedMode(void)
bcostm 1:ee089790cdbb 460 {
bcostm 1:ee089790cdbb 461 QSPI_CommandTypeDef s_command;
bcostm 1:ee089790cdbb 462 QSPI_MemoryMappedTypeDef s_mem_mapped_cfg;
bcostm 1:ee089790cdbb 463
bcostm 1:ee089790cdbb 464 /* Configure the command for the read instruction */
bcostm 1:ee089790cdbb 465 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 1:ee089790cdbb 466 s_command.Instruction = QUAD_INOUT_FAST_READ_CMD;
bcostm 1:ee089790cdbb 467 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
bcostm 1:ee089790cdbb 468 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 1:ee089790cdbb 469 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 1:ee089790cdbb 470 s_command.DataMode = QSPI_DATA_4_LINES;
bcostm 1:ee089790cdbb 471 s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD;
bcostm 1:ee089790cdbb 472 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 1:ee089790cdbb 473 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 1:ee089790cdbb 474 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 1:ee089790cdbb 475
bcostm 1:ee089790cdbb 476 /* Configure the memory mapped mode */
bcostm 1:ee089790cdbb 477 s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_ENABLE;
bcostm 1:ee089790cdbb 478 s_mem_mapped_cfg.TimeOutPeriod = 1;
bcostm 1:ee089790cdbb 479
bcostm 1:ee089790cdbb 480 if (HAL_QSPI_MemoryMapped(&QSPIHandle, &s_command, &s_mem_mapped_cfg) != HAL_OK)
bcostm 1:ee089790cdbb 481 {
bcostm 1:ee089790cdbb 482 return QSPI_ERROR;
bcostm 1:ee089790cdbb 483 }
bcostm 1:ee089790cdbb 484
bcostm 1:ee089790cdbb 485 return QSPI_OK;
bcostm 1:ee089790cdbb 486 }
bcostm 1:ee089790cdbb 487
bcostm 1:ee089790cdbb 488 /**
bcostm 1:ee089790cdbb 489 * @}
bcostm 1:ee089790cdbb 490 */
bcostm 1:ee089790cdbb 491
bcostm 1:ee089790cdbb 492 /** @addtogroup STM32746G_DISCOVERY_QSPI_Private_Functions
bcostm 1:ee089790cdbb 493 * @{
bcostm 1:ee089790cdbb 494 */
bcostm 1:ee089790cdbb 495
bcostm 1:ee089790cdbb 496 /**
bcostm 1:ee089790cdbb 497 * @brief QSPI MSP Initialization
bcostm 1:ee089790cdbb 498 * This function configures the hardware resources used in this example:
bcostm 1:ee089790cdbb 499 * - Peripheral's clock enable
bcostm 1:ee089790cdbb 500 * - Peripheral's GPIO Configuration
bcostm 1:ee089790cdbb 501 * - NVIC configuration for QSPI interrupt
bcostm 1:ee089790cdbb 502 * @retval None
bcostm 1:ee089790cdbb 503 */
bcostm 1:ee089790cdbb 504 __weak void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params)
bcostm 1:ee089790cdbb 505 {
bcostm 1:ee089790cdbb 506 GPIO_InitTypeDef gpio_init_structure;
bcostm 1:ee089790cdbb 507
bcostm 1:ee089790cdbb 508 /*##-1- Enable peripherals and GPIO Clocks #################################*/
bcostm 1:ee089790cdbb 509 /* Enable the QuadSPI memory interface clock */
bcostm 1:ee089790cdbb 510 QSPI_CLK_ENABLE();
bcostm 1:ee089790cdbb 511 /* Reset the QuadSPI memory interface */
bcostm 1:ee089790cdbb 512 QSPI_FORCE_RESET();
bcostm 1:ee089790cdbb 513 QSPI_RELEASE_RESET();
bcostm 1:ee089790cdbb 514 /* Enable GPIO clocks */
bcostm 1:ee089790cdbb 515 QSPI_CS_GPIO_CLK_ENABLE();
bcostm 1:ee089790cdbb 516 QSPI_CLK_GPIO_CLK_ENABLE();
bcostm 1:ee089790cdbb 517 QSPI_D0_GPIO_CLK_ENABLE();
bcostm 1:ee089790cdbb 518 QSPI_D1_GPIO_CLK_ENABLE();
bcostm 1:ee089790cdbb 519 QSPI_D2_GPIO_CLK_ENABLE();
bcostm 1:ee089790cdbb 520 QSPI_D3_GPIO_CLK_ENABLE();
bcostm 1:ee089790cdbb 521
bcostm 1:ee089790cdbb 522 /*##-2- Configure peripheral GPIO ##########################################*/
bcostm 1:ee089790cdbb 523 /* QSPI CS GPIO pin configuration */
bcostm 1:ee089790cdbb 524 gpio_init_structure.Pin = QSPI_CS_PIN;
bcostm 1:ee089790cdbb 525 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
bcostm 1:ee089790cdbb 526 gpio_init_structure.Pull = GPIO_PULLUP;
bcostm 1:ee089790cdbb 527 gpio_init_structure.Speed = GPIO_SPEED_HIGH;
bcostm 1:ee089790cdbb 528 gpio_init_structure.Alternate = GPIO_AF10_QUADSPI;
bcostm 1:ee089790cdbb 529 HAL_GPIO_Init(QSPI_CS_GPIO_PORT, &gpio_init_structure);
bcostm 1:ee089790cdbb 530
bcostm 1:ee089790cdbb 531 /* QSPI CLK GPIO pin configuration */
bcostm 1:ee089790cdbb 532 gpio_init_structure.Pin = QSPI_CLK_PIN;
bcostm 1:ee089790cdbb 533 gpio_init_structure.Pull = GPIO_NOPULL;
bcostm 1:ee089790cdbb 534 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
bcostm 1:ee089790cdbb 535 HAL_GPIO_Init(QSPI_CLK_GPIO_PORT, &gpio_init_structure);
bcostm 1:ee089790cdbb 536
bcostm 1:ee089790cdbb 537 /* QSPI D0 GPIO pin configuration */
bcostm 1:ee089790cdbb 538 gpio_init_structure.Pin = QSPI_D0_PIN;
bcostm 1:ee089790cdbb 539 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
bcostm 1:ee089790cdbb 540 HAL_GPIO_Init(QSPI_D0_GPIO_PORT, &gpio_init_structure);
bcostm 1:ee089790cdbb 541
bcostm 1:ee089790cdbb 542 /* QSPI D1 GPIO pin configuration */
bcostm 1:ee089790cdbb 543 gpio_init_structure.Pin = QSPI_D1_PIN;
bcostm 1:ee089790cdbb 544 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
bcostm 1:ee089790cdbb 545 HAL_GPIO_Init(QSPI_D1_GPIO_PORT, &gpio_init_structure);
bcostm 1:ee089790cdbb 546
bcostm 1:ee089790cdbb 547 /* QSPI D2 GPIO pin configuration */
bcostm 1:ee089790cdbb 548 gpio_init_structure.Pin = QSPI_D2_PIN;
bcostm 1:ee089790cdbb 549 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
bcostm 1:ee089790cdbb 550 HAL_GPIO_Init(QSPI_D2_GPIO_PORT, &gpio_init_structure);
bcostm 1:ee089790cdbb 551
bcostm 1:ee089790cdbb 552 /* QSPI D3 GPIO pin configuration */
bcostm 1:ee089790cdbb 553 gpio_init_structure.Pin = QSPI_D3_PIN;
bcostm 1:ee089790cdbb 554 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
bcostm 1:ee089790cdbb 555 HAL_GPIO_Init(QSPI_D3_GPIO_PORT, &gpio_init_structure);
bcostm 1:ee089790cdbb 556
bcostm 1:ee089790cdbb 557 /*##-3- Configure the NVIC for QSPI #########################################*/
bcostm 1:ee089790cdbb 558 /* NVIC configuration for QSPI interrupt */
bcostm 1:ee089790cdbb 559 HAL_NVIC_SetPriority(QUADSPI_IRQn, 0x0F, 0);
bcostm 1:ee089790cdbb 560 HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
bcostm 1:ee089790cdbb 561 }
bcostm 1:ee089790cdbb 562
bcostm 1:ee089790cdbb 563 /**
bcostm 1:ee089790cdbb 564 * @brief QSPI MSP De-Initialization
bcostm 1:ee089790cdbb 565 * This function frees the hardware resources used in this example:
bcostm 1:ee089790cdbb 566 * - Disable the Peripheral's clock
bcostm 1:ee089790cdbb 567 * - Revert GPIO and NVIC configuration to their default state
bcostm 1:ee089790cdbb 568 * @retval None
bcostm 1:ee089790cdbb 569 */
bcostm 1:ee089790cdbb 570 __weak void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params)
bcostm 1:ee089790cdbb 571 {
bcostm 1:ee089790cdbb 572 /*##-1- Disable the NVIC for QSPI ###########################################*/
bcostm 1:ee089790cdbb 573 HAL_NVIC_DisableIRQ(QUADSPI_IRQn);
bcostm 1:ee089790cdbb 574
bcostm 1:ee089790cdbb 575 /*##-2- Disable peripherals and GPIO Clocks ################################*/
bcostm 1:ee089790cdbb 576 /* De-Configure QSPI pins */
bcostm 1:ee089790cdbb 577 HAL_GPIO_DeInit(QSPI_CS_GPIO_PORT, QSPI_CS_PIN);
bcostm 1:ee089790cdbb 578 HAL_GPIO_DeInit(QSPI_CLK_GPIO_PORT, QSPI_CLK_PIN);
bcostm 1:ee089790cdbb 579 HAL_GPIO_DeInit(QSPI_D0_GPIO_PORT, QSPI_D0_PIN);
bcostm 1:ee089790cdbb 580 HAL_GPIO_DeInit(QSPI_D1_GPIO_PORT, QSPI_D1_PIN);
bcostm 1:ee089790cdbb 581 HAL_GPIO_DeInit(QSPI_D2_GPIO_PORT, QSPI_D2_PIN);
bcostm 1:ee089790cdbb 582 HAL_GPIO_DeInit(QSPI_D3_GPIO_PORT, QSPI_D3_PIN);
bcostm 1:ee089790cdbb 583
bcostm 1:ee089790cdbb 584 /*##-3- Reset peripherals ##################################################*/
bcostm 1:ee089790cdbb 585 /* Reset the QuadSPI memory interface */
bcostm 1:ee089790cdbb 586 QSPI_FORCE_RESET();
bcostm 1:ee089790cdbb 587 QSPI_RELEASE_RESET();
bcostm 1:ee089790cdbb 588
bcostm 1:ee089790cdbb 589 /* Disable the QuadSPI memory interface clock */
bcostm 1:ee089790cdbb 590 QSPI_CLK_DISABLE();
bcostm 1:ee089790cdbb 591 }
bcostm 1:ee089790cdbb 592
bcostm 1:ee089790cdbb 593 /**
bcostm 1:ee089790cdbb 594 * @brief This function reset the QSPI memory.
bcostm 1:ee089790cdbb 595 * @param hqspi: QSPI handle
bcostm 1:ee089790cdbb 596 * @retval None
bcostm 1:ee089790cdbb 597 */
bcostm 1:ee089790cdbb 598 static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi)
bcostm 1:ee089790cdbb 599 {
bcostm 1:ee089790cdbb 600 QSPI_CommandTypeDef s_command;
bcostm 1:ee089790cdbb 601
bcostm 1:ee089790cdbb 602 /* Initialize the reset enable command */
bcostm 1:ee089790cdbb 603 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 1:ee089790cdbb 604 s_command.Instruction = RESET_ENABLE_CMD;
bcostm 1:ee089790cdbb 605 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 1:ee089790cdbb 606 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 1:ee089790cdbb 607 s_command.DataMode = QSPI_DATA_NONE;
bcostm 1:ee089790cdbb 608 s_command.DummyCycles = 0;
bcostm 1:ee089790cdbb 609 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 1:ee089790cdbb 610 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 1:ee089790cdbb 611 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 1:ee089790cdbb 612
bcostm 1:ee089790cdbb 613 /* Send the command */
bcostm 1:ee089790cdbb 614 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 615 {
bcostm 1:ee089790cdbb 616 return QSPI_ERROR;
bcostm 1:ee089790cdbb 617 }
bcostm 1:ee089790cdbb 618
bcostm 1:ee089790cdbb 619 /* Send the reset memory command */
bcostm 1:ee089790cdbb 620 s_command.Instruction = RESET_MEMORY_CMD;
bcostm 1:ee089790cdbb 621 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 622 {
bcostm 1:ee089790cdbb 623 return QSPI_ERROR;
bcostm 1:ee089790cdbb 624 }
bcostm 1:ee089790cdbb 625
bcostm 1:ee089790cdbb 626 /* Configure automatic polling mode to wait the memory is ready */
bcostm 1:ee089790cdbb 627 if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
bcostm 1:ee089790cdbb 628 {
bcostm 1:ee089790cdbb 629 return QSPI_ERROR;
bcostm 1:ee089790cdbb 630 }
bcostm 1:ee089790cdbb 631
bcostm 1:ee089790cdbb 632 return QSPI_OK;
bcostm 1:ee089790cdbb 633 }
bcostm 1:ee089790cdbb 634
bcostm 1:ee089790cdbb 635 /**
bcostm 1:ee089790cdbb 636 * @brief This function configure the dummy cycles on memory side.
bcostm 1:ee089790cdbb 637 * @param hqspi: QSPI handle
bcostm 1:ee089790cdbb 638 * @retval None
bcostm 1:ee089790cdbb 639 */
bcostm 1:ee089790cdbb 640 static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi)
bcostm 1:ee089790cdbb 641 {
bcostm 1:ee089790cdbb 642 QSPI_CommandTypeDef s_command;
bcostm 1:ee089790cdbb 643 uint8_t reg;
bcostm 1:ee089790cdbb 644
bcostm 1:ee089790cdbb 645 /* Initialize the read volatile configuration register command */
bcostm 1:ee089790cdbb 646 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 1:ee089790cdbb 647 s_command.Instruction = READ_VOL_CFG_REG_CMD;
bcostm 1:ee089790cdbb 648 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 1:ee089790cdbb 649 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 1:ee089790cdbb 650 s_command.DataMode = QSPI_DATA_1_LINE;
bcostm 1:ee089790cdbb 651 s_command.DummyCycles = 0;
bcostm 1:ee089790cdbb 652 s_command.NbData = 1;
bcostm 1:ee089790cdbb 653 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 1:ee089790cdbb 654 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 1:ee089790cdbb 655 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 1:ee089790cdbb 656
bcostm 1:ee089790cdbb 657 /* Configure the command */
bcostm 1:ee089790cdbb 658 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 659 {
bcostm 1:ee089790cdbb 660 return QSPI_ERROR;
bcostm 1:ee089790cdbb 661 }
bcostm 1:ee089790cdbb 662
bcostm 1:ee089790cdbb 663 /* Reception of the data */
bcostm 1:ee089790cdbb 664 if (HAL_QSPI_Receive(hqspi, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 665 {
bcostm 1:ee089790cdbb 666 return QSPI_ERROR;
bcostm 1:ee089790cdbb 667 }
bcostm 1:ee089790cdbb 668
bcostm 1:ee089790cdbb 669 /* Enable write operations */
bcostm 1:ee089790cdbb 670 if (QSPI_WriteEnable(hqspi) != QSPI_OK)
bcostm 1:ee089790cdbb 671 {
bcostm 1:ee089790cdbb 672 return QSPI_ERROR;
bcostm 1:ee089790cdbb 673 }
bcostm 1:ee089790cdbb 674
bcostm 1:ee089790cdbb 675 /* Update volatile configuration register (with new dummy cycles) */
bcostm 1:ee089790cdbb 676 s_command.Instruction = WRITE_VOL_CFG_REG_CMD;
bcostm 1:ee089790cdbb 677 MODIFY_REG(reg, N25Q128A_VCR_NB_DUMMY, (N25Q128A_DUMMY_CYCLES_READ_QUAD << POSITION_VAL(N25Q128A_VCR_NB_DUMMY)));
bcostm 1:ee089790cdbb 678
bcostm 1:ee089790cdbb 679 /* Configure the write volatile configuration register command */
bcostm 1:ee089790cdbb 680 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 681 {
bcostm 1:ee089790cdbb 682 return QSPI_ERROR;
bcostm 1:ee089790cdbb 683 }
bcostm 1:ee089790cdbb 684
bcostm 1:ee089790cdbb 685 /* Transmission of the data */
bcostm 1:ee089790cdbb 686 if (HAL_QSPI_Transmit(hqspi, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 687 {
bcostm 1:ee089790cdbb 688 return QSPI_ERROR;
bcostm 1:ee089790cdbb 689 }
bcostm 1:ee089790cdbb 690
bcostm 1:ee089790cdbb 691 return QSPI_OK;
bcostm 1:ee089790cdbb 692 }
bcostm 1:ee089790cdbb 693
bcostm 1:ee089790cdbb 694 /**
bcostm 1:ee089790cdbb 695 * @brief This function send a Write Enable and wait it is effective.
bcostm 1:ee089790cdbb 696 * @param hqspi: QSPI handle
bcostm 1:ee089790cdbb 697 * @retval None
bcostm 1:ee089790cdbb 698 */
bcostm 1:ee089790cdbb 699 static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi)
bcostm 1:ee089790cdbb 700 {
bcostm 1:ee089790cdbb 701 QSPI_CommandTypeDef s_command;
bcostm 1:ee089790cdbb 702 QSPI_AutoPollingTypeDef s_config;
bcostm 1:ee089790cdbb 703
bcostm 1:ee089790cdbb 704 /* Enable write operations */
bcostm 1:ee089790cdbb 705 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 1:ee089790cdbb 706 s_command.Instruction = WRITE_ENABLE_CMD;
bcostm 1:ee089790cdbb 707 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 1:ee089790cdbb 708 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 1:ee089790cdbb 709 s_command.DataMode = QSPI_DATA_NONE;
bcostm 1:ee089790cdbb 710 s_command.DummyCycles = 0;
bcostm 1:ee089790cdbb 711 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 1:ee089790cdbb 712 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 1:ee089790cdbb 713 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 1:ee089790cdbb 714
bcostm 1:ee089790cdbb 715 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 716 {
bcostm 1:ee089790cdbb 717 return QSPI_ERROR;
bcostm 1:ee089790cdbb 718 }
bcostm 1:ee089790cdbb 719
bcostm 1:ee089790cdbb 720 /* Configure automatic polling mode to wait for write enabling */
bcostm 1:ee089790cdbb 721 s_config.Match = N25Q128A_SR_WREN;
bcostm 1:ee089790cdbb 722 s_config.Mask = N25Q128A_SR_WREN;
bcostm 1:ee089790cdbb 723 s_config.MatchMode = QSPI_MATCH_MODE_AND;
bcostm 1:ee089790cdbb 724 s_config.StatusBytesSize = 1;
bcostm 1:ee089790cdbb 725 s_config.Interval = 0x10;
bcostm 1:ee089790cdbb 726 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
bcostm 1:ee089790cdbb 727
bcostm 1:ee089790cdbb 728 s_command.Instruction = READ_STATUS_REG_CMD;
bcostm 1:ee089790cdbb 729 s_command.DataMode = QSPI_DATA_1_LINE;
bcostm 1:ee089790cdbb 730
bcostm 1:ee089790cdbb 731 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 1:ee089790cdbb 732 {
bcostm 1:ee089790cdbb 733 return QSPI_ERROR;
bcostm 1:ee089790cdbb 734 }
bcostm 1:ee089790cdbb 735
bcostm 1:ee089790cdbb 736 return QSPI_OK;
bcostm 1:ee089790cdbb 737 }
bcostm 1:ee089790cdbb 738
bcostm 1:ee089790cdbb 739 /**
bcostm 1:ee089790cdbb 740 * @brief This function read the SR of the memory and wait the EOP.
bcostm 1:ee089790cdbb 741 * @param hqspi: QSPI handle
bcostm 1:ee089790cdbb 742 * @param Timeout
bcostm 1:ee089790cdbb 743 * @retval None
bcostm 1:ee089790cdbb 744 */
bcostm 1:ee089790cdbb 745 static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
bcostm 1:ee089790cdbb 746 {
bcostm 1:ee089790cdbb 747 QSPI_CommandTypeDef s_command;
bcostm 1:ee089790cdbb 748 QSPI_AutoPollingTypeDef s_config;
bcostm 1:ee089790cdbb 749
bcostm 1:ee089790cdbb 750 /* Configure automatic polling mode to wait for memory ready */
bcostm 1:ee089790cdbb 751 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 1:ee089790cdbb 752 s_command.Instruction = READ_STATUS_REG_CMD;
bcostm 1:ee089790cdbb 753 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 1:ee089790cdbb 754 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 1:ee089790cdbb 755 s_command.DataMode = QSPI_DATA_1_LINE;
bcostm 1:ee089790cdbb 756 s_command.DummyCycles = 0;
bcostm 1:ee089790cdbb 757 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 1:ee089790cdbb 758 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 1:ee089790cdbb 759 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 1:ee089790cdbb 760
bcostm 1:ee089790cdbb 761 s_config.Match = 0;
bcostm 1:ee089790cdbb 762 s_config.Mask = N25Q128A_SR_WIP;
bcostm 1:ee089790cdbb 763 s_config.MatchMode = QSPI_MATCH_MODE_AND;
bcostm 1:ee089790cdbb 764 s_config.StatusBytesSize = 1;
bcostm 1:ee089790cdbb 765 s_config.Interval = 0x10;
bcostm 1:ee089790cdbb 766 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
bcostm 1:ee089790cdbb 767
bcostm 1:ee089790cdbb 768 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK)
bcostm 1:ee089790cdbb 769 {
bcostm 1:ee089790cdbb 770 return QSPI_ERROR;
bcostm 1:ee089790cdbb 771 }
bcostm 1:ee089790cdbb 772
bcostm 1:ee089790cdbb 773 return QSPI_OK;
bcostm 1:ee089790cdbb 774 }
bcostm 1:ee089790cdbb 775 /**
bcostm 1:ee089790cdbb 776 * @}
bcostm 1:ee089790cdbb 777 */
bcostm 1:ee089790cdbb 778
bcostm 1:ee089790cdbb 779 /**
bcostm 1:ee089790cdbb 780 * @}
bcostm 1:ee089790cdbb 781 */
bcostm 1:ee089790cdbb 782
bcostm 1:ee089790cdbb 783 /**
bcostm 1:ee089790cdbb 784 * @}
bcostm 1:ee089790cdbb 785 */
bcostm 1:ee089790cdbb 786
bcostm 1:ee089790cdbb 787 /**
bcostm 1:ee089790cdbb 788 * @}
bcostm 1:ee089790cdbb 789 */
bcostm 1:ee089790cdbb 790
bcostm 1:ee089790cdbb 791 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bcostm 1:ee089790cdbb 792