Tomo Yamanaka / mbed-dev

mbed library sources. Supersedes mbed-src. GR-PEACH runs on RAM.

Fork of mbed-dev by mbed official

Files at this revision

API Documentation at this revision

Revision 73:5d67568caa8f, committed 2016-02-26

Comitter:
mbed_official
Date:
Fri Feb 26 07:45:09 2016 +0000
Parent:
72:ad655cb9b50e
Child:
74:9322579e4309
Commit message:
Synchronized with git revision c00b00481f4c41773546719e3ecc7615fc4b2732

Full URL: https://github.com/mbedmicro/mbed/commit/c00b00481f4c41773546719e3ecc7615fc4b2732/

[LPC1549] Improve AnalogIn Performance

Changed in this revision

targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c Show annotated file Show diff for this revision Revisions of this file 
--- a/targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c	Thu Feb 25 10:15:11 2016 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c	Fri Feb 26 07:45:09 2016 +0000
@@ -77,10 +77,6 @@
         LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 28);
     }
 
-    // select IRC as asynchronous clock, divided by 1
-    LPC_SYSCON->ADCASYNCCLKSEL  = 0;
-    LPC_SYSCON->ADCASYNCCLKDIV  = 1;
-
     __IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
 
     // determine the system clock divider for a 500kHz ADC clock during calibration
@@ -90,8 +86,8 @@
     adc_reg->CTRL = (1UL << 30) | (clkdiv & 0xFF);
     while ((adc_reg->CTRL & (1UL << 30)) != 0);
 
-    // switch to asynchronous mode
-    adc_reg->CTRL = (1UL << 8);
+    // Sampling clock: SystemClock divided by 1
+    adc_reg->CTRL = 0;
 }
 
 static inline uint32_t adc_read(analogin_t *obj) {