Tomo Yamanaka / mbed-dev

mbed library sources. Supersedes mbed-src. GR-PEACH runs on RAM.

Fork of mbed-dev by mbed official

targets/hal/TARGET_STM/TARGET_STM32F1/pinmap.c@103:493a29d2d4d7, 2016-03-30 (annotated)

Committer:
1050186
Date:
Wed Mar 30 11:41:25 2016 +0000
Revision:
103:493a29d2d4d7
Parent:
0:9b334a45a8ff 
GR-PEACH runs on RAM.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 *******************************************************************************
bogdanm 0:9b334a45a8ff 3 * Copyright (c) 2014, STMicroelectronics
bogdanm 0:9b334a45a8ff 4 * All rights reserved.
bogdanm 0:9b334a45a8ff 5 *
bogdanm 0:9b334a45a8ff 6 * Redistribution and use in source and binary forms, with or without
bogdanm 0:9b334a45a8ff 7 * modification, are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 10 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 12 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 13 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 15 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 16 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 17 *
bogdanm 0:9b334a45a8ff 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 28 *******************************************************************************
bogdanm 0:9b334a45a8ff 29 */
bogdanm 0:9b334a45a8ff 30 #include "mbed_assert.h"
bogdanm 0:9b334a45a8ff 31 #include "pinmap.h"
bogdanm 0:9b334a45a8ff 32 #include "PortNames.h"
bogdanm 0:9b334a45a8ff 33 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 // GPIO mode look-up table
bogdanm 0:9b334a45a8ff 36 // Warning: the elements order must be the same as the one defined in PinNames.h
bogdanm 0:9b334a45a8ff 37 static const uint32_t gpio_mode[13] = {
bogdanm 0:9b334a45a8ff 38 GPIO_MODE_INPUT, // 0 = STM_MODE_INPUT
bogdanm 0:9b334a45a8ff 39 GPIO_MODE_OUTPUT_PP, // 1 = STM_MODE_OUTPUT_PP
bogdanm 0:9b334a45a8ff 40 GPIO_MODE_OUTPUT_OD, // 2 = STM_MODE_OUTPUT_OD
bogdanm 0:9b334a45a8ff 41 GPIO_MODE_AF_PP, // 3 = STM_MODE_AF_PP
bogdanm 0:9b334a45a8ff 42 GPIO_MODE_AF_OD, // 4 = STM_MODE_AF_OD
bogdanm 0:9b334a45a8ff 43 GPIO_MODE_ANALOG, // 5 = STM_MODE_ANALOG
bogdanm 0:9b334a45a8ff 44 GPIO_MODE_IT_RISING, // 6 = STM_MODE_IT_RISING
bogdanm 0:9b334a45a8ff 45 GPIO_MODE_IT_FALLING, // 7 = STM_MODE_IT_FALLING
bogdanm 0:9b334a45a8ff 46 GPIO_MODE_IT_RISING_FALLING, // 8 = STM_MODE_IT_RISING_FALLING
bogdanm 0:9b334a45a8ff 47 GPIO_MODE_EVT_RISING, // 9 = STM_MODE_EVT_RISING
bogdanm 0:9b334a45a8ff 48 GPIO_MODE_EVT_FALLING, // 10 = STM_MODE_EVT_FALLING
bogdanm 0:9b334a45a8ff 49 GPIO_MODE_EVT_RISING_FALLING, // 11 = STM_MODE_EVT_RISING_FALLING
bogdanm 0:9b334a45a8ff 50 0x10000000 // 12 = STM_MODE_IT_EVT_RESET (not in STM32Cube HAL)
bogdanm 0:9b334a45a8ff 51 };
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 // Enable GPIO clock and return GPIO base address
bogdanm 0:9b334a45a8ff 54 uint32_t Set_GPIO_Clock(uint32_t port_idx)
bogdanm 0:9b334a45a8ff 55 {
bogdanm 0:9b334a45a8ff 56 uint32_t gpio_add = 0;
bogdanm 0:9b334a45a8ff 57 switch (port_idx) {
bogdanm 0:9b334a45a8ff 58 case PortA:
bogdanm 0:9b334a45a8ff 59 gpio_add = GPIOA_BASE;
bogdanm 0:9b334a45a8ff 60 __GPIOA_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 61 break;
bogdanm 0:9b334a45a8ff 62 case PortB:
bogdanm 0:9b334a45a8ff 63 gpio_add = GPIOB_BASE;
bogdanm 0:9b334a45a8ff 64 __GPIOB_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 65 break;
bogdanm 0:9b334a45a8ff 66 case PortC:
bogdanm 0:9b334a45a8ff 67 gpio_add = GPIOC_BASE;
bogdanm 0:9b334a45a8ff 68 __GPIOC_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 69 break;
bogdanm 0:9b334a45a8ff 70 case PortD:
bogdanm 0:9b334a45a8ff 71 gpio_add = GPIOD_BASE;
bogdanm 0:9b334a45a8ff 72 __GPIOD_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 73 break;
bogdanm 0:9b334a45a8ff 74 default:
bogdanm 0:9b334a45a8ff 75 error("Pinmap error: wrong port number.");
bogdanm 0:9b334a45a8ff 76 break;
bogdanm 0:9b334a45a8ff 77 }
bogdanm 0:9b334a45a8ff 78 return gpio_add;
bogdanm 0:9b334a45a8ff 79 }
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 /**
bogdanm 0:9b334a45a8ff 82 * Configure pin (input, output, alternate function or analog) + output speed + AF
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84 void pin_function(PinName pin, int data)
bogdanm 0:9b334a45a8ff 85 {
bogdanm 0:9b334a45a8ff 86 MBED_ASSERT(pin != (PinName)NC);
bogdanm 0:9b334a45a8ff 87 // Get the pin informations
bogdanm 0:9b334a45a8ff 88 uint32_t mode = STM_PIN_MODE(data);
bogdanm 0:9b334a45a8ff 89 uint32_t pupd = STM_PIN_PUPD(data);
bogdanm 0:9b334a45a8ff 90 uint32_t afnum = STM_PIN_AFNUM(data);
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 uint32_t port_index = STM_PORT(pin);
bogdanm 0:9b334a45a8ff 93 uint32_t pin_index = STM_PIN(pin);
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 // Enable GPIO clock
bogdanm 0:9b334a45a8ff 96 uint32_t gpio_add = Set_GPIO_Clock(port_index);
bogdanm 0:9b334a45a8ff 97 GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 // Enable AFIO clock
bogdanm 0:9b334a45a8ff 100 __HAL_RCC_AFIO_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 // Configure Alternate Function
bogdanm 0:9b334a45a8ff 103 // Warning: Must be done before the GPIO is initialized
bogdanm 0:9b334a45a8ff 104 if (afnum > 0) {
bogdanm 0:9b334a45a8ff 105 switch (afnum) {
bogdanm 0:9b334a45a8ff 106 case 1: // Remap SPI1
bogdanm 0:9b334a45a8ff 107 __HAL_AFIO_REMAP_SPI1_ENABLE();
bogdanm 0:9b334a45a8ff 108 break;
bogdanm 0:9b334a45a8ff 109 case 2: // Remap I2C1
bogdanm 0:9b334a45a8ff 110 __HAL_AFIO_REMAP_I2C1_ENABLE();
bogdanm 0:9b334a45a8ff 111 break;
bogdanm 0:9b334a45a8ff 112 case 3: // Remap USART1
bogdanm 0:9b334a45a8ff 113 __HAL_AFIO_REMAP_USART1_ENABLE();
bogdanm 0:9b334a45a8ff 114 break;
bogdanm 0:9b334a45a8ff 115 case 4: // Remap USART2
bogdanm 0:9b334a45a8ff 116 __HAL_AFIO_REMAP_USART2_ENABLE();
bogdanm 0:9b334a45a8ff 117 break;
bogdanm 0:9b334a45a8ff 118 case 5: // Partial Remap USART3
bogdanm 0:9b334a45a8ff 119 __HAL_AFIO_REMAP_USART3_PARTIAL();
bogdanm 0:9b334a45a8ff 120 break;
bogdanm 0:9b334a45a8ff 121 case 6: // Partial Remap TIM1
bogdanm 0:9b334a45a8ff 122 __HAL_AFIO_REMAP_TIM1_PARTIAL();
bogdanm 0:9b334a45a8ff 123 break;
bogdanm 0:9b334a45a8ff 124 case 7: // Partial Remap TIM3
bogdanm 0:9b334a45a8ff 125 __HAL_AFIO_REMAP_TIM3_PARTIAL();
bogdanm 0:9b334a45a8ff 126 break;
bogdanm 0:9b334a45a8ff 127 case 8: // Full Remap TIM2
bogdanm 0:9b334a45a8ff 128 __HAL_AFIO_REMAP_TIM2_ENABLE();
bogdanm 0:9b334a45a8ff 129 break;
bogdanm 0:9b334a45a8ff 130 case 9: // Full Remap TIM3
bogdanm 0:9b334a45a8ff 131 __HAL_AFIO_REMAP_TIM3_ENABLE();
bogdanm 0:9b334a45a8ff 132 break;
bogdanm 0:9b334a45a8ff 133 default:
bogdanm 0:9b334a45a8ff 134 break;
bogdanm 0:9b334a45a8ff 135 }
bogdanm 0:9b334a45a8ff 136 }
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 // Configure GPIO
bogdanm 0:9b334a45a8ff 139 GPIO_InitTypeDef GPIO_InitStructure;
bogdanm 0:9b334a45a8ff 140 GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index);
bogdanm 0:9b334a45a8ff 141 GPIO_InitStructure.Mode = gpio_mode[mode];
bogdanm 0:9b334a45a8ff 142 GPIO_InitStructure.Pull = pupd;
bogdanm 0:9b334a45a8ff 143 GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
bogdanm 0:9b334a45a8ff 144 HAL_GPIO_Init(gpio, &GPIO_InitStructure);
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 // Disconnect JTAG-DP + SW-DP signals.
bogdanm 0:9b334a45a8ff 147 // Warning: Need to reconnect under reset
bogdanm 0:9b334a45a8ff 148 if ((pin == PA_13) || (pin == PA_14)) {
bogdanm 0:9b334a45a8ff 149 __HAL_AFIO_REMAP_SWJ_DISABLE(); // JTAG-DP Disabled and SW-DP Disabled
bogdanm 0:9b334a45a8ff 150 }
bogdanm 0:9b334a45a8ff 151 if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
bogdanm 0:9b334a45a8ff 152 __HAL_AFIO_REMAP_SWJ_NOJTAG(); // JTAG-DP Disabled and SW-DP enabled
bogdanm 0:9b334a45a8ff 153 }
bogdanm 0:9b334a45a8ff 154 }
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 /**
bogdanm 0:9b334a45a8ff 157 * Configure pin pull-up/pull-down
bogdanm 0:9b334a45a8ff 158 */
bogdanm 0:9b334a45a8ff 159 void pin_mode(PinName pin, PinMode mode)
bogdanm 0:9b334a45a8ff 160 {
bogdanm 0:9b334a45a8ff 161 MBED_ASSERT(pin != (PinName)NC);
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 uint32_t port_index = STM_PORT(pin);
bogdanm 0:9b334a45a8ff 164 uint32_t pin_index = STM_PIN(pin);
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 // Enable GPIO clock
bogdanm 0:9b334a45a8ff 167 uint32_t gpio_add = Set_GPIO_Clock(port_index);
bogdanm 0:9b334a45a8ff 168 GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 // Configure open-drain and pull-up/down
bogdanm 0:9b334a45a8ff 171 switch (mode) {
bogdanm 0:9b334a45a8ff 172 case PullNone:
bogdanm 0:9b334a45a8ff 173 break;
bogdanm 0:9b334a45a8ff 174 case PullUp:
bogdanm 0:9b334a45a8ff 175 case PullDown:
bogdanm 0:9b334a45a8ff 176 // Set pull-up / pull-down for Input mode
bogdanm 0:9b334a45a8ff 177 if (pin_index < 8) {
bogdanm 0:9b334a45a8ff 178 if ((gpio->CRL & (0x03 << (pin_index * 4))) == 0) { // MODE bits = Input mode
bogdanm 0:9b334a45a8ff 179 gpio->CRL |= (0x08 << (pin_index * 4)); // Set pull-up / pull-down
bogdanm 0:9b334a45a8ff 180 gpio->CRL &= ~(0x08 << ((pin_index * 4)-1)); // ENSURES GPIOx_CRL.CNFx.bit0 = 0
bogdanm 0:9b334a45a8ff 181 }
bogdanm 0:9b334a45a8ff 182 } else {
bogdanm 0:9b334a45a8ff 183 if ((gpio->CRH & (0x03 << ((pin_index % 8) * 4))) == 0) { // MODE bits = Input mode
bogdanm 0:9b334a45a8ff 184 gpio->CRH |= (0x08 << ((pin_index % 8) * 4)); // Set pull-up / pull-down
bogdanm 0:9b334a45a8ff 185 gpio->CRH &= ~(0x08 << (((pin_index % 8) * 4)-1)); // ENSURES GPIOx_CRH.CNFx.bit0 = 0
bogdanm 0:9b334a45a8ff 186 }
bogdanm 0:9b334a45a8ff 187 }
bogdanm 0:9b334a45a8ff 188 // Now it's time to setup properly if pullup or pulldown. This is done in ODR register:
bogdanm 0:9b334a45a8ff 189 // set pull-up => bit=1, set pull-down => bit = 0
bogdanm 0:9b334a45a8ff 190 if (mode == PullUp) {
bogdanm 0:9b334a45a8ff 191 gpio->ODR |= (0x01 << (pin_index)); // Set pull-up
bogdanm 0:9b334a45a8ff 192 } else{
bogdanm 0:9b334a45a8ff 193 gpio->ODR &= ~(0x01 << (pin_index)); // Set pull-down
bogdanm 0:9b334a45a8ff 194 }
bogdanm 0:9b334a45a8ff 195 break;
bogdanm 0:9b334a45a8ff 196 case OpenDrain:
bogdanm 0:9b334a45a8ff 197 // Set open-drain for Output mode (General Purpose or Alternate Function)
bogdanm 0:9b334a45a8ff 198 if (pin_index < 8) {
bogdanm 0:9b334a45a8ff 199 if ((gpio->CRL & (0x03 << (pin_index * 4))) > 0) { // MODE bits = Output mode
bogdanm 0:9b334a45a8ff 200 gpio->CRL |= (0x04 << (pin_index * 4)); // Set open-drain
bogdanm 0:9b334a45a8ff 201 }
bogdanm 0:9b334a45a8ff 202 } else {
bogdanm 0:9b334a45a8ff 203 if ((gpio->CRH & (0x03 << ((pin_index % 8) * 4))) > 0) { // MODE bits = Output mode
bogdanm 0:9b334a45a8ff 204 gpio->CRH |= (0x04 << ((pin_index % 8) * 4)); // Set open-drain
bogdanm 0:9b334a45a8ff 205 }
bogdanm 0:9b334a45a8ff 206 }
bogdanm 0:9b334a45a8ff 207 break;
bogdanm 0:9b334a45a8ff 208 default:
bogdanm 0:9b334a45a8ff 209 break;
bogdanm 0:9b334a45a8ff 210 }
bogdanm 0:9b334a45a8ff 211 }