Tomo Yamanaka / mbed-dev

mbed library sources. Supersedes mbed-src. GR-PEACH runs on RAM.

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h@103:493a29d2d4d7, 2016-03-30 (annotated)

Committer:
1050186
Date:
Wed Mar 30 11:41:25 2016 +0000
Revision:
103:493a29d2d4d7
Parent:
0:9b334a45a8ff 
GR-PEACH runs on RAM.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library - LPC24xx CMSIS-like structs
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * An LPC24xx header file, based on LPC23xx.h
bogdanm 0:9b334a45a8ff 5 */
bogdanm 0:9b334a45a8ff 6
bogdanm 0:9b334a45a8ff 7 #ifndef __LPC24xx_H
bogdanm 0:9b334a45a8ff 8 #define __LPC24xx_H
bogdanm 0:9b334a45a8ff 9
bogdanm 0:9b334a45a8ff 10 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 11 extern "C" {
bogdanm 0:9b334a45a8ff 12 #endif
bogdanm 0:9b334a45a8ff 13
bogdanm 0:9b334a45a8ff 14 /*
bogdanm 0:9b334a45a8ff 15 * ==========================================================================
bogdanm 0:9b334a45a8ff 16 * ---------- Interrupt Number Definition -----------------------------------
bogdanm 0:9b334a45a8ff 17 * ==========================================================================
bogdanm 0:9b334a45a8ff 18 */
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 typedef enum IRQn
bogdanm 0:9b334a45a8ff 21 {
bogdanm 0:9b334a45a8ff 22 /****** LPC23xx Specific Interrupt Numbers *******************************************************/
bogdanm 0:9b334a45a8ff 23 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
bogdanm 0:9b334a45a8ff 26 TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
bogdanm 0:9b334a45a8ff 27 UART0_IRQn = 6, /*!< UART0 Interrupt */
bogdanm 0:9b334a45a8ff 28 UART1_IRQn = 7, /*!< UART1 Interrupt */
bogdanm 0:9b334a45a8ff 29 PWM0_IRQn = 8, /*!< PWM0 Interrupt */
bogdanm 0:9b334a45a8ff 30 PWM1_IRQn = 8, /*!< PWM1 Interrupt */
bogdanm 0:9b334a45a8ff 31 I2C0_IRQn = 9, /*!< I2C0 Interrupt */
bogdanm 0:9b334a45a8ff 32 SPI_IRQn = 10, /*!< SPI Interrupt */
bogdanm 0:9b334a45a8ff 33 SSP0_IRQn = 10, /*!< SSP0 Interrupt */
bogdanm 0:9b334a45a8ff 34 SSP1_IRQn = 11, /*!< SSP1 Interrupt */
bogdanm 0:9b334a45a8ff 35 PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
bogdanm 0:9b334a45a8ff 36 RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
bogdanm 0:9b334a45a8ff 37 EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
bogdanm 0:9b334a45a8ff 38 EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
bogdanm 0:9b334a45a8ff 39 EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
bogdanm 0:9b334a45a8ff 40 EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
bogdanm 0:9b334a45a8ff 41 ADC_IRQn = 18, /*!< A/D Converter Interrupt */
bogdanm 0:9b334a45a8ff 42 I2C1_IRQn = 19, /*!< I2C1 Interrupt */
bogdanm 0:9b334a45a8ff 43 BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
bogdanm 0:9b334a45a8ff 44 ENET_IRQn = 21, /*!< Ethernet Interrupt */
bogdanm 0:9b334a45a8ff 45 USB_IRQn = 22, /*!< USB Interrupt */
bogdanm 0:9b334a45a8ff 46 CAN_IRQn = 23, /*!< CAN Interrupt */
bogdanm 0:9b334a45a8ff 47 SDMMC_IRQn = 24, /*!< SD/MMC Interrupt */
bogdanm 0:9b334a45a8ff 48 DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
bogdanm 0:9b334a45a8ff 49 TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
bogdanm 0:9b334a45a8ff 50 TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
bogdanm 0:9b334a45a8ff 51 UART2_IRQn = 28, /*!< UART2 Interrupt */
bogdanm 0:9b334a45a8ff 52 UART3_IRQn = 29, /*!< UART3 Interrupt */
bogdanm 0:9b334a45a8ff 53 I2C2_IRQn = 30, /*!< I2C2 Interrupt */
bogdanm 0:9b334a45a8ff 54 I2S_IRQn = 31, /*!< I2S Interrupt */
bogdanm 0:9b334a45a8ff 55 } IRQn_Type;
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /*
bogdanm 0:9b334a45a8ff 58 * ==========================================================================
bogdanm 0:9b334a45a8ff 59 * ----------- Processor and Core Peripheral Section ------------------------
bogdanm 0:9b334a45a8ff 60 * ==========================================================================
bogdanm 0:9b334a45a8ff 61 */
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /* Configuration of the ARM7 Processor and Core Peripherals */
bogdanm 0:9b334a45a8ff 64 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 0:9b334a45a8ff 65 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
bogdanm 0:9b334a45a8ff 66 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 #include <core_arm7.h>
bogdanm 0:9b334a45a8ff 70 #include "system_LPC24xx.h" /* System Header */
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 /******************************************************************************/
bogdanm 0:9b334a45a8ff 74 /* Device Specific Peripheral registers structures */
bogdanm 0:9b334a45a8ff 75 /******************************************************************************/
bogdanm 0:9b334a45a8ff 76 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 77 #pragma anon_unions
bogdanm 0:9b334a45a8ff 78 #endif
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 /*------------- Vector Interupt Controler (VIC) ------------------------------*/
bogdanm 0:9b334a45a8ff 81 typedef struct
bogdanm 0:9b334a45a8ff 82 {
bogdanm 0:9b334a45a8ff 83 __I uint32_t IRQStatus;
bogdanm 0:9b334a45a8ff 84 __I uint32_t FIQStatus;
bogdanm 0:9b334a45a8ff 85 __I uint32_t RawIntr;
bogdanm 0:9b334a45a8ff 86 __IO uint32_t IntSelect;
bogdanm 0:9b334a45a8ff 87 __IO uint32_t IntEnable;
bogdanm 0:9b334a45a8ff 88 __O uint32_t IntEnClr;
bogdanm 0:9b334a45a8ff 89 __IO uint32_t SoftInt;
bogdanm 0:9b334a45a8ff 90 __O uint32_t SoftIntClr;
bogdanm 0:9b334a45a8ff 91 __IO uint32_t Protection;
bogdanm 0:9b334a45a8ff 92 __IO uint32_t SWPriorityMask;
bogdanm 0:9b334a45a8ff 93 __IO uint32_t RESERVED0[54];
bogdanm 0:9b334a45a8ff 94 __IO uint32_t VectAddr[32];
bogdanm 0:9b334a45a8ff 95 __IO uint32_t RESERVED1[32];
bogdanm 0:9b334a45a8ff 96 __IO uint32_t VectPriority[32];
bogdanm 0:9b334a45a8ff 97 __IO uint32_t RESERVED2[800];
bogdanm 0:9b334a45a8ff 98 __IO uint32_t Address;
bogdanm 0:9b334a45a8ff 99 } LPC_VIC_TypeDef;
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /*------------- System Control (SC) ------------------------------------------*/
bogdanm 0:9b334a45a8ff 102 typedef struct
bogdanm 0:9b334a45a8ff 103 {
bogdanm 0:9b334a45a8ff 104 __IO uint32_t MAMCR;
bogdanm 0:9b334a45a8ff 105 __IO uint32_t MAMTIM;
bogdanm 0:9b334a45a8ff 106 uint32_t RESERVED0[14];
bogdanm 0:9b334a45a8ff 107 __IO uint32_t MEMMAP;
bogdanm 0:9b334a45a8ff 108 uint32_t RESERVED1[15];
bogdanm 0:9b334a45a8ff 109 __IO uint32_t PLL0CON; /* Clocking and Power Control */
bogdanm 0:9b334a45a8ff 110 __IO uint32_t PLL0CFG;
bogdanm 0:9b334a45a8ff 111 __I uint32_t PLL0STAT;
bogdanm 0:9b334a45a8ff 112 __O uint32_t PLL0FEED;
bogdanm 0:9b334a45a8ff 113 uint32_t RESERVED2[12];
bogdanm 0:9b334a45a8ff 114 __IO uint32_t PCON;
bogdanm 0:9b334a45a8ff 115 __IO uint32_t PCONP;
bogdanm 0:9b334a45a8ff 116 uint32_t RESERVED3[15];
bogdanm 0:9b334a45a8ff 117 __IO uint32_t CCLKCFG;
bogdanm 0:9b334a45a8ff 118 __IO uint32_t USBCLKCFG;
bogdanm 0:9b334a45a8ff 119 __IO uint32_t CLKSRCSEL;
bogdanm 0:9b334a45a8ff 120 uint32_t RESERVED4[12];
bogdanm 0:9b334a45a8ff 121 __IO uint32_t EXTINT; /* External Interrupts */
bogdanm 0:9b334a45a8ff 122 __IO uint32_t INTWAKE;
bogdanm 0:9b334a45a8ff 123 __IO uint32_t EXTMODE;
bogdanm 0:9b334a45a8ff 124 __IO uint32_t EXTPOLAR;
bogdanm 0:9b334a45a8ff 125 uint32_t RESERVED6[12];
bogdanm 0:9b334a45a8ff 126 __IO uint32_t RSID; /* Reset */
bogdanm 0:9b334a45a8ff 127 __IO uint32_t CSPR;
bogdanm 0:9b334a45a8ff 128 __IO uint32_t AHBCFG1;
bogdanm 0:9b334a45a8ff 129 __IO uint32_t AHBCFG2;
bogdanm 0:9b334a45a8ff 130 uint32_t RESERVED7[4];
bogdanm 0:9b334a45a8ff 131 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
bogdanm 0:9b334a45a8ff 132 __IO uint32_t IRCTRIM; /* Clock Dividers */
bogdanm 0:9b334a45a8ff 133 __IO uint32_t PCLKSEL0;
bogdanm 0:9b334a45a8ff 134 __IO uint32_t PCLKSEL1;
bogdanm 0:9b334a45a8ff 135 uint32_t RESERVED8[4];
bogdanm 0:9b334a45a8ff 136 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
bogdanm 0:9b334a45a8ff 137 uint32_t RESERVED9;
bogdanm 0:9b334a45a8ff 138 // __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
bogdanm 0:9b334a45a8ff 139 } LPC_SC_TypeDef;
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
bogdanm 0:9b334a45a8ff 142 typedef struct
bogdanm 0:9b334a45a8ff 143 {
bogdanm 0:9b334a45a8ff 144 __IO uint32_t PINSEL0;
bogdanm 0:9b334a45a8ff 145 __IO uint32_t PINSEL1;
bogdanm 0:9b334a45a8ff 146 __IO uint32_t PINSEL2;
bogdanm 0:9b334a45a8ff 147 __IO uint32_t PINSEL3;
bogdanm 0:9b334a45a8ff 148 __IO uint32_t PINSEL4;
bogdanm 0:9b334a45a8ff 149 __IO uint32_t PINSEL5;
bogdanm 0:9b334a45a8ff 150 __IO uint32_t PINSEL6;
bogdanm 0:9b334a45a8ff 151 __IO uint32_t PINSEL7;
bogdanm 0:9b334a45a8ff 152 __IO uint32_t PINSEL8;
bogdanm 0:9b334a45a8ff 153 __IO uint32_t PINSEL9;
bogdanm 0:9b334a45a8ff 154 __IO uint32_t PINSEL10;
bogdanm 0:9b334a45a8ff 155 uint32_t RESERVED0[5];
bogdanm 0:9b334a45a8ff 156 __IO uint32_t PINMODE0;
bogdanm 0:9b334a45a8ff 157 __IO uint32_t PINMODE1;
bogdanm 0:9b334a45a8ff 158 __IO uint32_t PINMODE2;
bogdanm 0:9b334a45a8ff 159 __IO uint32_t PINMODE3;
bogdanm 0:9b334a45a8ff 160 __IO uint32_t PINMODE4;
bogdanm 0:9b334a45a8ff 161 __IO uint32_t PINMODE5;
bogdanm 0:9b334a45a8ff 162 __IO uint32_t PINMODE6;
bogdanm 0:9b334a45a8ff 163 __IO uint32_t PINMODE7;
bogdanm 0:9b334a45a8ff 164 __IO uint32_t PINMODE8;
bogdanm 0:9b334a45a8ff 165 __IO uint32_t PINMODE9;
bogdanm 0:9b334a45a8ff 166 __IO uint32_t PINMODE_OD0;
bogdanm 0:9b334a45a8ff 167 __IO uint32_t PINMODE_OD1;
bogdanm 0:9b334a45a8ff 168 __IO uint32_t PINMODE_OD2;
bogdanm 0:9b334a45a8ff 169 __IO uint32_t PINMODE_OD3;
bogdanm 0:9b334a45a8ff 170 __IO uint32_t PINMODE_OD4;
bogdanm 0:9b334a45a8ff 171 } LPC_PINCON_TypeDef;
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 #define PCTIM0 1
bogdanm 0:9b334a45a8ff 174 #define PCTIM1 2
bogdanm 0:9b334a45a8ff 175 #define PCUART0 3
bogdanm 0:9b334a45a8ff 176 #define PCUART1 4
bogdanm 0:9b334a45a8ff 177 #define PCPWM1 6
bogdanm 0:9b334a45a8ff 178 #define PCI2C0 7
bogdanm 0:9b334a45a8ff 179 #define PCSPI 8
bogdanm 0:9b334a45a8ff 180 #define PCRTC 9
bogdanm 0:9b334a45a8ff 181 #define PCSSP1 10
bogdanm 0:9b334a45a8ff 182 #define PCEMC 11
bogdanm 0:9b334a45a8ff 183 #define PCADC 12
bogdanm 0:9b334a45a8ff 184 #define PCAN1 13
bogdanm 0:9b334a45a8ff 185 #define PCAN2 14
bogdanm 0:9b334a45a8ff 186 #define PCI2C1 19
bogdanm 0:9b334a45a8ff 187 #define PCSSP0 21
bogdanm 0:9b334a45a8ff 188 #define PCTIM2 22
bogdanm 0:9b334a45a8ff 189 #define PCTIM3 23
bogdanm 0:9b334a45a8ff 190 #define PCUART2 24
bogdanm 0:9b334a45a8ff 191 #define PCUART3 25
bogdanm 0:9b334a45a8ff 192 #define PCI2C2 26
bogdanm 0:9b334a45a8ff 193 #define PCI2S 27
bogdanm 0:9b334a45a8ff 194 #define PCSDC 28
bogdanm 0:9b334a45a8ff 195 #define PCGPDMA 29
bogdanm 0:9b334a45a8ff 196 #define PCENET 30
bogdanm 0:9b334a45a8ff 197 #define PCUSB 31
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
bogdanm 0:9b334a45a8ff 200 typedef struct
bogdanm 0:9b334a45a8ff 201 {
bogdanm 0:9b334a45a8ff 202 __IO uint32_t FIODIR;
bogdanm 0:9b334a45a8ff 203 uint32_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 204 __IO uint32_t FIOMASK;
bogdanm 0:9b334a45a8ff 205 __IO uint32_t FIOPIN;
bogdanm 0:9b334a45a8ff 206 __IO uint32_t FIOSET;
bogdanm 0:9b334a45a8ff 207 __O uint32_t FIOCLR;
bogdanm 0:9b334a45a8ff 208 } LPC_GPIO_TypeDef;
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 typedef struct
bogdanm 0:9b334a45a8ff 211 {
bogdanm 0:9b334a45a8ff 212 __I uint32_t IntStatus;
bogdanm 0:9b334a45a8ff 213 __I uint32_t IO0IntStatR;
bogdanm 0:9b334a45a8ff 214 __I uint32_t IO0IntStatF;
bogdanm 0:9b334a45a8ff 215 __O uint32_t IO0IntClr;
bogdanm 0:9b334a45a8ff 216 __IO uint32_t IO0IntEnR;
bogdanm 0:9b334a45a8ff 217 __IO uint32_t IO0IntEnF;
bogdanm 0:9b334a45a8ff 218 uint32_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 219 __I uint32_t IO2IntStatR;
bogdanm 0:9b334a45a8ff 220 __I uint32_t IO2IntStatF;
bogdanm 0:9b334a45a8ff 221 __O uint32_t IO2IntClr;
bogdanm 0:9b334a45a8ff 222 __IO uint32_t IO2IntEnR;
bogdanm 0:9b334a45a8ff 223 __IO uint32_t IO2IntEnF;
bogdanm 0:9b334a45a8ff 224 } LPC_GPIOINT_TypeDef;
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /*------------- Timer (TIM) --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 227 typedef struct
bogdanm 0:9b334a45a8ff 228 {
bogdanm 0:9b334a45a8ff 229 __IO uint32_t IR;
bogdanm 0:9b334a45a8ff 230 __IO uint32_t TCR;
bogdanm 0:9b334a45a8ff 231 __IO uint32_t TC;
bogdanm 0:9b334a45a8ff 232 __IO uint32_t PR;
bogdanm 0:9b334a45a8ff 233 __IO uint32_t PC;
bogdanm 0:9b334a45a8ff 234 __IO uint32_t MCR;
bogdanm 0:9b334a45a8ff 235 __IO uint32_t MR0;
bogdanm 0:9b334a45a8ff 236 __IO uint32_t MR1;
bogdanm 0:9b334a45a8ff 237 __IO uint32_t MR2;
bogdanm 0:9b334a45a8ff 238 __IO uint32_t MR3;
bogdanm 0:9b334a45a8ff 239 __IO uint32_t CCR;
bogdanm 0:9b334a45a8ff 240 __I uint32_t CR0;
bogdanm 0:9b334a45a8ff 241 __I uint32_t CR1;
bogdanm 0:9b334a45a8ff 242 uint32_t RESERVED0[2];
bogdanm 0:9b334a45a8ff 243 __IO uint32_t EMR;
bogdanm 0:9b334a45a8ff 244 uint32_t RESERVED1[12];
bogdanm 0:9b334a45a8ff 245 __IO uint32_t CTCR;
bogdanm 0:9b334a45a8ff 246 } LPC_TIM_TypeDef;
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
bogdanm 0:9b334a45a8ff 249 typedef struct
bogdanm 0:9b334a45a8ff 250 {
bogdanm 0:9b334a45a8ff 251 __IO uint32_t IR;
bogdanm 0:9b334a45a8ff 252 __IO uint32_t TCR;
bogdanm 0:9b334a45a8ff 253 __IO uint32_t TC;
bogdanm 0:9b334a45a8ff 254 __IO uint32_t PR;
bogdanm 0:9b334a45a8ff 255 __IO uint32_t PC;
bogdanm 0:9b334a45a8ff 256 __IO uint32_t MCR;
bogdanm 0:9b334a45a8ff 257 __IO uint32_t MR0;
bogdanm 0:9b334a45a8ff 258 __IO uint32_t MR1;
bogdanm 0:9b334a45a8ff 259 __IO uint32_t MR2;
bogdanm 0:9b334a45a8ff 260 __IO uint32_t MR3;
bogdanm 0:9b334a45a8ff 261 __IO uint32_t CCR;
bogdanm 0:9b334a45a8ff 262 __I uint32_t CR0;
bogdanm 0:9b334a45a8ff 263 __I uint32_t CR1;
bogdanm 0:9b334a45a8ff 264 __I uint32_t CR2;
bogdanm 0:9b334a45a8ff 265 __I uint32_t CR3;
bogdanm 0:9b334a45a8ff 266 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 267 __IO uint32_t MR4;
bogdanm 0:9b334a45a8ff 268 __IO uint32_t MR5;
bogdanm 0:9b334a45a8ff 269 __IO uint32_t MR6;
bogdanm 0:9b334a45a8ff 270 __IO uint32_t PCR;
bogdanm 0:9b334a45a8ff 271 __IO uint32_t LER;
bogdanm 0:9b334a45a8ff 272 uint32_t RESERVED1[7];
bogdanm 0:9b334a45a8ff 273 __IO uint32_t CTCR;
bogdanm 0:9b334a45a8ff 274 } LPC_PWM_TypeDef;
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
bogdanm 0:9b334a45a8ff 277 typedef struct
bogdanm 0:9b334a45a8ff 278 {
bogdanm 0:9b334a45a8ff 279 union {
bogdanm 0:9b334a45a8ff 280 __I uint8_t RBR;
bogdanm 0:9b334a45a8ff 281 __O uint8_t THR;
bogdanm 0:9b334a45a8ff 282 __IO uint8_t DLL;
bogdanm 0:9b334a45a8ff 283 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 284 };
bogdanm 0:9b334a45a8ff 285 union {
bogdanm 0:9b334a45a8ff 286 __IO uint8_t DLM;
bogdanm 0:9b334a45a8ff 287 __IO uint32_t IER;
bogdanm 0:9b334a45a8ff 288 };
bogdanm 0:9b334a45a8ff 289 union {
bogdanm 0:9b334a45a8ff 290 __I uint32_t IIR;
bogdanm 0:9b334a45a8ff 291 __O uint8_t FCR;
bogdanm 0:9b334a45a8ff 292 };
bogdanm 0:9b334a45a8ff 293 __IO uint8_t LCR;
bogdanm 0:9b334a45a8ff 294 uint8_t RESERVED1[7];
bogdanm 0:9b334a45a8ff 295 __IO uint8_t LSR;
bogdanm 0:9b334a45a8ff 296 uint8_t RESERVED2[7];
bogdanm 0:9b334a45a8ff 297 __IO uint8_t SCR;
bogdanm 0:9b334a45a8ff 298 uint8_t RESERVED3[3];
bogdanm 0:9b334a45a8ff 299 __IO uint32_t ACR;
bogdanm 0:9b334a45a8ff 300 __IO uint8_t ICR;
bogdanm 0:9b334a45a8ff 301 uint8_t RESERVED4[3];
bogdanm 0:9b334a45a8ff 302 __IO uint8_t FDR;
bogdanm 0:9b334a45a8ff 303 uint8_t RESERVED5[7];
bogdanm 0:9b334a45a8ff 304 __IO uint8_t TER;
bogdanm 0:9b334a45a8ff 305 uint8_t RESERVED6[27];
bogdanm 0:9b334a45a8ff 306 __IO uint8_t RS485CTRL;
bogdanm 0:9b334a45a8ff 307 uint8_t RESERVED7[3];
bogdanm 0:9b334a45a8ff 308 __IO uint8_t ADRMATCH;
bogdanm 0:9b334a45a8ff 309 } LPC_UART_TypeDef;
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 typedef struct
bogdanm 0:9b334a45a8ff 312 {
bogdanm 0:9b334a45a8ff 313 union {
bogdanm 0:9b334a45a8ff 314 __I uint8_t RBR;
bogdanm 0:9b334a45a8ff 315 __O uint8_t THR;
bogdanm 0:9b334a45a8ff 316 __IO uint8_t DLL;
bogdanm 0:9b334a45a8ff 317 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 318 };
bogdanm 0:9b334a45a8ff 319 union {
bogdanm 0:9b334a45a8ff 320 __IO uint8_t DLM;
bogdanm 0:9b334a45a8ff 321 __IO uint32_t IER;
bogdanm 0:9b334a45a8ff 322 };
bogdanm 0:9b334a45a8ff 323 union {
bogdanm 0:9b334a45a8ff 324 __I uint32_t IIR;
bogdanm 0:9b334a45a8ff 325 __O uint8_t FCR;
bogdanm 0:9b334a45a8ff 326 };
bogdanm 0:9b334a45a8ff 327 __IO uint8_t LCR;
bogdanm 0:9b334a45a8ff 328 uint8_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 329 __IO uint8_t MCR;
bogdanm 0:9b334a45a8ff 330 uint8_t RESERVED2[3];
bogdanm 0:9b334a45a8ff 331 __IO uint8_t LSR;
bogdanm 0:9b334a45a8ff 332 uint8_t RESERVED3[3];
bogdanm 0:9b334a45a8ff 333 __IO uint8_t MSR;
bogdanm 0:9b334a45a8ff 334 uint8_t RESERVED4[3];
bogdanm 0:9b334a45a8ff 335 __IO uint8_t SCR;
bogdanm 0:9b334a45a8ff 336 uint8_t RESERVED5[3];
bogdanm 0:9b334a45a8ff 337 __IO uint32_t ACR;
bogdanm 0:9b334a45a8ff 338 uint32_t RESERVED6;
bogdanm 0:9b334a45a8ff 339 __IO uint32_t FDR;
bogdanm 0:9b334a45a8ff 340 uint32_t RESERVED7;
bogdanm 0:9b334a45a8ff 341 __IO uint8_t TER;
bogdanm 0:9b334a45a8ff 342 uint8_t RESERVED8[27];
bogdanm 0:9b334a45a8ff 343 __IO uint8_t RS485CTRL;
bogdanm 0:9b334a45a8ff 344 uint8_t RESERVED9[3];
bogdanm 0:9b334a45a8ff 345 __IO uint8_t ADRMATCH;
bogdanm 0:9b334a45a8ff 346 uint8_t RESERVED10[3];
bogdanm 0:9b334a45a8ff 347 __IO uint8_t RS485DLY;
bogdanm 0:9b334a45a8ff 348 } LPC_UART1_TypeDef;
bogdanm 0:9b334a45a8ff 349
bogdanm 0:9b334a45a8ff 350 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
bogdanm 0:9b334a45a8ff 351 typedef struct
bogdanm 0:9b334a45a8ff 352 {
bogdanm 0:9b334a45a8ff 353 __IO uint32_t SPCR;
bogdanm 0:9b334a45a8ff 354 __I uint32_t SPSR;
bogdanm 0:9b334a45a8ff 355 __IO uint32_t SPDR;
bogdanm 0:9b334a45a8ff 356 __IO uint32_t SPCCR;
bogdanm 0:9b334a45a8ff 357 uint32_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 358 __IO uint32_t SPINT;
bogdanm 0:9b334a45a8ff 359 } LPC_SPI_TypeDef;
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
bogdanm 0:9b334a45a8ff 362 typedef struct
bogdanm 0:9b334a45a8ff 363 {
bogdanm 0:9b334a45a8ff 364 __IO uint32_t CR0;
bogdanm 0:9b334a45a8ff 365 __IO uint32_t CR1;
bogdanm 0:9b334a45a8ff 366 __IO uint32_t DR;
bogdanm 0:9b334a45a8ff 367 __I uint32_t SR;
bogdanm 0:9b334a45a8ff 368 __IO uint32_t CPSR;
bogdanm 0:9b334a45a8ff 369 __IO uint32_t IMSC;
bogdanm 0:9b334a45a8ff 370 __IO uint32_t RIS;
bogdanm 0:9b334a45a8ff 371 __IO uint32_t MIS;
bogdanm 0:9b334a45a8ff 372 __IO uint32_t ICR;
bogdanm 0:9b334a45a8ff 373 __IO uint32_t DMACR;
bogdanm 0:9b334a45a8ff 374 } LPC_SSP_TypeDef;
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
bogdanm 0:9b334a45a8ff 377 typedef struct
bogdanm 0:9b334a45a8ff 378 {
bogdanm 0:9b334a45a8ff 379 __IO uint32_t I2CONSET;
bogdanm 0:9b334a45a8ff 380 __I uint32_t I2STAT;
bogdanm 0:9b334a45a8ff 381 __IO uint32_t I2DAT;
bogdanm 0:9b334a45a8ff 382 __IO uint32_t I2ADR0;
bogdanm 0:9b334a45a8ff 383 __IO uint32_t I2SCLH;
bogdanm 0:9b334a45a8ff 384 __IO uint32_t I2SCLL;
bogdanm 0:9b334a45a8ff 385 __O uint32_t I2CONCLR;
bogdanm 0:9b334a45a8ff 386 __IO uint32_t MMCTRL;
bogdanm 0:9b334a45a8ff 387 __IO uint32_t I2ADR1;
bogdanm 0:9b334a45a8ff 388 __IO uint32_t I2ADR2;
bogdanm 0:9b334a45a8ff 389 __IO uint32_t I2ADR3;
bogdanm 0:9b334a45a8ff 390 __I uint32_t I2DATA_BUFFER;
bogdanm 0:9b334a45a8ff 391 __IO uint32_t I2MASK0;
bogdanm 0:9b334a45a8ff 392 __IO uint32_t I2MASK1;
bogdanm 0:9b334a45a8ff 393 __IO uint32_t I2MASK2;
bogdanm 0:9b334a45a8ff 394 __IO uint32_t I2MASK3;
bogdanm 0:9b334a45a8ff 395 } LPC_I2C_TypeDef;
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
bogdanm 0:9b334a45a8ff 398 typedef struct
bogdanm 0:9b334a45a8ff 399 {
bogdanm 0:9b334a45a8ff 400 __IO uint32_t I2SDAO;
bogdanm 0:9b334a45a8ff 401 __I uint32_t I2SDAI;
bogdanm 0:9b334a45a8ff 402 __O uint32_t I2STXFIFO;
bogdanm 0:9b334a45a8ff 403 __I uint32_t I2SRXFIFO;
bogdanm 0:9b334a45a8ff 404 __I uint32_t I2SSTATE;
bogdanm 0:9b334a45a8ff 405 __IO uint32_t I2SDMA1;
bogdanm 0:9b334a45a8ff 406 __IO uint32_t I2SDMA2;
bogdanm 0:9b334a45a8ff 407 __IO uint32_t I2SIRQ;
bogdanm 0:9b334a45a8ff 408 __IO uint32_t I2STXRATE;
bogdanm 0:9b334a45a8ff 409 __IO uint32_t I2SRXRATE;
bogdanm 0:9b334a45a8ff 410 __IO uint32_t I2STXBITRATE;
bogdanm 0:9b334a45a8ff 411 __IO uint32_t I2SRXBITRATE;
bogdanm 0:9b334a45a8ff 412 __IO uint32_t I2STXMODE;
bogdanm 0:9b334a45a8ff 413 __IO uint32_t I2SRXMODE;
bogdanm 0:9b334a45a8ff 414 } LPC_I2S_TypeDef;
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
bogdanm 0:9b334a45a8ff 417 typedef struct
bogdanm 0:9b334a45a8ff 418 {
bogdanm 0:9b334a45a8ff 419 __IO uint8_t ILR;
bogdanm 0:9b334a45a8ff 420 uint8_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 421 __IO uint8_t CTC;
bogdanm 0:9b334a45a8ff 422 uint8_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 423 __IO uint8_t CCR;
bogdanm 0:9b334a45a8ff 424 uint8_t RESERVED2[3];
bogdanm 0:9b334a45a8ff 425 __IO uint8_t CIIR;
bogdanm 0:9b334a45a8ff 426 uint8_t RESERVED3[3];
bogdanm 0:9b334a45a8ff 427 __IO uint8_t AMR;
bogdanm 0:9b334a45a8ff 428 uint8_t RESERVED4[3];
bogdanm 0:9b334a45a8ff 429 __I uint32_t CTIME0;
bogdanm 0:9b334a45a8ff 430 __I uint32_t CTIME1;
bogdanm 0:9b334a45a8ff 431 __I uint32_t CTIME2;
bogdanm 0:9b334a45a8ff 432 __IO uint8_t SEC;
bogdanm 0:9b334a45a8ff 433 uint8_t RESERVED5[3];
bogdanm 0:9b334a45a8ff 434 __IO uint8_t MIN;
bogdanm 0:9b334a45a8ff 435 uint8_t RESERVED6[3];
bogdanm 0:9b334a45a8ff 436 __IO uint8_t HOUR;
bogdanm 0:9b334a45a8ff 437 uint8_t RESERVED7[3];
bogdanm 0:9b334a45a8ff 438 __IO uint8_t DOM;
bogdanm 0:9b334a45a8ff 439 uint8_t RESERVED8[3];
bogdanm 0:9b334a45a8ff 440 __IO uint8_t DOW;
bogdanm 0:9b334a45a8ff 441 uint8_t RESERVED9[3];
bogdanm 0:9b334a45a8ff 442 __IO uint16_t DOY;
bogdanm 0:9b334a45a8ff 443 uint16_t RESERVED10;
bogdanm 0:9b334a45a8ff 444 __IO uint8_t MONTH;
bogdanm 0:9b334a45a8ff 445 uint8_t RESERVED11[3];
bogdanm 0:9b334a45a8ff 446 __IO uint16_t YEAR;
bogdanm 0:9b334a45a8ff 447 uint16_t RESERVED12;
bogdanm 0:9b334a45a8ff 448 __IO uint32_t CALIBRATION;
bogdanm 0:9b334a45a8ff 449 __IO uint32_t GPREG0;
bogdanm 0:9b334a45a8ff 450 __IO uint32_t GPREG1;
bogdanm 0:9b334a45a8ff 451 __IO uint32_t GPREG2;
bogdanm 0:9b334a45a8ff 452 __IO uint32_t GPREG3;
bogdanm 0:9b334a45a8ff 453 __IO uint32_t GPREG4;
bogdanm 0:9b334a45a8ff 454 __IO uint8_t WAKEUPDIS;
bogdanm 0:9b334a45a8ff 455 uint8_t RESERVED13[3];
bogdanm 0:9b334a45a8ff 456 __IO uint8_t PWRCTRL;
bogdanm 0:9b334a45a8ff 457 uint8_t RESERVED14[3];
bogdanm 0:9b334a45a8ff 458 __IO uint8_t ALSEC;
bogdanm 0:9b334a45a8ff 459 uint8_t RESERVED15[3];
bogdanm 0:9b334a45a8ff 460 __IO uint8_t ALMIN;
bogdanm 0:9b334a45a8ff 461 uint8_t RESERVED16[3];
bogdanm 0:9b334a45a8ff 462 __IO uint8_t ALHOUR;
bogdanm 0:9b334a45a8ff 463 uint8_t RESERVED17[3];
bogdanm 0:9b334a45a8ff 464 __IO uint8_t ALDOM;
bogdanm 0:9b334a45a8ff 465 uint8_t RESERVED18[3];
bogdanm 0:9b334a45a8ff 466 __IO uint8_t ALDOW;
bogdanm 0:9b334a45a8ff 467 uint8_t RESERVED19[3];
bogdanm 0:9b334a45a8ff 468 __IO uint16_t ALDOY;
bogdanm 0:9b334a45a8ff 469 uint16_t RESERVED20;
bogdanm 0:9b334a45a8ff 470 __IO uint8_t ALMON;
bogdanm 0:9b334a45a8ff 471 uint8_t RESERVED21[3];
bogdanm 0:9b334a45a8ff 472 __IO uint16_t ALYEAR;
bogdanm 0:9b334a45a8ff 473 uint16_t RESERVED22;
bogdanm 0:9b334a45a8ff 474 } LPC_RTC_TypeDef;
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
bogdanm 0:9b334a45a8ff 477 typedef struct
bogdanm 0:9b334a45a8ff 478 {
bogdanm 0:9b334a45a8ff 479 __IO uint8_t WDMOD;
bogdanm 0:9b334a45a8ff 480 uint8_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 481 __IO uint32_t WDTC;
bogdanm 0:9b334a45a8ff 482 __O uint8_t WDFEED;
bogdanm 0:9b334a45a8ff 483 uint8_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 484 __I uint32_t WDTV;
bogdanm 0:9b334a45a8ff 485 __IO uint32_t WDCLKSEL;
bogdanm 0:9b334a45a8ff 486 } LPC_WDT_TypeDef;
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
bogdanm 0:9b334a45a8ff 489 typedef struct
bogdanm 0:9b334a45a8ff 490 {
bogdanm 0:9b334a45a8ff 491 __IO uint32_t ADCR;
bogdanm 0:9b334a45a8ff 492 __IO uint32_t ADGDR;
bogdanm 0:9b334a45a8ff 493 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 494 __IO uint32_t ADINTEN;
bogdanm 0:9b334a45a8ff 495 __I uint32_t ADDR0;
bogdanm 0:9b334a45a8ff 496 __I uint32_t ADDR1;
bogdanm 0:9b334a45a8ff 497 __I uint32_t ADDR2;
bogdanm 0:9b334a45a8ff 498 __I uint32_t ADDR3;
bogdanm 0:9b334a45a8ff 499 __I uint32_t ADDR4;
bogdanm 0:9b334a45a8ff 500 __I uint32_t ADDR5;
bogdanm 0:9b334a45a8ff 501 __I uint32_t ADDR6;
bogdanm 0:9b334a45a8ff 502 __I uint32_t ADDR7;
bogdanm 0:9b334a45a8ff 503 __I uint32_t ADSTAT;
bogdanm 0:9b334a45a8ff 504 __IO uint32_t ADTRM;
bogdanm 0:9b334a45a8ff 505 } LPC_ADC_TypeDef;
bogdanm 0:9b334a45a8ff 506
bogdanm 0:9b334a45a8ff 507 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
bogdanm 0:9b334a45a8ff 508 typedef struct
bogdanm 0:9b334a45a8ff 509 {
bogdanm 0:9b334a45a8ff 510 __IO uint32_t DACR;
bogdanm 0:9b334a45a8ff 511 __IO uint32_t DACCTRL;
bogdanm 0:9b334a45a8ff 512 __IO uint16_t DACCNTVAL;
bogdanm 0:9b334a45a8ff 513 } LPC_DAC_TypeDef;
bogdanm 0:9b334a45a8ff 514
bogdanm 0:9b334a45a8ff 515 /*------------- Multimedia Card Interface (MCI) ------------------------------*/
bogdanm 0:9b334a45a8ff 516 typedef struct
bogdanm 0:9b334a45a8ff 517 {
bogdanm 0:9b334a45a8ff 518 __IO uint32_t MCIPower; /* Power control */
bogdanm 0:9b334a45a8ff 519 __IO uint32_t MCIClock; /* Clock control */
bogdanm 0:9b334a45a8ff 520 __IO uint32_t MCIArgument;
bogdanm 0:9b334a45a8ff 521 __IO uint32_t MMCCommand;
bogdanm 0:9b334a45a8ff 522 __I uint32_t MCIRespCmd;
bogdanm 0:9b334a45a8ff 523 __I uint32_t MCIResponse0;
bogdanm 0:9b334a45a8ff 524 __I uint32_t MCIResponse1;
bogdanm 0:9b334a45a8ff 525 __I uint32_t MCIResponse2;
bogdanm 0:9b334a45a8ff 526 __I uint32_t MCIResponse3;
bogdanm 0:9b334a45a8ff 527 __IO uint32_t MCIDataTimer;
bogdanm 0:9b334a45a8ff 528 __IO uint32_t MCIDataLength;
bogdanm 0:9b334a45a8ff 529 __IO uint32_t MCIDataCtrl;
bogdanm 0:9b334a45a8ff 530 __I uint32_t MCIDataCnt;
bogdanm 0:9b334a45a8ff 531 __I uint32_t MCIStatus;
bogdanm 0:9b334a45a8ff 532 __O uint32_t MCIClear;
bogdanm 0:9b334a45a8ff 533 __IO uint32_t MCIMask0;
bogdanm 0:9b334a45a8ff 534 uint32_t RESERVED1[2];
bogdanm 0:9b334a45a8ff 535 __I uint32_t MCIFifoCnt;
bogdanm 0:9b334a45a8ff 536 uint32_t RESERVED2[13];
bogdanm 0:9b334a45a8ff 537 __IO uint32_t MCIFIFO[16];
bogdanm 0:9b334a45a8ff 538 } LPC_MCI_TypeDef;
bogdanm 0:9b334a45a8ff 539
bogdanm 0:9b334a45a8ff 540 /*------------- Controller Area Network (CAN) --------------------------------*/
bogdanm 0:9b334a45a8ff 541 typedef struct
bogdanm 0:9b334a45a8ff 542 {
bogdanm 0:9b334a45a8ff 543 __IO uint32_t mask[512]; /* ID Masks */
bogdanm 0:9b334a45a8ff 544 } LPC_CANAF_RAM_TypeDef;
bogdanm 0:9b334a45a8ff 545
bogdanm 0:9b334a45a8ff 546 typedef struct /* Acceptance Filter Registers */
bogdanm 0:9b334a45a8ff 547 {
bogdanm 0:9b334a45a8ff 548 __IO uint32_t AFMR;
bogdanm 0:9b334a45a8ff 549 __IO uint32_t SFF_sa;
bogdanm 0:9b334a45a8ff 550 __IO uint32_t SFF_GRP_sa;
bogdanm 0:9b334a45a8ff 551 __IO uint32_t EFF_sa;
bogdanm 0:9b334a45a8ff 552 __IO uint32_t EFF_GRP_sa;
bogdanm 0:9b334a45a8ff 553 __IO uint32_t ENDofTable;
bogdanm 0:9b334a45a8ff 554 __I uint32_t LUTerrAd;
bogdanm 0:9b334a45a8ff 555 __I uint32_t LUTerr;
bogdanm 0:9b334a45a8ff 556 __IO uint32_t FCANIE;
bogdanm 0:9b334a45a8ff 557 __IO uint32_t FCANIC0;
bogdanm 0:9b334a45a8ff 558 __IO uint32_t FCANIC1;
bogdanm 0:9b334a45a8ff 559 } LPC_CANAF_TypeDef;
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 typedef struct /* Central Registers */
bogdanm 0:9b334a45a8ff 562 {
bogdanm 0:9b334a45a8ff 563 __I uint32_t CANTxSR;
bogdanm 0:9b334a45a8ff 564 __I uint32_t CANRxSR;
bogdanm 0:9b334a45a8ff 565 __I uint32_t CANMSR;
bogdanm 0:9b334a45a8ff 566 } LPC_CANCR_TypeDef;
bogdanm 0:9b334a45a8ff 567
bogdanm 0:9b334a45a8ff 568 typedef struct /* Controller Registers */
bogdanm 0:9b334a45a8ff 569 {
bogdanm 0:9b334a45a8ff 570 __IO uint32_t MOD;
bogdanm 0:9b334a45a8ff 571 __O uint32_t CMR;
bogdanm 0:9b334a45a8ff 572 __IO uint32_t GSR;
bogdanm 0:9b334a45a8ff 573 __I uint32_t ICR;
bogdanm 0:9b334a45a8ff 574 __IO uint32_t IER;
bogdanm 0:9b334a45a8ff 575 __IO uint32_t BTR;
bogdanm 0:9b334a45a8ff 576 __IO uint32_t EWL;
bogdanm 0:9b334a45a8ff 577 __I uint32_t SR;
bogdanm 0:9b334a45a8ff 578 __IO uint32_t RFS;
bogdanm 0:9b334a45a8ff 579 __IO uint32_t RID;
bogdanm 0:9b334a45a8ff 580 __IO uint32_t RDA;
bogdanm 0:9b334a45a8ff 581 __IO uint32_t RDB;
bogdanm 0:9b334a45a8ff 582 __IO uint32_t TFI1;
bogdanm 0:9b334a45a8ff 583 __IO uint32_t TID1;
bogdanm 0:9b334a45a8ff 584 __IO uint32_t TDA1;
bogdanm 0:9b334a45a8ff 585 __IO uint32_t TDB1;
bogdanm 0:9b334a45a8ff 586 __IO uint32_t TFI2;
bogdanm 0:9b334a45a8ff 587 __IO uint32_t TID2;
bogdanm 0:9b334a45a8ff 588 __IO uint32_t TDA2;
bogdanm 0:9b334a45a8ff 589 __IO uint32_t TDB2;
bogdanm 0:9b334a45a8ff 590 __IO uint32_t TFI3;
bogdanm 0:9b334a45a8ff 591 __IO uint32_t TID3;
bogdanm 0:9b334a45a8ff 592 __IO uint32_t TDA3;
bogdanm 0:9b334a45a8ff 593 __IO uint32_t TDB3;
bogdanm 0:9b334a45a8ff 594 } LPC_CAN_TypeDef;
bogdanm 0:9b334a45a8ff 595
bogdanm 0:9b334a45a8ff 596 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
bogdanm 0:9b334a45a8ff 597 typedef struct /* Common Registers */
bogdanm 0:9b334a45a8ff 598 {
bogdanm 0:9b334a45a8ff 599 __I uint32_t DMACIntStat;
bogdanm 0:9b334a45a8ff 600 __I uint32_t DMACIntTCStat;
bogdanm 0:9b334a45a8ff 601 __O uint32_t DMACIntTCClear;
bogdanm 0:9b334a45a8ff 602 __I uint32_t DMACIntErrStat;
bogdanm 0:9b334a45a8ff 603 __O uint32_t DMACIntErrClr;
bogdanm 0:9b334a45a8ff 604 __I uint32_t DMACRawIntTCStat;
bogdanm 0:9b334a45a8ff 605 __I uint32_t DMACRawIntErrStat;
bogdanm 0:9b334a45a8ff 606 __I uint32_t DMACEnbldChns;
bogdanm 0:9b334a45a8ff 607 __IO uint32_t DMACSoftBReq;
bogdanm 0:9b334a45a8ff 608 __IO uint32_t DMACSoftSReq;
bogdanm 0:9b334a45a8ff 609 __IO uint32_t DMACSoftLBReq;
bogdanm 0:9b334a45a8ff 610 __IO uint32_t DMACSoftLSReq;
bogdanm 0:9b334a45a8ff 611 __IO uint32_t DMACConfig;
bogdanm 0:9b334a45a8ff 612 __IO uint32_t DMACSync;
bogdanm 0:9b334a45a8ff 613 } LPC_GPDMA_TypeDef;
bogdanm 0:9b334a45a8ff 614
bogdanm 0:9b334a45a8ff 615 typedef struct /* Channel Registers */
bogdanm 0:9b334a45a8ff 616 {
bogdanm 0:9b334a45a8ff 617 __IO uint32_t DMACCSrcAddr;
bogdanm 0:9b334a45a8ff 618 __IO uint32_t DMACCDestAddr;
bogdanm 0:9b334a45a8ff 619 __IO uint32_t DMACCLLI;
bogdanm 0:9b334a45a8ff 620 __IO uint32_t DMACCControl;
bogdanm 0:9b334a45a8ff 621 __IO uint32_t DMACCConfig;
bogdanm 0:9b334a45a8ff 622 } LPC_GPDMACH_TypeDef;
bogdanm 0:9b334a45a8ff 623
bogdanm 0:9b334a45a8ff 624 /*------------- Universal Serial Bus (USB) -----------------------------------*/
bogdanm 0:9b334a45a8ff 625 typedef struct
bogdanm 0:9b334a45a8ff 626 {
bogdanm 0:9b334a45a8ff 627 __I uint32_t HcRevision; /* USB Host Registers */
bogdanm 0:9b334a45a8ff 628 __IO uint32_t HcControl;
bogdanm 0:9b334a45a8ff 629 __IO uint32_t HcCommandStatus;
bogdanm 0:9b334a45a8ff 630 __IO uint32_t HcInterruptStatus;
bogdanm 0:9b334a45a8ff 631 __IO uint32_t HcInterruptEnable;
bogdanm 0:9b334a45a8ff 632 __IO uint32_t HcInterruptDisable;
bogdanm 0:9b334a45a8ff 633 __IO uint32_t HcHCCA;
bogdanm 0:9b334a45a8ff 634 __I uint32_t HcPeriodCurrentED;
bogdanm 0:9b334a45a8ff 635 __IO uint32_t HcControlHeadED;
bogdanm 0:9b334a45a8ff 636 __IO uint32_t HcControlCurrentED;
bogdanm 0:9b334a45a8ff 637 __IO uint32_t HcBulkHeadED;
bogdanm 0:9b334a45a8ff 638 __IO uint32_t HcBulkCurrentED;
bogdanm 0:9b334a45a8ff 639 __I uint32_t HcDoneHead;
bogdanm 0:9b334a45a8ff 640 __IO uint32_t HcFmInterval;
bogdanm 0:9b334a45a8ff 641 __I uint32_t HcFmRemaining;
bogdanm 0:9b334a45a8ff 642 __I uint32_t HcFmNumber;
bogdanm 0:9b334a45a8ff 643 __IO uint32_t HcPeriodicStart;
bogdanm 0:9b334a45a8ff 644 __IO uint32_t HcLSTreshold;
bogdanm 0:9b334a45a8ff 645 __IO uint32_t HcRhDescriptorA;
bogdanm 0:9b334a45a8ff 646 __IO uint32_t HcRhDescriptorB;
bogdanm 0:9b334a45a8ff 647 __IO uint32_t HcRhStatus;
bogdanm 0:9b334a45a8ff 648 __IO uint32_t HcRhPortStatus1;
bogdanm 0:9b334a45a8ff 649 __IO uint32_t HcRhPortStatus2;
bogdanm 0:9b334a45a8ff 650 uint32_t RESERVED0[40];
bogdanm 0:9b334a45a8ff 651 __I uint32_t Module_ID;
bogdanm 0:9b334a45a8ff 652
bogdanm 0:9b334a45a8ff 653 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
bogdanm 0:9b334a45a8ff 654 __IO uint32_t OTGIntEn;
bogdanm 0:9b334a45a8ff 655 __O uint32_t OTGIntSet;
bogdanm 0:9b334a45a8ff 656 __O uint32_t OTGIntClr;
bogdanm 0:9b334a45a8ff 657 __IO uint32_t OTGStCtrl;
bogdanm 0:9b334a45a8ff 658 __IO uint32_t OTGTmr;
bogdanm 0:9b334a45a8ff 659 uint32_t RESERVED1[58];
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
bogdanm 0:9b334a45a8ff 662 __IO uint32_t USBDevIntEn;
bogdanm 0:9b334a45a8ff 663 __O uint32_t USBDevIntClr;
bogdanm 0:9b334a45a8ff 664 __O uint32_t USBDevIntSet;
bogdanm 0:9b334a45a8ff 665
bogdanm 0:9b334a45a8ff 666 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
bogdanm 0:9b334a45a8ff 667 __I uint32_t USBCmdData;
bogdanm 0:9b334a45a8ff 668
bogdanm 0:9b334a45a8ff 669 __I uint32_t USBRxData; /* USB Device Transfer Registers */
bogdanm 0:9b334a45a8ff 670 __O uint32_t USBTxData;
bogdanm 0:9b334a45a8ff 671 __I uint32_t USBRxPLen;
bogdanm 0:9b334a45a8ff 672 __O uint32_t USBTxPLen;
bogdanm 0:9b334a45a8ff 673 __IO uint32_t USBCtrl;
bogdanm 0:9b334a45a8ff 674 __O uint32_t USBDevIntPri;
bogdanm 0:9b334a45a8ff 675
bogdanm 0:9b334a45a8ff 676 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
bogdanm 0:9b334a45a8ff 677 __IO uint32_t USBEpIntEn;
bogdanm 0:9b334a45a8ff 678 __O uint32_t USBEpIntClr;
bogdanm 0:9b334a45a8ff 679 __O uint32_t USBEpIntSet;
bogdanm 0:9b334a45a8ff 680 __O uint32_t USBEpIntPri;
bogdanm 0:9b334a45a8ff 681
bogdanm 0:9b334a45a8ff 682 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
bogdanm 0:9b334a45a8ff 683 __O uint32_t USBEpInd;
bogdanm 0:9b334a45a8ff 684 __IO uint32_t USBMaxPSize;
bogdanm 0:9b334a45a8ff 685
bogdanm 0:9b334a45a8ff 686 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
bogdanm 0:9b334a45a8ff 687 __O uint32_t USBDMARClr;
bogdanm 0:9b334a45a8ff 688 __O uint32_t USBDMARSet;
bogdanm 0:9b334a45a8ff 689 uint32_t RESERVED2[9];
bogdanm 0:9b334a45a8ff 690 __IO uint32_t USBUDCAH;
bogdanm 0:9b334a45a8ff 691 __I uint32_t USBEpDMASt;
bogdanm 0:9b334a45a8ff 692 __O uint32_t USBEpDMAEn;
bogdanm 0:9b334a45a8ff 693 __O uint32_t USBEpDMADis;
bogdanm 0:9b334a45a8ff 694 __I uint32_t USBDMAIntSt;
bogdanm 0:9b334a45a8ff 695 __IO uint32_t USBDMAIntEn;
bogdanm 0:9b334a45a8ff 696 uint32_t RESERVED3[2];
bogdanm 0:9b334a45a8ff 697 __I uint32_t USBEoTIntSt;
bogdanm 0:9b334a45a8ff 698 __O uint32_t USBEoTIntClr;
bogdanm 0:9b334a45a8ff 699 __O uint32_t USBEoTIntSet;
bogdanm 0:9b334a45a8ff 700 __I uint32_t USBNDDRIntSt;
bogdanm 0:9b334a45a8ff 701 __O uint32_t USBNDDRIntClr;
bogdanm 0:9b334a45a8ff 702 __O uint32_t USBNDDRIntSet;
bogdanm 0:9b334a45a8ff 703 __I uint32_t USBSysErrIntSt;
bogdanm 0:9b334a45a8ff 704 __O uint32_t USBSysErrIntClr;
bogdanm 0:9b334a45a8ff 705 __O uint32_t USBSysErrIntSet;
bogdanm 0:9b334a45a8ff 706 uint32_t RESERVED4[15];
bogdanm 0:9b334a45a8ff 707
bogdanm 0:9b334a45a8ff 708 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
bogdanm 0:9b334a45a8ff 709 __O uint32_t I2C_WO;
bogdanm 0:9b334a45a8ff 710 __I uint32_t I2C_STS;
bogdanm 0:9b334a45a8ff 711 __IO uint32_t I2C_CTL;
bogdanm 0:9b334a45a8ff 712 __IO uint32_t I2C_CLKHI;
bogdanm 0:9b334a45a8ff 713 __O uint32_t I2C_CLKLO;
bogdanm 0:9b334a45a8ff 714 uint32_t RESERVED5[823];
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716 union {
bogdanm 0:9b334a45a8ff 717 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
bogdanm 0:9b334a45a8ff 718 __IO uint32_t OTGClkCtrl;
bogdanm 0:9b334a45a8ff 719 };
bogdanm 0:9b334a45a8ff 720 union {
bogdanm 0:9b334a45a8ff 721 __I uint32_t USBClkSt;
bogdanm 0:9b334a45a8ff 722 __I uint32_t OTGClkSt;
bogdanm 0:9b334a45a8ff 723 };
bogdanm 0:9b334a45a8ff 724 } LPC_USB_TypeDef;
bogdanm 0:9b334a45a8ff 725
bogdanm 0:9b334a45a8ff 726 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
bogdanm 0:9b334a45a8ff 727 typedef struct
bogdanm 0:9b334a45a8ff 728 {
bogdanm 0:9b334a45a8ff 729 __IO uint32_t MAC1; /* MAC Registers */
bogdanm 0:9b334a45a8ff 730 __IO uint32_t MAC2;
bogdanm 0:9b334a45a8ff 731 __IO uint32_t IPGT;
bogdanm 0:9b334a45a8ff 732 __IO uint32_t IPGR;
bogdanm 0:9b334a45a8ff 733 __IO uint32_t CLRT;
bogdanm 0:9b334a45a8ff 734 __IO uint32_t MAXF;
bogdanm 0:9b334a45a8ff 735 __IO uint32_t SUPP;
bogdanm 0:9b334a45a8ff 736 __IO uint32_t TEST;
bogdanm 0:9b334a45a8ff 737 __IO uint32_t MCFG;
bogdanm 0:9b334a45a8ff 738 __IO uint32_t MCMD;
bogdanm 0:9b334a45a8ff 739 __IO uint32_t MADR;
bogdanm 0:9b334a45a8ff 740 __O uint32_t MWTD;
bogdanm 0:9b334a45a8ff 741 __I uint32_t MRDD;
bogdanm 0:9b334a45a8ff 742 __I uint32_t MIND;
bogdanm 0:9b334a45a8ff 743 uint32_t RESERVED0[2];
bogdanm 0:9b334a45a8ff 744 __IO uint32_t SA0;
bogdanm 0:9b334a45a8ff 745 __IO uint32_t SA1;
bogdanm 0:9b334a45a8ff 746 __IO uint32_t SA2;
bogdanm 0:9b334a45a8ff 747 uint32_t RESERVED1[45];
bogdanm 0:9b334a45a8ff 748 __IO uint32_t Command; /* Control Registers */
bogdanm 0:9b334a45a8ff 749 __I uint32_t Status;
bogdanm 0:9b334a45a8ff 750 __IO uint32_t RxDescriptor;
bogdanm 0:9b334a45a8ff 751 __IO uint32_t RxStatus;
bogdanm 0:9b334a45a8ff 752 __IO uint32_t RxDescriptorNumber;
bogdanm 0:9b334a45a8ff 753 __I uint32_t RxProduceIndex;
bogdanm 0:9b334a45a8ff 754 __IO uint32_t RxConsumeIndex;
bogdanm 0:9b334a45a8ff 755 __IO uint32_t TxDescriptor;
bogdanm 0:9b334a45a8ff 756 __IO uint32_t TxStatus;
bogdanm 0:9b334a45a8ff 757 __IO uint32_t TxDescriptorNumber;
bogdanm 0:9b334a45a8ff 758 __IO uint32_t TxProduceIndex;
bogdanm 0:9b334a45a8ff 759 __I uint32_t TxConsumeIndex;
bogdanm 0:9b334a45a8ff 760 uint32_t RESERVED2[10];
bogdanm 0:9b334a45a8ff 761 __I uint32_t TSV0;
bogdanm 0:9b334a45a8ff 762 __I uint32_t TSV1;
bogdanm 0:9b334a45a8ff 763 __I uint32_t RSV;
bogdanm 0:9b334a45a8ff 764 uint32_t RESERVED3[3];
bogdanm 0:9b334a45a8ff 765 __IO uint32_t FlowControlCounter;
bogdanm 0:9b334a45a8ff 766 __I uint32_t FlowControlStatus;
bogdanm 0:9b334a45a8ff 767 uint32_t RESERVED4[34];
bogdanm 0:9b334a45a8ff 768 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
bogdanm 0:9b334a45a8ff 769 __IO uint32_t RxFilterWoLStatus;
bogdanm 0:9b334a45a8ff 770 __IO uint32_t RxFilterWoLClear;
bogdanm 0:9b334a45a8ff 771 uint32_t RESERVED5;
bogdanm 0:9b334a45a8ff 772 __IO uint32_t HashFilterL;
bogdanm 0:9b334a45a8ff 773 __IO uint32_t HashFilterH;
bogdanm 0:9b334a45a8ff 774 uint32_t RESERVED6[882];
bogdanm 0:9b334a45a8ff 775 __I uint32_t IntStatus; /* Module Control Registers */
bogdanm 0:9b334a45a8ff 776 __IO uint32_t IntEnable;
bogdanm 0:9b334a45a8ff 777 __O uint32_t IntClear;
bogdanm 0:9b334a45a8ff 778 __O uint32_t IntSet;
bogdanm 0:9b334a45a8ff 779 uint32_t RESERVED7;
bogdanm 0:9b334a45a8ff 780 __IO uint32_t PowerDown;
bogdanm 0:9b334a45a8ff 781 uint32_t RESERVED8;
bogdanm 0:9b334a45a8ff 782 __IO uint32_t Module_ID;
bogdanm 0:9b334a45a8ff 783 } LPC_EMAC_TypeDef;
bogdanm 0:9b334a45a8ff 784
bogdanm 0:9b334a45a8ff 785 /*-------------------- External Memory Controller (EMC) ----------------------*/
bogdanm 0:9b334a45a8ff 786 typedef struct
bogdanm 0:9b334a45a8ff 787 {
bogdanm 0:9b334a45a8ff 788 __IO uint32_t EMCControl;
bogdanm 0:9b334a45a8ff 789 __I uint32_t EMCStatus;
bogdanm 0:9b334a45a8ff 790 __IO uint32_t EMCConfig;
bogdanm 0:9b334a45a8ff 791 uint32_t RESERVED1[5];
bogdanm 0:9b334a45a8ff 792 __IO uint32_t EMCDynamicControl;
bogdanm 0:9b334a45a8ff 793 __IO uint32_t EMCDynamicRefresh;
bogdanm 0:9b334a45a8ff 794 __IO uint32_t EMCDynamicReadConfig;
bogdanm 0:9b334a45a8ff 795 uint32_t RESERVED2;
bogdanm 0:9b334a45a8ff 796 __IO uint32_t EMCDynamicRP;
bogdanm 0:9b334a45a8ff 797 __IO uint32_t EMCDynamicRAS;
bogdanm 0:9b334a45a8ff 798 __IO uint32_t EMCDynamicSREX;
bogdanm 0:9b334a45a8ff 799 __IO uint32_t EMCDynamicAPR;
bogdanm 0:9b334a45a8ff 800 __IO uint32_t EMCDynamicDAL;
bogdanm 0:9b334a45a8ff 801 __IO uint32_t EMCDynamicWR;
bogdanm 0:9b334a45a8ff 802 __IO uint32_t EMCDynamicRC;
bogdanm 0:9b334a45a8ff 803 __IO uint32_t EMCDynamicRFC;
bogdanm 0:9b334a45a8ff 804 __IO uint32_t EMCDynamicXSR;
bogdanm 0:9b334a45a8ff 805 __IO uint32_t EMCDynamicRRD;
bogdanm 0:9b334a45a8ff 806 __IO uint32_t EMCDynamicMRD;
bogdanm 0:9b334a45a8ff 807 uint32_t RESERVED3[9];
bogdanm 0:9b334a45a8ff 808 __IO uint32_t EMCStaticExtendedWait;
bogdanm 0:9b334a45a8ff 809 uint32_t RESERVED4[31];
bogdanm 0:9b334a45a8ff 810 __IO uint32_t EMCDynamicConfig0;
bogdanm 0:9b334a45a8ff 811 __IO uint32_t EMCDynamicRasCas0;
bogdanm 0:9b334a45a8ff 812 uint32_t RESERVED5[6];
bogdanm 0:9b334a45a8ff 813 __IO uint32_t EMCDynamicConfig1;
bogdanm 0:9b334a45a8ff 814 __IO uint32_t EMCDynamicRasCas1;
bogdanm 0:9b334a45a8ff 815 uint32_t RESERVED6[6];
bogdanm 0:9b334a45a8ff 816 __IO uint32_t EMCDynamicConfic2;
bogdanm 0:9b334a45a8ff 817 __IO uint32_t EMCDynamicRasCas2;
bogdanm 0:9b334a45a8ff 818 uint32_t RESERVED7[6];
bogdanm 0:9b334a45a8ff 819 __IO uint32_t EMCDynamicConfig3;
bogdanm 0:9b334a45a8ff 820 __IO uint32_t EMCDynamicRasCas3;
bogdanm 0:9b334a45a8ff 821 uint32_t RESERVED8[38];
bogdanm 0:9b334a45a8ff 822 __IO uint32_t EMCStaticConfig0;
bogdanm 0:9b334a45a8ff 823 __IO uint32_t EMCStaticWaitWen0;
bogdanm 0:9b334a45a8ff 824 __IO uint32_t EMCStaticWaitOen0;
bogdanm 0:9b334a45a8ff 825 __IO uint32_t EMCStaticWaitRd0;
bogdanm 0:9b334a45a8ff 826 __IO uint32_t EMCStaticWaitPage0;
bogdanm 0:9b334a45a8ff 827 __IO uint32_t EMCStaticWaitWr0;
bogdanm 0:9b334a45a8ff 828 __IO uint32_t EMCStaticWaitTurn0;
bogdanm 0:9b334a45a8ff 829 uint32_t RESERVED9;
bogdanm 0:9b334a45a8ff 830 __IO uint32_t EMCStaticConfig1;
bogdanm 0:9b334a45a8ff 831 __IO uint32_t EMCStaticWaitWen1;
bogdanm 0:9b334a45a8ff 832 __IO uint32_t EMCStaticWaitOen1;
bogdanm 0:9b334a45a8ff 833 __IO uint32_t EMCStaticWaitRd1;
bogdanm 0:9b334a45a8ff 834 __IO uint32_t EMCStaticWaitPage1;
bogdanm 0:9b334a45a8ff 835 __IO uint32_t EMCStaticWaitWr1;
bogdanm 0:9b334a45a8ff 836 __IO uint32_t EMCStaticWaitTurn1;
bogdanm 0:9b334a45a8ff 837 uint32_t RESERVED10;
bogdanm 0:9b334a45a8ff 838 __IO uint32_t EMCStaticConfig2;
bogdanm 0:9b334a45a8ff 839 __IO uint32_t EMCStaticWaitWen2;
bogdanm 0:9b334a45a8ff 840 __IO uint32_t EMCStaticWaitOen2;
bogdanm 0:9b334a45a8ff 841 __IO uint32_t EMCStaticWaitRd2;
bogdanm 0:9b334a45a8ff 842 __IO uint32_t EMCStaticWaitPage2;
bogdanm 0:9b334a45a8ff 843 __IO uint32_t EMCStaticWaitWr2;
bogdanm 0:9b334a45a8ff 844 __IO uint32_t EMCStaticWaitTurn2;
bogdanm 0:9b334a45a8ff 845 uint32_t RESERVED11;
bogdanm 0:9b334a45a8ff 846 __IO uint32_t EMCStaticConfig3;
bogdanm 0:9b334a45a8ff 847 __IO uint32_t EMCStaticWaitWen3;
bogdanm 0:9b334a45a8ff 848 __IO uint32_t EMCStaticWaitOen3;
bogdanm 0:9b334a45a8ff 849 __IO uint32_t EMCStaticWaitRd3;
bogdanm 0:9b334a45a8ff 850 __IO uint32_t EMCStaticWaitPage3;
bogdanm 0:9b334a45a8ff 851 __IO uint32_t EMCStaticWaitWr3;
bogdanm 0:9b334a45a8ff 852 __IO uint32_t EMCStaticWaitTurn3;
bogdanm 0:9b334a45a8ff 853 } LPC_EMC_TypeDef;
bogdanm 0:9b334a45a8ff 854 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 855 #pragma no_anon_unions
bogdanm 0:9b334a45a8ff 856 #endif
bogdanm 0:9b334a45a8ff 857
bogdanm 0:9b334a45a8ff 858 /******************************************************************************/
bogdanm 0:9b334a45a8ff 859 /* Peripheral memory map */
bogdanm 0:9b334a45a8ff 860 /******************************************************************************/
bogdanm 0:9b334a45a8ff 861 /* Base addresses */
bogdanm 0:9b334a45a8ff 862
bogdanm 0:9b334a45a8ff 863 /* AHB Peripheral # 0 */
bogdanm 0:9b334a45a8ff 864
bogdanm 0:9b334a45a8ff 865 /*
bogdanm 0:9b334a45a8ff 866 #define FLASH_BASE (0x00000000UL)
bogdanm 0:9b334a45a8ff 867 #define RAM_BASE (0x10000000UL)
bogdanm 0:9b334a45a8ff 868 #define GPIO_BASE (0x2009C000UL)
bogdanm 0:9b334a45a8ff 869 #define APB0_BASE (0x40000000UL)
bogdanm 0:9b334a45a8ff 870 #define APB1_BASE (0x40080000UL)
bogdanm 0:9b334a45a8ff 871 #define AHB_BASE (0x50000000UL)
bogdanm 0:9b334a45a8ff 872 #define CM3_BASE (0xE0000000UL)
bogdanm 0:9b334a45a8ff 873 */
bogdanm 0:9b334a45a8ff 874
bogdanm 0:9b334a45a8ff 875 // TODO - #define VIC_BASE_ADDR 0xFFFFF000
bogdanm 0:9b334a45a8ff 876
bogdanm 0:9b334a45a8ff 877 #define LPC_WDT_BASE (0xE0000000)
bogdanm 0:9b334a45a8ff 878 #define LPC_TIM0_BASE (0xE0004000)
bogdanm 0:9b334a45a8ff 879 #define LPC_TIM1_BASE (0xE0008000)
bogdanm 0:9b334a45a8ff 880 #define LPC_UART0_BASE (0xE000C000)
bogdanm 0:9b334a45a8ff 881 #define LPC_UART1_BASE (0xE0010000)
bogdanm 0:9b334a45a8ff 882 #define LPC_PWM1_BASE (0xE0018000)
bogdanm 0:9b334a45a8ff 883 #define LPC_I2C0_BASE (0xE001C000)
bogdanm 0:9b334a45a8ff 884 #define LPC_SPI_BASE (0xE0020000)
bogdanm 0:9b334a45a8ff 885 #define LPC_RTC_BASE (0xE0024000)
bogdanm 0:9b334a45a8ff 886 #define LPC_GPIOINT_BASE (0xE0028080)
bogdanm 0:9b334a45a8ff 887 #define LPC_PINCON_BASE (0xE002C000)
bogdanm 0:9b334a45a8ff 888 #define LPC_SSP1_BASE (0xE0030000)
bogdanm 0:9b334a45a8ff 889 #define LPC_ADC_BASE (0xE0034000)
bogdanm 0:9b334a45a8ff 890 #define LPC_CANAF_RAM_BASE (0xE0038000)
bogdanm 0:9b334a45a8ff 891 #define LPC_CANAF_BASE (0xE003C000)
bogdanm 0:9b334a45a8ff 892 #define LPC_CANCR_BASE (0xE0040000)
bogdanm 0:9b334a45a8ff 893 #define LPC_CAN1_BASE (0xE0044000)
bogdanm 0:9b334a45a8ff 894 #define LPC_CAN2_BASE (0xE0048000)
bogdanm 0:9b334a45a8ff 895 #define LPC_I2C1_BASE (0xE005C000)
bogdanm 0:9b334a45a8ff 896 #define LPC_SSP0_BASE (0xE0068000)
bogdanm 0:9b334a45a8ff 897 #define LPC_DAC_BASE (0xE006C000)
bogdanm 0:9b334a45a8ff 898 #define LPC_TIM2_BASE (0xE0070000)
bogdanm 0:9b334a45a8ff 899 #define LPC_TIM3_BASE (0xE0074000)
bogdanm 0:9b334a45a8ff 900 #define LPC_UART2_BASE (0xE0078000)
bogdanm 0:9b334a45a8ff 901 #define LPC_UART3_BASE (0xE007C000)
bogdanm 0:9b334a45a8ff 902 #define LPC_I2C2_BASE (0xE0080000)
bogdanm 0:9b334a45a8ff 903 #define LPC_I2S_BASE (0xE0088000)
bogdanm 0:9b334a45a8ff 904 #define LPC_MCI_BASE (0xE008C000)
bogdanm 0:9b334a45a8ff 905 #define LPC_SC_BASE (0xE01FC000)
bogdanm 0:9b334a45a8ff 906 #define LPC_EMAC_BASE (0xFFE00000)
bogdanm 0:9b334a45a8ff 907 #define LPC_GPDMA_BASE (0xFFE04000)
bogdanm 0:9b334a45a8ff 908 #define LPC_GPDMACH0_BASE (0xFFE04100)
bogdanm 0:9b334a45a8ff 909 #define LPC_GPDMACH1_BASE (0xFFE04120)
bogdanm 0:9b334a45a8ff 910 #define LPC_EMC_BASE (0xFFE08000)
bogdanm 0:9b334a45a8ff 911 #define LPC_USB_BASE (0xFFE0C000)
bogdanm 0:9b334a45a8ff 912 #define LPC_VIC_BASE (0xFFFFF000)
bogdanm 0:9b334a45a8ff 913
bogdanm 0:9b334a45a8ff 914 /* GPIOs */
bogdanm 0:9b334a45a8ff 915 #define LPC_GPIO0_BASE (0x3FFFC000)
bogdanm 0:9b334a45a8ff 916 #define LPC_GPIO1_BASE (0x3FFFC020)
bogdanm 0:9b334a45a8ff 917 #define LPC_GPIO2_BASE (0x3FFFC040)
bogdanm 0:9b334a45a8ff 918 #define LPC_GPIO3_BASE (0x3FFFC060)
bogdanm 0:9b334a45a8ff 919 #define LPC_GPIO4_BASE (0x3FFFC080)
bogdanm 0:9b334a45a8ff 920
bogdanm 0:9b334a45a8ff 921
bogdanm 0:9b334a45a8ff 922 /******************************************************************************/
bogdanm 0:9b334a45a8ff 923 /* Peripheral declaration */
bogdanm 0:9b334a45a8ff 924 /******************************************************************************/
bogdanm 0:9b334a45a8ff 925 #define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
bogdanm 0:9b334a45a8ff 926 #define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
bogdanm 0:9b334a45a8ff 927 #define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
bogdanm 0:9b334a45a8ff 928 #define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
bogdanm 0:9b334a45a8ff 929 #define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
bogdanm 0:9b334a45a8ff 930 #define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
bogdanm 0:9b334a45a8ff 931 #define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
bogdanm 0:9b334a45a8ff 932 #define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
bogdanm 0:9b334a45a8ff 933 #define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
bogdanm 0:9b334a45a8ff 934 #define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
bogdanm 0:9b334a45a8ff 935 #define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
bogdanm 0:9b334a45a8ff 936 #define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
bogdanm 0:9b334a45a8ff 937 #define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
bogdanm 0:9b334a45a8ff 938 #define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
bogdanm 0:9b334a45a8ff 939 #define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
bogdanm 0:9b334a45a8ff 940 #define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
bogdanm 0:9b334a45a8ff 941 #define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
bogdanm 0:9b334a45a8ff 942 #define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
bogdanm 0:9b334a45a8ff 943 #define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
bogdanm 0:9b334a45a8ff 944 #define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
bogdanm 0:9b334a45a8ff 945 #define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
bogdanm 0:9b334a45a8ff 946 #define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
bogdanm 0:9b334a45a8ff 947 #define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
bogdanm 0:9b334a45a8ff 948 #define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
bogdanm 0:9b334a45a8ff 949 #define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
bogdanm 0:9b334a45a8ff 950 #define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
bogdanm 0:9b334a45a8ff 951 #define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
bogdanm 0:9b334a45a8ff 952 #define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
bogdanm 0:9b334a45a8ff 953 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
bogdanm 0:9b334a45a8ff 954 #define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
bogdanm 0:9b334a45a8ff 955 #define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
bogdanm 0:9b334a45a8ff 956 #define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
bogdanm 0:9b334a45a8ff 957 #define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
bogdanm 0:9b334a45a8ff 958 #define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
bogdanm 0:9b334a45a8ff 959 #define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
bogdanm 0:9b334a45a8ff 960 #define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
bogdanm 0:9b334a45a8ff 961 #define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
bogdanm 0:9b334a45a8ff 962 #define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
bogdanm 0:9b334a45a8ff 963 #define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
bogdanm 0:9b334a45a8ff 964 #define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
bogdanm 0:9b334a45a8ff 965 #define LPC_EMC (( LPC_EMC_TypeDef *) LPC_EMC_BASE)
bogdanm 0:9b334a45a8ff 966
bogdanm 0:9b334a45a8ff 967 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 968 }
bogdanm 0:9b334a45a8ff 969 #endif
bogdanm 0:9b334a45a8ff 970
bogdanm 0:9b334a45a8ff 971 #endif // __LPC24xx_H
bogdanm 0:9b334a45a8ff 972