test / EALib

A library with drivers for different peripherals on the LPC4088 QuickStart Board or related add-on boards.

Dependencies:   FATFileSystem

Dependents:   bare

Fork of EALib by EmbeddedArtists AB

gpdma.cpp@13:64f3dd338612, 2014-03-27 (annotated)

Committer:
koiamk
Date:
Thu Mar 27 22:43:39 2014 +0000
Revision:
13:64f3dd338612
Parent:
12:15597e45eea0 
o;

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embeddedartists 12:15597e45eea0 1 /*
embeddedartists 12:15597e45eea0 2 * Copyright 2013 Embedded Artists AB
embeddedartists 12:15597e45eea0 3 *
embeddedartists 12:15597e45eea0 4 * Licensed under the Apache License, Version 2.0 (the "License");
embeddedartists 12:15597e45eea0 5 * you may not use this file except in compliance with the License.
embeddedartists 12:15597e45eea0 6 * You may obtain a copy of the License at
embeddedartists 12:15597e45eea0 7 *
embeddedartists 12:15597e45eea0 8 * http://www.apache.org/licenses/LICENSE-2.0
embeddedartists 12:15597e45eea0 9 *
embeddedartists 12:15597e45eea0 10 * Unless required by applicable law or agreed to in writing, software
embeddedartists 12:15597e45eea0 11 * distributed under the License is distributed on an "AS IS" BASIS,
embeddedartists 12:15597e45eea0 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
embeddedartists 12:15597e45eea0 13 * See the License for the specific language governing permissions and
embeddedartists 12:15597e45eea0 14 * limitations under the License.
embeddedartists 12:15597e45eea0 15 */
embeddedartists 0:0fdadbc3d852 16
embeddedartists 0:0fdadbc3d852 17 /******************************************************************************
embeddedartists 0:0fdadbc3d852 18 * Includes
embeddedartists 0:0fdadbc3d852 19 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 20
embeddedartists 0:0fdadbc3d852 21 #include "gpdma.h"
embeddedartists 0:0fdadbc3d852 22
embeddedartists 0:0fdadbc3d852 23 /******************************************************************************
embeddedartists 0:0fdadbc3d852 24 * Defines and typedefs
embeddedartists 0:0fdadbc3d852 25 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 26
embeddedartists 0:0fdadbc3d852 27 #define NUM_GPDMA_CHANNELS 8
embeddedartists 0:0fdadbc3d852 28
embeddedartists 0:0fdadbc3d852 29 #define GPDMACH(__x) ((LPC_GPDMACH_TypeDef*)(LPC_GPDMACH0_BASE + (0x20 * (__x))))
embeddedartists 0:0fdadbc3d852 30
embeddedartists 0:0fdadbc3d852 31 #define CH_MASK(__ch) (((1UL << (__ch)) & 0xFF))
embeddedartists 0:0fdadbc3d852 32
embeddedartists 0:0fdadbc3d852 33 /**
embeddedartists 0:0fdadbc3d852 34 * @brief GPDMA request connections
embeddedartists 0:0fdadbc3d852 35 */
embeddedartists 0:0fdadbc3d852 36 #define GPDMA_CONN_MEMORY ((0UL))
embeddedartists 0:0fdadbc3d852 37 #define GPDMA_CONN_SDC ((1UL)) /*!< SD card */
embeddedartists 0:0fdadbc3d852 38
embeddedartists 0:0fdadbc3d852 39 /**
embeddedartists 0:0fdadbc3d852 40 * @brief Macro defines for DMA channel control registers
embeddedartists 0:0fdadbc3d852 41 */
embeddedartists 0:0fdadbc3d852 42 #define GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0)) /*!< Transfer size*/
embeddedartists 0:0fdadbc3d852 43 #define GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12)) /*!< Source burst size*/
embeddedartists 0:0fdadbc3d852 44 #define GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15)) /*!< Destination burst size*/
embeddedartists 0:0fdadbc3d852 45 #define GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18)) /*!< Source transfer width*/
embeddedartists 0:0fdadbc3d852 46 #define GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21)) /*!< Destination transfer width*/
embeddedartists 0:0fdadbc3d852 47 #define GPDMA_DMACCxControl_SI ((1UL << 26)) /*!< Source increment*/
embeddedartists 0:0fdadbc3d852 48 #define GPDMA_DMACCxControl_DI ((1UL << 27)) /*!< Destination increment*/
embeddedartists 0:0fdadbc3d852 49 #define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 0
embeddedartists 0:0fdadbc3d852 50 #define GPDMA_DMACCxControl_DestTransUseAHBMaster1 0
embeddedartists 0:0fdadbc3d852 51 #define GPDMA_DMACCxControl_Prot1 ((1UL << 28)) /*!< Indicates that the access is in user mode or privileged mode*/
embeddedartists 0:0fdadbc3d852 52 #define GPDMA_DMACCxControl_Prot2 ((1UL << 29)) /*!< Indicates that the access is bufferable or not bufferable*/
embeddedartists 0:0fdadbc3d852 53 #define GPDMA_DMACCxControl_Prot3 ((1UL << 30)) /*!< Indicates that the access is cacheable or not cacheable*/
embeddedartists 0:0fdadbc3d852 54 #define GPDMA_DMACCxControl_I ((1UL << 31)) /*!< Terminal count interrupt enable bit */
embeddedartists 0:0fdadbc3d852 55
embeddedartists 0:0fdadbc3d852 56 /**
embeddedartists 0:0fdadbc3d852 57 * @brief GPDMA Burst size in Source and Destination definitions
embeddedartists 0:0fdadbc3d852 58 */
embeddedartists 0:0fdadbc3d852 59 #define GPDMA_BSIZE_1 ((0UL)) /*!< Burst size = 1 */
embeddedartists 0:0fdadbc3d852 60 #define GPDMA_BSIZE_4 ((1UL)) /*!< Burst size = 4 */
embeddedartists 0:0fdadbc3d852 61 #define GPDMA_BSIZE_8 ((2UL)) /*!< Burst size = 8 */
embeddedartists 0:0fdadbc3d852 62 #define GPDMA_BSIZE_16 ((3UL)) /*!< Burst size = 16 */
embeddedartists 0:0fdadbc3d852 63 #define GPDMA_BSIZE_32 ((4UL)) /*!< Burst size = 32 */
embeddedartists 0:0fdadbc3d852 64 #define GPDMA_BSIZE_64 ((5UL)) /*!< Burst size = 64 */
embeddedartists 0:0fdadbc3d852 65 #define GPDMA_BSIZE_128 ((6UL)) /*!< Burst size = 128 */
embeddedartists 0:0fdadbc3d852 66 #define GPDMA_BSIZE_256 ((7UL)) /*!< Burst size = 256 */
embeddedartists 0:0fdadbc3d852 67
embeddedartists 0:0fdadbc3d852 68 /**
embeddedartists 0:0fdadbc3d852 69 * @brief Width in Source transfer width and Destination transfer width definitions
embeddedartists 0:0fdadbc3d852 70 */
embeddedartists 0:0fdadbc3d852 71 #define GPDMA_WIDTH_BYTE ((0UL)) /*!< Width = 1 byte */
embeddedartists 0:0fdadbc3d852 72 #define GPDMA_WIDTH_HALFWORD ((1UL)) /*!< Width = 2 bytes */
embeddedartists 0:0fdadbc3d852 73 #define GPDMA_WIDTH_WORD ((2UL)) /*!< Width = 4 bytes */
embeddedartists 0:0fdadbc3d852 74
embeddedartists 0:0fdadbc3d852 75 /**
embeddedartists 0:0fdadbc3d852 76 * @brief Macro defines for DMA Configuration register
embeddedartists 0:0fdadbc3d852 77 */
embeddedartists 0:0fdadbc3d852 78 #define GPDMA_DMACConfig_E ((0x01)) /*!< DMA Controller enable*/
embeddedartists 0:0fdadbc3d852 79 #define GPDMA_DMACConfig_M ((0x02)) /*!< AHB Master endianness configuration*/
embeddedartists 0:0fdadbc3d852 80 #define GPDMA_DMACConfig_BITMASK ((0x03))
embeddedartists 0:0fdadbc3d852 81
embeddedartists 0:0fdadbc3d852 82 /**
embeddedartists 0:0fdadbc3d852 83 * @brief Macro defines for DMA Channel Configuration registers
embeddedartists 0:0fdadbc3d852 84 */
embeddedartists 0:0fdadbc3d852 85 #define GPDMA_DMACCxConfig_E ((1UL << 0)) /*!< DMA control enable*/
embeddedartists 0:0fdadbc3d852 86 #define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1)) /*!< Source peripheral*/
embeddedartists 0:0fdadbc3d852 87 #define GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6)) /*!< Destination peripheral*/
embeddedartists 0:0fdadbc3d852 88 #define GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11)) /*!< This value indicates the type of transfer*/
embeddedartists 0:0fdadbc3d852 89 #define GPDMA_DMACCxConfig_IE ((1UL << 14)) /*!< Interrupt error mask*/
embeddedartists 0:0fdadbc3d852 90 #define GPDMA_DMACCxConfig_ITC ((1UL << 15)) /*!< Terminal count interrupt mask*/
embeddedartists 0:0fdadbc3d852 91 #define GPDMA_DMACCxConfig_L ((1UL << 16)) /*!< Lock*/
embeddedartists 0:0fdadbc3d852 92 #define GPDMA_DMACCxConfig_A ((1UL << 17)) /*!< Active*/
embeddedartists 0:0fdadbc3d852 93 #define GPDMA_DMACCxConfig_H ((1UL << 18)) /*!< Halt*/
embeddedartists 0:0fdadbc3d852 94
embeddedartists 0:0fdadbc3d852 95 /**
embeddedartists 0:0fdadbc3d852 96 * @brief GPDMA structure using for DMA configuration
embeddedartists 0:0fdadbc3d852 97 */
embeddedartists 0:0fdadbc3d852 98 typedef struct {
embeddedartists 0:0fdadbc3d852 99 uint32_t ChannelNum; /*!< DMA channel number, should be in
embeddedartists 0:0fdadbc3d852 100 * range from 0 to 7.
embeddedartists 0:0fdadbc3d852 101 * Note: DMA channel 0 has the highest priority
embeddedartists 0:0fdadbc3d852 102 * and DMA channel 7 the lowest priority.
embeddedartists 0:0fdadbc3d852 103 */
embeddedartists 0:0fdadbc3d852 104 uint32_t TransferSize; /*!< Length/Size of transfer */
embeddedartists 0:0fdadbc3d852 105 uint32_t TransferWidth; /*!< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
embeddedartists 0:0fdadbc3d852 106 uint32_t SrcAddr; /*!< Physical Source Address, used in case TransferType is chosen as
embeddedartists 0:0fdadbc3d852 107 * GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
embeddedartists 0:0fdadbc3d852 108 uint32_t DstAddr; /*!< Physical Destination Address, used in case TransferType is chosen as
embeddedartists 0:0fdadbc3d852 109 * GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
embeddedartists 0:0fdadbc3d852 110 uint32_t TransferType; /*!< Transfer Type, should be one of the following:
embeddedartists 0:0fdadbc3d852 111 * - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
embeddedartists 0:0fdadbc3d852 112 * - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
embeddedartists 0:0fdadbc3d852 113 * - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
embeddedartists 0:0fdadbc3d852 114 * - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
embeddedartists 0:0fdadbc3d852 115 */
embeddedartists 0:0fdadbc3d852 116 } GPDMA_Channel_CFG_T;
embeddedartists 0:0fdadbc3d852 117
embeddedartists 0:0fdadbc3d852 118 /******************************************************************************
embeddedartists 0:0fdadbc3d852 119 * External global variables
embeddedartists 0:0fdadbc3d852 120 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 121
embeddedartists 0:0fdadbc3d852 122 /******************************************************************************
embeddedartists 0:0fdadbc3d852 123 * Local variables
embeddedartists 0:0fdadbc3d852 124 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 125
embeddedartists 0:0fdadbc3d852 126 static bool used_channels[NUM_GPDMA_CHANNELS];
embeddedartists 0:0fdadbc3d852 127
embeddedartists 0:0fdadbc3d852 128 /******************************************************************************
embeddedartists 0:0fdadbc3d852 129 * Local Functions
embeddedartists 0:0fdadbc3d852 130 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 131
embeddedartists 0:0fdadbc3d852 132 static void gpdma_transfer(GPDMA_Channel_CFG_T* cfg,
embeddedartists 0:0fdadbc3d852 133 uint32_t CtrlWord,
embeddedartists 0:0fdadbc3d852 134 uint32_t LinkListItem,
embeddedartists 0:0fdadbc3d852 135 uint8_t SrcPeripheral,
embeddedartists 0:0fdadbc3d852 136 uint8_t DstPeripheral)
embeddedartists 0:0fdadbc3d852 137 {
embeddedartists 0:0fdadbc3d852 138 /* Get Channel pointer */
embeddedartists 0:0fdadbc3d852 139 LPC_GPDMACH_TypeDef* pCh = GPDMACH(cfg->ChannelNum);
embeddedartists 0:0fdadbc3d852 140
embeddedartists 0:0fdadbc3d852 141 /* Reset the Interrupt status */
embeddedartists 0:0fdadbc3d852 142 LPC_GPDMA->IntTCClear = CH_MASK(cfg->ChannelNum);
embeddedartists 0:0fdadbc3d852 143 LPC_GPDMA->IntErrClr = CH_MASK(cfg->ChannelNum);
embeddedartists 0:0fdadbc3d852 144
embeddedartists 0:0fdadbc3d852 145 /* Assign Linker List Item value */
embeddedartists 0:0fdadbc3d852 146 pCh->CLLI = LinkListItem;
embeddedartists 0:0fdadbc3d852 147
embeddedartists 0:0fdadbc3d852 148 /* Enable DMA channels, little endian */
embeddedartists 0:0fdadbc3d852 149 LPC_GPDMA->Config = GPDMA_DMACConfig_E;
embeddedartists 0:0fdadbc3d852 150 while (!(LPC_GPDMA->Config & GPDMA_DMACConfig_E)) {}
embeddedartists 0:0fdadbc3d852 151
embeddedartists 0:0fdadbc3d852 152 pCh->CSrcAddr = cfg->SrcAddr;
embeddedartists 0:0fdadbc3d852 153 pCh->CDestAddr = cfg->DstAddr;
embeddedartists 0:0fdadbc3d852 154
embeddedartists 0:0fdadbc3d852 155 /* Configure DMA Channel, enable Error Counter and Terminate counter */
embeddedartists 0:0fdadbc3d852 156 pCh->CConfig = GPDMA_DMACCxConfig_IE
embeddedartists 0:0fdadbc3d852 157 | GPDMA_DMACCxConfig_ITC
embeddedartists 0:0fdadbc3d852 158 | GPDMA_DMACCxConfig_TransferType((uint32_t) cfg->TransferType)
embeddedartists 0:0fdadbc3d852 159 | GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral)
embeddedartists 0:0fdadbc3d852 160 | GPDMA_DMACCxConfig_DestPeripheral(DstPeripheral);
embeddedartists 0:0fdadbc3d852 161
embeddedartists 0:0fdadbc3d852 162 pCh->CControl = CtrlWord;
embeddedartists 0:0fdadbc3d852 163
embeddedartists 0:0fdadbc3d852 164 /* Start the Channel */
embeddedartists 0:0fdadbc3d852 165 pCh->CConfig |= GPDMA_DMACCxConfig_E;
embeddedartists 0:0fdadbc3d852 166 }
embeddedartists 0:0fdadbc3d852 167
embeddedartists 0:0fdadbc3d852 168 /******************************************************************************
embeddedartists 0:0fdadbc3d852 169 * Public Functions
embeddedartists 0:0fdadbc3d852 170 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 171
embeddedartists 0:0fdadbc3d852 172 void gpdma_init()
embeddedartists 0:0fdadbc3d852 173 {
embeddedartists 0:0fdadbc3d852 174 uint8_t i;
embeddedartists 0:0fdadbc3d852 175
embeddedartists 0:0fdadbc3d852 176 /* Enable GPDMA master clock */
embeddedartists 0:0fdadbc3d852 177 LPC_SC->PCONP |= (1<<29);
embeddedartists 0:0fdadbc3d852 178
embeddedartists 0:0fdadbc3d852 179 /* Reset all channel configuration register */
embeddedartists 0:0fdadbc3d852 180 for (i = 0; i < NUM_GPDMA_CHANNELS; i++) {
embeddedartists 0:0fdadbc3d852 181 GPDMACH(i)->CConfig = 0;
embeddedartists 0:0fdadbc3d852 182 }
embeddedartists 0:0fdadbc3d852 183
embeddedartists 0:0fdadbc3d852 184 /* Clear all DMA interrupt and error flag */
embeddedartists 0:0fdadbc3d852 185 LPC_GPDMA->IntTCClear = 0xFF;
embeddedartists 0:0fdadbc3d852 186 LPC_GPDMA->IntErrClr = 0xFF;
embeddedartists 0:0fdadbc3d852 187
embeddedartists 0:0fdadbc3d852 188 /* Reset all channels are free */
embeddedartists 0:0fdadbc3d852 189 for (int i = 0; i < NUM_GPDMA_CHANNELS; i++)
embeddedartists 0:0fdadbc3d852 190 {
embeddedartists 0:0fdadbc3d852 191 used_channels[i] = false;
embeddedartists 0:0fdadbc3d852 192 }
embeddedartists 0:0fdadbc3d852 193 }
embeddedartists 0:0fdadbc3d852 194
embeddedartists 0:0fdadbc3d852 195 void gpdma_deinit()
embeddedartists 0:0fdadbc3d852 196 {
embeddedartists 0:0fdadbc3d852 197 /* Disable GPDMA master clock */
embeddedartists 0:0fdadbc3d852 198 LPC_SC->PCONP &= ~(1<<29);
embeddedartists 0:0fdadbc3d852 199 }
embeddedartists 0:0fdadbc3d852 200
embeddedartists 0:0fdadbc3d852 201 void gpdma_stop(uint8_t ChannelNum)
embeddedartists 0:0fdadbc3d852 202 {
embeddedartists 0:0fdadbc3d852 203 if (ChannelNum >= NUM_GPDMA_CHANNELS) {
embeddedartists 0:0fdadbc3d852 204 return;
embeddedartists 0:0fdadbc3d852 205 }
embeddedartists 0:0fdadbc3d852 206
embeddedartists 0:0fdadbc3d852 207 /* Disable channel */
embeddedartists 0:0fdadbc3d852 208 GPDMACH(ChannelNum)->CConfig &= ~GPDMA_DMACCxConfig_E;
embeddedartists 0:0fdadbc3d852 209
embeddedartists 0:0fdadbc3d852 210 /* check terminal count interrupt request status for DMA */
embeddedartists 0:0fdadbc3d852 211 if (LPC_GPDMA->IntTCStat & CH_MASK(ChannelNum)) {
embeddedartists 0:0fdadbc3d852 212 /* Clear terminate counter Interrupt pending */
embeddedartists 0:0fdadbc3d852 213 LPC_GPDMA->IntTCClear = CH_MASK(ChannelNum);
embeddedartists 0:0fdadbc3d852 214 }
embeddedartists 0:0fdadbc3d852 215
embeddedartists 0:0fdadbc3d852 216 /* check status of the error interrupt for DMA channels */
embeddedartists 0:0fdadbc3d852 217 if (LPC_GPDMA->IntErrStat & CH_MASK(ChannelNum)) {
embeddedartists 0:0fdadbc3d852 218 /* clear the error interrupt request */
embeddedartists 0:0fdadbc3d852 219 LPC_GPDMA->IntErrClr = CH_MASK(ChannelNum);
embeddedartists 0:0fdadbc3d852 220 }
embeddedartists 0:0fdadbc3d852 221
embeddedartists 0:0fdadbc3d852 222 used_channels[ChannelNum] = false;
embeddedartists 0:0fdadbc3d852 223 }
embeddedartists 0:0fdadbc3d852 224
embeddedartists 0:0fdadbc3d852 225 bool gpdma_interrupt(uint8_t ChannelNum)
embeddedartists 0:0fdadbc3d852 226 {
embeddedartists 0:0fdadbc3d852 227 /* check status of DMA channel interrupts */
embeddedartists 0:0fdadbc3d852 228 if (LPC_GPDMA->IntStat & CH_MASK(ChannelNum)) {
embeddedartists 0:0fdadbc3d852 229 /* Check counter terminal status */
embeddedartists 0:0fdadbc3d852 230 if (LPC_GPDMA->IntTCStat & CH_MASK(ChannelNum)) {
embeddedartists 0:0fdadbc3d852 231 /* Clear terminate counter Interrupt pending */
embeddedartists 0:0fdadbc3d852 232 LPC_GPDMA->IntTCClear = CH_MASK(ChannelNum);
embeddedartists 0:0fdadbc3d852 233 return true;
embeddedartists 0:0fdadbc3d852 234 }
embeddedartists 0:0fdadbc3d852 235 /* Check error terminal status */
embeddedartists 0:0fdadbc3d852 236 if (LPC_GPDMA->IntErrStat & CH_MASK(ChannelNum)) {
embeddedartists 0:0fdadbc3d852 237 /* Clear error counter Interrupt pending */
embeddedartists 0:0fdadbc3d852 238 LPC_GPDMA->IntErrClr = CH_MASK(ChannelNum);
embeddedartists 0:0fdadbc3d852 239 return false;
embeddedartists 0:0fdadbc3d852 240 }
embeddedartists 0:0fdadbc3d852 241 }
embeddedartists 0:0fdadbc3d852 242 return false;
embeddedartists 0:0fdadbc3d852 243 }
embeddedartists 0:0fdadbc3d852 244
embeddedartists 0:0fdadbc3d852 245 bool gpdma_getFreeChannel(uint8_t* pCh)
embeddedartists 0:0fdadbc3d852 246 {
embeddedartists 0:0fdadbc3d852 247 for (int i = 0; i < NUM_GPDMA_CHANNELS; i++)
embeddedartists 0:0fdadbc3d852 248 {
embeddedartists 0:0fdadbc3d852 249 if ((!used_channels[i]) && ((LPC_GPDMA->EnbldChns & CH_MASK(i)) == 0))
embeddedartists 0:0fdadbc3d852 250 {
embeddedartists 0:0fdadbc3d852 251 used_channels[i] = true;
embeddedartists 0:0fdadbc3d852 252 *pCh = i;
embeddedartists 0:0fdadbc3d852 253 return true;
embeddedartists 0:0fdadbc3d852 254 }
embeddedartists 0:0fdadbc3d852 255 }
embeddedartists 0:0fdadbc3d852 256 return false;
embeddedartists 0:0fdadbc3d852 257 }
embeddedartists 0:0fdadbc3d852 258
embeddedartists 0:0fdadbc3d852 259 bool gpdma_transfer_to_mci(uint8_t ChannelNum,
embeddedartists 0:0fdadbc3d852 260 uint32_t src,
embeddedartists 0:0fdadbc3d852 261 uint32_t Size)
embeddedartists 0:0fdadbc3d852 262 {
embeddedartists 0:0fdadbc3d852 263 GPDMA_Channel_CFG_T cfg;
embeddedartists 0:0fdadbc3d852 264 cfg.ChannelNum = ChannelNum;
embeddedartists 0:0fdadbc3d852 265 cfg.TransferType = GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL;
embeddedartists 0:0fdadbc3d852 266 cfg.TransferSize = Size;
embeddedartists 0:0fdadbc3d852 267 cfg.TransferWidth = 0;
embeddedartists 0:0fdadbc3d852 268 cfg.SrcAddr = src;
embeddedartists 0:0fdadbc3d852 269 cfg.DstAddr = (uint32_t) (&LPC_MCI->FIFO);
embeddedartists 0:0fdadbc3d852 270
embeddedartists 0:0fdadbc3d852 271 uint32_t ctrl_word =
embeddedartists 0:0fdadbc3d852 272 GPDMA_DMACCxControl_TransferSize((uint32_t) cfg.TransferSize)
embeddedartists 0:0fdadbc3d852 273 | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_8)
embeddedartists 0:0fdadbc3d852 274 | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_8)
embeddedartists 0:0fdadbc3d852 275 | GPDMA_DMACCxControl_SWidth(GPDMA_WIDTH_WORD)
embeddedartists 0:0fdadbc3d852 276 | GPDMA_DMACCxControl_DWidth(GPDMA_WIDTH_WORD)
embeddedartists 0:0fdadbc3d852 277 | GPDMA_DMACCxControl_DestTransUseAHBMaster1
embeddedartists 0:0fdadbc3d852 278 | GPDMA_DMACCxControl_SI
embeddedartists 0:0fdadbc3d852 279 | GPDMA_DMACCxControl_I;
embeddedartists 0:0fdadbc3d852 280
embeddedartists 0:0fdadbc3d852 281 if (LPC_GPDMA->EnbldChns & CH_MASK(ChannelNum)) {
embeddedartists 0:0fdadbc3d852 282 /* This channel is enabled, return ERROR, need to release this channel first */
embeddedartists 0:0fdadbc3d852 283 return false;
embeddedartists 0:0fdadbc3d852 284 }
embeddedartists 0:0fdadbc3d852 285
embeddedartists 0:0fdadbc3d852 286 /* Select SD card interface in the DMA MUX*/
embeddedartists 0:0fdadbc3d852 287 LPC_SC->DMAREQSEL &= ~(1 << 1);
embeddedartists 0:0fdadbc3d852 288
embeddedartists 0:0fdadbc3d852 289 gpdma_transfer(&cfg, ctrl_word, 0, GPDMA_CONN_MEMORY, GPDMA_CONN_SDC);
embeddedartists 0:0fdadbc3d852 290 return true;
embeddedartists 0:0fdadbc3d852 291 }
embeddedartists 0:0fdadbc3d852 292
embeddedartists 0:0fdadbc3d852 293 bool gpdma_transfer_from_mci(uint8_t ChannelNum,
embeddedartists 0:0fdadbc3d852 294 uint32_t dst,
embeddedartists 0:0fdadbc3d852 295 uint32_t Size)
embeddedartists 0:0fdadbc3d852 296 {
embeddedartists 0:0fdadbc3d852 297 GPDMA_Channel_CFG_T cfg;
embeddedartists 0:0fdadbc3d852 298 cfg.ChannelNum = ChannelNum;
embeddedartists 0:0fdadbc3d852 299 cfg.TransferType = GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL;
embeddedartists 0:0fdadbc3d852 300 cfg.TransferSize = Size;
embeddedartists 0:0fdadbc3d852 301 cfg.TransferWidth = 0;
embeddedartists 0:0fdadbc3d852 302 cfg.SrcAddr = (uint32_t) (&LPC_MCI->FIFO);
embeddedartists 0:0fdadbc3d852 303 cfg.DstAddr = dst;
embeddedartists 0:0fdadbc3d852 304
embeddedartists 0:0fdadbc3d852 305 uint32_t ctrl_word =
embeddedartists 0:0fdadbc3d852 306 GPDMA_DMACCxControl_TransferSize((uint32_t) cfg.TransferSize)
embeddedartists 0:0fdadbc3d852 307 | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_8)
embeddedartists 0:0fdadbc3d852 308 | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_8)
embeddedartists 0:0fdadbc3d852 309 | GPDMA_DMACCxControl_SWidth(GPDMA_WIDTH_WORD)
embeddedartists 0:0fdadbc3d852 310 | GPDMA_DMACCxControl_DWidth(GPDMA_WIDTH_WORD)
embeddedartists 0:0fdadbc3d852 311 | GPDMA_DMACCxControl_SrcTransUseAHBMaster1
embeddedartists 0:0fdadbc3d852 312 | GPDMA_DMACCxControl_DI
embeddedartists 0:0fdadbc3d852 313 | GPDMA_DMACCxControl_I;
embeddedartists 0:0fdadbc3d852 314
embeddedartists 0:0fdadbc3d852 315 if (LPC_GPDMA->EnbldChns & CH_MASK(ChannelNum)) {
embeddedartists 0:0fdadbc3d852 316 /* This channel is enabled, return ERROR, need to release this channel first */
embeddedartists 0:0fdadbc3d852 317 return false;
embeddedartists 0:0fdadbc3d852 318 }
embeddedartists 0:0fdadbc3d852 319
embeddedartists 0:0fdadbc3d852 320 /* Select SD card interface in the DMA MUX*/
embeddedartists 0:0fdadbc3d852 321 LPC_SC->DMAREQSEL &= ~(1 << 1);
embeddedartists 0:0fdadbc3d852 322
embeddedartists 0:0fdadbc3d852 323 gpdma_transfer(&cfg, ctrl_word, 0, GPDMA_CONN_SDC, GPDMA_CONN_MEMORY);
embeddedartists 0:0fdadbc3d852 324 return true;
embeddedartists 0:0fdadbc3d852 325 }
embeddedartists 0:0fdadbc3d852 326
embeddedartists 0:0fdadbc3d852 327