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targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.s@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Child:
150:02e0a0aed4ec
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 ;/******************************************************************************
<> 149:156823d33999 2 ; * @file startup_ARMCM3.s
<> 149:156823d33999 3 ; * @brief CMSIS Cortex-M4 Core Device Startup File
<> 149:156823d33999 4 ; * for CM3 Device Series
<> 149:156823d33999 5 ; * @version V1.05
<> 149:156823d33999 6 ; * @date 25. July 2011
<> 149:156823d33999 7 ; *
<> 149:156823d33999 8 ; * @note
<> 149:156823d33999 9 ; * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
<> 149:156823d33999 10 ; *
<> 149:156823d33999 11 ; * @par
<> 149:156823d33999 12 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M
<> 149:156823d33999 13 ; * processor based microcontrollers. This file can be freely distributed
<> 149:156823d33999 14 ; * within development tools that are supporting such ARM based processors.
<> 149:156823d33999 15 ; *
<> 149:156823d33999 16 ; * @par
<> 149:156823d33999 17 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 18 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 19 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 20 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 149:156823d33999 21 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 22 ; *
<> 149:156823d33999 23 ; ******************************************************************************/
<> 149:156823d33999 24
<> 149:156823d33999 25
<> 149:156823d33999 26 ;
<> 149:156823d33999 27 ; The modules in this file are included in the libraries, and may be replaced
<> 149:156823d33999 28 ; by any user-defined modules that define the PUBLIC symbol _program_start or
<> 149:156823d33999 29 ; a user defined start symbol.
<> 149:156823d33999 30 ; To override the cstartup defined in the library, simply add your modified
<> 149:156823d33999 31 ; version to the workbench project.
<> 149:156823d33999 32 ;
<> 149:156823d33999 33 ; The vector table is normally located at address 0.
<> 149:156823d33999 34 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
<> 149:156823d33999 35 ; The name "__vector_table" has special meaning for C-SPY:
<> 149:156823d33999 36 ; it is where the SP start value is found, and the NVIC vector
<> 149:156823d33999 37 ; table register (VTOR) is initialized to this address if != 0.
<> 149:156823d33999 38 ;
<> 149:156823d33999 39 ; Cortex-M version
<> 149:156823d33999 40 ;
<> 149:156823d33999 41
<> 149:156823d33999 42 MODULE ?cstartup
<> 149:156823d33999 43
<> 149:156823d33999 44 ;; Forward declaration of sections.
<> 149:156823d33999 45 SECTION CSTACK:DATA:NOROOT(3)
<> 149:156823d33999 46
<> 149:156823d33999 47 SECTION .intvec:CODE:NOROOT(2)
<> 149:156823d33999 48
<> 149:156823d33999 49 EXTERN __iar_program_start
<> 149:156823d33999 50 EXTERN SystemInit
<> 149:156823d33999 51 EXTERN fInitSource
<> 149:156823d33999 52 EXTERN HardFault_Handler
<> 149:156823d33999 53 EXTERN SVC_Handler
<> 149:156823d33999 54 EXTERN PendSV_Handler
<> 149:156823d33999 55 EXTERN SysTick_Handler
<> 149:156823d33999 56 EXTERN fIrqTim0Handler
<> 149:156823d33999 57 EXTERN fIrqTim1Handler
<> 149:156823d33999 58 EXTERN fIrqTim2Handler
<> 149:156823d33999 59 EXTERN fIrqGpioHandler
<> 149:156823d33999 60 EXTERN fIrqSpiHandler
<> 149:156823d33999 61 EXTERN fIrqUart1Handler
<> 149:156823d33999 62 EXTERN fIrqUart2Handler
<> 149:156823d33999 63 PUBLIC __vector_table
<> 149:156823d33999 64 PUBLIC __vector_table_0x1c
<> 149:156823d33999 65 PUBLIC __Vectors
<> 149:156823d33999 66 PUBLIC __Vectors_End
<> 149:156823d33999 67 PUBLIC __Vectors_Size
<> 149:156823d33999 68
<> 149:156823d33999 69 DATA
<> 149:156823d33999 70
<> 149:156823d33999 71 __vector_table
<> 149:156823d33999 72 DCD sfe(CSTACK)
<> 149:156823d33999 73 DCD Reset_Handler
<> 149:156823d33999 74 #ifndef RAM_VECTOR_TABLE
<> 149:156823d33999 75 DCD NMI_Handler
<> 149:156823d33999 76 DCD HardFault_Handler
<> 149:156823d33999 77 DCD MemManage_Handler
<> 149:156823d33999 78 DCD BusFault_Handler
<> 149:156823d33999 79 DCD UsageFault_Handler
<> 149:156823d33999 80 #endif
<> 149:156823d33999 81 __vector_table_0x1c
<> 149:156823d33999 82 #ifndef RAM_VECTOR_TABLE
<> 149:156823d33999 83 DCD 0
<> 149:156823d33999 84 DCD 0
<> 149:156823d33999 85 DCD 0
<> 149:156823d33999 86 DCD 0
<> 149:156823d33999 87 DCD SVC_Handler
<> 149:156823d33999 88 DCD DebugMon_Handler
<> 149:156823d33999 89 DCD 0
<> 149:156823d33999 90 DCD PendSV_Handler
<> 149:156823d33999 91 DCD SysTick_Handler
<> 149:156823d33999 92
<> 149:156823d33999 93 ; External Interrupts
<> 149:156823d33999 94 DCD fIrqTim0Handler
<> 149:156823d33999 95 DCD fIrqTim1Handler
<> 149:156823d33999 96 DCD fIrqTim2Handler
<> 149:156823d33999 97 DCD fIrqUart1Handler
<> 149:156823d33999 98 DCD fIrqSpiHandler
<> 149:156823d33999 99 DCD fIrqI2CHandler
<> 149:156823d33999 100 DCD fIrqGpioHandler
<> 149:156823d33999 101 DCD fIrqRtcHandler
<> 149:156823d33999 102 DCD fIrqFlashHandler
<> 149:156823d33999 103 DCD fIrqMacHwHandler
<> 149:156823d33999 104 DCD fIrqAesHandler
<> 149:156823d33999 105 DCD fIrqAdcHandler
<> 149:156823d33999 106 DCD fIrqClockCalHandler
<> 149:156823d33999 107 DCD fIrqUart2Handler
<> 149:156823d33999 108 DCD fIrqUviHandler
<> 149:156823d33999 109 DCD fIrqDmaHandler
<> 149:156823d33999 110 DCD fIrqDbgPwrUpHandler
<> 149:156823d33999 111 /* REV C/D interrupts */
<> 149:156823d33999 112 DCD fIrqSpi2Handler
<> 149:156823d33999 113 DCD fIrqI2c2Handler
<> 149:156823d33999 114 DCD FIrqFVDDHCompHandler /* FVDDH Supply Comparator Trip */
<> 149:156823d33999 115 #endif
<> 149:156823d33999 116 __Vectors_End
<> 149:156823d33999 117
<> 149:156823d33999 118 __Vectors EQU __vector_table
<> 149:156823d33999 119 __Vectors_Size EQU __Vectors_End - __Vectors
<> 149:156823d33999 120
<> 149:156823d33999 121 opt: DC32 0x2082353F /* Full featured device */
<> 149:156823d33999 122 opt_reg: DC32 0x4001E000
<> 149:156823d33999 123 enable: DC32 0x00000000
<> 149:156823d33999 124 per_en: DC32 0x4001B010
<> 149:156823d33999 125
<> 149:156823d33999 126 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
<> 149:156823d33999 127 ;;
<> 149:156823d33999 128 ;; Default interrupt handlers.
<> 149:156823d33999 129 ;;
<> 149:156823d33999 130 THUMB
<> 149:156823d33999 131
<> 149:156823d33999 132 ;; Taken from article http://netstorage.iar.com/SuppDB/Public/UPDINFO/007040/arm/doc/infocenter/ilinkarm.ENU.html
<> 149:156823d33999 133 ;; If this line is removed, veneers for functions copied into RAM are flasely also placed in RAM, but are NOT
<> 149:156823d33999 134 ;; copied into it by __iar_copy_init3
<> 149:156823d33999 135 __iar_init$$done
<> 149:156823d33999 136
<> 149:156823d33999 137 PUBLIC Reset_Handler
<> 149:156823d33999 138 SECTION .text:CODE:REORDER(2)
<> 149:156823d33999 139 Reset_Handler
<> 149:156823d33999 140 LDR R0,= enable ;; load R0 with address of enable
<> 149:156823d33999 141 LDR R0,[R0] ;; load R0 with what address R0 points to
<> 149:156823d33999 142 LDR R1,= per_en ;; load R1 with address of per_en
<> 149:156823d33999 143 LDR R1,[R1] ;; load R1 with what address R1 points to
<> 149:156823d33999 144 STR R0,[R1] ;; store R0 into address pointed to by R1 /* Disable all peripherals */
<> 149:156823d33999 145
<> 149:156823d33999 146 LDR R0,= opt ;; load R0 with address of opt
<> 149:156823d33999 147 LDR R0,[R0] ;; load R0 with what address R0 points to
<> 149:156823d33999 148 LDR R1,= opt_reg ;; load R1 with address of opt_reg
<> 149:156823d33999 149 LDR R1,[R1] ;; load R1 with what address R1 points to
<> 149:156823d33999 150 STR R0, [R1] ;; store R0 into address pointed to by R1 /* Device option: Full featured device */
<> 149:156823d33999 151
<> 149:156823d33999 152 LDR R0,= sfe(CSTACK)
<> 149:156823d33999 153 MOV SP,R0
<> 149:156823d33999 154 LDR R0, =SystemInit
<> 149:156823d33999 155 BLX R0
<> 149:156823d33999 156 LDR R0, =__iar_program_start
<> 149:156823d33999 157 BX R0
<> 149:156823d33999 158
<> 149:156823d33999 159 PUBWEAK NMI_Handler
<> 149:156823d33999 160 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 161 NMI_Handler
<> 149:156823d33999 162 B NMI_Handler
<> 149:156823d33999 163
<> 149:156823d33999 164 ; PUBWEAK HardFault_Handler
<> 149:156823d33999 165 ; SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 166 ;HardFault_Handler
<> 149:156823d33999 167 ; B HardFault_Handler
<> 149:156823d33999 168
<> 149:156823d33999 169 PUBWEAK MemManage_Handler
<> 149:156823d33999 170 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 171 MemManage_Handler
<> 149:156823d33999 172 B MemManage_Handler
<> 149:156823d33999 173
<> 149:156823d33999 174 PUBWEAK BusFault_Handler
<> 149:156823d33999 175 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 176 BusFault_Handler
<> 149:156823d33999 177 B BusFault_Handler
<> 149:156823d33999 178
<> 149:156823d33999 179 PUBWEAK UsageFault_Handler
<> 149:156823d33999 180 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 181 UsageFault_Handler
<> 149:156823d33999 182 B UsageFault_Handler
<> 149:156823d33999 183
<> 149:156823d33999 184 ; PUBWEAK vPortSVCHandler
<> 149:156823d33999 185 ; SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 186 ;vPortSVCHandler
<> 149:156823d33999 187 ; B vPortSVCHandler
<> 149:156823d33999 188
<> 149:156823d33999 189 PUBWEAK DebugMon_Handler
<> 149:156823d33999 190 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 191 DebugMon_Handler
<> 149:156823d33999 192 B DebugMon_Handler
<> 149:156823d33999 193
<> 149:156823d33999 194 ; PUBWEAK xPortPendSVHandler
<> 149:156823d33999 195 ; SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 196 ;xPortPendSVHandler
<> 149:156823d33999 197 ; B xPortPendSVHandler
<> 149:156823d33999 198
<> 149:156823d33999 199 ; PUBWEAK SysTick_Handler
<> 149:156823d33999 200 ; SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 201 ;SysTick_Handler
<> 149:156823d33999 202 ; B SysTick_Handler
<> 149:156823d33999 203
<> 149:156823d33999 204
<> 149:156823d33999 205 ; PUBWEAK fIrqTim0Handler
<> 149:156823d33999 206 ; SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 207 ;fIrqTim0Handler
<> 149:156823d33999 208 ; B fIrqTim0Handler
<> 149:156823d33999 209
<> 149:156823d33999 210 ; PUBWEAK fIrqTim1Handler
<> 149:156823d33999 211 ; SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 212 ;fIrqTim1Handler
<> 149:156823d33999 213 ; B fIrqTim1Handler
<> 149:156823d33999 214
<> 149:156823d33999 215 ; PUBWEAK fIrqTim2Handler
<> 149:156823d33999 216 ; SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 217 ;fIrqTim2Handler
<> 149:156823d33999 218 ; B fIrqTim2Handler
<> 149:156823d33999 219
<> 149:156823d33999 220 ; PUBWEAK fIrqUart1Handler
<> 149:156823d33999 221 ; SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 222 ;fIrqUart1Handler
<> 149:156823d33999 223 ; B fIrqUart1Handler
<> 149:156823d33999 224
<> 149:156823d33999 225 ; PUBWEAK fIrqSpiHandler
<> 149:156823d33999 226 ; SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 227 ;fIrqSpiHandler
<> 149:156823d33999 228 ; B fIrqSpiHandler
<> 149:156823d33999 229
<> 149:156823d33999 230 PUBWEAK fIrqI2CHandler
<> 149:156823d33999 231 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 232 fIrqI2CHandler
<> 149:156823d33999 233 B fIrqI2CHandler
<> 149:156823d33999 234
<> 149:156823d33999 235 ; PUBWEAK fIrqGpioHandler
<> 149:156823d33999 236 ; SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 237 ;fIrqGpioHandler
<> 149:156823d33999 238 ; B fIrqGpioHandler
<> 149:156823d33999 239
<> 149:156823d33999 240 PUBWEAK fIrqRtcHandler
<> 149:156823d33999 241 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 242 fIrqRtcHandler
<> 149:156823d33999 243 B fIrqRtcHandler
<> 149:156823d33999 244
<> 149:156823d33999 245 PUBWEAK fIrqFlashHandler
<> 149:156823d33999 246 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 247 fIrqFlashHandler
<> 149:156823d33999 248 B fIrqFlashHandler
<> 149:156823d33999 249
<> 149:156823d33999 250 PUBWEAK fIrqMacHwHandler
<> 149:156823d33999 251 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 252 fIrqMacHwHandler
<> 149:156823d33999 253 B fIrqMacHwHandler
<> 149:156823d33999 254
<> 149:156823d33999 255 PUBWEAK fIrqAesHandler
<> 149:156823d33999 256 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 257 fIrqAesHandler
<> 149:156823d33999 258 B fIrqAesHandler
<> 149:156823d33999 259
<> 149:156823d33999 260 PUBWEAK fIrqAdcHandler
<> 149:156823d33999 261 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 262 fIrqAdcHandler
<> 149:156823d33999 263 B fIrqAdcHandler
<> 149:156823d33999 264
<> 149:156823d33999 265 PUBWEAK fIrqClockCalHandler
<> 149:156823d33999 266 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 267 fIrqClockCalHandler
<> 149:156823d33999 268 B fIrqClockCalHandler
<> 149:156823d33999 269
<> 149:156823d33999 270 ; PUBWEAK fIrqUart2Handler
<> 149:156823d33999 271 ; SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 272 ;fIrqUart2Handler
<> 149:156823d33999 273 ; B fIrqUart2Handler
<> 149:156823d33999 274
<> 149:156823d33999 275 PUBWEAK fIrqDbgPwrUpHandler
<> 149:156823d33999 276 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 277 fIrqDbgPwrUpHandler
<> 149:156823d33999 278 B fIrqDbgPwrUpHandler
<> 149:156823d33999 279
<> 149:156823d33999 280 PUBWEAK fIrqDmaHandler
<> 149:156823d33999 281 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 282 fIrqDmaHandler
<> 149:156823d33999 283 B fIrqDmaHandler
<> 149:156823d33999 284
<> 149:156823d33999 285 PUBWEAK fIrqUviHandler
<> 149:156823d33999 286 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 287 fIrqUviHandler
<> 149:156823d33999 288 B fIrqUviHandler
<> 149:156823d33999 289
<> 149:156823d33999 290 PUBWEAK fIrqSpi2Handler
<> 149:156823d33999 291 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 292 fIrqSpi2Handler
<> 149:156823d33999 293 B fIrqSpi2Handler
<> 149:156823d33999 294
<> 149:156823d33999 295 PUBWEAK fIrqI2c2Handler
<> 149:156823d33999 296 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 297 fIrqI2c2Handler
<> 149:156823d33999 298 B fIrqI2c2Handler
<> 149:156823d33999 299
<> 149:156823d33999 300 PUBWEAK FIrqFVDDHCompHandler
<> 149:156823d33999 301 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 302 FIrqFVDDHCompHandler
<> 149:156823d33999 303 B FIrqFVDDHCompHandler
<> 149:156823d33999 304
<> 149:156823d33999 305 PUBWEAK DEF_IRQHandler
<> 149:156823d33999 306 SECTION .text:CODE:REORDER(1)
<> 149:156823d33999 307 DEF_IRQHandler
<> 149:156823d33999 308 B DEF_IRQHandler
<> 149:156823d33999 309
<> 149:156823d33999 310 END