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targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spibsc_iodefine.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * DISCLAIMER
<> 144:ef7eb2e8f9f7 3 * This software is supplied by Renesas Electronics Corporation and is only
<> 144:ef7eb2e8f9f7 4 * intended for use with Renesas products. No other uses are authorized. This
<> 144:ef7eb2e8f9f7 5 * software is owned by Renesas Electronics Corporation and is protected under
<> 144:ef7eb2e8f9f7 6 * all applicable laws, including copyright laws.
<> 144:ef7eb2e8f9f7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
<> 144:ef7eb2e8f9f7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
<> 144:ef7eb2e8f9f7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
<> 144:ef7eb2e8f9f7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
<> 144:ef7eb2e8f9f7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
<> 144:ef7eb2e8f9f7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
<> 144:ef7eb2e8f9f7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
<> 144:ef7eb2e8f9f7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
<> 144:ef7eb2e8f9f7 16 * Renesas reserves the right, without notice, to make changes to this software
<> 144:ef7eb2e8f9f7 17 * and to discontinue the availability of this software. By using this software,
<> 144:ef7eb2e8f9f7 18 * you agree to the additional terms and conditions found by accessing the
<> 144:ef7eb2e8f9f7 19 * following link:
<> 144:ef7eb2e8f9f7 20 * http://www.renesas.com/disclaimer*
<> 144:ef7eb2e8f9f7 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
<> 144:ef7eb2e8f9f7 22 *******************************************************************************/
<> 144:ef7eb2e8f9f7 23 /*******************************************************************************
<> 144:ef7eb2e8f9f7 24 * File Name : spibsc_iodefine.h
<> 144:ef7eb2e8f9f7 25 * $Rev: $
<> 144:ef7eb2e8f9f7 26 * $Date:: $
<> 144:ef7eb2e8f9f7 27 * Description : Definition of I/O Register (V1.00a)
<> 144:ef7eb2e8f9f7 28 ******************************************************************************/
<> 144:ef7eb2e8f9f7 29 #ifndef SPIBSC_IODEFINE_H
<> 144:ef7eb2e8f9f7 30 #define SPIBSC_IODEFINE_H
<> 144:ef7eb2e8f9f7 31 /* ->SEC M1.10.1 : Not magic number */
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 struct st_spibsc
<> 144:ef7eb2e8f9f7 34 { /* SPIBSC */
<> 144:ef7eb2e8f9f7 35 volatile uint32_t CMNCR; /* CMNCR */
<> 144:ef7eb2e8f9f7 36 volatile uint32_t SSLDR; /* SSLDR */
<> 144:ef7eb2e8f9f7 37 volatile uint32_t SPBCR; /* SPBCR */
<> 144:ef7eb2e8f9f7 38 volatile uint32_t DRCR; /* DRCR */
<> 144:ef7eb2e8f9f7 39 volatile uint32_t DRCMR; /* DRCMR */
<> 144:ef7eb2e8f9f7 40 volatile uint32_t DREAR; /* DREAR */
<> 144:ef7eb2e8f9f7 41 volatile uint32_t DROPR; /* DROPR */
<> 144:ef7eb2e8f9f7 42 volatile uint32_t DRENR; /* DRENR */
<> 144:ef7eb2e8f9f7 43 volatile uint32_t SMCR; /* SMCR */
<> 144:ef7eb2e8f9f7 44 volatile uint32_t SMCMR; /* SMCMR */
<> 144:ef7eb2e8f9f7 45 volatile uint32_t SMADR; /* SMADR */
<> 144:ef7eb2e8f9f7 46 volatile uint32_t SMOPR; /* SMOPR */
<> 144:ef7eb2e8f9f7 47 volatile uint32_t SMENR; /* SMENR */
<> 144:ef7eb2e8f9f7 48 volatile uint8_t dummy1[4]; /* */
<> 144:ef7eb2e8f9f7 49 union iodefine_reg32_t SMRDR0; /* SMRDR0 */
<> 144:ef7eb2e8f9f7 50 union iodefine_reg32_t SMRDR1; /* SMRDR1 */
<> 144:ef7eb2e8f9f7 51 union iodefine_reg32_t SMWDR0; /* SMWDR0 */
<> 144:ef7eb2e8f9f7 52 union iodefine_reg32_t SMWDR1; /* SMWDR1 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 volatile uint32_t CMNSR; /* CMNSR */
<> 144:ef7eb2e8f9f7 55 volatile uint8_t dummy2[12]; /* */
<> 144:ef7eb2e8f9f7 56 volatile uint32_t DRDMCR; /* DRDMCR */
<> 144:ef7eb2e8f9f7 57 volatile uint32_t DRDRENR; /* DRDRENR */
<> 144:ef7eb2e8f9f7 58 volatile uint32_t SMDMCR; /* SMDMCR */
<> 144:ef7eb2e8f9f7 59 volatile uint32_t SMDRENR; /* SMDRENR */
<> 144:ef7eb2e8f9f7 60 };
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 #define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */
<> 144:ef7eb2e8f9f7 64 #define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /* Start of channnel array defines of SPIBSC */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /* Channnel array defines of SPIBSC */
<> 144:ef7eb2e8f9f7 70 /*(Sample) value = SPIBSC[ channel ]->CMNCR; */
<> 144:ef7eb2e8f9f7 71 #define SPIBSC_COUNT 2
<> 144:ef7eb2e8f9f7 72 #define SPIBSC_ADDRESS_LIST \
<> 144:ef7eb2e8f9f7 73 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
<> 144:ef7eb2e8f9f7 74 &SPIBSC0, &SPIBSC1 \
<> 144:ef7eb2e8f9f7 75 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /* End of channnel array defines of SPIBSC */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 #define CMNCR_0 SPIBSC0.CMNCR
<> 144:ef7eb2e8f9f7 81 #define SSLDR_0 SPIBSC0.SSLDR
<> 144:ef7eb2e8f9f7 82 #define SPBCR_0 SPIBSC0.SPBCR
<> 144:ef7eb2e8f9f7 83 #define DRCR_0 SPIBSC0.DRCR
<> 144:ef7eb2e8f9f7 84 #define DRCMR_0 SPIBSC0.DRCMR
<> 144:ef7eb2e8f9f7 85 #define DREAR_0 SPIBSC0.DREAR
<> 144:ef7eb2e8f9f7 86 #define DROPR_0 SPIBSC0.DROPR
<> 144:ef7eb2e8f9f7 87 #define DRENR_0 SPIBSC0.DRENR
<> 144:ef7eb2e8f9f7 88 #define SMCR_0 SPIBSC0.SMCR
<> 144:ef7eb2e8f9f7 89 #define SMCMR_0 SPIBSC0.SMCMR
<> 144:ef7eb2e8f9f7 90 #define SMADR_0 SPIBSC0.SMADR
<> 144:ef7eb2e8f9f7 91 #define SMOPR_0 SPIBSC0.SMOPR
<> 144:ef7eb2e8f9f7 92 #define SMENR_0 SPIBSC0.SMENR
<> 144:ef7eb2e8f9f7 93 #define SMRDR0_0 SPIBSC0.SMRDR0.UINT32
<> 144:ef7eb2e8f9f7 94 #define SMRDR0_0L SPIBSC0.SMRDR0.UINT16[L]
<> 144:ef7eb2e8f9f7 95 #define SMRDR0_0H SPIBSC0.SMRDR0.UINT16[H]
<> 144:ef7eb2e8f9f7 96 #define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL]
<> 144:ef7eb2e8f9f7 97 #define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH]
<> 144:ef7eb2e8f9f7 98 #define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL]
<> 144:ef7eb2e8f9f7 99 #define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH]
<> 144:ef7eb2e8f9f7 100 #define SMRDR1_0 SPIBSC0.SMRDR1.UINT32
<> 144:ef7eb2e8f9f7 101 #define SMRDR1_0L SPIBSC0.SMRDR1.UINT16[L]
<> 144:ef7eb2e8f9f7 102 #define SMRDR1_0H SPIBSC0.SMRDR1.UINT16[H]
<> 144:ef7eb2e8f9f7 103 #define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL]
<> 144:ef7eb2e8f9f7 104 #define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH]
<> 144:ef7eb2e8f9f7 105 #define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL]
<> 144:ef7eb2e8f9f7 106 #define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH]
<> 144:ef7eb2e8f9f7 107 #define SMWDR0_0 SPIBSC0.SMWDR0.UINT32
<> 144:ef7eb2e8f9f7 108 #define SMWDR0_0L SPIBSC0.SMWDR0.UINT16[L]
<> 144:ef7eb2e8f9f7 109 #define SMWDR0_0H SPIBSC0.SMWDR0.UINT16[H]
<> 144:ef7eb2e8f9f7 110 #define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL]
<> 144:ef7eb2e8f9f7 111 #define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH]
<> 144:ef7eb2e8f9f7 112 #define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL]
<> 144:ef7eb2e8f9f7 113 #define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH]
<> 144:ef7eb2e8f9f7 114 #define SMWDR1_0 SPIBSC0.SMWDR1.UINT32
<> 144:ef7eb2e8f9f7 115 #define SMWDR1_0L SPIBSC0.SMWDR1.UINT16[L]
<> 144:ef7eb2e8f9f7 116 #define SMWDR1_0H SPIBSC0.SMWDR1.UINT16[H]
<> 144:ef7eb2e8f9f7 117 #define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL]
<> 144:ef7eb2e8f9f7 118 #define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH]
<> 144:ef7eb2e8f9f7 119 #define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL]
<> 144:ef7eb2e8f9f7 120 #define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH]
<> 144:ef7eb2e8f9f7 121 #define CMNSR_0 SPIBSC0.CMNSR
<> 144:ef7eb2e8f9f7 122 #define DRDMCR_0 SPIBSC0.DRDMCR
<> 144:ef7eb2e8f9f7 123 #define DRDRENR_0 SPIBSC0.DRDRENR
<> 144:ef7eb2e8f9f7 124 #define SMDMCR_0 SPIBSC0.SMDMCR
<> 144:ef7eb2e8f9f7 125 #define SMDRENR_0 SPIBSC0.SMDRENR
<> 144:ef7eb2e8f9f7 126 #define CMNCR_1 SPIBSC1.CMNCR
<> 144:ef7eb2e8f9f7 127 #define SSLDR_1 SPIBSC1.SSLDR
<> 144:ef7eb2e8f9f7 128 #define SPBCR_1 SPIBSC1.SPBCR
<> 144:ef7eb2e8f9f7 129 #define DRCR_1 SPIBSC1.DRCR
<> 144:ef7eb2e8f9f7 130 #define DRCMR_1 SPIBSC1.DRCMR
<> 144:ef7eb2e8f9f7 131 #define DREAR_1 SPIBSC1.DREAR
<> 144:ef7eb2e8f9f7 132 #define DROPR_1 SPIBSC1.DROPR
<> 144:ef7eb2e8f9f7 133 #define DRENR_1 SPIBSC1.DRENR
<> 144:ef7eb2e8f9f7 134 #define SMCR_1 SPIBSC1.SMCR
<> 144:ef7eb2e8f9f7 135 #define SMCMR_1 SPIBSC1.SMCMR
<> 144:ef7eb2e8f9f7 136 #define SMADR_1 SPIBSC1.SMADR
<> 144:ef7eb2e8f9f7 137 #define SMOPR_1 SPIBSC1.SMOPR
<> 144:ef7eb2e8f9f7 138 #define SMENR_1 SPIBSC1.SMENR
<> 144:ef7eb2e8f9f7 139 #define SMRDR0_1 SPIBSC1.SMRDR0.UINT32
<> 144:ef7eb2e8f9f7 140 #define SMRDR0_1L SPIBSC1.SMRDR0.UINT16[L]
<> 144:ef7eb2e8f9f7 141 #define SMRDR0_1H SPIBSC1.SMRDR0.UINT16[H]
<> 144:ef7eb2e8f9f7 142 #define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL]
<> 144:ef7eb2e8f9f7 143 #define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH]
<> 144:ef7eb2e8f9f7 144 #define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL]
<> 144:ef7eb2e8f9f7 145 #define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH]
<> 144:ef7eb2e8f9f7 146 #define SMRDR1_1 SPIBSC1.SMRDR1.UINT32
<> 144:ef7eb2e8f9f7 147 #define SMRDR1_1L SPIBSC1.SMRDR1.UINT16[L]
<> 144:ef7eb2e8f9f7 148 #define SMRDR1_1H SPIBSC1.SMRDR1.UINT16[H]
<> 144:ef7eb2e8f9f7 149 #define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL]
<> 144:ef7eb2e8f9f7 150 #define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH]
<> 144:ef7eb2e8f9f7 151 #define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL]
<> 144:ef7eb2e8f9f7 152 #define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH]
<> 144:ef7eb2e8f9f7 153 #define SMWDR0_1 SPIBSC1.SMWDR0.UINT32
<> 144:ef7eb2e8f9f7 154 #define SMWDR0_1L SPIBSC1.SMWDR0.UINT16[L]
<> 144:ef7eb2e8f9f7 155 #define SMWDR0_1H SPIBSC1.SMWDR0.UINT16[H]
<> 144:ef7eb2e8f9f7 156 #define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL]
<> 144:ef7eb2e8f9f7 157 #define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH]
<> 144:ef7eb2e8f9f7 158 #define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL]
<> 144:ef7eb2e8f9f7 159 #define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH]
<> 144:ef7eb2e8f9f7 160 #define SMWDR1_1 SPIBSC1.SMWDR1.UINT32
<> 144:ef7eb2e8f9f7 161 #define SMWDR1_1L SPIBSC1.SMWDR1.UINT16[L]
<> 144:ef7eb2e8f9f7 162 #define SMWDR1_1H SPIBSC1.SMWDR1.UINT16[H]
<> 144:ef7eb2e8f9f7 163 #define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL]
<> 144:ef7eb2e8f9f7 164 #define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH]
<> 144:ef7eb2e8f9f7 165 #define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL]
<> 144:ef7eb2e8f9f7 166 #define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH]
<> 144:ef7eb2e8f9f7 167 #define CMNSR_1 SPIBSC1.CMNSR
<> 144:ef7eb2e8f9f7 168 #define DRDMCR_1 SPIBSC1.DRDMCR
<> 144:ef7eb2e8f9f7 169 #define DRDRENR_1 SPIBSC1.DRDRENR
<> 144:ef7eb2e8f9f7 170 #define SMDMCR_1 SPIBSC1.SMDMCR
<> 144:ef7eb2e8f9f7 171 #define SMDRENR_1 SPIBSC1.SMDRENR
<> 144:ef7eb2e8f9f7 172 /* <-SEC M1.10.1 */
<> 144:ef7eb2e8f9f7 173 #endif