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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 17 #include <math.h>
group-onsemi 0:098463de4c5d 18 #include "spi_api.h"
group-onsemi 0:098463de4c5d 19 #include "cmsis.h"
group-onsemi 0:098463de4c5d 20 #include "pinmap.h"
group-onsemi 0:098463de4c5d 21 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 22
group-onsemi 0:098463de4c5d 23 static const PinMap PinMap_SPI_SCLK[] = {
group-onsemi 0:098463de4c5d 24 {P0_6 , SPI_0, 0x02},
group-onsemi 0:098463de4c5d 25 // {P0_10, SPI_0, 0x02}, -- should be mapped to SWCLK only
group-onsemi 0:098463de4c5d 26 {P2_11, SPI_0, 0x01},
group-onsemi 0:098463de4c5d 27 {P2_1 , SPI_1, 0x02},
group-onsemi 0:098463de4c5d 28 {NC , NC , 0}
group-onsemi 0:098463de4c5d 29 };
group-onsemi 0:098463de4c5d 30
group-onsemi 0:098463de4c5d 31 static const PinMap PinMap_SPI_MOSI[] = {
group-onsemi 0:098463de4c5d 32 {P0_9 , SPI_0, 0x01},
group-onsemi 0:098463de4c5d 33 {P2_3 , SPI_1, 0x02},
group-onsemi 0:098463de4c5d 34 {NC , NC , 0}
group-onsemi 0:098463de4c5d 35 };
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 static const PinMap PinMap_SPI_MISO[] = {
group-onsemi 0:098463de4c5d 38 {P0_8 , SPI_0, 0x01},
group-onsemi 0:098463de4c5d 39 {P2_2 , SPI_1, 0x02},
group-onsemi 0:098463de4c5d 40 {NC , NC , 0}
group-onsemi 0:098463de4c5d 41 };
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 static const PinMap PinMap_SPI_SSEL[] = {
group-onsemi 0:098463de4c5d 44 {P0_2 , SPI_0, 0x01},
group-onsemi 0:098463de4c5d 45 {P2_0 , SPI_1, 0x02},
group-onsemi 0:098463de4c5d 46 {NC , NC , 0}
group-onsemi 0:098463de4c5d 47 };
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 static inline int ssp_disable(spi_t *obj);
group-onsemi 0:098463de4c5d 50 static inline int ssp_enable(spi_t *obj);
group-onsemi 0:098463de4c5d 51
group-onsemi 0:098463de4c5d 52 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
group-onsemi 0:098463de4c5d 53 // determine the SPI to use
group-onsemi 0:098463de4c5d 54 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
group-onsemi 0:098463de4c5d 55 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
group-onsemi 0:098463de4c5d 56 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
group-onsemi 0:098463de4c5d 57 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
group-onsemi 0:098463de4c5d 58 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
group-onsemi 0:098463de4c5d 59 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
group-onsemi 0:098463de4c5d 60
group-onsemi 0:098463de4c5d 61 obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
group-onsemi 0:098463de4c5d 62 MBED_ASSERT((int)obj->spi != NC);
group-onsemi 0:098463de4c5d 63
group-onsemi 0:098463de4c5d 64 // enable power and clocking
group-onsemi 0:098463de4c5d 65 switch ((int)obj->spi) {
group-onsemi 0:098463de4c5d 66 case SPI_0:
group-onsemi 0:098463de4c5d 67 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
group-onsemi 0:098463de4c5d 68 LPC_SYSCON->SSP0CLKDIV = 0x01;
group-onsemi 0:098463de4c5d 69 LPC_SYSCON->PRESETCTRL |= 1 << 0;
group-onsemi 0:098463de4c5d 70 if (sclk == P0_6) {
group-onsemi 0:098463de4c5d 71 LPC_IOCON->SCK_LOC = 0x02;
group-onsemi 0:098463de4c5d 72 }
group-onsemi 0:098463de4c5d 73 else {
group-onsemi 0:098463de4c5d 74 LPC_IOCON->SCK_LOC = 0x01;
group-onsemi 0:098463de4c5d 75 }
group-onsemi 0:098463de4c5d 76 break;
group-onsemi 0:098463de4c5d 77 case SPI_1:
group-onsemi 0:098463de4c5d 78 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
group-onsemi 0:098463de4c5d 79 LPC_SYSCON->SSP1CLKDIV = 0x01;
group-onsemi 0:098463de4c5d 80 LPC_SYSCON->PRESETCTRL |= 1 << 2;
group-onsemi 0:098463de4c5d 81 LPC_IOCON->SCK1_LOC = 0x00;
group-onsemi 0:098463de4c5d 82 LPC_IOCON->MISO1_LOC = 0x00;
group-onsemi 0:098463de4c5d 83 LPC_IOCON->MOSI1_LOC = 0x00;
group-onsemi 0:098463de4c5d 84 if (ssel != NC) {
group-onsemi 0:098463de4c5d 85 LPC_IOCON->SSEL1_LOC = 0x00;
group-onsemi 0:098463de4c5d 86 }
group-onsemi 0:098463de4c5d 87 break;
group-onsemi 0:098463de4c5d 88 }
group-onsemi 0:098463de4c5d 89
group-onsemi 0:098463de4c5d 90 // pin out the spi pins
group-onsemi 0:098463de4c5d 91 pinmap_pinout(mosi, PinMap_SPI_MOSI);
group-onsemi 0:098463de4c5d 92 pinmap_pinout(miso, PinMap_SPI_MISO);
group-onsemi 0:098463de4c5d 93 pinmap_pinout(sclk, PinMap_SPI_SCLK);
group-onsemi 0:098463de4c5d 94 if (ssel != NC) {
group-onsemi 0:098463de4c5d 95 pinmap_pinout(ssel, PinMap_SPI_SSEL);
group-onsemi 0:098463de4c5d 96 }
group-onsemi 0:098463de4c5d 97 }
group-onsemi 0:098463de4c5d 98
group-onsemi 0:098463de4c5d 99 void spi_free(spi_t *obj) {}
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 void spi_format(spi_t *obj, int bits, int mode, int slave) {
group-onsemi 0:098463de4c5d 102 MBED_ASSERT((bits >= 4 && bits <= 16) || (mode >= 0 && mode <= 3));
group-onsemi 0:098463de4c5d 103 ssp_disable(obj);
group-onsemi 0:098463de4c5d 104
group-onsemi 0:098463de4c5d 105 int polarity = (mode & 0x2) ? 1 : 0;
group-onsemi 0:098463de4c5d 106 int phase = (mode & 0x1) ? 1 : 0;
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 // set it up
group-onsemi 0:098463de4c5d 109 int DSS = bits - 1; // DSS (data select size)
group-onsemi 0:098463de4c5d 110 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
group-onsemi 0:098463de4c5d 111 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
group-onsemi 0:098463de4c5d 112
group-onsemi 0:098463de4c5d 113 int FRF = 0; // FRF (frame format) = SPI
group-onsemi 0:098463de4c5d 114 uint32_t tmp = obj->spi->CR0;
group-onsemi 0:098463de4c5d 115 tmp &= ~(0xFFFF);
group-onsemi 0:098463de4c5d 116 tmp |= DSS << 0
group-onsemi 0:098463de4c5d 117 | FRF << 4
group-onsemi 0:098463de4c5d 118 | SPO << 6
group-onsemi 0:098463de4c5d 119 | SPH << 7;
group-onsemi 0:098463de4c5d 120 obj->spi->CR0 = tmp;
group-onsemi 0:098463de4c5d 121
group-onsemi 0:098463de4c5d 122 tmp = obj->spi->CR1;
group-onsemi 0:098463de4c5d 123 tmp &= ~(0xD);
group-onsemi 0:098463de4c5d 124 tmp |= 0 << 0 // LBM - loop back mode - off
group-onsemi 0:098463de4c5d 125 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
group-onsemi 0:098463de4c5d 126 | 0 << 3; // SOD - slave output disable - na
group-onsemi 0:098463de4c5d 127 obj->spi->CR1 = tmp;
group-onsemi 0:098463de4c5d 128
group-onsemi 0:098463de4c5d 129 ssp_enable(obj);
group-onsemi 0:098463de4c5d 130 }
group-onsemi 0:098463de4c5d 131
group-onsemi 0:098463de4c5d 132 void spi_frequency(spi_t *obj, int hz) {
group-onsemi 0:098463de4c5d 133 ssp_disable(obj);
group-onsemi 0:098463de4c5d 134
group-onsemi 0:098463de4c5d 135 uint32_t PCLK = SystemCoreClock;
group-onsemi 0:098463de4c5d 136
group-onsemi 0:098463de4c5d 137 int prescaler;
group-onsemi 0:098463de4c5d 138
group-onsemi 0:098463de4c5d 139 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
group-onsemi 0:098463de4c5d 140 int prescale_hz = PCLK / prescaler;
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142 // calculate the divider
group-onsemi 0:098463de4c5d 143 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
group-onsemi 0:098463de4c5d 144
group-onsemi 0:098463de4c5d 145 // check we can support the divider
group-onsemi 0:098463de4c5d 146 if (divider < 256) {
group-onsemi 0:098463de4c5d 147 // prescaler
group-onsemi 0:098463de4c5d 148 obj->spi->CPSR = prescaler;
group-onsemi 0:098463de4c5d 149
group-onsemi 0:098463de4c5d 150 // divider
group-onsemi 0:098463de4c5d 151 obj->spi->CR0 &= ~(0xFFFF << 8);
group-onsemi 0:098463de4c5d 152 obj->spi->CR0 |= (divider - 1) << 8;
group-onsemi 0:098463de4c5d 153 ssp_enable(obj);
group-onsemi 0:098463de4c5d 154 return;
group-onsemi 0:098463de4c5d 155 }
group-onsemi 0:098463de4c5d 156 }
group-onsemi 0:098463de4c5d 157 error("Couldn't setup requested SPI frequency");
group-onsemi 0:098463de4c5d 158 }
group-onsemi 0:098463de4c5d 159
group-onsemi 0:098463de4c5d 160 static inline int ssp_disable(spi_t *obj) {
group-onsemi 0:098463de4c5d 161 return obj->spi->CR1 &= ~(1 << 1);
group-onsemi 0:098463de4c5d 162 }
group-onsemi 0:098463de4c5d 163
group-onsemi 0:098463de4c5d 164 static inline int ssp_enable(spi_t *obj) {
group-onsemi 0:098463de4c5d 165 return obj->spi->CR1 |= (1 << 1);
group-onsemi 0:098463de4c5d 166 }
group-onsemi 0:098463de4c5d 167
group-onsemi 0:098463de4c5d 168 static inline int ssp_readable(spi_t *obj) {
group-onsemi 0:098463de4c5d 169 return obj->spi->SR & (1 << 2);
group-onsemi 0:098463de4c5d 170 }
group-onsemi 0:098463de4c5d 171
group-onsemi 0:098463de4c5d 172 static inline int ssp_writeable(spi_t *obj) {
group-onsemi 0:098463de4c5d 173 return obj->spi->SR & (1 << 1);
group-onsemi 0:098463de4c5d 174 }
group-onsemi 0:098463de4c5d 175
group-onsemi 0:098463de4c5d 176 static inline void ssp_write(spi_t *obj, int value) {
group-onsemi 0:098463de4c5d 177 while (!ssp_writeable(obj));
group-onsemi 0:098463de4c5d 178 obj->spi->DR = value;
group-onsemi 0:098463de4c5d 179 }
group-onsemi 0:098463de4c5d 180
group-onsemi 0:098463de4c5d 181 static inline int ssp_read(spi_t *obj) {
group-onsemi 0:098463de4c5d 182 while (!ssp_readable(obj));
group-onsemi 0:098463de4c5d 183 return obj->spi->DR;
group-onsemi 0:098463de4c5d 184 }
group-onsemi 0:098463de4c5d 185
group-onsemi 0:098463de4c5d 186 static inline int ssp_busy(spi_t *obj) {
group-onsemi 0:098463de4c5d 187 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
group-onsemi 0:098463de4c5d 188 }
group-onsemi 0:098463de4c5d 189
group-onsemi 0:098463de4c5d 190 int spi_master_write(spi_t *obj, int value) {
group-onsemi 0:098463de4c5d 191 ssp_write(obj, value);
group-onsemi 0:098463de4c5d 192 return ssp_read(obj);
group-onsemi 0:098463de4c5d 193 }
group-onsemi 0:098463de4c5d 194
group-onsemi 0:098463de4c5d 195 int spi_slave_receive(spi_t *obj) {
group-onsemi 0:098463de4c5d 196 return ssp_readable(obj) ? (1) : (0);
group-onsemi 0:098463de4c5d 197 }
group-onsemi 0:098463de4c5d 198
group-onsemi 0:098463de4c5d 199 int spi_slave_read(spi_t *obj) {
group-onsemi 0:098463de4c5d 200 return obj->spi->DR & 0xFFFF;
group-onsemi 0:098463de4c5d 201 }
group-onsemi 0:098463de4c5d 202
group-onsemi 0:098463de4c5d 203 void spi_slave_write(spi_t *obj, int value) {
group-onsemi 0:098463de4c5d 204 while (ssp_writeable(obj) == 0) ;
group-onsemi 0:098463de4c5d 205 obj->spi->DR = value;
group-onsemi 0:098463de4c5d 206 }
group-onsemi 0:098463de4c5d 207
group-onsemi 0:098463de4c5d 208 int spi_busy(spi_t *obj) {
group-onsemi 0:098463de4c5d 209 return ssp_busy(obj);
group-onsemi 0:098463de4c5d 210 }