ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC82X/us_ticker.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include <stddef.h>
group-onsemi 0:098463de4c5d 17 #include "us_ticker_api.h"
group-onsemi 0:098463de4c5d 18 #include "PeripheralNames.h"
group-onsemi 0:098463de4c5d 19
group-onsemi 0:098463de4c5d 20 static int us_ticker_inited = 0;
group-onsemi 0:098463de4c5d 21 int MRT_Clock_MHz;
group-onsemi 0:098463de4c5d 22 unsigned int ticker_fullcount_us;
group-onsemi 0:098463de4c5d 23 unsigned long int ticker_expired_count_us = 0;
group-onsemi 0:098463de4c5d 24
group-onsemi 0:098463de4c5d 25 #define US_TICKER_TIMER_IRQn MRT_IRQn
group-onsemi 0:098463de4c5d 26
group-onsemi 0:098463de4c5d 27 void us_ticker_init(void) {
group-onsemi 0:098463de4c5d 28
group-onsemi 0:098463de4c5d 29 if (us_ticker_inited)
group-onsemi 0:098463de4c5d 30 return;
group-onsemi 0:098463de4c5d 31
group-onsemi 0:098463de4c5d 32 us_ticker_inited = 1;
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 // Calculate MRT clock value (MRT has no prescaler)
group-onsemi 0:098463de4c5d 35 MRT_Clock_MHz = (SystemCoreClock / 1000000);
group-onsemi 0:098463de4c5d 36 // Calculate fullcounter value in us (MRT has 31 bits and clock is 30MHz)
group-onsemi 0:098463de4c5d 37 ticker_fullcount_us = 0x80000000UL/MRT_Clock_MHz;
group-onsemi 0:098463de4c5d 38
group-onsemi 0:098463de4c5d 39 // Enable the MRT clock
group-onsemi 0:098463de4c5d 40 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 // Clear peripheral reset the MRT
group-onsemi 0:098463de4c5d 43 LPC_SYSCON->PRESETCTRL |= (1 << 7);
group-onsemi 0:098463de4c5d 44
group-onsemi 0:098463de4c5d 45 // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
group-onsemi 0:098463de4c5d 46 LPC_MRT->INTVAL0 = 0xFFFFFFFFUL;
group-onsemi 0:098463de4c5d 47 // Enable Ch0 interrupt, Mode 0 is Repeat Interrupt
group-onsemi 0:098463de4c5d 48 LPC_MRT->CTRL0 = (0x0 << 1) | (0x1 << 0);
group-onsemi 0:098463de4c5d 49
group-onsemi 0:098463de4c5d 50 // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
group-onsemi 0:098463de4c5d 51 LPC_MRT->INTVAL1 = 0x80000000UL;
group-onsemi 0:098463de4c5d 52 // Disable ch1 interrupt, Mode 0 is Repeat Interrupt
group-onsemi 0:098463de4c5d 53 LPC_MRT->CTRL1 = (0x0 << 1) | (0x0 << 0);
group-onsemi 0:098463de4c5d 54
group-onsemi 0:098463de4c5d 55 // Set MRT interrupt vector
group-onsemi 0:098463de4c5d 56 NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
group-onsemi 0:098463de4c5d 57 NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
group-onsemi 0:098463de4c5d 58 }
group-onsemi 0:098463de4c5d 59
group-onsemi 0:098463de4c5d 60 //TIMER0 is used for us ticker and timers (Timer, wait(), wait_us() etc)
group-onsemi 0:098463de4c5d 61 uint32_t us_ticker_read() {
group-onsemi 0:098463de4c5d 62
group-onsemi 0:098463de4c5d 63 if (!us_ticker_inited)
group-onsemi 0:098463de4c5d 64 us_ticker_init();
group-onsemi 0:098463de4c5d 65
group-onsemi 0:098463de4c5d 66 // Generate ticker value
group-onsemi 0:098463de4c5d 67 // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer
group-onsemi 0:098463de4c5d 68 // Calculate expected value using number of expired times to mimic a 32bit timer @ 1 MHz
group-onsemi 0:098463de4c5d 69 return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz + ticker_expired_count_us;
group-onsemi 0:098463de4c5d 70 }
group-onsemi 0:098463de4c5d 71
group-onsemi 0:098463de4c5d 72 //TIMER1 is used for Timestamped interrupts (Ticker(), Timeout())
group-onsemi 0:098463de4c5d 73 void us_ticker_set_interrupt(timestamp_t timestamp) {
group-onsemi 0:098463de4c5d 74
group-onsemi 0:098463de4c5d 75 // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer
group-onsemi 0:098463de4c5d 76 // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
group-onsemi 0:098463de4c5d 77 // Note: The MRT has less counter headroom available than the typical mbed 32bit timer @ 1 MHz.
group-onsemi 0:098463de4c5d 78 // The calculated counter interval until the next timestamp will be truncated and an
group-onsemi 0:098463de4c5d 79 // 'early' interrupt will be generated in case the max required count interval exceeds
group-onsemi 0:098463de4c5d 80 // the available 31 bits space. However, the mbed us_ticker interrupt handler will
group-onsemi 0:098463de4c5d 81 // check current time against the next scheduled timestamp and simply re-issue the
group-onsemi 0:098463de4c5d 82 // same interrupt again when needed. The calculated counter interval will now be smaller.
group-onsemi 0:098463de4c5d 83 LPC_MRT->INTVAL1 = (((timestamp - us_ticker_read()) * MRT_Clock_MHz) | 0x80000000UL);
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 // Enable interrupt
group-onsemi 0:098463de4c5d 86 LPC_MRT->CTRL1 |= 1;
group-onsemi 0:098463de4c5d 87 }
group-onsemi 0:098463de4c5d 88
group-onsemi 0:098463de4c5d 89 //Disable Timestamped interrupts triggered by TIMER1
group-onsemi 0:098463de4c5d 90 void us_ticker_disable_interrupt() {
group-onsemi 0:098463de4c5d 91 //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
group-onsemi 0:098463de4c5d 92 LPC_MRT->CTRL1 &= ~1;
group-onsemi 0:098463de4c5d 93 }
group-onsemi 0:098463de4c5d 94
group-onsemi 0:098463de4c5d 95 void us_ticker_clear_interrupt() {
group-onsemi 0:098463de4c5d 96
group-onsemi 0:098463de4c5d 97 //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
group-onsemi 0:098463de4c5d 98 if (LPC_MRT->STAT1 & 1)
group-onsemi 0:098463de4c5d 99 LPC_MRT->STAT1 = 1;
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 //Timer0 for us counter (31 bits downcounter @ SystemCoreClock)
group-onsemi 0:098463de4c5d 102 if (LPC_MRT->STAT0 & 1) {
group-onsemi 0:098463de4c5d 103 LPC_MRT->STAT0 = 1;
group-onsemi 0:098463de4c5d 104 ticker_expired_count_us += ticker_fullcount_us;
group-onsemi 0:098463de4c5d 105 }
group-onsemi 0:098463de4c5d 106 }