5.2.1 - Updated I2C files
Dependents: mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510
targets/TARGET_NXP/TARGET_LPC82X/sleep.c@1:f30bdcd2b33b, 2017-02-27 (annotated)
- Committer:
- jacobjohnson
- Date:
- Mon Feb 27 17:45:05 2017 +0000
- Revision:
- 1:f30bdcd2b33b
- Parent:
- 0:098463de4c5d
changed the inputscale from 1 to 7 in analogin_api.c. This will need to be changed later, and accessed from the main level, but for now this allows the adc to read a value from 0 to 3.7V, instead of just up to 1V.;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
group-onsemi | 0:098463de4c5d | 1 | /* mbed Microcontroller Library |
group-onsemi | 0:098463de4c5d | 2 | * Copyright (c) 2006-2013 ARM Limited |
group-onsemi | 0:098463de4c5d | 3 | * |
group-onsemi | 0:098463de4c5d | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
group-onsemi | 0:098463de4c5d | 5 | * you may not use this file except in compliance with the License. |
group-onsemi | 0:098463de4c5d | 6 | * You may obtain a copy of the License at |
group-onsemi | 0:098463de4c5d | 7 | * |
group-onsemi | 0:098463de4c5d | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
group-onsemi | 0:098463de4c5d | 9 | * |
group-onsemi | 0:098463de4c5d | 10 | * Unless required by applicable law or agreed to in writing, software |
group-onsemi | 0:098463de4c5d | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
group-onsemi | 0:098463de4c5d | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
group-onsemi | 0:098463de4c5d | 13 | * See the License for the specific language governing permissions and |
group-onsemi | 0:098463de4c5d | 14 | * limitations under the License. |
group-onsemi | 0:098463de4c5d | 15 | */ |
group-onsemi | 0:098463de4c5d | 16 | #include "sleep_api.h" |
group-onsemi | 0:098463de4c5d | 17 | #include "cmsis.h" |
group-onsemi | 0:098463de4c5d | 18 | |
group-onsemi | 0:098463de4c5d | 19 | |
group-onsemi | 0:098463de4c5d | 20 | //#define DEEPSLEEP |
group-onsemi | 0:098463de4c5d | 21 | #define POWERDOWN |
group-onsemi | 0:098463de4c5d | 22 | |
group-onsemi | 0:098463de4c5d | 23 | void sleep(void) |
group-onsemi | 0:098463de4c5d | 24 | { |
group-onsemi | 0:098463de4c5d | 25 | //Normal sleep mode for PCON: |
group-onsemi | 0:098463de4c5d | 26 | LPC_PMU->PCON &= ~0x03; |
group-onsemi | 0:098463de4c5d | 27 | |
group-onsemi | 0:098463de4c5d | 28 | //Normal sleep mode for ARM core: |
group-onsemi | 0:098463de4c5d | 29 | SCB->SCR = 0; |
group-onsemi | 0:098463de4c5d | 30 | |
group-onsemi | 0:098463de4c5d | 31 | //And go to sleep |
group-onsemi | 0:098463de4c5d | 32 | __WFI(); |
group-onsemi | 0:098463de4c5d | 33 | } |
group-onsemi | 0:098463de4c5d | 34 | |
group-onsemi | 0:098463de4c5d | 35 | // Deepsleep/powerdown modes assume the device is configured to use its internal RC oscillator directly |
group-onsemi | 0:098463de4c5d | 36 | |
group-onsemi | 0:098463de4c5d | 37 | void deepsleep(void) |
group-onsemi | 0:098463de4c5d | 38 | { |
group-onsemi | 0:098463de4c5d | 39 | //Deep sleep in PCON |
group-onsemi | 0:098463de4c5d | 40 | LPC_PMU->PCON &= ~0x03; |
group-onsemi | 0:098463de4c5d | 41 | |
group-onsemi | 0:098463de4c5d | 42 | #if defined(DEEPSLEEP) |
group-onsemi | 0:098463de4c5d | 43 | LPC_PMU->PCON |= 0x01; |
group-onsemi | 0:098463de4c5d | 44 | #elif defined(POWERDOWN) |
group-onsemi | 0:098463de4c5d | 45 | LPC_PMU->PCON |= 0x02; |
group-onsemi | 0:098463de4c5d | 46 | #endif |
group-onsemi | 0:098463de4c5d | 47 | |
group-onsemi | 0:098463de4c5d | 48 | //If brownout detection and WDT are enabled, keep them enabled during sleep |
group-onsemi | 0:098463de4c5d | 49 | LPC_SYSCON->PDSLEEPCFG = LPC_SYSCON->PDRUNCFG; |
group-onsemi | 0:098463de4c5d | 50 | |
group-onsemi | 0:098463de4c5d | 51 | //After wakeup same stuff as currently enabled: |
group-onsemi | 0:098463de4c5d | 52 | LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG; |
group-onsemi | 0:098463de4c5d | 53 | |
group-onsemi | 0:098463de4c5d | 54 | //All interrupts may wake up: |
group-onsemi | 0:098463de4c5d | 55 | LPC_SYSCON->STARTERP0 = 0xFF; |
group-onsemi | 0:098463de4c5d | 56 | LPC_SYSCON->STARTERP1 = 0xFFFF; |
group-onsemi | 0:098463de4c5d | 57 | |
group-onsemi | 0:098463de4c5d | 58 | //Deep sleep for ARM core: |
group-onsemi | 0:098463de4c5d | 59 | SCB->SCR = 1<<2; |
group-onsemi | 0:098463de4c5d | 60 | |
group-onsemi | 0:098463de4c5d | 61 | __WFI(); |
group-onsemi | 0:098463de4c5d | 62 | } |