ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC82X/serial_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 // math.h required for floating point operations for baud rate calculation
group-onsemi 0:098463de4c5d 17 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 18 #include <math.h>
group-onsemi 0:098463de4c5d 19 #include <string.h>
group-onsemi 0:098463de4c5d 20
group-onsemi 0:098463de4c5d 21 #include "serial_api.h"
group-onsemi 0:098463de4c5d 22 #include "cmsis.h"
group-onsemi 0:098463de4c5d 23 #include "pinmap.h"
group-onsemi 0:098463de4c5d 24 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 25
group-onsemi 0:098463de4c5d 26 #if DEVICE_SERIAL
group-onsemi 0:098463de4c5d 27
group-onsemi 0:098463de4c5d 28 /******************************************************************************
group-onsemi 0:098463de4c5d 29 * INITIALIZATION
group-onsemi 0:098463de4c5d 30 ******************************************************************************/
group-onsemi 0:098463de4c5d 31 #define UART_NUM 3
group-onsemi 0:098463de4c5d 32
group-onsemi 0:098463de4c5d 33 static const SWM_Map SWM_UART_TX[] = {
group-onsemi 0:098463de4c5d 34 {0, 0},
group-onsemi 0:098463de4c5d 35 {1, 8},
group-onsemi 0:098463de4c5d 36 {2, 16},
group-onsemi 0:098463de4c5d 37 };
group-onsemi 0:098463de4c5d 38
group-onsemi 0:098463de4c5d 39 static const SWM_Map SWM_UART_RX[] = {
group-onsemi 0:098463de4c5d 40 {0, 8},
group-onsemi 0:098463de4c5d 41 {1, 16},
group-onsemi 0:098463de4c5d 42 {2, 24},
group-onsemi 0:098463de4c5d 43 };
group-onsemi 0:098463de4c5d 44
group-onsemi 0:098463de4c5d 45 static const SWM_Map SWM_UART_RTS[] = {
group-onsemi 0:098463de4c5d 46 {0, 16},
group-onsemi 0:098463de4c5d 47 {1, 24},
group-onsemi 0:098463de4c5d 48 {3, 0},
group-onsemi 0:098463de4c5d 49 };
group-onsemi 0:098463de4c5d 50
group-onsemi 0:098463de4c5d 51 static const SWM_Map SWM_UART_CTS[] = {
group-onsemi 0:098463de4c5d 52 {0, 24},
group-onsemi 0:098463de4c5d 53 {2, 0},
group-onsemi 0:098463de4c5d 54 {3, 8}
group-onsemi 0:098463de4c5d 55 };
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 // bit flags for used UARTs
group-onsemi 0:098463de4c5d 58 static unsigned char uart_used = 0;
group-onsemi 0:098463de4c5d 59
group-onsemi 0:098463de4c5d 60 static int get_available_uart(void)
group-onsemi 0:098463de4c5d 61 {
group-onsemi 0:098463de4c5d 62 int i;
group-onsemi 0:098463de4c5d 63 for (i=0; i<UART_NUM; i++) {
group-onsemi 0:098463de4c5d 64 if ((uart_used & (1 << i)) == 0)
group-onsemi 0:098463de4c5d 65 return i;
group-onsemi 0:098463de4c5d 66 }
group-onsemi 0:098463de4c5d 67 return -1;
group-onsemi 0:098463de4c5d 68 }
group-onsemi 0:098463de4c5d 69
group-onsemi 0:098463de4c5d 70 #define UART_EN (0x01<<0)
group-onsemi 0:098463de4c5d 71
group-onsemi 0:098463de4c5d 72 #define CTS_DELTA (0x01<<5)
group-onsemi 0:098463de4c5d 73 #define RXBRK (0x01<<10)
group-onsemi 0:098463de4c5d 74 #define DELTA_RXBRK (0x01<<11)
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 #define RXRDY (0x01<<0)
group-onsemi 0:098463de4c5d 77 #define TXRDY (0x01<<2)
group-onsemi 0:098463de4c5d 78
group-onsemi 0:098463de4c5d 79 #define RXRDYEN RXRDY
group-onsemi 0:098463de4c5d 80 #define TXRDYEN TXRDY
group-onsemi 0:098463de4c5d 81
group-onsemi 0:098463de4c5d 82 #define TXBRKEN (0x01<<1)
group-onsemi 0:098463de4c5d 83 #define CTSEN (0x01<<9)
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 static uint32_t UARTSysClk;
group-onsemi 0:098463de4c5d 86
group-onsemi 0:098463de4c5d 87 static uint32_t serial_irq_ids[UART_NUM] = {0};
group-onsemi 0:098463de4c5d 88 static uart_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 89
group-onsemi 0:098463de4c5d 90 int stdio_uart_inited = 0;
group-onsemi 0:098463de4c5d 91 serial_t stdio_uart;
group-onsemi 0:098463de4c5d 92
group-onsemi 0:098463de4c5d 93 static int check_duplication(serial_t *obj, PinName tx, PinName rx)
group-onsemi 0:098463de4c5d 94 {
group-onsemi 0:098463de4c5d 95 if (uart_used == 0)
group-onsemi 0:098463de4c5d 96 return 0;
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98 const SWM_Map *swm;
group-onsemi 0:098463de4c5d 99 uint32_t assigned_tx, assigned_rx;
group-onsemi 0:098463de4c5d 100 int ch;
group-onsemi 0:098463de4c5d 101 for (ch=0; ch<UART_NUM; ch++) {
group-onsemi 0:098463de4c5d 102 // read assigned TX in the UART channel of switch matrix
group-onsemi 0:098463de4c5d 103 swm = &SWM_UART_TX[ch];
group-onsemi 0:098463de4c5d 104 assigned_tx = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
group-onsemi 0:098463de4c5d 105 assigned_tx = assigned_tx >> swm->offset;
group-onsemi 0:098463de4c5d 106 // read assigned RX in the UART channel of switch matrix
group-onsemi 0:098463de4c5d 107 swm = &SWM_UART_RX[ch];
group-onsemi 0:098463de4c5d 108 assigned_rx = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
group-onsemi 0:098463de4c5d 109 assigned_rx = assigned_rx >> swm->offset;
group-onsemi 0:098463de4c5d 110 if ((assigned_tx == (uint32_t)(tx >> PIN_SHIFT)) && (assigned_rx == (uint32_t)(rx >> PIN_SHIFT))) {
group-onsemi 0:098463de4c5d 111 obj->index = ch;
group-onsemi 0:098463de4c5d 112 obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * ch));
group-onsemi 0:098463de4c5d 113 return 1;
group-onsemi 0:098463de4c5d 114 }
group-onsemi 0:098463de4c5d 115 }
group-onsemi 0:098463de4c5d 116 return 0;
group-onsemi 0:098463de4c5d 117 }
group-onsemi 0:098463de4c5d 118
group-onsemi 0:098463de4c5d 119 void serial_init(serial_t *obj, PinName tx, PinName rx)
group-onsemi 0:098463de4c5d 120 {
group-onsemi 0:098463de4c5d 121 int is_stdio_uart = 0;
group-onsemi 0:098463de4c5d 122
group-onsemi 0:098463de4c5d 123 if (check_duplication(obj, tx, rx) == 1)
group-onsemi 0:098463de4c5d 124 return;
group-onsemi 0:098463de4c5d 125
group-onsemi 0:098463de4c5d 126 int uart_n = get_available_uart();
group-onsemi 0:098463de4c5d 127 if (uart_n == -1) {
group-onsemi 0:098463de4c5d 128 error("No available UART");
group-onsemi 0:098463de4c5d 129 }
group-onsemi 0:098463de4c5d 130 obj->index = uart_n;
group-onsemi 0:098463de4c5d 131 obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * uart_n));
group-onsemi 0:098463de4c5d 132 uart_used |= (1 << uart_n);
group-onsemi 0:098463de4c5d 133
group-onsemi 0:098463de4c5d 134 const SWM_Map *swm;
group-onsemi 0:098463de4c5d 135 uint32_t regVal;
group-onsemi 0:098463de4c5d 136
group-onsemi 0:098463de4c5d 137 swm = &SWM_UART_TX[uart_n];
group-onsemi 0:098463de4c5d 138 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
group-onsemi 0:098463de4c5d 139 LPC_SWM->PINASSIGN[swm->n] = regVal | ((tx >> PIN_SHIFT) << swm->offset);
group-onsemi 0:098463de4c5d 140
group-onsemi 0:098463de4c5d 141 swm = &SWM_UART_RX[uart_n];
group-onsemi 0:098463de4c5d 142 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
group-onsemi 0:098463de4c5d 143 LPC_SWM->PINASSIGN[swm->n] = regVal | ((rx >> PIN_SHIFT) << swm->offset);
group-onsemi 0:098463de4c5d 144
group-onsemi 0:098463de4c5d 145 /* uart clock divided by 1 */
group-onsemi 0:098463de4c5d 146 LPC_SYSCON->UARTCLKDIV = 1;
group-onsemi 0:098463de4c5d 147
group-onsemi 0:098463de4c5d 148 /* disable uart interrupts */
group-onsemi 0:098463de4c5d 149 NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
group-onsemi 0:098463de4c5d 150
group-onsemi 0:098463de4c5d 151 /* Enable UART clock */
group-onsemi 0:098463de4c5d 152 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (14 + uart_n));
group-onsemi 0:098463de4c5d 153
group-onsemi 0:098463de4c5d 154 /* Peripheral reset control to UART, a "1" bring it out of reset. */
group-onsemi 0:098463de4c5d 155 LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n));
group-onsemi 0:098463de4c5d 156 LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n));
group-onsemi 0:098463de4c5d 157
group-onsemi 0:098463de4c5d 158 UARTSysClk = MainClock / LPC_SYSCON->UARTCLKDIV;
group-onsemi 0:098463de4c5d 159
group-onsemi 0:098463de4c5d 160 // set default baud rate and format
group-onsemi 0:098463de4c5d 161 serial_baud (obj, 9600);
group-onsemi 0:098463de4c5d 162 serial_format(obj, 8, ParityNone, 1);
group-onsemi 0:098463de4c5d 163
group-onsemi 0:098463de4c5d 164 /* Clear all status bits. */
group-onsemi 0:098463de4c5d 165 obj->uart->STAT = CTS_DELTA | DELTA_RXBRK;
group-onsemi 0:098463de4c5d 166
group-onsemi 0:098463de4c5d 167 /* enable uart interrupts */
group-onsemi 0:098463de4c5d 168 NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
group-onsemi 0:098463de4c5d 169
group-onsemi 0:098463de4c5d 170 /* Enable UART */
group-onsemi 0:098463de4c5d 171 obj->uart->CFG |= UART_EN;
group-onsemi 0:098463de4c5d 172
group-onsemi 0:098463de4c5d 173 is_stdio_uart = ((tx == USBTX) && (rx == USBRX));
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175 if (is_stdio_uart) {
group-onsemi 0:098463de4c5d 176 stdio_uart_inited = 1;
group-onsemi 0:098463de4c5d 177 memcpy(&stdio_uart, obj, sizeof(serial_t));
group-onsemi 0:098463de4c5d 178 }
group-onsemi 0:098463de4c5d 179 }
group-onsemi 0:098463de4c5d 180
group-onsemi 0:098463de4c5d 181 void serial_free(serial_t *obj)
group-onsemi 0:098463de4c5d 182 {
group-onsemi 0:098463de4c5d 183 uart_used &= ~(1 << obj->index);
group-onsemi 0:098463de4c5d 184 serial_irq_ids[obj->index] = 0;
group-onsemi 0:098463de4c5d 185 }
group-onsemi 0:098463de4c5d 186
group-onsemi 0:098463de4c5d 187 void serial_baud(serial_t *obj, int baudrate)
group-onsemi 0:098463de4c5d 188 {
group-onsemi 0:098463de4c5d 189 /* Integer divider:
group-onsemi 0:098463de4c5d 190 BRG = UARTSysClk/(Baudrate * 16) - 1
group-onsemi 0:098463de4c5d 191
group-onsemi 0:098463de4c5d 192 Frational divider:
group-onsemi 0:098463de4c5d 193 FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1)
group-onsemi 0:098463de4c5d 194
group-onsemi 0:098463de4c5d 195 where
group-onsemi 0:098463de4c5d 196 FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1)
group-onsemi 0:098463de4c5d 197
group-onsemi 0:098463de4c5d 198 (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB
group-onsemi 0:098463de4c5d 199 register is 0xFF.
group-onsemi 0:098463de4c5d 200 (2) In ADD register value, depending on the value of UartSysClk,
group-onsemi 0:098463de4c5d 201 baudrate, BRG register value, and SUB register value, be careful
group-onsemi 0:098463de4c5d 202 about the order of multiplier and divider and make sure any
group-onsemi 0:098463de4c5d 203 multiplier doesn't exceed 32-bit boundary and any divider doesn't get
group-onsemi 0:098463de4c5d 204 down below one(integer 0).
group-onsemi 0:098463de4c5d 205 (3) ADD should be always less than SUB.
group-onsemi 0:098463de4c5d 206 */
group-onsemi 0:098463de4c5d 207 obj->uart->BRG = UARTSysClk / 16 / baudrate - 1;
group-onsemi 0:098463de4c5d 208
group-onsemi 0:098463de4c5d 209 LPC_SYSCON->UARTFRGDIV = 0xFF;
group-onsemi 0:098463de4c5d 210 LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) /
group-onsemi 0:098463de4c5d 211 (baudrate * (obj->uart->BRG + 1))
group-onsemi 0:098463de4c5d 212 ) - (LPC_SYSCON->UARTFRGDIV + 1);
group-onsemi 0:098463de4c5d 213 }
group-onsemi 0:098463de4c5d 214
group-onsemi 0:098463de4c5d 215 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
group-onsemi 0:098463de4c5d 216 {
group-onsemi 0:098463de4c5d 217 // 0: 1 stop bits, 1: 2 stop bits
group-onsemi 0:098463de4c5d 218 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
group-onsemi 0:098463de4c5d 219 MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
group-onsemi 0:098463de4c5d 220 MBED_ASSERT((parity == ParityNone) || (parity == ParityEven) || (parity == ParityOdd));
group-onsemi 0:098463de4c5d 221 stop_bits -= 1;
group-onsemi 0:098463de4c5d 222 data_bits -= 7;
group-onsemi 0:098463de4c5d 223
group-onsemi 0:098463de4c5d 224 int paritysel = 0;
group-onsemi 0:098463de4c5d 225 switch (parity) {
group-onsemi 0:098463de4c5d 226 case ParityNone: paritysel = 0; break;
group-onsemi 0:098463de4c5d 227 case ParityEven: paritysel = 2; break;
group-onsemi 0:098463de4c5d 228 case ParityOdd : paritysel = 3; break;
group-onsemi 0:098463de4c5d 229 default:
group-onsemi 0:098463de4c5d 230 break;
group-onsemi 0:098463de4c5d 231 }
group-onsemi 0:098463de4c5d 232
group-onsemi 0:098463de4c5d 233 // First disable the the usart as described in documentation and then enable while updating CFG
group-onsemi 0:098463de4c5d 234
group-onsemi 0:098463de4c5d 235 // 24.6.1 USART Configuration register
group-onsemi 0:098463de4c5d 236 // Remark: If software needs to change configuration values, the following sequence should
group-onsemi 0:098463de4c5d 237 // be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable
group-onsemi 0:098463de4c5d 238 // the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3)
group-onsemi 0:098463de4c5d 239 // Write the new configuration value, with the ENABLE bit set to 1.
group-onsemi 0:098463de4c5d 240 obj->uart->CFG &= ~(1 << 0);
group-onsemi 0:098463de4c5d 241
group-onsemi 0:098463de4c5d 242 obj->uart->CFG = (1 << 0) // this will enable the usart
group-onsemi 0:098463de4c5d 243 | (data_bits << 2)
group-onsemi 0:098463de4c5d 244 | (paritysel << 4)
group-onsemi 0:098463de4c5d 245 | (stop_bits << 6);
group-onsemi 0:098463de4c5d 246 }
group-onsemi 0:098463de4c5d 247
group-onsemi 0:098463de4c5d 248 /******************************************************************************
group-onsemi 0:098463de4c5d 249 * INTERRUPTS HANDLING
group-onsemi 0:098463de4c5d 250 ******************************************************************************/
group-onsemi 0:098463de4c5d 251 static inline void uart_irq(SerialIrq irq_type, uint32_t index)
group-onsemi 0:098463de4c5d 252 {
group-onsemi 0:098463de4c5d 253 if (serial_irq_ids[index] != 0)
group-onsemi 0:098463de4c5d 254 irq_handler(serial_irq_ids[index], irq_type);
group-onsemi 0:098463de4c5d 255 }
group-onsemi 0:098463de4c5d 256
group-onsemi 0:098463de4c5d 257 void uart0_irq() {uart_irq((LPC_USART0->INTSTAT & RXRDY) ? RxIrq : TxIrq, 0);}
group-onsemi 0:098463de4c5d 258 void uart1_irq() {uart_irq((LPC_USART1->INTSTAT & RXRDY) ? RxIrq : TxIrq, 1);}
group-onsemi 0:098463de4c5d 259 void uart2_irq() {uart_irq((LPC_USART2->INTSTAT & RXRDY) ? RxIrq : TxIrq, 2);}
group-onsemi 0:098463de4c5d 260
group-onsemi 0:098463de4c5d 261 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
group-onsemi 0:098463de4c5d 262 {
group-onsemi 0:098463de4c5d 263 irq_handler = handler;
group-onsemi 0:098463de4c5d 264 serial_irq_ids[obj->index] = id;
group-onsemi 0:098463de4c5d 265 }
group-onsemi 0:098463de4c5d 266
group-onsemi 0:098463de4c5d 267 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
group-onsemi 0:098463de4c5d 268 {
group-onsemi 0:098463de4c5d 269 IRQn_Type irq_n = (IRQn_Type)0;
group-onsemi 0:098463de4c5d 270 uint32_t vector = 0;
group-onsemi 0:098463de4c5d 271 switch ((int)obj->uart) {
group-onsemi 0:098463de4c5d 272 case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
group-onsemi 0:098463de4c5d 273 case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
group-onsemi 0:098463de4c5d 274 case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
group-onsemi 0:098463de4c5d 275 }
group-onsemi 0:098463de4c5d 276
group-onsemi 0:098463de4c5d 277 if (enable) {
group-onsemi 0:098463de4c5d 278 NVIC_DisableIRQ(irq_n);
group-onsemi 0:098463de4c5d 279 obj->uart->INTENSET |= (1 << ((irq == RxIrq) ? 0 : 2));
group-onsemi 0:098463de4c5d 280 NVIC_SetVector(irq_n, vector);
group-onsemi 0:098463de4c5d 281 NVIC_EnableIRQ(irq_n);
group-onsemi 0:098463de4c5d 282 } else { // disable
group-onsemi 0:098463de4c5d 283 obj->uart->INTENCLR |= (1 << ((irq == RxIrq) ? 0 : 2));
group-onsemi 0:098463de4c5d 284 if ( (obj->uart->INTENSET & (RXRDYEN | TXRDYEN)) == 0) {
group-onsemi 0:098463de4c5d 285 NVIC_DisableIRQ(irq_n);
group-onsemi 0:098463de4c5d 286 }
group-onsemi 0:098463de4c5d 287 }
group-onsemi 0:098463de4c5d 288 }
group-onsemi 0:098463de4c5d 289
group-onsemi 0:098463de4c5d 290 /******************************************************************************
group-onsemi 0:098463de4c5d 291 * READ/WRITE
group-onsemi 0:098463de4c5d 292 ******************************************************************************/
group-onsemi 0:098463de4c5d 293 int serial_getc(serial_t *obj)
group-onsemi 0:098463de4c5d 294 {
group-onsemi 0:098463de4c5d 295 while (!serial_readable(obj));
group-onsemi 0:098463de4c5d 296 return obj->uart->RXDAT;
group-onsemi 0:098463de4c5d 297 }
group-onsemi 0:098463de4c5d 298
group-onsemi 0:098463de4c5d 299 void serial_putc(serial_t *obj, int c)
group-onsemi 0:098463de4c5d 300 {
group-onsemi 0:098463de4c5d 301 while (!serial_writable(obj));
group-onsemi 0:098463de4c5d 302 obj->uart->TXDAT = c;
group-onsemi 0:098463de4c5d 303 }
group-onsemi 0:098463de4c5d 304
group-onsemi 0:098463de4c5d 305 int serial_readable(serial_t *obj)
group-onsemi 0:098463de4c5d 306 {
group-onsemi 0:098463de4c5d 307 return obj->uart->STAT & RXRDY;
group-onsemi 0:098463de4c5d 308 }
group-onsemi 0:098463de4c5d 309
group-onsemi 0:098463de4c5d 310 int serial_writable(serial_t *obj)
group-onsemi 0:098463de4c5d 311 {
group-onsemi 0:098463de4c5d 312 return obj->uart->STAT & TXRDY;
group-onsemi 0:098463de4c5d 313 }
group-onsemi 0:098463de4c5d 314
group-onsemi 0:098463de4c5d 315 void serial_clear(serial_t *obj)
group-onsemi 0:098463de4c5d 316 {
group-onsemi 0:098463de4c5d 317 // [TODO]
group-onsemi 0:098463de4c5d 318 }
group-onsemi 0:098463de4c5d 319
group-onsemi 0:098463de4c5d 320 void serial_pinout_tx(PinName tx)
group-onsemi 0:098463de4c5d 321 {
group-onsemi 0:098463de4c5d 322
group-onsemi 0:098463de4c5d 323 }
group-onsemi 0:098463de4c5d 324
group-onsemi 0:098463de4c5d 325 void serial_break_set(serial_t *obj)
group-onsemi 0:098463de4c5d 326 {
group-onsemi 0:098463de4c5d 327 obj->uart->CTL |= TXBRKEN;
group-onsemi 0:098463de4c5d 328 }
group-onsemi 0:098463de4c5d 329
group-onsemi 0:098463de4c5d 330 void serial_break_clear(serial_t *obj)
group-onsemi 0:098463de4c5d 331 {
group-onsemi 0:098463de4c5d 332 obj->uart->CTL &= ~TXBRKEN;
group-onsemi 0:098463de4c5d 333 }
group-onsemi 0:098463de4c5d 334
group-onsemi 0:098463de4c5d 335 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
group-onsemi 0:098463de4c5d 336 {
group-onsemi 0:098463de4c5d 337 const SWM_Map *swm_rts, *swm_cts;
group-onsemi 0:098463de4c5d 338 uint32_t regVal_rts, regVal_cts;
group-onsemi 0:098463de4c5d 339
group-onsemi 0:098463de4c5d 340 swm_rts = &SWM_UART_RTS[obj->index];
group-onsemi 0:098463de4c5d 341 swm_cts = &SWM_UART_CTS[obj->index];
group-onsemi 0:098463de4c5d 342 regVal_rts = LPC_SWM->PINASSIGN[swm_rts->n] & ~(0xFF << swm_rts->offset);
group-onsemi 0:098463de4c5d 343 regVal_cts = LPC_SWM->PINASSIGN[swm_cts->n] & ~(0xFF << swm_cts->offset);
group-onsemi 0:098463de4c5d 344
group-onsemi 0:098463de4c5d 345 if (FlowControlNone == type) {
group-onsemi 0:098463de4c5d 346 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
group-onsemi 0:098463de4c5d 347 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
group-onsemi 0:098463de4c5d 348 obj->uart->CFG &= ~CTSEN;
group-onsemi 0:098463de4c5d 349 return;
group-onsemi 0:098463de4c5d 350 }
group-onsemi 0:098463de4c5d 351 if ((FlowControlRTS == type || FlowControlRTSCTS == type) && (rxflow != NC)) {
group-onsemi 0:098463de4c5d 352 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | ((rxflow >> PIN_SHIFT) << swm_rts->offset);
group-onsemi 0:098463de4c5d 353 if (FlowControlRTS == type) {
group-onsemi 0:098463de4c5d 354 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
group-onsemi 0:098463de4c5d 355 obj->uart->CFG &= ~CTSEN;
group-onsemi 0:098463de4c5d 356 }
group-onsemi 0:098463de4c5d 357 }
group-onsemi 0:098463de4c5d 358 if ((FlowControlCTS == type || FlowControlRTSCTS == type) && (txflow != NC)) {
group-onsemi 0:098463de4c5d 359 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | ((txflow >> PIN_SHIFT) << swm_cts->offset);
group-onsemi 0:098463de4c5d 360 obj->uart->CFG |= CTSEN;
group-onsemi 0:098463de4c5d 361 if (FlowControlCTS == type) {
group-onsemi 0:098463de4c5d 362 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
group-onsemi 0:098463de4c5d 363 }
group-onsemi 0:098463de4c5d 364 }
group-onsemi 0:098463de4c5d 365 }
group-onsemi 0:098463de4c5d 366
group-onsemi 0:098463de4c5d 367 #endif