ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC82X/pwmout_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 17 #include "pwmout_api.h"
group-onsemi 0:098463de4c5d 18 #include "cmsis.h"
group-onsemi 0:098463de4c5d 19 #include "pinmap.h"
group-onsemi 0:098463de4c5d 20 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 21
group-onsemi 0:098463de4c5d 22 #if DEVICE_PWMOUT
group-onsemi 0:098463de4c5d 23
group-onsemi 0:098463de4c5d 24 // bit flags for used SCTs
group-onsemi 0:098463de4c5d 25 static unsigned char sct_used = 0;
group-onsemi 0:098463de4c5d 26
group-onsemi 0:098463de4c5d 27 static int get_available_sct()
group-onsemi 0:098463de4c5d 28 {
group-onsemi 0:098463de4c5d 29 int i;
group-onsemi 0:098463de4c5d 30 for (i = 0; i < 4; i++) {
group-onsemi 0:098463de4c5d 31 if ((sct_used & (1 << i)) == 0)
group-onsemi 0:098463de4c5d 32 return i;
group-onsemi 0:098463de4c5d 33 }
group-onsemi 0:098463de4c5d 34 return -1;
group-onsemi 0:098463de4c5d 35 }
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 void pwmout_init(pwmout_t* obj, PinName pin)
group-onsemi 0:098463de4c5d 38 {
group-onsemi 0:098463de4c5d 39 MBED_ASSERT(pin != (PinName)NC);
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 int sct_n = get_available_sct();
group-onsemi 0:098463de4c5d 42 if (sct_n == -1) {
group-onsemi 0:098463de4c5d 43 error("No available SCT");
group-onsemi 0:098463de4c5d 44 }
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 sct_used |= (1 << sct_n);
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 obj->pwm = (LPC_SCT_Type*)LPC_SCT;
group-onsemi 0:098463de4c5d 49 obj->pwm_ch = sct_n;
group-onsemi 0:098463de4c5d 50
group-onsemi 0:098463de4c5d 51 LPC_SCT_Type* pwm = obj->pwm;
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 // Enable the SCT clock
group-onsemi 0:098463de4c5d 54 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
group-onsemi 0:098463de4c5d 55
group-onsemi 0:098463de4c5d 56 // Clear peripheral reset the SCT:
group-onsemi 0:098463de4c5d 57 LPC_SYSCON->PRESETCTRL |= (1 << 8);
group-onsemi 0:098463de4c5d 58
group-onsemi 0:098463de4c5d 59 switch(sct_n) {
group-onsemi 0:098463de4c5d 60 case 0:
group-onsemi 0:098463de4c5d 61 // SCT_OUT0
group-onsemi 0:098463de4c5d 62 LPC_SWM->PINASSIGN[7] &= ~0xFF000000;
group-onsemi 0:098463de4c5d 63 LPC_SWM->PINASSIGN[7] |= ((pin >> PIN_SHIFT) << 24);
group-onsemi 0:098463de4c5d 64 break;
group-onsemi 0:098463de4c5d 65 case 1:
group-onsemi 0:098463de4c5d 66 // SCT_OUT1
group-onsemi 0:098463de4c5d 67 LPC_SWM->PINASSIGN[8] &= ~0x000000FF;
group-onsemi 0:098463de4c5d 68 LPC_SWM->PINASSIGN[8] |= (pin >> PIN_SHIFT);
group-onsemi 0:098463de4c5d 69 break;
group-onsemi 0:098463de4c5d 70 case 2:
group-onsemi 0:098463de4c5d 71 // SCT2_OUT2
group-onsemi 0:098463de4c5d 72 LPC_SWM->PINASSIGN[8] &= ~0x0000FF00;
group-onsemi 0:098463de4c5d 73 LPC_SWM->PINASSIGN[8] |= ((pin >> PIN_SHIFT) << 8);
group-onsemi 0:098463de4c5d 74 break;
group-onsemi 0:098463de4c5d 75 case 3:
group-onsemi 0:098463de4c5d 76 // SCT3_OUT3
group-onsemi 0:098463de4c5d 77 LPC_SWM->PINASSIGN[8] &= ~0x00FF0000;
group-onsemi 0:098463de4c5d 78 LPC_SWM->PINASSIGN[8] |= ((pin >> PIN_SHIFT) << 16);
group-onsemi 0:098463de4c5d 79 break;
group-onsemi 0:098463de4c5d 80 default:
group-onsemi 0:098463de4c5d 81 break;
group-onsemi 0:098463de4c5d 82 }
group-onsemi 0:098463de4c5d 83
group-onsemi 0:098463de4c5d 84 // Unified 32-bit counter, autolimit
group-onsemi 0:098463de4c5d 85 pwm->CONFIG |= ((0x3 << 17) | 0x01);
group-onsemi 0:098463de4c5d 86
group-onsemi 0:098463de4c5d 87 // halt and clear the counter
group-onsemi 0:098463de4c5d 88 pwm->CTRL |= (1 << 2) | (1 << 3);
group-onsemi 0:098463de4c5d 89
group-onsemi 0:098463de4c5d 90 // System Clock -> us_ticker (1)MHz
group-onsemi 0:098463de4c5d 91 pwm->CTRL &= ~(0x7F << 5);
group-onsemi 0:098463de4c5d 92 pwm->CTRL |= (((SystemCoreClock/1000000 - 1) & 0x7F) << 5);
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 // Set event number
group-onsemi 0:098463de4c5d 95 pwm->OUT[sct_n].SET = (1 << ((sct_n * 2) + 0));
group-onsemi 0:098463de4c5d 96 pwm->OUT[sct_n].CLR = (1 << ((sct_n * 2) + 1));
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98 pwm->EVENT[(sct_n * 2) + 0].CTRL = (1 << 12) | ((sct_n * 2) + 0); // match event
group-onsemi 0:098463de4c5d 99 pwm->EVENT[(sct_n * 2) + 0].STATE = 0xFFFFFFFF;
group-onsemi 0:098463de4c5d 100 pwm->EVENT[(sct_n * 2) + 1].CTRL = (1 << 12) | ((sct_n * 2) + 1);
group-onsemi 0:098463de4c5d 101 pwm->EVENT[(sct_n * 2) + 1].STATE = 0xFFFFFFFF;
group-onsemi 0:098463de4c5d 102
group-onsemi 0:098463de4c5d 103 // default to 20ms: standard for servos, and fine for e.g. brightness control
group-onsemi 0:098463de4c5d 104 pwmout_period_ms(obj, 20);
group-onsemi 0:098463de4c5d 105 pwmout_write (obj, 0);
group-onsemi 0:098463de4c5d 106 }
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 void pwmout_free(pwmout_t* obj)
group-onsemi 0:098463de4c5d 109 {
group-onsemi 0:098463de4c5d 110 // Disable the SCT clock
group-onsemi 0:098463de4c5d 111 LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
group-onsemi 0:098463de4c5d 112 sct_used &= ~(1 << obj->pwm_ch);
group-onsemi 0:098463de4c5d 113 }
group-onsemi 0:098463de4c5d 114
group-onsemi 0:098463de4c5d 115 void pwmout_write(pwmout_t* obj, float value)
group-onsemi 0:098463de4c5d 116 {
group-onsemi 0:098463de4c5d 117 if (value < 0.0f) {
group-onsemi 0:098463de4c5d 118 value = 0.0;
group-onsemi 0:098463de4c5d 119 } else if (value > 1.0f) {
group-onsemi 0:098463de4c5d 120 value = 1.0f;
group-onsemi 0:098463de4c5d 121 }
group-onsemi 0:098463de4c5d 122 uint32_t t_on = (uint32_t)((float)(obj->pwm->MATCHREL[obj->pwm_ch * 2] + 1) * value);
group-onsemi 0:098463de4c5d 123 if (t_on > 0) { // duty is not 0%
group-onsemi 0:098463de4c5d 124 if (value != 1.0f) { // duty is not 100%
group-onsemi 0:098463de4c5d 125 obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = t_on - 1;
group-onsemi 0:098463de4c5d 126 // unhalt the counter
group-onsemi 0:098463de4c5d 127 obj->pwm->CTRL &= ~(1 << 2);
group-onsemi 0:098463de4c5d 128 } else { // duty is 100%
group-onsemi 0:098463de4c5d 129 // halt and clear the counter
group-onsemi 0:098463de4c5d 130 obj->pwm->CTRL |= (1 << 2) | (1 << 3);
group-onsemi 0:098463de4c5d 131 // output level tied to high
group-onsemi 0:098463de4c5d 132 obj->pwm->OUTPUT |= (1 << obj->pwm_ch);
group-onsemi 0:098463de4c5d 133 }
group-onsemi 0:098463de4c5d 134 } else { // duty is 0%
group-onsemi 0:098463de4c5d 135 // halt and clear the counter
group-onsemi 0:098463de4c5d 136 obj->pwm->CTRL |= (1 << 2) | (1 << 3);
group-onsemi 0:098463de4c5d 137 // output level tied to low
group-onsemi 0:098463de4c5d 138 obj->pwm->OUTPUT &= ~(1 << obj->pwm_ch);
group-onsemi 0:098463de4c5d 139 }
group-onsemi 0:098463de4c5d 140 }
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142 float pwmout_read(pwmout_t* obj)
group-onsemi 0:098463de4c5d 143 {
group-onsemi 0:098463de4c5d 144 uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] + 1;
group-onsemi 0:098463de4c5d 145 uint32_t t_on = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] + 1;
group-onsemi 0:098463de4c5d 146 float v = (float)t_on/(float)t_off;
group-onsemi 0:098463de4c5d 147 return (v > 1.0f) ? (1.0f) : (v);
group-onsemi 0:098463de4c5d 148 }
group-onsemi 0:098463de4c5d 149
group-onsemi 0:098463de4c5d 150 void pwmout_period(pwmout_t* obj, float seconds)
group-onsemi 0:098463de4c5d 151 {
group-onsemi 0:098463de4c5d 152 pwmout_period_us(obj, seconds * 1000000.0f);
group-onsemi 0:098463de4c5d 153 }
group-onsemi 0:098463de4c5d 154
group-onsemi 0:098463de4c5d 155 void pwmout_period_ms(pwmout_t* obj, int ms)
group-onsemi 0:098463de4c5d 156 {
group-onsemi 0:098463de4c5d 157 pwmout_period_us(obj, ms * 1000);
group-onsemi 0:098463de4c5d 158 }
group-onsemi 0:098463de4c5d 159
group-onsemi 0:098463de4c5d 160 // Set the PWM period, keeping the duty cycle the same.
group-onsemi 0:098463de4c5d 161 void pwmout_period_us(pwmout_t* obj, int us)
group-onsemi 0:098463de4c5d 162 {
group-onsemi 0:098463de4c5d 163 // The period are off by one for MATCHREL, so +1 to get actual value
group-onsemi 0:098463de4c5d 164 uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] + 1;
group-onsemi 0:098463de4c5d 165 uint32_t t_on = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] + 1;
group-onsemi 0:098463de4c5d 166 float v = (float)t_on/(float)t_off;
group-onsemi 0:098463de4c5d 167 obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] = (uint32_t)us - 1;
group-onsemi 0:098463de4c5d 168 if (us > 0) { // PWM period is not 0
group-onsemi 0:098463de4c5d 169 obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint32_t)((float)us * (float)v) - 1;
group-onsemi 0:098463de4c5d 170 // unhalt the counter
group-onsemi 0:098463de4c5d 171 obj->pwm->CTRL &= ~(1 << 2);
group-onsemi 0:098463de4c5d 172 } else { // PWM period is 0
group-onsemi 0:098463de4c5d 173 // halt and clear the counter
group-onsemi 0:098463de4c5d 174 obj->pwm->CTRL |= (1 << 2) | (1 << 3);
group-onsemi 0:098463de4c5d 175 // output level tied to low
group-onsemi 0:098463de4c5d 176 obj->pwm->OUTPUT &= ~(1 << obj->pwm_ch);
group-onsemi 0:098463de4c5d 177 }
group-onsemi 0:098463de4c5d 178 }
group-onsemi 0:098463de4c5d 179
group-onsemi 0:098463de4c5d 180 void pwmout_pulsewidth(pwmout_t* obj, float seconds)
group-onsemi 0:098463de4c5d 181 {
group-onsemi 0:098463de4c5d 182 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
group-onsemi 0:098463de4c5d 183 }
group-onsemi 0:098463de4c5d 184
group-onsemi 0:098463de4c5d 185 void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
group-onsemi 0:098463de4c5d 186 {
group-onsemi 0:098463de4c5d 187 pwmout_pulsewidth_us(obj, ms * 1000);
group-onsemi 0:098463de4c5d 188 }
group-onsemi 0:098463de4c5d 189
group-onsemi 0:098463de4c5d 190 void pwmout_pulsewidth_us(pwmout_t* obj, int us)
group-onsemi 0:098463de4c5d 191 {
group-onsemi 0:098463de4c5d 192 if (us > 0) { // PWM peried is not 0
group-onsemi 0:098463de4c5d 193 obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint32_t)us - 1;
group-onsemi 0:098463de4c5d 194 obj->pwm->CTRL &= ~(1 << 2);
group-onsemi 0:098463de4c5d 195 } else { //PWM period is 0
group-onsemi 0:098463de4c5d 196 // halt and clear the counter
group-onsemi 0:098463de4c5d 197 obj->pwm->CTRL |= (1 << 2) | (1 << 3);
group-onsemi 0:098463de4c5d 198 // output level tied to low
group-onsemi 0:098463de4c5d 199 obj->pwm->OUTPUT &= ~(1 << obj->pwm_ch);
group-onsemi 0:098463de4c5d 200 }
group-onsemi 0:098463de4c5d 201 }
group-onsemi 0:098463de4c5d 202
group-onsemi 0:098463de4c5d 203 #endif