ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC11UXX/pinmap.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 17 #include "pinmap.h"
group-onsemi 0:098463de4c5d 18 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 19
group-onsemi 0:098463de4c5d 20 #define LPC_IOCON0_BASE (LPC_IOCON_BASE)
group-onsemi 0:098463de4c5d 21 #define LPC_IOCON1_BASE (LPC_IOCON_BASE + 0x60)
group-onsemi 0:098463de4c5d 22
group-onsemi 0:098463de4c5d 23 void pin_function(PinName pin, int function) {
group-onsemi 0:098463de4c5d 24 MBED_ASSERT(pin != (PinName)NC);
group-onsemi 0:098463de4c5d 25 if (pin == (PinName)NC) return;
group-onsemi 0:098463de4c5d 26
group-onsemi 0:098463de4c5d 27 uint32_t pin_number = (uint32_t)pin;
group-onsemi 0:098463de4c5d 28
group-onsemi 0:098463de4c5d 29 __IO uint32_t *reg = (pin_number < 32) ?
group-onsemi 0:098463de4c5d 30 (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
group-onsemi 0:098463de4c5d 31 (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
group-onsemi 0:098463de4c5d 32
group-onsemi 0:098463de4c5d 33 // pin function bits: [2:0] -> 111 = (0x7)
group-onsemi 0:098463de4c5d 34 *reg = (*reg & ~0x7) | (function & 0x7);
group-onsemi 0:098463de4c5d 35 }
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 void pin_mode(PinName pin, PinMode mode) {
group-onsemi 0:098463de4c5d 38 MBED_ASSERT(pin != (PinName)NC);
group-onsemi 0:098463de4c5d 39 uint32_t pin_number = (uint32_t)pin;
group-onsemi 0:098463de4c5d 40 uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2;
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 __IO uint32_t *reg = (pin_number < 32) ?
group-onsemi 0:098463de4c5d 43 (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
group-onsemi 0:098463de4c5d 44 (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
group-onsemi 0:098463de4c5d 45 uint32_t tmp = *reg;
group-onsemi 0:098463de4c5d 46
group-onsemi 0:098463de4c5d 47 // pin mode bits: [4:3] -> 11000 = (0x3 << 3)
group-onsemi 0:098463de4c5d 48 tmp &= ~(0x3 << 3);
group-onsemi 0:098463de4c5d 49 tmp |= (mode & 0x3) << 3;
group-onsemi 0:098463de4c5d 50
group-onsemi 0:098463de4c5d 51 // drain
group-onsemi 0:098463de4c5d 52 tmp &= ~(0x1 << 10);
group-onsemi 0:098463de4c5d 53 tmp |= drain << 10;
group-onsemi 0:098463de4c5d 54
group-onsemi 0:098463de4c5d 55 *reg = tmp;
group-onsemi 0:098463de4c5d 56 }