ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NUVOTON/TARGET_M451/spi_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2015-2016 Nuvoton
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16
group-onsemi 0:098463de4c5d 17 #include "spi_api.h"
group-onsemi 0:098463de4c5d 18
group-onsemi 0:098463de4c5d 19 #if DEVICE_SPI
group-onsemi 0:098463de4c5d 20
group-onsemi 0:098463de4c5d 21 #include "cmsis.h"
group-onsemi 0:098463de4c5d 22 #include "pinmap.h"
group-onsemi 0:098463de4c5d 23 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 24 #include "nu_modutil.h"
group-onsemi 0:098463de4c5d 25 #include "nu_miscutil.h"
group-onsemi 0:098463de4c5d 26 #include "nu_bitutil.h"
group-onsemi 0:098463de4c5d 27
group-onsemi 0:098463de4c5d 28 #if DEVICE_SPI_ASYNCH
group-onsemi 0:098463de4c5d 29 #include "dma_api.h"
group-onsemi 0:098463de4c5d 30 #include "dma.h"
group-onsemi 0:098463de4c5d 31 #endif
group-onsemi 0:098463de4c5d 32
group-onsemi 0:098463de4c5d 33 #define NU_SPI_FRAME_MIN 8
group-onsemi 0:098463de4c5d 34 #define NU_SPI_FRAME_MAX 32
group-onsemi 0:098463de4c5d 35 #define NU_SPI_FIFO_DEPTH 8
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 struct nu_spi_var {
group-onsemi 0:098463de4c5d 38 #if DEVICE_SPI_ASYNCH
group-onsemi 0:098463de4c5d 39 uint8_t pdma_perp_tx;
group-onsemi 0:098463de4c5d 40 uint8_t pdma_perp_rx;
group-onsemi 0:098463de4c5d 41 #endif
group-onsemi 0:098463de4c5d 42 };
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 static struct nu_spi_var spi0_var = {
group-onsemi 0:098463de4c5d 45 #if DEVICE_SPI_ASYNCH
group-onsemi 0:098463de4c5d 46 .pdma_perp_tx = PDMA_SPI0_TX,
group-onsemi 0:098463de4c5d 47 .pdma_perp_rx = PDMA_SPI0_RX
group-onsemi 0:098463de4c5d 48 #endif
group-onsemi 0:098463de4c5d 49 };
group-onsemi 0:098463de4c5d 50 static struct nu_spi_var spi1_var = {
group-onsemi 0:098463de4c5d 51 #if DEVICE_SPI_ASYNCH
group-onsemi 0:098463de4c5d 52 .pdma_perp_tx = PDMA_SPI1_TX,
group-onsemi 0:098463de4c5d 53 .pdma_perp_rx = PDMA_SPI1_RX
group-onsemi 0:098463de4c5d 54 #endif
group-onsemi 0:098463de4c5d 55 };
group-onsemi 0:098463de4c5d 56 static struct nu_spi_var spi2_var = {
group-onsemi 0:098463de4c5d 57 #if DEVICE_SPI_ASYNCH
group-onsemi 0:098463de4c5d 58 .pdma_perp_tx = PDMA_SPI2_TX,
group-onsemi 0:098463de4c5d 59 .pdma_perp_rx = PDMA_SPI2_RX
group-onsemi 0:098463de4c5d 60 #endif
group-onsemi 0:098463de4c5d 61 };
group-onsemi 0:098463de4c5d 62
group-onsemi 0:098463de4c5d 63 #if DEVICE_SPI_ASYNCH
group-onsemi 0:098463de4c5d 64 static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable);
group-onsemi 0:098463de4c5d 65 static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable);
group-onsemi 0:098463de4c5d 66 static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit);
group-onsemi 0:098463de4c5d 67 static uint32_t spi_master_read_asynch(spi_t *obj);
group-onsemi 0:098463de4c5d 68 static uint32_t spi_event_check(spi_t *obj);
group-onsemi 0:098463de4c5d 69 static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable);
group-onsemi 0:098463de4c5d 70 static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
group-onsemi 0:098463de4c5d 71 static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx);
group-onsemi 0:098463de4c5d 72 static uint8_t spi_get_data_width(spi_t *obj);
group-onsemi 0:098463de4c5d 73 static int spi_is_tx_complete(spi_t *obj);
group-onsemi 0:098463de4c5d 74 static int spi_is_rx_complete(spi_t *obj);
group-onsemi 0:098463de4c5d 75 static int spi_writeable(spi_t * obj);
group-onsemi 0:098463de4c5d 76 static int spi_readable(spi_t * obj);
group-onsemi 0:098463de4c5d 77 static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma);
group-onsemi 0:098463de4c5d 78 static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma);
group-onsemi 0:098463de4c5d 79 #endif
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 static uint32_t spi_modinit_mask = 0;
group-onsemi 0:098463de4c5d 82
group-onsemi 0:098463de4c5d 83 static const struct nu_modinit_s spi_modinit_tab[] = {
group-onsemi 0:098463de4c5d 84 {SPI_0, SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK0, MODULE_NoMsk, SPI0_RST, SPI0_IRQn, &spi0_var},
group-onsemi 0:098463de4c5d 85 {SPI_1, SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PCLK1, MODULE_NoMsk, SPI1_RST, SPI1_IRQn, &spi1_var},
group-onsemi 0:098463de4c5d 86 {SPI_2, SPI2_MODULE, CLK_CLKSEL2_SPI2SEL_PCLK0, MODULE_NoMsk, SPI2_RST, SPI2_IRQn, &spi2_var},
group-onsemi 0:098463de4c5d 87
group-onsemi 0:098463de4c5d 88 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
group-onsemi 0:098463de4c5d 89 };
group-onsemi 0:098463de4c5d 90
group-onsemi 0:098463de4c5d 91 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
group-onsemi 0:098463de4c5d 92 // Determine which SPI_x the pins are used for
group-onsemi 0:098463de4c5d 93 uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
group-onsemi 0:098463de4c5d 94 uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
group-onsemi 0:098463de4c5d 95 uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
group-onsemi 0:098463de4c5d 96 uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
group-onsemi 0:098463de4c5d 97 uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
group-onsemi 0:098463de4c5d 98 uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
group-onsemi 0:098463de4c5d 99 obj->spi.spi = (SPIName) pinmap_merge(spi_data, spi_cntl);
group-onsemi 0:098463de4c5d 100 MBED_ASSERT((int)obj->spi.spi != NC);
group-onsemi 0:098463de4c5d 101
group-onsemi 0:098463de4c5d 102 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
group-onsemi 0:098463de4c5d 103 MBED_ASSERT(modinit != NULL);
group-onsemi 0:098463de4c5d 104 MBED_ASSERT(modinit->modname == obj->spi.spi);
group-onsemi 0:098463de4c5d 105
group-onsemi 0:098463de4c5d 106 // Reset this module
group-onsemi 0:098463de4c5d 107 SYS_ResetModule(modinit->rsetidx);
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109 // Select IP clock source
group-onsemi 0:098463de4c5d 110 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
group-onsemi 0:098463de4c5d 111 // Enable IP clock
group-onsemi 0:098463de4c5d 112 CLK_EnableModuleClock(modinit->clkidx);
group-onsemi 0:098463de4c5d 113
group-onsemi 0:098463de4c5d 114 //SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 pinmap_pinout(mosi, PinMap_SPI_MOSI);
group-onsemi 0:098463de4c5d 117 pinmap_pinout(miso, PinMap_SPI_MISO);
group-onsemi 0:098463de4c5d 118 pinmap_pinout(sclk, PinMap_SPI_SCLK);
group-onsemi 0:098463de4c5d 119 pinmap_pinout(ssel, PinMap_SPI_SSEL);
group-onsemi 0:098463de4c5d 120
group-onsemi 0:098463de4c5d 121 obj->spi.pin_mosi = mosi;
group-onsemi 0:098463de4c5d 122 obj->spi.pin_miso = miso;
group-onsemi 0:098463de4c5d 123 obj->spi.pin_sclk = sclk;
group-onsemi 0:098463de4c5d 124 obj->spi.pin_ssel = ssel;
group-onsemi 0:098463de4c5d 125
group-onsemi 0:098463de4c5d 126
group-onsemi 0:098463de4c5d 127 // Configure the SPI data format and frequency
group-onsemi 0:098463de4c5d 128 //spi_format(obj, 8, 0, SPI_MSB); // 8 bits, mode 0
group-onsemi 0:098463de4c5d 129 //spi_frequency(obj, 1000000);
group-onsemi 0:098463de4c5d 130
group-onsemi 0:098463de4c5d 131 #if DEVICE_SPI_ASYNCH
group-onsemi 0:098463de4c5d 132 obj->spi.dma_usage = DMA_USAGE_NEVER;
group-onsemi 0:098463de4c5d 133 obj->spi.event = 0;
group-onsemi 0:098463de4c5d 134 obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
group-onsemi 0:098463de4c5d 135 obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
group-onsemi 0:098463de4c5d 136 #endif
group-onsemi 0:098463de4c5d 137
group-onsemi 0:098463de4c5d 138 // Mark this module to be inited.
group-onsemi 0:098463de4c5d 139 int i = modinit - spi_modinit_tab;
group-onsemi 0:098463de4c5d 140 spi_modinit_mask |= 1 << i;
group-onsemi 0:098463de4c5d 141 }
group-onsemi 0:098463de4c5d 142
group-onsemi 0:098463de4c5d 143 void spi_free(spi_t *obj)
group-onsemi 0:098463de4c5d 144 {
group-onsemi 0:098463de4c5d 145 #if DEVICE_SPI_ASYNCH
group-onsemi 0:098463de4c5d 146 if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
group-onsemi 0:098463de4c5d 147 dma_channel_free(obj->spi.dma_chn_id_tx);
group-onsemi 0:098463de4c5d 148 obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
group-onsemi 0:098463de4c5d 149 }
group-onsemi 0:098463de4c5d 150 if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
group-onsemi 0:098463de4c5d 151 dma_channel_free(obj->spi.dma_chn_id_rx);
group-onsemi 0:098463de4c5d 152 obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
group-onsemi 0:098463de4c5d 153 }
group-onsemi 0:098463de4c5d 154 #endif
group-onsemi 0:098463de4c5d 155
group-onsemi 0:098463de4c5d 156 SPI_Close((SPI_T *) NU_MODBASE(obj->spi.spi));
group-onsemi 0:098463de4c5d 157
group-onsemi 0:098463de4c5d 158 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
group-onsemi 0:098463de4c5d 159 MBED_ASSERT(modinit != NULL);
group-onsemi 0:098463de4c5d 160 MBED_ASSERT(modinit->modname == obj->spi.spi);
group-onsemi 0:098463de4c5d 161
group-onsemi 0:098463de4c5d 162 SPI_DisableInt(((SPI_T *) NU_MODBASE(obj->spi.spi)), (SPI_FIFO_RXOV_INT_MASK | SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK));
group-onsemi 0:098463de4c5d 163 NVIC_DisableIRQ(modinit->irq_n);
group-onsemi 0:098463de4c5d 164
group-onsemi 0:098463de4c5d 165 // Disable IP clock
group-onsemi 0:098463de4c5d 166 CLK_DisableModuleClock(modinit->clkidx);
group-onsemi 0:098463de4c5d 167
group-onsemi 0:098463de4c5d 168 //((struct nu_spi_var *) modinit->var)->obj = NULL;
group-onsemi 0:098463de4c5d 169
group-onsemi 0:098463de4c5d 170 // Mark this module to be deinited.
group-onsemi 0:098463de4c5d 171 int i = modinit - spi_modinit_tab;
group-onsemi 0:098463de4c5d 172 spi_modinit_mask &= ~(1 << i);
group-onsemi 0:098463de4c5d 173 }
group-onsemi 0:098463de4c5d 174 void spi_format(spi_t *obj, int bits, int mode, int slave)
group-onsemi 0:098463de4c5d 175 {
group-onsemi 0:098463de4c5d 176 MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
group-onsemi 0:098463de4c5d 177
group-onsemi 0:098463de4c5d 178 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 179
group-onsemi 0:098463de4c5d 180 // NOTE 1: All configurations should be ready before enabling SPI peripheral.
group-onsemi 0:098463de4c5d 181 // NOTE 2: Re-configuration is allowed only as SPI peripheral is idle.
group-onsemi 0:098463de4c5d 182 while (SPI_IS_BUSY(spi_base));
group-onsemi 0:098463de4c5d 183 SPI_DISABLE(spi_base);
group-onsemi 0:098463de4c5d 184
group-onsemi 0:098463de4c5d 185 SPI_Open(spi_base,
group-onsemi 0:098463de4c5d 186 slave ? SPI_SLAVE : SPI_MASTER,
group-onsemi 0:098463de4c5d 187 (mode == 0) ? SPI_MODE_0 : (mode == 1) ? SPI_MODE_1 : (mode == 2) ? SPI_MODE_2 : SPI_MODE_3,
group-onsemi 0:098463de4c5d 188 bits,
group-onsemi 0:098463de4c5d 189 SPI_GetBusClock(spi_base));
group-onsemi 0:098463de4c5d 190 // NOTE: Hardcode to be MSB first.
group-onsemi 0:098463de4c5d 191 SPI_SET_MSB_FIRST(spi_base);
group-onsemi 0:098463de4c5d 192
group-onsemi 0:098463de4c5d 193 if (! slave) {
group-onsemi 0:098463de4c5d 194 // Master
group-onsemi 0:098463de4c5d 195 if (obj->spi.pin_ssel != NC) {
group-onsemi 0:098463de4c5d 196 // Configure SS as low active.
group-onsemi 0:098463de4c5d 197 SPI_EnableAutoSS(spi_base, SPI_SS, SPI_SS_ACTIVE_LOW);
group-onsemi 0:098463de4c5d 198 }
group-onsemi 0:098463de4c5d 199 else {
group-onsemi 0:098463de4c5d 200 SPI_DisableAutoSS(spi_base);
group-onsemi 0:098463de4c5d 201 }
group-onsemi 0:098463de4c5d 202 }
group-onsemi 0:098463de4c5d 203 else {
group-onsemi 0:098463de4c5d 204 // Slave
group-onsemi 0:098463de4c5d 205 // Configure SS as low active.
group-onsemi 0:098463de4c5d 206 spi_base->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
group-onsemi 0:098463de4c5d 207 }
group-onsemi 0:098463de4c5d 208
group-onsemi 0:098463de4c5d 209 // NOTE: M451's SPI_Open() will enable SPI transfer (SPI_CTL_SPIEN_Msk). This will violate judgement of spi_active(). Disable it.
group-onsemi 0:098463de4c5d 210 SPI_DISABLE(spi_base);
group-onsemi 0:098463de4c5d 211 }
group-onsemi 0:098463de4c5d 212
group-onsemi 0:098463de4c5d 213 void spi_frequency(spi_t *obj, int hz)
group-onsemi 0:098463de4c5d 214 {
group-onsemi 0:098463de4c5d 215 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 216
group-onsemi 0:098463de4c5d 217 while (SPI_IS_BUSY(spi_base));
group-onsemi 0:098463de4c5d 218 SPI_DISABLE(spi_base);
group-onsemi 0:098463de4c5d 219
group-onsemi 0:098463de4c5d 220 SPI_SetBusClock((SPI_T *) NU_MODBASE(obj->spi.spi), hz);
group-onsemi 0:098463de4c5d 221 }
group-onsemi 0:098463de4c5d 222
group-onsemi 0:098463de4c5d 223
group-onsemi 0:098463de4c5d 224 int spi_master_write(spi_t *obj, int value)
group-onsemi 0:098463de4c5d 225 {
group-onsemi 0:098463de4c5d 226 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 227
group-onsemi 0:098463de4c5d 228 // NOTE: Data in receive FIFO can be read out via ICE.
group-onsemi 0:098463de4c5d 229 SPI_ENABLE(spi_base);
group-onsemi 0:098463de4c5d 230
group-onsemi 0:098463de4c5d 231 // Wait for tx buffer empty
group-onsemi 0:098463de4c5d 232 while(! spi_writeable(obj));
group-onsemi 0:098463de4c5d 233 SPI_WRITE_TX(spi_base, value);
group-onsemi 0:098463de4c5d 234
group-onsemi 0:098463de4c5d 235 // Wait for rx buffer full
group-onsemi 0:098463de4c5d 236 while (! spi_readable(obj));
group-onsemi 0:098463de4c5d 237 int value2 = SPI_READ_RX(spi_base);
group-onsemi 0:098463de4c5d 238
group-onsemi 0:098463de4c5d 239 SPI_DISABLE(spi_base);
group-onsemi 0:098463de4c5d 240
group-onsemi 0:098463de4c5d 241 return value2;
group-onsemi 0:098463de4c5d 242 }
group-onsemi 0:098463de4c5d 243
group-onsemi 0:098463de4c5d 244 #if DEVICE_SPISLAVE
group-onsemi 0:098463de4c5d 245 int spi_slave_receive(spi_t *obj)
group-onsemi 0:098463de4c5d 246 {
group-onsemi 0:098463de4c5d 247 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 248
group-onsemi 0:098463de4c5d 249 SPI_ENABLE(spi_base);
group-onsemi 0:098463de4c5d 250
group-onsemi 0:098463de4c5d 251 return spi_readable(obj);
group-onsemi 0:098463de4c5d 252 };
group-onsemi 0:098463de4c5d 253
group-onsemi 0:098463de4c5d 254 int spi_slave_read(spi_t *obj)
group-onsemi 0:098463de4c5d 255 {
group-onsemi 0:098463de4c5d 256 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 257
group-onsemi 0:098463de4c5d 258 SPI_ENABLE(spi_base);
group-onsemi 0:098463de4c5d 259
group-onsemi 0:098463de4c5d 260 // Wait for rx buffer full
group-onsemi 0:098463de4c5d 261 while (! spi_readable(obj));
group-onsemi 0:098463de4c5d 262 int value = SPI_READ_RX(spi_base);
group-onsemi 0:098463de4c5d 263 return value;
group-onsemi 0:098463de4c5d 264 }
group-onsemi 0:098463de4c5d 265
group-onsemi 0:098463de4c5d 266 void spi_slave_write(spi_t *obj, int value)
group-onsemi 0:098463de4c5d 267 {
group-onsemi 0:098463de4c5d 268 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 269
group-onsemi 0:098463de4c5d 270 SPI_ENABLE(spi_base);
group-onsemi 0:098463de4c5d 271
group-onsemi 0:098463de4c5d 272 // Wait for tx buffer empty
group-onsemi 0:098463de4c5d 273 while(! spi_writeable(obj));
group-onsemi 0:098463de4c5d 274 SPI_WRITE_TX(spi_base, value);
group-onsemi 0:098463de4c5d 275 }
group-onsemi 0:098463de4c5d 276 #endif
group-onsemi 0:098463de4c5d 277
group-onsemi 0:098463de4c5d 278 #if DEVICE_SPI_ASYNCH
group-onsemi 0:098463de4c5d 279 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
group-onsemi 0:098463de4c5d 280 {
group-onsemi 0:098463de4c5d 281 //MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
group-onsemi 0:098463de4c5d 282 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 283 SPI_SET_DATA_WIDTH(spi_base, bit_width);
group-onsemi 0:098463de4c5d 284
group-onsemi 0:098463de4c5d 285 obj->spi.dma_usage = hint;
group-onsemi 0:098463de4c5d 286 spi_check_dma_usage(&obj->spi.dma_usage, &obj->spi.dma_chn_id_tx, &obj->spi.dma_chn_id_rx);
group-onsemi 0:098463de4c5d 287 uint32_t data_width = spi_get_data_width(obj);
group-onsemi 0:098463de4c5d 288 // Conditions to go DMA way:
group-onsemi 0:098463de4c5d 289 // (1) No DMA support for non-8 multiple data width.
group-onsemi 0:098463de4c5d 290 // (2) tx length >= rx length. Otherwise, as tx DMA is done, no bus activity for remaining rx.
group-onsemi 0:098463de4c5d 291 if ((data_width % 8) ||
group-onsemi 0:098463de4c5d 292 (tx_length < rx_length)) {
group-onsemi 0:098463de4c5d 293 obj->spi.dma_usage = DMA_USAGE_NEVER;
group-onsemi 0:098463de4c5d 294 dma_channel_free(obj->spi.dma_chn_id_tx);
group-onsemi 0:098463de4c5d 295 obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
group-onsemi 0:098463de4c5d 296 dma_channel_free(obj->spi.dma_chn_id_rx);
group-onsemi 0:098463de4c5d 297 obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
group-onsemi 0:098463de4c5d 298 }
group-onsemi 0:098463de4c5d 299
group-onsemi 0:098463de4c5d 300 // SPI IRQ is necessary for both interrupt way and DMA way
group-onsemi 0:098463de4c5d 301 spi_enable_event(obj, event, 1);
group-onsemi 0:098463de4c5d 302 spi_buffer_set(obj, tx, tx_length, rx, rx_length);
group-onsemi 0:098463de4c5d 303
group-onsemi 0:098463de4c5d 304 SPI_ENABLE(spi_base);
group-onsemi 0:098463de4c5d 305
group-onsemi 0:098463de4c5d 306 if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
group-onsemi 0:098463de4c5d 307 // Interrupt way
group-onsemi 0:098463de4c5d 308 spi_master_write_asynch(obj, NU_SPI_FIFO_DEPTH / 2);
group-onsemi 0:098463de4c5d 309 spi_enable_vector_interrupt(obj, handler, 1);
group-onsemi 0:098463de4c5d 310 spi_master_enable_interrupt(obj, 1);
group-onsemi 0:098463de4c5d 311 } else {
group-onsemi 0:098463de4c5d 312 // DMA way
group-onsemi 0:098463de4c5d 313 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
group-onsemi 0:098463de4c5d 314 MBED_ASSERT(modinit != NULL);
group-onsemi 0:098463de4c5d 315 MBED_ASSERT(modinit->modname == obj->spi.spi);
group-onsemi 0:098463de4c5d 316
group-onsemi 0:098463de4c5d 317 // Configure tx DMA
group-onsemi 0:098463de4c5d 318 PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel
group-onsemi 0:098463de4c5d 319 PDMA_SetTransferMode(obj->spi.dma_chn_id_tx,
group-onsemi 0:098463de4c5d 320 ((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
group-onsemi 0:098463de4c5d 321 0, // Scatter-gather disabled
group-onsemi 0:098463de4c5d 322 0); // Scatter-gather descriptor address
group-onsemi 0:098463de4c5d 323 PDMA_SetTransferCnt(obj->spi.dma_chn_id_tx,
group-onsemi 0:098463de4c5d 324 (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
group-onsemi 0:098463de4c5d 325 tx_length);
group-onsemi 0:098463de4c5d 326 PDMA_SetTransferAddr(obj->spi.dma_chn_id_tx,
group-onsemi 0:098463de4c5d 327 (uint32_t) tx, // NOTE:
group-onsemi 0:098463de4c5d 328 // NUC472: End of source address
group-onsemi 0:098463de4c5d 329 // M451: Start of source address
group-onsemi 0:098463de4c5d 330 PDMA_SAR_INC, // Source address incremental
group-onsemi 0:098463de4c5d 331 (uint32_t) &spi_base->TX, // Destination address
group-onsemi 0:098463de4c5d 332 PDMA_DAR_FIX); // Destination address fixed
group-onsemi 0:098463de4c5d 333 PDMA_SetBurstType(obj->spi.dma_chn_id_tx,
group-onsemi 0:098463de4c5d 334 PDMA_REQ_SINGLE, // Single mode
group-onsemi 0:098463de4c5d 335 0); // Burst size
group-onsemi 0:098463de4c5d 336 PDMA_EnableInt(obj->spi.dma_chn_id_tx,
group-onsemi 0:098463de4c5d 337 PDMA_INT_TRANS_DONE); // Interrupt type
group-onsemi 0:098463de4c5d 338 // Register DMA event handler
group-onsemi 0:098463de4c5d 339 dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
group-onsemi 0:098463de4c5d 340
group-onsemi 0:098463de4c5d 341 // Configure rx DMA
group-onsemi 0:098463de4c5d 342 PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel
group-onsemi 0:098463de4c5d 343 PDMA_SetTransferMode(obj->spi.dma_chn_id_rx,
group-onsemi 0:098463de4c5d 344 ((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
group-onsemi 0:098463de4c5d 345 0, // Scatter-gather disabled
group-onsemi 0:098463de4c5d 346 0); // Scatter-gather descriptor address
group-onsemi 0:098463de4c5d 347 PDMA_SetTransferCnt(obj->spi.dma_chn_id_rx,
group-onsemi 0:098463de4c5d 348 (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
group-onsemi 0:098463de4c5d 349 rx_length);
group-onsemi 0:098463de4c5d 350 PDMA_SetTransferAddr(obj->spi.dma_chn_id_rx,
group-onsemi 0:098463de4c5d 351 (uint32_t) &spi_base->RX, // Source address
group-onsemi 0:098463de4c5d 352 PDMA_SAR_FIX, // Source address fixed
group-onsemi 0:098463de4c5d 353 (uint32_t) rx, // NOTE:
group-onsemi 0:098463de4c5d 354 // NUC472: End of destination address
group-onsemi 0:098463de4c5d 355 // M451: Start of destination address
group-onsemi 0:098463de4c5d 356 PDMA_DAR_INC); // Destination address incremental
group-onsemi 0:098463de4c5d 357 PDMA_SetBurstType(obj->spi.dma_chn_id_rx,
group-onsemi 0:098463de4c5d 358 PDMA_REQ_SINGLE, // Single mode
group-onsemi 0:098463de4c5d 359 0); // Burst size
group-onsemi 0:098463de4c5d 360 PDMA_EnableInt(obj->spi.dma_chn_id_rx,
group-onsemi 0:098463de4c5d 361 PDMA_INT_TRANS_DONE); // Interrupt type
group-onsemi 0:098463de4c5d 362 // Register DMA event handler
group-onsemi 0:098463de4c5d 363 dma_set_handler(obj->spi.dma_chn_id_rx, (uint32_t) spi_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
group-onsemi 0:098463de4c5d 364
group-onsemi 0:098463de4c5d 365 // Start tx/rx DMA transfer
group-onsemi 0:098463de4c5d 366 spi_enable_vector_interrupt(obj, handler, 1);
group-onsemi 0:098463de4c5d 367 // NOTE: It is safer to start rx DMA first and then tx DMA. Otherwise, receive FIFO is subject to overflow by tx DMA.
group-onsemi 0:098463de4c5d 368 SPI_TRIGGER_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
group-onsemi 0:098463de4c5d 369 SPI_TRIGGER_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
group-onsemi 0:098463de4c5d 370 spi_master_enable_interrupt(obj, 1);
group-onsemi 0:098463de4c5d 371 }
group-onsemi 0:098463de4c5d 372 }
group-onsemi 0:098463de4c5d 373
group-onsemi 0:098463de4c5d 374 /**
group-onsemi 0:098463de4c5d 375 * Abort an SPI transfer
group-onsemi 0:098463de4c5d 376 * This is a helper function for event handling. When any of the events listed occurs, the HAL will abort any ongoing
group-onsemi 0:098463de4c5d 377 * transfers
group-onsemi 0:098463de4c5d 378 * @param[in] obj The SPI peripheral to stop
group-onsemi 0:098463de4c5d 379 */
group-onsemi 0:098463de4c5d 380 void spi_abort_asynch(spi_t *obj)
group-onsemi 0:098463de4c5d 381 {
group-onsemi 0:098463de4c5d 382 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 383
group-onsemi 0:098463de4c5d 384 if (obj->spi.dma_usage != DMA_USAGE_NEVER) {
group-onsemi 0:098463de4c5d 385 // Receive FIFO Overrun in case of tx length > rx length on DMA way
group-onsemi 0:098463de4c5d 386 if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
group-onsemi 0:098463de4c5d 387 spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
group-onsemi 0:098463de4c5d 388 }
group-onsemi 0:098463de4c5d 389
group-onsemi 0:098463de4c5d 390 if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
group-onsemi 0:098463de4c5d 391 PDMA_DisableInt(obj->spi.dma_chn_id_tx, 0);
group-onsemi 0:098463de4c5d 392 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
group-onsemi 0:098463de4c5d 393 //PDMA_STOP(obj->spi.dma_chn_id_tx);
group-onsemi 0:098463de4c5d 394 PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx);
group-onsemi 0:098463de4c5d 395 }
group-onsemi 0:098463de4c5d 396 SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
group-onsemi 0:098463de4c5d 397
group-onsemi 0:098463de4c5d 398 if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
group-onsemi 0:098463de4c5d 399 PDMA_DisableInt(obj->spi.dma_chn_id_rx, 0);
group-onsemi 0:098463de4c5d 400 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
group-onsemi 0:098463de4c5d 401 //PDMA_STOP(obj->spi.dma_chn_id_rx);
group-onsemi 0:098463de4c5d 402 PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx);
group-onsemi 0:098463de4c5d 403 }
group-onsemi 0:098463de4c5d 404 SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
group-onsemi 0:098463de4c5d 405 }
group-onsemi 0:098463de4c5d 406
group-onsemi 0:098463de4c5d 407 // Necessary for both interrupt way and DMA way
group-onsemi 0:098463de4c5d 408 spi_enable_vector_interrupt(obj, 0, 0);
group-onsemi 0:098463de4c5d 409 spi_master_enable_interrupt(obj, 0);
group-onsemi 0:098463de4c5d 410
group-onsemi 0:098463de4c5d 411 // FIXME: SPI H/W may get out of state without the busy check.
group-onsemi 0:098463de4c5d 412 while (SPI_IS_BUSY(spi_base));
group-onsemi 0:098463de4c5d 413 SPI_DISABLE(spi_base);
group-onsemi 0:098463de4c5d 414
group-onsemi 0:098463de4c5d 415 SPI_ClearRxFIFO(spi_base);
group-onsemi 0:098463de4c5d 416 SPI_ClearTxFIFO(spi_base);
group-onsemi 0:098463de4c5d 417 }
group-onsemi 0:098463de4c5d 418
group-onsemi 0:098463de4c5d 419 /**
group-onsemi 0:098463de4c5d 420 * Handle the SPI interrupt
group-onsemi 0:098463de4c5d 421 * Read frames until the RX FIFO is empty. Write at most as many frames as were read. This way,
group-onsemi 0:098463de4c5d 422 * it is unlikely that the RX FIFO will overflow.
group-onsemi 0:098463de4c5d 423 * @param[in] obj The SPI peripheral that generated the interrupt
group-onsemi 0:098463de4c5d 424 * @return
group-onsemi 0:098463de4c5d 425 */
group-onsemi 0:098463de4c5d 426 uint32_t spi_irq_handler_asynch(spi_t *obj)
group-onsemi 0:098463de4c5d 427 {
group-onsemi 0:098463de4c5d 428 // Check for SPI events
group-onsemi 0:098463de4c5d 429 uint32_t event = spi_event_check(obj);
group-onsemi 0:098463de4c5d 430 if (event) {
group-onsemi 0:098463de4c5d 431 spi_abort_asynch(obj);
group-onsemi 0:098463de4c5d 432 }
group-onsemi 0:098463de4c5d 433
group-onsemi 0:098463de4c5d 434 return (obj->spi.event & event) | ((event & SPI_EVENT_COMPLETE) ? SPI_EVENT_INTERNAL_TRANSFER_COMPLETE : 0);
group-onsemi 0:098463de4c5d 435 }
group-onsemi 0:098463de4c5d 436
group-onsemi 0:098463de4c5d 437 uint8_t spi_active(spi_t *obj)
group-onsemi 0:098463de4c5d 438 {
group-onsemi 0:098463de4c5d 439 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 440 // FIXME
group-onsemi 0:098463de4c5d 441 /*
group-onsemi 0:098463de4c5d 442 if ((obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length)
group-onsemi 0:098463de4c5d 443 || (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) ){
group-onsemi 0:098463de4c5d 444 return 1;
group-onsemi 0:098463de4c5d 445 } else {
group-onsemi 0:098463de4c5d 446 // interrupts are disabled, all transaction have been completed
group-onsemi 0:098463de4c5d 447 // TODO: checking rx fifo, it reports data eventhough RFDF is not set
group-onsemi 0:098463de4c5d 448 return DSPI_HAL_GetIntMode(obj->spi.address, kDspiRxFifoDrainRequest);
group-onsemi 0:098463de4c5d 449 }*/
group-onsemi 0:098463de4c5d 450
group-onsemi 0:098463de4c5d 451 //return SPI_IS_BUSY(spi_base);
group-onsemi 0:098463de4c5d 452 return (spi_base->CTL & SPI_CTL_SPIEN_Msk);
group-onsemi 0:098463de4c5d 453 }
group-onsemi 0:098463de4c5d 454
group-onsemi 0:098463de4c5d 455 int spi_allow_powerdown(void)
group-onsemi 0:098463de4c5d 456 {
group-onsemi 0:098463de4c5d 457 uint32_t modinit_mask = spi_modinit_mask;
group-onsemi 0:098463de4c5d 458 while (modinit_mask) {
group-onsemi 0:098463de4c5d 459 int spi_idx = nu_ctz(modinit_mask);
group-onsemi 0:098463de4c5d 460 const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx;
group-onsemi 0:098463de4c5d 461 if (modinit->modname != NC) {
group-onsemi 0:098463de4c5d 462 SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname);
group-onsemi 0:098463de4c5d 463 // Disallow entering power-down mode if SPI transfer is enabled.
group-onsemi 0:098463de4c5d 464 if (spi_base->CTL & SPI_CTL_SPIEN_Msk) {
group-onsemi 0:098463de4c5d 465 return 0;
group-onsemi 0:098463de4c5d 466 }
group-onsemi 0:098463de4c5d 467 }
group-onsemi 0:098463de4c5d 468 modinit_mask &= ~(1 << spi_idx);
group-onsemi 0:098463de4c5d 469 }
group-onsemi 0:098463de4c5d 470
group-onsemi 0:098463de4c5d 471 return 1;
group-onsemi 0:098463de4c5d 472 }
group-onsemi 0:098463de4c5d 473
group-onsemi 0:098463de4c5d 474 static int spi_writeable(spi_t * obj)
group-onsemi 0:098463de4c5d 475 {
group-onsemi 0:098463de4c5d 476 // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
group-onsemi 0:098463de4c5d 477 //return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)))) && (SPI_GET_RX_FIFO_COUNT(((SPI_T *) NU_MODBASE(obj->spi.spi))) < NU_SPI_FIFO_DEPTH);
group-onsemi 0:098463de4c5d 478 return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
group-onsemi 0:098463de4c5d 479 }
group-onsemi 0:098463de4c5d 480
group-onsemi 0:098463de4c5d 481 static int spi_readable(spi_t * obj)
group-onsemi 0:098463de4c5d 482 {
group-onsemi 0:098463de4c5d 483 return ! SPI_GET_RX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)));
group-onsemi 0:098463de4c5d 484 }
group-onsemi 0:098463de4c5d 485
group-onsemi 0:098463de4c5d 486 static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable)
group-onsemi 0:098463de4c5d 487 {
group-onsemi 0:098463de4c5d 488 obj->spi.event &= ~SPI_EVENT_ALL;
group-onsemi 0:098463de4c5d 489 obj->spi.event |= (event & SPI_EVENT_ALL);
group-onsemi 0:098463de4c5d 490 if (event & SPI_EVENT_RX_OVERFLOW) {
group-onsemi 0:098463de4c5d 491 SPI_EnableInt((SPI_T *) NU_MODBASE(obj->spi.spi), SPI_FIFO_RXOV_INT_MASK);
group-onsemi 0:098463de4c5d 492 }
group-onsemi 0:098463de4c5d 493 }
group-onsemi 0:098463de4c5d 494
group-onsemi 0:098463de4c5d 495 static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable)
group-onsemi 0:098463de4c5d 496 {
group-onsemi 0:098463de4c5d 497 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
group-onsemi 0:098463de4c5d 498 MBED_ASSERT(modinit != NULL);
group-onsemi 0:098463de4c5d 499 MBED_ASSERT(modinit->modname == obj->spi.spi);
group-onsemi 0:098463de4c5d 500
group-onsemi 0:098463de4c5d 501 if (enable) {
group-onsemi 0:098463de4c5d 502 NVIC_SetVector(modinit->irq_n, handler);
group-onsemi 0:098463de4c5d 503 NVIC_EnableIRQ(modinit->irq_n);
group-onsemi 0:098463de4c5d 504 }
group-onsemi 0:098463de4c5d 505 else {
group-onsemi 0:098463de4c5d 506 //NVIC_SetVector(modinit->irq_n, handler);
group-onsemi 0:098463de4c5d 507 NVIC_DisableIRQ(modinit->irq_n);
group-onsemi 0:098463de4c5d 508 }
group-onsemi 0:098463de4c5d 509 }
group-onsemi 0:098463de4c5d 510
group-onsemi 0:098463de4c5d 511 static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable)
group-onsemi 0:098463de4c5d 512 {
group-onsemi 0:098463de4c5d 513 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 514
group-onsemi 0:098463de4c5d 515 if (enable) {
group-onsemi 0:098463de4c5d 516 // For SPI0, it could be 0 ~ 7. For SPI1 and SPI2, it could be 0 ~ 3.
group-onsemi 0:098463de4c5d 517 if (spi_base == (SPI_T *) SPI0_BASE) {
group-onsemi 0:098463de4c5d 518 SPI_SetFIFO(spi_base, 4, 4);
group-onsemi 0:098463de4c5d 519 }
group-onsemi 0:098463de4c5d 520 else {
group-onsemi 0:098463de4c5d 521 SPI_SetFIFO(spi_base, 2, 2);
group-onsemi 0:098463de4c5d 522 }
group-onsemi 0:098463de4c5d 523 //SPI_SET_SUSPEND_CYCLE(spi_base, 4);
group-onsemi 0:098463de4c5d 524 // Enable tx/rx FIFO threshold interrupt
group-onsemi 0:098463de4c5d 525 SPI_EnableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
group-onsemi 0:098463de4c5d 526 }
group-onsemi 0:098463de4c5d 527 else {
group-onsemi 0:098463de4c5d 528 SPI_DisableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
group-onsemi 0:098463de4c5d 529 }
group-onsemi 0:098463de4c5d 530 }
group-onsemi 0:098463de4c5d 531
group-onsemi 0:098463de4c5d 532 static uint32_t spi_event_check(spi_t *obj)
group-onsemi 0:098463de4c5d 533 {
group-onsemi 0:098463de4c5d 534 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 535 uint32_t event = 0;
group-onsemi 0:098463de4c5d 536
group-onsemi 0:098463de4c5d 537 if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
group-onsemi 0:098463de4c5d 538 uint32_t n_rec = spi_master_read_asynch(obj);
group-onsemi 0:098463de4c5d 539 spi_master_write_asynch(obj, n_rec);
group-onsemi 0:098463de4c5d 540 }
group-onsemi 0:098463de4c5d 541
group-onsemi 0:098463de4c5d 542 if (spi_is_tx_complete(obj) && spi_is_rx_complete(obj)) {
group-onsemi 0:098463de4c5d 543 event |= SPI_EVENT_COMPLETE;
group-onsemi 0:098463de4c5d 544 }
group-onsemi 0:098463de4c5d 545
group-onsemi 0:098463de4c5d 546 // Receive FIFO Overrun
group-onsemi 0:098463de4c5d 547 if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
group-onsemi 0:098463de4c5d 548 spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
group-onsemi 0:098463de4c5d 549 // In case of tx length > rx length on DMA way
group-onsemi 0:098463de4c5d 550 if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
group-onsemi 0:098463de4c5d 551 event |= SPI_EVENT_RX_OVERFLOW;
group-onsemi 0:098463de4c5d 552 }
group-onsemi 0:098463de4c5d 553 }
group-onsemi 0:098463de4c5d 554
group-onsemi 0:098463de4c5d 555 // Receive Time-Out
group-onsemi 0:098463de4c5d 556 if (spi_base->STATUS & SPI_STATUS_RXTOIF_Msk) {
group-onsemi 0:098463de4c5d 557 spi_base->STATUS = SPI_STATUS_RXTOIF_Msk;
group-onsemi 0:098463de4c5d 558 //event |= SPI_EVENT_ERROR;
group-onsemi 0:098463de4c5d 559 }
group-onsemi 0:098463de4c5d 560 // Transmit FIFO Under-Run
group-onsemi 0:098463de4c5d 561 if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) {
group-onsemi 0:098463de4c5d 562 spi_base->STATUS = SPI_STATUS_TXUFIF_Msk;
group-onsemi 0:098463de4c5d 563 event |= SPI_EVENT_ERROR;
group-onsemi 0:098463de4c5d 564 }
group-onsemi 0:098463de4c5d 565
group-onsemi 0:098463de4c5d 566 return event;
group-onsemi 0:098463de4c5d 567 }
group-onsemi 0:098463de4c5d 568
group-onsemi 0:098463de4c5d 569 /**
group-onsemi 0:098463de4c5d 570 * Send words from the SPI TX buffer until the send limit is reached or the TX FIFO is full
group-onsemi 0:098463de4c5d 571 * tx_limit is provided to ensure that the number of SPI frames (words) in flight can be managed.
group-onsemi 0:098463de4c5d 572 * @param[in] obj The SPI object on which to operate
group-onsemi 0:098463de4c5d 573 * @param[in] tx_limit The maximum number of words to send
group-onsemi 0:098463de4c5d 574 * @return The number of SPI words that have been transfered
group-onsemi 0:098463de4c5d 575 */
group-onsemi 0:098463de4c5d 576 static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
group-onsemi 0:098463de4c5d 577 {
group-onsemi 0:098463de4c5d 578 uint32_t n_words = 0;
group-onsemi 0:098463de4c5d 579 uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
group-onsemi 0:098463de4c5d 580 uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
group-onsemi 0:098463de4c5d 581 uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn);
group-onsemi 0:098463de4c5d 582 max_tx = NU_MIN(max_tx, tx_limit);
group-onsemi 0:098463de4c5d 583 uint8_t data_width = spi_get_data_width(obj);
group-onsemi 0:098463de4c5d 584 uint8_t bytes_per_word = (data_width + 7) / 8;
group-onsemi 0:098463de4c5d 585 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
group-onsemi 0:098463de4c5d 586 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 587
group-onsemi 0:098463de4c5d 588 while ((n_words < max_tx) && spi_writeable(obj)) {
group-onsemi 0:098463de4c5d 589 if (spi_is_tx_complete(obj)) {
group-onsemi 0:098463de4c5d 590 // Transmit dummy as transmit buffer is empty
group-onsemi 0:098463de4c5d 591 SPI_WRITE_TX(spi_base, 0);
group-onsemi 0:098463de4c5d 592 }
group-onsemi 0:098463de4c5d 593 else {
group-onsemi 0:098463de4c5d 594 switch (bytes_per_word) {
group-onsemi 0:098463de4c5d 595 case 4:
group-onsemi 0:098463de4c5d 596 SPI_WRITE_TX(spi_base, nu_get32_le(tx));
group-onsemi 0:098463de4c5d 597 tx += 4;
group-onsemi 0:098463de4c5d 598 break;
group-onsemi 0:098463de4c5d 599 case 2:
group-onsemi 0:098463de4c5d 600 SPI_WRITE_TX(spi_base, nu_get16_le(tx));
group-onsemi 0:098463de4c5d 601 tx += 2;
group-onsemi 0:098463de4c5d 602 break;
group-onsemi 0:098463de4c5d 603 case 1:
group-onsemi 0:098463de4c5d 604 SPI_WRITE_TX(spi_base, *((uint8_t *) tx));
group-onsemi 0:098463de4c5d 605 tx += 1;
group-onsemi 0:098463de4c5d 606 break;
group-onsemi 0:098463de4c5d 607 }
group-onsemi 0:098463de4c5d 608
group-onsemi 0:098463de4c5d 609 obj->tx_buff.pos ++;
group-onsemi 0:098463de4c5d 610 }
group-onsemi 0:098463de4c5d 611 n_words ++;
group-onsemi 0:098463de4c5d 612 }
group-onsemi 0:098463de4c5d 613
group-onsemi 0:098463de4c5d 614 //Return the number of words that have been sent
group-onsemi 0:098463de4c5d 615 return n_words;
group-onsemi 0:098463de4c5d 616 }
group-onsemi 0:098463de4c5d 617
group-onsemi 0:098463de4c5d 618 /**
group-onsemi 0:098463de4c5d 619 * Read SPI words out of the RX FIFO
group-onsemi 0:098463de4c5d 620 * Continues reading words out of the RX FIFO until the following condition is met:
group-onsemi 0:098463de4c5d 621 * o There are no more words in the FIFO
group-onsemi 0:098463de4c5d 622 * OR BOTH OF:
group-onsemi 0:098463de4c5d 623 * o At least as many words as the TX buffer have been received
group-onsemi 0:098463de4c5d 624 * o At least as many words as the RX buffer have been received
group-onsemi 0:098463de4c5d 625 * This way, RX overflows are not generated when the TX buffer size exceeds the RX buffer size
group-onsemi 0:098463de4c5d 626 * @param[in] obj The SPI object on which to operate
group-onsemi 0:098463de4c5d 627 * @return Returns the number of words extracted from the RX FIFO
group-onsemi 0:098463de4c5d 628 */
group-onsemi 0:098463de4c5d 629 static uint32_t spi_master_read_asynch(spi_t *obj)
group-onsemi 0:098463de4c5d 630 {
group-onsemi 0:098463de4c5d 631 uint32_t n_words = 0;
group-onsemi 0:098463de4c5d 632 uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
group-onsemi 0:098463de4c5d 633 uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
group-onsemi 0:098463de4c5d 634 uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn);
group-onsemi 0:098463de4c5d 635 uint8_t data_width = spi_get_data_width(obj);
group-onsemi 0:098463de4c5d 636 uint8_t bytes_per_word = (data_width + 7) / 8;
group-onsemi 0:098463de4c5d 637 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
group-onsemi 0:098463de4c5d 638 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 639
group-onsemi 0:098463de4c5d 640 while ((n_words < max_rx) && spi_readable(obj)) {
group-onsemi 0:098463de4c5d 641 if (spi_is_rx_complete(obj)) {
group-onsemi 0:098463de4c5d 642 // Disregard as receive buffer is full
group-onsemi 0:098463de4c5d 643 SPI_READ_RX(spi_base);
group-onsemi 0:098463de4c5d 644 }
group-onsemi 0:098463de4c5d 645 else {
group-onsemi 0:098463de4c5d 646 switch (bytes_per_word) {
group-onsemi 0:098463de4c5d 647 case 4: {
group-onsemi 0:098463de4c5d 648 uint32_t val = SPI_READ_RX(spi_base);
group-onsemi 0:098463de4c5d 649 nu_set32_le(rx, val);
group-onsemi 0:098463de4c5d 650 rx += 4;
group-onsemi 0:098463de4c5d 651 break;
group-onsemi 0:098463de4c5d 652 }
group-onsemi 0:098463de4c5d 653 case 2: {
group-onsemi 0:098463de4c5d 654 uint16_t val = SPI_READ_RX(spi_base);
group-onsemi 0:098463de4c5d 655 nu_set16_le(rx, val);
group-onsemi 0:098463de4c5d 656 rx += 2;
group-onsemi 0:098463de4c5d 657 break;
group-onsemi 0:098463de4c5d 658 }
group-onsemi 0:098463de4c5d 659 case 1:
group-onsemi 0:098463de4c5d 660 *rx ++ = SPI_READ_RX(spi_base);
group-onsemi 0:098463de4c5d 661 break;
group-onsemi 0:098463de4c5d 662 }
group-onsemi 0:098463de4c5d 663
group-onsemi 0:098463de4c5d 664 obj->rx_buff.pos ++;
group-onsemi 0:098463de4c5d 665 }
group-onsemi 0:098463de4c5d 666 n_words ++;
group-onsemi 0:098463de4c5d 667 }
group-onsemi 0:098463de4c5d 668
group-onsemi 0:098463de4c5d 669 // Return the number of words received
group-onsemi 0:098463de4c5d 670 return n_words;
group-onsemi 0:098463de4c5d 671 }
group-onsemi 0:098463de4c5d 672
group-onsemi 0:098463de4c5d 673 static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
group-onsemi 0:098463de4c5d 674 {
group-onsemi 0:098463de4c5d 675 obj->tx_buff.buffer = (void *) tx;
group-onsemi 0:098463de4c5d 676 obj->tx_buff.length = tx_length;
group-onsemi 0:098463de4c5d 677 obj->tx_buff.pos = 0;
group-onsemi 0:098463de4c5d 678 obj->tx_buff.width = spi_get_data_width(obj);
group-onsemi 0:098463de4c5d 679 obj->rx_buff.buffer = rx;
group-onsemi 0:098463de4c5d 680 obj->rx_buff.length = rx_length;
group-onsemi 0:098463de4c5d 681 obj->rx_buff.pos = 0;
group-onsemi 0:098463de4c5d 682 obj->rx_buff.width = spi_get_data_width(obj);
group-onsemi 0:098463de4c5d 683 }
group-onsemi 0:098463de4c5d 684
group-onsemi 0:098463de4c5d 685 static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx)
group-onsemi 0:098463de4c5d 686 {
group-onsemi 0:098463de4c5d 687 if (*dma_usage != DMA_USAGE_NEVER) {
group-onsemi 0:098463de4c5d 688 if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS) {
group-onsemi 0:098463de4c5d 689 *dma_ch_tx = dma_channel_allocate(DMA_CAP_NONE);
group-onsemi 0:098463de4c5d 690 }
group-onsemi 0:098463de4c5d 691 if (*dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
group-onsemi 0:098463de4c5d 692 *dma_ch_rx = dma_channel_allocate(DMA_CAP_NONE);
group-onsemi 0:098463de4c5d 693 }
group-onsemi 0:098463de4c5d 694
group-onsemi 0:098463de4c5d 695 if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS || *dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
group-onsemi 0:098463de4c5d 696 *dma_usage = DMA_USAGE_NEVER;
group-onsemi 0:098463de4c5d 697 }
group-onsemi 0:098463de4c5d 698 }
group-onsemi 0:098463de4c5d 699
group-onsemi 0:098463de4c5d 700 if (*dma_usage == DMA_USAGE_NEVER) {
group-onsemi 0:098463de4c5d 701 dma_channel_free(*dma_ch_tx);
group-onsemi 0:098463de4c5d 702 *dma_ch_tx = DMA_ERROR_OUT_OF_CHANNELS;
group-onsemi 0:098463de4c5d 703 dma_channel_free(*dma_ch_rx);
group-onsemi 0:098463de4c5d 704 *dma_ch_rx = DMA_ERROR_OUT_OF_CHANNELS;
group-onsemi 0:098463de4c5d 705 }
group-onsemi 0:098463de4c5d 706 }
group-onsemi 0:098463de4c5d 707
group-onsemi 0:098463de4c5d 708 static uint8_t spi_get_data_width(spi_t *obj)
group-onsemi 0:098463de4c5d 709 {
group-onsemi 0:098463de4c5d 710 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
group-onsemi 0:098463de4c5d 711
group-onsemi 0:098463de4c5d 712 uint32_t data_width = ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos);
group-onsemi 0:098463de4c5d 713 if (data_width == 0) {
group-onsemi 0:098463de4c5d 714 data_width = 32;
group-onsemi 0:098463de4c5d 715 }
group-onsemi 0:098463de4c5d 716
group-onsemi 0:098463de4c5d 717 return data_width;
group-onsemi 0:098463de4c5d 718 }
group-onsemi 0:098463de4c5d 719
group-onsemi 0:098463de4c5d 720 static int spi_is_tx_complete(spi_t *obj)
group-onsemi 0:098463de4c5d 721 {
group-onsemi 0:098463de4c5d 722 // ???: Exclude tx fifo empty check due to no such interrupt on DMA way
group-onsemi 0:098463de4c5d 723 return (obj->tx_buff.pos == obj->tx_buff.length);
group-onsemi 0:098463de4c5d 724 //return (obj->tx_buff.pos == obj->tx_buff.length && SPI_GET_TX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
group-onsemi 0:098463de4c5d 725 }
group-onsemi 0:098463de4c5d 726
group-onsemi 0:098463de4c5d 727 static int spi_is_rx_complete(spi_t *obj)
group-onsemi 0:098463de4c5d 728 {
group-onsemi 0:098463de4c5d 729 return (obj->rx_buff.pos == obj->rx_buff.length);
group-onsemi 0:098463de4c5d 730 }
group-onsemi 0:098463de4c5d 731
group-onsemi 0:098463de4c5d 732 static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma)
group-onsemi 0:098463de4c5d 733 {
group-onsemi 0:098463de4c5d 734 spi_t *obj = (spi_t *) id;
group-onsemi 0:098463de4c5d 735
group-onsemi 0:098463de4c5d 736 // FIXME: Pass this error to caller
group-onsemi 0:098463de4c5d 737 if (event_dma & DMA_EVENT_ABORT) {
group-onsemi 0:098463de4c5d 738 }
group-onsemi 0:098463de4c5d 739 // Expect SPI IRQ will catch this transfer done event
group-onsemi 0:098463de4c5d 740 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
group-onsemi 0:098463de4c5d 741 obj->tx_buff.pos = obj->tx_buff.length;
group-onsemi 0:098463de4c5d 742 }
group-onsemi 0:098463de4c5d 743 // FIXME: Pass this error to caller
group-onsemi 0:098463de4c5d 744 if (event_dma & DMA_EVENT_TIMEOUT) {
group-onsemi 0:098463de4c5d 745 }
group-onsemi 0:098463de4c5d 746
group-onsemi 0:098463de4c5d 747 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
group-onsemi 0:098463de4c5d 748 MBED_ASSERT(modinit != NULL);
group-onsemi 0:098463de4c5d 749 MBED_ASSERT(modinit->modname == obj->spi.spi);
group-onsemi 0:098463de4c5d 750
group-onsemi 0:098463de4c5d 751 void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
group-onsemi 0:098463de4c5d 752 vec();
group-onsemi 0:098463de4c5d 753 }
group-onsemi 0:098463de4c5d 754
group-onsemi 0:098463de4c5d 755 static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma)
group-onsemi 0:098463de4c5d 756 {
group-onsemi 0:098463de4c5d 757 spi_t *obj = (spi_t *) id;
group-onsemi 0:098463de4c5d 758
group-onsemi 0:098463de4c5d 759 // FIXME: Pass this error to caller
group-onsemi 0:098463de4c5d 760 if (event_dma & DMA_EVENT_ABORT) {
group-onsemi 0:098463de4c5d 761 }
group-onsemi 0:098463de4c5d 762 // Expect SPI IRQ will catch this transfer done event
group-onsemi 0:098463de4c5d 763 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
group-onsemi 0:098463de4c5d 764 obj->rx_buff.pos = obj->rx_buff.length;
group-onsemi 0:098463de4c5d 765 }
group-onsemi 0:098463de4c5d 766 // FIXME: Pass this error to caller
group-onsemi 0:098463de4c5d 767 if (event_dma & DMA_EVENT_TIMEOUT) {
group-onsemi 0:098463de4c5d 768 }
group-onsemi 0:098463de4c5d 769
group-onsemi 0:098463de4c5d 770 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
group-onsemi 0:098463de4c5d 771 MBED_ASSERT(modinit != NULL);
group-onsemi 0:098463de4c5d 772 MBED_ASSERT(modinit->modname == obj->spi.spi);
group-onsemi 0:098463de4c5d 773
group-onsemi 0:098463de4c5d 774 void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
group-onsemi 0:098463de4c5d 775 vec();
group-onsemi 0:098463de4c5d 776 }
group-onsemi 0:098463de4c5d 777
group-onsemi 0:098463de4c5d 778 #endif
group-onsemi 0:098463de4c5d 779
group-onsemi 0:098463de4c5d 780 #endif