ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32620/sleep.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #include "sleep_api.h"
group-onsemi 0:098463de4c5d 35 #include "pwrman_regs.h"
group-onsemi 0:098463de4c5d 36 #include "pwrseq_regs.h"
group-onsemi 0:098463de4c5d 37 #include "clkman_regs.h"
group-onsemi 0:098463de4c5d 38 #include "ioman_regs.h"
group-onsemi 0:098463de4c5d 39 #include "rtc_regs.h"
group-onsemi 0:098463de4c5d 40 #include "usb_regs.h"
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 #define REVISION_A3 2
group-onsemi 0:098463de4c5d 43 #define REVISION_A4 3
group-onsemi 0:098463de4c5d 44
group-onsemi 0:098463de4c5d 45 // USB state to be restored upon wakeup
group-onsemi 0:098463de4c5d 46 typedef struct {
group-onsemi 0:098463de4c5d 47 uint32_t dev_cn;
group-onsemi 0:098463de4c5d 48 uint32_t dev_inten;
group-onsemi 0:098463de4c5d 49 uint32_t ep_base;
group-onsemi 0:098463de4c5d 50 uint32_t ep[MXC_USB_NUM_EP];
group-onsemi 0:098463de4c5d 51 } usb_state_t;
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
group-onsemi 0:098463de4c5d 54 static int restore_usb;
group-onsemi 0:098463de4c5d 55 static usb_state_t usb_state;
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 void sleep(void)
group-onsemi 0:098463de4c5d 58 {
group-onsemi 0:098463de4c5d 59 // Normal sleep mode for ARM core
group-onsemi 0:098463de4c5d 60 SCB->SCR = 0;
group-onsemi 0:098463de4c5d 61
group-onsemi 0:098463de4c5d 62 __DSB();
group-onsemi 0:098463de4c5d 63 __WFI();
group-onsemi 0:098463de4c5d 64 }
group-onsemi 0:098463de4c5d 65
group-onsemi 0:098463de4c5d 66 static void usb_sleep(void)
group-onsemi 0:098463de4c5d 67 {
group-onsemi 0:098463de4c5d 68 int i;
group-onsemi 0:098463de4c5d 69
group-onsemi 0:098463de4c5d 70 if (MXC_USB->cn & MXC_F_USB_CN_USB_EN) {
group-onsemi 0:098463de4c5d 71 // The USB module will not survive Deep Sleep.
group-onsemi 0:098463de4c5d 72
group-onsemi 0:098463de4c5d 73 // Save the USB state to restore it upon wakeup
group-onsemi 0:098463de4c5d 74 usb_state.dev_cn = MXC_USB->dev_cn;
group-onsemi 0:098463de4c5d 75 usb_state.dev_inten = MXC_USB->dev_inten;
group-onsemi 0:098463de4c5d 76 usb_state.ep_base = MXC_USB->ep_base;
group-onsemi 0:098463de4c5d 77 for (i = 0; i < MXC_USB_NUM_EP; i++) {
group-onsemi 0:098463de4c5d 78 usb_state.ep[i] = MXC_USB->ep[i] & (MXC_F_USB_EP_DIR | MXC_F_USB_EP_BUF2 | MXC_F_USB_EP_INT_EN | MXC_F_USB_EP_NAK_EN);
group-onsemi 0:098463de4c5d 79 }
group-onsemi 0:098463de4c5d 80 restore_usb = 1;
group-onsemi 0:098463de4c5d 81
group-onsemi 0:098463de4c5d 82 // Shut down the USB module.
group-onsemi 0:098463de4c5d 83 MXC_USB->dev_inten = 0;
group-onsemi 0:098463de4c5d 84 MXC_USB->dev_cn = 0;
group-onsemi 0:098463de4c5d 85 MXC_USB->cn = 0;
group-onsemi 0:098463de4c5d 86 restore_usb = 1; // USB should be restored upon wakeup
group-onsemi 0:098463de4c5d 87 } else {
group-onsemi 0:098463de4c5d 88 restore_usb = 0;
group-onsemi 0:098463de4c5d 89 }
group-onsemi 0:098463de4c5d 90 }
group-onsemi 0:098463de4c5d 91
group-onsemi 0:098463de4c5d 92 // Restore the USB module state.
group-onsemi 0:098463de4c5d 93 static void usb_wakeup(void)
group-onsemi 0:098463de4c5d 94 {
group-onsemi 0:098463de4c5d 95 int i;
group-onsemi 0:098463de4c5d 96
group-onsemi 0:098463de4c5d 97 if (restore_usb) {
group-onsemi 0:098463de4c5d 98 MXC_USB->cn = MXC_F_USB_CN_USB_EN;
group-onsemi 0:098463de4c5d 99 MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST;
group-onsemi 0:098463de4c5d 100 MXC_USB->dev_cn = 0;
group-onsemi 0:098463de4c5d 101 for (i = 0; i < MXC_USB_NUM_EP; i++) {
group-onsemi 0:098463de4c5d 102 MXC_USB->ep[i] = usb_state.ep[i];
group-onsemi 0:098463de4c5d 103 }
group-onsemi 0:098463de4c5d 104 MXC_USB->ep_base = usb_state.ep_base;
group-onsemi 0:098463de4c5d 105 MXC_USB->dev_cn = usb_state.dev_cn;
group-onsemi 0:098463de4c5d 106 MXC_USB->dev_inten = usb_state.dev_inten;
group-onsemi 0:098463de4c5d 107 restore_usb = 0;
group-onsemi 0:098463de4c5d 108 }
group-onsemi 0:098463de4c5d 109 }
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 // Low-power stop mode
group-onsemi 0:098463de4c5d 112 void deepsleep(void)
group-onsemi 0:098463de4c5d 113 {
group-onsemi 0:098463de4c5d 114 unsigned int part_rev = MXC_PWRMAN->mask_id0 & MXC_F_PWRMAN_MASK_ID0_REVISION_ID;
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 // Deep Sleep is not working properly on Revisions A3 and earlier
group-onsemi 0:098463de4c5d 117 if (part_rev <= REVISION_A3) {
group-onsemi 0:098463de4c5d 118 sleep();
group-onsemi 0:098463de4c5d 119 return;
group-onsemi 0:098463de4c5d 120 }
group-onsemi 0:098463de4c5d 121
group-onsemi 0:098463de4c5d 122 // Wait for all STDIO characters to be sent. The UART clock will stop.
group-onsemi 0:098463de4c5d 123 while ((stdio_uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) ||
group-onsemi 0:098463de4c5d 124 !(stdio_uart->intfl & MXC_F_UART_INTFL_TX_DONE));
group-onsemi 0:098463de4c5d 125
group-onsemi 0:098463de4c5d 126 __disable_irq();
group-onsemi 0:098463de4c5d 127
group-onsemi 0:098463de4c5d 128 // Do not enter Deep Sleep if connected to VBUS
group-onsemi 0:098463de4c5d 129 if (MXC_USB->dev_intfl & MXC_F_USB_DEV_INTFL_VBUS_ST) {
group-onsemi 0:098463de4c5d 130 __enable_irq();
group-onsemi 0:098463de4c5d 131 sleep();
group-onsemi 0:098463de4c5d 132 return;
group-onsemi 0:098463de4c5d 133 }
group-onsemi 0:098463de4c5d 134
group-onsemi 0:098463de4c5d 135 // The USB module will not survive Deep Sleep. Shut it down.
group-onsemi 0:098463de4c5d 136 usb_sleep();
group-onsemi 0:098463de4c5d 137
group-onsemi 0:098463de4c5d 138 // Make sure RTC is not pending before sleeping, if its still synchronizing
group-onsemi 0:098463de4c5d 139 // we might not wake up.
group-onsemi 0:098463de4c5d 140 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142 // Clear any active GPIO Wake Up Events
group-onsemi 0:098463de4c5d 143 if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP) {
group-onsemi 0:098463de4c5d 144 // NOTE: These must be cleared before clearing IOWAKEUP
group-onsemi 0:098463de4c5d 145 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH;
group-onsemi 0:098463de4c5d 146 MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH;
group-onsemi 0:098463de4c5d 147
group-onsemi 0:098463de4c5d 148 MXC_PWRSEQ->flags |= MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP;
group-onsemi 0:098463de4c5d 149 }
group-onsemi 0:098463de4c5d 150
group-onsemi 0:098463de4c5d 151 // Set the LP1 select bit so CPU goes to LP1 during SLEEPDEEP
group-onsemi 0:098463de4c5d 152 if (part_rev == REVISION_A4) {
group-onsemi 0:098463de4c5d 153 MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_LP1; // A4 requires part to go to pseudo LP0
group-onsemi 0:098463de4c5d 154 } else {
group-onsemi 0:098463de4c5d 155 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1;
group-onsemi 0:098463de4c5d 156 }
group-onsemi 0:098463de4c5d 157
group-onsemi 0:098463de4c5d 158 // The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state)
group-onsemi 0:098463de4c5d 159 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
group-onsemi 0:098463de4c5d 160
group-onsemi 0:098463de4c5d 161 if (part_rev == REVISION_A4) {
group-onsemi 0:098463de4c5d 162 // WORKAROUND: Toggle SVM bits, which send extra clocks to the power sequencer to fix retention controller
group-onsemi 0:098463de4c5d 163 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD;
group-onsemi 0:098463de4c5d 164 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN);
group-onsemi 0:098463de4c5d 165 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN;
group-onsemi 0:098463de4c5d 166 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD;
group-onsemi 0:098463de4c5d 167 }
group-onsemi 0:098463de4c5d 168
group-onsemi 0:098463de4c5d 169 // Enable Retention controller
group-onsemi 0:098463de4c5d 170 MXC_PWRSEQ->retn_ctrl0 |= MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN;
group-onsemi 0:098463de4c5d 171
group-onsemi 0:098463de4c5d 172 // Clear the firstboot bit, which is generated by a POR event and locks out LPx modes
group-onsemi 0:098463de4c5d 173 MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT;
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175 // Freeze GPIO using MBUS so that it doesn't flail while digital core is asleep
group-onsemi 0:098463de4c5d 176 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
group-onsemi 0:098463de4c5d 177
group-onsemi 0:098463de4c5d 178 // Dummy read to make sure SSB writes are complete
group-onsemi 0:098463de4c5d 179 MXC_PWRSEQ->reg0 = MXC_PWRSEQ->reg0;
group-onsemi 0:098463de4c5d 180
group-onsemi 0:098463de4c5d 181 if (part_rev == REVISION_A4) {
group-onsemi 0:098463de4c5d 182 // Note: ARM deep-sleep requires a specific sequence to clear event latches,
group-onsemi 0:098463de4c5d 183 // otherwise the CPU will not enter sleep.
group-onsemi 0:098463de4c5d 184 __SEV();
group-onsemi 0:098463de4c5d 185 __WFE();
group-onsemi 0:098463de4c5d 186 __WFI();
group-onsemi 0:098463de4c5d 187 } else {
group-onsemi 0:098463de4c5d 188 // Note: ARM deep-sleep requires a specific sequence to clear event latches,
group-onsemi 0:098463de4c5d 189 // otherwise the CPU will not enter sleep.
group-onsemi 0:098463de4c5d 190 __SEV();
group-onsemi 0:098463de4c5d 191 __WFE();
group-onsemi 0:098463de4c5d 192 __WFE();
group-onsemi 0:098463de4c5d 193 }
group-onsemi 0:098463de4c5d 194
group-onsemi 0:098463de4c5d 195 // We'll wakeup here ...
group-onsemi 0:098463de4c5d 196
group-onsemi 0:098463de4c5d 197 // Unfreeze the GPIO by clearing MBUS_GATE
group-onsemi 0:098463de4c5d 198 MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
group-onsemi 0:098463de4c5d 199
group-onsemi 0:098463de4c5d 200 usb_wakeup();
group-onsemi 0:098463de4c5d 201
group-onsemi 0:098463de4c5d 202 // Clear power sequencer event flags (write-1-to-clear)
group-onsemi 0:098463de4c5d 203 // RTC and GPIO flags are cleared in their interrupts handlers
group-onsemi 0:098463de4c5d 204 // NOTE: We are ignoring all of these potential wake up types
group-onsemi 0:098463de4c5d 205 MXC_PWRSEQ->flags = (MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL |
group-onsemi 0:098463de4c5d 206 MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL |
group-onsemi 0:098463de4c5d 207 MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE |
group-onsemi 0:098463de4c5d 208 MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD |
group-onsemi 0:098463de4c5d 209 MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD |
group-onsemi 0:098463de4c5d 210 MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD |
group-onsemi 0:098463de4c5d 211 MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD |
group-onsemi 0:098463de4c5d 212 MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD |
group-onsemi 0:098463de4c5d 213 MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH |
group-onsemi 0:098463de4c5d 214 MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP |
group-onsemi 0:098463de4c5d 215 MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP |
group-onsemi 0:098463de4c5d 216 MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD);
group-onsemi 0:098463de4c5d 217
group-onsemi 0:098463de4c5d 218 __enable_irq();
group-onsemi 0:098463de4c5d 219 }