ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #include "rtc_api.h"
group-onsemi 0:098463de4c5d 35 #include "lp_ticker_api.h"
group-onsemi 0:098463de4c5d 36 #include "cmsis.h"
group-onsemi 0:098463de4c5d 37 #include "rtc_regs.h"
group-onsemi 0:098463de4c5d 38 #include "pwrseq_regs.h"
group-onsemi 0:098463de4c5d 39 #include "clkman_regs.h"
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 /**
group-onsemi 0:098463de4c5d 42 * Defines clock divider for 4096Hz input clock.
group-onsemi 0:098463de4c5d 43 */
group-onsemi 0:098463de4c5d 44 typedef enum {
group-onsemi 0:098463de4c5d 45 /** (4kHz) divide input clock by 2^0 = 1 */
group-onsemi 0:098463de4c5d 46 MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
group-onsemi 0:098463de4c5d 47 /** (2kHz) divide input clock by 2^1 = 2 */
group-onsemi 0:098463de4c5d 48 MXC_E_RTC_PRESCALE_DIV_2_1,
group-onsemi 0:098463de4c5d 49 /** (1kHz) divide input clock by 2^2 = 4 */
group-onsemi 0:098463de4c5d 50 MXC_E_RTC_PRESCALE_DIV_2_2,
group-onsemi 0:098463de4c5d 51 /** (512Hz) divide input clock by 2^3 = 8 */
group-onsemi 0:098463de4c5d 52 MXC_E_RTC_PRESCALE_DIV_2_3,
group-onsemi 0:098463de4c5d 53 /** (256Hz) divide input clock by 2^4 = 16 */
group-onsemi 0:098463de4c5d 54 MXC_E_RTC_PRESCALE_DIV_2_4,
group-onsemi 0:098463de4c5d 55 /** (128Hz) divide input clock by 2^5 = 32 */
group-onsemi 0:098463de4c5d 56 MXC_E_RTC_PRESCALE_DIV_2_5,
group-onsemi 0:098463de4c5d 57 /** (64Hz) divide input clock by 2^6 = 64 */
group-onsemi 0:098463de4c5d 58 MXC_E_RTC_PRESCALE_DIV_2_6,
group-onsemi 0:098463de4c5d 59 /** (32Hz) divide input clock by 2^7 = 128 */
group-onsemi 0:098463de4c5d 60 MXC_E_RTC_PRESCALE_DIV_2_7,
group-onsemi 0:098463de4c5d 61 /** (16Hz) divide input clock by 2^8 = 256 */
group-onsemi 0:098463de4c5d 62 MXC_E_RTC_PRESCALE_DIV_2_8,
group-onsemi 0:098463de4c5d 63 /** (8Hz) divide input clock by 2^9 = 512 */
group-onsemi 0:098463de4c5d 64 MXC_E_RTC_PRESCALE_DIV_2_9,
group-onsemi 0:098463de4c5d 65 /** (4Hz) divide input clock by 2^10 = 1024 */
group-onsemi 0:098463de4c5d 66 MXC_E_RTC_PRESCALE_DIV_2_10,
group-onsemi 0:098463de4c5d 67 /** (2Hz) divide input clock by 2^11 = 2048 */
group-onsemi 0:098463de4c5d 68 MXC_E_RTC_PRESCALE_DIV_2_11,
group-onsemi 0:098463de4c5d 69 /** (1Hz) divide input clock by 2^12 = 4096 */
group-onsemi 0:098463de4c5d 70 MXC_E_RTC_PRESCALE_DIV_2_12,
group-onsemi 0:098463de4c5d 71 } mxc_rtc_prescale_t;
group-onsemi 0:098463de4c5d 72
group-onsemi 0:098463de4c5d 73 #define PRESCALE_VAL MXC_E_RTC_PRESCALE_DIV_2_0 // Set the divider for the 4kHz clock
group-onsemi 0:098463de4c5d 74 #define SHIFT_AMT (MXC_E_RTC_PRESCALE_DIV_2_12 - PRESCALE_VAL)
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 #define WINDOW 1000
group-onsemi 0:098463de4c5d 77
group-onsemi 0:098463de4c5d 78 static int rtc_inited = 0;
group-onsemi 0:098463de4c5d 79 static volatile uint32_t overflow_cnt = 0;
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 static uint64_t rtc_read64(void);
group-onsemi 0:098463de4c5d 82
group-onsemi 0:098463de4c5d 83 //******************************************************************************
group-onsemi 0:098463de4c5d 84 static void overflow_handler(void)
group-onsemi 0:098463de4c5d 85 {
group-onsemi 0:098463de4c5d 86 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
group-onsemi 0:098463de4c5d 87 overflow_cnt++;
group-onsemi 0:098463de4c5d 88
group-onsemi 0:098463de4c5d 89 // Wait for pending transactions
group-onsemi 0:098463de4c5d 90 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
group-onsemi 0:098463de4c5d 91 }
group-onsemi 0:098463de4c5d 92
group-onsemi 0:098463de4c5d 93 //******************************************************************************
group-onsemi 0:098463de4c5d 94 void rtc_init(void)
group-onsemi 0:098463de4c5d 95 {
group-onsemi 0:098463de4c5d 96 if (rtc_inited) {
group-onsemi 0:098463de4c5d 97 return;
group-onsemi 0:098463de4c5d 98 }
group-onsemi 0:098463de4c5d 99 rtc_inited = 1;
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 overflow_cnt = 0;
group-onsemi 0:098463de4c5d 102
group-onsemi 0:098463de4c5d 103 // Enable the clock to the synchronizer
group-onsemi 0:098463de4c5d 104 MXC_CLKMAN->sys_clk_ctrl_1_sync = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
group-onsemi 0:098463de4c5d 105
group-onsemi 0:098463de4c5d 106 // Enable the clock to the RTC
group-onsemi 0:098463de4c5d 107 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109 // Prepare interrupt handlers
group-onsemi 0:098463de4c5d 110 NVIC_SetVector(RTC0_IRQn, (uint32_t)lp_ticker_irq_handler);
group-onsemi 0:098463de4c5d 111 NVIC_EnableIRQ(RTC0_IRQn);
group-onsemi 0:098463de4c5d 112 NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler);
group-onsemi 0:098463de4c5d 113 NVIC_EnableIRQ(RTC3_IRQn);
group-onsemi 0:098463de4c5d 114
group-onsemi 0:098463de4c5d 115 // Enable wakeup on RTC rollover
group-onsemi 0:098463de4c5d 116 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER;
group-onsemi 0:098463de4c5d 117
group-onsemi 0:098463de4c5d 118 /* RTC registers are only reset on a power cycle. Do not reconfigure the RTC
group-onsemi 0:098463de4c5d 119 * if it is already running.
group-onsemi 0:098463de4c5d 120 */
group-onsemi 0:098463de4c5d 121 if (!(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE)) {
group-onsemi 0:098463de4c5d 122 // Set the clock divider
group-onsemi 0:098463de4c5d 123 MXC_RTCTMR->prescale = PRESCALE_VAL;
group-onsemi 0:098463de4c5d 124
group-onsemi 0:098463de4c5d 125 // Enable the overflow interrupt
group-onsemi 0:098463de4c5d 126 MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW;
group-onsemi 0:098463de4c5d 127
group-onsemi 0:098463de4c5d 128 // Restart the timer from 0
group-onsemi 0:098463de4c5d 129 MXC_RTCTMR->timer = 0;
group-onsemi 0:098463de4c5d 130
group-onsemi 0:098463de4c5d 131 // Enable the RTC
group-onsemi 0:098463de4c5d 132 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;
group-onsemi 0:098463de4c5d 133 }
group-onsemi 0:098463de4c5d 134 }
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 //******************************************************************************
group-onsemi 0:098463de4c5d 137 void lp_ticker_init(void)
group-onsemi 0:098463de4c5d 138 {
group-onsemi 0:098463de4c5d 139 rtc_init();
group-onsemi 0:098463de4c5d 140 }
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142 //******************************************************************************
group-onsemi 0:098463de4c5d 143 void rtc_free(void)
group-onsemi 0:098463de4c5d 144 {
group-onsemi 0:098463de4c5d 145 if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) {
group-onsemi 0:098463de4c5d 146 // Clear and disable RTC
group-onsemi 0:098463de4c5d 147 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR;
group-onsemi 0:098463de4c5d 148 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE;
group-onsemi 0:098463de4c5d 149
group-onsemi 0:098463de4c5d 150 // Wait for pending transactions
group-onsemi 0:098463de4c5d 151 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
group-onsemi 0:098463de4c5d 152 }
group-onsemi 0:098463de4c5d 153
group-onsemi 0:098463de4c5d 154 // Disable the clock to the RTC
group-onsemi 0:098463de4c5d 155 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
group-onsemi 0:098463de4c5d 156
group-onsemi 0:098463de4c5d 157 // Disable the clock to the synchronizer
group-onsemi 0:098463de4c5d 158 MXC_CLKMAN->sys_clk_ctrl_1_sync = MXC_S_CLKMAN_CLK_SCALE_DISABLED;
group-onsemi 0:098463de4c5d 159 }
group-onsemi 0:098463de4c5d 160
group-onsemi 0:098463de4c5d 161 //******************************************************************************
group-onsemi 0:098463de4c5d 162 int rtc_isenabled(void)
group-onsemi 0:098463de4c5d 163 {
group-onsemi 0:098463de4c5d 164 return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE);
group-onsemi 0:098463de4c5d 165 }
group-onsemi 0:098463de4c5d 166
group-onsemi 0:098463de4c5d 167 //******************************************************************************
group-onsemi 0:098463de4c5d 168 time_t rtc_read(void)
group-onsemi 0:098463de4c5d 169 {
group-onsemi 0:098463de4c5d 170 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
group-onsemi 0:098463de4c5d 171 uint32_t ovf1, ovf2;
group-onsemi 0:098463de4c5d 172
group-onsemi 0:098463de4c5d 173 // Make sure RTC is setup before trying to read
group-onsemi 0:098463de4c5d 174 if (!rtc_inited) {
group-onsemi 0:098463de4c5d 175 rtc_init();
group-onsemi 0:098463de4c5d 176 }
group-onsemi 0:098463de4c5d 177
group-onsemi 0:098463de4c5d 178 // Ensure coherency between overflow_cnt and timer
group-onsemi 0:098463de4c5d 179 do {
group-onsemi 0:098463de4c5d 180 ovf_cnt_1 = overflow_cnt;
group-onsemi 0:098463de4c5d 181 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
group-onsemi 0:098463de4c5d 182 timer_cnt = MXC_RTCTMR->timer;
group-onsemi 0:098463de4c5d 183 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
group-onsemi 0:098463de4c5d 184 ovf_cnt_2 = overflow_cnt;
group-onsemi 0:098463de4c5d 185 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
group-onsemi 0:098463de4c5d 186
group-onsemi 0:098463de4c5d 187 // Account for an unserviced interrupt
group-onsemi 0:098463de4c5d 188 if (ovf1) {
group-onsemi 0:098463de4c5d 189 ovf_cnt_1++;
group-onsemi 0:098463de4c5d 190 }
group-onsemi 0:098463de4c5d 191
group-onsemi 0:098463de4c5d 192 return (timer_cnt >> SHIFT_AMT) + (ovf_cnt_1 << (32 - SHIFT_AMT));
group-onsemi 0:098463de4c5d 193 }
group-onsemi 0:098463de4c5d 194
group-onsemi 0:098463de4c5d 195 //******************************************************************************
group-onsemi 0:098463de4c5d 196 static uint64_t rtc_read64(void)
group-onsemi 0:098463de4c5d 197 {
group-onsemi 0:098463de4c5d 198 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
group-onsemi 0:098463de4c5d 199 uint32_t ovf1, ovf2;
group-onsemi 0:098463de4c5d 200 uint64_t current_us;
group-onsemi 0:098463de4c5d 201
group-onsemi 0:098463de4c5d 202 // Make sure RTC is setup before trying to read
group-onsemi 0:098463de4c5d 203 if (!rtc_inited) {
group-onsemi 0:098463de4c5d 204 rtc_init();
group-onsemi 0:098463de4c5d 205 }
group-onsemi 0:098463de4c5d 206
group-onsemi 0:098463de4c5d 207 // Ensure coherency between overflow_cnt and timer
group-onsemi 0:098463de4c5d 208 do {
group-onsemi 0:098463de4c5d 209 ovf_cnt_1 = overflow_cnt;
group-onsemi 0:098463de4c5d 210 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
group-onsemi 0:098463de4c5d 211 timer_cnt = MXC_RTCTMR->timer;
group-onsemi 0:098463de4c5d 212 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
group-onsemi 0:098463de4c5d 213 ovf_cnt_2 = overflow_cnt;
group-onsemi 0:098463de4c5d 214 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
group-onsemi 0:098463de4c5d 215
group-onsemi 0:098463de4c5d 216 // Account for an unserviced interrupt
group-onsemi 0:098463de4c5d 217 if (ovf1) {
group-onsemi 0:098463de4c5d 218 ovf_cnt_1++;
group-onsemi 0:098463de4c5d 219 }
group-onsemi 0:098463de4c5d 220
group-onsemi 0:098463de4c5d 221 current_us = (((uint64_t)timer_cnt * 1000000) >> SHIFT_AMT) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - SHIFT_AMT));
group-onsemi 0:098463de4c5d 222
group-onsemi 0:098463de4c5d 223 return current_us;
group-onsemi 0:098463de4c5d 224 }
group-onsemi 0:098463de4c5d 225
group-onsemi 0:098463de4c5d 226 //******************************************************************************
group-onsemi 0:098463de4c5d 227 void rtc_write(time_t t)
group-onsemi 0:098463de4c5d 228 {
group-onsemi 0:098463de4c5d 229 // Make sure RTC is setup before accessing
group-onsemi 0:098463de4c5d 230 if (!rtc_inited) {
group-onsemi 0:098463de4c5d 231 rtc_init();
group-onsemi 0:098463de4c5d 232 }
group-onsemi 0:098463de4c5d 233
group-onsemi 0:098463de4c5d 234 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating
group-onsemi 0:098463de4c5d 235 MXC_RTCTMR->timer = t << SHIFT_AMT;
group-onsemi 0:098463de4c5d 236 overflow_cnt = t >> (32 - SHIFT_AMT);
group-onsemi 0:098463de4c5d 237 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; // enable the timer while updating
group-onsemi 0:098463de4c5d 238 }
group-onsemi 0:098463de4c5d 239
group-onsemi 0:098463de4c5d 240 //******************************************************************************
group-onsemi 0:098463de4c5d 241 void lp_ticker_set_interrupt(timestamp_t timestamp)
group-onsemi 0:098463de4c5d 242 {
group-onsemi 0:098463de4c5d 243 uint32_t comp_value;
group-onsemi 0:098463de4c5d 244 uint64_t curr_ts64;
group-onsemi 0:098463de4c5d 245 uint64_t ts64;
group-onsemi 0:098463de4c5d 246
group-onsemi 0:098463de4c5d 247 // Note: interrupts are disabled before this function is called.
group-onsemi 0:098463de4c5d 248
group-onsemi 0:098463de4c5d 249 // Disable the alarm while it is prepared
group-onsemi 0:098463de4c5d 250 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
group-onsemi 0:098463de4c5d 251
group-onsemi 0:098463de4c5d 252 curr_ts64 = rtc_read64();
group-onsemi 0:098463de4c5d 253 ts64 = (uint64_t)timestamp | (curr_ts64 & 0xFFFFFFFF00000000ULL);
group-onsemi 0:098463de4c5d 254
group-onsemi 0:098463de4c5d 255 // If this event is older than a recent window, it must be in the future
group-onsemi 0:098463de4c5d 256 if ((ts64 < (curr_ts64 - WINDOW)) && ((curr_ts64 - WINDOW) < curr_ts64)) {
group-onsemi 0:098463de4c5d 257 ts64 += 0x100000000ULL;
group-onsemi 0:098463de4c5d 258 }
group-onsemi 0:098463de4c5d 259
group-onsemi 0:098463de4c5d 260 uint32_t timer = MXC_RTCTMR->timer;
group-onsemi 0:098463de4c5d 261 if (ts64 <= curr_ts64) {
group-onsemi 0:098463de4c5d 262 // This event has already occurred. Set the alarm to expire immediately.
group-onsemi 0:098463de4c5d 263 comp_value = timer + 1;
group-onsemi 0:098463de4c5d 264 } else {
group-onsemi 0:098463de4c5d 265 comp_value = (ts64 << SHIFT_AMT) / 1000000;
group-onsemi 0:098463de4c5d 266 }
group-onsemi 0:098463de4c5d 267
group-onsemi 0:098463de4c5d 268 // Ensure that the compare value is far enough in the future to guarantee the interrupt occurs.
group-onsemi 0:098463de4c5d 269 if ((comp_value < (timer + 2)) && (comp_value > (timer - 10))) {
group-onsemi 0:098463de4c5d 270 comp_value = timer + 2;
group-onsemi 0:098463de4c5d 271 }
group-onsemi 0:098463de4c5d 272
group-onsemi 0:098463de4c5d 273 MXC_RTCTMR->comp[0] = comp_value;
group-onsemi 0:098463de4c5d 274 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
group-onsemi 0:098463de4c5d 275 MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; // enable the interrupt
group-onsemi 0:098463de4c5d 276
group-onsemi 0:098463de4c5d 277 // Enable wakeup from RTC
group-onsemi 0:098463de4c5d 278 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0;
group-onsemi 0:098463de4c5d 279
group-onsemi 0:098463de4c5d 280 // Wait for pending transactions
group-onsemi 0:098463de4c5d 281 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
group-onsemi 0:098463de4c5d 282 }
group-onsemi 0:098463de4c5d 283
group-onsemi 0:098463de4c5d 284 //******************************************************************************
group-onsemi 0:098463de4c5d 285 inline void lp_ticker_disable_interrupt(void)
group-onsemi 0:098463de4c5d 286 {
group-onsemi 0:098463de4c5d 287 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
group-onsemi 0:098463de4c5d 288 }
group-onsemi 0:098463de4c5d 289
group-onsemi 0:098463de4c5d 290 //******************************************************************************
group-onsemi 0:098463de4c5d 291 inline void lp_ticker_clear_interrupt(void)
group-onsemi 0:098463de4c5d 292 {
group-onsemi 0:098463de4c5d 293 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
group-onsemi 0:098463de4c5d 294
group-onsemi 0:098463de4c5d 295 // Wait for pending transactions
group-onsemi 0:098463de4c5d 296 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
group-onsemi 0:098463de4c5d 297 }
group-onsemi 0:098463de4c5d 298
group-onsemi 0:098463de4c5d 299 //******************************************************************************
group-onsemi 0:098463de4c5d 300 inline uint32_t lp_ticker_read(void)
group-onsemi 0:098463de4c5d 301 {
group-onsemi 0:098463de4c5d 302 return rtc_read64();
group-onsemi 0:098463de4c5d 303 }