ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32620/i2c_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 35 #include "i2c_api.h"
group-onsemi 0:098463de4c5d 36 #include "cmsis.h"
group-onsemi 0:098463de4c5d 37 #include "i2cm_regs.h"
group-onsemi 0:098463de4c5d 38 #include "clkman_regs.h"
group-onsemi 0:098463de4c5d 39 #include "ioman_regs.h"
group-onsemi 0:098463de4c5d 40 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 #define I2C_SLAVE_ADDR_READ_BIT 0x0001
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 #ifndef MXC_I2CM_TX_TIMEOUT
group-onsemi 0:098463de4c5d 45 #define MXC_I2CM_TX_TIMEOUT 0x5000
group-onsemi 0:098463de4c5d 46 #endif
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 #ifndef MXC_I2CM_RX_TIMEOUT
group-onsemi 0:098463de4c5d 49 #define MXC_I2CM_RX_TIMEOUT 0x5000
group-onsemi 0:098463de4c5d 50 #endif
group-onsemi 0:098463de4c5d 51
group-onsemi 0:098463de4c5d 52 typedef enum {
group-onsemi 0:098463de4c5d 53 /** 100KHz */
group-onsemi 0:098463de4c5d 54 MXC_E_I2CM_SPEED_100KHZ = 0,
group-onsemi 0:098463de4c5d 55 /** 400KHz */
group-onsemi 0:098463de4c5d 56 MXC_E_I2CM_SPEED_400KHZ
group-onsemi 0:098463de4c5d 57 } i2cm_speed_t;
group-onsemi 0:098463de4c5d 58
group-onsemi 0:098463de4c5d 59 /* Clock divider lookup table */
group-onsemi 0:098463de4c5d 60 static const uint32_t clk_div_table[2][8] = {
group-onsemi 0:098463de4c5d 61 /* MXC_E_I2CM_SPEED_100KHZ */
group-onsemi 0:098463de4c5d 62 {
group-onsemi 0:098463de4c5d 63 /* 0: 12MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
group-onsemi 0:098463de4c5d 64 (17 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
group-onsemi 0:098463de4c5d 65 (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 66 /* 1: 24MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
group-onsemi 0:098463de4c5d 67 (38 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
group-onsemi 0:098463de4c5d 68 (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 69 /* 2: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 70 /* 3: 48MHz */ ((24 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
group-onsemi 0:098463de4c5d 71 (80 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
group-onsemi 0:098463de4c5d 72 (288 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 73 /* 4: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 74 /* 5: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 75 /* 6: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 76 /* 7: 96MHz */ ((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
group-onsemi 0:098463de4c5d 77 (164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
group-onsemi 0:098463de4c5d 78 (576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 79 },
group-onsemi 0:098463de4c5d 80 /* MXC_E_I2CM_SPEED_400KHZ */
group-onsemi 0:098463de4c5d 81 {
group-onsemi 0:098463de4c5d 82 /* 0: 12MHz */ ((2 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
group-onsemi 0:098463de4c5d 83 (1 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
group-onsemi 0:098463de4c5d 84 (18 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 85 /* 1: 24MHz */ ((3 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
group-onsemi 0:098463de4c5d 86 (5 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
group-onsemi 0:098463de4c5d 87 (36 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 88 /* 2: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 89 /* 3: 48MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
group-onsemi 0:098463de4c5d 90 (15 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
group-onsemi 0:098463de4c5d 91 (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 92 /* 4: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 93 /* 5: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 94 /* 6: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 95 /* 7: 96MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
group-onsemi 0:098463de4c5d 96 (33 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
group-onsemi 0:098463de4c5d 97 (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 98 },
group-onsemi 0:098463de4c5d 99 };
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
group-onsemi 0:098463de4c5d 102 {
group-onsemi 0:098463de4c5d 103 // determine the I2C to use
group-onsemi 0:098463de4c5d 104 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
group-onsemi 0:098463de4c5d 105 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
group-onsemi 0:098463de4c5d 106 mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl);
group-onsemi 0:098463de4c5d 107 MBED_ASSERT((int)i2c != NC);
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109 obj->i2c = i2c;
group-onsemi 0:098463de4c5d 110 obj->fifos = (mxc_i2cm_fifo_regs_t*)MXC_I2CM_GET_BASE_FIFO(MXC_I2CM_GET_IDX(i2c));
group-onsemi 0:098463de4c5d 111 obj->start_pending = 0;
group-onsemi 0:098463de4c5d 112 obj->stop_pending = 0;
group-onsemi 0:098463de4c5d 113
group-onsemi 0:098463de4c5d 114 // configure the pins
group-onsemi 0:098463de4c5d 115 pinmap_pinout(sda, PinMap_I2C_SDA);
group-onsemi 0:098463de4c5d 116 pinmap_pinout(scl, PinMap_I2C_SCL);
group-onsemi 0:098463de4c5d 117
group-onsemi 0:098463de4c5d 118 // enable the clock
group-onsemi 0:098463de4c5d 119 MXC_CLKMAN->sys_clk_ctrl_9_i2cm = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
group-onsemi 0:098463de4c5d 120
group-onsemi 0:098463de4c5d 121 // reset module
group-onsemi 0:098463de4c5d 122 i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
group-onsemi 0:098463de4c5d 123 i2c->ctrl = 0;
group-onsemi 0:098463de4c5d 124
group-onsemi 0:098463de4c5d 125 // set default frequency at 100k
group-onsemi 0:098463de4c5d 126 i2c_frequency(obj, 100000);
group-onsemi 0:098463de4c5d 127
group-onsemi 0:098463de4c5d 128 // set timeout to 255 ms and turn on the auto-stop option
group-onsemi 0:098463de4c5d 129 i2c->timeout = (0xFF << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS) | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN;
group-onsemi 0:098463de4c5d 130
group-onsemi 0:098463de4c5d 131 // enable tx_fifo and rx_fifo
group-onsemi 0:098463de4c5d 132 i2c->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN);
group-onsemi 0:098463de4c5d 133 }
group-onsemi 0:098463de4c5d 134
group-onsemi 0:098463de4c5d 135 void i2c_frequency(i2c_t *obj, int hz)
group-onsemi 0:098463de4c5d 136 {
group-onsemi 0:098463de4c5d 137 // compute clock array index
group-onsemi 0:098463de4c5d 138 // (96Mhz/12M) -1 = 7
group-onsemi 0:098463de4c5d 139 // (48Mhz/12M) -1 = 3
group-onsemi 0:098463de4c5d 140 // (24Mhz/12M) -1 = 1
group-onsemi 0:098463de4c5d 141 // (12Mhz/12M) -1 = 0
group-onsemi 0:098463de4c5d 142 int clki = (SystemCoreClock / 12000000) - 1;
group-onsemi 0:098463de4c5d 143
group-onsemi 0:098463de4c5d 144 // get clock divider settings from lookup table
group-onsemi 0:098463de4c5d 145 if ((hz < 400000) && (clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki] > 0)) {
group-onsemi 0:098463de4c5d 146 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki];
group-onsemi 0:098463de4c5d 147 } else if ((hz >= 400000) && (clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki] > 0)) {
group-onsemi 0:098463de4c5d 148 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki];
group-onsemi 0:098463de4c5d 149 }
group-onsemi 0:098463de4c5d 150 }
group-onsemi 0:098463de4c5d 151
group-onsemi 0:098463de4c5d 152 static int write_tx_fifo(i2c_t *obj, const uint16_t data)
group-onsemi 0:098463de4c5d 153 {
group-onsemi 0:098463de4c5d 154 int timeout = MXC_I2CM_TX_TIMEOUT;
group-onsemi 0:098463de4c5d 155
group-onsemi 0:098463de4c5d 156 while (*obj->fifos->trans) {
group-onsemi 0:098463de4c5d 157 uint32_t intfl = obj->i2c->intfl;
group-onsemi 0:098463de4c5d 158 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
group-onsemi 0:098463de4c5d 159 return I2C_ERROR_NO_SLAVE;
group-onsemi 0:098463de4c5d 160 }
group-onsemi 0:098463de4c5d 161 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
group-onsemi 0:098463de4c5d 162 return I2C_ERROR_BUS_BUSY;
group-onsemi 0:098463de4c5d 163 }
group-onsemi 0:098463de4c5d 164 timeout--;
group-onsemi 0:098463de4c5d 165 }
group-onsemi 0:098463de4c5d 166 *obj->fifos->trans = data;
group-onsemi 0:098463de4c5d 167
group-onsemi 0:098463de4c5d 168 return 0;
group-onsemi 0:098463de4c5d 169 }
group-onsemi 0:098463de4c5d 170
group-onsemi 0:098463de4c5d 171 static int wait_tx_in_progress(i2c_t *obj)
group-onsemi 0:098463de4c5d 172 {
group-onsemi 0:098463de4c5d 173 int timeout = MXC_I2CM_TX_TIMEOUT;
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175 while ((obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout);
group-onsemi 0:098463de4c5d 176
group-onsemi 0:098463de4c5d 177 uint32_t intfl = obj->i2c->intfl;
group-onsemi 0:098463de4c5d 178
group-onsemi 0:098463de4c5d 179 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
group-onsemi 0:098463de4c5d 180 i2c_reset(obj);
group-onsemi 0:098463de4c5d 181 return I2C_ERROR_NO_SLAVE;
group-onsemi 0:098463de4c5d 182 }
group-onsemi 0:098463de4c5d 183
group-onsemi 0:098463de4c5d 184 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
group-onsemi 0:098463de4c5d 185 i2c_reset(obj);
group-onsemi 0:098463de4c5d 186 return I2C_ERROR_BUS_BUSY;
group-onsemi 0:098463de4c5d 187 }
group-onsemi 0:098463de4c5d 188
group-onsemi 0:098463de4c5d 189 return 0;
group-onsemi 0:098463de4c5d 190 }
group-onsemi 0:098463de4c5d 191
group-onsemi 0:098463de4c5d 192 int i2c_start(i2c_t *obj)
group-onsemi 0:098463de4c5d 193 {
group-onsemi 0:098463de4c5d 194 obj->start_pending = 1;
group-onsemi 0:098463de4c5d 195 return 0;
group-onsemi 0:098463de4c5d 196 }
group-onsemi 0:098463de4c5d 197
group-onsemi 0:098463de4c5d 198 int i2c_stop(i2c_t *obj)
group-onsemi 0:098463de4c5d 199 {
group-onsemi 0:098463de4c5d 200 obj->start_pending = 0;
group-onsemi 0:098463de4c5d 201 write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP);
group-onsemi 0:098463de4c5d 202
group-onsemi 0:098463de4c5d 203 return wait_tx_in_progress(obj);
group-onsemi 0:098463de4c5d 204 }
group-onsemi 0:098463de4c5d 205
group-onsemi 0:098463de4c5d 206 void i2c_reset(i2c_t *obj)
group-onsemi 0:098463de4c5d 207 {
group-onsemi 0:098463de4c5d 208 obj->i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
group-onsemi 0:098463de4c5d 209 obj->i2c->intfl = 0x3FF; // clear all interrupts
group-onsemi 0:098463de4c5d 210 obj->i2c->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN;
group-onsemi 0:098463de4c5d 211 obj->start_pending = 0;
group-onsemi 0:098463de4c5d 212 }
group-onsemi 0:098463de4c5d 213
group-onsemi 0:098463de4c5d 214 int i2c_byte_write(i2c_t *obj, int data)
group-onsemi 0:098463de4c5d 215 {
group-onsemi 0:098463de4c5d 216 int err;
group-onsemi 0:098463de4c5d 217
group-onsemi 0:098463de4c5d 218 // clear all interrupts
group-onsemi 0:098463de4c5d 219 obj->i2c->intfl = 0x3FF;
group-onsemi 0:098463de4c5d 220
group-onsemi 0:098463de4c5d 221 if (obj->start_pending) {
group-onsemi 0:098463de4c5d 222 obj->start_pending = 0;
group-onsemi 0:098463de4c5d 223 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_START;
group-onsemi 0:098463de4c5d 224 } else {
group-onsemi 0:098463de4c5d 225 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_TXDATA_ACK;
group-onsemi 0:098463de4c5d 226 }
group-onsemi 0:098463de4c5d 227
group-onsemi 0:098463de4c5d 228 if ((err = write_tx_fifo(obj, data)) != 0) {
group-onsemi 0:098463de4c5d 229 return err;
group-onsemi 0:098463de4c5d 230 }
group-onsemi 0:098463de4c5d 231
group-onsemi 0:098463de4c5d 232 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
group-onsemi 0:098463de4c5d 233
group-onsemi 0:098463de4c5d 234 // Wait for the FIFO to be empty
group-onsemi 0:098463de4c5d 235 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY));
group-onsemi 0:098463de4c5d 236
group-onsemi 0:098463de4c5d 237 if (obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
group-onsemi 0:098463de4c5d 238 i2c_reset(obj);
group-onsemi 0:098463de4c5d 239 return 0;
group-onsemi 0:098463de4c5d 240 }
group-onsemi 0:098463de4c5d 241
group-onsemi 0:098463de4c5d 242 if (obj->i2c->intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) {
group-onsemi 0:098463de4c5d 243 i2c_reset(obj);
group-onsemi 0:098463de4c5d 244 return 2;
group-onsemi 0:098463de4c5d 245 }
group-onsemi 0:098463de4c5d 246
group-onsemi 0:098463de4c5d 247 return 1;
group-onsemi 0:098463de4c5d 248 }
group-onsemi 0:098463de4c5d 249
group-onsemi 0:098463de4c5d 250 int i2c_byte_read(i2c_t *obj, int last)
group-onsemi 0:098463de4c5d 251 {
group-onsemi 0:098463de4c5d 252 uint16_t fifo_value;
group-onsemi 0:098463de4c5d 253 int err;
group-onsemi 0:098463de4c5d 254
group-onsemi 0:098463de4c5d 255 // clear all interrupts
group-onsemi 0:098463de4c5d 256 obj->i2c->intfl = 0x3FF;
group-onsemi 0:098463de4c5d 257
group-onsemi 0:098463de4c5d 258 if (last) {
group-onsemi 0:098463de4c5d 259 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_NACK;
group-onsemi 0:098463de4c5d 260 } else {
group-onsemi 0:098463de4c5d 261 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT;
group-onsemi 0:098463de4c5d 262 }
group-onsemi 0:098463de4c5d 263
group-onsemi 0:098463de4c5d 264 if ((err = write_tx_fifo(obj, fifo_value)) != 0) {
group-onsemi 0:098463de4c5d 265 i2c_reset(obj);
group-onsemi 0:098463de4c5d 266 return err;
group-onsemi 0:098463de4c5d 267 }
group-onsemi 0:098463de4c5d 268
group-onsemi 0:098463de4c5d 269 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
group-onsemi 0:098463de4c5d 270
group-onsemi 0:098463de4c5d 271 int timeout = MXC_I2CM_RX_TIMEOUT;
group-onsemi 0:098463de4c5d 272 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
group-onsemi 0:098463de4c5d 273 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
group-onsemi 0:098463de4c5d 274 if ((--timeout < 0) || (obj->i2c->trans & (MXC_F_I2CM_TRANS_TX_TIMEOUT |
group-onsemi 0:098463de4c5d 275 MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED))) {
group-onsemi 0:098463de4c5d 276 break;
group-onsemi 0:098463de4c5d 277 }
group-onsemi 0:098463de4c5d 278 }
group-onsemi 0:098463de4c5d 279
group-onsemi 0:098463de4c5d 280 if (obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) {
group-onsemi 0:098463de4c5d 281 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
group-onsemi 0:098463de4c5d 282 return *obj->fifos->rslts;
group-onsemi 0:098463de4c5d 283 }
group-onsemi 0:098463de4c5d 284
group-onsemi 0:098463de4c5d 285 i2c_reset(obj);
group-onsemi 0:098463de4c5d 286
group-onsemi 0:098463de4c5d 287 return -1;
group-onsemi 0:098463de4c5d 288 }
group-onsemi 0:098463de4c5d 289
group-onsemi 0:098463de4c5d 290 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
group-onsemi 0:098463de4c5d 291 {
group-onsemi 0:098463de4c5d 292 int err, retval = 0;
group-onsemi 0:098463de4c5d 293 int i;
group-onsemi 0:098463de4c5d 294
group-onsemi 0:098463de4c5d 295 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
group-onsemi 0:098463de4c5d 296 return 0;
group-onsemi 0:098463de4c5d 297 }
group-onsemi 0:098463de4c5d 298
group-onsemi 0:098463de4c5d 299 // clear all interrupts
group-onsemi 0:098463de4c5d 300 obj->i2c->intfl = 0x3FF;
group-onsemi 0:098463de4c5d 301
group-onsemi 0:098463de4c5d 302 // write the address to the fifo
group-onsemi 0:098463de4c5d 303 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address))) != 0) { // start + addr (write)
group-onsemi 0:098463de4c5d 304 i2c_reset(obj);
group-onsemi 0:098463de4c5d 305 return err;
group-onsemi 0:098463de4c5d 306 }
group-onsemi 0:098463de4c5d 307 obj->start_pending = 0;
group-onsemi 0:098463de4c5d 308
group-onsemi 0:098463de4c5d 309 // start the transaction
group-onsemi 0:098463de4c5d 310 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
group-onsemi 0:098463de4c5d 311
group-onsemi 0:098463de4c5d 312 // load as much of the cmd into the FIFO as possible
group-onsemi 0:098463de4c5d 313 for (i = 0; i < length; i++) {
group-onsemi 0:098463de4c5d 314 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != 0) { // cmd (expect ACK)
group-onsemi 0:098463de4c5d 315 retval = (retval ? retval : err);
group-onsemi 0:098463de4c5d 316 break;
group-onsemi 0:098463de4c5d 317 }
group-onsemi 0:098463de4c5d 318 }
group-onsemi 0:098463de4c5d 319
group-onsemi 0:098463de4c5d 320 if (stop) {
group-onsemi 0:098463de4c5d 321 obj->stop_pending = 0;
group-onsemi 0:098463de4c5d 322 if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
group-onsemi 0:098463de4c5d 323 retval = (retval ? retval : err);
group-onsemi 0:098463de4c5d 324 }
group-onsemi 0:098463de4c5d 325
group-onsemi 0:098463de4c5d 326 if ((err = wait_tx_in_progress(obj)) != 0) {
group-onsemi 0:098463de4c5d 327 retval = (retval ? retval : err);
group-onsemi 0:098463de4c5d 328 }
group-onsemi 0:098463de4c5d 329 } else {
group-onsemi 0:098463de4c5d 330 obj->stop_pending = 1;
group-onsemi 0:098463de4c5d 331 int timeout = MXC_I2CM_TX_TIMEOUT;
group-onsemi 0:098463de4c5d 332 // Wait for TX fifo to be empty
group-onsemi 0:098463de4c5d 333 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY) && timeout--);
group-onsemi 0:098463de4c5d 334 }
group-onsemi 0:098463de4c5d 335
group-onsemi 0:098463de4c5d 336 if (retval == 0) {
group-onsemi 0:098463de4c5d 337 return length;
group-onsemi 0:098463de4c5d 338 }
group-onsemi 0:098463de4c5d 339
group-onsemi 0:098463de4c5d 340 i2c_reset(obj);
group-onsemi 0:098463de4c5d 341
group-onsemi 0:098463de4c5d 342 return retval;
group-onsemi 0:098463de4c5d 343 }
group-onsemi 0:098463de4c5d 344
group-onsemi 0:098463de4c5d 345 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
group-onsemi 0:098463de4c5d 346 {
group-onsemi 0:098463de4c5d 347 int err, retval = 0;
group-onsemi 0:098463de4c5d 348 int i = length;
group-onsemi 0:098463de4c5d 349 int timeout;
group-onsemi 0:098463de4c5d 350
group-onsemi 0:098463de4c5d 351 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
group-onsemi 0:098463de4c5d 352 return 0;
group-onsemi 0:098463de4c5d 353 }
group-onsemi 0:098463de4c5d 354
group-onsemi 0:098463de4c5d 355 // clear all interrupts
group-onsemi 0:098463de4c5d 356 obj->i2c->intfl = 0x3FF;
group-onsemi 0:098463de4c5d 357
group-onsemi 0:098463de4c5d 358 // start + addr (read)
group-onsemi 0:098463de4c5d 359 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address | I2C_SLAVE_ADDR_READ_BIT))) != 0) {
group-onsemi 0:098463de4c5d 360 goto read_done;
group-onsemi 0:098463de4c5d 361 }
group-onsemi 0:098463de4c5d 362 obj->start_pending = 0;
group-onsemi 0:098463de4c5d 363
group-onsemi 0:098463de4c5d 364 while (i > 256) {
group-onsemi 0:098463de4c5d 365 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != 0) {
group-onsemi 0:098463de4c5d 366 goto read_done;
group-onsemi 0:098463de4c5d 367 }
group-onsemi 0:098463de4c5d 368 i -= 256;
group-onsemi 0:098463de4c5d 369 }
group-onsemi 0:098463de4c5d 370
group-onsemi 0:098463de4c5d 371 if (i > 1) {
group-onsemi 0:098463de4c5d 372 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i - 2)))) != 0) {
group-onsemi 0:098463de4c5d 373 goto read_done;
group-onsemi 0:098463de4c5d 374 }
group-onsemi 0:098463de4c5d 375 }
group-onsemi 0:098463de4c5d 376
group-onsemi 0:098463de4c5d 377 // start the transaction
group-onsemi 0:098463de4c5d 378 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
group-onsemi 0:098463de4c5d 379
group-onsemi 0:098463de4c5d 380 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK)) != 0) { // NACK last data byte
group-onsemi 0:098463de4c5d 381 goto read_done;
group-onsemi 0:098463de4c5d 382 }
group-onsemi 0:098463de4c5d 383
group-onsemi 0:098463de4c5d 384 if (stop) {
group-onsemi 0:098463de4c5d 385 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
group-onsemi 0:098463de4c5d 386 goto read_done;
group-onsemi 0:098463de4c5d 387 }
group-onsemi 0:098463de4c5d 388 }
group-onsemi 0:098463de4c5d 389
group-onsemi 0:098463de4c5d 390 timeout = MXC_I2CM_RX_TIMEOUT;
group-onsemi 0:098463de4c5d 391 i = 0;
group-onsemi 0:098463de4c5d 392 while (i < length) {
group-onsemi 0:098463de4c5d 393 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
group-onsemi 0:098463de4c5d 394 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
group-onsemi 0:098463de4c5d 395 if ((--timeout < 0) || (obj->i2c->trans & (MXC_F_I2CM_TRANS_TX_TIMEOUT |
group-onsemi 0:098463de4c5d 396 MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED))) {
group-onsemi 0:098463de4c5d 397 retval = -3;
group-onsemi 0:098463de4c5d 398 goto read_done;
group-onsemi 0:098463de4c5d 399 }
group-onsemi 0:098463de4c5d 400 }
group-onsemi 0:098463de4c5d 401
group-onsemi 0:098463de4c5d 402 timeout = MXC_I2CM_RX_TIMEOUT;
group-onsemi 0:098463de4c5d 403
group-onsemi 0:098463de4c5d 404 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
group-onsemi 0:098463de4c5d 405
group-onsemi 0:098463de4c5d 406 uint16_t temp = *obj->fifos->rslts;
group-onsemi 0:098463de4c5d 407
group-onsemi 0:098463de4c5d 408 if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) {
group-onsemi 0:098463de4c5d 409 continue;
group-onsemi 0:098463de4c5d 410 }
group-onsemi 0:098463de4c5d 411 data[i++] = (uint8_t) temp;
group-onsemi 0:098463de4c5d 412 }
group-onsemi 0:098463de4c5d 413
group-onsemi 0:098463de4c5d 414 read_done:
group-onsemi 0:098463de4c5d 415
group-onsemi 0:098463de4c5d 416 if (stop) {
group-onsemi 0:098463de4c5d 417 obj->stop_pending = 0;
group-onsemi 0:098463de4c5d 418 if ((err = wait_tx_in_progress(obj)) != 0) {
group-onsemi 0:098463de4c5d 419 retval = (retval ? retval : err);
group-onsemi 0:098463de4c5d 420 }
group-onsemi 0:098463de4c5d 421 } else {
group-onsemi 0:098463de4c5d 422 obj->stop_pending = 1;
group-onsemi 0:098463de4c5d 423 }
group-onsemi 0:098463de4c5d 424
group-onsemi 0:098463de4c5d 425 if (retval == 0) {
group-onsemi 0:098463de4c5d 426 return length;
group-onsemi 0:098463de4c5d 427 }
group-onsemi 0:098463de4c5d 428
group-onsemi 0:098463de4c5d 429 i2c_reset(obj);
group-onsemi 0:098463de4c5d 430
group-onsemi 0:098463de4c5d 431 return retval;
group-onsemi 0:098463de4c5d 432 }