5.2.1 - Updated I2C files
Dependents: mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510
targets/TARGET_ARM_SSG/TARGET_IOTSS/PeripheralNames.h@1:f30bdcd2b33b, 2017-02-27 (annotated)
- Committer:
- jacobjohnson
- Date:
- Mon Feb 27 17:45:05 2017 +0000
- Revision:
- 1:f30bdcd2b33b
- Parent:
- 0:098463de4c5d
changed the inputscale from 1 to 7 in analogin_api.c. This will need to be changed later, and accessed from the main level, but for now this allows the adc to read a value from 0 to 3.7V, instead of just up to 1V.;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
group-onsemi | 0:098463de4c5d | 1 | /* mbed Microcontroller Library |
group-onsemi | 0:098463de4c5d | 2 | * Copyright (c) 2006-2015 ARM Limited |
group-onsemi | 0:098463de4c5d | 3 | * |
group-onsemi | 0:098463de4c5d | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
group-onsemi | 0:098463de4c5d | 5 | * you may not use this file except in compliance with the License. |
group-onsemi | 0:098463de4c5d | 6 | * You may obtain a copy of the License at |
group-onsemi | 0:098463de4c5d | 7 | * |
group-onsemi | 0:098463de4c5d | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
group-onsemi | 0:098463de4c5d | 9 | * |
group-onsemi | 0:098463de4c5d | 10 | * Unless required by applicable law or agreed to in writing, software |
group-onsemi | 0:098463de4c5d | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
group-onsemi | 0:098463de4c5d | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
group-onsemi | 0:098463de4c5d | 13 | * See the License for the specific language governing permissions and |
group-onsemi | 0:098463de4c5d | 14 | * limitations under the License. |
group-onsemi | 0:098463de4c5d | 15 | */ |
group-onsemi | 0:098463de4c5d | 16 | #ifndef MBED_PERIPHERALNAMES_H |
group-onsemi | 0:098463de4c5d | 17 | #define MBED_PERIPHERALNAMES_H |
group-onsemi | 0:098463de4c5d | 18 | |
group-onsemi | 0:098463de4c5d | 19 | #include "cmsis.h" |
group-onsemi | 0:098463de4c5d | 20 | |
group-onsemi | 0:098463de4c5d | 21 | #ifdef __cplusplus |
group-onsemi | 0:098463de4c5d | 22 | extern "C" { |
group-onsemi | 0:098463de4c5d | 23 | #endif |
group-onsemi | 0:098463de4c5d | 24 | |
group-onsemi | 0:098463de4c5d | 25 | typedef enum { |
group-onsemi | 0:098463de4c5d | 26 | UART_0 = (int)CMSDK_UART1_BASE, |
group-onsemi | 0:098463de4c5d | 27 | UART_1 = (int)CMSDK_UART3_BASE, |
group-onsemi | 0:098463de4c5d | 28 | UART_2 = (int)CMSDK_UART0_BASE, |
group-onsemi | 0:098463de4c5d | 29 | UART_3 = (int)CMSDK_UART2_BASE |
group-onsemi | 0:098463de4c5d | 30 | } UARTName; |
group-onsemi | 0:098463de4c5d | 31 | |
group-onsemi | 0:098463de4c5d | 32 | typedef enum { |
group-onsemi | 0:098463de4c5d | 33 | I2C_0 = (int)MPS2_TSC_I2C_BASE, |
group-onsemi | 0:098463de4c5d | 34 | I2C_1 = (int)MPS2_AAIC_I2C_BASE, |
group-onsemi | 0:098463de4c5d | 35 | I2C_2 = (int)MPS2_SHIELD0_I2C_BASE, |
group-onsemi | 0:098463de4c5d | 36 | I2C_3 = (int)MPS2_SHIELD1_I2C_BASE |
group-onsemi | 0:098463de4c5d | 37 | |
group-onsemi | 0:098463de4c5d | 38 | } I2CName; |
group-onsemi | 0:098463de4c5d | 39 | |
group-onsemi | 0:098463de4c5d | 40 | typedef enum { |
group-onsemi | 0:098463de4c5d | 41 | ADC0_0 = 0, |
group-onsemi | 0:098463de4c5d | 42 | ADC0_1, |
group-onsemi | 0:098463de4c5d | 43 | ADC0_2, |
group-onsemi | 0:098463de4c5d | 44 | ADC0_3, |
group-onsemi | 0:098463de4c5d | 45 | ADC0_4, |
group-onsemi | 0:098463de4c5d | 46 | ADC0_5, |
group-onsemi | 0:098463de4c5d | 47 | ADC0_6, |
group-onsemi | 0:098463de4c5d | 48 | ADC0_7, |
group-onsemi | 0:098463de4c5d | 49 | ADC0_8, |
group-onsemi | 0:098463de4c5d | 50 | ADC0_9, |
group-onsemi | 0:098463de4c5d | 51 | ADC0_10, |
group-onsemi | 0:098463de4c5d | 52 | ADC0_11 |
group-onsemi | 0:098463de4c5d | 53 | } ADCName; |
group-onsemi | 0:098463de4c5d | 54 | |
group-onsemi | 0:098463de4c5d | 55 | typedef enum { |
group-onsemi | 0:098463de4c5d | 56 | SPI_0 = (int)MPS2_SSP0_BASE, |
group-onsemi | 0:098463de4c5d | 57 | SPI_1 = (int)MPS2_SSP1_BASE, |
group-onsemi | 0:098463de4c5d | 58 | SPI_2 = (int)MPS2_SSP2_BASE, |
group-onsemi | 0:098463de4c5d | 59 | SPI_3 = (int)MPS2_SSP3_BASE, |
group-onsemi | 0:098463de4c5d | 60 | SPI_4 = (int)MPS2_SSP4_BASE |
group-onsemi | 0:098463de4c5d | 61 | } SPIName; |
group-onsemi | 0:098463de4c5d | 62 | |
group-onsemi | 0:098463de4c5d | 63 | typedef enum { |
group-onsemi | 0:098463de4c5d | 64 | PWM_1 = 0, |
group-onsemi | 0:098463de4c5d | 65 | PWM_2, |
group-onsemi | 0:098463de4c5d | 66 | PWM_3, |
group-onsemi | 0:098463de4c5d | 67 | PWM_4, |
group-onsemi | 0:098463de4c5d | 68 | PWM_5, |
group-onsemi | 0:098463de4c5d | 69 | PWM_6, |
group-onsemi | 0:098463de4c5d | 70 | PWM_7, |
group-onsemi | 0:098463de4c5d | 71 | PWM_8, |
group-onsemi | 0:098463de4c5d | 72 | PWM_9, |
group-onsemi | 0:098463de4c5d | 73 | PWM_10, |
group-onsemi | 0:098463de4c5d | 74 | PWM_11 |
group-onsemi | 0:098463de4c5d | 75 | } PWMName; |
group-onsemi | 0:098463de4c5d | 76 | |
group-onsemi | 0:098463de4c5d | 77 | #define STDIO_UART_TX USBTX |
group-onsemi | 0:098463de4c5d | 78 | #define STDIO_UART_RX USBRX |
group-onsemi | 0:098463de4c5d | 79 | #define STDIO_UART UART_0 |
group-onsemi | 0:098463de4c5d | 80 | |
group-onsemi | 0:098463de4c5d | 81 | #define MBED_UART0 USBTX, USBRX |
group-onsemi | 0:098463de4c5d | 82 | #define MBED_UART1 XB_TX, XB_RX |
group-onsemi | 0:098463de4c5d | 83 | #define MBED_UART2 SH0_TX, SH0_RX |
group-onsemi | 0:098463de4c5d | 84 | #define MBED_UART3 SH1_TX, SH1_RX |
group-onsemi | 0:098463de4c5d | 85 | #define MBED_UARTUSB USBTX, USBRX |
group-onsemi | 0:098463de4c5d | 86 | |
group-onsemi | 0:098463de4c5d | 87 | #ifdef __cplusplus |
group-onsemi | 0:098463de4c5d | 88 | } |
group-onsemi | 0:098463de4c5d | 89 | #endif |
group-onsemi | 0:098463de4c5d | 90 | |
group-onsemi | 0:098463de4c5d | 91 | #endif |