5.2.1 - Updated I2C files
Dependents: mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510
targets/TARGET_NXP/TARGET_LPC408X/us_ticker.c@0:098463de4c5d, 2017-01-25 (annotated)
- Committer:
- group-onsemi
- Date:
- Wed Jan 25 20:34:15 2017 +0000
- Revision:
- 0:098463de4c5d
Initial commit
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
group-onsemi | 0:098463de4c5d | 1 | /* mbed Microcontroller Library |
group-onsemi | 0:098463de4c5d | 2 | * Copyright (c) 2006-2013 ARM Limited |
group-onsemi | 0:098463de4c5d | 3 | * |
group-onsemi | 0:098463de4c5d | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
group-onsemi | 0:098463de4c5d | 5 | * you may not use this file except in compliance with the License. |
group-onsemi | 0:098463de4c5d | 6 | * You may obtain a copy of the License at |
group-onsemi | 0:098463de4c5d | 7 | * |
group-onsemi | 0:098463de4c5d | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
group-onsemi | 0:098463de4c5d | 9 | * |
group-onsemi | 0:098463de4c5d | 10 | * Unless required by applicable law or agreed to in writing, software |
group-onsemi | 0:098463de4c5d | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
group-onsemi | 0:098463de4c5d | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
group-onsemi | 0:098463de4c5d | 13 | * See the License for the specific language governing permissions and |
group-onsemi | 0:098463de4c5d | 14 | * limitations under the License. |
group-onsemi | 0:098463de4c5d | 15 | */ |
group-onsemi | 0:098463de4c5d | 16 | #include <stddef.h> |
group-onsemi | 0:098463de4c5d | 17 | #include "us_ticker_api.h" |
group-onsemi | 0:098463de4c5d | 18 | #include "PeripheralNames.h" |
group-onsemi | 0:098463de4c5d | 19 | |
group-onsemi | 0:098463de4c5d | 20 | #define US_TICKER_TIMER ((LPC_TIM_TypeDef *)LPC_TIM3_BASE) |
group-onsemi | 0:098463de4c5d | 21 | #define US_TICKER_TIMER_IRQn TIMER3_IRQn |
group-onsemi | 0:098463de4c5d | 22 | |
group-onsemi | 0:098463de4c5d | 23 | int us_ticker_inited = 0; |
group-onsemi | 0:098463de4c5d | 24 | |
group-onsemi | 0:098463de4c5d | 25 | void us_ticker_init(void) { |
group-onsemi | 0:098463de4c5d | 26 | if (us_ticker_inited) return; |
group-onsemi | 0:098463de4c5d | 27 | us_ticker_inited = 1; |
group-onsemi | 0:098463de4c5d | 28 | |
group-onsemi | 0:098463de4c5d | 29 | LPC_SC->PCONP |= 1 << 23; // Clock TIMER_3 |
group-onsemi | 0:098463de4c5d | 30 | |
group-onsemi | 0:098463de4c5d | 31 | US_TICKER_TIMER->CTCR = 0x0; // timer mode |
group-onsemi | 0:098463de4c5d | 32 | uint32_t PCLK = PeripheralClock; |
group-onsemi | 0:098463de4c5d | 33 | |
group-onsemi | 0:098463de4c5d | 34 | US_TICKER_TIMER->TCR = 0x2; // reset |
group-onsemi | 0:098463de4c5d | 35 | |
group-onsemi | 0:098463de4c5d | 36 | uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks) |
group-onsemi | 0:098463de4c5d | 37 | US_TICKER_TIMER->PR = prescale - 1; |
group-onsemi | 0:098463de4c5d | 38 | US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0 |
group-onsemi | 0:098463de4c5d | 39 | |
group-onsemi | 0:098463de4c5d | 40 | NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); |
group-onsemi | 0:098463de4c5d | 41 | NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); |
group-onsemi | 0:098463de4c5d | 42 | } |
group-onsemi | 0:098463de4c5d | 43 | |
group-onsemi | 0:098463de4c5d | 44 | uint32_t us_ticker_read() { |
group-onsemi | 0:098463de4c5d | 45 | if (!us_ticker_inited) |
group-onsemi | 0:098463de4c5d | 46 | us_ticker_init(); |
group-onsemi | 0:098463de4c5d | 47 | |
group-onsemi | 0:098463de4c5d | 48 | return US_TICKER_TIMER->TC; |
group-onsemi | 0:098463de4c5d | 49 | } |
group-onsemi | 0:098463de4c5d | 50 | |
group-onsemi | 0:098463de4c5d | 51 | void us_ticker_set_interrupt(timestamp_t timestamp) { |
group-onsemi | 0:098463de4c5d | 52 | // set match value |
group-onsemi | 0:098463de4c5d | 53 | US_TICKER_TIMER->MR0 = (uint32_t)timestamp; |
group-onsemi | 0:098463de4c5d | 54 | // enable match interrupt |
group-onsemi | 0:098463de4c5d | 55 | US_TICKER_TIMER->MCR |= 1; |
group-onsemi | 0:098463de4c5d | 56 | } |
group-onsemi | 0:098463de4c5d | 57 | |
group-onsemi | 0:098463de4c5d | 58 | void us_ticker_disable_interrupt(void) { |
group-onsemi | 0:098463de4c5d | 59 | US_TICKER_TIMER->MCR &= ~1; |
group-onsemi | 0:098463de4c5d | 60 | } |
group-onsemi | 0:098463de4c5d | 61 | |
group-onsemi | 0:098463de4c5d | 62 | void us_ticker_clear_interrupt(void) { |
group-onsemi | 0:098463de4c5d | 63 | US_TICKER_TIMER->IR = 1; |
group-onsemi | 0:098463de4c5d | 64 | } |