5.2.1 - Updated I2C files
Dependents: mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510
targets/TARGET_NXP/TARGET_LPC11XX_11CXX/pinmap.c@0:098463de4c5d, 2017-01-25 (annotated)
- Committer:
- group-onsemi
- Date:
- Wed Jan 25 20:34:15 2017 +0000
- Revision:
- 0:098463de4c5d
Initial commit
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
group-onsemi | 0:098463de4c5d | 1 | /* mbed Microcontroller Library |
group-onsemi | 0:098463de4c5d | 2 | * Copyright (c) 2006-2013 ARM Limited |
group-onsemi | 0:098463de4c5d | 3 | * |
group-onsemi | 0:098463de4c5d | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
group-onsemi | 0:098463de4c5d | 5 | * you may not use this file except in compliance with the License. |
group-onsemi | 0:098463de4c5d | 6 | * You may obtain a copy of the License at |
group-onsemi | 0:098463de4c5d | 7 | * |
group-onsemi | 0:098463de4c5d | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
group-onsemi | 0:098463de4c5d | 9 | * |
group-onsemi | 0:098463de4c5d | 10 | * Unless required by applicable law or agreed to in writing, software |
group-onsemi | 0:098463de4c5d | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
group-onsemi | 0:098463de4c5d | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
group-onsemi | 0:098463de4c5d | 13 | * See the License for the specific language governing permissions and |
group-onsemi | 0:098463de4c5d | 14 | * limitations under the License. |
group-onsemi | 0:098463de4c5d | 15 | */ |
group-onsemi | 0:098463de4c5d | 16 | #include "mbed_assert.h" |
group-onsemi | 0:098463de4c5d | 17 | #include "pinmap.h" |
group-onsemi | 0:098463de4c5d | 18 | #include "mbed_error.h" |
group-onsemi | 0:098463de4c5d | 19 | |
group-onsemi | 0:098463de4c5d | 20 | void pin_function(PinName pin, int function) { |
group-onsemi | 0:098463de4c5d | 21 | MBED_ASSERT(pin != (PinName)NC); |
group-onsemi | 0:098463de4c5d | 22 | uint32_t offset = (uint32_t)pin & 0xff; |
group-onsemi | 0:098463de4c5d | 23 | __IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + offset); |
group-onsemi | 0:098463de4c5d | 24 | |
group-onsemi | 0:098463de4c5d | 25 | // pin function bits: [2:0] -> 111 = (0x7) |
group-onsemi | 0:098463de4c5d | 26 | *reg = (*reg & ~0x7) | (function & 0x7); |
group-onsemi | 0:098463de4c5d | 27 | } |
group-onsemi | 0:098463de4c5d | 28 | |
group-onsemi | 0:098463de4c5d | 29 | void pin_mode(PinName pin, PinMode mode) { |
group-onsemi | 0:098463de4c5d | 30 | MBED_ASSERT(pin != (PinName)NC); |
group-onsemi | 0:098463de4c5d | 31 | uint32_t offset = (uint32_t)pin & 0xff; |
group-onsemi | 0:098463de4c5d | 32 | uint32_t drain = ((uint32_t)mode & (uint32_t)OpenDrain) >> 2; |
group-onsemi | 0:098463de4c5d | 33 | |
group-onsemi | 0:098463de4c5d | 34 | __IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + offset); |
group-onsemi | 0:098463de4c5d | 35 | uint32_t tmp = *reg; |
group-onsemi | 0:098463de4c5d | 36 | |
group-onsemi | 0:098463de4c5d | 37 | // pin mode bits: [4:3] -> 11000 = (0x3 << 3) |
group-onsemi | 0:098463de4c5d | 38 | tmp &= ~(0x3 << 3); |
group-onsemi | 0:098463de4c5d | 39 | tmp |= (mode & 0x3) << 3; |
group-onsemi | 0:098463de4c5d | 40 | |
group-onsemi | 0:098463de4c5d | 41 | // drain |
group-onsemi | 0:098463de4c5d | 42 | tmp &= ~(0x1 << 10); |
group-onsemi | 0:098463de4c5d | 43 | tmp |= drain << 10; |
group-onsemi | 0:098463de4c5d | 44 | |
group-onsemi | 0:098463de4c5d | 45 | *reg = tmp; |
group-onsemi | 0:098463de4c5d | 46 | } |