ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

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group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #include <string.h>
group-onsemi 0:098463de4c5d 35 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 36 #include "cmsis.h"
group-onsemi 0:098463de4c5d 37 #include "spi_api.h"
group-onsemi 0:098463de4c5d 38 #include "spi_multi_api.h"
group-onsemi 0:098463de4c5d 39 #include "pinmap.h"
group-onsemi 0:098463de4c5d 40 #include "ioman_regs.h"
group-onsemi 0:098463de4c5d 41 #include "clkman_regs.h"
group-onsemi 0:098463de4c5d 42 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 #define DEFAULT_CHAR 8
group-onsemi 0:098463de4c5d 45 #define DEFAULT_MODE 0
group-onsemi 0:098463de4c5d 46 #define DEFAULT_FREQ 1000000
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 // BYTE maximums for FIFO and page writes; FIFO depth spec'd as 16-bit words
group-onsemi 0:098463de4c5d 49 #define SPI_MAX_BYTE_LEN (MXC_CFG_SPI_FIFO_DEPTH * 2)
group-onsemi 0:098463de4c5d 50 #define SPI_MAX_PAGE_LEN (MXC_CFG_SPI_FIFO_DEPTH * 2)
group-onsemi 0:098463de4c5d 51
group-onsemi 0:098463de4c5d 52 #if DEVICE_SPI_ASYNCH
group-onsemi 0:098463de4c5d 53 // Instance references for async transactions
group-onsemi 0:098463de4c5d 54 static struct spi_s *state[MXC_CFG_SPI_INSTANCES] = {NULL};
group-onsemi 0:098463de4c5d 55 #endif
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 //******************************************************************************
group-onsemi 0:098463de4c5d 58 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
group-onsemi 0:098463de4c5d 59 {
group-onsemi 0:098463de4c5d 60 // Make sure pins are pointing to the same SPI instance
group-onsemi 0:098463de4c5d 61 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
group-onsemi 0:098463de4c5d 62 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
group-onsemi 0:098463de4c5d 63 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
group-onsemi 0:098463de4c5d 64 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
group-onsemi 0:098463de4c5d 65
group-onsemi 0:098463de4c5d 66 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
group-onsemi 0:098463de4c5d 67 SPIName spi_cntl;
group-onsemi 0:098463de4c5d 68
group-onsemi 0:098463de4c5d 69 // Give the application the option to manually control Slave Select
group-onsemi 0:098463de4c5d 70 if ((SPIName)spi_ssel != (SPIName)NC) {
group-onsemi 0:098463de4c5d 71 spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
group-onsemi 0:098463de4c5d 72 // Slave select is currently limited to slave select zero. If others are
group-onsemi 0:098463de4c5d 73 // to be supported a function to map PinName to a value suitable for use
group-onsemi 0:098463de4c5d 74 // in mstr_cfg.slave_sel will be required.
group-onsemi 0:098463de4c5d 75 obj->spi.ssel = 0;
group-onsemi 0:098463de4c5d 76 } else {
group-onsemi 0:098463de4c5d 77 spi_cntl = spi_sclk;
group-onsemi 0:098463de4c5d 78 obj->spi.ssel = -1;
group-onsemi 0:098463de4c5d 79 }
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 SPIName spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
group-onsemi 0:098463de4c5d 82
group-onsemi 0:098463de4c5d 83 MBED_ASSERT((SPIName)spi != (SPIName)NC);
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 // Set the obj pointer to the proper SPI Instance
group-onsemi 0:098463de4c5d 86 obj->spi.spi = (mxc_spi_regs_t*)spi;
group-onsemi 0:098463de4c5d 87
group-onsemi 0:098463de4c5d 88 // Set the SPI index and FIFOs
group-onsemi 0:098463de4c5d 89 obj->spi.index = MXC_SPI_GET_IDX(obj->spi.spi);
group-onsemi 0:098463de4c5d 90 obj->spi.fifo = MXC_SPI_GET_SPI_FIFO(obj->spi.index);
group-onsemi 0:098463de4c5d 91
group-onsemi 0:098463de4c5d 92 // Configure the pins
group-onsemi 0:098463de4c5d 93 pinmap_pinout(mosi, PinMap_SPI_MOSI);
group-onsemi 0:098463de4c5d 94 pinmap_pinout(miso, PinMap_SPI_MISO);
group-onsemi 0:098463de4c5d 95 pinmap_pinout(sclk, PinMap_SPI_SCLK);
group-onsemi 0:098463de4c5d 96 pinmap_pinout(ssel, PinMap_SPI_SSEL);
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98 #if DEVICE_SPI_ASYNCH
group-onsemi 0:098463de4c5d 99 // Configure default page size; size is known to async interface
group-onsemi 0:098463de4c5d 100 obj->spi.spi->mstr_cfg = (obj->spi.spi->mstr_cfg & ~MXC_F_SPI_MSTR_CFG_PAGE_SIZE) | MXC_S_SPI_MSTR_CFG_PAGE_32B;
group-onsemi 0:098463de4c5d 101 #endif
group-onsemi 0:098463de4c5d 102
group-onsemi 0:098463de4c5d 103 // Enable SPI and FIFOs
group-onsemi 0:098463de4c5d 104 obj->spi.spi->gen_ctrl = (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN |
group-onsemi 0:098463de4c5d 105 MXC_F_SPI_GEN_CTRL_TX_FIFO_EN |
group-onsemi 0:098463de4c5d 106 MXC_F_SPI_GEN_CTRL_RX_FIFO_EN );
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 obj->spi.sclk = sclk; // save the sclk PinName in the object as a key for Quad SPI pin mapping lookup
group-onsemi 0:098463de4c5d 109 spi_master_width(obj, 0); // default this for Single SPI communications
group-onsemi 0:098463de4c5d 110 }
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 //******************************************************************************
group-onsemi 0:098463de4c5d 113 void spi_format(spi_t *obj, int bits, int mode, int slave)
group-onsemi 0:098463de4c5d 114 {
group-onsemi 0:098463de4c5d 115 // Check the validity of the inputs
group-onsemi 0:098463de4c5d 116 MBED_ASSERT(((bits >= 1) && (bits <= 32)) && ((mode >= 0) && (mode <= 3)));
group-onsemi 0:098463de4c5d 117
group-onsemi 0:098463de4c5d 118 // Only supports master mode
group-onsemi 0:098463de4c5d 119 MBED_ASSERT(!slave);
group-onsemi 0:098463de4c5d 120
group-onsemi 0:098463de4c5d 121 // Save formatting data
group-onsemi 0:098463de4c5d 122 obj->spi.bits = bits;
group-onsemi 0:098463de4c5d 123
group-onsemi 0:098463de4c5d 124 // Set the mode
group-onsemi 0:098463de4c5d 125 MXC_SET_FIELD(&obj->spi.spi->mstr_cfg, MXC_F_SPI_MSTR_CFG_SPI_MODE, mode << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS);
group-onsemi 0:098463de4c5d 126 }
group-onsemi 0:098463de4c5d 127
group-onsemi 0:098463de4c5d 128 //******************************************************************************
group-onsemi 0:098463de4c5d 129 void spi_frequency(spi_t *obj, int hz)
group-onsemi 0:098463de4c5d 130 {
group-onsemi 0:098463de4c5d 131 // Maximum frequency is half the system frequency
group-onsemi 0:098463de4c5d 132 MBED_ASSERT((unsigned int)hz <= (SystemCoreClock / 2));
group-onsemi 0:098463de4c5d 133 unsigned clocks = ((SystemCoreClock / 2) / hz);
group-onsemi 0:098463de4c5d 134
group-onsemi 0:098463de4c5d 135 // Figure out the divider ratio
group-onsemi 0:098463de4c5d 136 int clk_div = 1;
group-onsemi 0:098463de4c5d 137 while (clk_div < 10) {
group-onsemi 0:098463de4c5d 138 if (clocks < 0x10) {
group-onsemi 0:098463de4c5d 139 break;
group-onsemi 0:098463de4c5d 140 }
group-onsemi 0:098463de4c5d 141 clk_div++;
group-onsemi 0:098463de4c5d 142 clocks = clocks >> 1;
group-onsemi 0:098463de4c5d 143 }
group-onsemi 0:098463de4c5d 144
group-onsemi 0:098463de4c5d 145 // Turn on the SPI clock
group-onsemi 0:098463de4c5d 146 if (obj->spi.index == 0) {
group-onsemi 0:098463de4c5d 147 MXC_CLKMAN->sys_clk_ctrl_11_spi0 = clk_div;
group-onsemi 0:098463de4c5d 148 } else if (obj->spi.index == 1) {
group-onsemi 0:098463de4c5d 149 MXC_CLKMAN->sys_clk_ctrl_12_spi1 = clk_div;
group-onsemi 0:098463de4c5d 150 } else if (obj->spi.index == 2) {
group-onsemi 0:098463de4c5d 151 MXC_CLKMAN->sys_clk_ctrl_13_spi2 = clk_div;
group-onsemi 0:098463de4c5d 152 } else {
group-onsemi 0:098463de4c5d 153 MBED_ASSERT(0);
group-onsemi 0:098463de4c5d 154 }
group-onsemi 0:098463de4c5d 155
group-onsemi 0:098463de4c5d 156 // Set the number of clocks to hold sclk high and low
group-onsemi 0:098463de4c5d 157 MXC_SET_FIELD(&obj->spi.spi->mstr_cfg, (MXC_F_SPI_MSTR_CFG_SCK_HI_CLK | MXC_F_SPI_MSTR_CFG_SCK_LO_CLK),
group-onsemi 0:098463de4c5d 158 ((clocks << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS) | (clocks << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS)));
group-onsemi 0:098463de4c5d 159 }
group-onsemi 0:098463de4c5d 160
group-onsemi 0:098463de4c5d 161 //******************************************************************************
group-onsemi 0:098463de4c5d 162 void spi_master_width(spi_t *obj, SpiWidth width)
group-onsemi 0:098463de4c5d 163 {
group-onsemi 0:098463de4c5d 164 // Save the width to be used in the SPI header
group-onsemi 0:098463de4c5d 165 switch (width) {
group-onsemi 0:098463de4c5d 166 case WidthSingle:
group-onsemi 0:098463de4c5d 167 obj->spi.width = MXC_S_SPI_FIFO_WIDTH_SINGLE;
group-onsemi 0:098463de4c5d 168 break;
group-onsemi 0:098463de4c5d 169 case WidthDual:
group-onsemi 0:098463de4c5d 170 obj->spi.width = MXC_S_SPI_FIFO_WIDTH_DUAL;
group-onsemi 0:098463de4c5d 171 break;
group-onsemi 0:098463de4c5d 172 case WidthQuad:
group-onsemi 0:098463de4c5d 173 obj->spi.width = MXC_S_SPI_FIFO_WIDTH_QUAD;
group-onsemi 0:098463de4c5d 174 // do pin mapping for SDIO[2] and SDIO[3] if Quad SPI is selected
group-onsemi 0:098463de4c5d 175 pinmap_pinout(obj->spi.sclk, PinMap_SPI_QUAD);
group-onsemi 0:098463de4c5d 176 break;
group-onsemi 0:098463de4c5d 177 default:
group-onsemi 0:098463de4c5d 178 MBED_ASSERT(0);
group-onsemi 0:098463de4c5d 179 }
group-onsemi 0:098463de4c5d 180 }
group-onsemi 0:098463de4c5d 181
group-onsemi 0:098463de4c5d 182 //******************************************************************************
group-onsemi 0:098463de4c5d 183 /** Performs a master write or read transaction
group-onsemi 0:098463de4c5d 184 *
group-onsemi 0:098463de4c5d 185 * @param[in] obj The SPI peripheral to use for sending
group-onsemi 0:098463de4c5d 186 * @param[in] value The value to send
group-onsemi 0:098463de4c5d 187 * @param[in] direction Direction of the transaction, TX, RX or both
group-onsemi 0:098463de4c5d 188 * @return Returns the value received during send
group-onsemi 0:098463de4c5d 189 */
group-onsemi 0:098463de4c5d 190 static int spi_master_transaction(spi_t *obj, int value, uint32_t direction)
group-onsemi 0:098463de4c5d 191 {
group-onsemi 0:098463de4c5d 192 int bits;
group-onsemi 0:098463de4c5d 193
group-onsemi 0:098463de4c5d 194 // Create the header
group-onsemi 0:098463de4c5d 195 uint16_t header = (direction | // direction based on SPI object
group-onsemi 0:098463de4c5d 196 MXC_S_SPI_FIFO_UNIT_BITS | // unit size
group-onsemi 0:098463de4c5d 197 ((obj->spi.bits == 32) ? 0 : obj->spi.bits << MXC_F_SPI_FIFO_SIZE_POS) | // Number of units
group-onsemi 0:098463de4c5d 198 obj->spi.width | // I/O width
group-onsemi 0:098463de4c5d 199 ((obj->spi.ssel == -1) ? 0 : 1 << MXC_F_SPI_FIFO_DASS_POS));
group-onsemi 0:098463de4c5d 200
group-onsemi 0:098463de4c5d 201 // Send the message header
group-onsemi 0:098463de4c5d 202 *obj->spi.fifo->trans_16 = header;
group-onsemi 0:098463de4c5d 203
group-onsemi 0:098463de4c5d 204 // Send the data
group-onsemi 0:098463de4c5d 205 if (obj->spi.bits < 17) {
group-onsemi 0:098463de4c5d 206 *obj->spi.fifo->trans_16 = (uint16_t)value;
group-onsemi 0:098463de4c5d 207 } else {
group-onsemi 0:098463de4c5d 208 *obj->spi.fifo->trans_32 = (uint32_t)value;
group-onsemi 0:098463de4c5d 209 }
group-onsemi 0:098463de4c5d 210
group-onsemi 0:098463de4c5d 211 // Get the data
group-onsemi 0:098463de4c5d 212 bits = obj->spi.bits;
group-onsemi 0:098463de4c5d 213 int result = 0;
group-onsemi 0:098463de4c5d 214 int i = 0;
group-onsemi 0:098463de4c5d 215 while (bits > 0) {
group-onsemi 0:098463de4c5d 216 // Wait for data
group-onsemi 0:098463de4c5d 217 while (((obj->spi.spi->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED)
group-onsemi 0:098463de4c5d 218 >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS) < 1);
group-onsemi 0:098463de4c5d 219
group-onsemi 0:098463de4c5d 220 result |= (*obj->spi.fifo->rslts_8 << (i++*8));
group-onsemi 0:098463de4c5d 221 bits-=8;
group-onsemi 0:098463de4c5d 222 }
group-onsemi 0:098463de4c5d 223
group-onsemi 0:098463de4c5d 224 return result;
group-onsemi 0:098463de4c5d 225 }
group-onsemi 0:098463de4c5d 226
group-onsemi 0:098463de4c5d 227 //******************************************************************************
group-onsemi 0:098463de4c5d 228 int spi_master_write(spi_t *obj, int value)
group-onsemi 0:098463de4c5d 229 {
group-onsemi 0:098463de4c5d 230 // set the fifo direction for full duplex, TX and RX simultaneously
group-onsemi 0:098463de4c5d 231 return spi_master_transaction(obj, value, MXC_S_SPI_FIFO_DIR_BOTH);
group-onsemi 0:098463de4c5d 232 }
group-onsemi 0:098463de4c5d 233
group-onsemi 0:098463de4c5d 234 //******************************************************************************
group-onsemi 0:098463de4c5d 235 int spi_master_read(spi_t *obj)
group-onsemi 0:098463de4c5d 236 {
group-onsemi 0:098463de4c5d 237 return spi_master_transaction(obj, 0xFF, MXC_S_SPI_FIFO_DIR_RX);
group-onsemi 0:098463de4c5d 238 }
group-onsemi 0:098463de4c5d 239
group-onsemi 0:098463de4c5d 240 //******************************************************************************
group-onsemi 0:098463de4c5d 241 // spi_busy() is part of the synchronous API, it is not used by the asynchronous API.
group-onsemi 0:098463de4c5d 242 int spi_busy(spi_t *obj)
group-onsemi 0:098463de4c5d 243 {
group-onsemi 0:098463de4c5d 244 return !(obj->spi.spi->intfl & MXC_F_SPI_INTFL_TX_READY);
group-onsemi 0:098463de4c5d 245 }
group-onsemi 0:098463de4c5d 246
group-onsemi 0:098463de4c5d 247 #if DEVICE_SPI_ASYNCH
group-onsemi 0:098463de4c5d 248 //******************************************************************************
group-onsemi 0:098463de4c5d 249 static uint32_t spi_master_read_rxfifo(mxc_spi_regs_t *spim, mxc_spi_fifo_regs_t *fifo, uint8_t *data, uint32_t len)
group-onsemi 0:098463de4c5d 250 {
group-onsemi 0:098463de4c5d 251 uint32_t num = 0;
group-onsemi 0:098463de4c5d 252 uint32_t avail = ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS);
group-onsemi 0:098463de4c5d 253
group-onsemi 0:098463de4c5d 254 // Get data from the RXFIFO
group-onsemi 0:098463de4c5d 255 while (avail && (len - num)) {
group-onsemi 0:098463de4c5d 256 // Save data from the RXFIFO
group-onsemi 0:098463de4c5d 257 if ((avail >= 4) && ((len - num) >= 4)) {
group-onsemi 0:098463de4c5d 258 uint32_t temp = *fifo->rslts_32;
group-onsemi 0:098463de4c5d 259 data[num++] = temp;
group-onsemi 0:098463de4c5d 260 data[num++] = temp >> 8;
group-onsemi 0:098463de4c5d 261 data[num++] = temp >> 16;
group-onsemi 0:098463de4c5d 262 data[num++] = temp >> 24;
group-onsemi 0:098463de4c5d 263 avail -= 4;
group-onsemi 0:098463de4c5d 264 } else if ((avail >= 2) && ((len - num) >= 2)) {
group-onsemi 0:098463de4c5d 265 uint16_t temp = *fifo->rslts_16;
group-onsemi 0:098463de4c5d 266 data[num++] = temp;
group-onsemi 0:098463de4c5d 267 data[num++] = temp >> 8;
group-onsemi 0:098463de4c5d 268 avail -= 2;
group-onsemi 0:098463de4c5d 269 } else {
group-onsemi 0:098463de4c5d 270 data[num++] = *fifo->rslts_8;
group-onsemi 0:098463de4c5d 271 avail--;
group-onsemi 0:098463de4c5d 272 }
group-onsemi 0:098463de4c5d 273
group-onsemi 0:098463de4c5d 274 // Check to see if there is more data in the FIFO
group-onsemi 0:098463de4c5d 275 if (avail == 0) {
group-onsemi 0:098463de4c5d 276 avail = ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS);
group-onsemi 0:098463de4c5d 277 }
group-onsemi 0:098463de4c5d 278 }
group-onsemi 0:098463de4c5d 279
group-onsemi 0:098463de4c5d 280 return num;
group-onsemi 0:098463de4c5d 281 }
group-onsemi 0:098463de4c5d 282
group-onsemi 0:098463de4c5d 283 //******************************************************************************
group-onsemi 0:098463de4c5d 284 static uint32_t spi_master_transfer_handler(spi_t *obj)
group-onsemi 0:098463de4c5d 285 {
group-onsemi 0:098463de4c5d 286 uint8_t read;
group-onsemi 0:098463de4c5d 287 uint8_t write;
group-onsemi 0:098463de4c5d 288 uint16_t header;
group-onsemi 0:098463de4c5d 289 uint32_t pages;
group-onsemi 0:098463de4c5d 290 uint32_t bytes;
group-onsemi 0:098463de4c5d 291 uint32_t inten;
group-onsemi 0:098463de4c5d 292 unsigned remain;
group-onsemi 0:098463de4c5d 293 unsigned bytes_read;
group-onsemi 0:098463de4c5d 294 unsigned head_rem_temp;
group-onsemi 0:098463de4c5d 295 unsigned avail;
group-onsemi 0:098463de4c5d 296 struct spi_s *req = &obj->spi;
group-onsemi 0:098463de4c5d 297 mxc_spi_regs_t *spim = obj->spi.spi;
group-onsemi 0:098463de4c5d 298 mxc_spi_fifo_regs_t *fifo = obj->spi.fifo;
group-onsemi 0:098463de4c5d 299
group-onsemi 0:098463de4c5d 300 inten = 0;
group-onsemi 0:098463de4c5d 301
group-onsemi 0:098463de4c5d 302 // Figure out if we're reading
group-onsemi 0:098463de4c5d 303 read = (req->rx_data != NULL) ? 1 : 0;
group-onsemi 0:098463de4c5d 304
group-onsemi 0:098463de4c5d 305 // Figure out if we're writing
group-onsemi 0:098463de4c5d 306 write = (req->tx_data != NULL) ? 1 : 0;
group-onsemi 0:098463de4c5d 307
group-onsemi 0:098463de4c5d 308 // Read byte from the FIFO if we are reading
group-onsemi 0:098463de4c5d 309 if (read) {
group-onsemi 0:098463de4c5d 310
group-onsemi 0:098463de4c5d 311 // Read all of the data in the RXFIFO, or until we don't need anymore
group-onsemi 0:098463de4c5d 312 bytes_read = spi_master_read_rxfifo(spim, fifo, &req->rx_data[req->read_num], (req->len - req->read_num));
group-onsemi 0:098463de4c5d 313
group-onsemi 0:098463de4c5d 314 req->read_num += bytes_read;
group-onsemi 0:098463de4c5d 315
group-onsemi 0:098463de4c5d 316 // Adjust head_rem if we are only reading
group-onsemi 0:098463de4c5d 317 if (!write && (req->head_rem > 0)) {
group-onsemi 0:098463de4c5d 318 req->head_rem -= bytes_read;
group-onsemi 0:098463de4c5d 319 }
group-onsemi 0:098463de4c5d 320
group-onsemi 0:098463de4c5d 321 // Figure out how many bytes we have left to read
group-onsemi 0:098463de4c5d 322 if (req->head_rem > 0) {
group-onsemi 0:098463de4c5d 323 remain = req->head_rem;
group-onsemi 0:098463de4c5d 324 } else {
group-onsemi 0:098463de4c5d 325 remain = req->len - req->read_num;
group-onsemi 0:098463de4c5d 326 }
group-onsemi 0:098463de4c5d 327
group-onsemi 0:098463de4c5d 328 if (remain) {
group-onsemi 0:098463de4c5d 329
group-onsemi 0:098463de4c5d 330 // Set the RX interrupts
group-onsemi 0:098463de4c5d 331 if (remain > MXC_CFG_SPI_FIFO_DEPTH) {
group-onsemi 0:098463de4c5d 332 spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL) |
group-onsemi 0:098463de4c5d 333 ((MXC_CFG_SPI_FIFO_DEPTH - 2) << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS));
group-onsemi 0:098463de4c5d 334 } else {
group-onsemi 0:098463de4c5d 335 spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL) |
group-onsemi 0:098463de4c5d 336 ((remain - 1) << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS));
group-onsemi 0:098463de4c5d 337 }
group-onsemi 0:098463de4c5d 338
group-onsemi 0:098463de4c5d 339 inten |= MXC_F_SPI_INTEN_RX_FIFO_AF;
group-onsemi 0:098463de4c5d 340 }
group-onsemi 0:098463de4c5d 341 }
group-onsemi 0:098463de4c5d 342
group-onsemi 0:098463de4c5d 343 // Figure out how many bytes we have left to send headers for
group-onsemi 0:098463de4c5d 344 if (write) {
group-onsemi 0:098463de4c5d 345 remain = req->len - req->write_num;
group-onsemi 0:098463de4c5d 346 } else {
group-onsemi 0:098463de4c5d 347 remain = req->len - req->read_num;
group-onsemi 0:098463de4c5d 348 }
group-onsemi 0:098463de4c5d 349
group-onsemi 0:098463de4c5d 350 // See if we need to send a new header
group-onsemi 0:098463de4c5d 351 if ((req->head_rem <= 0) && remain) {
group-onsemi 0:098463de4c5d 352
group-onsemi 0:098463de4c5d 353 // Set the transaction configuration in the header
group-onsemi 0:098463de4c5d 354 header = ((write | (read << 1)) << MXC_F_SPI_FIFO_DIR_POS) | (req->width << MXC_F_SPI_FIFO_WIDTH_POS);
group-onsemi 0:098463de4c5d 355
group-onsemi 0:098463de4c5d 356 if (remain >= SPI_MAX_BYTE_LEN) {
group-onsemi 0:098463de4c5d 357
group-onsemi 0:098463de4c5d 358 // Send a 32 byte header
group-onsemi 0:098463de4c5d 359 if (remain == SPI_MAX_BYTE_LEN) {
group-onsemi 0:098463de4c5d 360
group-onsemi 0:098463de4c5d 361 header |= (MXC_S_SPI_FIFO_UNIT_BYTES | MXC_F_SPI_FIFO_DASS);
group-onsemi 0:098463de4c5d 362
group-onsemi 0:098463de4c5d 363 // Save the number of bytes we need to write to the FIFO
group-onsemi 0:098463de4c5d 364 bytes = SPI_MAX_BYTE_LEN;
group-onsemi 0:098463de4c5d 365
group-onsemi 0:098463de4c5d 366 } else {
group-onsemi 0:098463de4c5d 367 // Send in increments of 32 byte pages
group-onsemi 0:098463de4c5d 368 header |= MXC_S_SPI_FIFO_UNIT_PAGES;
group-onsemi 0:098463de4c5d 369 pages = remain / SPI_MAX_PAGE_LEN;
group-onsemi 0:098463de4c5d 370
group-onsemi 0:098463de4c5d 371 if (pages >= 32) {
group-onsemi 0:098463de4c5d 372 // 0 maps to 32 in the header
group-onsemi 0:098463de4c5d 373 bytes = 32 * SPI_MAX_PAGE_LEN;
group-onsemi 0:098463de4c5d 374 } else {
group-onsemi 0:098463de4c5d 375 header |= (pages << MXC_F_SPI_FIFO_SIZE_POS);
group-onsemi 0:098463de4c5d 376 bytes = pages * SPI_MAX_PAGE_LEN;
group-onsemi 0:098463de4c5d 377 }
group-onsemi 0:098463de4c5d 378
group-onsemi 0:098463de4c5d 379 // Check if this is the last header we will send
group-onsemi 0:098463de4c5d 380 if ((remain - bytes) == 0) {
group-onsemi 0:098463de4c5d 381 header |= MXC_F_SPI_FIFO_DASS;
group-onsemi 0:098463de4c5d 382 }
group-onsemi 0:098463de4c5d 383 }
group-onsemi 0:098463de4c5d 384
group-onsemi 0:098463de4c5d 385 fifo->trans_16[0] = header;
group-onsemi 0:098463de4c5d 386
group-onsemi 0:098463de4c5d 387 // Save the number of bytes we need to write to the FIFO
group-onsemi 0:098463de4c5d 388 req->head_rem = bytes;
group-onsemi 0:098463de4c5d 389
group-onsemi 0:098463de4c5d 390 } else {
group-onsemi 0:098463de4c5d 391 // Send final header with the number of bytes remaining and de-assert the SS at the end of the transaction
group-onsemi 0:098463de4c5d 392 header |= (MXC_S_SPI_FIFO_UNIT_BYTES | (remain << MXC_F_SPI_FIFO_SIZE_POS) | MXC_F_SPI_FIFO_DASS);
group-onsemi 0:098463de4c5d 393 fifo->trans_16[0] = header;
group-onsemi 0:098463de4c5d 394 req->head_rem = remain;
group-onsemi 0:098463de4c5d 395 }
group-onsemi 0:098463de4c5d 396 }
group-onsemi 0:098463de4c5d 397
group-onsemi 0:098463de4c5d 398 // Put data into the FIFO if we are writing
group-onsemi 0:098463de4c5d 399 remain = req->len - req->write_num;
group-onsemi 0:098463de4c5d 400 head_rem_temp = req->head_rem;
group-onsemi 0:098463de4c5d 401 if (write && head_rem_temp) {
group-onsemi 0:098463de4c5d 402
group-onsemi 0:098463de4c5d 403 // Fill the FIFO
group-onsemi 0:098463de4c5d 404 avail = (MXC_CFG_SPI_FIFO_DEPTH - ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS));
group-onsemi 0:098463de4c5d 405
group-onsemi 0:098463de4c5d 406 // Use memcpy for everything except the last byte in odd length transactions
group-onsemi 0:098463de4c5d 407 while ((avail >= 2) && (head_rem_temp >= 2)) {
group-onsemi 0:098463de4c5d 408
group-onsemi 0:098463de4c5d 409 unsigned length;
group-onsemi 0:098463de4c5d 410 if (head_rem_temp < avail) {
group-onsemi 0:098463de4c5d 411 length = head_rem_temp;
group-onsemi 0:098463de4c5d 412 } else {
group-onsemi 0:098463de4c5d 413 length = avail;
group-onsemi 0:098463de4c5d 414 }
group-onsemi 0:098463de4c5d 415
group-onsemi 0:098463de4c5d 416 // Only memcpy even numbers
group-onsemi 0:098463de4c5d 417 length = ((length / 2) * 2);
group-onsemi 0:098463de4c5d 418
group-onsemi 0:098463de4c5d 419 memcpy((void*)fifo->trans_32, &(req->tx_data[req->write_num]), length);
group-onsemi 0:098463de4c5d 420
group-onsemi 0:098463de4c5d 421 head_rem_temp -= length;
group-onsemi 0:098463de4c5d 422 req->write_num += length;
group-onsemi 0:098463de4c5d 423
group-onsemi 0:098463de4c5d 424 avail = (MXC_CFG_SPI_FIFO_DEPTH - ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS));
group-onsemi 0:098463de4c5d 425 }
group-onsemi 0:098463de4c5d 426
group-onsemi 0:098463de4c5d 427 // Copy the last byte and pad with 0xF0 to not get confused as header
group-onsemi 0:098463de4c5d 428 if ((avail >= 1) && (head_rem_temp == 1)) {
group-onsemi 0:098463de4c5d 429
group-onsemi 0:098463de4c5d 430 // Write the last byte
group-onsemi 0:098463de4c5d 431 fifo->trans_16[0] = (0xF000 | req->tx_data[req->write_num]);
group-onsemi 0:098463de4c5d 432
group-onsemi 0:098463de4c5d 433 avail -= 1;
group-onsemi 0:098463de4c5d 434 req->write_num += 1;
group-onsemi 0:098463de4c5d 435 head_rem_temp -= 1;
group-onsemi 0:098463de4c5d 436 }
group-onsemi 0:098463de4c5d 437
group-onsemi 0:098463de4c5d 438 req->head_rem = head_rem_temp;
group-onsemi 0:098463de4c5d 439 remain = req->len - req->write_num;
group-onsemi 0:098463de4c5d 440
group-onsemi 0:098463de4c5d 441 // Set the TX interrupts
group-onsemi 0:098463de4c5d 442 if (remain) {
group-onsemi 0:098463de4c5d 443
group-onsemi 0:098463de4c5d 444 // Set the TX FIFO almost empty interrupt if we have to refill
group-onsemi 0:098463de4c5d 445 spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL) |
group-onsemi 0:098463de4c5d 446 ((MXC_CFG_SPI_FIFO_DEPTH - 2) << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS));
group-onsemi 0:098463de4c5d 447
group-onsemi 0:098463de4c5d 448 inten |= MXC_F_SPI_INTEN_TX_FIFO_AE;
group-onsemi 0:098463de4c5d 449 }
group-onsemi 0:098463de4c5d 450 }
group-onsemi 0:098463de4c5d 451
group-onsemi 0:098463de4c5d 452 // Check to see if we've finished reading and writing
group-onsemi 0:098463de4c5d 453 if (((read && (req->read_num == req->len)) || !read) &&
group-onsemi 0:098463de4c5d 454 ((req->write_num == req->len) || !write)) {
group-onsemi 0:098463de4c5d 455
group-onsemi 0:098463de4c5d 456 // Disable interrupts
group-onsemi 0:098463de4c5d 457 spim->inten = 0;
group-onsemi 0:098463de4c5d 458 }
group-onsemi 0:098463de4c5d 459
group-onsemi 0:098463de4c5d 460 // Enable the SPIM interrupts
group-onsemi 0:098463de4c5d 461 return inten;
group-onsemi 0:098463de4c5d 462 }
group-onsemi 0:098463de4c5d 463
group-onsemi 0:098463de4c5d 464 //******************************************************************************
group-onsemi 0:098463de4c5d 465 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
group-onsemi 0:098463de4c5d 466 {
group-onsemi 0:098463de4c5d 467 MBED_ASSERT(tx_length == rx_length);
group-onsemi 0:098463de4c5d 468 MBED_ASSERT(bit_width == obj->spi.bits);
group-onsemi 0:098463de4c5d 469
group-onsemi 0:098463de4c5d 470 // Save object reference for callback
group-onsemi 0:098463de4c5d 471 state[obj->spi.index] = &obj->spi;
group-onsemi 0:098463de4c5d 472
group-onsemi 0:098463de4c5d 473 // Initialize request info
group-onsemi 0:098463de4c5d 474 obj->spi.tx_data = tx;
group-onsemi 0:098463de4c5d 475 obj->spi.rx_data = rx;
group-onsemi 0:098463de4c5d 476 obj->spi.len = tx_length;
group-onsemi 0:098463de4c5d 477 obj->spi.callback = (void(*)())handler;
group-onsemi 0:098463de4c5d 478 obj->spi.event = event;
group-onsemi 0:098463de4c5d 479 // Clear transfer state
group-onsemi 0:098463de4c5d 480 obj->spi.read_num = 0;
group-onsemi 0:098463de4c5d 481 obj->spi.write_num = 0;
group-onsemi 0:098463de4c5d 482 obj->spi.head_rem = 0;
group-onsemi 0:098463de4c5d 483
group-onsemi 0:098463de4c5d 484 NVIC_EnableIRQ(MXC_SPI_GET_IRQ(obj->spi.index));
group-onsemi 0:098463de4c5d 485
group-onsemi 0:098463de4c5d 486 obj->spi.spi->inten = spi_master_transfer_handler(obj);
group-onsemi 0:098463de4c5d 487 }
group-onsemi 0:098463de4c5d 488
group-onsemi 0:098463de4c5d 489 //******************************************************************************
group-onsemi 0:098463de4c5d 490 uint32_t spi_irq_handler_asynch(spi_t *obj)
group-onsemi 0:098463de4c5d 491 {
group-onsemi 0:098463de4c5d 492 mxc_spi_regs_t *spim = obj->spi.spi;
group-onsemi 0:098463de4c5d 493 uint32_t flags;
group-onsemi 0:098463de4c5d 494
group-onsemi 0:098463de4c5d 495 // Clear the interrupt flags
group-onsemi 0:098463de4c5d 496 spim->inten = 0;
group-onsemi 0:098463de4c5d 497 flags = spim->intfl;
group-onsemi 0:098463de4c5d 498 spim->intfl = flags;
group-onsemi 0:098463de4c5d 499
group-onsemi 0:098463de4c5d 500 // Figure out if this SPIM has an active request
group-onsemi 0:098463de4c5d 501 if (flags) {
group-onsemi 0:098463de4c5d 502 if ((spim->inten = spi_master_transfer_handler(obj)) != 0) {
group-onsemi 0:098463de4c5d 503 return 0;
group-onsemi 0:098463de4c5d 504 }
group-onsemi 0:098463de4c5d 505 }
group-onsemi 0:098463de4c5d 506
group-onsemi 0:098463de4c5d 507 state[obj->spi.index] = NULL;
group-onsemi 0:098463de4c5d 508
group-onsemi 0:098463de4c5d 509 return SPI_EVENT_COMPLETE;
group-onsemi 0:098463de4c5d 510 }
group-onsemi 0:098463de4c5d 511
group-onsemi 0:098463de4c5d 512 //******************************************************************************
group-onsemi 0:098463de4c5d 513 uint8_t spi_active(spi_t *obj)
group-onsemi 0:098463de4c5d 514 {
group-onsemi 0:098463de4c5d 515 mxc_spi_regs_t *spim = obj->spi.spi;
group-onsemi 0:098463de4c5d 516
group-onsemi 0:098463de4c5d 517 // Check to see if there are any ongoing transactions
group-onsemi 0:098463de4c5d 518 if ((state[obj->spi.index] == NULL) &&
group-onsemi 0:098463de4c5d 519 !(spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED)) {
group-onsemi 0:098463de4c5d 520 return 0;
group-onsemi 0:098463de4c5d 521 }
group-onsemi 0:098463de4c5d 522
group-onsemi 0:098463de4c5d 523 return 1;
group-onsemi 0:098463de4c5d 524 }
group-onsemi 0:098463de4c5d 525
group-onsemi 0:098463de4c5d 526 //******************************************************************************
group-onsemi 0:098463de4c5d 527 void spi_abort_asynch(spi_t *obj)
group-onsemi 0:098463de4c5d 528 {
group-onsemi 0:098463de4c5d 529 mxc_spi_regs_t *spim = obj->spi.spi;
group-onsemi 0:098463de4c5d 530
group-onsemi 0:098463de4c5d 531 // Disable interrupts, clear the flags
group-onsemi 0:098463de4c5d 532 spim->inten = 0;
group-onsemi 0:098463de4c5d 533 spim->intfl = spim->intfl;
group-onsemi 0:098463de4c5d 534
group-onsemi 0:098463de4c5d 535 // Reset the SPIM to cancel the on ongoing transaction
group-onsemi 0:098463de4c5d 536 spim->gen_ctrl &= ~(MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN);
group-onsemi 0:098463de4c5d 537 spim->gen_ctrl |= (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN);
group-onsemi 0:098463de4c5d 538
group-onsemi 0:098463de4c5d 539 state[obj->spi.index] = NULL;
group-onsemi 0:098463de4c5d 540 }
group-onsemi 0:098463de4c5d 541
group-onsemi 0:098463de4c5d 542 //******************************************************************************
group-onsemi 0:098463de4c5d 543 static void SPI_IRQHandler(int spim_num)
group-onsemi 0:098463de4c5d 544 {
group-onsemi 0:098463de4c5d 545 if (state[spim_num] != NULL) {
group-onsemi 0:098463de4c5d 546 if (state[spim_num]->callback != NULL) {
group-onsemi 0:098463de4c5d 547 state[spim_num]->callback();
group-onsemi 0:098463de4c5d 548 return;
group-onsemi 0:098463de4c5d 549 }
group-onsemi 0:098463de4c5d 550 }
group-onsemi 0:098463de4c5d 551 mxc_spi_regs_t *spim = MXC_SPI_GET_SPI(spim_num);
group-onsemi 0:098463de4c5d 552 spim->inten = 0;
group-onsemi 0:098463de4c5d 553 }
group-onsemi 0:098463de4c5d 554
group-onsemi 0:098463de4c5d 555 //******************************************************************************
group-onsemi 0:098463de4c5d 556 void SPI0_IRQHandler(void) { SPI_IRQHandler(0); }
group-onsemi 0:098463de4c5d 557 void SPI1_IRQHandler(void) { SPI_IRQHandler(1); }
group-onsemi 0:098463de4c5d 558 void SPI2_IRQHandler(void) { SPI_IRQHandler(2); }
group-onsemi 0:098463de4c5d 559
group-onsemi 0:098463de4c5d 560 #endif