ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32620/serial_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #include <string.h>
group-onsemi 0:098463de4c5d 35 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 36 #include "cmsis.h"
group-onsemi 0:098463de4c5d 37 #include "serial_api.h"
group-onsemi 0:098463de4c5d 38 #include "uart_regs.h"
group-onsemi 0:098463de4c5d 39 #include "ioman_regs.h"
group-onsemi 0:098463de4c5d 40 #include "gpio_api.h"
group-onsemi 0:098463de4c5d 41 #include "clkman_regs.h"
group-onsemi 0:098463de4c5d 42 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 #define DEFAULT_BAUD 9600
group-onsemi 0:098463de4c5d 45 #define DEFAULT_STOP 1
group-onsemi 0:098463de4c5d 46 #define DEFAULT_PARITY ParityNone
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 #define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAMING_ERR | \
group-onsemi 0:098463de4c5d 49 MXC_F_UART_INTFL_RX_PARITY_ERR | \
group-onsemi 0:098463de4c5d 50 MXC_F_UART_INTFL_RX_FIFO_OVERFLOW)
group-onsemi 0:098463de4c5d 51
group-onsemi 0:098463de4c5d 52 // Variables for managing the stdio UART
group-onsemi 0:098463de4c5d 53 int stdio_uart_inited;
group-onsemi 0:098463de4c5d 54 serial_t stdio_uart;
group-onsemi 0:098463de4c5d 55
group-onsemi 0:098463de4c5d 56 // Variables for interrupt driven
group-onsemi 0:098463de4c5d 57 static uart_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 58 static uint32_t serial_irq_ids[MXC_CFG_UART_INSTANCES];
group-onsemi 0:098463de4c5d 59
group-onsemi 0:098463de4c5d 60 //******************************************************************************
group-onsemi 0:098463de4c5d 61 void serial_init(serial_t *obj, PinName tx, PinName rx)
group-onsemi 0:098463de4c5d 62 {
group-onsemi 0:098463de4c5d 63 // Determine which uart is associated with each pin
group-onsemi 0:098463de4c5d 64 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 65 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
group-onsemi 0:098463de4c5d 66 UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
group-onsemi 0:098463de4c5d 67
group-onsemi 0:098463de4c5d 68 // Make sure that both pins are pointing to the same uart
group-onsemi 0:098463de4c5d 69 MBED_ASSERT(uart != (UARTName)NC);
group-onsemi 0:098463de4c5d 70
group-onsemi 0:098463de4c5d 71 // Ensure that the UART clock is enabled
group-onsemi 0:098463de4c5d 72 switch (uart) {
group-onsemi 0:098463de4c5d 73 case UART_0:
group-onsemi 0:098463de4c5d 74 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER;
group-onsemi 0:098463de4c5d 75 break;
group-onsemi 0:098463de4c5d 76 case UART_1:
group-onsemi 0:098463de4c5d 77 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER;
group-onsemi 0:098463de4c5d 78 break;
group-onsemi 0:098463de4c5d 79 case UART_2:
group-onsemi 0:098463de4c5d 80 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER;
group-onsemi 0:098463de4c5d 81 break;
group-onsemi 0:098463de4c5d 82 case UART_3:
group-onsemi 0:098463de4c5d 83 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER;
group-onsemi 0:098463de4c5d 84 break;
group-onsemi 0:098463de4c5d 85 default:
group-onsemi 0:098463de4c5d 86 break;
group-onsemi 0:098463de4c5d 87 }
group-onsemi 0:098463de4c5d 88
group-onsemi 0:098463de4c5d 89 // Ensure that the UART clock is enabled
group-onsemi 0:098463de4c5d 90 // But don't override the scaler
group-onsemi 0:098463de4c5d 91 //
group-onsemi 0:098463de4c5d 92 // To support the most common baud rates, 9600 and 115200, we need to
group-onsemi 0:098463de4c5d 93 // scale down the uart input clock.
group-onsemi 0:098463de4c5d 94 if (!(MXC_CLKMAN->sys_clk_ctrl_8_uart & MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE)) {
group-onsemi 0:098463de4c5d 95
group-onsemi 0:098463de4c5d 96 switch (SystemCoreClock) {
group-onsemi 0:098463de4c5d 97 case RO_FREQ:
group-onsemi 0:098463de4c5d 98 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
group-onsemi 0:098463de4c5d 99 break;
group-onsemi 0:098463de4c5d 100 case (RO_FREQ / 2):
group-onsemi 0:098463de4c5d 101 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_2;
group-onsemi 0:098463de4c5d 102 break;
group-onsemi 0:098463de4c5d 103 default:
group-onsemi 0:098463de4c5d 104 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
group-onsemi 0:098463de4c5d 105 break;
group-onsemi 0:098463de4c5d 106 }
group-onsemi 0:098463de4c5d 107 }
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109 // Set the obj pointer to the proper uart
group-onsemi 0:098463de4c5d 110 obj->uart = (mxc_uart_regs_t*)uart;
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 // Set the uart index
group-onsemi 0:098463de4c5d 113 obj->index = MXC_UART_GET_IDX(obj->uart);
group-onsemi 0:098463de4c5d 114 obj->fifo = (mxc_uart_fifo_regs_t*)MXC_UART_GET_BASE_FIFO(obj->index);
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 // Configure the pins
group-onsemi 0:098463de4c5d 117 pinmap_pinout(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 118 pinmap_pinout(rx, PinMap_UART_RX);
group-onsemi 0:098463de4c5d 119
group-onsemi 0:098463de4c5d 120 // Flush the RX and TX FIFOs, clear the settings
group-onsemi 0:098463de4c5d 121 obj->uart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
group-onsemi 0:098463de4c5d 122 obj->uart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
group-onsemi 0:098463de4c5d 123
group-onsemi 0:098463de4c5d 124 // Disable interrupts
group-onsemi 0:098463de4c5d 125 obj->uart->inten = 0;
group-onsemi 0:098463de4c5d 126 obj->uart->intfl = obj->uart->intfl;
group-onsemi 0:098463de4c5d 127
group-onsemi 0:098463de4c5d 128 // Configure to default settings
group-onsemi 0:098463de4c5d 129 serial_baud(obj, DEFAULT_BAUD);
group-onsemi 0:098463de4c5d 130 serial_format(obj, 8, ParityNone, 1);
group-onsemi 0:098463de4c5d 131
group-onsemi 0:098463de4c5d 132 // Manage stdio UART
group-onsemi 0:098463de4c5d 133 if (uart == STDIO_UART) {
group-onsemi 0:098463de4c5d 134 stdio_uart_inited = 1;
group-onsemi 0:098463de4c5d 135 memcpy(&stdio_uart, obj, sizeof(serial_t));
group-onsemi 0:098463de4c5d 136 }
group-onsemi 0:098463de4c5d 137
group-onsemi 0:098463de4c5d 138 // Enable UART
group-onsemi 0:098463de4c5d 139 obj->uart->ctrl |= MXC_F_UART_CTRL_UART_EN;
group-onsemi 0:098463de4c5d 140 }
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142 //******************************************************************************
group-onsemi 0:098463de4c5d 143 void serial_baud(serial_t *obj, int baudrate)
group-onsemi 0:098463de4c5d 144 {
group-onsemi 0:098463de4c5d 145 uint32_t baud_setting = 0;
group-onsemi 0:098463de4c5d 146
group-onsemi 0:098463de4c5d 147 MBED_ASSERT(MXC_CLKMAN->sys_clk_ctrl_8_uart > MXC_S_CLKMAN_CLK_SCALE_DISABLED);
group-onsemi 0:098463de4c5d 148
group-onsemi 0:098463de4c5d 149 // Calculate the integer and decimal portions
group-onsemi 0:098463de4c5d 150 baud_setting = SystemCoreClock / (1<<(MXC_CLKMAN->sys_clk_ctrl_8_uart-1));
group-onsemi 0:098463de4c5d 151 baud_setting = baud_setting / (baudrate * 16);
group-onsemi 0:098463de4c5d 152
group-onsemi 0:098463de4c5d 153 // If the result doesn't fit in the register
group-onsemi 0:098463de4c5d 154 MBED_ASSERT(baud_setting <= UINT8_MAX);
group-onsemi 0:098463de4c5d 155
group-onsemi 0:098463de4c5d 156 obj->uart->baud = baud_setting;
group-onsemi 0:098463de4c5d 157 }
group-onsemi 0:098463de4c5d 158
group-onsemi 0:098463de4c5d 159 //******************************************************************************
group-onsemi 0:098463de4c5d 160 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
group-onsemi 0:098463de4c5d 161 {
group-onsemi 0:098463de4c5d 162 // Check the validity of the inputs
group-onsemi 0:098463de4c5d 163 MBED_ASSERT((data_bits > 4) && (data_bits < 9));
group-onsemi 0:098463de4c5d 164 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) ||
group-onsemi 0:098463de4c5d 165 (parity == ParityEven) || (parity == ParityForced1) ||
group-onsemi 0:098463de4c5d 166 (parity == ParityForced0));
group-onsemi 0:098463de4c5d 167 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
group-onsemi 0:098463de4c5d 168
group-onsemi 0:098463de4c5d 169 // Adjust the stop and data bits
group-onsemi 0:098463de4c5d 170 stop_bits -= 1;
group-onsemi 0:098463de4c5d 171 data_bits -= 5;
group-onsemi 0:098463de4c5d 172
group-onsemi 0:098463de4c5d 173 // Adjust the parity setting
group-onsemi 0:098463de4c5d 174 int mode = 0;
group-onsemi 0:098463de4c5d 175 switch (parity) {
group-onsemi 0:098463de4c5d 176 case ParityNone:
group-onsemi 0:098463de4c5d 177 mode = 0;
group-onsemi 0:098463de4c5d 178 break;
group-onsemi 0:098463de4c5d 179 case ParityOdd :
group-onsemi 0:098463de4c5d 180 mode = 1;
group-onsemi 0:098463de4c5d 181 break;
group-onsemi 0:098463de4c5d 182 case ParityEven:
group-onsemi 0:098463de4c5d 183 mode = 2;
group-onsemi 0:098463de4c5d 184 break;
group-onsemi 0:098463de4c5d 185 case ParityForced1:
group-onsemi 0:098463de4c5d 186 // Hardware does not support forced parity
group-onsemi 0:098463de4c5d 187 MBED_ASSERT(0);
group-onsemi 0:098463de4c5d 188 break;
group-onsemi 0:098463de4c5d 189 case ParityForced0:
group-onsemi 0:098463de4c5d 190 // Hardware does not support forced parity
group-onsemi 0:098463de4c5d 191 MBED_ASSERT(0);
group-onsemi 0:098463de4c5d 192 break;
group-onsemi 0:098463de4c5d 193 default:
group-onsemi 0:098463de4c5d 194 mode = 0;
group-onsemi 0:098463de4c5d 195 break;
group-onsemi 0:098463de4c5d 196 }
group-onsemi 0:098463de4c5d 197
group-onsemi 0:098463de4c5d 198 int temp = obj->uart->ctrl;
group-onsemi 0:098463de4c5d 199 temp &= ~(MXC_F_UART_CTRL_DATA_SIZE | MXC_F_UART_CTRL_EXTRA_STOP | MXC_F_UART_CTRL_PARITY);
group-onsemi 0:098463de4c5d 200 temp |= (data_bits << MXC_F_UART_CTRL_DATA_SIZE_POS);
group-onsemi 0:098463de4c5d 201 temp |= (stop_bits << MXC_F_UART_CTRL_EXTRA_STOP_POS);
group-onsemi 0:098463de4c5d 202 temp |= (mode << MXC_F_UART_CTRL_PARITY_POS);
group-onsemi 0:098463de4c5d 203 obj->uart->ctrl = temp;
group-onsemi 0:098463de4c5d 204 }
group-onsemi 0:098463de4c5d 205
group-onsemi 0:098463de4c5d 206 //******************************************************************************
group-onsemi 0:098463de4c5d 207 void uart_handler(mxc_uart_regs_t* uart, int id)
group-onsemi 0:098463de4c5d 208 {
group-onsemi 0:098463de4c5d 209 // Check for errors or RX Threshold
group-onsemi 0:098463de4c5d 210 if (uart->intfl & (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS)) {
group-onsemi 0:098463de4c5d 211 if (serial_irq_ids[id]) {
group-onsemi 0:098463de4c5d 212 irq_handler(serial_irq_ids[id], RxIrq);
group-onsemi 0:098463de4c5d 213 }
group-onsemi 0:098463de4c5d 214 uart->intfl = (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
group-onsemi 0:098463de4c5d 215 }
group-onsemi 0:098463de4c5d 216
group-onsemi 0:098463de4c5d 217 // Check for TX Threshold
group-onsemi 0:098463de4c5d 218 if (uart->intfl & MXC_F_UART_INTFL_TX_FIFO_AE) {
group-onsemi 0:098463de4c5d 219 if (serial_irq_ids[id]) {
group-onsemi 0:098463de4c5d 220 irq_handler(serial_irq_ids[id], TxIrq);
group-onsemi 0:098463de4c5d 221 }
group-onsemi 0:098463de4c5d 222 uart->intfl = MXC_F_UART_INTFL_TX_FIFO_AE;
group-onsemi 0:098463de4c5d 223 }
group-onsemi 0:098463de4c5d 224 }
group-onsemi 0:098463de4c5d 225
group-onsemi 0:098463de4c5d 226 void uart0_handler(void) { uart_handler(MXC_UART0, 0); }
group-onsemi 0:098463de4c5d 227 void uart1_handler(void) { uart_handler(MXC_UART1, 1); }
group-onsemi 0:098463de4c5d 228 void uart2_handler(void) { uart_handler(MXC_UART2, 2); }
group-onsemi 0:098463de4c5d 229 void uart3_handler(void) { uart_handler(MXC_UART3, 3); }
group-onsemi 0:098463de4c5d 230
group-onsemi 0:098463de4c5d 231 //******************************************************************************
group-onsemi 0:098463de4c5d 232 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
group-onsemi 0:098463de4c5d 233 {
group-onsemi 0:098463de4c5d 234 irq_handler = handler;
group-onsemi 0:098463de4c5d 235 serial_irq_ids[obj->index] = id;
group-onsemi 0:098463de4c5d 236 }
group-onsemi 0:098463de4c5d 237
group-onsemi 0:098463de4c5d 238 //******************************************************************************
group-onsemi 0:098463de4c5d 239 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
group-onsemi 0:098463de4c5d 240 {
group-onsemi 0:098463de4c5d 241 switch (obj->index) {
group-onsemi 0:098463de4c5d 242 case 0:
group-onsemi 0:098463de4c5d 243 NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler);
group-onsemi 0:098463de4c5d 244 NVIC_EnableIRQ(UART0_IRQn);
group-onsemi 0:098463de4c5d 245 break;
group-onsemi 0:098463de4c5d 246 case 1:
group-onsemi 0:098463de4c5d 247 NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler);
group-onsemi 0:098463de4c5d 248 NVIC_EnableIRQ(UART1_IRQn);
group-onsemi 0:098463de4c5d 249 break;
group-onsemi 0:098463de4c5d 250 case 2:
group-onsemi 0:098463de4c5d 251 NVIC_SetVector(UART2_IRQn, (uint32_t)uart2_handler);
group-onsemi 0:098463de4c5d 252 NVIC_EnableIRQ(UART2_IRQn);
group-onsemi 0:098463de4c5d 253 break;
group-onsemi 0:098463de4c5d 254 case 3:
group-onsemi 0:098463de4c5d 255 NVIC_SetVector(UART3_IRQn, (uint32_t)uart3_handler);
group-onsemi 0:098463de4c5d 256 NVIC_EnableIRQ(UART3_IRQn);
group-onsemi 0:098463de4c5d 257 break;
group-onsemi 0:098463de4c5d 258 default:
group-onsemi 0:098463de4c5d 259 MBED_ASSERT(0);
group-onsemi 0:098463de4c5d 260 }
group-onsemi 0:098463de4c5d 261
group-onsemi 0:098463de4c5d 262 if (irq == RxIrq) {
group-onsemi 0:098463de4c5d 263 // Enable RX FIFO Threshold Interrupt
group-onsemi 0:098463de4c5d 264 if (enable) {
group-onsemi 0:098463de4c5d 265 // Clear pending interrupts
group-onsemi 0:098463de4c5d 266 obj->uart->intfl = obj->uart->intfl;
group-onsemi 0:098463de4c5d 267 obj->uart->inten |= (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
group-onsemi 0:098463de4c5d 268 } else {
group-onsemi 0:098463de4c5d 269 // Clear pending interrupts
group-onsemi 0:098463de4c5d 270 obj->uart->intfl = obj->uart->intfl;
group-onsemi 0:098463de4c5d 271 obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
group-onsemi 0:098463de4c5d 272 }
group-onsemi 0:098463de4c5d 273
group-onsemi 0:098463de4c5d 274 } else if (irq == TxIrq) {
group-onsemi 0:098463de4c5d 275 // Set TX Almost Empty level to interrupt when empty
group-onsemi 0:098463de4c5d 276 MXC_SET_FIELD(&obj->uart->tx_fifo_ctrl, MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL,
group-onsemi 0:098463de4c5d 277 (MXC_UART_FIFO_DEPTH - 1) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS);
group-onsemi 0:098463de4c5d 278
group-onsemi 0:098463de4c5d 279 // Enable TX Almost Empty Interrupt
group-onsemi 0:098463de4c5d 280 if (enable) {
group-onsemi 0:098463de4c5d 281 // Clear pending interrupts
group-onsemi 0:098463de4c5d 282 obj->uart->intfl = obj->uart->intfl;
group-onsemi 0:098463de4c5d 283 obj->uart->inten |= MXC_F_UART_INTFL_TX_FIFO_AE;
group-onsemi 0:098463de4c5d 284 } else {
group-onsemi 0:098463de4c5d 285 // Clear pending interrupts
group-onsemi 0:098463de4c5d 286 obj->uart->intfl = obj->uart->intfl;
group-onsemi 0:098463de4c5d 287 obj->uart->inten &= ~MXC_F_UART_INTFL_TX_FIFO_AE;
group-onsemi 0:098463de4c5d 288 }
group-onsemi 0:098463de4c5d 289
group-onsemi 0:098463de4c5d 290 } else {
group-onsemi 0:098463de4c5d 291 MBED_ASSERT(0);
group-onsemi 0:098463de4c5d 292 }
group-onsemi 0:098463de4c5d 293 }
group-onsemi 0:098463de4c5d 294
group-onsemi 0:098463de4c5d 295
group-onsemi 0:098463de4c5d 296 //******************************************************************************
group-onsemi 0:098463de4c5d 297 int serial_getc(serial_t *obj)
group-onsemi 0:098463de4c5d 298 {
group-onsemi 0:098463de4c5d 299 int c;
group-onsemi 0:098463de4c5d 300
group-onsemi 0:098463de4c5d 301 // Wait for data to be available
group-onsemi 0:098463de4c5d 302 while ((obj->uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) == 0);
group-onsemi 0:098463de4c5d 303
group-onsemi 0:098463de4c5d 304 c = *obj->fifo->rx_8;
group-onsemi 0:098463de4c5d 305
group-onsemi 0:098463de4c5d 306 return c;
group-onsemi 0:098463de4c5d 307 }
group-onsemi 0:098463de4c5d 308
group-onsemi 0:098463de4c5d 309 //******************************************************************************
group-onsemi 0:098463de4c5d 310 void serial_putc(serial_t *obj, int c)
group-onsemi 0:098463de4c5d 311 {
group-onsemi 0:098463de4c5d 312 // Wait for TXFIFO to not be full
group-onsemi 0:098463de4c5d 313 while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
group-onsemi 0:098463de4c5d 314 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
group-onsemi 0:098463de4c5d 315 >= MXC_UART_FIFO_DEPTH );
group-onsemi 0:098463de4c5d 316
group-onsemi 0:098463de4c5d 317 // Must clear before every write to the buffer to know that the fifo
group-onsemi 0:098463de4c5d 318 // is empty when the TX DONE bit is set
group-onsemi 0:098463de4c5d 319 obj->uart->intfl = MXC_F_UART_INTFL_TX_DONE;
group-onsemi 0:098463de4c5d 320 *obj->fifo->tx_8 = (uint8_t)c;
group-onsemi 0:098463de4c5d 321 }
group-onsemi 0:098463de4c5d 322
group-onsemi 0:098463de4c5d 323 //******************************************************************************
group-onsemi 0:098463de4c5d 324 int serial_readable(serial_t *obj)
group-onsemi 0:098463de4c5d 325 {
group-onsemi 0:098463de4c5d 326 return (obj->uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY);
group-onsemi 0:098463de4c5d 327 }
group-onsemi 0:098463de4c5d 328
group-onsemi 0:098463de4c5d 329 //******************************************************************************
group-onsemi 0:098463de4c5d 330 int serial_writable(serial_t *obj)
group-onsemi 0:098463de4c5d 331 {
group-onsemi 0:098463de4c5d 332 return ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
group-onsemi 0:098463de4c5d 333 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
group-onsemi 0:098463de4c5d 334 < MXC_UART_FIFO_DEPTH );
group-onsemi 0:098463de4c5d 335 }
group-onsemi 0:098463de4c5d 336
group-onsemi 0:098463de4c5d 337 //******************************************************************************
group-onsemi 0:098463de4c5d 338 void serial_clear(serial_t *obj)
group-onsemi 0:098463de4c5d 339 {
group-onsemi 0:098463de4c5d 340 // Clear the rx and tx fifos
group-onsemi 0:098463de4c5d 341 obj->uart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
group-onsemi 0:098463de4c5d 342 obj->uart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
group-onsemi 0:098463de4c5d 343 }
group-onsemi 0:098463de4c5d 344
group-onsemi 0:098463de4c5d 345
group-onsemi 0:098463de4c5d 346 //******************************************************************************
group-onsemi 0:098463de4c5d 347 void serial_break_set(serial_t *obj)
group-onsemi 0:098463de4c5d 348 {
group-onsemi 0:098463de4c5d 349 // Make sure that nothing is being sent
group-onsemi 0:098463de4c5d 350 while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
group-onsemi 0:098463de4c5d 351 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) > 0);
group-onsemi 0:098463de4c5d 352 while (!(obj->uart->intfl & MXC_F_UART_INTFL_TX_DONE));
group-onsemi 0:098463de4c5d 353
group-onsemi 0:098463de4c5d 354 // Configure the GPIO to output 0
group-onsemi 0:098463de4c5d 355 gpio_t tx_gpio;
group-onsemi 0:098463de4c5d 356 switch (((UARTName)(obj->uart))) {
group-onsemi 0:098463de4c5d 357 case UART_0:
group-onsemi 0:098463de4c5d 358 gpio_init_out(&tx_gpio, UART0_TX);
group-onsemi 0:098463de4c5d 359 break;
group-onsemi 0:098463de4c5d 360 case UART_1:
group-onsemi 0:098463de4c5d 361 gpio_init_out(&tx_gpio, UART1_TX);
group-onsemi 0:098463de4c5d 362 break;
group-onsemi 0:098463de4c5d 363 case UART_2:
group-onsemi 0:098463de4c5d 364 gpio_init_out(&tx_gpio, UART2_TX);
group-onsemi 0:098463de4c5d 365 break;
group-onsemi 0:098463de4c5d 366 case UART_3:
group-onsemi 0:098463de4c5d 367 gpio_init_out(&tx_gpio, UART3_TX);
group-onsemi 0:098463de4c5d 368 break;
group-onsemi 0:098463de4c5d 369 default:
group-onsemi 0:098463de4c5d 370 gpio_init_out(&tx_gpio, (PinName)NC);
group-onsemi 0:098463de4c5d 371 break;
group-onsemi 0:098463de4c5d 372 }
group-onsemi 0:098463de4c5d 373
group-onsemi 0:098463de4c5d 374 gpio_write(&tx_gpio, 0);
group-onsemi 0:098463de4c5d 375
group-onsemi 0:098463de4c5d 376 // GPIO is setup now, but we need to map GPIO to the pin
group-onsemi 0:098463de4c5d 377 switch (((UARTName)(obj->uart))) {
group-onsemi 0:098463de4c5d 378 case UART_0:
group-onsemi 0:098463de4c5d 379 MXC_IOMAN->uart0_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
group-onsemi 0:098463de4c5d 380 MBED_ASSERT((MXC_IOMAN->uart0_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
group-onsemi 0:098463de4c5d 381 break;
group-onsemi 0:098463de4c5d 382 case UART_1:
group-onsemi 0:098463de4c5d 383 MXC_IOMAN->uart1_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
group-onsemi 0:098463de4c5d 384 MBED_ASSERT((MXC_IOMAN->uart1_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
group-onsemi 0:098463de4c5d 385 break;
group-onsemi 0:098463de4c5d 386 case UART_2:
group-onsemi 0:098463de4c5d 387 MXC_IOMAN->uart2_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
group-onsemi 0:098463de4c5d 388 MBED_ASSERT((MXC_IOMAN->uart2_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
group-onsemi 0:098463de4c5d 389 break;
group-onsemi 0:098463de4c5d 390 case UART_3:
group-onsemi 0:098463de4c5d 391 MXC_IOMAN->uart3_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
group-onsemi 0:098463de4c5d 392 MBED_ASSERT((MXC_IOMAN->uart3_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
group-onsemi 0:098463de4c5d 393 break;
group-onsemi 0:098463de4c5d 394 default:
group-onsemi 0:098463de4c5d 395 break;
group-onsemi 0:098463de4c5d 396 }
group-onsemi 0:098463de4c5d 397 }
group-onsemi 0:098463de4c5d 398
group-onsemi 0:098463de4c5d 399 //******************************************************************************
group-onsemi 0:098463de4c5d 400 void serial_break_clear(serial_t *obj)
group-onsemi 0:098463de4c5d 401 {
group-onsemi 0:098463de4c5d 402 // Configure the GPIO to output 1
group-onsemi 0:098463de4c5d 403 gpio_t tx_gpio;
group-onsemi 0:098463de4c5d 404 switch (((UARTName)(obj->uart))) {
group-onsemi 0:098463de4c5d 405 case UART_0:
group-onsemi 0:098463de4c5d 406 gpio_init_out(&tx_gpio, UART0_TX);
group-onsemi 0:098463de4c5d 407 break;
group-onsemi 0:098463de4c5d 408 case UART_1:
group-onsemi 0:098463de4c5d 409 gpio_init_out(&tx_gpio, UART1_TX);
group-onsemi 0:098463de4c5d 410 break;
group-onsemi 0:098463de4c5d 411 case UART_2:
group-onsemi 0:098463de4c5d 412 gpio_init_out(&tx_gpio, UART2_TX);
group-onsemi 0:098463de4c5d 413 break;
group-onsemi 0:098463de4c5d 414 case UART_3:
group-onsemi 0:098463de4c5d 415 gpio_init_out(&tx_gpio, UART3_TX);
group-onsemi 0:098463de4c5d 416 break;
group-onsemi 0:098463de4c5d 417 default:
group-onsemi 0:098463de4c5d 418 gpio_init_out(&tx_gpio, (PinName)NC);
group-onsemi 0:098463de4c5d 419 break;
group-onsemi 0:098463de4c5d 420 }
group-onsemi 0:098463de4c5d 421
group-onsemi 0:098463de4c5d 422 gpio_write(&tx_gpio, 1);
group-onsemi 0:098463de4c5d 423
group-onsemi 0:098463de4c5d 424 // Renable UART
group-onsemi 0:098463de4c5d 425 switch (((UARTName)(obj->uart))) {
group-onsemi 0:098463de4c5d 426 case UART_0:
group-onsemi 0:098463de4c5d 427 serial_pinout_tx(UART0_TX);
group-onsemi 0:098463de4c5d 428 break;
group-onsemi 0:098463de4c5d 429 case UART_1:
group-onsemi 0:098463de4c5d 430 serial_pinout_tx(UART1_TX);
group-onsemi 0:098463de4c5d 431 break;
group-onsemi 0:098463de4c5d 432 case UART_2:
group-onsemi 0:098463de4c5d 433 serial_pinout_tx(UART2_TX);
group-onsemi 0:098463de4c5d 434 break;
group-onsemi 0:098463de4c5d 435 case UART_3:
group-onsemi 0:098463de4c5d 436 serial_pinout_tx(UART3_TX);
group-onsemi 0:098463de4c5d 437 break;
group-onsemi 0:098463de4c5d 438 default:
group-onsemi 0:098463de4c5d 439 serial_pinout_tx((PinName)NC);
group-onsemi 0:098463de4c5d 440 break;
group-onsemi 0:098463de4c5d 441 }
group-onsemi 0:098463de4c5d 442 }
group-onsemi 0:098463de4c5d 443
group-onsemi 0:098463de4c5d 444 //******************************************************************************
group-onsemi 0:098463de4c5d 445 void serial_pinout_tx(PinName tx)
group-onsemi 0:098463de4c5d 446 {
group-onsemi 0:098463de4c5d 447 pinmap_pinout(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 448 }
group-onsemi 0:098463de4c5d 449
group-onsemi 0:098463de4c5d 450 //******************************************************************************
group-onsemi 0:098463de4c5d 451 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
group-onsemi 0:098463de4c5d 452 {
group-onsemi 0:098463de4c5d 453 uint32_t ctrl = obj->uart->ctrl;
group-onsemi 0:098463de4c5d 454
group-onsemi 0:098463de4c5d 455 // Disable hardware flow control
group-onsemi 0:098463de4c5d 456 ctrl &= ~(MXC_F_UART_CTRL_RTS_EN | MXC_F_UART_CTRL_CTS_EN);
group-onsemi 0:098463de4c5d 457
group-onsemi 0:098463de4c5d 458 if (FlowControlNone != type) {
group-onsemi 0:098463de4c5d 459 // Check to see if we can use HW flow control
group-onsemi 0:098463de4c5d 460 UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
group-onsemi 0:098463de4c5d 461 UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
group-onsemi 0:098463de4c5d 462 UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
group-onsemi 0:098463de4c5d 463
group-onsemi 0:098463de4c5d 464 // Make sure that the pins are pointing to the same UART
group-onsemi 0:098463de4c5d 465 MBED_ASSERT(uart != (UARTName)NC);
group-onsemi 0:098463de4c5d 466
group-onsemi 0:098463de4c5d 467 if ((FlowControlCTS == type) || (FlowControlRTSCTS == type)) {
group-onsemi 0:098463de4c5d 468 // Make sure pin is in the PinMap
group-onsemi 0:098463de4c5d 469 MBED_ASSERT(uart_cts != (UARTName)NC);
group-onsemi 0:098463de4c5d 470
group-onsemi 0:098463de4c5d 471 // Enable the pin for CTS function
group-onsemi 0:098463de4c5d 472 pinmap_pinout(txflow, PinMap_UART_CTS);
group-onsemi 0:098463de4c5d 473
group-onsemi 0:098463de4c5d 474 // Enable active-low hardware flow control
group-onsemi 0:098463de4c5d 475 ctrl |= (MXC_F_UART_CTRL_CTS_EN | MXC_F_UART_CTRL_CTS_POLARITY);
group-onsemi 0:098463de4c5d 476 }
group-onsemi 0:098463de4c5d 477
group-onsemi 0:098463de4c5d 478 if ((FlowControlRTS == type) || (FlowControlRTSCTS == type)) {
group-onsemi 0:098463de4c5d 479 // Make sure pin is in the PinMap
group-onsemi 0:098463de4c5d 480 MBED_ASSERT(uart_rts != (UARTName)NC);
group-onsemi 0:098463de4c5d 481
group-onsemi 0:098463de4c5d 482 // Enable the pin for RTS function
group-onsemi 0:098463de4c5d 483 pinmap_pinout(rxflow, PinMap_UART_RTS);
group-onsemi 0:098463de4c5d 484
group-onsemi 0:098463de4c5d 485 // Enable active-low hardware flow control
group-onsemi 0:098463de4c5d 486 ctrl |= (MXC_F_UART_CTRL_RTS_EN | MXC_F_UART_CTRL_RTS_POLARITY);
group-onsemi 0:098463de4c5d 487 }
group-onsemi 0:098463de4c5d 488 }
group-onsemi 0:098463de4c5d 489
group-onsemi 0:098463de4c5d 490 obj->uart->ctrl = ctrl;
group-onsemi 0:098463de4c5d 491 }