ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32610/i2c_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 35 #include "i2c_api.h"
group-onsemi 0:098463de4c5d 36 #include "cmsis.h"
group-onsemi 0:098463de4c5d 37 #include "i2cm_regs.h"
group-onsemi 0:098463de4c5d 38 #include "clkman_regs.h"
group-onsemi 0:098463de4c5d 39 #include "ioman_regs.h"
group-onsemi 0:098463de4c5d 40 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 #define I2C_SLAVE_ADDR_READ_BIT 0x0001
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 #ifndef MXC_I2CM_TX_TIMEOUT
group-onsemi 0:098463de4c5d 45 #define MXC_I2CM_TX_TIMEOUT 0x5000
group-onsemi 0:098463de4c5d 46 #endif
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 #ifndef MXC_I2CM_RX_TIMEOUT
group-onsemi 0:098463de4c5d 49 #define MXC_I2CM_RX_TIMEOUT 0x5000
group-onsemi 0:098463de4c5d 50 #endif
group-onsemi 0:098463de4c5d 51
group-onsemi 0:098463de4c5d 52 typedef enum {
group-onsemi 0:098463de4c5d 53 /** 100KHz */
group-onsemi 0:098463de4c5d 54 MXC_E_I2CM_SPEED_100KHZ = 0,
group-onsemi 0:098463de4c5d 55 /** 400KHz */
group-onsemi 0:098463de4c5d 56 MXC_E_I2CM_SPEED_400KHZ,
group-onsemi 0:098463de4c5d 57 /** 1MHz */
group-onsemi 0:098463de4c5d 58 MXC_E_I2CM_SPEED_1MHZ
group-onsemi 0:098463de4c5d 59 } i2cm_speed_t;
group-onsemi 0:098463de4c5d 60
group-onsemi 0:098463de4c5d 61 /* Clock divider lookup table */
group-onsemi 0:098463de4c5d 62 static const uint32_t clk_div_table[3][8] = {
group-onsemi 0:098463de4c5d 63 /* MXC_E_I2CM_SPEED_100KHZ */
group-onsemi 0:098463de4c5d 64 {
group-onsemi 0:098463de4c5d 65 /* 0: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 66 /* 1: 6MHz */ (( 3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | ( 7 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 67 /* 2: 8MHz */ (( 4 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (10 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 48 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 68 /* 3: 12MHz */ (( 6 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (17 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 72 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 69 /* 4: 16MHz */ (( 8 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 96 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 70 /* 5: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 71 /* 6: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 72 /* 7: 24MHz */ ((12 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (38 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (144 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 73 },
group-onsemi 0:098463de4c5d 74 /* MXC_E_I2CM_SPEED_400KHZ */
group-onsemi 0:098463de4c5d 75 {
group-onsemi 0:098463de4c5d 76 /* 0: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 77 /* 1: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 78 /* 2: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 79 /* 3: 12MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (1 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (18 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 80 /* 4: 16MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (2 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 81 /* 5: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 82 /* 6: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 83 /* 7: 24MHz */ ((3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (5 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 84 },
group-onsemi 0:098463de4c5d 85 /* MXC_E_I2CM_SPEED_1MHZ */
group-onsemi 0:098463de4c5d 86 {
group-onsemi 0:098463de4c5d 87 /* 0: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 88 /* 1: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 89 /* 2: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 90 /* 3: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 91 /* 4: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 92 /* 5: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 93 /* 6: */ 0, /* not supported */
group-onsemi 0:098463de4c5d 94 /* 7: 24MHz */ ((1 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (0 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (14 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
group-onsemi 0:098463de4c5d 95 },
group-onsemi 0:098463de4c5d 96 };
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
group-onsemi 0:098463de4c5d 99 {
group-onsemi 0:098463de4c5d 100 // determine the I2C to use
group-onsemi 0:098463de4c5d 101 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
group-onsemi 0:098463de4c5d 102 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
group-onsemi 0:098463de4c5d 103 mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl);
group-onsemi 0:098463de4c5d 104 MBED_ASSERT((int)i2c != NC);
group-onsemi 0:098463de4c5d 105
group-onsemi 0:098463de4c5d 106 obj->i2c = i2c;
group-onsemi 0:098463de4c5d 107 obj->txfifo = (uint16_t*)MXC_I2CM_GET_BASE_TX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
group-onsemi 0:098463de4c5d 108 obj->rxfifo = (uint16_t*)MXC_I2CM_GET_BASE_RX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
group-onsemi 0:098463de4c5d 109 obj->start_pending = 0;
group-onsemi 0:098463de4c5d 110 obj->stop_pending = 0;
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 // configure the pins
group-onsemi 0:098463de4c5d 113 pinmap_pinout(sda, PinMap_I2C_SDA);
group-onsemi 0:098463de4c5d 114 pinmap_pinout(scl, PinMap_I2C_SCL);
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 // enable the clock
group-onsemi 0:098463de4c5d 117 MXC_CLKMAN->clk_ctrl_6_i2cm = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
group-onsemi 0:098463de4c5d 118
group-onsemi 0:098463de4c5d 119 // reset module
group-onsemi 0:098463de4c5d 120 i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
group-onsemi 0:098463de4c5d 121 i2c->ctrl = 0;
group-onsemi 0:098463de4c5d 122
group-onsemi 0:098463de4c5d 123 // set default frequency at 100k
group-onsemi 0:098463de4c5d 124 i2c_frequency(obj, 100000);
group-onsemi 0:098463de4c5d 125
group-onsemi 0:098463de4c5d 126 // set timeout to 255 ms and turn on the auto-stop option
group-onsemi 0:098463de4c5d 127 i2c->timeout = (0xFF << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS) | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN;
group-onsemi 0:098463de4c5d 128
group-onsemi 0:098463de4c5d 129 // enable tx_fifo and rx_fifo
group-onsemi 0:098463de4c5d 130 i2c->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN);
group-onsemi 0:098463de4c5d 131 }
group-onsemi 0:098463de4c5d 132
group-onsemi 0:098463de4c5d 133 void i2c_frequency(i2c_t *obj, int hz)
group-onsemi 0:098463de4c5d 134 {
group-onsemi 0:098463de4c5d 135 // compute clock array index
group-onsemi 0:098463de4c5d 136 int clki = ((SystemCoreClock + 1500000) / 3000000) - 1;
group-onsemi 0:098463de4c5d 137
group-onsemi 0:098463de4c5d 138 // get clock divider settings from lookup table
group-onsemi 0:098463de4c5d 139 if ((hz < 400000) && (clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki] > 0)) {
group-onsemi 0:098463de4c5d 140 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki];
group-onsemi 0:098463de4c5d 141 } else if ((hz < 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki] > 0)) {
group-onsemi 0:098463de4c5d 142 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki];
group-onsemi 0:098463de4c5d 143 } else if ((hz >= 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki] > 0)) {
group-onsemi 0:098463de4c5d 144 obj->i2c->hs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki];
group-onsemi 0:098463de4c5d 145 }
group-onsemi 0:098463de4c5d 146 }
group-onsemi 0:098463de4c5d 147
group-onsemi 0:098463de4c5d 148 static int write_tx_fifo(i2c_t *obj, const uint16_t data)
group-onsemi 0:098463de4c5d 149 {
group-onsemi 0:098463de4c5d 150 int timeout = MXC_I2CM_TX_TIMEOUT;
group-onsemi 0:098463de4c5d 151
group-onsemi 0:098463de4c5d 152 while (*obj->txfifo) {
group-onsemi 0:098463de4c5d 153 uint32_t intfl = obj->i2c->intfl;
group-onsemi 0:098463de4c5d 154 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
group-onsemi 0:098463de4c5d 155 return I2C_ERROR_NO_SLAVE;
group-onsemi 0:098463de4c5d 156 }
group-onsemi 0:098463de4c5d 157 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
group-onsemi 0:098463de4c5d 158 return I2C_ERROR_BUS_BUSY;
group-onsemi 0:098463de4c5d 159 }
group-onsemi 0:098463de4c5d 160 timeout--;
group-onsemi 0:098463de4c5d 161 }
group-onsemi 0:098463de4c5d 162 *obj->txfifo = data;
group-onsemi 0:098463de4c5d 163
group-onsemi 0:098463de4c5d 164 return 0;
group-onsemi 0:098463de4c5d 165 }
group-onsemi 0:098463de4c5d 166
group-onsemi 0:098463de4c5d 167 static int wait_tx_in_progress(i2c_t *obj)
group-onsemi 0:098463de4c5d 168 {
group-onsemi 0:098463de4c5d 169 int timeout = MXC_I2CM_TX_TIMEOUT;
group-onsemi 0:098463de4c5d 170
group-onsemi 0:098463de4c5d 171 while ((obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout);
group-onsemi 0:098463de4c5d 172
group-onsemi 0:098463de4c5d 173 uint32_t intfl = obj->i2c->intfl;
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
group-onsemi 0:098463de4c5d 176 i2c_reset(obj);
group-onsemi 0:098463de4c5d 177 return I2C_ERROR_NO_SLAVE;
group-onsemi 0:098463de4c5d 178 }
group-onsemi 0:098463de4c5d 179
group-onsemi 0:098463de4c5d 180 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
group-onsemi 0:098463de4c5d 181 i2c_reset(obj);
group-onsemi 0:098463de4c5d 182 return I2C_ERROR_BUS_BUSY;
group-onsemi 0:098463de4c5d 183 }
group-onsemi 0:098463de4c5d 184
group-onsemi 0:098463de4c5d 185 return 0;
group-onsemi 0:098463de4c5d 186 }
group-onsemi 0:098463de4c5d 187
group-onsemi 0:098463de4c5d 188 int i2c_start(i2c_t *obj)
group-onsemi 0:098463de4c5d 189 {
group-onsemi 0:098463de4c5d 190 obj->start_pending = 1;
group-onsemi 0:098463de4c5d 191 return 0;
group-onsemi 0:098463de4c5d 192 }
group-onsemi 0:098463de4c5d 193
group-onsemi 0:098463de4c5d 194 int i2c_stop(i2c_t *obj)
group-onsemi 0:098463de4c5d 195 {
group-onsemi 0:098463de4c5d 196 obj->start_pending = 0;
group-onsemi 0:098463de4c5d 197 write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP);
group-onsemi 0:098463de4c5d 198
group-onsemi 0:098463de4c5d 199 return wait_tx_in_progress(obj);
group-onsemi 0:098463de4c5d 200 }
group-onsemi 0:098463de4c5d 201
group-onsemi 0:098463de4c5d 202 void i2c_reset(i2c_t *obj)
group-onsemi 0:098463de4c5d 203 {
group-onsemi 0:098463de4c5d 204 obj->i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
group-onsemi 0:098463de4c5d 205 obj->i2c->intfl = 0x3FF; // clear all interrupts
group-onsemi 0:098463de4c5d 206 obj->i2c->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN;
group-onsemi 0:098463de4c5d 207 obj->start_pending = 0;
group-onsemi 0:098463de4c5d 208 }
group-onsemi 0:098463de4c5d 209
group-onsemi 0:098463de4c5d 210 int i2c_byte_write(i2c_t *obj, int data)
group-onsemi 0:098463de4c5d 211 {
group-onsemi 0:098463de4c5d 212 int err;
group-onsemi 0:098463de4c5d 213
group-onsemi 0:098463de4c5d 214 // clear all interrupts
group-onsemi 0:098463de4c5d 215 obj->i2c->intfl = 0x3FF;
group-onsemi 0:098463de4c5d 216
group-onsemi 0:098463de4c5d 217 if (obj->start_pending) {
group-onsemi 0:098463de4c5d 218 obj->start_pending = 0;
group-onsemi 0:098463de4c5d 219 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_START;
group-onsemi 0:098463de4c5d 220 } else {
group-onsemi 0:098463de4c5d 221 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_TXDATA_ACK;
group-onsemi 0:098463de4c5d 222 }
group-onsemi 0:098463de4c5d 223
group-onsemi 0:098463de4c5d 224 if ((err = write_tx_fifo(obj, data)) != 0) {
group-onsemi 0:098463de4c5d 225 return err;
group-onsemi 0:098463de4c5d 226 }
group-onsemi 0:098463de4c5d 227
group-onsemi 0:098463de4c5d 228 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
group-onsemi 0:098463de4c5d 229
group-onsemi 0:098463de4c5d 230 // Wait for the FIFO to be empty
group-onsemi 0:098463de4c5d 231 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY));
group-onsemi 0:098463de4c5d 232
group-onsemi 0:098463de4c5d 233 if (obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
group-onsemi 0:098463de4c5d 234 i2c_reset(obj);
group-onsemi 0:098463de4c5d 235 return 0;
group-onsemi 0:098463de4c5d 236 }
group-onsemi 0:098463de4c5d 237
group-onsemi 0:098463de4c5d 238 if (obj->i2c->intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) {
group-onsemi 0:098463de4c5d 239 i2c_reset(obj);
group-onsemi 0:098463de4c5d 240 return 2;
group-onsemi 0:098463de4c5d 241 }
group-onsemi 0:098463de4c5d 242
group-onsemi 0:098463de4c5d 243 return 1;
group-onsemi 0:098463de4c5d 244 }
group-onsemi 0:098463de4c5d 245
group-onsemi 0:098463de4c5d 246 int i2c_byte_read(i2c_t *obj, int last)
group-onsemi 0:098463de4c5d 247 {
group-onsemi 0:098463de4c5d 248 uint16_t fifo_value;
group-onsemi 0:098463de4c5d 249 int err;
group-onsemi 0:098463de4c5d 250
group-onsemi 0:098463de4c5d 251 // clear all interrupts
group-onsemi 0:098463de4c5d 252 obj->i2c->intfl = 0x3FF;
group-onsemi 0:098463de4c5d 253
group-onsemi 0:098463de4c5d 254 if (last) {
group-onsemi 0:098463de4c5d 255 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_NACK;
group-onsemi 0:098463de4c5d 256 } else {
group-onsemi 0:098463de4c5d 257 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT;
group-onsemi 0:098463de4c5d 258 }
group-onsemi 0:098463de4c5d 259
group-onsemi 0:098463de4c5d 260 if ((err = write_tx_fifo(obj, fifo_value)) != 0) {
group-onsemi 0:098463de4c5d 261 i2c_reset(obj);
group-onsemi 0:098463de4c5d 262 return err;
group-onsemi 0:098463de4c5d 263 }
group-onsemi 0:098463de4c5d 264
group-onsemi 0:098463de4c5d 265 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
group-onsemi 0:098463de4c5d 266
group-onsemi 0:098463de4c5d 267 int timeout = MXC_I2CM_RX_TIMEOUT;
group-onsemi 0:098463de4c5d 268 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
group-onsemi 0:098463de4c5d 269 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
group-onsemi 0:098463de4c5d 270 if ((--timeout < 0) || (obj->i2c->trans & (MXC_F_I2CM_TRANS_TX_TIMEOUT |
group-onsemi 0:098463de4c5d 271 MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED))) {
group-onsemi 0:098463de4c5d 272 break;
group-onsemi 0:098463de4c5d 273 }
group-onsemi 0:098463de4c5d 274 }
group-onsemi 0:098463de4c5d 275
group-onsemi 0:098463de4c5d 276 if (obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) {
group-onsemi 0:098463de4c5d 277 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
group-onsemi 0:098463de4c5d 278 return *obj->rxfifo;
group-onsemi 0:098463de4c5d 279 }
group-onsemi 0:098463de4c5d 280
group-onsemi 0:098463de4c5d 281 i2c_reset(obj);
group-onsemi 0:098463de4c5d 282
group-onsemi 0:098463de4c5d 283 return -1;
group-onsemi 0:098463de4c5d 284 }
group-onsemi 0:098463de4c5d 285
group-onsemi 0:098463de4c5d 286 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
group-onsemi 0:098463de4c5d 287 {
group-onsemi 0:098463de4c5d 288 int err, retval = 0;
group-onsemi 0:098463de4c5d 289 int i;
group-onsemi 0:098463de4c5d 290
group-onsemi 0:098463de4c5d 291 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
group-onsemi 0:098463de4c5d 292 return 0;
group-onsemi 0:098463de4c5d 293 }
group-onsemi 0:098463de4c5d 294
group-onsemi 0:098463de4c5d 295 // clear all interrupts
group-onsemi 0:098463de4c5d 296 obj->i2c->intfl = 0x3FF;
group-onsemi 0:098463de4c5d 297
group-onsemi 0:098463de4c5d 298 // write the address to the fifo
group-onsemi 0:098463de4c5d 299 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address))) != 0) { // start + addr (write)
group-onsemi 0:098463de4c5d 300 i2c_reset(obj);
group-onsemi 0:098463de4c5d 301 return err;
group-onsemi 0:098463de4c5d 302 }
group-onsemi 0:098463de4c5d 303 obj->start_pending = 0;
group-onsemi 0:098463de4c5d 304
group-onsemi 0:098463de4c5d 305 // start the transaction
group-onsemi 0:098463de4c5d 306 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
group-onsemi 0:098463de4c5d 307
group-onsemi 0:098463de4c5d 308 // load as much of the cmd into the FIFO as possible
group-onsemi 0:098463de4c5d 309 for (i = 0; i < length; i++) {
group-onsemi 0:098463de4c5d 310 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != 0) { // cmd (expect ACK)
group-onsemi 0:098463de4c5d 311 retval = (retval ? retval : err);
group-onsemi 0:098463de4c5d 312 break;
group-onsemi 0:098463de4c5d 313 }
group-onsemi 0:098463de4c5d 314 }
group-onsemi 0:098463de4c5d 315
group-onsemi 0:098463de4c5d 316 if (stop) {
group-onsemi 0:098463de4c5d 317 obj->stop_pending = 0;
group-onsemi 0:098463de4c5d 318 if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
group-onsemi 0:098463de4c5d 319 retval = (retval ? retval : err);
group-onsemi 0:098463de4c5d 320 }
group-onsemi 0:098463de4c5d 321
group-onsemi 0:098463de4c5d 322 if ((err = wait_tx_in_progress(obj)) != 0) {
group-onsemi 0:098463de4c5d 323 retval = (retval ? retval : err);
group-onsemi 0:098463de4c5d 324 }
group-onsemi 0:098463de4c5d 325 } else {
group-onsemi 0:098463de4c5d 326 obj->stop_pending = 1;
group-onsemi 0:098463de4c5d 327 int timeout = MXC_I2CM_TX_TIMEOUT;
group-onsemi 0:098463de4c5d 328 // Wait for TX fifo to be empty
group-onsemi 0:098463de4c5d 329 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY) && timeout--);
group-onsemi 0:098463de4c5d 330 }
group-onsemi 0:098463de4c5d 331
group-onsemi 0:098463de4c5d 332 if (retval == 0) {
group-onsemi 0:098463de4c5d 333 return length;
group-onsemi 0:098463de4c5d 334 }
group-onsemi 0:098463de4c5d 335
group-onsemi 0:098463de4c5d 336 i2c_reset(obj);
group-onsemi 0:098463de4c5d 337
group-onsemi 0:098463de4c5d 338 return retval;
group-onsemi 0:098463de4c5d 339 }
group-onsemi 0:098463de4c5d 340
group-onsemi 0:098463de4c5d 341 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
group-onsemi 0:098463de4c5d 342 {
group-onsemi 0:098463de4c5d 343 int err, retval = 0;
group-onsemi 0:098463de4c5d 344 int i = length;
group-onsemi 0:098463de4c5d 345 int timeout;
group-onsemi 0:098463de4c5d 346
group-onsemi 0:098463de4c5d 347 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
group-onsemi 0:098463de4c5d 348 return 0;
group-onsemi 0:098463de4c5d 349 }
group-onsemi 0:098463de4c5d 350
group-onsemi 0:098463de4c5d 351 // clear all interrupts
group-onsemi 0:098463de4c5d 352 obj->i2c->intfl = 0x3FF;
group-onsemi 0:098463de4c5d 353
group-onsemi 0:098463de4c5d 354 // start + addr (read)
group-onsemi 0:098463de4c5d 355 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address | I2C_SLAVE_ADDR_READ_BIT))) != 0) {
group-onsemi 0:098463de4c5d 356 goto read_done;
group-onsemi 0:098463de4c5d 357 }
group-onsemi 0:098463de4c5d 358 obj->start_pending = 0;
group-onsemi 0:098463de4c5d 359
group-onsemi 0:098463de4c5d 360 while (i > 256) {
group-onsemi 0:098463de4c5d 361 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != 0) {
group-onsemi 0:098463de4c5d 362 goto read_done;
group-onsemi 0:098463de4c5d 363 }
group-onsemi 0:098463de4c5d 364 i -= 256;
group-onsemi 0:098463de4c5d 365 }
group-onsemi 0:098463de4c5d 366
group-onsemi 0:098463de4c5d 367 if (i > 1) {
group-onsemi 0:098463de4c5d 368 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i - 2)))) != 0) {
group-onsemi 0:098463de4c5d 369 goto read_done;
group-onsemi 0:098463de4c5d 370 }
group-onsemi 0:098463de4c5d 371 }
group-onsemi 0:098463de4c5d 372
group-onsemi 0:098463de4c5d 373 // start the transaction
group-onsemi 0:098463de4c5d 374 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
group-onsemi 0:098463de4c5d 375
group-onsemi 0:098463de4c5d 376 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK)) != 0) { // NACK last data byte
group-onsemi 0:098463de4c5d 377 goto read_done;
group-onsemi 0:098463de4c5d 378 }
group-onsemi 0:098463de4c5d 379
group-onsemi 0:098463de4c5d 380 if (stop) {
group-onsemi 0:098463de4c5d 381 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
group-onsemi 0:098463de4c5d 382 goto read_done;
group-onsemi 0:098463de4c5d 383 }
group-onsemi 0:098463de4c5d 384 }
group-onsemi 0:098463de4c5d 385
group-onsemi 0:098463de4c5d 386 timeout = MXC_I2CM_RX_TIMEOUT;
group-onsemi 0:098463de4c5d 387 i = 0;
group-onsemi 0:098463de4c5d 388 while (i < length) {
group-onsemi 0:098463de4c5d 389 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
group-onsemi 0:098463de4c5d 390 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
group-onsemi 0:098463de4c5d 391 if ((--timeout < 0) || (obj->i2c->trans & (MXC_F_I2CM_TRANS_TX_TIMEOUT |
group-onsemi 0:098463de4c5d 392 MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED))) {
group-onsemi 0:098463de4c5d 393 retval = -3;
group-onsemi 0:098463de4c5d 394 goto read_done;
group-onsemi 0:098463de4c5d 395 }
group-onsemi 0:098463de4c5d 396 }
group-onsemi 0:098463de4c5d 397
group-onsemi 0:098463de4c5d 398 timeout = MXC_I2CM_RX_TIMEOUT;
group-onsemi 0:098463de4c5d 399
group-onsemi 0:098463de4c5d 400 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
group-onsemi 0:098463de4c5d 401
group-onsemi 0:098463de4c5d 402 uint16_t temp = *obj->rxfifo;
group-onsemi 0:098463de4c5d 403
group-onsemi 0:098463de4c5d 404 if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) {
group-onsemi 0:098463de4c5d 405 continue;
group-onsemi 0:098463de4c5d 406 }
group-onsemi 0:098463de4c5d 407 data[i++] = (uint8_t) temp;
group-onsemi 0:098463de4c5d 408 }
group-onsemi 0:098463de4c5d 409
group-onsemi 0:098463de4c5d 410 read_done:
group-onsemi 0:098463de4c5d 411
group-onsemi 0:098463de4c5d 412 if (stop) {
group-onsemi 0:098463de4c5d 413 obj->stop_pending = 0;
group-onsemi 0:098463de4c5d 414 if ((err = wait_tx_in_progress(obj)) != 0) {
group-onsemi 0:098463de4c5d 415 retval = (retval ? retval : err);
group-onsemi 0:098463de4c5d 416 }
group-onsemi 0:098463de4c5d 417 } else {
group-onsemi 0:098463de4c5d 418 obj->stop_pending = 1;
group-onsemi 0:098463de4c5d 419 }
group-onsemi 0:098463de4c5d 420
group-onsemi 0:098463de4c5d 421 if (retval == 0) {
group-onsemi 0:098463de4c5d 422 return length;
group-onsemi 0:098463de4c5d 423 }
group-onsemi 0:098463de4c5d 424
group-onsemi 0:098463de4c5d 425 i2c_reset(obj);
group-onsemi 0:098463de4c5d 426
group-onsemi 0:098463de4c5d 427 return retval;
group-onsemi 0:098463de4c5d 428 }