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CMSIS DSP library

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cmsis_dsp/ControllerFunctions/arm_pid_init_q31.c@1:fdd22bb7aa52, 2012-11-28 (annotated)

Committer:
emilmont
Date:
Wed Nov 28 12:30:09 2012 +0000
Revision:
1:fdd22bb7aa52
Child:
2:da51fb522205
DSP library code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
emilmont 1:fdd22bb7aa52 2 * Copyright (C) 2010 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
emilmont 1:fdd22bb7aa52 4 * $Date: 15. February 2012
emilmont 1:fdd22bb7aa52 5 * $Revision: V1.1.0
emilmont 1:fdd22bb7aa52 6 *
emilmont 1:fdd22bb7aa52 7 * Project: CMSIS DSP Library
emilmont 1:fdd22bb7aa52 8 * Title: arm_pid_init_q31.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 1:fdd22bb7aa52 10 * Description: Q31 PID Control initialization function
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 13 *
emilmont 1:fdd22bb7aa52 14 * Version 1.1.0 2012/02/15
emilmont 1:fdd22bb7aa52 15 * Updated with more optimizations, bug fixes and minor API changes.
emilmont 1:fdd22bb7aa52 16 *
emilmont 1:fdd22bb7aa52 17 * Version 1.0.10 2011/7/15
emilmont 1:fdd22bb7aa52 18 * Big Endian support added and Merged M0 and M3/M4 Source code.
emilmont 1:fdd22bb7aa52 19 *
emilmont 1:fdd22bb7aa52 20 * Version 1.0.3 2010/11/29
emilmont 1:fdd22bb7aa52 21 * Re-organized the CMSIS folders and updated documentation.
emilmont 1:fdd22bb7aa52 22 *
emilmont 1:fdd22bb7aa52 23 * Version 1.0.2 2010/11/11
emilmont 1:fdd22bb7aa52 24 * Documentation updated.
emilmont 1:fdd22bb7aa52 25 *
emilmont 1:fdd22bb7aa52 26 * Version 1.0.1 2010/10/05
emilmont 1:fdd22bb7aa52 27 * Production release and review comments incorporated.
emilmont 1:fdd22bb7aa52 28 *
emilmont 1:fdd22bb7aa52 29 * Version 1.0.0 2010/09/20
emilmont 1:fdd22bb7aa52 30 * Production release and review comments incorporated.
emilmont 1:fdd22bb7aa52 31 * ------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 32
emilmont 1:fdd22bb7aa52 33 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 34
emilmont 1:fdd22bb7aa52 35 /**
emilmont 1:fdd22bb7aa52 36 * @addtogroup PID
emilmont 1:fdd22bb7aa52 37 * @{
emilmont 1:fdd22bb7aa52 38 */
emilmont 1:fdd22bb7aa52 39
emilmont 1:fdd22bb7aa52 40 /**
emilmont 1:fdd22bb7aa52 41 * @brief Initialization function for the Q31 PID Control.
emilmont 1:fdd22bb7aa52 42 * @param[in,out] *S points to an instance of the Q31 PID structure.
emilmont 1:fdd22bb7aa52 43 * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
emilmont 1:fdd22bb7aa52 44 * @return none.
emilmont 1:fdd22bb7aa52 45 * \par Description:
emilmont 1:fdd22bb7aa52 46 * \par
emilmont 1:fdd22bb7aa52 47 * The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n
emilmont 1:fdd22bb7aa52 48 * The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>
emilmont 1:fdd22bb7aa52 49 * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
emilmont 1:fdd22bb7aa52 50 * also sets the state variables to all zeros.
emilmont 1:fdd22bb7aa52 51 */
emilmont 1:fdd22bb7aa52 52
emilmont 1:fdd22bb7aa52 53 void arm_pid_init_q31(
emilmont 1:fdd22bb7aa52 54 arm_pid_instance_q31 * S,
emilmont 1:fdd22bb7aa52 55 int32_t resetStateFlag)
emilmont 1:fdd22bb7aa52 56 {
emilmont 1:fdd22bb7aa52 57
emilmont 1:fdd22bb7aa52 58 #ifndef ARM_MATH_CM0
emilmont 1:fdd22bb7aa52 59
emilmont 1:fdd22bb7aa52 60 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 61
emilmont 1:fdd22bb7aa52 62 /* Derived coefficient A0 */
emilmont 1:fdd22bb7aa52 63 S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
emilmont 1:fdd22bb7aa52 64
emilmont 1:fdd22bb7aa52 65 /* Derived coefficient A1 */
emilmont 1:fdd22bb7aa52 66 S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
emilmont 1:fdd22bb7aa52 67
emilmont 1:fdd22bb7aa52 68
emilmont 1:fdd22bb7aa52 69 #else
emilmont 1:fdd22bb7aa52 70
emilmont 1:fdd22bb7aa52 71 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 72
emilmont 1:fdd22bb7aa52 73 q31_t temp;
emilmont 1:fdd22bb7aa52 74
emilmont 1:fdd22bb7aa52 75 /* Derived coefficient A0 */
emilmont 1:fdd22bb7aa52 76 temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
emilmont 1:fdd22bb7aa52 77 S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
emilmont 1:fdd22bb7aa52 78
emilmont 1:fdd22bb7aa52 79 /* Derived coefficient A1 */
emilmont 1:fdd22bb7aa52 80 temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
emilmont 1:fdd22bb7aa52 81 S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
emilmont 1:fdd22bb7aa52 82
emilmont 1:fdd22bb7aa52 83 #endif /* #ifndef ARM_MATH_CM0 */
emilmont 1:fdd22bb7aa52 84
emilmont 1:fdd22bb7aa52 85 /* Derived coefficient A2 */
emilmont 1:fdd22bb7aa52 86 S->A2 = S->Kd;
emilmont 1:fdd22bb7aa52 87
emilmont 1:fdd22bb7aa52 88 /* Check whether state needs reset or not */
emilmont 1:fdd22bb7aa52 89 if(resetStateFlag)
emilmont 1:fdd22bb7aa52 90 {
emilmont 1:fdd22bb7aa52 91 /* Clear the state buffer. The size will be always 3 samples */
emilmont 1:fdd22bb7aa52 92 memset(S->state, 0, 3u * sizeof(q31_t));
emilmont 1:fdd22bb7aa52 93 }
emilmont 1:fdd22bb7aa52 94
emilmont 1:fdd22bb7aa52 95 }
emilmont 1:fdd22bb7aa52 96
emilmont 1:fdd22bb7aa52 97 /**
emilmont 1:fdd22bb7aa52 98 * @} end of PID group
emilmont 1:fdd22bb7aa52 99 */