local for mbed5
sx126x-hal.cpp@0:deaafdfde3bb, 2016-09-06 (annotated)
- Committer:
- GregCr
- Date:
- Tue Sep 06 06:56:46 2016 +0000
- Revision:
- 0:deaafdfde3bb
- Child:
- 1:35d34672a089
Initial commit using Martin's version
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
GregCr | 0:deaafdfde3bb | 1 | /* |
GregCr | 0:deaafdfde3bb | 2 | / _____) _ | | |
GregCr | 0:deaafdfde3bb | 3 | ( (____ _____ ____ _| |_ _____ ____| |__ |
GregCr | 0:deaafdfde3bb | 4 | \____ \| ___ | (_ _) ___ |/ ___) _ \ |
GregCr | 0:deaafdfde3bb | 5 | _____) ) ____| | | || |_| ____( (___| | | | |
GregCr | 0:deaafdfde3bb | 6 | (______/|_____)_|_|_| \__)_____)\____)_| |_| |
GregCr | 0:deaafdfde3bb | 7 | (C)2016 Semtech |
GregCr | 0:deaafdfde3bb | 8 | |
GregCr | 0:deaafdfde3bb | 9 | Description: Handling of the node configuration protocol |
GregCr | 0:deaafdfde3bb | 10 | |
GregCr | 0:deaafdfde3bb | 11 | License: Revised BSD License, see LICENSE.TXT file include in the project |
GregCr | 0:deaafdfde3bb | 12 | |
GregCr | 0:deaafdfde3bb | 13 | Maintainer: Miguel Luis, Gregory Cristian and Matthieu Verdy |
GregCr | 0:deaafdfde3bb | 14 | */ |
GregCr | 0:deaafdfde3bb | 15 | #include "sx1261-hal.h" |
GregCr | 0:deaafdfde3bb | 16 | |
GregCr | 0:deaafdfde3bb | 17 | #define V1A_WORKAROUNDS |
GregCr | 0:deaafdfde3bb | 18 | |
GregCr | 0:deaafdfde3bb | 19 | /*! |
GregCr | 0:deaafdfde3bb | 20 | * \brief Used to block execution waiting for low state on radio busy pin. |
GregCr | 0:deaafdfde3bb | 21 | * Essentially used in SPI communications |
GregCr | 0:deaafdfde3bb | 22 | */ |
GregCr | 0:deaafdfde3bb | 23 | #define WaitBusy( ) while( BUSY == 1 ){ } |
GregCr | 0:deaafdfde3bb | 24 | |
GregCr | 0:deaafdfde3bb | 25 | |
GregCr | 0:deaafdfde3bb | 26 | |
GregCr | 0:deaafdfde3bb | 27 | /*! |
GregCr | 0:deaafdfde3bb | 28 | * \brief Blocking routine for waiting the UART to be writeable |
GregCr | 0:deaafdfde3bb | 29 | * |
GregCr | 0:deaafdfde3bb | 30 | */ |
GregCr | 0:deaafdfde3bb | 31 | #define WaitUartWritable( ) while( RadioUart->writeable( ) == false ){ } |
GregCr | 0:deaafdfde3bb | 32 | |
GregCr | 0:deaafdfde3bb | 33 | /*! |
GregCr | 0:deaafdfde3bb | 34 | * \brief Blocking routine for waiting the UART to be readable |
GregCr | 0:deaafdfde3bb | 35 | * |
GregCr | 0:deaafdfde3bb | 36 | */ |
GregCr | 0:deaafdfde3bb | 37 | #define WaitUartReadable( ) while( RadioUart->readable( ) == false ){ } |
GregCr | 0:deaafdfde3bb | 38 | |
GregCr | 0:deaafdfde3bb | 39 | SX1261Hal::SX1261Hal( PinName mosi, PinName miso, PinName sclk, PinName nss, PinName busy, PinName dio1, PinName dio2, PinName dio3, PinName rst, |
GregCr | 0:deaafdfde3bb | 40 | void ( *txDone )( ), void ( *rxDone )( ), void ( *rxPblSyncWordHeader )( IrqPblSyncHeaderCode_t val ), |
GregCr | 0:deaafdfde3bb | 41 | void ( *rxTxTimeout )( ), void ( *rxError )( IrqErrorCode_t errorCode ), void ( *rangingDone )( IrqRangingCode_t val ), |
GregCr | 0:deaafdfde3bb | 42 | void ( *cadDone )( bool channelActivityDetected ), |
GregCr | 0:deaafdfde3bb | 43 | void ( *onDioIrq )( ) ) |
GregCr | 0:deaafdfde3bb | 44 | : SX1261( txDone, rxDone, rxPblSyncWordHeader, rxTxTimeout, rxError, rangingDone, cadDone, onDioIrq ), |
GregCr | 0:deaafdfde3bb | 45 | RadioNss( nss ), |
GregCr | 0:deaafdfde3bb | 46 | RadioReset( rst ), |
GregCr | 0:deaafdfde3bb | 47 | BUSY( busy ), |
GregCr | 0:deaafdfde3bb | 48 | DIO1( dio1 ), |
GregCr | 0:deaafdfde3bb | 49 | DIO2( dio2 ), |
GregCr | 0:deaafdfde3bb | 50 | DIO3( dio3 ) |
GregCr | 0:deaafdfde3bb | 51 | { |
GregCr | 0:deaafdfde3bb | 52 | RadioSpi = new SPI( mosi, miso, sclk ); |
GregCr | 0:deaafdfde3bb | 53 | RadioUart = NULL; |
GregCr | 0:deaafdfde3bb | 54 | |
GregCr | 0:deaafdfde3bb | 55 | RadioNss = 1; |
GregCr | 0:deaafdfde3bb | 56 | RadioReset = 1; |
GregCr | 0:deaafdfde3bb | 57 | } |
GregCr | 0:deaafdfde3bb | 58 | |
GregCr | 0:deaafdfde3bb | 59 | SX1261Hal::SX1261Hal( PinName tx, PinName rx, PinName busy, PinName dio1, PinName dio2, PinName dio3, PinName rst, |
GregCr | 0:deaafdfde3bb | 60 | void ( *txDone )( ), void ( *rxDone )( ), void ( *rxPblSyncWordHeader )( IrqPblSyncHeaderCode_t val ), |
GregCr | 0:deaafdfde3bb | 61 | void ( *rxTxTimeout )( ), void ( *rxError )( IrqErrorCode_t errorCode ), void ( *rangingDone )( IrqRangingCode_t val ), |
GregCr | 0:deaafdfde3bb | 62 | void ( *cadDone )( bool channelActivityDetected ), |
GregCr | 0:deaafdfde3bb | 63 | void ( *onDioIrq )( ) ) |
GregCr | 0:deaafdfde3bb | 64 | : SX1261( txDone, rxDone, rxPblSyncWordHeader, rxTxTimeout, rxError, rangingDone, cadDone, onDioIrq ), |
GregCr | 0:deaafdfde3bb | 65 | RadioNss( NC ), |
GregCr | 0:deaafdfde3bb | 66 | RadioReset( rst ), |
GregCr | 0:deaafdfde3bb | 67 | BUSY( busy ), |
GregCr | 0:deaafdfde3bb | 68 | DIO1( dio1 ), |
GregCr | 0:deaafdfde3bb | 69 | DIO2( dio2 ), |
GregCr | 0:deaafdfde3bb | 70 | DIO3( dio3 ) |
GregCr | 0:deaafdfde3bb | 71 | { |
GregCr | 0:deaafdfde3bb | 72 | RadioSpi = NULL; |
GregCr | 0:deaafdfde3bb | 73 | RadioUart = new Serial( tx, rx ); |
GregCr | 0:deaafdfde3bb | 74 | RadioReset = 1; |
GregCr | 0:deaafdfde3bb | 75 | } |
GregCr | 0:deaafdfde3bb | 76 | |
GregCr | 0:deaafdfde3bb | 77 | void SX1261Hal::SpiInit( void ) |
GregCr | 0:deaafdfde3bb | 78 | { |
GregCr | 0:deaafdfde3bb | 79 | RadioNss = 1; |
GregCr | 0:deaafdfde3bb | 80 | RadioSpi->format( 8, 0 ); |
GregCr | 0:deaafdfde3bb | 81 | RadioSpi->frequency( SX1261_SPI_FREQ_DEFAULT ); |
GregCr | 0:deaafdfde3bb | 82 | |
GregCr | 0:deaafdfde3bb | 83 | wait( 0.1 ); |
GregCr | 0:deaafdfde3bb | 84 | } |
GregCr | 0:deaafdfde3bb | 85 | |
GregCr | 0:deaafdfde3bb | 86 | void SX1261Hal::UartInit( void ) |
GregCr | 0:deaafdfde3bb | 87 | { |
GregCr | 0:deaafdfde3bb | 88 | RadioUart->format( 9, SerialBase::Even, 1 ); // 8 data bits + 1 even parity bit + 1 stop bit |
GregCr | 0:deaafdfde3bb | 89 | RadioUart->baud( 115200 ); |
GregCr | 0:deaafdfde3bb | 90 | |
GregCr | 0:deaafdfde3bb | 91 | // By default the SX1261 UART is setup to handle bytes MSB first. |
GregCr | 0:deaafdfde3bb | 92 | // In order to setup the radio to use the UART standard way we first send |
GregCr | 0:deaafdfde3bb | 93 | // the equivalent of a WriteRegister with reversed bit order in order to |
GregCr | 0:deaafdfde3bb | 94 | // change the endianness. |
GregCr | 0:deaafdfde3bb | 95 | //@todo |
GregCr | 0:deaafdfde3bb | 96 | /*uint8_t regVal = 0; |
GregCr | 0:deaafdfde3bb | 97 | RadioUart->putc( 0x98 ); // Reversed opcode for read register (0x19) |
GregCr | 0:deaafdfde3bb | 98 | RadioUart->putc( 0x10 ); // Reversed MSB register address (0x08) |
GregCr | 0:deaafdfde3bb | 99 | RadioUart->putc( 0x18 ); // Reversed LSB register address (0x18) |
GregCr | 0:deaafdfde3bb | 100 | RadioUart->putc( 0x80 ); // Reversed value for reading only 1 byte (0x01) |
GregCr | 0:deaafdfde3bb | 101 | regVal = RadioUart->getc( )& 0xF3; // Read reversed value and mask it |
GregCr | 0:deaafdfde3bb | 102 | |
GregCr | 0:deaafdfde3bb | 103 | RadioUart->putc( 0x18 ); // Reversed opcode for read register (0x18) |
GregCr | 0:deaafdfde3bb | 104 | RadioUart->putc( 0x10 ); // Reversed MSB register address (0x08) |
GregCr | 0:deaafdfde3bb | 105 | RadioUart->putc( 0x18 ); // Reversed LSB register address (0x18) |
GregCr | 0:deaafdfde3bb | 106 | RadioUart->putc( 0x80 ); // Reversed value for writing only 1 byte (0x01) |
GregCr | 0:deaafdfde3bb | 107 | RadioUart->putc( regVal ); // The new value of the register*/ |
GregCr | 0:deaafdfde3bb | 108 | |
GregCr | 0:deaafdfde3bb | 109 | // After this point, the UART is running standard mode: 8 data bit, 1 even |
GregCr | 0:deaafdfde3bb | 110 | // parity bit, 1 stop bit, 115200 baud, LSB first |
GregCr | 0:deaafdfde3bb | 111 | wait_us( 10 ); |
GregCr | 0:deaafdfde3bb | 112 | } |
GregCr | 0:deaafdfde3bb | 113 | |
GregCr | 0:deaafdfde3bb | 114 | void SX1261Hal::IoIrqInit( DioIrqHandler irqHandler ) |
GregCr | 0:deaafdfde3bb | 115 | { |
GregCr | 0:deaafdfde3bb | 116 | assert_param( RadioSpi != 0 || RadioUart != 0 ); |
GregCr | 0:deaafdfde3bb | 117 | if( RadioSpi != NULL ) |
GregCr | 0:deaafdfde3bb | 118 | { |
GregCr | 0:deaafdfde3bb | 119 | SpiInit( ); |
GregCr | 0:deaafdfde3bb | 120 | } |
GregCr | 0:deaafdfde3bb | 121 | if( RadioUart != NULL ) |
GregCr | 0:deaafdfde3bb | 122 | { |
GregCr | 0:deaafdfde3bb | 123 | UartInit( ); |
GregCr | 0:deaafdfde3bb | 124 | } |
GregCr | 0:deaafdfde3bb | 125 | |
GregCr | 0:deaafdfde3bb | 126 | BUSY.mode( PullDown ); |
GregCr | 0:deaafdfde3bb | 127 | DIO1.mode( PullDown ); |
GregCr | 0:deaafdfde3bb | 128 | DIO2.mode( PullDown ); |
GregCr | 0:deaafdfde3bb | 129 | DIO3.mode( PullDown ); |
GregCr | 0:deaafdfde3bb | 130 | |
GregCr | 0:deaafdfde3bb | 131 | DIO1.rise( this, static_cast <Trigger>( irqHandler ) ); |
GregCr | 0:deaafdfde3bb | 132 | DIO2.rise( this, static_cast <Trigger>( irqHandler ) ); |
GregCr | 0:deaafdfde3bb | 133 | DIO3.rise( this, static_cast <Trigger>( irqHandler ) ); |
GregCr | 0:deaafdfde3bb | 134 | } |
GregCr | 0:deaafdfde3bb | 135 | |
GregCr | 0:deaafdfde3bb | 136 | void SX1261Hal::Reset( void ) |
GregCr | 0:deaafdfde3bb | 137 | { |
GregCr | 0:deaafdfde3bb | 138 | __disable_irq( ); |
GregCr | 0:deaafdfde3bb | 139 | wait( 0.05 ); |
GregCr | 0:deaafdfde3bb | 140 | RadioReset = 0; |
GregCr | 0:deaafdfde3bb | 141 | wait( 0.1 ); |
GregCr | 0:deaafdfde3bb | 142 | RadioReset = 1; |
GregCr | 0:deaafdfde3bb | 143 | wait( 0.05 ); |
GregCr | 0:deaafdfde3bb | 144 | __enable_irq( ); |
GregCr | 0:deaafdfde3bb | 145 | } |
GregCr | 0:deaafdfde3bb | 146 | |
GregCr | 0:deaafdfde3bb | 147 | void SX1261Hal::ClearInstructionRam( void ) |
GregCr | 0:deaafdfde3bb | 148 | { |
GregCr | 0:deaafdfde3bb | 149 | // Clearing the instruction RAM is writing 0x00s on every bytes of the |
GregCr | 0:deaafdfde3bb | 150 | // instruction RAM |
GregCr | 0:deaafdfde3bb | 151 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 152 | |
GregCr | 0:deaafdfde3bb | 153 | if( RadioSpi != NULL ) |
GregCr | 0:deaafdfde3bb | 154 | { |
GregCr | 0:deaafdfde3bb | 155 | RadioNss = 0; |
GregCr | 0:deaafdfde3bb | 156 | RadioSpi->write( RADIO_WRITE_REGISTER ); // Send write register opcode |
GregCr | 0:deaafdfde3bb | 157 | RadioSpi->write( ( IRAM_START_ADDRESS >> 8 ) & 0x00FF ); // Send MSB of the first byte address |
GregCr | 0:deaafdfde3bb | 158 | RadioSpi->write( IRAM_START_ADDRESS & 0x00FF ); // Send LSB of the first byte address |
GregCr | 0:deaafdfde3bb | 159 | |
GregCr | 0:deaafdfde3bb | 160 | for( uint16_t address = IRAM_START_ADDRESS; address < ( IRAM_START_ADDRESS + IRAM_SIZE ); address++ ) |
GregCr | 0:deaafdfde3bb | 161 | { |
GregCr | 0:deaafdfde3bb | 162 | RadioSpi->write( 0x00 ); |
GregCr | 0:deaafdfde3bb | 163 | } |
GregCr | 0:deaafdfde3bb | 164 | RadioNss = 1; |
GregCr | 0:deaafdfde3bb | 165 | } |
GregCr | 0:deaafdfde3bb | 166 | if( RadioUart != NULL ) |
GregCr | 0:deaafdfde3bb | 167 | { |
GregCr | 0:deaafdfde3bb | 168 | // We can't erase the whole instruction RAM in one shot with UART |
GregCr | 0:deaafdfde3bb | 169 | // because we need to send the length of register to erase |
GregCr | 0:deaafdfde3bb | 170 | // and this length is coded on 1 byte. |
GregCr | 0:deaafdfde3bb | 171 | for( uint16_t address = IRAM_START_ADDRESS; address < ( IRAM_START_ADDRESS + IRAM_SIZE ); address++ ) |
GregCr | 0:deaafdfde3bb | 172 | { |
GregCr | 0:deaafdfde3bb | 173 | WriteRegister( address, 0 ); |
GregCr | 0:deaafdfde3bb | 174 | } |
GregCr | 0:deaafdfde3bb | 175 | } |
GregCr | 0:deaafdfde3bb | 176 | |
GregCr | 0:deaafdfde3bb | 177 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 178 | } |
GregCr | 0:deaafdfde3bb | 179 | |
GregCr | 0:deaafdfde3bb | 180 | void SX1261Hal::Wakeup( void ) |
GregCr | 0:deaafdfde3bb | 181 | { |
GregCr | 0:deaafdfde3bb | 182 | __disable_irq( ); |
GregCr | 0:deaafdfde3bb | 183 | |
GregCr | 0:deaafdfde3bb | 184 | //Don't wait for DIO0 here |
GregCr | 0:deaafdfde3bb | 185 | |
GregCr | 0:deaafdfde3bb | 186 | if( RadioSpi != NULL ) |
GregCr | 0:deaafdfde3bb | 187 | { |
GregCr | 0:deaafdfde3bb | 188 | RadioNss = 0; |
GregCr | 0:deaafdfde3bb | 189 | RadioSpi->write( RADIO_GET_STATUS ); |
GregCr | 0:deaafdfde3bb | 190 | RadioSpi->write( 0 ); |
GregCr | 0:deaafdfde3bb | 191 | RadioNss = 1; |
GregCr | 0:deaafdfde3bb | 192 | } |
GregCr | 0:deaafdfde3bb | 193 | if( RadioUart != NULL ) |
GregCr | 0:deaafdfde3bb | 194 | { |
GregCr | 0:deaafdfde3bb | 195 | RadioUart->putc( RADIO_GET_STATUS ); |
GregCr | 0:deaafdfde3bb | 196 | WaitUartReadable( ); |
GregCr | 0:deaafdfde3bb | 197 | RadioUart->getc( ); |
GregCr | 0:deaafdfde3bb | 198 | } |
GregCr | 0:deaafdfde3bb | 199 | |
GregCr | 0:deaafdfde3bb | 200 | // Wait for chip to be ready. |
GregCr | 0:deaafdfde3bb | 201 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 202 | |
GregCr | 0:deaafdfde3bb | 203 | #ifdef V1A_WORKAROUNDS |
GregCr | 0:deaafdfde3bb | 204 | //V1a workaround: rc64k not enabled after warm_start, rtc_wake_up=0 |
GregCr | 0:deaafdfde3bb | 205 | WriteRegister(0x91e, ReadRegister(0x91e) | 0x40); |
GregCr | 0:deaafdfde3bb | 206 | //rc13m enable bug |
GregCr | 0:deaafdfde3bb | 207 | uint8_t txFallbackFunc[2]; |
GregCr | 0:deaafdfde3bb | 208 | //set to ModeTx2Rc addr = 0fce, so rc is not enabled before ramp down |
GregCr | 0:deaafdfde3bb | 209 | txFallbackFunc[0] = 0x0f; |
GregCr | 0:deaafdfde3bb | 210 | txFallbackFunc[1] = 0xce; |
GregCr | 0:deaafdfde3bb | 211 | WriteRegister(0x00CC, txFallbackFunc, 2); |
GregCr | 0:deaafdfde3bb | 212 | #endif |
GregCr | 0:deaafdfde3bb | 213 | |
GregCr | 0:deaafdfde3bb | 214 | __enable_irq( ); |
GregCr | 0:deaafdfde3bb | 215 | } |
GregCr | 0:deaafdfde3bb | 216 | |
GregCr | 0:deaafdfde3bb | 217 | void SX1261Hal::WriteCommand( RadioCommands_t command, uint8_t *buffer, uint16_t size ) |
GregCr | 0:deaafdfde3bb | 218 | { |
GregCr | 0:deaafdfde3bb | 219 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 220 | |
GregCr | 0:deaafdfde3bb | 221 | if( RadioSpi != NULL ) |
GregCr | 0:deaafdfde3bb | 222 | { |
GregCr | 0:deaafdfde3bb | 223 | RadioNss = 0; |
GregCr | 0:deaafdfde3bb | 224 | RadioSpi->write( ( uint8_t )command ); |
GregCr | 0:deaafdfde3bb | 225 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 226 | { |
GregCr | 0:deaafdfde3bb | 227 | RadioSpi->write( buffer[i] ); |
GregCr | 0:deaafdfde3bb | 228 | } |
GregCr | 0:deaafdfde3bb | 229 | RadioNss = 1; |
GregCr | 0:deaafdfde3bb | 230 | } |
GregCr | 0:deaafdfde3bb | 231 | if( RadioUart != NULL ) |
GregCr | 0:deaafdfde3bb | 232 | { |
GregCr | 0:deaafdfde3bb | 233 | RadioUart->putc( command ); |
GregCr | 0:deaafdfde3bb | 234 | if( size > 0 ) |
GregCr | 0:deaafdfde3bb | 235 | { |
GregCr | 0:deaafdfde3bb | 236 | RadioUart->putc( size ); |
GregCr | 0:deaafdfde3bb | 237 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 238 | { |
GregCr | 0:deaafdfde3bb | 239 | RadioUart->putc( buffer[i] ); |
GregCr | 0:deaafdfde3bb | 240 | } |
GregCr | 0:deaafdfde3bb | 241 | } |
GregCr | 0:deaafdfde3bb | 242 | } |
GregCr | 0:deaafdfde3bb | 243 | |
GregCr | 0:deaafdfde3bb | 244 | if( command != RADIO_SET_SLEEP ) |
GregCr | 0:deaafdfde3bb | 245 | { |
GregCr | 0:deaafdfde3bb | 246 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 247 | } |
GregCr | 0:deaafdfde3bb | 248 | } |
GregCr | 0:deaafdfde3bb | 249 | |
GregCr | 0:deaafdfde3bb | 250 | void SX1261Hal::ReadCommand( RadioCommands_t command, uint8_t *buffer, uint16_t size ) |
GregCr | 0:deaafdfde3bb | 251 | { |
GregCr | 0:deaafdfde3bb | 252 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 253 | |
GregCr | 0:deaafdfde3bb | 254 | if( RadioSpi != NULL ) |
GregCr | 0:deaafdfde3bb | 255 | { |
GregCr | 0:deaafdfde3bb | 256 | RadioNss = 0; |
GregCr | 0:deaafdfde3bb | 257 | RadioSpi->write( ( uint8_t )command ); |
GregCr | 0:deaafdfde3bb | 258 | RadioSpi->write( 0 ); |
GregCr | 0:deaafdfde3bb | 259 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 260 | { |
GregCr | 0:deaafdfde3bb | 261 | buffer[i] = RadioSpi->write( 0 ); |
GregCr | 0:deaafdfde3bb | 262 | } |
GregCr | 0:deaafdfde3bb | 263 | RadioNss = 1; |
GregCr | 0:deaafdfde3bb | 264 | } |
GregCr | 0:deaafdfde3bb | 265 | else if( RadioUart != NULL ) |
GregCr | 0:deaafdfde3bb | 266 | { |
GregCr | 0:deaafdfde3bb | 267 | RadioUart->putc( command ); |
GregCr | 0:deaafdfde3bb | 268 | |
GregCr | 0:deaafdfde3bb | 269 | // Behavior on the UART is different depending of the opcode command |
GregCr | 0:deaafdfde3bb | 270 | if( ( command == RADIO_GET_PACKETTYPE ) || |
GregCr | 0:deaafdfde3bb | 271 | ( command == RADIO_GET_RXBUFFERSTATUS ) || |
GregCr | 0:deaafdfde3bb | 272 | ( command == RADIO_GET_RSSIINST ) || |
GregCr | 0:deaafdfde3bb | 273 | ( command == RADIO_GET_PACKETSTATUS ) || |
GregCr | 0:deaafdfde3bb | 274 | ( command == RADIO_GET_IRQSTATUS ) ) |
GregCr | 0:deaafdfde3bb | 275 | { |
GregCr | 0:deaafdfde3bb | 276 | RadioUart->putc( size ); |
GregCr | 0:deaafdfde3bb | 277 | } |
GregCr | 0:deaafdfde3bb | 278 | |
GregCr | 0:deaafdfde3bb | 279 | WaitUartReadable( ); |
GregCr | 0:deaafdfde3bb | 280 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 281 | { |
GregCr | 0:deaafdfde3bb | 282 | buffer[i] = RadioUart->getc( ); |
GregCr | 0:deaafdfde3bb | 283 | } |
GregCr | 0:deaafdfde3bb | 284 | } |
GregCr | 0:deaafdfde3bb | 285 | else |
GregCr | 0:deaafdfde3bb | 286 | { |
GregCr | 0:deaafdfde3bb | 287 | buffer[0] = 0xFF; |
GregCr | 0:deaafdfde3bb | 288 | } |
GregCr | 0:deaafdfde3bb | 289 | |
GregCr | 0:deaafdfde3bb | 290 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 291 | } |
GregCr | 0:deaafdfde3bb | 292 | |
GregCr | 0:deaafdfde3bb | 293 | void SX1261Hal::WriteRegister( uint16_t address, uint8_t *buffer, uint16_t size ) |
GregCr | 0:deaafdfde3bb | 294 | { |
GregCr | 0:deaafdfde3bb | 295 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 296 | |
GregCr | 0:deaafdfde3bb | 297 | if( RadioSpi != NULL ) |
GregCr | 0:deaafdfde3bb | 298 | { |
GregCr | 0:deaafdfde3bb | 299 | RadioNss = 0; |
GregCr | 0:deaafdfde3bb | 300 | RadioSpi->write( RADIO_WRITE_REGISTER ); |
GregCr | 0:deaafdfde3bb | 301 | RadioSpi->write( ( address & 0xFF00 ) >> 8 ); |
GregCr | 0:deaafdfde3bb | 302 | RadioSpi->write( address & 0x00FF ); |
GregCr | 0:deaafdfde3bb | 303 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 304 | { |
GregCr | 0:deaafdfde3bb | 305 | RadioSpi->write( buffer[i] ); |
GregCr | 0:deaafdfde3bb | 306 | } |
GregCr | 0:deaafdfde3bb | 307 | RadioNss = 1; |
GregCr | 0:deaafdfde3bb | 308 | } |
GregCr | 0:deaafdfde3bb | 309 | if( RadioUart != NULL ) |
GregCr | 0:deaafdfde3bb | 310 | { |
GregCr | 0:deaafdfde3bb | 311 | RadioUart->putc( RADIO_WRITE_REGISTER ); |
GregCr | 0:deaafdfde3bb | 312 | RadioUart->putc( ( address & 0xFF00 ) >> 8 ); |
GregCr | 0:deaafdfde3bb | 313 | RadioUart->putc( address & 0x00FF ); |
GregCr | 0:deaafdfde3bb | 314 | RadioUart->putc( size ); |
GregCr | 0:deaafdfde3bb | 315 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 316 | { |
GregCr | 0:deaafdfde3bb | 317 | RadioUart->putc( buffer[i] ); |
GregCr | 0:deaafdfde3bb | 318 | } |
GregCr | 0:deaafdfde3bb | 319 | } |
GregCr | 0:deaafdfde3bb | 320 | |
GregCr | 0:deaafdfde3bb | 321 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 322 | } |
GregCr | 0:deaafdfde3bb | 323 | |
GregCr | 0:deaafdfde3bb | 324 | void SX1261Hal::WriteRegisterNoBusy( uint16_t address, uint8_t *buffer, uint16_t size ) |
GregCr | 0:deaafdfde3bb | 325 | { |
GregCr | 0:deaafdfde3bb | 326 | if( RadioSpi != NULL ) |
GregCr | 0:deaafdfde3bb | 327 | { |
GregCr | 0:deaafdfde3bb | 328 | RadioNss = 0; |
GregCr | 0:deaafdfde3bb | 329 | RadioSpi->write( RADIO_WRITE_REGISTER ); |
GregCr | 0:deaafdfde3bb | 330 | RadioSpi->write( ( address & 0xFF00 ) >> 8 ); |
GregCr | 0:deaafdfde3bb | 331 | RadioSpi->write( address & 0x00FF ); |
GregCr | 0:deaafdfde3bb | 332 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 333 | { |
GregCr | 0:deaafdfde3bb | 334 | RadioSpi->write( buffer[i] ); |
GregCr | 0:deaafdfde3bb | 335 | } |
GregCr | 0:deaafdfde3bb | 336 | RadioNss = 1; |
GregCr | 0:deaafdfde3bb | 337 | } |
GregCr | 0:deaafdfde3bb | 338 | if( RadioUart != NULL ) |
GregCr | 0:deaafdfde3bb | 339 | { |
GregCr | 0:deaafdfde3bb | 340 | RadioUart->putc( RADIO_WRITE_REGISTER ); |
GregCr | 0:deaafdfde3bb | 341 | RadioUart->putc( ( address & 0xFF00 ) >> 8 ); |
GregCr | 0:deaafdfde3bb | 342 | RadioUart->putc( address & 0x00FF ); |
GregCr | 0:deaafdfde3bb | 343 | RadioUart->putc( size ); |
GregCr | 0:deaafdfde3bb | 344 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 345 | { |
GregCr | 0:deaafdfde3bb | 346 | RadioUart->putc( buffer[i] ); |
GregCr | 0:deaafdfde3bb | 347 | } |
GregCr | 0:deaafdfde3bb | 348 | } |
GregCr | 0:deaafdfde3bb | 349 | } |
GregCr | 0:deaafdfde3bb | 350 | |
GregCr | 0:deaafdfde3bb | 351 | void SX1261Hal::WriteRegister( uint16_t address, uint8_t value ) |
GregCr | 0:deaafdfde3bb | 352 | { |
GregCr | 0:deaafdfde3bb | 353 | WriteRegister( address, &value, 1 ); |
GregCr | 0:deaafdfde3bb | 354 | } |
GregCr | 0:deaafdfde3bb | 355 | |
GregCr | 0:deaafdfde3bb | 356 | void SX1261Hal::WriteRegisterNoBusy( uint16_t address, uint8_t value ) |
GregCr | 0:deaafdfde3bb | 357 | { |
GregCr | 0:deaafdfde3bb | 358 | WriteRegisterNoBusy( address, &value, 1 ); |
GregCr | 0:deaafdfde3bb | 359 | } |
GregCr | 0:deaafdfde3bb | 360 | |
GregCr | 0:deaafdfde3bb | 361 | void SX1261Hal::ReadRegister( uint16_t address, uint8_t *buffer, uint16_t size ) |
GregCr | 0:deaafdfde3bb | 362 | { |
GregCr | 0:deaafdfde3bb | 363 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 364 | |
GregCr | 0:deaafdfde3bb | 365 | if( RadioSpi != NULL ) |
GregCr | 0:deaafdfde3bb | 366 | { |
GregCr | 0:deaafdfde3bb | 367 | RadioNss = 0; |
GregCr | 0:deaafdfde3bb | 368 | RadioSpi->write( RADIO_READ_REGISTER ); |
GregCr | 0:deaafdfde3bb | 369 | RadioSpi->write( ( address & 0xFF00 ) >> 8 ); |
GregCr | 0:deaafdfde3bb | 370 | RadioSpi->write( address & 0x00FF ); |
GregCr | 0:deaafdfde3bb | 371 | RadioSpi->write( 0 ); |
GregCr | 0:deaafdfde3bb | 372 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 373 | { |
GregCr | 0:deaafdfde3bb | 374 | buffer[i] = RadioSpi->write( 0 ); |
GregCr | 0:deaafdfde3bb | 375 | } |
GregCr | 0:deaafdfde3bb | 376 | RadioNss = 1; |
GregCr | 0:deaafdfde3bb | 377 | } |
GregCr | 0:deaafdfde3bb | 378 | if( RadioUart != NULL ) |
GregCr | 0:deaafdfde3bb | 379 | { |
GregCr | 0:deaafdfde3bb | 380 | RadioUart->putc( RADIO_READ_REGISTER ); |
GregCr | 0:deaafdfde3bb | 381 | RadioUart->putc( ( address & 0xFF00 ) >> 8 ); |
GregCr | 0:deaafdfde3bb | 382 | RadioUart->putc( address & 0x00FF ); |
GregCr | 0:deaafdfde3bb | 383 | RadioUart->putc( size ); |
GregCr | 0:deaafdfde3bb | 384 | WaitUartReadable( ); |
GregCr | 0:deaafdfde3bb | 385 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 386 | { |
GregCr | 0:deaafdfde3bb | 387 | buffer[i] = RadioUart->getc( ); |
GregCr | 0:deaafdfde3bb | 388 | } |
GregCr | 0:deaafdfde3bb | 389 | } |
GregCr | 0:deaafdfde3bb | 390 | |
GregCr | 0:deaafdfde3bb | 391 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 392 | } |
GregCr | 0:deaafdfde3bb | 393 | |
GregCr | 0:deaafdfde3bb | 394 | void SX1261Hal::ReadRegisterNoBusy( uint16_t address, uint8_t *buffer, uint16_t size ) |
GregCr | 0:deaafdfde3bb | 395 | { |
GregCr | 0:deaafdfde3bb | 396 | |
GregCr | 0:deaafdfde3bb | 397 | if( RadioSpi != NULL ) |
GregCr | 0:deaafdfde3bb | 398 | { |
GregCr | 0:deaafdfde3bb | 399 | RadioNss = 0; |
GregCr | 0:deaafdfde3bb | 400 | RadioSpi->write( RADIO_READ_REGISTER ); |
GregCr | 0:deaafdfde3bb | 401 | RadioSpi->write( ( address & 0xFF00 ) >> 8 ); |
GregCr | 0:deaafdfde3bb | 402 | RadioSpi->write( address & 0x00FF ); |
GregCr | 0:deaafdfde3bb | 403 | RadioSpi->write( 0 ); |
GregCr | 0:deaafdfde3bb | 404 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 405 | { |
GregCr | 0:deaafdfde3bb | 406 | buffer[i] = RadioSpi->write( 0 ); |
GregCr | 0:deaafdfde3bb | 407 | } |
GregCr | 0:deaafdfde3bb | 408 | RadioNss = 1; |
GregCr | 0:deaafdfde3bb | 409 | } |
GregCr | 0:deaafdfde3bb | 410 | if( RadioUart != NULL ) |
GregCr | 0:deaafdfde3bb | 411 | { |
GregCr | 0:deaafdfde3bb | 412 | RadioUart->putc( RADIO_READ_REGISTER ); |
GregCr | 0:deaafdfde3bb | 413 | RadioUart->putc( ( address & 0xFF00 ) >> 8 ); |
GregCr | 0:deaafdfde3bb | 414 | RadioUart->putc( address & 0x00FF ); |
GregCr | 0:deaafdfde3bb | 415 | RadioUart->putc( size ); |
GregCr | 0:deaafdfde3bb | 416 | WaitUartReadable( ); |
GregCr | 0:deaafdfde3bb | 417 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 418 | { |
GregCr | 0:deaafdfde3bb | 419 | buffer[i] = RadioUart->getc( ); |
GregCr | 0:deaafdfde3bb | 420 | } |
GregCr | 0:deaafdfde3bb | 421 | } |
GregCr | 0:deaafdfde3bb | 422 | |
GregCr | 0:deaafdfde3bb | 423 | } |
GregCr | 0:deaafdfde3bb | 424 | |
GregCr | 0:deaafdfde3bb | 425 | uint8_t SX1261Hal::ReadRegister( uint16_t address ) |
GregCr | 0:deaafdfde3bb | 426 | { |
GregCr | 0:deaafdfde3bb | 427 | uint8_t data; |
GregCr | 0:deaafdfde3bb | 428 | |
GregCr | 0:deaafdfde3bb | 429 | ReadRegister( address, &data, 1 ); |
GregCr | 0:deaafdfde3bb | 430 | return data; |
GregCr | 0:deaafdfde3bb | 431 | } |
GregCr | 0:deaafdfde3bb | 432 | |
GregCr | 0:deaafdfde3bb | 433 | uint8_t SX1261Hal::ReadRegisterNoBusy( uint16_t address ) |
GregCr | 0:deaafdfde3bb | 434 | { |
GregCr | 0:deaafdfde3bb | 435 | uint8_t data; |
GregCr | 0:deaafdfde3bb | 436 | |
GregCr | 0:deaafdfde3bb | 437 | ReadRegisterNoBusy( address, &data, 1 ); |
GregCr | 0:deaafdfde3bb | 438 | return data; |
GregCr | 0:deaafdfde3bb | 439 | } |
GregCr | 0:deaafdfde3bb | 440 | |
GregCr | 0:deaafdfde3bb | 441 | void SX1261Hal::WriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) |
GregCr | 0:deaafdfde3bb | 442 | { |
GregCr | 0:deaafdfde3bb | 443 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 444 | |
GregCr | 0:deaafdfde3bb | 445 | if( RadioSpi != NULL ) |
GregCr | 0:deaafdfde3bb | 446 | { |
GregCr | 0:deaafdfde3bb | 447 | RadioNss = 0; |
GregCr | 0:deaafdfde3bb | 448 | RadioSpi->write( RADIO_WRITE_BUFFER ); |
GregCr | 0:deaafdfde3bb | 449 | RadioSpi->write( offset ); |
GregCr | 0:deaafdfde3bb | 450 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 451 | { |
GregCr | 0:deaafdfde3bb | 452 | RadioSpi->write( buffer[i] ); |
GregCr | 0:deaafdfde3bb | 453 | } |
GregCr | 0:deaafdfde3bb | 454 | RadioNss = 1; |
GregCr | 0:deaafdfde3bb | 455 | } |
GregCr | 0:deaafdfde3bb | 456 | if( RadioUart != NULL ) |
GregCr | 0:deaafdfde3bb | 457 | { |
GregCr | 0:deaafdfde3bb | 458 | RadioUart->putc( RADIO_WRITE_BUFFER ); |
GregCr | 0:deaafdfde3bb | 459 | RadioUart->putc( offset ); |
GregCr | 0:deaafdfde3bb | 460 | RadioUart->putc( size ); |
GregCr | 0:deaafdfde3bb | 461 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 462 | { |
GregCr | 0:deaafdfde3bb | 463 | RadioUart->putc( buffer[i] ); |
GregCr | 0:deaafdfde3bb | 464 | } |
GregCr | 0:deaafdfde3bb | 465 | } |
GregCr | 0:deaafdfde3bb | 466 | |
GregCr | 0:deaafdfde3bb | 467 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 468 | } |
GregCr | 0:deaafdfde3bb | 469 | |
GregCr | 0:deaafdfde3bb | 470 | void SX1261Hal::ReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) |
GregCr | 0:deaafdfde3bb | 471 | { |
GregCr | 0:deaafdfde3bb | 472 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 473 | |
GregCr | 0:deaafdfde3bb | 474 | if( RadioSpi != NULL ) |
GregCr | 0:deaafdfde3bb | 475 | { |
GregCr | 0:deaafdfde3bb | 476 | RadioNss = 0; |
GregCr | 0:deaafdfde3bb | 477 | RadioSpi->write( RADIO_READ_BUFFER ); |
GregCr | 0:deaafdfde3bb | 478 | RadioSpi->write( offset ); |
GregCr | 0:deaafdfde3bb | 479 | RadioSpi->write( 0 ); |
GregCr | 0:deaafdfde3bb | 480 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 481 | { |
GregCr | 0:deaafdfde3bb | 482 | buffer[i] = RadioSpi->write( 0 ); |
GregCr | 0:deaafdfde3bb | 483 | } |
GregCr | 0:deaafdfde3bb | 484 | RadioNss = 1; |
GregCr | 0:deaafdfde3bb | 485 | } |
GregCr | 0:deaafdfde3bb | 486 | if( RadioUart != NULL ) |
GregCr | 0:deaafdfde3bb | 487 | { |
GregCr | 0:deaafdfde3bb | 488 | RadioUart->putc( RADIO_READ_BUFFER ); |
GregCr | 0:deaafdfde3bb | 489 | RadioUart->putc( offset ); |
GregCr | 0:deaafdfde3bb | 490 | RadioUart->putc( size ); |
GregCr | 0:deaafdfde3bb | 491 | WaitUartReadable( ); |
GregCr | 0:deaafdfde3bb | 492 | for( uint16_t i = 0; i < size; i++ ) |
GregCr | 0:deaafdfde3bb | 493 | { |
GregCr | 0:deaafdfde3bb | 494 | buffer[i] = RadioUart->getc( ); |
GregCr | 0:deaafdfde3bb | 495 | } |
GregCr | 0:deaafdfde3bb | 496 | } |
GregCr | 0:deaafdfde3bb | 497 | |
GregCr | 0:deaafdfde3bb | 498 | WaitBusy( ); |
GregCr | 0:deaafdfde3bb | 499 | } |
GregCr | 0:deaafdfde3bb | 500 | |
GregCr | 0:deaafdfde3bb | 501 | uint8_t SX1261Hal::GetDioStatus( void ) |
GregCr | 0:deaafdfde3bb | 502 | { |
GregCr | 0:deaafdfde3bb | 503 | return ( DIO3 << 3 ) | ( DIO2 << 2 ) | ( DIO1 << 1 ) | ( BUSY << 0 ); |
GregCr | 0:deaafdfde3bb | 504 | } |
GregCr | 0:deaafdfde3bb | 505 | |
GregCr | 0:deaafdfde3bb | 506 |