WIZnet / WIZnetInterface_namespace

WIZnetInterface using namespace

Dependents:   DualNetworkInterface-Basic

Fork of WIZnetInterface by WIZnet

arch/int/W7500x_toe.cpp@20:3e61863c1f67, 2015-07-14 (annotated)

Committer:
SteveKim
Date:
Tue Jul 14 10:16:16 2015 +0000
Revision:
20:3e61863c1f67
Parent:
19:d8773cd4edc5 
Dual Network Interface for mbed;  - WIZwiki-W7500;  - ESP8266

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Soohwan Kim 0:6f28332c466f 1 /* Copyright (C) 2012 mbed.org, MIT License
Soohwan Kim 0:6f28332c466f 2 *
Soohwan Kim 0:6f28332c466f 3 * and associated documentation files (the "Software"), to deal in the Software without restriction,
Soohwan Kim 0:6f28332c466f 4 * including without limitation the rights to use, copy, modify, merge, publish, distribute,
Soohwan Kim 0:6f28332c466f 5 * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
Soohwan Kim 0:6f28332c466f 6 * furnished to do so, subject to the following conditions:
Soohwan Kim 0:6f28332c466f 7 *
Soohwan Kim 0:6f28332c466f 8 * The above copyright notice and this permission notice shall be included in all copies or
Soohwan Kim 0:6f28332c466f 9 * substantial portions of the Software.
Soohwan Kim 0:6f28332c466f 10 *
Soohwan Kim 0:6f28332c466f 11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
Soohwan Kim 0:6f28332c466f 12 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
Soohwan Kim 0:6f28332c466f 13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
Soohwan Kim 0:6f28332c466f 14 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Soohwan Kim 0:6f28332c466f 15 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Soohwan Kim 0:6f28332c466f 16 */
SteveKim 20:3e61863c1f67 17 #include "eth_arch.hpp"
Soohwan Kim 8:4c02de1dbf3a 18 #if defined(TARGET_WIZwiki_W7500)
Soohwan Kim 0:6f28332c466f 19
Soohwan Kim 0:6f28332c466f 20 #include "mbed.h"
Soohwan Kim 0:6f28332c466f 21 #include "mbed_debug.h"
SteveKim 20:3e61863c1f67 22 #include "DNSClient.hpp"
Soohwan Kim 0:6f28332c466f 23
SteveKim 20:3e61863c1f67 24 using namespace wiznet_space;
Soohwan Kim 0:6f28332c466f 25
Soohwan Kim 0:6f28332c466f 26 /*
Soohwan Kim 0:6f28332c466f 27 * MDIO via GPIO
Soohwan Kim 0:6f28332c466f 28 * mdio via gpio is supported and related functions as follows.
Soohwan Kim 0:6f28332c466f 29 * - mdio_init(),mdio_read(),mdio_write()
Soohwan Kim 0:6f28332c466f 30 * - input_MDIO(),output_MDIO(),turnaroud_MDIO(),idle_MDIO()
Soohwan Kim 0:6f28332c466f 31 * called by ethernet_link() and ethernet_set_link()
Soohwan Kim 0:6f28332c466f 32 */
Soohwan Kim 0:6f28332c466f 33 #define MDIO GPIO_Pin_14
Soohwan Kim 0:6f28332c466f 34 #define MDC GPIO_Pin_15
Soohwan Kim 0:6f28332c466f 35 #define GPIO_MDC GPIOB
Soohwan Kim 0:6f28332c466f 36 #define PHY_ADDR_IP101G 0x07
Soohwan Kim 0:6f28332c466f 37 #define PHY_ADDR PHY_ADDR_IP101G
Soohwan Kim 0:6f28332c466f 38 #define SVAL 0x2 //right shift val = 2
Soohwan Kim 0:6f28332c466f 39 #define PHYREG_CONTROL 0x0 //Control Register address (Contorl basic register)
Soohwan Kim 0:6f28332c466f 40 #define PHYREG_STATUS 0x1 //Status Register address (Status basic register)
Soohwan Kim 0:6f28332c466f 41 #define CNTL_DUPLEX (0x01ul<< 7)
Soohwan Kim 0:6f28332c466f 42 #define CNTL_AUTONEGO (0x01ul<<11)
Soohwan Kim 0:6f28332c466f 43 #define CNTL_SPEED (0x01ul<<12)
Soohwan Kim 0:6f28332c466f 44 #define MDC_WAIT (1)
Soohwan Kim 0:6f28332c466f 45 void mdio_init(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin_MDC, uint16_t GPIO_Pin_MDIO);
Soohwan Kim 0:6f28332c466f 46 void mdio_write(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr, uint32_t val);
Soohwan Kim 0:6f28332c466f 47 uint32_t mdio_read(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr);
Soohwan Kim 0:6f28332c466f 48
Soohwan Kim 0:6f28332c466f 49 WIZnet_Chip* WIZnet_Chip::inst;
Soohwan Kim 0:6f28332c466f 50
Soohwan Kim 0:6f28332c466f 51 WIZnet_Chip::WIZnet_Chip()
Soohwan Kim 0:6f28332c466f 52 {
Soohwan Kim 0:6f28332c466f 53 inst = this;
Soohwan Kim 0:6f28332c466f 54 }
Soohwan Kim 0:6f28332c466f 55
Soohwan Kim 8:4c02de1dbf3a 56 bool WIZnet_Chip::setmac()
Soohwan Kim 8:4c02de1dbf3a 57 {
Soohwan Kim 8:4c02de1dbf3a 58
Soohwan Kim 8:4c02de1dbf3a 59 for (int i =0; i < 6; i++) reg_wr<uint8_t>(SHAR+i, mac[i]);
Soohwan Kim 8:4c02de1dbf3a 60
Soohwan Kim 8:4c02de1dbf3a 61 return true;
Soohwan Kim 8:4c02de1dbf3a 62 }
Soohwan Kim 8:4c02de1dbf3a 63
Soohwan Kim 0:6f28332c466f 64 // Set the IP
Soohwan Kim 0:6f28332c466f 65 bool WIZnet_Chip::setip()
Soohwan Kim 0:6f28332c466f 66 {
Soohwan Kim 0:6f28332c466f 67 reg_wr<uint32_t>(SIPR, ip);
Soohwan Kim 0:6f28332c466f 68 reg_wr<uint32_t>(GAR, gateway);
Soohwan Kim 0:6f28332c466f 69 reg_wr<uint32_t>(SUBR, netmask);
Soohwan Kim 0:6f28332c466f 70 return true;
Soohwan Kim 0:6f28332c466f 71 }
Soohwan Kim 0:6f28332c466f 72
Soohwan Kim 0:6f28332c466f 73 bool WIZnet_Chip::setProtocol(int socket, Protocol p)
Soohwan Kim 0:6f28332c466f 74 {
Soohwan Kim 0:6f28332c466f 75 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 76 return false;
Soohwan Kim 0:6f28332c466f 77 }
Soohwan Kim 0:6f28332c466f 78 sreg<uint8_t>(socket, Sn_MR, p);
Soohwan Kim 0:6f28332c466f 79 return true;
Soohwan Kim 0:6f28332c466f 80 }
Soohwan Kim 0:6f28332c466f 81
Soohwan Kim 0:6f28332c466f 82 bool WIZnet_Chip::connect(int socket, const char * host, int port, int timeout_ms)
Soohwan Kim 0:6f28332c466f 83 {
Soohwan Kim 0:6f28332c466f 84 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 85 return false;
Soohwan Kim 0:6f28332c466f 86 }
Soohwan Kim 0:6f28332c466f 87 sreg<uint8_t>(socket, Sn_MR, TCP);
Soohwan Kim 0:6f28332c466f 88 scmd(socket, OPEN);
Soohwan Kim 0:6f28332c466f 89 sreg_ip(socket, Sn_DIPR, host);
Soohwan Kim 0:6f28332c466f 90 sreg<uint16_t>(socket, Sn_DPORT, port);
Soohwan Kim 0:6f28332c466f 91 sreg<uint16_t>(socket, Sn_PORT, new_port());
Soohwan Kim 0:6f28332c466f 92 scmd(socket, CONNECT);
Soohwan Kim 0:6f28332c466f 93 Timer t;
Soohwan Kim 0:6f28332c466f 94 t.reset();
Soohwan Kim 0:6f28332c466f 95 t.start();
Soohwan Kim 0:6f28332c466f 96 while(!is_connected(socket)) {
Soohwan Kim 0:6f28332c466f 97 if (t.read_ms() > timeout_ms) {
Soohwan Kim 0:6f28332c466f 98 return false;
Soohwan Kim 0:6f28332c466f 99 }
Soohwan Kim 0:6f28332c466f 100 }
Soohwan Kim 0:6f28332c466f 101 return true;
Soohwan Kim 0:6f28332c466f 102 }
Soohwan Kim 0:6f28332c466f 103
Soohwan Kim 0:6f28332c466f 104 bool WIZnet_Chip::gethostbyname(const char* host, uint32_t* ip)
Soohwan Kim 0:6f28332c466f 105 {
Soohwan Kim 0:6f28332c466f 106 uint32_t addr = str_to_ip(host);
Soohwan Kim 0:6f28332c466f 107 char buf[17];
Soohwan Kim 0:6f28332c466f 108 snprintf(buf, sizeof(buf), "%d.%d.%d.%d",
Soohwan Kim 0:6f28332c466f 109 (uint8_t)((addr>>24)&0xff),
Soohwan Kim 0:6f28332c466f 110 (uint8_t)((addr>>16)&0xff),
Soohwan Kim 0:6f28332c466f 111 (uint8_t)((addr>>8)&0xff),
Soohwan Kim 0:6f28332c466f 112 (uint8_t)(addr&0xff));
Soohwan Kim 0:6f28332c466f 113 if (strcmp(buf, host) == 0) {
Soohwan Kim 0:6f28332c466f 114 *ip = addr;
Soohwan Kim 0:6f28332c466f 115 return true;
Soohwan Kim 0:6f28332c466f 116 }
Soohwan Kim 0:6f28332c466f 117 DNSClient client;
Soohwan Kim 0:6f28332c466f 118 if(client.lookup(host)) {
Soohwan Kim 0:6f28332c466f 119 *ip = client.ip;
Soohwan Kim 0:6f28332c466f 120 return true;
Soohwan Kim 0:6f28332c466f 121 }
Soohwan Kim 0:6f28332c466f 122 return false;
Soohwan Kim 0:6f28332c466f 123 }
Soohwan Kim 0:6f28332c466f 124
Soohwan Kim 0:6f28332c466f 125
Soohwan Kim 0:6f28332c466f 126 bool WIZnet_Chip::is_connected(int socket)
Soohwan Kim 0:6f28332c466f 127 {
Soohwan Kim 0:6f28332c466f 128 /*
Soohwan Kim 0:6f28332c466f 129 if (sreg<uint8_t>(socket, Sn_SR) == SOCK_ESTABLISHED) {
Soohwan Kim 0:6f28332c466f 130 return true;
Soohwan Kim 0:6f28332c466f 131 }
Soohwan Kim 0:6f28332c466f 132 */
Soohwan Kim 0:6f28332c466f 133 uint8_t tmpSn_SR;
Soohwan Kim 0:6f28332c466f 134 tmpSn_SR = sreg<uint8_t>(socket, Sn_SR);
Soohwan Kim 0:6f28332c466f 135 // packet sending is possible, when state is SOCK_CLOSE_WAIT.
Soohwan Kim 0:6f28332c466f 136 if ((tmpSn_SR == SOCK_ESTABLISHED) || (tmpSn_SR == SOCK_CLOSE_WAIT)) {
Soohwan Kim 0:6f28332c466f 137 return true;
Soohwan Kim 0:6f28332c466f 138 }
Soohwan Kim 0:6f28332c466f 139 return false;
Soohwan Kim 0:6f28332c466f 140 }
Soohwan Kim 0:6f28332c466f 141 // Reset the chip & set the buffer
Soohwan Kim 0:6f28332c466f 142 void WIZnet_Chip::reset()
Soohwan Kim 0:6f28332c466f 143 {
Soohwan Kim 0:6f28332c466f 144 /* S/W Reset PHY */
Soohwan Kim 0:6f28332c466f 145 mdio_write(GPIO_MDC, PHYREG_CONTROL, 0x8000);
Soohwan Kim 0:6f28332c466f 146 wait_ms(10);//for S/W reset
Soohwan Kim 0:6f28332c466f 147 wait_ms(10);//for MDC I/F RDY
Soohwan Kim 0:6f28332c466f 148
embeddist 15:24a9f2df2145 149 mdio_init(GPIO_MDC, MDC, MDIO);
embeddist 15:24a9f2df2145 150
Soohwan Kim 0:6f28332c466f 151 /* S/W Reset WZTOE */
Soohwan Kim 0:6f28332c466f 152 reg_wr<uint8_t>(MR, MR_RST);
Soohwan Kim 0:6f28332c466f 153 // set PAD strengh and pull-up for TXD[3:0] and TXE
Soohwan Kim 0:6f28332c466f 154 #ifdef __DEF_USED_IC101AG__ //For using IC+101AG
Soohwan Kim 0:6f28332c466f 155 *(volatile uint32_t *)(0x41003068) = 0x64; //TXD0
Soohwan Kim 0:6f28332c466f 156 *(volatile uint32_t *)(0x4100306C) = 0x64; //TXD1
Soohwan Kim 0:6f28332c466f 157 *(volatile uint32_t *)(0x41003070) = 0x64; //TXD2
Soohwan Kim 0:6f28332c466f 158 *(volatile uint32_t *)(0x41003074) = 0x64; //TXD3
Soohwan Kim 0:6f28332c466f 159 *(volatile uint32_t *)(0x41003050) = 0x64; //TXE
Soohwan Kim 0:6f28332c466f 160 #endif
Soohwan Kim 0:6f28332c466f 161 // set ticker counter
Soohwan Kim 0:6f28332c466f 162 reg_wr<uint32_t>(TIC100US, (SystemCoreClock/10000));
Soohwan Kim 0:6f28332c466f 163 // write MAC address inside the WZTOE MAC address register
Soohwan Kim 0:6f28332c466f 164 reg_wr_mac(SHAR, mac);
Soohwan Kim 0:6f28332c466f 165 /*
Soohwan Kim 0:6f28332c466f 166 * set RX and TX buffer size
Soohwan Kim 0:6f28332c466f 167 * for (int socket = 0; socket < MAX_SOCK_NUM; socket++) {
Soohwan Kim 0:6f28332c466f 168 * sreg<uint8_t>(socket, Sn_RXBUF_SIZE, 2);
Soohwan Kim 0:6f28332c466f 169 * sreg<uint8_t>(socket, Sn_TXBUF_SIZE, 2);
Soohwan Kim 0:6f28332c466f 170 * }
Soohwan Kim 0:6f28332c466f 171 */
Soohwan Kim 0:6f28332c466f 172 }
Soohwan Kim 0:6f28332c466f 173
Soohwan Kim 0:6f28332c466f 174
Soohwan Kim 0:6f28332c466f 175 bool WIZnet_Chip::close(int socket)
Soohwan Kim 0:6f28332c466f 176 {
Soohwan Kim 0:6f28332c466f 177 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 178 return false;
Soohwan Kim 0:6f28332c466f 179 }
Soohwan Kim 0:6f28332c466f 180 // if SOCK_CLOSED, return
Soohwan Kim 0:6f28332c466f 181 if (sreg<uint8_t>(socket, Sn_SR) == SOCK_CLOSED) {
Soohwan Kim 0:6f28332c466f 182 return true;
Soohwan Kim 0:6f28332c466f 183 }
Soohwan Kim 0:6f28332c466f 184 // if SOCK_ESTABLISHED, send FIN-Packet to peer
Soohwan Kim 0:6f28332c466f 185 if (sreg<uint8_t>(socket, Sn_MR) == TCP) {
Soohwan Kim 0:6f28332c466f 186 scmd(socket, DISCON);
Soohwan Kim 0:6f28332c466f 187 }
Soohwan Kim 0:6f28332c466f 188 // close socket
Soohwan Kim 0:6f28332c466f 189 scmd(socket, CLOSE);
Soohwan Kim 0:6f28332c466f 190 // clear Socket Interrupt Register
Soohwan Kim 0:6f28332c466f 191 sreg<uint8_t>(socket, Sn_ICR, 0xff);
Soohwan Kim 0:6f28332c466f 192 return true;
Soohwan Kim 0:6f28332c466f 193 }
Soohwan Kim 0:6f28332c466f 194
Soohwan Kim 0:6f28332c466f 195 int WIZnet_Chip::wait_readable(int socket, int wait_time_ms, int req_size)
Soohwan Kim 0:6f28332c466f 196 {
Soohwan Kim 0:6f28332c466f 197 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 198 return -1;
Soohwan Kim 0:6f28332c466f 199 }
Soohwan Kim 0:6f28332c466f 200 Timer t;
Soohwan Kim 0:6f28332c466f 201 t.reset();
Soohwan Kim 0:6f28332c466f 202 t.start();
Soohwan Kim 0:6f28332c466f 203 while(1) {
Soohwan Kim 0:6f28332c466f 204 int size = sreg<uint16_t>(socket, Sn_RX_RSR);
Soohwan Kim 0:6f28332c466f 205 if (size > req_size) {
Soohwan Kim 0:6f28332c466f 206 return size;
Soohwan Kim 0:6f28332c466f 207 }
Soohwan Kim 0:6f28332c466f 208 if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {
Soohwan Kim 0:6f28332c466f 209 break;
Soohwan Kim 0:6f28332c466f 210 }
Soohwan Kim 0:6f28332c466f 211 }
Soohwan Kim 0:6f28332c466f 212 return -1;
Soohwan Kim 0:6f28332c466f 213 }
Soohwan Kim 0:6f28332c466f 214
Soohwan Kim 0:6f28332c466f 215 int WIZnet_Chip::wait_writeable(int socket, int wait_time_ms, int req_size)
Soohwan Kim 0:6f28332c466f 216 {
Soohwan Kim 0:6f28332c466f 217 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 218 return -1;
Soohwan Kim 0:6f28332c466f 219 }
Soohwan Kim 0:6f28332c466f 220 Timer t;
Soohwan Kim 0:6f28332c466f 221 t.reset();
Soohwan Kim 0:6f28332c466f 222 t.start();
Soohwan Kim 0:6f28332c466f 223 while(1) {
Soohwan Kim 0:6f28332c466f 224 int size = sreg<uint16_t>(socket, Sn_TX_FSR);
Soohwan Kim 0:6f28332c466f 225 if (size > req_size) {
Soohwan Kim 0:6f28332c466f 226 return size;
Soohwan Kim 0:6f28332c466f 227 }
Soohwan Kim 0:6f28332c466f 228 if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {
Soohwan Kim 0:6f28332c466f 229 break;
Soohwan Kim 0:6f28332c466f 230 }
Soohwan Kim 0:6f28332c466f 231 }
Soohwan Kim 0:6f28332c466f 232 return -1;
Soohwan Kim 0:6f28332c466f 233 }
Soohwan Kim 0:6f28332c466f 234
Soohwan Kim 0:6f28332c466f 235 int WIZnet_Chip::send(int socket, const char * str, int len)
Soohwan Kim 0:6f28332c466f 236 {
Soohwan Kim 0:6f28332c466f 237 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 238 return -1;
Soohwan Kim 0:6f28332c466f 239 }
Soohwan Kim 0:6f28332c466f 240
Soohwan Kim 0:6f28332c466f 241 uint16_t ptr = sreg<uint16_t>(socket, Sn_TX_WR);
Soohwan Kim 0:6f28332c466f 242 uint32_t sn_tx_base = W7500x_TXMEM_BASE + (uint32_t)(socket<<18);
Soohwan Kim 0:6f28332c466f 243
Soohwan Kim 0:6f28332c466f 244 for(int i=0; i<len; i++)
Soohwan Kim 0:6f28332c466f 245 *(volatile uint8_t *)(sn_tx_base + ((ptr+i)&0xFFFF)) = str[i];
Soohwan Kim 0:6f28332c466f 246
Soohwan Kim 0:6f28332c466f 247 sreg<uint16_t>(socket, Sn_TX_WR, ptr + len);
Soohwan Kim 0:6f28332c466f 248 scmd(socket, SEND);
Soohwan Kim 0:6f28332c466f 249
Soohwan Kim 0:6f28332c466f 250 uint8_t tmp_Sn_IR;
Soohwan Kim 0:6f28332c466f 251 while (( (tmp_Sn_IR = sreg<uint8_t>(socket, Sn_IR)) & INT_SEND_OK) != INT_SEND_OK) {
Soohwan Kim 0:6f28332c466f 252 // @Jul.10, 2014 fix contant name, and udp sendto function.
Soohwan Kim 0:6f28332c466f 253 switch (sreg<uint8_t>(socket, Sn_SR)) {
Soohwan Kim 0:6f28332c466f 254 case SOCK_CLOSED :
Soohwan Kim 0:6f28332c466f 255 close(socket);
Soohwan Kim 0:6f28332c466f 256 return 0;
Soohwan Kim 0:6f28332c466f 257 //break;
Soohwan Kim 0:6f28332c466f 258 case SOCK_UDP :
Soohwan Kim 0:6f28332c466f 259 // ARP timeout is possible.
Soohwan Kim 0:6f28332c466f 260 if ((tmp_Sn_IR & INT_TIMEOUT) == INT_TIMEOUT) {
Soohwan Kim 0:6f28332c466f 261 sreg<uint8_t>(socket, Sn_ICR, INT_TIMEOUT);
Soohwan Kim 0:6f28332c466f 262 return 0;
Soohwan Kim 0:6f28332c466f 263 }
Soohwan Kim 0:6f28332c466f 264 break;
Soohwan Kim 0:6f28332c466f 265 default :
Soohwan Kim 0:6f28332c466f 266 break;
Soohwan Kim 0:6f28332c466f 267 }
Soohwan Kim 0:6f28332c466f 268 }
Soohwan Kim 0:6f28332c466f 269
Soohwan Kim 0:6f28332c466f 270 sreg<uint8_t>(socket, Sn_ICR, INT_SEND_OK);
Soohwan Kim 0:6f28332c466f 271
Soohwan Kim 0:6f28332c466f 272 return len;
Soohwan Kim 0:6f28332c466f 273 }
Soohwan Kim 0:6f28332c466f 274
Soohwan Kim 0:6f28332c466f 275 int WIZnet_Chip::recv(int socket, char* buf, int len)
Soohwan Kim 0:6f28332c466f 276 {
Soohwan Kim 0:6f28332c466f 277 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 278 return -1;
Soohwan Kim 0:6f28332c466f 279 }
Soohwan Kim 0:6f28332c466f 280 uint16_t ptr = sreg<uint16_t>(socket, Sn_RX_RD);
Soohwan Kim 0:6f28332c466f 281 uint32_t sn_rx_base = W7500x_RXMEM_BASE + (uint32_t)(socket<<18);
Soohwan Kim 0:6f28332c466f 282
Soohwan Kim 0:6f28332c466f 283 for(int i=0; i<len; i++)
Soohwan Kim 0:6f28332c466f 284 buf[i] = *(volatile uint8_t *)(sn_rx_base + ((ptr+i)&0xFFFF));
Soohwan Kim 0:6f28332c466f 285
Soohwan Kim 0:6f28332c466f 286 sreg<uint16_t>(socket, Sn_RX_RD, ptr + len);
Soohwan Kim 0:6f28332c466f 287 scmd(socket, RECV);
Soohwan Kim 0:6f28332c466f 288
Soohwan Kim 0:6f28332c466f 289 return len;
Soohwan Kim 0:6f28332c466f 290 }
Soohwan Kim 0:6f28332c466f 291
Soohwan Kim 0:6f28332c466f 292 int WIZnet_Chip::new_socket()
Soohwan Kim 0:6f28332c466f 293 {
Soohwan Kim 0:6f28332c466f 294 for(int s = 0; s < MAX_SOCK_NUM; s++) {
Soohwan Kim 0:6f28332c466f 295 if (sreg<uint8_t>(s, Sn_SR) == SOCK_CLOSED) {
Soohwan Kim 0:6f28332c466f 296 return s;
Soohwan Kim 0:6f28332c466f 297 }
Soohwan Kim 0:6f28332c466f 298 }
Soohwan Kim 0:6f28332c466f 299 return -1;
Soohwan Kim 0:6f28332c466f 300 }
Soohwan Kim 0:6f28332c466f 301
Soohwan Kim 0:6f28332c466f 302 uint16_t WIZnet_Chip::new_port()
Soohwan Kim 0:6f28332c466f 303 {
Soohwan Kim 0:6f28332c466f 304 uint16_t port = rand();
Soohwan Kim 0:6f28332c466f 305 port |= 49152;
Soohwan Kim 0:6f28332c466f 306 return port;
Soohwan Kim 0:6f28332c466f 307 }
Soohwan Kim 0:6f28332c466f 308
Soohwan Kim 0:6f28332c466f 309 bool WIZnet_Chip::link(int wait_time_ms)
Soohwan Kim 0:6f28332c466f 310 {
Soohwan Kim 0:6f28332c466f 311 Timer t;
Soohwan Kim 0:6f28332c466f 312 t.reset();
Soohwan Kim 0:6f28332c466f 313 t.start();
Soohwan Kim 0:6f28332c466f 314 while(1) {
Soohwan Kim 0:6f28332c466f 315 int is_link = ethernet_link();
hjjeon 19:d8773cd4edc5 316
Soohwan Kim 0:6f28332c466f 317 if (is_link) {
Soohwan Kim 0:6f28332c466f 318 return true;
Soohwan Kim 0:6f28332c466f 319 }
Soohwan Kim 0:6f28332c466f 320 if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {
Soohwan Kim 0:6f28332c466f 321 break;
Soohwan Kim 0:6f28332c466f 322 }
Soohwan Kim 0:6f28332c466f 323 }
Soohwan Kim 0:6f28332c466f 324 return 0;
Soohwan Kim 0:6f28332c466f 325 }
Soohwan Kim 0:6f28332c466f 326
Soohwan Kim 0:6f28332c466f 327 void WIZnet_Chip::set_link(PHYMode phymode)
Soohwan Kim 0:6f28332c466f 328 {
Soohwan Kim 0:6f28332c466f 329 int speed = -1;
Soohwan Kim 0:6f28332c466f 330 int duplex = 0;
Soohwan Kim 0:6f28332c466f 331
Soohwan Kim 0:6f28332c466f 332 switch(phymode) {
Soohwan Kim 0:6f28332c466f 333 case AutoNegotiate : speed = -1; duplex = 0; break;
Soohwan Kim 0:6f28332c466f 334 case HalfDuplex10 : speed = 0; duplex = 0; break;
Soohwan Kim 0:6f28332c466f 335 case FullDuplex10 : speed = 0; duplex = 1; break;
Soohwan Kim 0:6f28332c466f 336 case HalfDuplex100 : speed = 1; duplex = 0; break;
Soohwan Kim 0:6f28332c466f 337 case FullDuplex100 : speed = 1; duplex = 1; break;
Soohwan Kim 0:6f28332c466f 338 }
Soohwan Kim 0:6f28332c466f 339
Soohwan Kim 0:6f28332c466f 340 ethernet_set_link(speed, duplex);
Soohwan Kim 0:6f28332c466f 341 }
Soohwan Kim 0:6f28332c466f 342
Soohwan Kim 0:6f28332c466f 343 uint32_t str_to_ip(const char* str)
Soohwan Kim 0:6f28332c466f 344 {
Soohwan Kim 0:6f28332c466f 345 uint32_t ip = 0;
Soohwan Kim 0:6f28332c466f 346 char* p = (char*)str;
Soohwan Kim 0:6f28332c466f 347 for(int i = 0; i < 4; i++) {
Soohwan Kim 0:6f28332c466f 348 ip |= atoi(p);
Soohwan Kim 0:6f28332c466f 349 p = strchr(p, '.');
Soohwan Kim 0:6f28332c466f 350 if (p == NULL) {
Soohwan Kim 0:6f28332c466f 351 break;
Soohwan Kim 0:6f28332c466f 352 }
Soohwan Kim 0:6f28332c466f 353 ip <<= 8;
Soohwan Kim 0:6f28332c466f 354 p++;
Soohwan Kim 0:6f28332c466f 355 }
Soohwan Kim 0:6f28332c466f 356 return ip;
Soohwan Kim 0:6f28332c466f 357 }
Soohwan Kim 0:6f28332c466f 358
Soohwan Kim 0:6f28332c466f 359 void printfBytes(char* str, uint8_t* buf, int len)
Soohwan Kim 0:6f28332c466f 360 {
Soohwan Kim 0:6f28332c466f 361 printf("%s %d:", str, len);
Soohwan Kim 0:6f28332c466f 362 for(int i = 0; i < len; i++) {
Soohwan Kim 0:6f28332c466f 363 printf(" %02x", buf[i]);
Soohwan Kim 0:6f28332c466f 364 }
Soohwan Kim 0:6f28332c466f 365 printf("\n");
Soohwan Kim 0:6f28332c466f 366 }
Soohwan Kim 0:6f28332c466f 367
Soohwan Kim 0:6f28332c466f 368 void printHex(uint8_t* buf, int len)
Soohwan Kim 0:6f28332c466f 369 {
Soohwan Kim 0:6f28332c466f 370 for(int i = 0; i < len; i++) {
Soohwan Kim 0:6f28332c466f 371 if ((i%16) == 0) {
Soohwan Kim 0:6f28332c466f 372 printf("%p", buf+i);
Soohwan Kim 0:6f28332c466f 373 }
Soohwan Kim 0:6f28332c466f 374 printf(" %02x", buf[i]);
Soohwan Kim 0:6f28332c466f 375 if ((i%16) == 15) {
Soohwan Kim 0:6f28332c466f 376 printf("\n");
Soohwan Kim 0:6f28332c466f 377 }
Soohwan Kim 0:6f28332c466f 378 }
Soohwan Kim 0:6f28332c466f 379 printf("\n");
Soohwan Kim 0:6f28332c466f 380 }
Soohwan Kim 0:6f28332c466f 381
Soohwan Kim 0:6f28332c466f 382 void debug_hex(uint8_t* buf, int len)
Soohwan Kim 0:6f28332c466f 383 {
Soohwan Kim 0:6f28332c466f 384 for(int i = 0; i < len; i++) {
Soohwan Kim 0:6f28332c466f 385 if ((i%16) == 0) {
Soohwan Kim 0:6f28332c466f 386 debug("%p", buf+i);
Soohwan Kim 0:6f28332c466f 387 }
Soohwan Kim 0:6f28332c466f 388 debug(" %02x", buf[i]);
Soohwan Kim 0:6f28332c466f 389 if ((i%16) == 15) {
Soohwan Kim 0:6f28332c466f 390 debug("\n");
Soohwan Kim 0:6f28332c466f 391 }
Soohwan Kim 0:6f28332c466f 392 }
Soohwan Kim 0:6f28332c466f 393 debug("\n");
Soohwan Kim 0:6f28332c466f 394 }
Soohwan Kim 0:6f28332c466f 395
Soohwan Kim 0:6f28332c466f 396 void WIZnet_Chip::scmd(int socket, Command cmd)
Soohwan Kim 0:6f28332c466f 397 {
Soohwan Kim 0:6f28332c466f 398 sreg<uint8_t>(socket, Sn_CR, cmd);
Soohwan Kim 0:6f28332c466f 399 while(sreg<uint8_t>(socket, Sn_CR));
Soohwan Kim 0:6f28332c466f 400 }
Soohwan Kim 0:6f28332c466f 401
Soohwan Kim 0:6f28332c466f 402
Soohwan Kim 0:6f28332c466f 403 void mdio_init(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin_MDC, uint16_t GPIO_Pin_MDIO)
Soohwan Kim 0:6f28332c466f 404 {
Soohwan Kim 0:6f28332c466f 405 /* Set GPIOs for MDIO and MDC */
Soohwan Kim 0:6f28332c466f 406 GPIO_InitTypeDef MDIO_InitDef;
Soohwan Kim 0:6f28332c466f 407 HAL_PAD_AFConfig(PAD_PB, GPIO_Pin_MDIO, PAD_AF1);
Soohwan Kim 0:6f28332c466f 408 HAL_PAD_AFConfig(PAD_PB, GPIO_Pin_MDC, PAD_AF1);
Soohwan Kim 0:6f28332c466f 409 MDIO_InitDef.GPIO_Pin = GPIO_Pin_MDC | GPIO_Pin_MDIO;
Soohwan Kim 0:6f28332c466f 410 MDIO_InitDef.GPIO_Mode = GPIO_Mode_OUT;
Soohwan Kim 0:6f28332c466f 411 HAL_GPIO_Init(GPIOx, &MDIO_InitDef);
Soohwan Kim 0:6f28332c466f 412 }
Soohwan Kim 0:6f28332c466f 413
Soohwan Kim 0:6f28332c466f 414 void output_MDIO(GPIO_TypeDef* GPIOx, uint32_t val, uint32_t n)
Soohwan Kim 0:6f28332c466f 415 {
Soohwan Kim 0:6f28332c466f 416 for(val <<= (32-n); n; val<<=1, n--)
Soohwan Kim 0:6f28332c466f 417 {
Soohwan Kim 0:6f28332c466f 418 if(val & 0x80000000)
Soohwan Kim 0:6f28332c466f 419 HAL_GPIO_SetBits(GPIOx, MDIO);
Soohwan Kim 0:6f28332c466f 420 else
Soohwan Kim 0:6f28332c466f 421 HAL_GPIO_ResetBits(GPIOx, MDIO);
Soohwan Kim 0:6f28332c466f 422
Soohwan Kim 0:6f28332c466f 423 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 424 HAL_GPIO_SetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 425 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 426 HAL_GPIO_ResetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 427 }
Soohwan Kim 0:6f28332c466f 428 }
Soohwan Kim 0:6f28332c466f 429
Soohwan Kim 0:6f28332c466f 430 uint32_t input_MDIO( GPIO_TypeDef* GPIOx )
Soohwan Kim 0:6f28332c466f 431 {
Soohwan Kim 0:6f28332c466f 432 uint32_t i, val=0;
Soohwan Kim 0:6f28332c466f 433 for(i=0; i<16; i++)
Soohwan Kim 0:6f28332c466f 434 {
Soohwan Kim 0:6f28332c466f 435 val <<=1;
Soohwan Kim 0:6f28332c466f 436 HAL_GPIO_SetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 437 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 438 HAL_GPIO_ResetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 439 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 440 val |= HAL_GPIO_ReadInputDataBit(GPIOx, MDIO);
Soohwan Kim 0:6f28332c466f 441 }
Soohwan Kim 0:6f28332c466f 442 return (val);
Soohwan Kim 0:6f28332c466f 443 }
Soohwan Kim 0:6f28332c466f 444
Soohwan Kim 0:6f28332c466f 445 void turnaround_MDIO( GPIO_TypeDef* GPIOx)
Soohwan Kim 0:6f28332c466f 446 {
Soohwan Kim 0:6f28332c466f 447 GPIOx->OUTENCLR = MDIO ;
Soohwan Kim 0:6f28332c466f 448 HAL_GPIO_SetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 449 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 450 HAL_GPIO_ResetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 451 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 452 }
Soohwan Kim 0:6f28332c466f 453
Soohwan Kim 0:6f28332c466f 454 void idle_MDIO( GPIO_TypeDef* GPIOx )
Soohwan Kim 0:6f28332c466f 455 {
Soohwan Kim 0:6f28332c466f 456 GPIOx->OUTENSET = MDIO ;
Soohwan Kim 0:6f28332c466f 457 HAL_GPIO_SetBits(GPIOx,MDC);
Soohwan Kim 0:6f28332c466f 458 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 459 HAL_GPIO_ResetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 460 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 461 }
Soohwan Kim 0:6f28332c466f 462
Soohwan Kim 0:6f28332c466f 463 uint32_t mdio_read(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr)
Soohwan Kim 0:6f28332c466f 464 {
Soohwan Kim 0:6f28332c466f 465 output_MDIO(GPIOx, 0xFFFFFFFF, 32);
Soohwan Kim 0:6f28332c466f 466 output_MDIO(GPIOx, 0x06, 4);
Soohwan Kim 0:6f28332c466f 467 output_MDIO(GPIOx, PHY_ADDR, 5);
Soohwan Kim 0:6f28332c466f 468 output_MDIO(GPIOx, PhyRegAddr, 5);
Soohwan Kim 0:6f28332c466f 469 turnaround_MDIO(GPIOx);
Soohwan Kim 0:6f28332c466f 470 uint32_t val = input_MDIO(GPIOx );
Soohwan Kim 0:6f28332c466f 471 idle_MDIO(GPIOx);
Soohwan Kim 0:6f28332c466f 472 return val;
Soohwan Kim 0:6f28332c466f 473 }
Soohwan Kim 0:6f28332c466f 474
Soohwan Kim 0:6f28332c466f 475 void mdio_write(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr, uint32_t val)
Soohwan Kim 0:6f28332c466f 476 {
Soohwan Kim 0:6f28332c466f 477 output_MDIO(GPIOx, 0xFFFFFFFF, 32);
Soohwan Kim 0:6f28332c466f 478 output_MDIO(GPIOx, 0x05, 4);
Soohwan Kim 0:6f28332c466f 479 output_MDIO(GPIOx, PHY_ADDR, 5);
Soohwan Kim 0:6f28332c466f 480 output_MDIO(GPIOx, PhyRegAddr, 5);
Soohwan Kim 0:6f28332c466f 481 output_MDIO(GPIOx, 0x02, 2);
Soohwan Kim 0:6f28332c466f 482 output_MDIO(GPIOx, val, 16);
Soohwan Kim 0:6f28332c466f 483 idle_MDIO(GPIOx);
Soohwan Kim 0:6f28332c466f 484 }
Soohwan Kim 0:6f28332c466f 485
embeddist 14:2101ab5ee40f 486 int WIZnet_Chip::ethernet_link(void) {
Soohwan Kim 0:6f28332c466f 487 return ((mdio_read(GPIO_MDC, PHYREG_STATUS)>>SVAL)&0x01);
Soohwan Kim 0:6f28332c466f 488 }
Soohwan Kim 0:6f28332c466f 489
embeddist 14:2101ab5ee40f 490 void WIZnet_Chip::ethernet_set_link(int speed, int duplex) {
Soohwan Kim 0:6f28332c466f 491 uint32_t val=0;
Soohwan Kim 0:6f28332c466f 492 if((speed < 0) || (speed > 1)) {
Soohwan Kim 0:6f28332c466f 493 val = CNTL_AUTONEGO;
Soohwan Kim 0:6f28332c466f 494 } else {
Soohwan Kim 0:6f28332c466f 495 val = ((CNTL_SPEED&(speed<<11))|(CNTL_DUPLEX&(duplex<<7)));
Soohwan Kim 0:6f28332c466f 496 }
Soohwan Kim 0:6f28332c466f 497 mdio_write(GPIO_MDC, PHYREG_CONTROL, val);
Soohwan Kim 0:6f28332c466f 498 }
embeddist 14:2101ab5ee40f 499
embeddist 14:2101ab5ee40f 500 void WIZnet_Chip::reg_rd_mac(uint16_t addr, uint8_t* data)
embeddist 14:2101ab5ee40f 501 {
embeddist 14:2101ab5ee40f 502 data[0] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+3));
embeddist 14:2101ab5ee40f 503 data[1] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+2));
embeddist 14:2101ab5ee40f 504 data[2] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+1));
embeddist 14:2101ab5ee40f 505 data[3] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+0));
embeddist 14:2101ab5ee40f 506 data[4] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+7));
embeddist 14:2101ab5ee40f 507 data[5] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+6));
embeddist 14:2101ab5ee40f 508 }
embeddist 14:2101ab5ee40f 509
embeddist 14:2101ab5ee40f 510 void WIZnet_Chip::reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip)
embeddist 14:2101ab5ee40f 511 {
embeddist 14:2101ab5ee40f 512 uint8_t buf[4]={0,};
embeddist 14:2101ab5ee40f 513 uint32_t wr_ip = 0;
embeddist 14:2101ab5ee40f 514 char* p = (char*)ip;
embeddist 14:2101ab5ee40f 515
embeddist 14:2101ab5ee40f 516 for(int i = 0; i < 4; i++) {
embeddist 14:2101ab5ee40f 517 wr_ip = (wr_ip<<8);
embeddist 14:2101ab5ee40f 518 buf[i] = atoi(p);
embeddist 14:2101ab5ee40f 519 wr_ip |= buf[i];
embeddist 14:2101ab5ee40f 520 p = strchr(p, '.');
embeddist 14:2101ab5ee40f 521 if (p == NULL) break;
embeddist 14:2101ab5ee40f 522 p++;
embeddist 14:2101ab5ee40f 523 }
embeddist 14:2101ab5ee40f 524 *(volatile uint32_t *)(W7500x_WZTOE_BASE + (uint32_t)((cb<<16)+addr)) = wr_ip;
embeddist 14:2101ab5ee40f 525 }
embeddist 14:2101ab5ee40f 526
embeddist 14:2101ab5ee40f 527 void WIZnet_Chip::sreg_ip(int socket, uint16_t addr, const char* ip) {
embeddist 14:2101ab5ee40f 528 reg_wr_ip(addr, (uint8_t)(0x01+(socket<<2)), ip);
embeddist 14:2101ab5ee40f 529 }
embeddist 14:2101ab5ee40f 530
Soohwan Kim 0:6f28332c466f 531 #endif
Soohwan Kim 0:6f28332c466f 532