r_ospl_memory.c

00001 /*******************************************************************************
00002 * DISCLAIMER
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00005 * software is owned by Renesas Electronics Corporation and is protected under
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00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
00016 * Renesas reserves the right, without notice, to make changes to this software
00017 * and to discontinue the availability of this software. By using this software,
00018 * you agree to the additional terms and conditions found by accessing the
00019 * following link:
00020 * http://www.renesas.com/disclaimer
00021 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
00022 *******************************************************************************/
00023 /**
00024 * @file  r_ospl_memory.c
00025 * @brief   Memory map
00026 *
00027 * $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
00028 * $Rev: $
00029 * $Date::                           $
00030 */
00031 
00032 
00033 /******************************************************************************
00034 Includes   <System Includes> , "Project Includes"
00035 ******************************************************************************/
00036 #include  "r_ospl.h"
00037 #ifdef R_OSPL_TEST_CODE
00038 #include  "r_ospl_test.h"
00039 #endif
00040 #include  "r_ospl_private.h"
00041 
00042 /******************************************************************************
00043 Typedef definitions
00044 ******************************************************************************/
00045 
00046 /**
00047 * @struct  gs_address_table_line_t
00048 * @brief  gs_address_table_line_t
00049 */
00050 typedef struct st_gs_address_table_line_t  gs_address_table_line_t;
00051 struct st_gs_address_table_line_t {
00052 
00053     /** Address */
00054     uintptr_t  Address;
00055 
00056     /** Value */
00057     int_fast32_t  Value;
00058 };
00059 
00060 
00061 /**
00062 * @struct  gs_address_table_line_c_t
00063 * @brief  gs_address_table_line_c_t
00064 */
00065 typedef struct st_gs_address_table_line_c_t  gs_address_table_line_c_t;
00066 struct st_gs_address_table_line_c_t {
00067 
00068     /** Address */
00069     uintptr_t  Address;
00070 
00071     /** Value */
00072     r_ospl_axi_cache_attribute_t  Value;
00073 };
00074 
00075 
00076 /******************************************************************************
00077 Macro definitions
00078 ******************************************************************************/
00079 
00080 /* ->MISRA 17.4 : These are addresses */
00081 
00082 #define GS_MIRROR_SIZE    0x40000000u
00083 #define GS_CACHED_START   0x00000000u
00084 #define GS_CACHED_END     ( GS_CACHED_START + GS_MIRROR_SIZE )
00085 #define GS_UNCACHED_START 0x40000000u
00086 #define GS_UNCACHED_END   ( GS_UNCACHED_START + GS_MIRROR_SIZE )
00087 
00088 #define GS_IO_START       0x60A00000u
00089 
00090 /* From "scatter.scat" file */
00091 #if defined( RZ_A1L )
00092 #define LRAM_SIZE                   0x00300000u
00093 #else  /* RZ/A1H */
00094 #define LRAM_SIZE                   0x00A00000u
00095 #endif
00096 #define LRAM_START                  0x20000000u
00097 #define LRAM_END                    ( LRAM_START + LRAM_SIZE )
00098 #define UNUSED_UNCACHED_LRAM_START  0x60000000u
00099 #define UNCACHED_LRAM_END           ( UNUSED_UNCACHED_LRAM_START + LRAM_SIZE )
00100 
00101 /* <-MISRA 17.4 */
00102 
00103 #define  GS_EXTERNAL_START_0x00000000               0x00000000u
00104 #define  GS_EXTERNAL_SDRAM_START_0x08000000         0x08000000u
00105 #define  GS_INTERNAL_RAM_START_0x20000000           0x20000000u
00106 #define  GS_INTERNAL_REGISTERS_START_0x80000000     0x80000000u
00107 
00108 #if defined( RZ_A1L_EV_BOARD )
00109 #define  GS_SDRAM_SIZE  0x04000000u
00110 #else
00111 #define  GS_SDRAM_SIZE  0x02000000u
00112 #endif
00113 
00114 
00115 /******************************************************************************
00116 Imported global variables and functions (from other files)
00117 ******************************************************************************/
00118 
00119 /******************************************************************************
00120 Exported global variables and functions (to be accessed by other files)
00121 ******************************************************************************/
00122 
00123 /******************************************************************************
00124 Private global variables and functions
00125 ******************************************************************************/
00126 #ifdef R_OSPL_TEST_CODE
00127 static  r_ospl_axi_envronment_t  gs_Environment;
00128 #endif
00129 
00130 
00131 /******************************************************************************
00132 * Implement: R_OSPL_ToPhysicalAddress
00133 ******************************************************************************/
00134 errnum_t  R_OSPL_ToPhysicalAddress( const volatile void *in_Address, uintptr_t *out_PhysicalAddress )
00135 {
00136     errnum_t  e;
00137     /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
00138     uintptr_t const  address = (uintptr_t) in_Address;
00139     /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
00140 
00141     IF_DQ( out_PhysicalAddress == NULL ) {
00142         e=E_OTHERS;
00143         goto fin;
00144     }
00145 
00146     *out_PhysicalAddress = address;
00147 
00148     e=0;
00149 fin:
00150     return  e;
00151 }
00152 
00153 
00154 /******************************************************************************
00155 * Implement: R_OSPL_ToCachedAddress
00156 ******************************************************************************/
00157 errnum_t  R_OSPL_ToCachedAddress( const volatile void *in_Address, void *out_CachedAddress )
00158 {
00159     /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
00160     /* ->QAC 0289 */ /* ->QAC 1002 : Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base */
00161     errnum_t  e;
00162 #if  IS_MBED_USED
00163     uintptr_t  address = (uintptr_t) in_Address;
00164     const uintptr_t  uncached_from_cached = UNUSED_UNCACHED_LRAM_START - LRAM_START;
00165 #else
00166     uintptr_t const  address = (uintptr_t) in_Address;
00167 #endif
00168 
00169     IF_DQ( out_CachedAddress == NULL ) {
00170         e=E_OTHERS;
00171         goto fin;
00172     }
00173 
00174 #if  IS_MBED_USED
00175     IF ( address < LRAM_START ) {
00176         e = E_ACCESS_DENIED;
00177     }
00178     else if ( address < LRAM_END ) {
00179         e = 0;
00180     } else IF ( address < UNUSED_UNCACHED_LRAM_START ) {
00181         e = E_ACCESS_DENIED;
00182     }
00183     else if ( address < UNCACHED_LRAM_END ) {
00184         address -= uncached_from_cached;
00185         e = 0;
00186     } else {
00187         e = E_ACCESS_DENIED;
00188     }
00189 #else
00190     IF ( (address >= (uintptr_t)&Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base)  &&
00191          (address < (uintptr_t)&Image$$END_OF_INTERNAL_RAM_BARRIER$$ZI$$Limit) ) {
00192         /* "BEGIN_OF_NOCACHE_RAM_BARRIER" is defined in "scatter.sct" file. */
00193         /* Image$$ execution region symbols */
00194         /* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0377d/CHDFHJDJ.html */
00195 
00196         e = E_ACCESS_DENIED;
00197     }
00198     else IF ( address >= UNUSED_UNCACHED_LRAM_START ) {
00199         e = E_ACCESS_DENIED;
00200     }
00201     else {
00202         e = 0;
00203     }
00204 #endif
00205 
00206     *(void **) out_CachedAddress = (void *) address;
00207 
00208 fin:
00209     return  e;
00210     /* <-QAC 0289 *//* <-QAC 1002 */
00211     /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
00212 }
00213 
00214 
00215 /******************************************************************************
00216 * Implement: R_OSPL_ToUncachedAddress
00217 ******************************************************************************/
00218 errnum_t  R_OSPL_ToUncachedAddress( const volatile void *in_Address, void *out_UncachedAddress )
00219 {
00220     /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
00221     /* ->QAC 0289 */ /* ->QAC 1002 : Image$$BEGIN_OF_CACHED_RAM_BARRIER$$Base */
00222     errnum_t  e;
00223 #if  IS_MBED_USED
00224     uintptr_t  address = (uintptr_t) in_Address;
00225     uintptr_t  nc_base = UNUSED_UNCACHED_LRAM_START;
00226     const uintptr_t  uncached_from_cached = UNUSED_UNCACHED_LRAM_START - LRAM_START;
00227 #else
00228     uintptr_t const  address = (uintptr_t) in_Address;
00229 #endif
00230 
00231     IF_DQ( out_UncachedAddress == NULL ) {
00232         e=E_OTHERS;
00233         goto fin;
00234     }
00235 
00236 #if  IS_MBED_USED
00237     IF ( address < nc_base - uncached_from_cached ) {
00238         e = E_ACCESS_DENIED;
00239     }
00240     else if ( address < LRAM_END ) {
00241         address += uncached_from_cached;
00242         e = 0;
00243     } else IF ( address < nc_base ) {
00244         e = E_ACCESS_DENIED;
00245     }
00246     else if ( address < UNCACHED_LRAM_END ) {
00247         e = 0;
00248     } else {
00249         e = E_ACCESS_DENIED;
00250     }
00251 #else
00252     IF ( (address >= (uintptr_t)&Image$$BEGIN_OF_CACHED_RAM_BARRIER$$Base)  &&
00253          (address < (uintptr_t)&Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$ZI$$Limit) ) {
00254         e = E_ACCESS_DENIED;
00255     }
00256     else if ( (address >= (uintptr_t)&Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base)  &&
00257               (address < (uintptr_t)&Image$$END_OF_INTERNAL_RAM_BARRIER$$ZI$$Limit) ) {
00258         e = 0;
00259     } else IF ( R_CUT_IF_ALWAYS_TRUE( (address >= GS_CACHED_START)  &&)  (address < GS_CACHED_END) ) {
00260         e = E_ACCESS_DENIED;
00261     }
00262     else IF ( (address >= UNUSED_UNCACHED_LRAM_START) && (address < GS_IO_START) ) {
00263         e = E_ACCESS_DENIED;
00264     }
00265     else {
00266         e = 0;
00267     }
00268 #endif
00269 
00270     *(void **) out_UncachedAddress = (void *) address;
00271 
00272 fin:
00273     return  e;
00274     /* <-QAC 0289 *//* <-QAC 1002 */
00275     /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
00276 }
00277 
00278 
00279 /******************************************************************************
00280 * Implement: R_OSPL_MEMORY_GetLevelOfFlush
00281 ******************************************************************************/
00282 errnum_t  R_OSPL_MEMORY_GetLevelOfFlush( const void *in_Address, int_fast32_t *out_Level )
00283 {
00284     uintptr_t  address = (uintptr_t) in_Address;
00285 
00286 #ifdef R_OSPL_TEST_CODE
00287     if ( gs_Environment == R_OSPL_AXI_L2CACHED ) {
00288 #endif
00289         static const gs_address_table_line_t  table[] = {
00290             /* .Address                                       .Value */
00291             { GS_EXTERNAL_START_0x00000000,                        0 },
00292             { GS_EXTERNAL_SDRAM_START_0x08000000,                  1 },
00293             { GS_EXTERNAL_SDRAM_START_0x08000000 + GS_SDRAM_SIZE,  0 },
00294             { GS_INTERNAL_RAM_START_0x20000000,                    1 },
00295             { GS_INTERNAL_RAM_START_0x20000000 + LRAM_SIZE,        0 }
00296         };
00297 
00298 
00299         if ( address < table[1].Address ) {
00300             *out_Level = table[0].Value;
00301         } else if ( address < table[2].Address ) {
00302             *out_Level = table[1].Value;
00303         } else if ( address < table[3].Address ) {
00304             *out_Level = table[2].Value;
00305         } else if ( address < table[4].Address ) {
00306             *out_Level = table[3].Value;
00307         } else {
00308             *out_Level = table[4].Value;
00309         }
00310         R_STATIC_ASSERT( R_COUNT_OF( table ) == 5, "" );
00311 
00312 #ifdef R_OSPL_TEST_CODE
00313     } else {
00314         static const gs_address_table_line_t  table[] = {
00315             /* .Address                                       .Value */
00316             { GS_EXTERNAL_START_0x00000000,                        0 },
00317             { GS_EXTERNAL_SDRAM_START_0x08000000,                  2 },
00318             { GS_EXTERNAL_SDRAM_START_0x08000000 + GS_SDRAM_SIZE,  0 },
00319             { GS_INTERNAL_RAM_START_0x20000000,                    1 },
00320             { GS_INTERNAL_RAM_START_0x20000000 + LRAM_SIZE,        0 },
00321             /* { GS_EXTERNAL_SDRAM_MIRROR_START_0x48000000,                 2 }, */
00322             /* { GS_EXTERNAL_SDRAM_MIRROR_START_0x48000000 + GS_SDRAM_SIZE, 0 }, */
00323             /* { GS_INTERNAL_RAM_MIRROR_START_0x60000000,                   0 }, */
00324             /* { GS_INTERNAL_RAM_MIRROR_START_0x60000000 + LRAM_SIZE,       0 } */
00325         };
00326 
00327 
00328         ASSERT_R( gs_Environment == R_OSPL_AXI_L2STRONGLY, R_NOOP() );
00329 
00330         if ( address < table[1].Address ) {
00331             *out_Level = table[0].Value;
00332         } else if ( address < table[2].Address ) {
00333             *out_Level = table[1].Value;
00334         } else if ( address < table[3].Address ) {
00335             *out_Level = table[2].Value;
00336         } else if ( address < table[4].Address ) {
00337             *out_Level = table[3].Value;
00338         } else {
00339             *out_Level = table[4].Value;
00340         }
00341         R_STATIC_ASSERT( R_COUNT_OF( table ) == 5, "" );
00342     }
00343 #endif
00344     return  0;
00345 }
00346 
00347 
00348 /******************************************************************************
00349 * Implement: R_OSPL_AXI_Get2ndCacheAttribute
00350 ******************************************************************************/
00351 errnum_t  R_OSPL_AXI_Get2ndCacheAttribute( uintptr_t const  in_PhysicalAddress,
00352         r_ospl_axi_cache_attribute_t *const  out_CacheAttribute )
00353 {
00354     uintptr_t  address = in_PhysicalAddress;
00355 
00356 #ifdef R_OSPL_TEST_CODE
00357     if ( gs_Environment == R_OSPL_AXI_L2CACHED ) {
00358 #endif
00359         static const gs_address_table_line_c_t  table[] = {
00360             /* .Address                                  .Value */
00361             { GS_EXTERNAL_START_0x00000000,               R_OSPL_AXI_WRITE_BACK_W },
00362             /*{ GS_EXTERNAL_SDRAM_START_0x08000000,       R_OSPL_AXI_WRITE_BACK_W },*/
00363             { GS_INTERNAL_RAM_START_0x20000000,           R_OSPL_AXI_CACHE_ZERO },
00364             /*{ GS_INTERNAL_REGISTERS_START_0x80000000,   R_OSPL_AXI_CACHE_ZERO }*/
00365             /* If external I/O existed, "*out_CacheAttribute = R_AXI_DEVICE;" */
00366         };
00367 
00368 
00369         if ( address < table[1].Address ) {
00370             *out_CacheAttribute = table[0].Value;
00371         } else {
00372             *out_CacheAttribute = table[1].Value;
00373         }
00374         R_STATIC_ASSERT( R_COUNT_OF( table ) == 2, "" );
00375 
00376 #ifdef R_OSPL_TEST_CODE
00377     } else {
00378         static const gs_address_table_line_c_t  table[] = {
00379             /* .Address                                  .Value */
00380             { GS_EXTERNAL_START_0x00000000,               R_OSPL_AXI_STRONGLY },
00381             /*{ GS_EXTERNAL_SDRAM_START_0x08000000,       R_OSPL_AXI_STRONGLY },*/
00382             { GS_INTERNAL_RAM_START_0x20000000,           R_OSPL_AXI_CACHE_ZERO },
00383             /*{ GS_EXTERNAL_MIRROR_START_0x40000000,        R_OSPL_AXI_STRONGLY },*/
00384             /*{ GS_EXTERNAL_SDRAM_MIRROR_START_0x48000000,R_OSPL_AXI_STRONGLY },*/
00385             /*{ GS_INTERNAL_RAM_MIRROR_START_0x60000000,    R_OSPL_AXI_CACHE_ZERO },*/
00386             /*{ GS_INTERNAL_REGISTERS_START_0x80000000,   R_OSPL_AXI_CACHE_ZERO }*/
00387             /* If external I/O existed, "*out_CacheAttribute = R_AXI_DEVICE;" */
00388         };
00389 
00390 
00391         ASSERT_R( gs_Environment == R_OSPL_AXI_L2STRONGLY, R_NOOP() );
00392 
00393         if ( address < table[1].Address ) {
00394             *out_CacheAttribute = table[0].Value;
00395         } else {
00396             *out_CacheAttribute = table[1].Value;
00397         }
00398         R_STATIC_ASSERT( R_COUNT_OF( table ) == 2, "" );
00399     }
00400 #endif
00401     return  0;
00402 }
00403 
00404 
00405 /***********************************************************************
00406 * Implement: R_OSPL_AXI_GetProtection
00407 ************************************************************************/
00408 errnum_t  R_OSPL_AXI_GetProtection( uintptr_t const  in_PhysicalAddress,
00409                                     r_ospl_axi_protection_t *const  out_Protection )
00410 {
00411     *out_Protection = R_OSPL_AXI_NON_SECURE;  /* Same as CPU(TTB) NS bit */
00412 
00413     return  0;
00414 }
00415 
00416 
00417 /***********************************************************************
00418 * Implement: R_OSPL_AXI_SetEnvironment
00419 ************************************************************************/
00420 #ifdef R_OSPL_TEST_CODE
00421 errnum_t  R_OSPL_AXI_SetEnvironment( r_ospl_axi_envronment_t in_Environment )
00422 {
00423     gs_Environment = in_Environment;
00424     return  0;
00425 }
00426 #endif
00427 
00428 
00429