lcd_vklcd70rt_ch0.h

00001 /*******************************************************************************
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00021 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
00022 *******************************************************************************/
00023 /**************************************************************************//**
00024 * @file         lcd_vklcd70rt_ch0.h
00025 * @version      1.00
00026 * $Rev: 199 $
00027 * $Date:: 2014-05-23 16:33:52 +0900#$
00028 * @brief        LCD panel for vdc5 channel 0 definition header
00029 ******************************************************************************/
00030 
00031 #ifndef LCD_VKLCD70RT_CH0_H
00032 #define LCD_VKLCD70RT_CH0_H
00033 
00034 #ifndef LCD_PANEL_H
00035 #error  Do not include this file directly!
00036 #else
00037 /******************************************************************************
00038 Includes   <System Includes> , "Project Includes"
00039 ******************************************************************************/
00040 #include    <stdlib.h>
00041 
00042 #include    "r_typedefs.h"
00043 
00044 #include    "r_vdc5.h"
00045 
00046 
00047 /******************************************************************************
00048 Macro definitions
00049 ******************************************************************************/
00050 #define     LCD_CH0_DISP_HS         (160u)                      /* LCD display area size, horizontal start position */
00051 #define     LCD_CH0_DISP_HW         (1024u)                     /* LCD display area size, horizontal width */
00052 #define     LCD_CH0_DISP_VS         (18u)                       /* LCD display area size, vertical start position */
00053 #define     LCD_CH0_DISP_VW         (600u)                      /* LCD display area size, height (vertical width) */
00054 #define     LCD_CH0_SIG_FV          (635u - 1u)                 /* Free-running Vsync period */
00055 #define     LCD_CH0_SIG_FH          (1344u - 1u)                /* Hsync period */
00056 /* Pixel data is latched in the falling edge of pixel clock.
00057    Therefore, pixel data should be output from VDC5 at the rising edge of the clock. */
00058 #define     LCD_CH0_OUT_EDGE        VDC5_EDGE_RISING            /* Output phase control of LCD_DATA[23:0] signal */
00059 #define     LCD_CH0_OUT_FORMAT      VDC5_LCD_OUTFORMAT_RGB888   /* LCD output format select */
00060 
00061 #define     LCD_CH0_PANEL_CLK       VDC5_PANEL_ICKSEL_LVDS_DIV7 /* Panel clock select */
00062 #define     LCD_CH0_PANEL_CLK_DIV   VDC5_PANEL_CLKDIV_1_2       /* Panel clock frequency division ratio */
00063 
00064 #define     LCD_CH0_TCON_HALF       (LCD_CH0_SIG_FH / 2u)       /* TCON reference timing, 1/2fH timing */
00065 #define     LCD_CH0_TCON_OFFSET     (0u)                        /* TCON reference timing, offset Hsync signal timing */
00066 
00067 #define     LCD_CH0_INITIAL_DC      30
00068 
00069 #define     LCD_CH0_EXP_ADDR        0x80
00070 #define     LCD_CH0_CALIB_ADDR      0x90
00071 /******************************************************************************
00072 Typedef definitions
00073 ******************************************************************************/
00074 enum CONTROL_BIT__ {
00075    RGB_DATA = 0,
00076    M666_888,
00077    L_R_SCAN,
00078    U_D_SCAN,
00079    BL_EN   ,
00080    RESET_CTP,
00081 //-----------
00082    MAXBITS
00083 };
00084 
00085 enum CONTROL_REG__ {
00086    PORTMODE = 0,
00087    OUTPUT,
00088    INPUT,
00089    PWM_DC,
00090    PWM_DIV,
00091    PWM_T,
00092 //-----------
00093    MAXREGS
00094 };
00095 
00096 typedef union __IOEXP
00097 {
00098   struct __CONTROL
00099   {
00100     uint8_t portmode;
00101     uint8_t output;
00102     uint8_t input;
00103     uint8_t PWM_dc;
00104     uint8_t PWM_div;
00105     uint8_t PWM_t;
00106   }regs;
00107   
00108   uint8_t reg[sizeof(struct __CONTROL)];
00109 }ioexp_t;
00110 
00111 /******************************************************************************
00112 Exported global functions (to be accessed by other files)
00113 ******************************************************************************/
00114 void GRAPHICS_SetLcdPanel_Ch0(void);
00115 void GRAPHICS_SetLcdTconSettings_Ch0(const vdc5_lcd_tcon_timing_t  * * const outctrl);
00116 
00117 
00118 #endif  /* LCD_PANEL_H not defined */
00119 #endif  /* LCD_VKLCD70RT_CH0_H */
00120