Vekatech
SDHI_driver patch (mbedOS 5.11.5)
Revision 0:e1f465d87307, committed 2019-03-18
- Comitter:
- tvendov
- Date:
- Mon Mar 18 16:54:40 2019 +0000
- Child:
- 1:6f9a14a6bcac
- Commit message:
- Initial_II
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/approach.txt Mon Mar 18 16:54:40 2019 +0000 @@ -0,0 +1,4 @@ +Опит за реюзване на вече съществъващ компонент SD (и най вече тестовете му). +Напрактика SD и SDHI правят едно и също нещо през различни физически интерфейси (SPI и SDHI контролер) +Няма много смисъл да има 2 компонента с идентична функционалност и затова SDHI отиде в SD с всички произтичащи от това последствия! +Въпреки това, SYNC_FAIL продължава да се случва! \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/components/storage/blockdevice/COMPONENT_SD/SDHIBlockDevice.cpp Mon Mar 18 16:54:40 2019 +0000
@@ -0,0 +1,638 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#if (defined(TARGET_VK_RZ_A1H) || defined(TARGET_VK_RZ_A1LU))
+
+#include "SDHIBlockDevice.h"
+#include "mbed_debug.h"
+#include <errno.h>
+
+#include "iodefine.h"
+#include "PeripheralPins.h"
+
+/* Required version: 5.6.1 and above */
+#ifdef MBED_MAJOR_VERSION
+#if (MBED_VERSION < MBED_ENCODE_VERSION(5,6,1))
+#error "Incompatible mbed-os version detected! Required 5.5.4 and above"
+#endif
+#else
+#warning "mbed-os version 5.6.1 or above required"
+#endif
+
+
+
+//#define SD_COMMAND_TIMEOUT 5000 /*!< Timeout in ms for response */
+//#define SD_CMD0_GO_IDLE_STATE_RETRIES 5 /*!< Number of retries for sending CMDO */
+#define SD_CMD_TRACE 0 /*!< 1 - Enable SD command tracing */
+
+//#define SD_BLOCK_DEVICE_ERROR_WOULD_BLOCK -5001 /*!< operation would block */
+#define SD_BLOCK_DEVICE_ERROR_UNSUPPORTED -5002 /*!< unsupported operation */
+#define SD_BLOCK_DEVICE_ERROR_PARAMETER -5003 /*!< invalid parameter */
+#define SD_BLOCK_DEVICE_ERROR_NO_INIT -5004 /*!< uninitialized */
+#define SD_BLOCK_DEVICE_ERROR_NO_DEVICE -5005 /*!< device is missing or not connected */
+#define SD_BLOCK_DEVICE_ERROR_WRITE_PROTECTED -5006 /*!< write protected */
+#define SD_BLOCK_DEVICE_ERROR_UNUSABLE -5007 /*!< unusable card */
+#define SD_BLOCK_DEVICE_ERROR_NO_RESPONSE -5008 /*!< No response from device */
+#define SD_BLOCK_DEVICE_ERROR_CRC -5009 /*!< CRC error */
+#define SD_BLOCK_DEVICE_ERROR_ERASE -5010 /*!< Erase error: reset/sequence */
+#define SD_BLOCK_DEVICE_ERROR_WRITE -5011 /*!< SPI Write error: !SPI_DATA_ACCEPTED */
+
+#define BLOCK_SIZE_HC 512 /*!< Block size supported for SD card is 512 bytes */
+#define WRITE_BL_PARTIAL 0 /*!< Partial block write - Not supported */
+//
+// Types
+#define SDCARD_NONE 0 /**< No card is present */
+#define SDCARD_V1 1 /**< v1.x Standard Capacity */
+#define SDCARD_V2 2 /**< v2.x Standard capacity SD card */
+#define SDCARD_V2HC 3 /**< v2.x High capacity SD card */
+#define CARD_UNKNOWN 4 /**< Unknown or unsupported card */
+
+/* R3 Response : OCR Register */
+#define OCR_HCS_CCS (0x1 << 30)
+#define OCR_LOW_VOLTAGE (0x01 << 24)
+#define OCR_3_3V (0x1 << 20)
+
+#define ESD_SECTOR_SIZE BLOCK_SIZE_HC
+
+#define REG_CSD_HACK
+
+#define CSD_CID_LENGTH 16
+
+#define ARRAYSIZE(arr) (size_t)(sizeof(arr)/sizeof(arr[0]))
+
+static uint32_t _sd_workbuf[SD_SIZE_OF_INIT/ sizeof(uint32_t)] __attribute__ ((section ("NC_BSS")));
+static uint32_t _sd_rw_buf[ESD_SECTOR_SIZE/sizeof(uint32_t)] __attribute__ ((section ("NC_BSS")));
+//static uint8_t _sectorBuff[ESD_SECTOR_SIZE] __attribute__ ((section ("NC_BSS")));
+
+
+static uint32_t ext_bits(unsigned char *data, size_t datasize, unsigned int msb, unsigned int lsb) {
+ uint32_t bits = 0;
+
+ if ((datasize > 0) && (msb < (datasize<<3)))
+ {
+ uint32_t size = 1 + msb - lsb;
+ for (uint32_t i = 0; i < size; i++)
+ {
+ uint32_t position = lsb + i;
+ int32_t byte = (datasize-1) - (position >> 3);
+ if( byte < 0 )
+ break;
+ uint32_t bit = position & 0x7;
+ uint32_t value = (data[byte] >> bit) & 1;
+ bits |= value << i;
+ }
+ }
+ return bits;
+}
+
+#if SDHI_DBG
+const sderr_t SDHIBlockDevice::_sd_error_msg[]= {
+ {"SD_OK", 0}, /* OK */
+ {"SD_ERR", -1}, /* general error */
+ {"SD_ERR_WP", -2}, /* write protect error */
+ {"SD_ERR_RO", -3}, /* read only error */
+ {"SD_ERR_RES_TOE", -4}, /* response time out error */
+ {"SD_ERR_CARD_TOE", -5}, /* card time out error */
+ {"SD_ERR_END_BIT", -6}, /* end bit error */
+ {"SD_ERR_CRC", -7}, /* CRC error */
+ {"SD_ERR_CARD_RES", -8}, /* card response error */
+ {"SD_ERR_HOST_TOE", -9}, /* host time out error */
+ {"SD_ERR_CARD_ERASE", -10}, /* card erase error */
+ {"SD_ERR_CARD_LOCK", -11}, /* card lock error */
+ {"SD_ERR_CARD_UNLOCK", -12}, /* card unlock error */
+ {"SD_ERR_HOST_CRC", -13}, /* host CRC error */
+ {"SD_ERR_CARD_ECC", -14}, /* card internal ECC error */
+ {"SD_ERR_CARD_CC", -15}, /* card internal error */
+ {"SD_ERR_CARD_ERROR", -16}, /* unknown card error */
+ {"SD_ERR_CARD_TYPE", -17}, /* non support card type */
+ {"SD_ERR_NO_CARD", -18}, /* no card */
+ {"SD_ERR_ILL_READ", -19}, /* illegal buffer read */
+ {"SD_ERR_ILL_WRITE", -20}, /* illegal buffer write */
+ {"SD_ERR_AKE_SEQ", -21}, /* the sequence of authentication process */
+ {"SD_ERR_OVERWRITE", -22}, /* CID/CSD overwrite error */
+ /* 23-29 */
+ {"SD_ERR_CPU_IF", -30}, /* target CPU interface function error */
+ {"SD_ERR_STOP", -31}, /* user stop */
+ /* 32-49 */
+ {"SD_ERR_CSD_VER", -50}, /* CSD register version error */
+ {"SD_ERR_SCR_VER", -51}, /* SCR register version error */
+ {"SD_ERR_FILE_FORMAT", -52}, /* CSD register file format error */
+ {"SD_ERR_NOTSUP_CMD", -53}, /* not supported command */
+ /* 54-59 */
+ {"SD_ERR_ILL_FUNC", -60}, /* invalid function request error */
+ {"SD_ERR_IO_VERIFY", -61}, /* direct write verify error */
+ {"SD_ERR_IO_CAPAB", -62}, /* IO capability error */
+ /* 63-69 */
+ {"SD_ERR_IFCOND_VER", -70}, /* Interface condition version error */
+ {"SD_ERR_IFCOND_VOLT", -71}, /* Interface condition voltage error */
+ {"SD_ERR_IFCOND_ECHO", -72}, /* Interface condition echo back pattern error */
+ /* 73-79 */
+ {"SD_ERR_OUT_OF_RANGE", -80}, /* the argument was out of range */
+ {"SD_ERR_ADDRESS_ERROR", -81},
+ {"SD_ERR_BLOCK_LEN_ERROR", -82},
+ {"SD_ERR_ILLEGAL_COMMAND", -83},
+ {"SD_ERR_RESERVED_ERROR18", -84},
+ {"SD_ERR_RESERVED_ERROR17", -85},
+ {"SD_ERR_CMD_ERROR", -86},
+ {"SD_ERR_CBSY_ERROR", -87},
+ {"SD_ERR_NO_RESP_ERROR", -88},
+ /* 89 */
+ /* 90-95 */
+ {"SD_ERR_ERROR", -96},
+ {"SD_ERR_FUNCTION_NUMBER", -97},
+ {"SD_ERR_COM_CRC_ERROR", -98},
+ {"SD_ERR_INTERNAL", -99}, /* driver software internal error */
+};
+
+#endif
+
+SDHIBlockDevice::SDHIBlockDevice(uint32_t sdport)
+{
+ _init_ref_count = 0;
+ Initialize(sdport);
+// for( uint32_t n=0; n < ARRAYSIZE(_sd_error_msg); n++ )
+// {
+// _sd_err_map[_sd_error_msg[n].errorno] = _sd_error_msg[n].msg;
+// }
+//
+// if ( sdport < SDHI_COUNT )
+// {
+// _sd_channel = sdport;
+// _regbase = (uint32_t)((_sd_channel == 0ul) ? &SDHI0 : &SDHI1);
+//
+// _card_type = SDCARD_NONE;
+//
+// // Set default to 100kHz for initialisation and 1MHz for data transfer
+// _init_sck = 100000;
+// _transfer_sck = hz;
+//
+// // Only HC block size is supported.
+// _block_size = BLOCK_SIZE_HC;
+// _erase_size = BLOCK_SIZE_HC;
+// _mtx_lock = false;
+//
+// int32_t sd_err = sd_init( _sd_channel, _regbase, &_sd_workbuf[0], SD_CD_SOCKET );
+// if ( sd_err != SD_OK)
+// {
+// _error(sd_err);
+//// return SD_BLOCK_DEVICE_ERROR_NO_DEVICE;
+// }
+//
+// void *rw_buff = (void *)&_sd_rw_buf[0];
+//
+// sd_err = sd_set_buffer( _sd_channel, rw_buff, (unsigned long)sizeof(_sd_rw_buf) );
+// if ( sd_err != SD_OK )
+// {
+// _error(sd_err);
+// }
+//
+// }
+// else
+// {
+// _sd_channel = -1;
+// _regbase = 0ul;
+//
+// }
+}
+
+SDHIBlockDevice::SDHIBlockDevice(PinName sd_CLK, PinName sd_CMD, PinName sd_CD, PinName sd_WP,
+ PinName sd_D0, PinName sd_D1, PinName sd_D2, PinName sd_D3 )
+{
+ _init_ref_count = 0;
+
+ uint32_t sd_wp = pinmap_peripheral(sd_WP, PinMap_SDHI_WP);
+ uint32_t sd_cd = pinmap_peripheral(sd_CD, PinMap_SDHI_CD);
+ uint32_t sd_clk = pinmap_peripheral(sd_CLK, PinMap_SDHI_CLK);
+ uint32_t sd_cmd = pinmap_peripheral(sd_CMD, PinMap_SDHI_CMD);
+ uint32_t sd_d0 = pinmap_peripheral(sd_D0, PinMap_SDHI_D0);
+ uint32_t sd_d1 = pinmap_peripheral(sd_D1, PinMap_SDHI_D1);
+ uint32_t sd_d2 = pinmap_peripheral(sd_D2, PinMap_SDHI_D2);
+ uint32_t sd_d3 = pinmap_peripheral(sd_D3, PinMap_SDHI_D3);
+
+ uint32_t sd_cntl_1 = pinmap_merge(sd_wp, sd_cd);
+ uint32_t sd_cntl_2 = pinmap_merge(sd_clk, sd_cmd);
+ uint32_t sd_cntl = pinmap_merge(sd_cntl_1, sd_cntl_2);
+
+ uint32_t sd_data_1 = pinmap_merge(sd_d0, sd_d1);
+ uint32_t sd_data_2 = pinmap_merge(sd_d2, sd_d3);
+ uint32_t sd_data = pinmap_merge(sd_data_1, sd_data_2);
+
+ uint32_t sdport = pinmap_merge(sd_cntl, sd_data);
+
+ MBED_ASSERT((int)sdport != NC);
+
+ Initialize(sdport);
+}
+
+
+
+SDHIBlockDevice::~SDHIBlockDevice()
+{
+ if (_is_initialized) {
+ deinit();
+ }
+}
+
+void SDHIBlockDevice::Initialize( uint32_t sdport )
+{
+#if SDHI_DBG
+ for( uint32_t n=0; n < ARRAYSIZE(_sd_error_msg); n++ )
+ {
+ _sd_err_map[_sd_error_msg[n].errorno] = _sd_error_msg[n].msg;
+ }
+#endif
+ _sectors = 0;
+ _is_initialized = 0;
+ if ( sdport < SDHI_COUNT )
+ {
+ _sd_channel = sdport;
+ _regbase = (uint32_t)((_sd_channel == SDHI_0) ? &SDHI0 : &SDHI1);
+
+ _card_type = SDCARD_NONE;
+
+ // Only HC block size is supported.
+ _block_size = BLOCK_SIZE_HC;
+ _erase_size = BLOCK_SIZE_HC;
+
+ int32_t sd_err = sd_init( _sd_channel, _regbase, &_sd_workbuf[0], SD_CD_SOCKET );
+ if ( sd_err != SD_OK)
+ {
+ _error(sd_err);
+ }
+
+ void *rw_buff = (void *)&_sd_rw_buf[0];
+
+ sd_err = sd_set_buffer( _sd_channel, rw_buff, (unsigned long)sizeof(_sd_rw_buf) );
+ if ( sd_err != SD_OK )
+ {
+ _error(sd_err);
+ }
+ }
+ else
+ {
+ _sd_channel = -1;
+ _regbase = 0ul;
+
+ }
+
+}
+
+int SDHIBlockDevice::_initialise_card()
+{
+ // Detail debugging is for commands
+ _dbg = SDHI_DBG ? SD_CMD_TRACE : 0;
+
+ int32_t status = BD_ERROR_OK;
+
+ int32_t sd_err;
+
+ if( _regbase )
+ {
+ sd_err = sd_mount(_sd_channel, SDCFG_DRIVER_MODE, SD_VOLT_3_3);
+
+ if ( sd_err != SD_OK )
+ {
+ _error(sd_err);
+ return SD_BLOCK_DEVICE_ERROR_UNUSABLE;
+ }
+ uint8_t card_type;
+ uint8_t card_speed;
+ uint8_t card_capa;
+
+ sd_err=sd_get_type(_sd_channel, &card_type, &card_speed, &card_capa);
+ if( sd_err != SD_OK)
+ {
+ return _error(sd_err);
+ }
+
+ if( (card_type & SD_MEDIA_SD) != SD_MEDIA_SD )
+ {
+ return SD_BLOCK_DEVICE_ERROR_UNUSABLE;
+ }
+
+ uint32_t regOCR;
+ uint8_t regCID[CSD_CID_LENGTH];
+ uint8_t regCSD[CSD_CID_LENGTH];
+ uint8_t regDSR[2];
+ uint8_t regSCR[8];
+
+ sd_err = sd_get_reg(_sd_channel, (uint8_t *)®OCR, regCID, regCSD, regDSR, regSCR);
+ if (sd_err != SD_OK)
+ {
+ return _error(sd_err);
+ }
+ regOCR = __REV(regOCR);
+ // Check if card supports voltage range: 3.3V
+ if (!(regOCR & OCR_3_3V)) {
+ _card_type = CARD_UNKNOWN;
+ status = SD_BLOCK_DEVICE_ERROR_UNUSABLE;
+ return status;
+ }
+ }
+ else
+ {
+ status = SD_BLOCK_DEVICE_ERROR_NO_INIT;
+ }
+
+ return status;
+}
+
+
+int SDHIBlockDevice::init()
+{
+ vMutex l(&_mutex);
+
+ if(!_is_initialized)
+ _init_ref_count = 0;
+
+ _init_ref_count++;
+
+ if(_init_ref_count != 1)
+ return BD_ERROR_OK;
+
+ int err = _initialise_card();
+ _is_initialized = (err == BD_ERROR_OK);
+ if (!_is_initialized) {
+ debug_if(SDHI_DBG, "Fail to initialize card\n");
+ return err;
+ }
+ debug_if(SDHI_DBG, "init card = %d\r\n", _is_initialized);
+ _sectors = _sd_sectors();
+
+ if (0 == _sectors) {
+ return BD_ERROR_DEVICE_ERROR;
+ }
+
+ return BD_ERROR_OK;
+}
+
+int SDHIBlockDevice::deinit()
+{
+ vMutex l(&_mutex);
+
+ if(!_is_initialized)
+ _init_ref_count = 0;
+
+ _init_ref_count--; //!!!
+
+ if(_init_ref_count)
+ return BD_ERROR_OK;
+
+ _sectors = 0;
+ if ( _is_initialized )
+ {
+ sd_unmount(_sd_channel);
+ debug_if(SDHI_DBG, "card deinited![%d]\r\n", _is_initialized);
+ _is_initialized = false;
+ }
+ return 0;
+}
+
+
+int SDHIBlockDevice::program(const void *b, bd_addr_t addr, bd_size_t size)
+{
+ if (!is_valid_program(addr, size)) {
+ return SD_BLOCK_DEVICE_ERROR_PARAMETER;
+ }
+
+ vMutex l(&_mutex);
+
+ if (!_is_initialized) {
+ return SD_BLOCK_DEVICE_ERROR_NO_INIT;
+ }
+
+ uint8_t* buffer = const_cast<uint8_t*>(static_cast<const uint8_t*>(b));
+ int status = BD_ERROR_OK;
+
+ // Get block count
+ bd_addr_t blockCnt = size / _block_size;
+
+ addr = addr / _block_size;
+
+ // Send command to perform write operation
+ int32_t sd_err = sd_write_sect( _sd_channel, buffer, addr, blockCnt, SD_WRITE_OVERWRITE);
+
+ if (sd_err != SD_OK)
+ {
+ _error(sd_err);
+ status = SD_BLOCK_DEVICE_ERROR_WRITE;
+ }
+
+ return status;
+}
+
+int SDHIBlockDevice::read(void *b, bd_addr_t addr, bd_size_t size)
+{
+ if (!is_valid_read(addr, size)) {
+ return SD_BLOCK_DEVICE_ERROR_PARAMETER;
+ }
+
+ vMutex l(&_mutex);
+
+ if (!_is_initialized) {
+ return SD_BLOCK_DEVICE_ERROR_NO_INIT;
+ }
+ uint8_t *buffer = static_cast<uint8_t*>(b);
+ int status = BD_ERROR_OK;
+ bd_addr_t blockCnt = size / _block_size;
+
+ addr = addr / _block_size;
+
+ int32_t sd_err = sd_read_sect(_sd_channel, buffer, addr, blockCnt);
+
+ if (sd_err != SD_OK)
+ {
+ _error(sd_err);
+ status = SD_BLOCK_DEVICE_ERROR_NO_RESPONSE;
+ }
+
+ return status;
+}
+
+int SDHIBlockDevice::erase(bd_addr_t addr, bd_size_t size)
+{
+ return 0;
+}
+
+
+bool SDHIBlockDevice::_is_valid_trim(bd_addr_t addr, bd_size_t size)
+{
+ return (
+ addr % _erase_size == 0 &&
+ size % _erase_size == 0 &&
+ addr + size <= this->size());
+}
+
+int SDHIBlockDevice::trim(bd_addr_t addr, bd_size_t size)
+{
+ if (!_is_valid_trim(addr, size)) {
+ return SD_BLOCK_DEVICE_ERROR_PARAMETER;
+ }
+
+ vMutex l(&_mutex);
+
+ if (!_is_initialized) {
+ return SD_BLOCK_DEVICE_ERROR_NO_INIT;
+ }
+ int status = BD_ERROR_OK;
+
+ size -= _block_size;
+ // SDSC Card (CCS=0) uses byte unit address
+ // SDHC and SDXC Cards (CCS=1) use block unit address (512 Bytes unit)
+ if (SDCARD_V2HC == _card_type) {
+ size = size / _block_size;
+ addr = addr / _block_size;
+ }
+
+ return status;
+}
+
+bd_size_t SDHIBlockDevice::get_read_size() const
+{
+ return _block_size;
+}
+
+bd_size_t SDHIBlockDevice::get_program_size() const
+{
+ return _block_size;
+}
+
+/*
+bd_size_t SDHIBlockDevice::get_erase_size() const
+{
+ return _block_size;
+}
+*/
+
+bd_size_t SDHIBlockDevice::size() const
+{
+ return _block_size*_sectors;
+}
+
+void SDHIBlockDevice::debug(bool dbg)
+{
+ _dbg = dbg;
+}
+
+const char *SDHIBlockDevice::get_type() const
+{
+ return "RZ-SDHI";
+}
+
+// PRIVATE FUNCTIONS
+
+bd_size_t SDHIBlockDevice::_sd_sectors() {
+ uint32_t c_size, c_size_mult, read_bl_len;
+ uint32_t block_len, mult, blocknr;
+ uint32_t hc_c_size;
+ bd_size_t blocks = 0, capacity = 0;
+ uint8_t csd[CSD_CID_LENGTH];
+
+ int32_t sd_err = sd_get_reg(_sd_channel, NULL, NULL, csd, NULL, NULL);
+ if ( sd_err != SD_OK )
+ {
+ debug_if(SDHI_DBG, "Couldn't read csd response from disk\r\n");
+ _error(sd_err);
+ return 0;
+ }
+ for(int i = 0; i < (CSD_CID_LENGTH-1); i++)
+ {
+ csd[i] = csd[i+1];
+ }
+
+ debug_if(SDHI_DBG,"CSD is ");
+ for(unsigned int i = 0; i < sizeof(csd); i++)
+ {
+ debug_if(SDHI_DBG, "%02X ", csd[i]);
+ }
+ debug_if(SDHI_DBG,"\r\n");
+
+ // csd_structure : csd[127:126]
+ int csd_structure = ext_bits(csd, CSD_CID_LENGTH, 127, 126);
+ switch (csd_structure) {
+ case 0:
+ c_size = ext_bits(csd, CSD_CID_LENGTH, 73, 62); // c_size : csd[73:62]
+ c_size_mult = ext_bits(csd, CSD_CID_LENGTH, 49, 47); // c_size_mult : csd[49:47]
+ read_bl_len = ext_bits(csd, CSD_CID_LENGTH, 83, 80); // read_bl_len : csd[83:80] - the *maximum* read block length
+ block_len = 1 << read_bl_len; // BLOCK_LEN = 2^READ_BL_LEN
+ mult = 1 << (c_size_mult + 2); // MULT = 2^C_SIZE_MULT+2 (C_SIZE_MULT < 8)
+ blocknr = (c_size + 1) * mult; // BLOCKNR = (C_SIZE+1) * MULT
+ capacity = blocknr * block_len; // memory capacity = BLOCKNR * BLOCK_LEN
+ blocks = capacity / _block_size;
+ debug_if(SDHI_DBG, "Standard Capacity: c_size: %lu\r\n", c_size);
+ debug_if(SDHI_DBG, "Sectors: 0x%llx : %llu\r\n", blocks, blocks);
+ debug_if(SDHI_DBG, "Capacity: 0x%llx : %llu MB\r\n", capacity, (capacity/(1024U*1024U)));
+
+ // ERASE_BLK_EN = 1: Erase in multiple of 512 bytes supported
+ if (ext_bits(csd, CSD_CID_LENGTH, 46, 46)) {
+ _erase_size = BLOCK_SIZE_HC;
+ } else {
+ // ERASE_BLK_EN = 1: Erase in multiple of SECTOR_SIZE supported
+ _erase_size = BLOCK_SIZE_HC * (ext_bits(csd, CSD_CID_LENGTH, 45, 39) + 1);
+ }
+ break;
+
+ case 1:
+ hc_c_size = ext_bits(csd, CSD_CID_LENGTH, 69, 48); // device size : C_SIZE : [69:48]
+ blocks = (hc_c_size+1) << 10; // block count = C_SIZE+1) * 1K byte (512B is block size)
+ debug_if(SDHI_DBG, "SDHC/SDXC Card: hc_c_size: %lu\r\n", hc_c_size);
+ debug_if(SDHI_DBG, "Sectors: 0x%llx : %llu\r\n", blocks, blocks);
+ debug_if(SDHI_DBG, "Capacity: %llu MB\r\n", (blocks/(2048U)));
+ // ERASE_BLK_EN is fixed to 1, which means host can erase one or multiple of 512 bytes.
+ _erase_size = BLOCK_SIZE_HC;
+ break;
+
+ default:
+ debug_if(SDHI_DBG, "CSD struct unsupported\r\n");
+ return 0;
+ };
+ return blocks;
+}
+
+const char * SDHIBlockDevice::_sderr_msg(int32_t errorno)
+{
+#if SDHI_DBG
+ map<int32_t, const char *>::iterator it = _sd_err_map.find(errorno);
+
+ if ( it != _sd_err_map.end() )
+ return it->second;
+ else
+ return "SD UNKNWON ERROR NO\n";
+#else
+ return (const char *)0;
+#endif
+}
+
+int SDHIBlockDevice::_error(int32_t errcode)
+{
+ int32_t sd_err = errcode;
+ if(_sd_channel >= 0 && _sd_channel < SDHI_COUNT )
+ {
+ int32_t err = sd_get_error(_sd_channel);
+ if ( err != SD_OK)
+ sd_err = err;
+ debug_if(SDHI_DBG, _sderr_msg(sd_err));
+ }
+ return sd_err;
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/components/storage/blockdevice/COMPONENT_SD/SDHIBlockDevice.h Mon Mar 18 16:54:40 2019 +0000
@@ -0,0 +1,242 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_RZ_SDHI_BLOCK_DEVICE_HPP
+#define MBED_RZ_SDHI_BLOCK_DEVICE_HPP
+
+/* If the target has no SPI support then SDCard is not supported */
+#ifdef DEVICE_SPI
+
+#include "BlockDevice.h"
+#include "mbed.h"
+#include "platform/PlatformMutex.h"
+#include <map>
+
+//#include "r_typedefs.h"
+
+#include "sdif.h"
+#include "sd_cfg.h"
+
+#define SDHI_DBG 1 /*!< 1 - Enable debugging */
+
+/** Access an SD Card using SDHI
+ *
+ * @code
+ * #include "mbed.h"
+ * #include "SDHIBlockDevice.h"
+ *
+ * SDHIBlockDevice rz_sdhi(p5, p6, p7, p12, p13, p14, p15, p2); // CLK, CMD, CD, WP, D0, D1, D2, D3
+ * -- or --
+ * #define SDHI_CHANNEL 0
+ * SDHIBlockDevice rz_sdhi(SDHI_CHANNEL); // use channel 0
+ *
+ * uint8_t block[512] = "Hello World!\n";
+ *
+ * int main() {
+ * rz_sdhi.init();
+ * rz_sdhi.write(block, 0, 512);
+ * rz_sdhi.read(block, 0, 512);
+ * printf("%s", block);
+ * rz_sdhi.deinit();
+ * }
+ */
+
+class vMutex
+{
+public:
+ vMutex(PlatformMutex * mtx) :
+ _mutex(mtx)
+ {
+ if (_mutex)
+ _mutex->lock();
+ }
+ virtual ~vMutex()
+ {
+ if(_mutex)
+ _mutex->unlock();
+ }
+
+private:
+ PlatformMutex * _mutex;
+};
+
+typedef struct {
+ const char *msg;
+ int32_t errorno;
+} sderr_t;
+
+
+
+class SDHIBlockDevice : public BlockDevice {
+public:
+ /** Lifetime of an SD card
+ */
+ SDHIBlockDevice(uint32_t sdport);
+ SDHIBlockDevice(PinName sd_CLK, PinName sd_CMD, PinName sd_CD, PinName sd_WP,
+ PinName sd_D0, PinName sd_D1, PinName sd_D2, PinName sd_D3 );
+ virtual ~SDHIBlockDevice();
+
+ /** Initialize a block device
+ *
+ * @return 0 on success or a negative error code on failure
+ */
+ virtual int init();
+
+ /** Deinitialize a block device
+ *
+ * @return 0 on success or a negative error code on failure
+ */
+ virtual int deinit();
+
+ /** Read blocks from a block device
+ *
+ * @param buffer Buffer to write blocks to
+ * @param addr Address of block to begin reading from
+ * @param size Size to read in bytes, must be a multiple of read block size
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int read(void *buffer, bd_addr_t addr, bd_size_t size);
+
+ /** Program blocks to a block device
+ *
+ * The blocks must have been erased prior to being programmed
+ *
+ * @param buffer Buffer of data to write to blocks
+ * @param addr Address of block to begin writing to
+ * @param size Size to write in bytes, must be a multiple of program block size
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int program(const void *buffer, bd_addr_t addr, bd_size_t size);
+
+ /** Erase blocks on a block device
+ *
+ * The state of an erased block is undefined until it has been programmed
+ *
+ * @param addr Address of block to begin erasing
+ * @param size Size to erase in bytes, must be a multiple of erase block size
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int erase(bd_addr_t addr, bd_size_t size);
+
+
+ /** Mark blocks as no longer in use
+ *
+ * This function provides a hint to the underlying block device that a region of blocks
+ * is no longer in use and may be erased without side effects. Erase must still be called
+ * before programming, but trimming allows flash-translation-layers to schedule erases when
+ * the device is not busy.
+ *
+ * @param addr Address of block to mark as unused
+ * @param size Size to mark as unused in bytes, must be a multiple of erase block size
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int trim(bd_addr_t addr, bd_size_t size);
+
+ /** Get the size of a readable block
+ *
+ * @return Size of a readable block in bytes
+ */
+ virtual bd_size_t get_read_size() const;
+
+ /** Get the size of a programable block
+ *
+ * @return Size of a programable block in bytes
+ * @note Must be a multiple of the read size
+ */
+ virtual bd_size_t get_program_size() const;
+
+ /** Get the size of a eraseable block
+ *
+ * @return Size of a eraseable block in bytes
+ * @note Must be a multiple of the program size
+ */
+ /*virtual bd_size_t get_erase_size() const; */
+
+
+ /** Get the total size of the underlying device
+ *
+ * @return Size of the underlying device in bytes
+ */
+ virtual bd_size_t size() const;
+
+ /** Enable or disable debugging
+ *
+ * @param State of debugging
+ */
+ virtual void debug(bool dbg);
+
+ /** Get the BlockDevice class type.
+ *
+ * @return A string represent the BlockDevice class type.
+ */
+
+ virtual const char *get_type() const;
+
+protected:
+ void Initialize( uint32_t sdport );
+
+private:
+
+ uint8_t _card_type;
+
+ /* Move the SDCard into the SPI Mode idle state
+ *
+ * The card is transitioned from SDCard mode to SPI mode by sending the
+ * CMD0 (GO_IDLE_STATE) command with CS asserted. See the notes in the
+ * "SPI Startup" section of the comments at the head of the
+ * implementation file for further details and specification references.
+ *
+ * @return Response form the card. R1_IDLE_STATE (0x1), the successful
+ * response from CMD0. R1_XXX_XXX for more response
+ */
+// uint32_t _go_idle_state();
+ int _initialise_card();
+
+ bd_size_t _sectors;
+ bd_size_t _sd_sectors();
+
+ bool _is_valid_trim(bd_addr_t addr, bd_size_t size);
+
+ const char * _sderr_msg(int32_t errorno);
+
+ int _error(int32_t errcode);
+
+ PlatformMutex _mutex;
+
+ bd_size_t _block_size;
+ bd_size_t _erase_size;
+ bool _is_initialized;
+ bool _dbg;
+ uint32_t _init_ref_count;
+
+ int32_t _sd_channel;
+ uint32_t _regbase;
+#if SDHI_DBG
+ static const sderr_t _sd_error_msg[];
+
+ map<int32_t, const char *> _sd_err_map;
+#endif
+};
+
+#endif /* DEVICE_SPI */
+
+#endif /* MBED_RZ_SDHI_BLOCK_DEVICE_HPP */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/components/storage/blockdevice/COMPONENT_SD/TESTS/filesystem/fopen/fopen.cpp Mon Mar 18 16:54:40 2019 +0000
@@ -0,0 +1,1652 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/** @file fopen.cpp Test cases to POSIX file fopen() interface.
+ *
+ * Please consult the documentation under the test-case functions for
+ * a description of the individual test case.
+ */
+
+#include "mbed.h"
+#include "mbed_config.h"
+#if (defined(TARGET_VK_RZ_A1H) || defined(TARGET_VK_RZ_A1LU))
+ #include "SDHIBlockDevice.h"
+#else
+ #include "SDBlockDevice.h"
+#endif
+#include "FATFileSystem.h"
+#include "fsfat_debug.h"
+#include "fsfat_test.h"
+#include "utest/utest.h"
+#include "unity/unity.h"
+#include "greentea-client/test_env.h"
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h> /*rand()*/
+#include <inttypes.h>
+#include <errno.h>
+/* mbed_retarget.h is included after errno.h so symbols are mapped to
+ * consistent values for all toolchains */
+#include "platform/mbed_retarget.h"
+
+using namespace utest::v1;
+
+/// @cond FSFAT_DOXYGEN_DISABLE
+#ifdef FSFAT_DEBUG
+#define FSFAT_FOPEN_GREENTEA_TIMEOUT_S 3000
+#else
+#define FSFAT_FOPEN_GREENTEA_TIMEOUT_S 1000
+#endif
+/// @endcond
+
+
+/* DEVICE_SPI
+ * This symbol is defined in targets.json if the target has a SPI interface, which is required for SDCard support.
+ *
+ * MBED_CONF_APP_FSFAT_SDCARD_INSTALLED
+ * For testing purposes, an SDCard must be installed on the target for the test cases in this file to succeed.
+ * If the target has an SD card installed then the MBED_CONF_APP_FSFAT_SDCARD_INSTALLED will be generated
+ * from the mbed_app.json, which includes the line
+ * {
+ * "config": {
+ * "UART_RX": "D0",
+ * <<< lines removed >>>
+ * "DEVICE_SPI": 1,
+ * "FSFAT_SDCARD_INSTALLED": 1
+ * },
+ * <<< lines removed >>>
+ */
+
+#if DEVICE_SPI && ( defined(MBED_CONF_APP_FSFAT_SDCARD_INSTALLED) || (MBED_CONF_SD_FSFAT_SDCARD_INSTALLED))
+static char fsfat_fopen_utest_msg_g[FSFAT_UTEST_MSG_BUF_SIZE];
+#define FSFAT_FOPEN_TEST_MOUNT_PT_NAME "sd"
+#define FSFAT_FOPEN_TEST_MOUNT_PT_PATH "/" FSFAT_FOPEN_TEST_MOUNT_PT_NAME
+#define FSFAT_FOPEN_TEST_WORK_BUF_SIZE_1 64
+#define FSFAT_FOPEN_TEST_FILEPATH_MAX_DEPTH 20
+static const char *sd_badfile_path = "/sd/badfile.txt";
+static const char *sd_testfile_path = "/sd/test.txt";
+
+#if (defined(TARGET_VK_RZ_A1H) || defined(TARGET_VK_RZ_A1LU))
+ SDHIBlockDevice sd(MBED_CONF_SD_SDHI_CH);
+#else
+ SDBlockDevice sd(MBED_CONF_SD_SPI_MOSI, MBED_CONF_SD_SPI_MISO, MBED_CONF_SD_SPI_CLK, MBED_CONF_SD_SPI_CS);
+#endif
+FATFileSystem fs("sd", &sd);
+
+#define FSFAT_FOPEN_TEST_00 fsfat_fopen_test_00
+#define FSFAT_FOPEN_TEST_01 fsfat_fopen_test_01
+#define FSFAT_FOPEN_TEST_02 fsfat_fopen_test_02
+#define FSFAT_FOPEN_TEST_03 fsfat_fopen_test_03
+#define FSFAT_FOPEN_TEST_04 fsfat_fopen_test_04
+#define FSFAT_FOPEN_TEST_05 fsfat_fopen_test_05
+#define FSFAT_FOPEN_TEST_06 fsfat_fopen_test_06
+#define FSFAT_FOPEN_TEST_07 fsfat_fopen_test_07
+#define FSFAT_FOPEN_TEST_08 fsfat_fopen_test_08
+#define FSFAT_FOPEN_TEST_09 fsfat_fopen_test_09
+#define FSFAT_FOPEN_TEST_10 fsfat_fopen_test_10
+#define FSFAT_FOPEN_TEST_11 fsfat_fopen_test_11
+#define FSFAT_FOPEN_TEST_12 fsfat_fopen_test_12
+#define FSFAT_FOPEN_TEST_13 fsfat_fopen_test_13
+#define FSFAT_FOPEN_TEST_14 fsfat_fopen_test_14
+#define FSFAT_FOPEN_TEST_15 fsfat_fopen_test_15
+#define FSFAT_FOPEN_TEST_16 fsfat_fopen_test_16
+#define FSFAT_FOPEN_TEST_17 fsfat_fopen_test_17
+#define FSFAT_FOPEN_TEST_18 fsfat_fopen_test_18
+#define FSFAT_FOPEN_TEST_19 fsfat_fopen_test_19
+#define FSFAT_FOPEN_TEST_20 fsfat_fopen_test_20
+#define FSFAT_FOPEN_TEST_21 fsfat_fopen_test_21
+#define FSFAT_FOPEN_TEST_22 fsfat_fopen_test_22
+#define FSFAT_FOPEN_TEST_23 fsfat_fopen_test_23
+#define FSFAT_FOPEN_TEST_24 fsfat_fopen_test_24
+#define FSFAT_FOPEN_TEST_25 fsfat_fopen_test_25
+#define FSFAT_FOPEN_TEST_26 fsfat_fopen_test_26
+#define FSFAT_FOPEN_TEST_27 fsfat_fopen_test_27
+#define FSFAT_FOPEN_TEST_28 fsfat_fopen_test_28
+#define FSFAT_FOPEN_TEST_29 fsfat_fopen_test_29
+#define FSFAT_FOPEN_TEST_30 fsfat_fopen_test_30
+
+
+/* support functions */
+
+/*
+ * open tests that focus on testing fopen()
+ * fsfat_handle_t fopen(const char* filename, char* data, size_t* len, fsfat_key_desc_t* kdesc)
+ */
+
+/* file data for test_01 */
+static fsfat_kv_data_t fsfat_fopen_test_01_kv_data[] = {
+ { "/sd/fopentst/hello/world/animal/wobbly/dog/foot/frontlft.txt", "missing"},
+ { NULL, NULL},
+};
+
+
+/** @brief
+ * Split a file path into its component parts, setting '/' characters to '\0', and returning
+ * pointers to the file path components in the parts array. For example, if
+ * filepath = "/sd/fopentst/hello/world/animal/wobbly/dog/foot/frontlft.txt" then
+ * *parts[0] = "sd"
+ * *parts[1] = "fopentst"
+ * *parts[2] = "hello"
+ * *parts[3] = "world"
+ * *parts[4] = "animal"
+ * *parts[5] = "wobbly"
+ * *parts[6] = "dog"
+ * *parts[7] = "foot"
+ * *parts[8] = "frontlft.txt"
+ * parts[9] = NULL
+ *
+ * ARGUMENTS
+ * @param filepath IN file path string to split into component parts. Expected to start with '/'
+ * @param parts IN OUT array to hold pointers to parts
+ * @param num IN number of components available in parts
+ *
+ * @return On success, this returns the number of components in the filepath Returns number of compoee
+ */
+static int32_t fsfat_filepath_split(char *filepath, char *parts[], uint32_t num)
+{
+ uint32_t i = 0;
+ int32_t ret = -1;
+ char *z = filepath;
+
+ while (i < num && *z != '\0') {
+ if (*z == '/') {
+ *z = '\0';
+ parts[i] = ++z;
+ i++;
+ } else {
+ z++;
+ }
+ }
+ if (*z == '\0' && i > 0) {
+ ret = (int32_t) i;
+ }
+ return ret;
+}
+
+
+/** @brief
+ * remove all directories and file in the given filepath
+ *
+ * ARGUMENTS
+ * @param filepath IN file path string to split into component parts. Expected to start with '/'
+ *
+ * @return On success, this returns 0, otherwise < 0 is returned;
+ */
+int32_t fsfat_filepath_remove_all(char *filepath)
+{
+ int32_t ret = -1;
+ int32_t len = 0;
+ char *fpathbuf = NULL;
+ char *pos = NULL;
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ len = strlen(filepath);
+ fpathbuf = (char *) malloc(len + 1);
+ if (fpathbuf == NULL) {
+ FSFAT_DBGLOG("%s: failed to duplicate string (out of memory)\n", __func__);
+ return ret;
+ }
+ memset(fpathbuf, 0, len + 1);
+ memcpy(fpathbuf, filepath, len);
+
+ /* delete the leaf node first, and then successively parent directories. */
+ pos = fpathbuf + strlen(fpathbuf);
+ while (pos != fpathbuf) {
+ /* If the remaining file path is the mount point path then finish as the mount point cannot be removed */
+ if (strlen(fpathbuf) == strlen(FSFAT_FOPEN_TEST_MOUNT_PT_PATH)) {
+ if (strncmp(fpathbuf, FSFAT_FOPEN_TEST_MOUNT_PT_PATH, strlen(fpathbuf)) == 0) {
+ break;
+ }
+ }
+ ret = remove(fpathbuf);
+ pos = strrchr(fpathbuf, '/');
+ *pos = '\0';
+ }
+ if (fpathbuf) {
+ free(fpathbuf);
+ }
+ return ret;
+}
+
+
+/** @brief
+ * make all directories in the given filepath. Do not create the file if present at end of filepath
+ *
+ * ARGUMENTS
+ * @param filepath IN file path containing directories and file
+ * @param do_asserts IN set to true if function should assert on errors
+ *
+ * @return On success, this returns 0, otherwise < 0 is returned;
+ */
+static int32_t fsfat_filepath_make_dirs(char *filepath, bool do_asserts)
+{
+ int32_t i = 0;
+ int32_t num_parts = 0;
+ int32_t len = 0;
+ int32_t ret = -1;
+ char *fpathbuf = NULL;
+ char *buf = NULL;
+ int pos = 0;
+ char *parts[FSFAT_FOPEN_TEST_FILEPATH_MAX_DEPTH];
+
+ FSFAT_DBGLOG("%s:entered\n", __func__);
+ /* find the dirs to create*/
+ memset(parts, 0, sizeof(parts));
+ len = strlen(filepath);
+ fpathbuf = (char *) malloc(len + 1);
+ if (fpathbuf == NULL) {
+ FSFAT_DBGLOG("%s: failed to duplicate string (out of memory)\n", __func__);
+ return ret;
+ }
+ memset(fpathbuf, 0, len + 1);
+ memcpy(fpathbuf, filepath, len);
+ num_parts = fsfat_filepath_split(fpathbuf, parts, FSFAT_FOPEN_TEST_FILEPATH_MAX_DEPTH);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to split filepath (filename=\"%s\", num_parts=%d)\n", __func__, filepath, (int) num_parts);
+ TEST_ASSERT_MESSAGE(num_parts > 0, fsfat_fopen_utest_msg_g);
+
+ /* Now create the directories on the directory path.
+ * Skip creating dir for "/sd" which must be present */
+ buf = (char *) malloc(strlen(filepath) + 1);
+ memset(buf, 0, strlen(filepath) + 1);
+ pos = sprintf(buf, "/%s", parts[0]);
+ for (i = 1; i < num_parts - 1; i++) {
+ pos += sprintf(buf + pos, "/%s", parts[i]);
+ FSFAT_DBGLOG("mkdir(%s)\n", buf);
+ ret = mkdir(buf, S_IRWXU | S_IRWXG | S_IROTH | S_IXOTH);
+ if (do_asserts == true) {
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create directory (filepath2=\"%s\", ret=%d, errno=%d)\n", __func__, buf, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+ }
+ }
+
+ if (buf) {
+ free(buf);
+ }
+ if (fpathbuf) {
+ free(fpathbuf);
+ }
+ return ret;
+}
+
+/** @brief
+ * First and last test must format the SD card to FAT FS format:
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_00(const size_t call_count)
+{
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+ int32_t ret = -1;
+
+ fs.unmount();
+ ret = fs.format(&sd);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to format sdcard (ret=%d)\n", __func__, (int) ret);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+ fs.mount(&sd);
+
+ return CaseNext;
+}
+
+
+/* FIX ME: errno not set correctly when error occurs. This indicates a problem with the implementation. */
+
+/** @brief
+ * Basic fopen test which does the following:
+ * - creates file and writes some data to the value blob.
+ * - closes the newly created file.
+ * - opens the file (r-only)
+ * - reads the file data and checks its the same as the previously created data.
+ * - closes the opened file
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+static control_t fsfat_fopen_test_01(const size_t call_count)
+{
+ char *read_buf;
+ int32_t ret = 0;
+ size_t len = 0;
+ fsfat_kv_data_t *node;
+ FILE *fp = NULL;
+
+ FSFAT_DBGLOG("%s:entered\n", __func__);
+ (void) call_count;
+ node = fsfat_fopen_test_01_kv_data;
+
+ /* remove file and directory from a previous failed test run, if present */
+ fsfat_filepath_remove_all((char *) node->filename);
+
+ /* create dirs */
+ ret = fsfat_filepath_make_dirs((char *) node->filename, true);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create dirs for filename (filename=\"%s\")(ret=%d)\n", __func__, node->filename, (int) ret);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ FSFAT_DBGLOG("%s:About to create new file (filename=\"%s\", data=\"%s\")\n", __func__, node->filename, node->value);
+ fp = fopen(node->filename, "w+");
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create file (filename=\"%s\", data=\"%s\")(ret=%d, errno=%d)\n", __func__, node->filename,
+ node->value, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(fp != NULL, fsfat_fopen_utest_msg_g);
+
+ FSFAT_DBGLOG("%s:length of file=%d (filename=\"%s\", data=\"%s\")\n", __func__, (int) len, node->filename, node->value);
+ len = strlen(node->value);
+ ret = fwrite((const void *) node->value, len, 1, fp);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to write file (filename=\"%s\", data=\"%s\")(ret=%d)\n", __func__, node->filename, node->value,
+ (int) ret);
+ TEST_ASSERT_MESSAGE(ret == 1, fsfat_fopen_utest_msg_g);
+
+ FSFAT_DBGLOG("Created file successfully (filename=\"%s\", data=\"%s\")\n", node->filename, node->value);
+ ret = fclose(fp);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to close file (ret=%d, errno=%d)\n", __func__, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ /* now open the newly created key */
+ fp = NULL;
+ fp = fopen(node->filename, "r");
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to open file for reading (filename=\"%s\", data=\"%s\")(ret=%d)\n", __func__, node->filename,
+ node->value, (int) ret);
+ TEST_ASSERT_MESSAGE(fp != NULL, fsfat_fopen_utest_msg_g);
+
+ len = strlen(node->value) + 1;
+ read_buf = (char *) malloc(len);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to allocated read buffer \n", __func__);
+ TEST_ASSERT_MESSAGE(read_buf != NULL, fsfat_fopen_utest_msg_g);
+
+ FSFAT_DBGLOG("Opened file successfully (filename=\"%s\", data=\"%s\")\n", node->filename, node->value);
+ memset(read_buf, 0, len);
+ ret = fread((void *) read_buf, len, 1, fp);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to read file (filename=\"%s\", data=\"%s\", read_buf=\"%s\", ret=%d)\n", __func__, node->filename,
+ node->value, read_buf, (int) ret);
+ /* FIX ME: fread should return the number of items read, not 0 when an item is read successfully.
+ * This indicates a problem with the implementation, as the correct data is read. The correct assert should be:
+ * TEST_ASSERT_MESSAGE(ret == 1, fsfat_fopen_utest_msg_g);
+ * The following assert is curerntly used until the implementation is fixed
+ */
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ /* check read data is as expected */
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: read value data (%s) != expected value data (filename=\"%s\", data=\"%s\", read_buf=\"%s\", ret=%d)\n",
+ __func__, read_buf, node->filename, node->value, read_buf, (int) ret);
+ TEST_ASSERT_MESSAGE(strncmp(read_buf, node->value, strlen(node->value)) == 0, fsfat_fopen_utest_msg_g);
+
+ if (read_buf) {
+ free(read_buf);
+ }
+ ret = fclose(fp);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: fclose() call failed (ret=%d, errno=%d).\n", __func__, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+ return CaseNext;
+}
+
+static fsfat_kv_data_t fsfat_fopen_test_02_data[] = {
+ FSFAT_INIT_1_TABLE_MID_NODE,
+ { NULL, NULL},
+};
+
+/**
+ * @brief test to fopen() a pre-existing key and try to write it, which should fail
+ * as by default pre-existing keys are opened read-only
+ *
+ * Basic open test which does the following:
+ * - creates file with default rw perms and writes some data to the value blob.
+ * - closes the newly created file.
+ * - opens the file with the default permissions (read-only)
+ * - tries to write the file data which should fail because file was not opened with write flag set.
+ * - closes the opened key
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_02(const size_t call_count)
+{
+ int32_t ret = -1;
+ size_t len = 0;
+ FILE *fp = NULL;
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+ len = strlen(fsfat_fopen_test_02_data[0].value);
+ ret = fsfat_test_create(fsfat_fopen_test_02_data[0].filename, (char *) fsfat_fopen_test_02_data[0].value, len);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create file (ret=%d).\n", __func__, (int) ret);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+
+ /* by default, owner of key opens with read-only permissions*/
+ fp = fopen(fsfat_fopen_test_02_data[0].filename, "r");
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to open file (filename=\"%s\", ret=%d)\n", __func__, fsfat_fopen_test_02_data[0].filename, (int) ret);
+ TEST_ASSERT_MESSAGE(fp != NULL, fsfat_fopen_utest_msg_g);
+
+ len = strlen(fsfat_fopen_test_02_data[0].value);
+ ret = fwrite((const void *) fsfat_fopen_test_02_data[0].value, len, 1, fp);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: call to fwrite() succeeded when should have failed for read-only file (filename=\"%s\")(ret=%d).\n",
+ __func__, fsfat_fopen_test_02_data[0].filename, (int) ret);
+ TEST_ASSERT_MESSAGE(ret <= 0, fsfat_fopen_utest_msg_g);
+
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE, "%s:Error: fclose() call failed.\n",
+ __func__);
+ TEST_ASSERT_MESSAGE(fclose(fp) == 0, fsfat_fopen_utest_msg_g);
+
+ return CaseNext;
+}
+
+
+/**
+ * @brief test to fopen() a pre-existing file and try to write it, which should succeed
+ * because the key was opened read-write permissions explicitly
+ *
+ * Basic open test which does the following:
+ * - creates file with default rw perms and writes some data to the value blob.
+ * - closes the newly created file.
+ * - opens the file with the rw permissions (non default)
+ * - tries to write the file data which should succeeds because file was opened with write flag set.
+ * - closes the opened key
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_03(const size_t call_count)
+{
+ int32_t ret = -1;
+ size_t len = 0;
+ FILE *fp = NULL;
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+ len = strlen(fsfat_fopen_test_02_data[0].value);
+ ret = fsfat_test_create(fsfat_fopen_test_02_data[0].filename, (char *) fsfat_fopen_test_02_data[0].value, len);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create file in store (ret=%d).\n", __func__, (int) ret);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+
+ /* opens with read-write permissions*/
+ fp = fopen(fsfat_fopen_test_02_data[0].filename, "w+");
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to open file (filename=\"%s\")(ret=%d)\n", __func__, fsfat_fopen_test_02_data[0].filename, (int) ret);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+
+ len = strlen(fsfat_fopen_test_02_data[0].value);
+ ret = fwrite((const void *) fsfat_fopen_test_02_data[0].value, len, 1, fp);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: call to fwrite() failed when should have succeeded (filename=\"%s\", ret=%d).\n", __func__,
+ fsfat_fopen_test_02_data[0].filename, (int) ret);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE, "%s:Error: fclose() call failed.\n",
+ __func__);
+ TEST_ASSERT_MESSAGE(fclose(fp) >= 0, fsfat_fopen_utest_msg_g);
+
+ /* clean-up */
+ ret = remove(fsfat_fopen_test_02_data[0].filename);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: unable to delete file (filename=%s, ret=%d) .\n", __func__, fsfat_fopen_test_02_data[0].filename, (int) ret);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+
+ return CaseNext;
+}
+
+
+/** @brief test to call fopen() with a filename string that exceeds the maximum length
+ * - chanFS supports the exFAT format which should support 255 char filenames
+ * - check that filenames of this length can be created
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_04(const size_t call_count)
+{
+ char filename_good[FSFAT_FILENAME_MAX_LENGTH + 1];
+ char filename_bad[FSFAT_FILENAME_MAX_LENGTH + 2];
+ int32_t ret = -1;
+ size_t len = 0;
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+
+ memset(filename_good, 0, FSFAT_FILENAME_MAX_LENGTH + 1);
+ memset(filename_bad, 0, FSFAT_FILENAME_MAX_LENGTH + 2);
+ ret = fsfat_test_filename_gen(filename_good, FSFAT_FILENAME_MAX_LENGTH);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: unable to generate filename_good.\n", __func__);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: filename_good is not the correct length (filename_good=%s, len=%d, expected=%d).\n", __func__, filename_good,
+ (int) strlen(filename_good), (int) FSFAT_FILENAME_MAX_LENGTH);
+ TEST_ASSERT_MESSAGE(strlen(filename_good) == FSFAT_FILENAME_MAX_LENGTH, fsfat_fopen_utest_msg_g);
+
+ ret = fsfat_test_filename_gen(filename_bad, FSFAT_FILENAME_MAX_LENGTH + 1);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: unable to generate filename_bad.\n", __func__);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: filename_bad is not the correct length (len=%d, expected=%d).\n", __func__, (int) strlen(filename_bad),
+ (int) FSFAT_FILENAME_MAX_LENGTH + 1);
+ TEST_ASSERT_MESSAGE(strlen(filename_bad) == FSFAT_FILENAME_MAX_LENGTH + 1, fsfat_fopen_utest_msg_g);
+
+ len = strlen(filename_good);
+ ret = fsfat_test_create(filename_good, filename_good, len);
+ /* FIXME:
+ * The current implementation can create file with a filename with 9 chars (more than the 8 restriction of FAT32 Short File Names).
+ * However, the exFAT 255 char filesnames is not supported and hence the following is commented out. Find out what is
+ * the supported max filename length and change this testcase according.
+ *
+ * FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE, "%s:Error: failed to create file (filename=%s, ret=%d).\n", __func__, filename_good, (int) ret);
+ * TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+ */
+
+ len = strlen(filename_bad);
+ ret = fsfat_test_create(filename_bad, filename_bad, len);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: created file in store for filename_bad when should have failed (filename=%s, ret=%d).\n", __func__,
+ filename_bad, (int) ret);
+ TEST_ASSERT_MESSAGE(ret < 0, fsfat_fopen_utest_msg_g);
+ return CaseNext;
+}
+
+
+/// @cond FSFAT_DOXYGEN_DISABLE
+typedef struct fsfat_fopen_kv_name_ascii_node {
+ uint32_t code;
+ uint32_t f_allowed : 1;
+} fsfat_fopen_kv_name_ascii_node;
+/// @endcond
+
+static const uint32_t fsfat_fopen_kv_name_ascii_table_code_sentinel_g = 256;
+
+/*@brief table recording ascii character codes permitted in kv names */
+static fsfat_fopen_kv_name_ascii_node fsfat_fopen_kv_name_ascii_table[] = {
+ {0, true}, /* code 0-33 allowed*/
+ {34, false}, /* '"' not allowed */
+ {35, true}, /* allowed */
+ {42, false}, /* '*' not allowed */
+ {43, true}, /* allowed */
+ {47, false}, /* '/' not allowed */
+ {48, true}, /* allowed */
+ {58, false}, /* ':' not allowed */
+ {59, true}, /* allowed */
+ {60, false}, /* '<' not allowed */
+ {61, true}, /* allowed */
+ {62, false}, /* '?', '>' not allowed */
+ {64, true}, /* allowed */
+ {92, false}, /* '\' not allowed */
+ {93, true}, /* allowed */
+ {124, false}, /* '!' not allowed */
+ {125, true}, /* allowed */
+ {127, false}, /* DEL not allowed */
+ {128, true}, /* allowed */
+ {fsfat_fopen_kv_name_ascii_table_code_sentinel_g, false}, /* sentinel */
+};
+
+
+/// @cond FSFAT_DOXYGEN_DISABLE
+enum fsfat_fopen_kv_name_pos {
+ fsfat_fopen_kv_name_pos_start = 0x0,
+ fsfat_fopen_kv_name_pos_mid,
+ fsfat_fopen_kv_name_pos_end,
+ fsfat_fopen_kv_name_pos_max
+};
+/// @endcond
+
+/** @brief test to call fopen() with filename that in includes illegal characters
+ * - the character(s) can be at the beginning of the filename
+ * - the character(s) can be at the end of the filename
+ * - the character(s) can be somewhere within the filename string
+ * - a max-length string of random characters (legal and illegal)
+ * - a max-length string of random illegal characters only
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_05(const size_t call_count)
+{
+ bool f_allowed = false;
+ const char *mnt_pt = FSFAT_FOPEN_TEST_MOUNT_PT_PATH;
+ const char *basename = "goodfile";
+ const char *extname = "txt";
+ const size_t basename_len = strlen(basename);
+ const size_t filename_len = strlen(mnt_pt) + strlen(basename) + strlen(extname) +
+ 2; /* extra 2 chars for '/' and '.' in "/sd/goodfile.txt" */
+ char filename[FSFAT_BUF_MAX_LENGTH];
+ size_t len = 0;
+ uint32_t j = 0;
+ int32_t ret = 0;
+ fsfat_fopen_kv_name_ascii_node *node = NULL;
+ uint32_t pos;
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+
+#ifdef FSFAT_DEBUG
+ /* symbol only used why debug is enabled */
+ const char *pos_str = NULL;
+#endif
+
+ /* create bad keyname strings with invalid character code at start of keyname */
+ node = fsfat_fopen_kv_name_ascii_table;
+ memset(filename, 0, FSFAT_BUF_MAX_LENGTH);
+ while (node->code != fsfat_fopen_kv_name_ascii_table_code_sentinel_g) {
+ /* loop over range */
+ for (j = node->code; j < (node + 1)->code; j++) {
+ if ((j >= 48 && j <= 57) || (j >= 65 && j <= 90) || (j >= 97 && j <= 122)) {
+ FSFAT_DBGLOG("%s: skipping alpha-numeric ascii character code %d (%c).\n", __func__, (int) j, (char) j);
+ continue;
+ }
+
+ /* set the start, mid, last character of the name to the test char code */
+ for (pos = (uint32_t) fsfat_fopen_kv_name_pos_start; pos < (uint32_t) fsfat_fopen_kv_name_pos_max; pos++) {
+ len = snprintf(filename, filename_len + 1, "%s/%s.%s", mnt_pt, basename, extname);
+ /* overwrite a char at the pos start, mid, end of the filename with an ascii char code (both illegal and legal)*/
+ switch (pos) {
+ case fsfat_fopen_kv_name_pos_start:
+ filename[5] = (char) j; /* 5 so at to write the second basename char (bad chars as first char not accepted)*/
+ break;
+ case fsfat_fopen_kv_name_pos_mid:
+ /* create bad keyname strings with invalid character code in the middle of keyname */
+ filename[5 + basename_len / 2] = (char) j;
+ break;
+ case fsfat_fopen_kv_name_pos_end:
+ /* create bad keyname strings with invalid character code at end of keyname */
+ filename[5 + basename_len - 1] = (char) j;
+ break;
+ default:
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: unexpected value of pos (pos=%d).\n", __func__, (int) pos);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+ break;
+ }
+
+#ifdef FSFAT_DEBUG
+ /* processing only required when debug trace enabled */
+ switch (pos) {
+ case fsfat_fopen_kv_name_pos_start:
+ pos_str = "start";
+ break;
+ case fsfat_fopen_kv_name_pos_mid:
+ pos_str = "middle";
+ break;
+ case fsfat_fopen_kv_name_pos_end:
+ pos_str = "end";
+ break;
+ default:
+ break;
+ }
+#endif
+ ret = fsfat_test_create(filename, (const char *) filename, len);
+
+ /* special cases */
+ switch (j) {
+ //case 0 :
+ //case 46 :
+ // switch(pos)
+ // {
+ // /* for code = 0 (null terminator). permitted at mid and end of string */
+ // /* for code = 46 ('.'). permitted at mid and end of string but not at start */
+ // case fsfat_fopen_kv_name_pos_start:
+ // f_allowed = false;
+ // break;
+ // case fsfat_fopen_kv_name_pos_mid:
+ // case fsfat_fopen_kv_name_pos_end:
+ // default:
+ // f_allowed = true;
+ // break;
+ // }
+ // break;
+ default:
+ f_allowed = node->f_allowed;
+ break;
+ }
+ if (f_allowed == true) {
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create file in store when filename contains valid characters (code=%d, ret=%d).\n", __func__,
+ (int) j, (int) ret);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+ /* revert FSFAT_LOG for more trace */
+ FSFAT_DBGLOG("Successfully created a file with valid keyname containing ascii character code %d (%c) at the %s of the keyname.\n",
+ (int) j, (int) j, pos_str);
+ FSFAT_LOG("%c", '.');
+
+ ret = fsfat_test_delete(filename);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to delete file previously created (code=%d, ret=%d).\n", __func__, (int) j, (int) ret);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+ } else {
+ /*node->f_allowed == false => not allowed to create kv name with ascii code */
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: created file in store when filename contains an invalid character (code=%d, ret=%d).\n", __func__, (int) j,
+ (int) ret);
+ TEST_ASSERT_MESSAGE(ret < 0, fsfat_fopen_utest_msg_g);
+ /* revert FSFAT_LOG for more trace */
+ FSFAT_DBGLOG("Successfully failed to create a file with an invalid keyname containing ascii character code %d at the %s of the keyname.\n",
+ (int) j, pos_str);
+ FSFAT_LOG("%c", '.');
+ }
+ }
+ }
+ node++;
+ }
+
+ FSFAT_LOG("%c", '\n');
+ return CaseNext;
+}
+
+
+static const char fsfat_fopen_ascii_illegal_buf_g[] = "\"�'*+,./:;<=>?[\\]|";
+
+/** @brief test to call fopen() with filename that in includes
+ * illegal characters
+ * - a max-length string of random illegal characters only
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_06(const size_t call_count)
+{
+ const char *mnt_pt = FSFAT_FOPEN_TEST_MOUNT_PT_PATH;
+ const char *extname = "txt";
+ const size_t filename_len = strlen(mnt_pt) + FSFAT_MAX_FILE_BASENAME + strlen(extname) +
+ 2; /* extra 2 chars for '/' and '.' in "/sd/goodfile.txt" */
+ char filename[FSFAT_BUF_MAX_LENGTH];
+ int32_t i = 0;
+ int32_t j = 0;
+ uint32_t pos = 0;
+ uint32_t len = 0;
+ int32_t ret = -1;
+ size_t buf_data_max = 0;
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+
+ memset(filename, 0, FSFAT_BUF_MAX_LENGTH);
+ /* create bad keyname strings with invalid character code at start of keyname */
+ buf_data_max = strlen(fsfat_fopen_ascii_illegal_buf_g);
+
+ /* generate a number of illegal filenames */
+ for (j = 0; i < FSFAT_MAX_FILE_BASENAME; j++) {
+ /* generate a kv name of illegal chars*/
+ len = snprintf(filename, filename_len + 1, "%s/", mnt_pt);
+ for (i = 0; i < FSFAT_MAX_FILE_BASENAME; i++) {
+ pos = rand() % (buf_data_max + 1);
+ len += snprintf(filename + len, filename_len + 1, "%c", fsfat_fopen_ascii_illegal_buf_g[pos]);
+
+ }
+ len += snprintf(filename + len, filename_len + 1, ".%s", extname);
+ ret = fsfat_test_create(filename, filename, len);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: created file when filename contains invalid characters (filename=%s, ret=%d).\n", __func__, filename,
+ (int) ret);
+ TEST_ASSERT_MESSAGE(ret < 0, fsfat_fopen_utest_msg_g);
+ }
+ return CaseNext;
+}
+
+
+/** @brief test for errno reporting on a failed fopen()call
+ *
+ * This test does the following:
+ * - tries to open a file that does not exist for reading, and checks that a NULL pointer is returned.
+ * - checks that errno is not 0 as there is an error.
+ * - checks that ferror() returns 1 indicating an error exists.
+ *
+ * Note: see NOTE_1 below.
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_07(const size_t call_count)
+{
+ FILE *f = NULL;
+ int ret = -1;
+ int errno_val = 0;
+ const char *filename = sd_badfile_path;
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+
+ errno = 0;
+ /* this is expect to fail as the file doesnt exist */
+ f = fopen(filename, "r");
+
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: opened non-existent file for reading (filename=%s, f=%p).\n", __func__, filename, f);
+ TEST_ASSERT_MESSAGE(f == NULL, fsfat_fopen_utest_msg_g);
+
+ /* check errno is set correctly */
+#if ! defined(__ARMCC_VERSION) && defined(__GNUC__)
+ /* Store errno so the current value set is not changed by new function call */
+ errno_val = errno;
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: errno has unexpected value (errno != 0 expected) (filename=%s, errno=%d).\n", __func__, filename, errno);
+ TEST_ASSERT_MESSAGE(errno_val != 0, fsfat_fopen_utest_msg_g);
+#endif /* ! defined(__ARMCC_VERSION) && defined(__GNUC__) */
+ return CaseNext;
+}
+
+
+/** @brief test for operation of clearerr() and ferror()
+ *
+ * The test does the following:
+ * - opens and then closes a file, but keeps a copy of the FILE pointer fp.
+ * - set errno to 0.
+ * - write to the close file with fwrite(fp) which should return 0 (no writes) and set the errno.
+ * - check the error condition is set with ferror().
+ * - clear the error with clearerr().
+ * - check the error condition is reset with ferror().
+ *
+ * NOTE_1: GCC/ARMCC support for setting errno
+ * - Documentation (e.g. fwrite() man page) does not explicity say fwrite() sets errno
+ * (e.g. for an fwrite() on a read-only file).
+ * - GCC libc fwrite() appears to set errno as expected.
+ * - ARMCC & IAR libc fwrite() appears not to set errno.
+ *
+ * The following ARMCC documents are silent on whether fwrite() sets errno:
+ * - "ARM C and C++ Libraries and Floating-Point Support".
+ * - "RL-ARM User Guide fwrite() section".
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_08(const size_t call_count)
+{
+ FILE *fp = NULL;
+ int ret = -1;
+ int ret_ferror = -1;
+ const char *filename = sd_testfile_path;
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+
+ errno = 0;
+ fp = fopen(filename, "w+");
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to open file (filename=%s, f=%p).\n", __func__, filename, fp);
+ TEST_ASSERT_MESSAGE(fp != NULL, fsfat_fopen_utest_msg_g);
+
+ /* close the fp but then try to read or write it */
+ ret = fclose(fp);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to close file (ret=%d, errno=%d)\n", __func__, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ /* open file */
+ errno = 0;
+ fp = fopen(filename, "r");
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to open file for reading (filename=\"%s\", ret=%d)\n", __func__, filename, (int) ret);
+ TEST_ASSERT_MESSAGE(fp != NULL, fsfat_fopen_utest_msg_g);
+
+ /* Perform fwrite() operation that will fail. */
+ errno = 0;
+ ret = fwrite("42!", 4, 1, fp);
+
+ ret_ferror = ferror(fp);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: ferror() failed to report error (filename=%s, ret_ferror=%d).\n", __func__, filename, (int) ret_ferror);
+ TEST_ASSERT_MESSAGE(ret_ferror != 0, fsfat_fopen_utest_msg_g);
+
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: fwrite successfully wrote to read-only file (filename=%s, ret=%d).\n", __func__, filename, (int) ret);
+ /* the fwrite() should fail and return 0. */
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+#if ! defined(__ARMCC_VERSION) && defined(__GNUC__)
+ /* check that errno is set. ARMCC appears not to set errno for fwrite() failure. */
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: unexpected zero value for errno (filename=%s, ret=%d, errno=%d).\n", __func__, filename, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(errno != 0, fsfat_fopen_utest_msg_g);
+
+ /* check that errno is set to the expected value (this may change differ for different libc's) */
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: errno != EBADF (filename=%s, ret=%d, errno=%d).\n", __func__, filename, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(errno == EBADF, fsfat_fopen_utest_msg_g);
+#endif /* ! defined(__ARMCC_VERSION) && defined(__GNUC__) */
+
+ /* check clearerr() return clears the error */
+ clearerr(fp);
+ ret = ferror(fp);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: ferror() did not return zero value when error has been cleared (filename=%s, ret=%d).\n", __func__, filename,
+ (int) ret);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ fclose(fp);
+ return CaseNext;
+}
+
+
+/** @brief test for operation of ftell()
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_09(const size_t call_count)
+{
+ FILE *fp = NULL;
+ int ret = -1;
+ int32_t len = 0;
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+
+ /* create a file of a certain length */
+ len = strlen(fsfat_fopen_test_02_data[0].value);
+ ret = fsfat_test_create(fsfat_fopen_test_02_data[0].filename, (char *) fsfat_fopen_test_02_data[0].value, len);
+
+ errno = 0;
+ /* Open the file for reading so the file is not truncated to 0 length. */
+ fp = fopen(fsfat_fopen_test_02_data[0].filename, "r");
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to open file (filename=%s, fp=%p, errno=%d).\n", __func__, fsfat_fopen_test_02_data[0].filename, fp,
+ errno);
+ TEST_ASSERT_MESSAGE(fp != NULL, fsfat_fopen_utest_msg_g);
+
+ errno = 0;
+ ret = fseek(fp, 0, SEEK_END);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: fseek() failed to SEEK_END (filename=%s, ret=%d, errno=%d).\n", __func__,
+ fsfat_fopen_test_02_data[0].filename, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ errno = 0;
+ ret = ftell(fp);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: ftell() failed to report correct offset value (filename=%s, ret=%d, errno=%d).\n", __func__,
+ fsfat_fopen_test_02_data[0].filename, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == len, fsfat_fopen_utest_msg_g);
+
+ errno = 0;
+ ret = fclose(fp);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to close file (ret=%d, errno=%d)\n", __func__, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ return CaseNext;
+}
+
+
+/* file data for test_10 */
+static fsfat_kv_data_t fsfat_fopen_test_10_kv_data[] = {
+ { "/sd/test_10/testfile.txt", "test_data"},
+ { NULL, NULL},
+};
+
+/** @brief test for operation of remove()
+ *
+ * Performs the following tests:
+ * 1. test remove() on a file that exists. This should succeed.
+ * 2. test remove() on a dir that exists. This should succeed.
+ * 3. test remove() on a file that doesnt exist. This should fail. check errno set.
+ * 4. test remove() on a dir that doesnt exist. This should fail. check errno set.
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_10(const size_t call_count)
+{
+ char buf[FSFAT_FOPEN_TEST_WORK_BUF_SIZE_1];
+ char *pos = NULL;
+ int32_t ret = -1;
+ size_t len = 0;
+ fsfat_kv_data_t *node = fsfat_fopen_test_10_kv_data;
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+
+ TEST_ASSERT(strlen(node->filename) < FSFAT_FOPEN_TEST_WORK_BUF_SIZE_1);
+
+ /* start from a known state i.e. directory to be created in not present */
+ fsfat_filepath_remove_all((char *) node->filename);
+
+ /* (1) */
+ errno = 0;
+ ret = fsfat_filepath_make_dirs((char *) node->filename, false);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create dir (dirname=%s, ret=%d, errno=%d)\n", __func__, node->filename, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ len = strlen(node->value);
+ ret = fsfat_test_create(node->filename, (char *) node->value, len);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create file (ret=%d).\n", __func__, (int) ret);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+
+ ret = remove(node->filename);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: delete file operation failed (filename=%s, ret=%d) .\n", __func__, node->filename, (int) ret);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ /* (3) */
+ ret = remove(node->filename);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: deleted a file that doesn't exist (filename=%s, ret=%d, errno=%d) .\n", __func__, node->filename, (int) ret,
+ errno);
+ TEST_ASSERT_MESSAGE(ret != 0, fsfat_fopen_utest_msg_g);
+
+ /* (2) */
+ memset(buf, 0, FSFAT_FOPEN_TEST_WORK_BUF_SIZE_1);
+ memcpy(buf, node->filename, strlen(node->filename));
+ pos = strrchr(buf, '/');
+ *pos = '\0';
+ ret = remove(buf);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: delete directory operation failed (directory name=%s, ret=%d, errno=%d).\n", __func__, buf, (int) ret,
+ errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ /* (4) */
+ ret = remove(buf);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: deleted a directory that doesn't exist (directory name=%s, ret=%d, errno=%d).\n", __func__, buf, (int) ret,
+ errno);
+ TEST_ASSERT_MESSAGE(ret != 0, fsfat_fopen_utest_msg_g);
+
+ return CaseNext;
+}
+
+
+/* file data for test_11 */
+static fsfat_kv_data_t fsfat_fopen_test_11_kv_data[] = {
+ { "/sd/test_11/step0.txt", "test_data"},
+ { "/sd/test_11/step1.txt", "test_data"},
+ { "/sd/test_11/subdir/step3.txt", "test_data"},
+ { NULL, NULL},
+};
+
+/** @brief test for operation of rename()
+ *
+ * This test does the following:
+ * 1) test rename() on a file that exists to a new filename within the same directory.
+ * 2) test rename() on a file that exists to a new filename within a different directory.
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_11(const size_t call_count)
+{
+ int32_t ret = -1;
+ size_t len = 0;
+ fsfat_kv_data_t *node = fsfat_fopen_test_11_kv_data;
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+
+ TEST_ASSERT(strlen(node->filename) < FSFAT_FOPEN_TEST_WORK_BUF_SIZE_1);
+
+ /* start from a known state i.e. directory to be created in not present, files not present */
+ while (node->filename != NULL) {
+ fsfat_filepath_remove_all((char *) node->filename);
+ node++;
+ }
+
+ /* create file and directories ready for rename() tests */
+ errno = 0;
+ node = fsfat_fopen_test_11_kv_data;
+ ret = fsfat_filepath_make_dirs((char *) node->filename, false);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create dir (dirname=%s, ret=%d, errno=%d)\n", __func__, node->filename, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ len = strlen(node->value);
+ ret = fsfat_test_create(node->filename, (char *) node->value, len);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create file (ret=%d).\n", __func__, (int) ret);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+
+ errno = 0;
+ node = &fsfat_fopen_test_11_kv_data[2];
+ ret = fsfat_filepath_make_dirs((char *) node->filename, false);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create dir (dirname=%s, ret=%d, errno=%d)\n", __func__, node->filename, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ /* (1) */
+ ret = rename(fsfat_fopen_test_11_kv_data[0].filename, fsfat_fopen_test_11_kv_data[1].filename);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: unable to rename file from (%s) to (%s) (ret=%d, errno=%d).\n", __func__,
+ fsfat_fopen_test_11_kv_data[0].filename, fsfat_fopen_test_11_kv_data[1].filename, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ /* (2) */
+ ret = rename(fsfat_fopen_test_11_kv_data[1].filename, fsfat_fopen_test_11_kv_data[2].filename);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: unable to rename file from (%s) to (%s) (ret=%d, errno=%d).\n", __func__,
+ fsfat_fopen_test_11_kv_data[1].filename, fsfat_fopen_test_11_kv_data[2].filename, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ return CaseNext;
+}
+
+
+/* file data for test_12 */
+static fsfat_kv_data_t fsfat_fopen_test_12_kv_data[] = {
+ { "/sd/test_12/subdir/testfil1.txt", "testfil1.txt"},
+ { "/sd/test_12/testfil2.txt", "testfil2.txt"},
+ { "/sd/test_12/testfil3.txt", "testfil3.txt"},
+ { "/sd/test_12/testfil4.txt", "testfil4.txt"},
+ { "/sd/test_12/testfil5.txt", "testfil5.txt"},
+ { NULL, NULL},
+};
+
+/** @brief test for operation of readdir().
+ *
+ * Note, rewinddir(), telldir() and seekdir() dont appear to work reliably.
+ * opendir() not available on ARM/IAR toolchains.
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_12(const size_t call_count)
+{
+ char buf[FSFAT_FOPEN_TEST_WORK_BUF_SIZE_1];
+ char *pos = NULL;
+ int32_t count = 0;
+ int32_t ret = -1;
+ size_t len = 0;
+ DIR *dir;
+ struct dirent *dp;
+ fsfat_kv_data_t *node = fsfat_fopen_test_12_kv_data;
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+
+#if ! defined(__ARMCC_VERSION) && defined(__GNUC__)
+
+ /* start from a known state i.e. directory to be created in not present */
+ while (node->filename != NULL) {
+ fsfat_filepath_remove_all((char *) node->filename);
+ node++;
+ }
+
+ /* create a file */
+ node = fsfat_fopen_test_12_kv_data;
+ errno = 0;
+ ret = fsfat_filepath_make_dirs((char *) node->filename, false);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create dir (dirname=%s, ret=%d, errno=%d)\n", __func__, node->filename, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ node = fsfat_fopen_test_12_kv_data;
+ while (node->filename != NULL) {
+ len = strlen(node->value);
+ ret = fsfat_test_create(node->filename, (char *) node->value, len);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create file (ret=%d).\n", __func__, (int) ret);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+ node++;
+ }
+
+ node = fsfat_fopen_test_12_kv_data;
+ memset(buf, 0, FSFAT_FOPEN_TEST_WORK_BUF_SIZE_1);
+ memcpy(buf, node->filename, strlen(node->filename));
+ pos = strrchr(buf, '/');
+ *pos = '\0';
+ dir = opendir(buf);
+
+ while ((dp = readdir(dir)) != NULL) {
+ FSFAT_DBGLOG("%s: filename: \"%s\"\n", __func__, dp->d_name);
+ TEST_ASSERT_MESSAGE(dp != 0, "Error: readdir() failed\n");
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: unexpected object name (name=%s, expected=%s).\n", __func__, dp->d_name,
+ fsfat_fopen_test_12_kv_data[count].value);
+ TEST_ASSERT_MESSAGE(strncmp(dp->d_name, fsfat_fopen_test_12_kv_data[count].value,
+ strlen(fsfat_fopen_test_12_kv_data[count].value)) == 0, fsfat_fopen_utest_msg_g);
+ count++;
+ }
+ closedir(dir);
+
+ /* cleanup */
+ node = fsfat_fopen_test_12_kv_data;
+ while (node->filename != NULL) {
+ fsfat_filepath_remove_all((char *) node->filename);
+ node++;
+ }
+#endif /* ! defined(__ARMCC_VERSION) && defined(__GNUC__) */
+ return CaseNext;
+}
+
+
+/* file data for test_13 */
+static fsfat_kv_data_t fsfat_fopen_test_13_kv_data[] = {
+ /* a file is included in the filepath even though its not created by the test,
+ * as the fsfat_filepath_make_dirs() works with it present. */
+ { "/sd/test_13/dummy.txt", "testdir"},
+ { NULL, NULL},
+};
+/** @brief test for operation of mkdir()/remove()
+ *
+ * This test checks that:
+ * - The mkdir() function successfully creates a directory that is not already present.
+ * - The mkdir() function returns EEXIST when trying to create a directory thats already present.
+ * - The remove() function successfully removes a directory that is present.
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_13(const size_t call_count)
+{
+ int32_t ret = 0;
+
+ FSFAT_DBGLOG("%s:entered\n", __func__);
+ (void) call_count;
+
+ /* start from a known state i.e. directory to be created in not present */
+ fsfat_filepath_remove_all((char *) fsfat_fopen_test_13_kv_data[0].filename);
+
+ errno = 0;
+ ret = fsfat_filepath_make_dirs((char *) fsfat_fopen_test_13_kv_data[0].filename, false);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create dir (dirname=%s, ret=%d, errno=%d)\n", __func__, fsfat_fopen_test_13_kv_data[0].filename,
+ (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ /* check that get a suitable error when try to create it again.*/
+ errno = 0;
+ ret = fsfat_filepath_make_dirs((char *) fsfat_fopen_test_13_kv_data[0].filename, false);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: permitted to create directory when already exists (dirname=%s, ret=%d, errno=%d)\n", __func__,
+ fsfat_fopen_test_13_kv_data[0].filename, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret != 0, fsfat_fopen_utest_msg_g);
+
+ /* check errno is as expected */
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: errno != EEXIST (dirname=%s, ret=%d, errno=%d)\n", __func__, fsfat_fopen_test_13_kv_data[0].filename,
+ (int) ret, errno);
+ TEST_ASSERT_MESSAGE(errno == EEXIST, fsfat_fopen_utest_msg_g);
+
+ ret = fsfat_filepath_remove_all((char *) fsfat_fopen_test_13_kv_data[0].filename);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to remove directory (dirname=%s, ret=%d, errno=%d)\n", __func__,
+ fsfat_fopen_test_13_kv_data[0].filename, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ return CaseNext;
+}
+
+/* file data for test_14 */
+static fsfat_kv_data_t fsfat_fopen_test_14_kv_data[] = {
+ /* a file is included in the filepath even though its not created by the test,
+ * as the fsfat_filepath_make_dirs() works with it present. */
+ { "/sd/test_14/testfile.txt", "testdata"},
+ { NULL, NULL},
+};
+
+/** @brief test for operation of stat()
+ *
+ * stat() is currently no supported by ARMCC and IAR toolchains libc.
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_14(const size_t call_count)
+{
+#if ! defined(__ARMCC_VERSION) && defined(__GNUC__)
+
+ char buf[FSFAT_FOPEN_TEST_WORK_BUF_SIZE_1];
+ char *pos = NULL;
+ int32_t ret = -1;
+ size_t len = 0;
+ struct stat file_stat;
+ fsfat_kv_data_t *node = fsfat_fopen_test_14_kv_data;
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+
+ TEST_ASSERT(strlen(node->filename) < FSFAT_FOPEN_TEST_WORK_BUF_SIZE_1);
+
+ /* start from a known state i.e. directory to be created in not present */
+ fsfat_filepath_remove_all((char *) node->filename);
+
+ /* Create file in a directory. */
+ errno = 0;
+ ret = fsfat_filepath_make_dirs((char *) node->filename, false);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create dir (dirname=%s, ret=%d, errno=%d)\n", __func__, node->filename, (int) ret, errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ len = strlen(node->value);
+ ret = fsfat_test_create(node->filename, (char *) node->value, len);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create file (ret=%d).\n", __func__, (int) ret);
+ TEST_ASSERT_MESSAGE(ret >= 0, fsfat_fopen_utest_msg_g);
+
+ /* Test stat() on the file returns the correct attribute set */
+ memset(&file_stat, 0, sizeof(file_stat));
+ ret = stat(node->filename, &file_stat);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: stat() operation on file failed (filename=%s, ret=%d, errno=%d).\n", __func__, node->filename, (int) ret,
+ errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: expected st_mode S_IFREG flag not set (filename=%s).\n", __func__, node->filename);
+ TEST_ASSERT_MESSAGE((file_stat.st_mode & S_IFREG) == S_IFREG, fsfat_fopen_utest_msg_g);
+
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: unexpected st_mode S_IFDIR flag set (filename=%s).\n", __func__, node->filename);
+ TEST_ASSERT_MESSAGE((file_stat.st_mode & S_IFDIR) != S_IFDIR, fsfat_fopen_utest_msg_g);
+
+ /* Test stat() on the directory returns the correct attribute set */
+ memset(&file_stat, 0, sizeof(file_stat));
+ memset(buf, 0, FSFAT_FOPEN_TEST_WORK_BUF_SIZE_1);
+ memcpy(buf, node->filename, strlen(node->filename));
+ pos = strrchr(buf, '/');
+ *pos = '\0';
+ ret = stat(buf, &file_stat);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: stat() operation on directory failed (directory name=%s, ret=%d, errno=%d).\n", __func__, buf, (int) ret,
+ errno);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: unexpected st_mode S_IFREG flag set (directory name=%s).\n", __func__, buf);
+ TEST_ASSERT_MESSAGE((file_stat.st_mode & S_IFREG) != S_IFREG, fsfat_fopen_utest_msg_g);
+
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: expected st_mode S_IFDIR flag not set (directory name=%s).\n", __func__, buf);
+ TEST_ASSERT_MESSAGE((file_stat.st_mode & S_IFDIR) == S_IFDIR, fsfat_fopen_utest_msg_g);
+
+ /* clean up after successful test */
+ fsfat_filepath_remove_all((char *) node->filename);
+
+#endif /* ! defined(__ARMCC_VERSION) && defined(__GNUC__) */
+ return CaseNext;
+}
+
+/** @brief test for operation of SDFileSystem::format()
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_15(const size_t call_count)
+{
+
+ FSFAT_FENTRYLOG("%s:entered\n", __func__);
+ (void) call_count;
+ int32_t ret = -1;
+
+ /* the allocation_unit of 0 means chanFS will use the default for the card (varies according to capacity). */
+ fs.unmount();
+ ret = fs.format(&sd);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to format sdcard (ret=%d)\n", __func__, (int) ret);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+ fs.mount(&sd);
+ return CaseNext;
+}
+
+
+/* @brief test utility function to create a file of a given size.
+ *
+ * A reference data table is used of so that the data file can be later be
+ * checked with fsfat_test_check_data_file().
+ *
+ * @param filename name of the file including path
+ * @param data data to store in file
+ * @param len number of bytes of data present in the data buffer.
+ */
+int32_t fsfat_test_create_data_file(const char *filename, size_t len)
+{
+ int32_t ret = -1;
+ FILE *fp = NULL;
+ size_t write_len = 0;
+ size_t written_len = 0;
+ int32_t exp = 0;
+ const int32_t exp_max = 8; /* so as not to exceed FSFAT_TEST_BYTE_DATA_TABLE_SIZE/2 */
+
+ FSFAT_FENTRYLOG("%s:entered (filename=%s, len=%d).\n", __func__, filename, (int) len);
+ TEST_ASSERT(len % FSFAT_TEST_BYTE_DATA_TABLE_SIZE == 0);
+ fp = fopen(filename, "a");
+ if (fp == NULL) {
+ return ret;
+ }
+
+ while (written_len < len) {
+ /* write fsfat_test_byte_data_table or part thereof, in 9 writes of sizes
+ * 1, 2, 4, 8, 16, 32, 64, 128, 1, totalling 256 bytes len permitting. */
+ for (exp = 0; (exp <= exp_max) && (written_len < len); exp++) {
+ write_len = 0x1 << (exp % exp_max);
+ write_len = len - written_len > write_len ? write_len : len - written_len;
+ ret = fwrite((const void *) &fsfat_test_byte_data_table[written_len % FSFAT_TEST_BYTE_DATA_TABLE_SIZE], write_len, 1,
+ fp);
+ written_len += write_len;
+ if (ret != 1) {
+ FSFAT_DBGLOG("%s:Error: fwrite() failed (ret=%d)\n", __func__, (int) ret);
+ ret = -1;
+ goto out0;
+ }
+ }
+ }
+ if (written_len == len) {
+ ret = 0;
+ } else {
+ ret = -1;
+ }
+out0:
+ fclose(fp);
+ return ret;
+}
+
+
+/* @brief test utility function to check the data in the specified file is correct.
+ *
+ * The data read from the file is check that it agrees with the data written by
+ * fsfat_test_create_data_file().
+ *
+ * @param filename name of the file including path
+ * @param data data to store in file
+ * @param len number of bytes of data present in the data buffer.
+ */
+int32_t fsfat_test_check_data_file(const char *filename, size_t len)
+{
+ int32_t ret = -1;
+ FILE *fp = NULL;
+ size_t read_len = 0;
+ uint8_t buf[FSFAT_TEST_BYTE_DATA_TABLE_SIZE];
+
+ FSFAT_FENTRYLOG("%s:entered (filename=%s, len=%d).\n", __func__, filename, (int) len);
+ TEST_ASSERT(len % FSFAT_TEST_BYTE_DATA_TABLE_SIZE == 0);
+ fp = fopen(filename, "r");
+ if (fp == NULL) {
+ return ret;
+ }
+
+ while (read_len < len) {
+ ret = fread((void *) buf, FSFAT_TEST_BYTE_DATA_TABLE_SIZE, 1, fp);
+ read_len += FSFAT_TEST_BYTE_DATA_TABLE_SIZE;
+ if (ret == 0) {
+ /* end of read*/
+ FSFAT_DBGLOG("%s:unable to read data\n", __func__);
+ break;
+ }
+ if (memcmp(buf, fsfat_test_byte_data_table, FSFAT_TEST_BYTE_DATA_TABLE_SIZE) != 0) {
+ FSFAT_DBGLOG("%s:Error: read data not as expected (0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x, 0x%2x\n",
+ __func__,
+ buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9], buf[10], buf[11], buf[12], buf[13],
+ buf[14], buf[15]);
+ ret = -1;
+ goto out0;
+ }
+ }
+ if (read_len == len) {
+ ret = 0;
+ }
+out0:
+ fclose(fp);
+ return ret;
+}
+
+/* file data for test_16 */
+static fsfat_kv_data_t fsfat_fopen_test_16_kv_data[] = {
+ { "/sd/tst16_0/testfil0.txt", "dummy_data"},
+ { "/sd/tst16_1/subdir0/testfil0.txt", "dummy_data"},
+ { "/sd/tst16_2/subdir0/subdir1/testfil0.txt", "dummy_data"},
+ { "/sd/tst16_3/subdir0/subdir1/subdir2/subdir3/testfil0.txt", "dummy_data"},
+ { "/sd/tst16_4/subdir0/subdir1/subdir2/subdir3/subdir4/testfil0.txt", "dummy_data"},
+ { "/sd/tst16_5/subdir0/subdir1/subdir2/subdir3/subdir4/subdir5/testfil0.txt", "dummy_data"},
+ { "/sd/tst16_6/subdir0/subdir1/subdir2/subdir3/subdir4/subdir5/subdir6/testfil0.txt", "dummy_data"},
+ { "/sd/tst16_7/subdir0/subdir1/subdir2/subdir3/subdir4/subdir5/subdir6/subdir7/testfil0.txt", "dummy_data"},
+ { "/sd/tst16_8/subdir0/subdir1/subdir2/subdir3/subdir4/subdir5/subdir6/subdir7/subdir8/testfil0.txt", "dummy_data"},
+ { "/sd/tst16_9/subdir0/subdir1/subdir2/subdir3/subdir4/subdir5/subdir6/subdir7/subdir8/subdir9/testfil0.txt", "dummy_data"},
+ { NULL, NULL},
+};
+
+
+/** @brief stress test to write data to fs
+ *
+ * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors.
+ */
+control_t fsfat_fopen_test_16(const size_t call_count)
+{
+ int32_t ret = 0;
+ fsfat_kv_data_t *node = fsfat_fopen_test_16_kv_data;
+ const int32_t num_blocks = 100; /* each file ~25kB */
+
+ FSFAT_DBGLOG("%s:entered\n", __func__);
+ (void) call_count;
+
+ /* remove file and directory from a previous failed test run, if present */
+ while (node->filename != NULL) {
+ fsfat_filepath_remove_all((char *) node->filename);
+ node++;
+ }
+
+ /* create dirs */
+ node = fsfat_fopen_test_16_kv_data;
+ while (node->filename != NULL) {
+ ret = fsfat_filepath_make_dirs((char *) node->filename, true);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create dirs for filename (filename=\"%s\")(ret=%d)\n", __func__, node->filename, (int) ret);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+ node++;
+ }
+
+ /* create the data files */
+ node = fsfat_fopen_test_16_kv_data;
+ while (node->filename != NULL) {
+ ret = fsfat_test_create_data_file(node->filename, num_blocks * FSFAT_TEST_BYTE_DATA_TABLE_SIZE);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to create data file (filename=\"%s\")(ret=%d)\n", __func__, node->filename, (int) ret);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+ node++;
+ }
+
+ /* read the data back and check its as expected */
+ node = fsfat_fopen_test_16_kv_data;
+ while (node->filename != NULL) {
+ ret = fsfat_test_check_data_file(node->filename, num_blocks * FSFAT_TEST_BYTE_DATA_TABLE_SIZE);
+ FSFAT_TEST_UTEST_MESSAGE(fsfat_fopen_utest_msg_g, FSFAT_UTEST_MSG_BUF_SIZE,
+ "%s:Error: failed to check data file (filename=\"%s\")(ret=%d)\n", __func__, node->filename, (int) ret);
+ TEST_ASSERT_MESSAGE(ret == 0, fsfat_fopen_utest_msg_g);
+ node++;
+ }
+
+ /* clean up */
+ node = fsfat_fopen_test_16_kv_data;
+ while (node->filename != NULL) {
+ fsfat_filepath_remove_all((char *) node->filename);
+ node++;
+ }
+ return CaseNext;
+}
+
+
+#else
+
+#define FSFAT_FOPEN_TEST_00 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_01 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_02 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_03 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_04 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_05 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_06 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_07 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_08 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_09 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_10 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_11 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_12 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_13 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_14 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_15 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_16 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_17 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_18 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_19 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_20 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_21 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_22 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_23 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_24 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_25 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_26 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_27 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_28 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_29 fsfat_fopen_test_dummy
+#define FSFAT_FOPEN_TEST_30 fsfat_fopen_test_dummy
+
+/** @brief fsfat_fopen_test_dummy Dummy test case for testing when platform doesnt have an SDCard installed.
+ *
+ * @return success always
+ */
+static control_t fsfat_fopen_test_dummy()
+{
+ printf("Null test\n");
+ return CaseNext;
+}
+
+#endif
+
+
+/// @cond FSFAT_DOXYGEN_DISABLE
+utest::v1::status_t greentea_setup(const size_t number_of_cases)
+{
+ GREENTEA_SETUP(FSFAT_FOPEN_GREENTEA_TIMEOUT_S, "default_auto");
+ return greentea_test_setup_handler(number_of_cases);
+}
+
+Case cases[] = {
+ /* 1 2 3 4 5 6 7 */
+ /* 1234567890123456789012345678901234567890123456789012345678901234567890 */
+ Case("FSFAT_FOPEN_TEST_00: format sd card to FAT FS.", FSFAT_FOPEN_TEST_00),
+ Case("FSFAT_FOPEN_TEST_01: fopen()/fwrite()/fclose() directories/file in multi-dir filepath.", FSFAT_FOPEN_TEST_01),
+ Case("FSFAT_FOPEN_TEST_02: fopen(r) pre-existing file try to write it.", FSFAT_FOPEN_TEST_02),
+ Case("FSFAT_FOPEN_TEST_03: fopen(w+) pre-existing file try to write it.", FSFAT_FOPEN_TEST_03),
+ Case("FSFAT_FOPEN_TEST_04: fopen() with a filename exceeding the maximum length.", FSFAT_FOPEN_TEST_04),
+#ifdef FOPEN_EXTENDED_TESTING
+ Case("FSFAT_FOPEN_TEST_05: fopen() with bad filenames (extended).", FSFAT_FOPEN_TEST_05),
+#endif
+ Case("FSFAT_FOPEN_TEST_06: fopen() with bad filenames (minimal).", FSFAT_FOPEN_TEST_06),
+ Case("FSFAT_FOPEN_TEST_07: fopen()/errno handling.", FSFAT_FOPEN_TEST_07),
+ Case("FSFAT_FOPEN_TEST_08: ferror()/clearerr()/errno handling.", FSFAT_FOPEN_TEST_08),
+ Case("FSFAT_FOPEN_TEST_09: ftell() handling.", FSFAT_FOPEN_TEST_09),
+ Case("FSFAT_FOPEN_TEST_10: remove() test.", FSFAT_FOPEN_TEST_10),
+ Case("FSFAT_FOPEN_TEST_11: rename().", FSFAT_FOPEN_TEST_11),
+ Case("FSFAT_FOPEN_TEST_12: opendir(), readdir(), closedir() test.", FSFAT_FOPEN_TEST_12),
+ Case("FSFAT_FOPEN_TEST_13: mkdir() test.", FSFAT_FOPEN_TEST_13),
+ Case("FSFAT_FOPEN_TEST_14: stat() test.", FSFAT_FOPEN_TEST_14),
+ Case("FSFAT_FOPEN_TEST_15: format() test.", FSFAT_FOPEN_TEST_15),
+ Case("FSFAT_FOPEN_TEST_16: write/check n x 25kB data files.", FSFAT_FOPEN_TEST_16),
+};
+
+
+/* Declare your test specification with a custom setup handler */
+Specification specification(greentea_setup, cases);
+
+int main()
+{
+ return !Harness::run(specification);
+}
+/// @endcond
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json Mon Mar 18 16:54:40 2019 +0000
@@ -0,0 +1,259 @@
+{
+ "name": "sd",
+ "config": {
+ "SDHI_CH": "SDHI_CH",
+ "SPI_CS": "SPI_CS",
+ "SPI_MOSI": "SPI_MOSI",
+ "SPI_MISO": "SPI_MISO",
+ "SPI_CLK": "SPI_SCK",
+ "FSFAT_SDCARD_INSTALLED": 1,
+ "CMD_TIMEOUT": 10000,
+ "CMD0_IDLE_STATE_RETRIES": 5,
+ "INIT_FREQUENCY": 100000,
+ "CRC_ENABLED": 1,
+ "TEST_BUFFER": 8192,
+ "SDBlockDevice_type": {
+ "help": "default: (SPI) or HWdedicated (SDHI)",
+ "macro_name": "MBED_TEST_BLOCKDEVICE",
+ "value": "SDBlockDevice"
+ },
+ "SDBlockDevice_class": {
+ "help": "how to be inited the specified bd",
+ "macro_name": "MBED_TEST_BLOCKDEVICE_DECL",
+ "value": "SDBlockDevice bd(MBED_CONF_SD_SPI_MOSI, MBED_CONF_SD_SPI_MISO, MBED_CONF_SD_SPI_CLK, MBED_CONF_SD_SPI_CS)"
+ }
+ },
+ "target_overrides": {
+ "DISCO_F051R8": {
+ "SPI_MOSI": "SPI_MOSI",
+ "SPI_MISO": "SPI_MISO",
+ "SPI_CLK": "SPI_SCK",
+ "SPI_CS": "SPI_CS"
+ },
+ "DISCO_L475VG_IOT01A": {
+ "SPI_MOSI": "SPI_MOSI",
+ "SPI_MISO": "SPI_MISO",
+ "SPI_CLK": "SPI_SCK",
+ "SPI_CS": "SPI_CS"
+ },
+ "DISCO_L476VG": {
+ "SPI_MOSI": "PE_15",
+ "SPI_MISO": "PE_14",
+ "SPI_CLK": "PE_13",
+ "SPI_CS": "PE_12"
+ },
+ "NUCLEO_F070RB": {
+ "TEST_BUFFER": 4096
+ },
+ "NUCLEO_F072RB": {
+ "TEST_BUFFER": 4096
+ },
+ "NUCLEO_F103RB": {
+ "TEST_BUFFER": 4096
+ },
+ "NUCLEO_L073RZ": {
+ "TEST_BUFFER": 4096
+ },
+ "DISCO_L072CZ_LRWAN1": {
+ "TEST_BUFFER": 4096
+ },
+ "NUCLEO_F091RC": {
+ "TEST_BUFFER": 4096
+ },
+ "NUCLEO_F410RB": {
+ "TEST_BUFFER": 4096
+ },
+ "K20D50M": {
+ "SPI_MOSI": "PTD2",
+ "SPI_MISO": "PTD3",
+ "SPI_CLK": "PTD1",
+ "SPI_CS": "PTC2"
+ },
+ "KL22F": {
+ "SPI_MOSI": "PTD6",
+ "SPI_MISO": "PTD7",
+ "SPI_CLK": "PTD5",
+ "SPI_CS": "PTD4"
+ },
+ "KL25Z": {
+ "SPI_MOSI": "PTD2",
+ "SPI_MISO": "PTD3",
+ "SPI_CLK": "PTD1",
+ "SPI_CS": "PTD0"
+ },
+ "KL43Z": {
+ "SPI_MOSI": "PTD6",
+ "SPI_MISO": "PTD7",
+ "SPI_CLK": "PTD5",
+ "SPI_CS": "PTD4"
+ },
+ "KL46Z": {
+ "SPI_MOSI": "PTD6",
+ "SPI_MISO": "PTD7",
+ "SPI_CLK": "PTD5",
+ "SPI_CS": "PTD4"
+ },
+ "K66F": {
+ "SPI_MOSI": "PTE3",
+ "SPI_MISO": "PTE1",
+ "SPI_CLK": "PTE2",
+ "SPI_CS": "PTE4"
+ },
+ "LPC11U37H_401": {
+ "SPI_MOSI": "SDMOSI",
+ "SPI_MISO": "SDMISO",
+ "SPI_CLK": "SDSCLK",
+ "SPI_CS": "SDSSEL"
+ },
+ "LPC2368": {
+ "SPI_MOSI": "p11",
+ "SPI_MISO": "p12",
+ "SPI_CLK": "p13",
+ "SPI_CS": "p14"
+ },
+ "NUCLEO_F411RE": {
+ "SPI_MOSI": "PC_3",
+ "SPI_MISO": "PC_2",
+ "SPI_CLK": "PC_7",
+ "SPI_CS": "PB_9"
+ },
+ "NUCLEO_F429ZI": {
+ "SPI_MOSI": "PC_12",
+ "SPI_MISO": "PC_11",
+ "SPI_CLK": "PC_10",
+ "SPI_CS": "PA_15"
+ },
+ "DISCO_F429ZI": {
+ "SPI_MOSI": "PC_12",
+ "SPI_MISO": "PC_11",
+ "SPI_CLK": "PC_10",
+ "SPI_CS": "PA_15"
+ },
+ "NUCLEO_F746ZG": {
+ "SPI_MOSI": "PC_12",
+ "SPI_MISO": "PC_11",
+ "SPI_CLK": "PC_10",
+ "SPI_CS": "PA_15"
+ },
+ "NUCLEO_F767ZI": {
+ "SPI_MOSI": "PC_12",
+ "SPI_MISO": "PC_11",
+ "SPI_CLK": "PC_10",
+ "SPI_CS": "PA_15"
+ },
+ "NUCLEO_L031K6": {
+ "SPI_MOSI": "SPI_MOSI",
+ "SPI_MISO": "SPI_MISO",
+ "SPI_CLK": "SPI_SCK",
+ "SPI_CS": "SPI_CS"
+ },
+ "NUCLEO_L476RG": {
+ "SPI_MOSI": "SPI_MOSI",
+ "SPI_MISO": "SPI_MISO",
+ "SPI_CLK": "SPI_SCK",
+ "SPI_CS": "SPI_CS"
+ },
+ "NUMAKER_PFM_M453": {
+ "SPI_MOSI": "PD_13",
+ "SPI_MISO": "PD_14",
+ "SPI_CLK": "PD_15",
+ "SPI_CS": "PD_12"
+ },
+ "NUMAKER_PFM_M487": {
+ "SPI_MOSI": "D11",
+ "SPI_MISO": "D12",
+ "SPI_CLK": "D13",
+ "SPI_CS": "D10"
+ },
+ "NUMAKER_PFM_NUC472": {
+ "SPI_MOSI": "PF_0",
+ "SPI_MISO": "PD_15",
+ "SPI_CLK": "PD_14",
+ "SPI_CS": "PD_13"
+ },
+ "nRF51822": {
+ "SPI_MOSI": "p12",
+ "SPI_MISO": "p13",
+ "SPI_CLK": "p15",
+ "SPI_CS": "p14"
+ },
+ "UBLOX_C030": {
+ "SPI_MOSI": "D11",
+ "SPI_MISO": "D12",
+ "SPI_CLK": "D13",
+ "SPI_CS": "D10"
+ },
+ "UBLOX_EVK_ODIN_W2": {
+ "SPI_CS": "D9",
+ "SPI_MOSI": "D11",
+ "SPI_MISO": "D12",
+ "SPI_CLK": "D13"
+ },
+ "MTB_UBLOX_ODIN_W2": {
+ "SPI_CS": "PG_4",
+ "SPI_MOSI": "PE_14",
+ "SPI_MISO": "PE_13",
+ "SPI_CLK": "PE_12"
+ },
+ "RZ_A1H": {
+ "SPI_MOSI": "P8_5",
+ "SPI_MISO": "P8_6",
+ "SPI_CLK": "P8_3",
+ "SPI_CS": "P8_4"
+ },
+ "GR_LYCHEE": {
+ "SPI_MOSI": "P5_6",
+ "SPI_MISO": "P5_7",
+ "SPI_CLK": "P5_4",
+ "SPI_CS": "P5_5"
+ },
+ "VK_RZ_A1H": {
+ "SDHI_CH": 0,
+ "SDBlockDevice_type": "SDHIBlockDevice",
+ "SDBlockDevice_class": "SDHIBlockDevice bd(MBED_CONF_SD_SDHI_CH)"
+ },
+ "VK_RZ_A1LU": {
+ "SDHI_CH": 1,
+ "SDBlockDevice_type": "SDHIBlockDevice",
+ "SDBlockDevice_class": "SDHIBlockDevice bd(MBED_CONF_SD_SDHI_CH)"
+ },
+ "HEXIWEAR": {
+ "SPI_MOSI": "PTE3",
+ "SPI_MISO": "PTE1",
+ "SPI_CLK": "PTE2",
+ "SPI_CS": "PTE4"
+ },
+ "MTB_MTS_DRAGONFLY": {
+ "SPI_MOSI": "SPI2_MOSI",
+ "SPI_MISO": "SPI2_MISO",
+ "SPI_CLK": "SPI2_SCK",
+ "SPI_CS": "SPI_CS2"
+ },
+ "TB_SENSE_12": {
+ "SPI_MOSI": "PC6",
+ "SPI_MISO": "PC7",
+ "SPI_CLK": "PC8",
+ "SPI_CS": "PC9"
+ },
+ "LPC1768": {
+ "SPI_MOSI": "p5",
+ "SPI_MISO": "p6",
+ "SPI_CLK": "p7",
+ "SPI_CS": "p8"
+ },
+ "REALTEK_RTL8195AM": {
+ "SPI_MOSI": "D11",
+ "SPI_MISO": "D12",
+ "SPI_CLK": "D13",
+ "SPI_CS": "D10"
+ },
+ "NUCLEO_F207ZG": {
+ "SPI_MOSI": "PC_12",
+ "SPI_MISO": "PC_11",
+ "SPI_CLK": "PC_10",
+ "SPI_CS": "PA_15"
+ }
+
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/features/storage/kvstore/conf/kv_config.cpp Mon Mar 18 16:54:40 2019 +0000
@@ -0,0 +1,1119 @@
+/*
+ * Copyright (c) 2018 ARM Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "kv_config.h"
+#include "KVStore.h"
+#include "KVMap.h"
+#include "BlockDevice.h"
+#include "FileSystem.h"
+#include "FileSystemStore.h"
+#include "SlicingBlockDevice.h"
+#include "FATFileSystem.h"
+#include "LittleFileSystem.h"
+#include "TDBStore.h"
+#include "mbed_error.h"
+#include "FlashIAP.h"
+#include "FlashSimBlockDevice.h"
+#include "mbed_trace.h"
+#include "SecureStore.h"
+#define TRACE_GROUP "KVCFG"
+
+#if COMPONENT_FLASHIAP
+#include "FlashIAPBlockDevice.h"
+#endif
+
+#if COMPONENT_QSPIF
+#include "QSPIFBlockDevice.h"
+#endif
+
+#if COMPONENT_SPIF
+#include "SPIFBlockDevice.h"
+#endif
+
+#if COMPONENT_DATAFLASH
+#include "DataFlashBlockDevice.h"
+#endif
+
+#if COMPONENT_SD
+ #if (defined(TARGET_VK_RZ_A1H) || defined(TARGET_VK_RZ_A1LU))
+ #include "SDHIBlockDevice.h"
+ #else
+ #include "SDBlockDevice.h"
+ #endif
+#endif
+
+/**
+ * @brief This function initializes internal memory secure storage
+ * This includes a TDBStore instance with a FlashIAPBlockdevice
+ * as the supported storage.
+ * The following is a list of configuration parameter
+ * MBED_CONF_STORAGE_TDB_INTERNAL_SIZE - The size of the underlying FlashIAPBlockdevice
+ * MBED_CONF_STORAGE_TDB_INTERNAL_BASE_ADDRESS - The start address of the underlying FlashIAPBlockdevice
+ * @returns 0 on success or negative value on failure.
+ */
+int _storage_config_TDB_INTERNAL();
+
+/**
+ * @brief This function initialize external memory secure storage
+ * This includes a SecureStore class with TDBStore over FlashIAPBlockdevice
+ * and an external TDBStore over a default blockdevice unless configured differently.
+ * The following is a list of configuration parameter:
+ * MBED_CONF_STORAGE_TDB_EXTERNAL_RBP_INTERNAL_SIZE - Size of the internal FlashIAPBlockDevice and by
+ * default is set to from start address to the end of the flash.
+ * If start address is 0 the start address will be set to end of
+ * flash - rbp_internal_size.
+ * MBED_CONF_STORAGE_TDB_EXTERNAL_INTERNAL_BASE_ADDRESS - The satrt address of the internal FlashIAPBlockDevice.
+ * MBED_CONF_STORAGE_TDB_EXTERNAL_EXTERNAL_SIZE - Size of the external blockdevice in bytes or NULL for
+ * max possible size.
+ * MBED_CONF_STORAGE_TDB_EXTERNAL_EXTERNAL_BASE_ADDRESS - The block device start address.
+ * MBED_CONF_STORAGE_TDB_EXTERNAL_EXTERNAL_BLOCK_DEVICE - Alowed vlaues are: default, SPIF, DATAFASH, QSPIF or SD
+ * @returns 0 on success or negative value on failure.
+ */
+int _storage_config_TDB_EXTERNAL();
+
+/**
+ * @brief This function initialize a external memory secure storage
+ * This includes a SecureStore class with external TDBStore over a blockdevice or,
+ * if no blockdevice was set the default blockdevice will be used.
+ * The following is a list of configuration parameter:
+ * MBED_CONF_STORAGE_TDB_EXTERNAL_NO_RBP_EXTERNAL_SIZE - Size of the external blockdevice in bytes
+ * or NULL for max possible size.
+ * MBED_CONF_STORAGE_TDB_EXTERNAL_NO_RBP_EXTERNAL_BASE_ADDRESS - The block device start address
+ * MBED_CONF_STORAGE_TDB_EXTERNAL_NO_RBP_EXTERNAL_BLOCK_DEVICE - Alowed vlaues are: default, SPIF, DATAFASH, QSPIF or SD
+ * @returns 0 on success or negative value on failure.
+ */
+int _storage_config_TDB_EXTERNAL_NO_RBP();
+
+/**
+ * @brief This function initialize a FILESYSTEM memory secure storage
+ * This includes a SecureStore class with TDBStore over FlashIAPBlockdevice
+ * in the internal memory and an external FileSysteStore. If blockdevice and filesystem not set,
+ * the system will use the default block device and default filesystem
+ * The following is a list of configuration parameter:
+ * MBED_CONF_STORAGE_FILESYSTEM_RBP_INTERNAL_SIZE - Size of the internal FlashIAPBlockDevice and by
+ * default is set to from start address to the end of the flash.
+ * If start address is 0 the start address will be set to end of
+ * flash - rbp_internal_size.
+ * MBED_CONF_STORAGE_FILESYSTEM_INTERNAL_BASE_ADDRESS - The satrt address of the internal FlashIAPBlockDevice.
+ * MBED_CONF_STORAGE_FILESYSTEM_FILESYSTEM - Allowed values are: default, FAT or LITTLE
+ * MBED_CONF_STORAGE_FILESYSTEM_BLOCKDEVICE - Allowed values are: default, SPIF, DATAFASH, QSPIF or SD
+ * MBED_CONF_STORAGE_FILESYSTEM_EXTERNAL_SIZE - External Blockdevice size in bytes or NULL for max possible size.
+ * MBED_CONF_STORAGE_FILESYSTEM_EXTERNAL_BASE_ADDRESS - The block device start address.
+ * MBED_CONF_STORAGE_FILESYSTEM_MOUNT_POINT - Where to mount the filesystem
+ * MBED_CONF_STORAGE_FILESYSTEM_FOLDER_PATH - The working folder paths
+ *
+ * @returns 0 on success or negative value on failure.
+ */
+int _storage_config_FILESYSTEM();
+
+/**
+ * @brief This function initialize a FILESYSTEM_NO_RBP memory secure storage with no
+ * rollback protection. This includes a SecureStore class an external FileSysteStore over a default
+ * filesystem with default blockdevice unless differently configured.
+ * The following is a list of configuration parameter:
+ * MBED_CONF_STORAGE_FILESYSTEM_NO_RBP_FILESYSTEM - Allowed values are: default, FAT or LITTLE
+ * MBED_CONF_STORAGE_FILESYSTEM_NO_RBP_BLOCKDEVICE - Allowed values are: default, SPIF, DATAFASH, QSPIF or SD
+ * MBED_CONF_STORAGE_FILESYSTEM_NO_RBP_EXTERNAL_SIZE - Blockdevice size in bytes. or NULL for max possible size.
+ * MBED_CONF_STORAGE_FILESYSTEM_NO_RBP_EXTERNAL_BASE_ADDRESS - The block device start address.
+ * MBED_CONF_STORAGE_FILESYSTEM_NO_RBP_MOUNT_POINT - Where to mount the filesystem
+ * MBED_CONF_STORAGE_FILESYSTEM_NO_RBP_FOLDER_PATH - The working folder paths
+ *
+ * @returns 0 on success or negative value on failure.
+ */
+int _storage_config_FILESYSTEM_NO_RBP();
+
+int _storage_config_tdb_external_common();
+int _storage_config_filesystem_common();
+
+static const char *filesystemstore_folder_path = NULL;
+
+using namespace mbed;
+
+
+static SingletonPtr<PlatformMutex> mutex;
+static bool is_kv_config_initialize = false;
+static kvstore_config_t kvstore_config;
+
+#define INTERNAL_BLOCKDEVICE_NAME FLASHIAP
+
+#define STR_EXPAND(tok) #tok
+#define STR(tok) STR_EXPAND(tok)
+
+#define _GET_FILESYSTEM_concat(dev, ...) _get_filesystem_##dev(__VA_ARGS__)
+#define GET_FILESYSTEM(dev, ...) _GET_FILESYSTEM_concat(dev, __VA_ARGS__)
+
+#define _GET_BLOCKDEVICE_concat(dev, ...) _get_blockdevice_##dev(__VA_ARGS__)
+#define GET_BLOCKDEVICE(dev, ...) _GET_BLOCKDEVICE_concat(dev, __VA_ARGS__)
+
+static inline uint32_t align_up(uint64_t val, uint64_t size)
+{
+ return (((val - 1) / size) + 1) * size;
+}
+
+static inline uint32_t align_down(uint64_t val, uint64_t size)
+{
+ return (((val) / size)) * size;
+}
+
+int _calculate_blocksize_match_tdbstore(BlockDevice *bd)
+{
+ bd_size_t size = bd->size();
+ bd_size_t erase_size = bd->get_erase_size();
+ bd_size_t number_of_sector = size / erase_size;
+
+ if (number_of_sector < 2) {
+ tr_warning("KV Config: There are less than two sectors - TDBStore will not work.");
+ return -1;
+ }
+
+
+ if (number_of_sector % 2 != 0) {
+ tr_warning("KV Config: Number of sectors is not an even number. Consider changing the BlockDevice size");
+ }
+
+ return MBED_SUCCESS;
+}
+
+int _get_addresses(BlockDevice *bd, bd_addr_t start_address, bd_size_t size, bd_addr_t *out_start_addr,
+ bd_addr_t *out_end_addr)
+{
+ bd_addr_t aligned_end_address;
+ bd_addr_t end_address;
+ bd_addr_t aligned_start_address;
+
+ aligned_start_address = align_down(start_address, bd->get_erase_size(start_address));
+ if (aligned_start_address != start_address) {
+ tr_error("KV Config: Start address is not aligned. Better use %02llx", aligned_start_address);
+ return -1;
+ }
+
+ if (size == 0) {
+ (*out_start_addr) = aligned_start_address;
+ (*out_end_addr) = bd->size();
+ return 0;
+ }
+
+ end_address = start_address + size;
+ aligned_end_address = align_up(end_address, bd->get_erase_size(end_address));
+ if (aligned_end_address != end_address) {
+ tr_error("KV Config: End address is not aligned. Consider changing the size parameter.");
+ return -1;
+ }
+
+ if (aligned_end_address > bd->size()) {
+ tr_error("KV Config: End address is out of boundaries");
+ return -1;
+ }
+
+ (*out_start_addr) = aligned_start_address;
+ (*out_end_addr) = aligned_end_address;
+ return 0;
+}
+
+FileSystem *_get_filesystem_FAT(const char *mount)
+{
+ static FATFileSystem sdcard(mount);
+ return &sdcard;
+
+}
+
+FileSystem *_get_filesystem_LITTLE(const char *mount)
+{
+ static LittleFileSystem flash(mount);
+ return &flash;
+}
+
+FileSystemStore *_get_file_system_store(FileSystem *fs)
+{
+ static FileSystemStore fss(fs);
+ return &fss;
+}
+
+FileSystem *_get_filesystem_default(const char *mount)
+{
+#if COMPONENT_QSPIF || COMPONENT_SPIF || COMPONENT_DATAFLASH
+ return _get_filesystem_LITTLE(mount);
+#elif COMPONENT_SD
+ return _get_filesystem_FAT(mount);
+#else
+ return NULL;
+#endif
+}
+
+//Calculates the start address of FLASHIAP block device for TDB_INTERNAL profile.
+//If possible, the address will start 2 sectors after the end of code sector allowing
+//some space for an application update.
+int _get_flashiap_bd_default_addresses_tdb_internal(bd_addr_t *start_address, bd_size_t *size)
+{
+#if COMPONENT_FLASHIAP
+
+ FlashIAP flash;
+
+ if (*start_address != 0 || *size != 0) {
+ return MBED_ERROR_INVALID_ARGUMENT;
+ }
+
+ //If default values are set, we should get the maximum available size of internal bd.
+ if (flash.init() != 0) {
+ return MBED_ERROR_FAILED_OPERATION;
+ }
+
+ *start_address = align_up(FLASHIAP_APP_ROM_END_ADDR, flash.get_sector_size(FLASHIAP_APP_ROM_END_ADDR));
+
+ // Give the application a couple of spare sectors to grow (if there are such)
+ bd_size_t spare_size_for_app = 0;
+ bd_addr_t curr_addr = *start_address;
+ bd_addr_t flash_end_address = flash.get_flash_start() + flash.get_flash_size();
+
+ int spare_sectors_for_app = 2;
+ int min_sectors_for_storage = 2;
+ for (int i = 0; i < spare_sectors_for_app + min_sectors_for_storage - 1; i++) {
+ bd_size_t sector_size = flash.get_sector_size(curr_addr);
+ curr_addr += sector_size;
+ if (curr_addr >= flash_end_address) {
+ spare_size_for_app = 0;
+ break;
+ }
+
+ if (i < spare_sectors_for_app) {
+ spare_size_for_app += sector_size;
+ }
+ }
+ *start_address += spare_size_for_app;
+
+ flash.deinit();
+
+#endif
+
+ return MBED_SUCCESS;
+}
+
+//Calculates address and size for FLASHIAP block device in TDB_EXTERNAL and FILESYSTEM profiles.
+//The size of the block device will be 2 sectors at the ends of the internal flash for
+//the use of the rbp internal TDBStore.
+int _get_flashiap_bd_default_addresses_rbp(bd_addr_t *start_address, bd_size_t *size)
+{
+#if COMPONENT_FLASHIAP
+
+ bd_addr_t flash_end_address;
+ bd_addr_t flash_start_address;
+ bd_addr_t aligned_start_address;
+ bd_addr_t flash_first_writable_sector_address;
+ FlashIAP flash;
+
+ if (*start_address != 0 || *size != 0) {
+ return MBED_ERROR_INVALID_ARGUMENT;
+ }
+
+ int ret = flash.init();
+ if (ret != 0) {
+ return MBED_ERROR_INITIALIZATION_FAILED;
+ }
+
+ flash_first_writable_sector_address = align_up(FLASHIAP_APP_ROM_END_ADDR, flash.get_sector_size(FLASHIAP_APP_ROM_END_ADDR));
+ flash_start_address = flash.get_flash_start();
+ flash_end_address = flash_start_address + flash.get_flash_size();;
+ *start_address = flash_end_address - 1;
+ aligned_start_address = align_down(*start_address, flash.get_sector_size(*start_address));
+ *size = (flash_end_address - aligned_start_address) * 2;
+ *start_address = (flash_end_address - *size);
+ aligned_start_address = align_down(*start_address, flash.get_sector_size(*start_address));
+
+ flash.deinit();
+
+ if (aligned_start_address < flash_first_writable_sector_address) {
+ tr_error("KV Config: Internal block device start address overlapped ROM address ");
+ return MBED_ERROR_INITIALIZATION_FAILED;
+ }
+
+#endif
+
+ return MBED_SUCCESS;
+
+}
+
+BlockDevice *_get_blockdevice_FLASHIAP(bd_addr_t start_address, bd_size_t size)
+{
+#if COMPONENT_FLASHIAP
+
+ bd_addr_t flash_end_address;
+ bd_addr_t flash_start_address;
+ bd_addr_t flash_first_writable_sector_address;
+ bd_addr_t aligned_start_address;
+ bd_addr_t aligned_end_address;
+ bd_addr_t end_address;
+ FlashIAP flash;
+
+ int ret = flash.init();
+ if (ret != 0) {
+ return NULL;
+ }
+
+ //Get flash parameters before starting
+ flash_first_writable_sector_address = align_up(FLASHIAP_APP_ROM_END_ADDR, flash.get_sector_size(FLASHIAP_APP_ROM_END_ADDR));
+ flash_start_address = flash.get_flash_start();
+ flash_end_address = flash_start_address + flash.get_flash_size();;
+
+ //Non default configuration
+ if (start_address != 0) {
+
+ aligned_start_address = align_down(start_address, flash.get_sector_size(start_address));
+ if (start_address != aligned_start_address) {
+ tr_error("KV Config: Internal block device start address is not aligned. Better use %02llx", aligned_start_address);
+ flash.deinit();
+ return NULL;
+ }
+
+ if (size == 0) {
+ //The block device will have all space form start address to the end of the flash
+ size = (flash_end_address - start_address);
+
+ static FlashIAPBlockDevice bd(start_address, size);
+ flash.deinit();
+ return &bd;
+ }
+
+ if (size != 0) {
+ end_address = start_address + size;
+ if (end_address > flash_end_address) {
+ tr_error("KV Config: Internal block device end address is out of boundaries");
+ flash.deinit();
+ return NULL;
+ }
+
+ aligned_end_address = align_up(end_address, flash.get_sector_size(end_address - 1));
+ if (end_address != aligned_end_address) {
+ tr_error("KV Config: Internal block device start address is not aligned. Consider changing the size parameter");
+ flash.deinit();
+ return NULL;
+ }
+
+ static FlashIAPBlockDevice bd(start_address, size);
+ flash.deinit();
+ return &bd;
+ }
+ }
+
+ //Non default configuration start_address = 0
+ start_address = flash_end_address - size;
+ aligned_start_address = align_down(start_address, flash.get_sector_size(start_address));
+ if (start_address != aligned_start_address) {
+ tr_error("KV Config: Internal block device start address is not aligned. Consider changing the size parameter");
+ flash.deinit();
+ return NULL;
+ }
+
+ flash.deinit();
+
+ if (aligned_start_address < flash_first_writable_sector_address) {
+ tr_error("KV Config: Internal block device start address overlapped ROM address ");
+ return NULL;
+ }
+ static FlashIAPBlockDevice bd(aligned_start_address, size);
+ return &bd;
+
+#else
+ return NULL;
+#endif
+}
+
+BlockDevice *_get_blockdevice_SPIF(bd_addr_t start_address, bd_size_t size)
+{
+#if COMPONENT_SPIF
+
+ bd_addr_t aligned_end_address;
+ bd_addr_t aligned_start_address;
+
+ static SPIFBlockDevice bd(
+ MBED_CONF_SPIF_DRIVER_SPI_MOSI,
+ MBED_CONF_SPIF_DRIVER_SPI_MISO,
+ MBED_CONF_SPIF_DRIVER_SPI_CLK,
+ MBED_CONF_SPIF_DRIVER_SPI_CS,
+ MBED_CONF_SPIF_DRIVER_SPI_FREQ
+ );
+
+ if (bd.init() != MBED_SUCCESS) {
+ tr_error("KV Config: SPIFBlockDevice init fail");
+ return NULL;
+ }
+
+ if (start_address == 0 && size == 0) {
+ return &bd;
+ }
+
+ //If address and size were specified use SlicingBlockDevice to get the correct block device size and start address.
+ if (_get_addresses(&bd, start_address, size, &aligned_start_address, &aligned_end_address) != 0) {
+ tr_error("KV Config: Fail to get addresses for SlicingBlockDevice.");
+ return NULL;
+ }
+
+ static SlicingBlockDevice sbd(&bd, aligned_start_address, aligned_end_address);
+ return &sbd;
+
+#else
+ return NULL;
+#endif
+}
+
+BlockDevice *_get_blockdevice_QSPIF(bd_addr_t start_address, bd_size_t size)
+{
+#if COMPONENT_QSPIF
+
+ bd_addr_t aligned_end_address;
+ bd_addr_t aligned_start_address;
+
+ static QSPIFBlockDevice bd(
+ QSPI_FLASH1_IO0,
+ QSPI_FLASH1_IO1,
+ QSPI_FLASH1_IO2,
+ QSPI_FLASH1_IO3,
+ QSPI_FLASH1_SCK,
+ QSPI_FLASH1_CSN,
+ QSPIF_POLARITY_MODE_0,
+ MBED_CONF_QSPIF_QSPI_FREQ
+ );
+
+ if (bd.init() != MBED_SUCCESS) {
+ tr_error("KV Config: QSPIFBlockDevice init fail");
+ return NULL;
+ }
+
+ if (start_address == 0 && size == 0) {
+ return &bd;
+ }
+
+ //If address and size were specified use SlicingBlockDevice to get the correct block device size and start address.
+ if (_get_addresses(&bd, start_address, size, &aligned_start_address, &aligned_end_address) != 0) {
+ tr_error("KV Config: Fail to get addresses for SlicingBlockDevice.");
+ return NULL;
+ }
+
+ static SlicingBlockDevice sbd(&bd, aligned_start_address, aligned_end_address);
+ return &sbd;
+
+#else
+ return NULL;
+#endif
+}
+
+BlockDevice *_get_blockdevice_DATAFLASH(bd_addr_t start_address, bd_size_t size)
+{
+#if COMPONENT_DATAFLASH
+
+ bd_addr_t aligned_end_address;
+ bd_addr_t aligned_start_address;
+
+ static DataFlashBlockDevice bd(
+ MBED_CONF_DATAFLASH_SPI_MOSI,
+ MBED_CONF_DATAFLASH_SPI_MISO,
+ MBED_CONF_DATAFLASH_SPI_CLK,
+ MBED_CONF_DATAFLASH_SPI_CS
+ );
+
+ if (bd.init() != MBED_SUCCESS) {
+ tr_error("KV Config: DataFlashBlockDevice init fail");
+ return NULL;
+ }
+
+ if (start_address == 0 && size == 0) {
+ return &bd;
+ }
+
+ //If address and size were specified use SlicingBlockDevice to get the correct block device size and start address.
+ if (_get_addresses(&bd, start_address, size, &aligned_start_address, &aligned_end_address) != 0) {
+ tr_error("KV Config: Fail to get addresses for SlicingBlockDevice.");
+ return NULL;
+ }
+
+ static SlicingBlockDevice sbd(&bd, aligned_start_address, aligned_end_address);
+ return &sbd;
+
+
+#else
+ return NULL;
+#endif
+}
+
+BlockDevice *_get_blockdevice_SD(bd_addr_t start_address, bd_size_t size)
+{
+#if COMPONENT_SD
+
+ bd_addr_t aligned_end_address;
+ bd_addr_t aligned_start_address;
+
+ #if (defined(TARGET_VK_RZ_A1H) || defined(TARGET_VK_RZ_A1LU))
+ static SDHIBlockDevice bd(
+ MBED_CONF_SD_SDHI_CH
+ );
+ #else
+ static SDBlockDevice bd(
+ MBED_CONF_SD_SPI_MOSI,
+ MBED_CONF_SD_SPI_MISO,
+ MBED_CONF_SD_SPI_CLK,
+ MBED_CONF_SD_SPI_CS
+ );
+ #endif
+
+ if (bd.init() != MBED_SUCCESS) {
+ tr_error("KV Config: SDBlockDevice init fail");
+ return NULL;
+ }
+
+ if (strcmp(STR(MBED_CONF_STORAGE_STORAGE_TYPE), "TDB_EXTERNAL_NO_RBP") == 0 ||
+ strcmp(STR(MBED_CONF_STORAGE_STORAGE_TYPE), "TDB_EXTERNAL") == 0) {
+ //In TDBStore profile, we have a constraint of 4GByte
+ if (start_address == 0 && size == 0 && bd.size() < (uint32_t)(-1)) {
+ return &bd;
+ }
+
+ //If the size of external storage is bigger than 4G we need to slice it.
+ size = size != 0 ? size : align_down(bd.size(), bd.get_erase_size(bd.size() - 1));
+
+ if (_get_addresses(&bd, start_address, size, &aligned_start_address, &aligned_end_address) != 0) {
+ tr_error("KV Config: Fail to get addresses for SlicingBlockDevice.");
+ return NULL;
+ }
+
+ if (aligned_end_address - aligned_start_address != (uint32_t)(aligned_end_address - aligned_start_address)) {
+ aligned_end_address = aligned_start_address + (uint32_t)(-1);//Support up to 4G only
+ }
+ } else {
+ //For all other KVStore profiles beside TDBStore we take the entire external memory space.
+ if (start_address == 0 && size == 0) {
+ return &bd;
+ }
+
+ if (_get_addresses(&bd, start_address, size, &aligned_start_address, &aligned_end_address) != 0) {
+ tr_error("KV Config: Fail to get addresses for SlicingBlockDevice.");
+ return NULL;
+ }
+ }
+
+ aligned_end_address = align_down(aligned_end_address, bd.get_erase_size(aligned_end_address));
+ static SlicingBlockDevice sbd(&bd, aligned_start_address, aligned_end_address);
+ return &sbd;
+
+#else
+ return NULL;
+#endif
+}
+
+BlockDevice *_get_blockdevice_default(bd_addr_t start_address, bd_size_t size)
+{
+#if COMPONENT_QSPIF
+ return _get_blockdevice_QSPIF(start_address, size);
+#elif COMPONENT_SPIF
+ return _get_blockdevice_SPIF(start_address, size);
+#elif COMPONENT_DATAFLASH
+ return _get_blockdevice_DATAFLASH(start_address, size);
+#elif COMPONENT_SD
+ return _get_blockdevice_SD(start_address, size);
+#else
+ tr_error("KV Config: No default component define in target.json for this target.");
+ return NULL;
+#endif
+}
+
+int _storage_config_TDB_INTERNAL()
+{
+#if COMPONENT_FLASHIAP
+ bd_size_t internal_size = MBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_SIZE;
+ bd_addr_t internal_start_address = MBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_BASE_ADDRESS;
+
+ if (internal_size == 0 && internal_start_address == 0) {
+ //Calculate the block device size and start address in case default values are used.
+ if (_get_flashiap_bd_default_addresses_tdb_internal(&internal_start_address, &internal_size) != MBED_SUCCESS) {
+ return MBED_ERROR_FAILED_OPERATION;
+ }
+ }
+
+ //Get internal memory FLASHIAP block device.
+ kvstore_config.internal_bd = GET_BLOCKDEVICE(INTERNAL_BLOCKDEVICE_NAME, internal_start_address, internal_size);
+ if (kvstore_config.internal_bd == NULL) {
+ tr_error("KV Config: Fail to get internal BlockDevice.");
+ return MBED_ERROR_FAILED_OPERATION;
+ }
+
+
+ int ret = kvstore_config.internal_bd->init();
+ if (ret != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to init internal BlockDevice.");
+ return MBED_ERROR_FAILED_OPERATION;
+ }
+
+ //Check that internal flash has 2 or more sectors
+ if (_calculate_blocksize_match_tdbstore(kvstore_config.internal_bd) != MBED_SUCCESS) {
+ tr_error("KV Config: Can not create TDBStore with less then 2 sector.");
+ return MBED_ERROR_INVALID_ARGUMENT;
+ }
+
+ //Deinitialize internal block device and TDB will reinitialize and take control on it.
+ ret = kvstore_config.internal_bd->deinit();
+ if (ret != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to deinit internal BlockDevice.");
+ return MBED_ERROR_FAILED_OPERATION;
+ }
+
+ //Create a TDBStore in the internal FLASHIAP block device.
+ static TDBStore tdb_internal(kvstore_config.internal_bd);
+ kvstore_config.internal_store = &tdb_internal;
+
+ ret = kvstore_config.internal_store->init();
+ if (ret != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to init internal TDBStore.");
+ return ret;
+ }
+ kvstore_config.kvstore_main_instance =
+ kvstore_config.internal_store;
+
+ //Masking flag - Actually used to remove any KVStore flag which is not supported
+ //in the chosen KVStore profile.
+ kvstore_config.flags_mask = ~(KVStore::REQUIRE_CONFIDENTIALITY_FLAG |
+ KVStore::REQUIRE_REPLAY_PROTECTION_FLAG);
+
+ //Initialize kv_map and add the configuration struct to KVStore map.
+ KVMap &kv_map = KVMap::get_instance();
+ ret = kv_map.init();
+ if (MBED_SUCCESS != ret) {
+ tr_error("KV Config: Fail to init KVStore global API.");
+ return ret;
+ }
+
+ ret = kv_map.attach(STR(MBED_CONF_STORAGE_DEFAULT_KV), &kvstore_config);
+ if (MBED_SUCCESS != ret) {
+ tr_error("KV Config: Fail to attach KVStore main instance to KVStore global API.");
+ return ret;
+ }
+ return MBED_SUCCESS;
+#else
+ return MBED_ERROR_UNSUPPORTED;
+#endif
+
+}
+
+int _storage_config_TDB_EXTERNAL()
+{
+#if !SECURESTORE_ENABLED
+ return MBED_ERROR_UNSUPPORTED;
+#endif
+
+ bd_size_t internal_rbp_size = MBED_CONF_STORAGE_TDB_EXTERNAL_RBP_INTERNAL_SIZE;
+ bd_addr_t internal_start_address = MBED_CONF_STORAGE_TDB_EXTERNAL_INTERNAL_BASE_ADDRESS;
+
+ //Get the default address and size for internal rbp TDBStore
+ if (internal_rbp_size == 0 && internal_start_address == 0) {
+ //Calculate the block device size and start address in case default values are used.
+ if (_get_flashiap_bd_default_addresses_rbp(&internal_start_address, &internal_rbp_size) != MBED_SUCCESS) {
+ return MBED_ERROR_FAILED_OPERATION;
+ }
+ }
+
+ //Create internal FLASHIAP block device
+ kvstore_config.internal_bd = GET_BLOCKDEVICE(INTERNAL_BLOCKDEVICE_NAME, internal_start_address, internal_rbp_size);
+ if (kvstore_config.internal_bd == NULL) {
+ tr_error("KV Config: Fail to get internal BlockDevice.");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ int ret = kvstore_config.internal_bd->init();
+ if (ret != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to init internal BlockDevice.");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ //Check if TDBStore has at least 2 sector.
+ if (_calculate_blocksize_match_tdbstore(kvstore_config.internal_bd) != MBED_SUCCESS) {
+ tr_error("KV Config: Can not create TDBStore with less then 2 sector.");
+ return MBED_ERROR_INVALID_ARGUMENT;
+ }
+
+ //Create internal TDBStore
+ static TDBStore tdb_internal(kvstore_config.internal_bd);
+ kvstore_config.internal_store = &tdb_internal;
+
+ ret = kvstore_config.internal_store->init();
+ if (ret != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to init internal TDBStore.");
+ return ret;
+ }
+
+ bd_size_t size = MBED_CONF_STORAGE_TDB_EXTERNAL_EXTERNAL_SIZE;
+ bd_addr_t address = MBED_CONF_STORAGE_TDB_EXTERNAL_EXTERNAL_BASE_ADDRESS;
+
+ //Get external BlockDevice for TDBStore
+ BlockDevice *bd = GET_BLOCKDEVICE(MBED_CONF_STORAGE_TDB_EXTERNAL_BLOCKDEVICE, address, size);
+ if (bd == NULL) {
+ tr_error("KV Config: Fail to get external BlockDevice.");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ //TDBStore needs a block device base on flash. so if this is SD block device or the default block device is SD
+ //add FlashSimBlockDevice on top of the SDBlockDevice
+#if defined(COMPONENT_SD)
+ if (strcmp(STR(MBED_CONF_STORAGE_TDB_EXTERNAL_BLOCKDEVICE), "SD") == 0
+#if defined(COMPONENT_SD) && !defined(COMPONENT_SPIF) && !defined(COMPONENT_QSPIF) && !defined(COMPONENT_DATAFLASH)
+ || strcmp(STR(MBED_CONF_STORAGE_TDB_EXTERNAL_BLOCKDEVICE), "default") == 0) {
+#else
+ ) {
+
+#endif
+ //TDBStore need FlashSimBlockDevice when working with SD block device
+ if (bd->init() != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to init external BlockDevice.");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ static FlashSimBlockDevice flash_bd(bd);
+ kvstore_config.external_bd = &flash_bd;
+ } else {
+ kvstore_config.external_bd = bd;
+ }
+#else
+ kvstore_config.external_bd = bd;
+#endif
+
+ kvstore_config.flags_mask = ~(0);
+
+ return _storage_config_tdb_external_common();
+}
+
+int _storage_config_TDB_EXTERNAL_NO_RBP()
+{
+#if !SECURESTORE_ENABLED
+ return MBED_ERROR_UNSUPPORTED;
+#endif
+ bd_size_t size = MBED_CONF_STORAGE_TDB_EXTERNAL_NO_RBP_EXTERNAL_SIZE;
+ bd_addr_t address = MBED_CONF_STORAGE_TDB_EXTERNAL_NO_RBP_EXTERNAL_BASE_ADDRESS;
+
+ //Get external block device
+ BlockDevice *bd = GET_BLOCKDEVICE(MBED_CONF_STORAGE_TDB_EXTERNAL_NO_RBP_BLOCKDEVICE, address, size);
+ if (bd == NULL) {
+ tr_error("KV Config: Fail to get external BlockDevice.");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ //TDBStore needs a block device base on flash. so if this is SD block device or the default block device is SD
+ //add FlashSimBlockDevice on top of the SDBlockDevice
+#if defined(COMPONENT_SD)
+ if (strcmp(STR(MBED_CONF_STORAGE_TDB_EXTERNAL_NO_RBP_BLOCKDEVICE), "SD") == 0
+#if defined(COMPONENT_SD) && !defined(COMPONENT_SPIF) && !defined(COMPONENT_QSPIF) && !defined(COMPONENT_DATAFLASH)
+ || strcmp(STR(MBED_CONF_STORAGE_TDB_EXTERNAL_NO_RBP_BLOCKDEVICE), "default") == 0) {
+#else
+ ) {
+
+#endif
+ //TDBStore need FlashSimBlockDevice when working with SD block device
+ if (bd->init() != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to init external BlockDevice.");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ static FlashSimBlockDevice flash_bd(bd);
+ kvstore_config.external_bd = &flash_bd;
+ } else {
+ kvstore_config.external_bd = bd;
+ }
+#else
+ kvstore_config.external_bd = bd;
+#endif
+
+ //Masking flag - Actually used to remove any KVStore flag which is not supported
+ //in the chosen KVStore profile.
+ kvstore_config.flags_mask = ~(KVStore::REQUIRE_REPLAY_PROTECTION_FLAG);
+
+ return _storage_config_tdb_external_common();
+}
+
+int _storage_config_tdb_external_common()
+{
+#if SECURESTORE_ENABLED
+ //Initialize external block device
+ int ret = kvstore_config.external_bd->init();
+ if (ret != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to init external BlockDevice.");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ //Check that there is at least 2 sector for the external TDBStore
+ if (_calculate_blocksize_match_tdbstore(kvstore_config.external_bd) != MBED_SUCCESS) {
+ tr_error("KV Config: Can not create TDBStore with less then 2 sector.");
+ return MBED_ERROR_INVALID_SIZE;
+ }
+
+ //Create external TDBStore
+ static TDBStore tdb_external(kvstore_config.external_bd);
+ kvstore_config.external_store = &tdb_external;
+
+ //Create SecureStore and initialize it
+ static SecureStore secst(kvstore_config.external_store, kvstore_config.internal_store);
+
+ ret = secst.init();
+ if (ret != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to init SecureStore.");
+ return ret ;
+ }
+
+ kvstore_config.kvstore_main_instance = &secst;
+
+ //Init kv_map and add the configuration struct to KVStore map.
+ KVMap &kv_map = KVMap::get_instance();
+ ret = kv_map.init();
+ if (MBED_SUCCESS != ret) {
+ tr_error("KV Config: Fail to init KVStore global API");
+ return ret;
+ }
+
+ ret = kv_map.attach(STR(MBED_CONF_STORAGE_DEFAULT_KV), &kvstore_config);
+ if (MBED_SUCCESS != ret) {
+ tr_error("KV Config: Fail to attach KvStore main instance to KVStore global API");
+ return ret;
+ }
+
+ return MBED_SUCCESS;
+#else
+ return MBED_ERROR_UNSUPPORTED;
+#endif
+}
+
+int _storage_config_FILESYSTEM()
+{
+#if !SECURESTORE_ENABLED
+ return MBED_ERROR_UNSUPPORTED;
+#endif
+
+ filesystemstore_folder_path = STR(MBED_CONF_STORAGE_FILESYSTEM_FOLDER_PATH);
+
+ bd_size_t internal_rbp_size = MBED_CONF_STORAGE_FILESYSTEM_RBP_INTERNAL_SIZE;
+ bd_addr_t internal_start_address = MBED_CONF_STORAGE_FILESYSTEM_INTERNAL_BASE_ADDRESS;
+
+ //Get the default address and size for internal rbp TDBStore
+ if (internal_rbp_size == 0 && internal_start_address == 0) {
+ //Calculate the block device size and start address in case default values are used.
+ if (_get_flashiap_bd_default_addresses_rbp(&internal_start_address, &internal_rbp_size) != MBED_SUCCESS) {
+ return MBED_ERROR_FAILED_OPERATION;
+ }
+ }
+
+ //Get internal FLASHIAP block device
+ kvstore_config.internal_bd = GET_BLOCKDEVICE(INTERNAL_BLOCKDEVICE_NAME, internal_start_address, internal_rbp_size);
+ if (kvstore_config.internal_bd == NULL) {
+ tr_error("KV Config: Fail to get internal BlockDevice ");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ int ret = kvstore_config.internal_bd->init();
+ if (ret != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to init internal BlockDevice ");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ //Check that internal flash has 2 or more sectors
+ if (_calculate_blocksize_match_tdbstore(kvstore_config.internal_bd) != MBED_SUCCESS) {
+ tr_error("KV Config: Can not create TDBStore with less then 2 sector.");
+ return MBED_ERROR_INVALID_ARGUMENT;
+ }
+
+ //Deinitialize internal block device and TDB will reinitialize and take control on it.
+ ret = kvstore_config.internal_bd->deinit();
+ if (ret != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to deinit internal BlockDevice.");
+ return MBED_ERROR_FAILED_OPERATION;
+ }
+
+ //Create internal TDBStore for rbp
+ static TDBStore tdb_internal(kvstore_config.internal_bd);
+ kvstore_config.internal_store = &tdb_internal;
+
+ ret = kvstore_config.internal_store->init();
+ if (ret != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to init internal TDBStore");
+ return ret;
+ }
+
+ bd_size_t size = MBED_CONF_STORAGE_FILESYSTEM_EXTERNAL_SIZE;
+ bd_addr_t address = MBED_CONF_STORAGE_FILESYSTEM_EXTERNAL_BASE_ADDRESS;
+ const char *mount_point = STR(MBED_CONF_STORAGE_FILESYSTEM_MOUNT_POINT);
+
+ //Get external block device for FileSystem.
+ kvstore_config.external_bd = GET_BLOCKDEVICE(MBED_CONF_STORAGE_FILESYSTEM_BLOCKDEVICE, address, size);
+ if (kvstore_config.external_bd == NULL) {
+ tr_error("KV Config: Fail to get external BlockDevice ");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ ret = kvstore_config.external_bd->init();
+ if (MBED_SUCCESS != ret) {
+ tr_error("KV Config: Fail to init external BlockDevice ");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ //Get FileSystem. Can be FAT, LITTLE or default. in case of default, the type will be decided base on the default
+ //component block device configured in the system. The priority is:
+ //QSPI -> SPI -> DATAFLASH == LITTLE
+ //SD == FAT
+ kvstore_config.external_fs = GET_FILESYSTEM(MBED_CONF_STORAGE_FILESYSTEM_FILESYSTEM, mount_point);
+ if (kvstore_config.external_fs == NULL) {
+ tr_error("KV Config: Fail to get FileSystem");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ kvstore_config.flags_mask = ~(0);
+
+ return _storage_config_filesystem_common();
+}
+
+int _storage_config_FILESYSTEM_NO_RBP()
+{
+#if !SECURESTORE_ENABLED
+ return MBED_ERROR_UNSUPPORTED;
+#endif
+
+ filesystemstore_folder_path = STR(MBED_CONF_STORAGE_FILESYSTEM_NO_RBP_FOLDER_PATH);
+
+ bd_size_t size = MBED_CONF_STORAGE_FILESYSTEM_NO_RBP_EXTERNAL_SIZE;
+ bd_addr_t address = MBED_CONF_STORAGE_FILESYSTEM_NO_RBP_EXTERNAL_BASE_ADDRESS;
+ const char *mount_point = STR(MBED_CONF_STORAGE_FILESYSTEM_NO_RBP_MOUNT_POINT);
+
+ //Get external block device for FileSystem.
+ kvstore_config.external_bd = GET_BLOCKDEVICE(MBED_CONF_STORAGE_FILESYSTEM_NO_RBP_BLOCKDEVICE, address, size);
+ if (kvstore_config.external_bd == NULL) {
+ tr_error("KV Config: Fail to get external BlockDevice ");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ int ret = kvstore_config.external_bd->init();
+ if (MBED_SUCCESS != ret) {
+ tr_error("KV Config: Fail to init external BlockDevice ");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ //Get FileSystem. Can be FAT, LITTLE or default. in case of default, the type will be decided base on the default
+ //component block device configured in the system. The priority is:
+ //QSPI -> SPI -> DATAFLASH == LITTLE
+ //SD == FAT
+ kvstore_config.external_fs = GET_FILESYSTEM(MBED_CONF_STORAGE_FILESYSTEM_NO_RBP_FILESYSTEM, mount_point);
+ if (kvstore_config.external_fs == NULL) {
+ tr_error("KV Config: Fail to get FileSystem");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ //Masking flag - Actually used to remove any KVStore flag which is not supported
+ //in the chosen KVStore profile.
+ kvstore_config.flags_mask = ~(KVStore::REQUIRE_REPLAY_PROTECTION_FLAG);
+
+ return _storage_config_filesystem_common();
+}
+
+int _storage_config_filesystem_common()
+{
+#if SECURESTORE_ENABLED
+
+ //Mount file system. if it fails, try to reformat
+ int ret = kvstore_config.external_fs->mount(kvstore_config.external_bd);
+ if (ret != MBED_SUCCESS) {
+ ret = kvstore_config.external_fs->reformat(kvstore_config.external_bd);
+ if (ret != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to mount FileSystem to %s",
+ STR(MBED_CONF_STORAGE_FILESYSTEM_NO_RBP_MOUNT_POINT));
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+ }
+
+ //Create FileSystemStore
+ kvstore_config.external_store = _get_file_system_store(kvstore_config.external_fs);
+ if (kvstore_config.external_store == NULL) {
+ tr_error("KV Config: Fail to get FileSystemStore");
+ return MBED_ERROR_FAILED_OPERATION ;
+ }
+
+ //Create SecureStore and set it as main KVStore
+ static SecureStore secst(kvstore_config.external_store, kvstore_config.internal_store);
+
+ ret = secst.init();
+ if (ret != MBED_SUCCESS) {
+ tr_error("KV Config: Fail to init SecureStore.");
+ return ret; ;
+ }
+
+ kvstore_config.kvstore_main_instance = &secst;
+
+ //Init kv_map and add the configuration struct to KVStore map.
+ KVMap &kv_map = KVMap::get_instance();
+ ret = kv_map.init();
+ if (MBED_SUCCESS != ret) {
+ tr_error("KV Config: Fail to init KVStore global API");
+ return ret;
+ }
+
+ ret = kv_map.attach(STR(MBED_CONF_STORAGE_DEFAULT_KV), &kvstore_config);
+ if (MBED_SUCCESS != ret) {
+ tr_error("KV Config: Fail to attach KvStore main instance to KVStore global API");
+ return ret;
+ }
+
+ return MBED_SUCCESS;
+#else
+ return MBED_ERROR_UNSUPPORTED;
+#endif
+}
+
+int _storage_config_default()
+{
+#if COMPONENT_QSPIF || COMPONENT_SPIF || COMPONENT_DATAFLASH
+ return _storage_config_TDB_EXTERNAL();
+#elif COMPONENT_SD
+ return _storage_config_FILESYSTEM();
+#elif COMPONENT_FLASHIAP
+ return _storage_config_TDB_INTERNAL();
+#else
+ return MBED_ERROR_UNSUPPORTED;
+#endif
+}
+
+const char *get_filesystemstore_folder_path()
+{
+ return filesystemstore_folder_path;
+}
+
+MBED_WEAK int kv_init_storage_config()
+{
+
+ int ret = MBED_SUCCESS;
+
+ // We currently have no supported configuration without internal storage
+#ifndef COMPONENT_FLASHIAP
+ return MBED_ERROR_UNSUPPORTED;
+#endif
+
+ mutex->lock();
+
+ if (is_kv_config_initialize) {
+ goto exit;
+ }
+
+ memset(&kvstore_config, 0, sizeof(kvstore_config_t));
+
+ ret = _STORAGE_CONFIG(MBED_CONF_STORAGE_STORAGE_TYPE);
+
+ if (ret == MBED_SUCCESS) {
+ is_kv_config_initialize = true;
+ }
+
+exit:
+ mutex->unlock();
+ return ret;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/features/storage/system_storage/SystemStorage.cpp Mon Mar 18 16:54:40 2019 +0000
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2018 ARM Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SystemStorage.h"
+#include "BlockDevice.h"
+#include "FileSystem.h"
+#include "FATFileSystem.h"
+#include "LittleFileSystem.h"
+#include "mbed_error.h"
+
+
+#if COMPONENT_SPIF
+#include "SPIFBlockDevice.h"
+#endif
+
+#if COMPONENT_QSPIF
+#include "QSPIFBlockDevice.h"
+#endif
+
+#if COMPONENT_DATAFLASH
+#include "DataFlashBlockDevice.h"
+#endif
+
+#if COMPONENT_SD
+ #if (defined(TARGET_VK_RZ_A1H) || defined(TARGET_VK_RZ_A1LU))
+ #include "SDHIBlockDevice.h"
+ #else
+ #include "SDBlockDevice.h"
+ #endif
+#endif
+
+#if COMPONENT_FLASHIAP
+#include "FlashIAPBlockDevice.h"
+#endif
+
+using namespace mbed;
+
+
+
+MBED_WEAK int avoid_conflict_nvstore_tdbstore(owner_type_e in_mem_owner)
+{
+ int status = MBED_SUCCESS;
+ static PlatformMutex _mutex;
+ static owner_type_e internal_memory_owner = NONE;
+
+ _mutex.lock();
+
+ if (internal_memory_owner != NONE &&
+ internal_memory_owner != in_mem_owner) {
+
+ status = MBED_ERROR_ALREADY_INITIALIZED;
+
+ } else {
+
+ internal_memory_owner = in_mem_owner;
+ }
+
+ _mutex.unlock();
+
+ return status;
+}
+
+// Align a value to a specified size.
+// Parameters :
+// val - [IN] Value.
+// size - [IN] Size.
+// Return : Aligned value.
+static inline uint32_t align_up(uint32_t val, uint32_t size)
+{
+ return (((val - 1) / size) + 1) * size;
+}
+
+MBED_WEAK BlockDevice *BlockDevice::get_default_instance()
+{
+#if COMPONENT_SPIF
+
+ static SPIFBlockDevice default_bd(
+ MBED_CONF_SPIF_DRIVER_SPI_MOSI,
+ MBED_CONF_SPIF_DRIVER_SPI_MISO,
+ MBED_CONF_SPIF_DRIVER_SPI_CLK,
+ MBED_CONF_SPIF_DRIVER_SPI_CS,
+ MBED_CONF_SPIF_DRIVER_SPI_FREQ
+ );
+
+ return &default_bd;
+
+#elif COMPONENT_QSPIF
+
+ static QSPIFBlockDevice default_bd(
+ MBED_CONF_QSPIF_QSPI_IO0,
+ MBED_CONF_QSPIF_QSPI_IO1,
+ MBED_CONF_QSPIF_QSPI_IO2,
+ MBED_CONF_QSPIF_QSPI_IO3,
+ MBED_CONF_QSPIF_QSPI_SCK,
+ MBED_CONF_QSPIF_QSPI_CSN,
+ MBED_CONF_QSPIF_QSPI_POLARITY_MODE,
+ MBED_CONF_QSPIF_QSPI_FREQ
+ );
+
+ return &default_bd;
+
+#elif COMPONENT_DATAFLASH
+
+ static DataFlashBlockDevice default_bd(
+ MBED_CONF_DATAFLASH_SPI_MOSI,
+ MBED_CONF_DATAFLASH_SPI_MISO,
+ MBED_CONF_DATAFLASH_SPI_CLK,
+ MBED_CONF_DATAFLASH_SPI_CS
+ );
+
+ return &default_bd;
+
+#elif COMPONENT_SD
+
+ #if (defined(TARGET_VK_RZ_A1H) || defined(TARGET_VK_RZ_A1LU))
+ static SDHIBlockDevice default_bd(
+ MBED_CONF_SD_SDHI_CH
+ );
+ #else
+ static SDBlockDevice default_bd(
+ MBED_CONF_SD_SPI_MOSI,
+ MBED_CONF_SD_SPI_MISO,
+ MBED_CONF_SD_SPI_CLK,
+ MBED_CONF_SD_SPI_CS
+ );
+ #endif
+
+ return &default_bd;
+
+#elif COMPONENT_FLASHIAP
+
+#if (MBED_CONF_FLASHIAP_BLOCK_DEVICE_SIZE == 0) && (MBED_CONF_FLASHIAP_BLOCK_DEVICE_BASE_ADDRESS == 0xFFFFFFFF)
+
+ size_t flash_size;
+ uint32_t start_address;
+ uint32_t bottom_address;
+ FlashIAP flash;
+
+ int ret = flash.init();
+ if (ret != 0) {
+ return 0;
+ }
+
+ //Find the start of first sector after text area
+ bottom_address = align_up(FLASHIAP_APP_ROM_END_ADDR, flash.get_sector_size(FLASHIAP_APP_ROM_END_ADDR));
+ start_address = flash.get_flash_start();
+ flash_size = flash.get_flash_size();
+
+ ret = flash.deinit();
+
+ static FlashIAPBlockDevice default_bd(bottom_address, start_address + flash_size - bottom_address);
+
+#else
+
+ static FlashIAPBlockDevice default_bd;
+
+#endif
+
+ return &default_bd;
+
+#else
+
+ return NULL;
+
+#endif
+
+}
+
+MBED_WEAK FileSystem *FileSystem::get_default_instance()
+{
+#if COMPONENT_SPIF || COMPONENT_QSPIF || COMPONENT_DATAFLASH
+
+ static LittleFileSystem flash("flash", BlockDevice::get_default_instance());
+ flash.set_as_default();
+
+ return &flash;
+
+#elif COMPONENT_SD
+
+ static FATFileSystem sdcard("sd", BlockDevice::get_default_instance());
+ sdcard.set_as_default();
+
+ return &sdcard;
+
+#elif COMPONENT_FLASHIAP
+
+ static LittleFileSystem flash("flash", BlockDevice::get_default_instance());
+ flash.set_as_default();
+
+ return &flash;
+
+#else
+
+ return NULL;
+
+#endif
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/PeripheralPins.h Mon Mar 18 16:54:40 2019 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+typedef struct {
+ PinName pin;
+ int function;
+ int pm;
+} PinFunc;
+
+/************IRQ***************/
+extern const PinMap PinMap_IRQ[];
+
+/************PINMAP***************/
+extern const PinFunc PIPC_0_tbl[];
+
+/************ADC***************/
+extern const PinMap PinMap_ADC[];
+
+/************DAC***************/
+extern const PinMap PinMap_DAC[];
+
+/************I2C***************/
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+
+/************UART***************/
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+extern const PinMap PinMap_UART_CTS[];
+extern const PinMap PinMap_UART_RTS[];
+
+/************SPI***************/
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SSEL[];
+
+/************PWM***************/
+extern const PinMap PinMap_PWM[];
+
+/************CAN***************/
+extern const PinMap PinMap_CAN_RD[];
+extern const PinMap PinMap_CAN_TD[];
+
+#if (defined(TARGET_VK_RZ_A1H) || defined(TARGET_VK_RZ_A1LU))
+/************SDHI***************/
+extern const PinMap PinMap_SDHI_WP[];
+extern const PinMap PinMap_SDHI_CD[];
+extern const PinMap PinMap_SDHI_CLK[];
+extern const PinMap PinMap_SDHI_CMD[];
+extern const PinMap PinMap_SDHI_D0[];
+extern const PinMap PinMap_SDHI_D1[];
+extern const PinMap PinMap_SDHI_D2[];
+extern const PinMap PinMap_SDHI_D3[];
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h Mon Mar 18 16:54:40 2019 +0000
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART0,
+ UART1,
+ UART2,
+ UART3,
+ UART4,
+ UART5,
+ UART6,
+ UART7,
+} UARTName;
+
+typedef enum {
+ PWM_PWM1A = 0,
+ PWM_PWM1B,
+ PWM_PWM1C,
+ PWM_PWM1D,
+ PWM_PWM1E,
+ PWM_PWM1F,
+ PWM_PWM1G,
+ PWM_PWM1H,
+ PWM_PWM2A,
+ PWM_PWM2B,
+ PWM_PWM2C,
+ PWM_PWM2D,
+ PWM_PWM2E,
+ PWM_PWM2F,
+ PWM_PWM2G,
+ PWM_PWM2H,
+ PWM_TIOC0A = 0x20,
+ PWM_TIOC0C,
+ PWM_TIOC1A,
+ PWM_TIOC2A,
+ PWM_TIOC3A,
+ PWM_TIOC3C,
+ PWM_TIOC4A,
+ PWM_TIOC4C,
+} PWMName;
+
+typedef enum {
+ AN0= 0,
+ AN1= 1,
+ AN2= 2,
+ AN3= 3,
+ AN4= 4,
+ AN5= 5,
+ AN6= 6,
+ AN7= 7,
+} ADCName;
+
+typedef enum {
+ SPI_0 = 0,
+ SPI_1,
+ SPI_2,
+ SPI_3,
+ SPI_4,
+} SPIName;
+
+typedef enum {
+ I2C_0 = 0,
+ I2C_1,
+ I2C_2,
+ I2C_3,
+} I2CName;
+
+typedef enum {
+ CAN_0 = 0,
+ CAN_1,
+ CAN_2,
+ CAN_3,
+ CAN_4,
+} CANName;
+
+typedef enum {
+ SDHI_0 = 0,
+ SDHI_1
+} SDHIName;
+
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART3
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c Mon Mar 18 16:54:40 2019 +0000
@@ -0,0 +1,588 @@
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+/************IRQ***************/
+enum {
+ IRQ0,IRQ1,
+ IRQ2,IRQ3,
+ IRQ4,IRQ5,
+ IRQ6,IRQ7,
+} IRQNo;
+const PinMap PinMap_IRQ[] = {
+#ifdef MAX_PERI
+ {P1_0, IRQ0, 4}, {P4_8, IRQ0, 8}, {P6_8, IRQ0, 8}, {P7_9, IRQ0, 8}, {P8_2, IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8, IRQ0, 2}, {P9_1, IRQ0, 4},
+ {P1_1, IRQ1, 4}, {P4_9, IRQ1, 8}, {P6_9, IRQ1, 8}, {P7_8, IRQ1, 8}, {P8_3, IRQ1, 6}, {P2_15, IRQ1, 8},
+ {P1_2, IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, {P6_3, IRQ2, 4},
+ {P1_3, IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9, IRQ3, 3}, {P6_4, IRQ3, 4},
+ {P1_4, IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3, IRQ4, 3}, {P6_1, IRQ4, 4},
+ {P1_5, IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0, IRQ5, 6}, {P6_0, IRQ5, 6}, {P8_7, IRQ5, 4},
+ {P1_6, IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6},
+ {P1_7, IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2, IRQ7, 4}, {P2_13, IRQ7, 8},
+ {NC, NC, 0}
+#else
+ {P9_1, IRQ0, 4},
+ {P7_8, IRQ1, 8},
+ {P1_2, IRQ2, 4}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4},
+ {P1_3, IRQ3, 4}, {P1_9, IRQ3, 3},
+ {P1_4, IRQ4, 4}, {P1_10, IRQ4, 3},
+ {P1_5, IRQ5, 4}, {P1_11, IRQ5, 3},
+ {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6},
+ {NC, NC, 0}
+#endif
+};
+
+/************PINMAP***************/
+const PinFunc PIPC_0_tbl[] = {
+#ifdef MAX_PERI
+// pin func pm
+ {P4_0 , 2 , -1}, /* TIOC0A */
+ {P5_0 , 6 , -1}, /* TIOC0A */
+ {P7_0 , 7 , -1}, /* TIOC0A */
+ {P4_1 , 2 , -1}, /* TIOC0B */
+ {P5_1 , 6 , -1}, /* TIOC0B */
+ {P7_1 , 7 , -1}, /* TIOC0B */
+ {P4_2 , 2 , -1}, /* TIOC0C */
+ {P5_5 , 6 , -1}, /* TIOC0C */
+ {P7_2 , 7 , -1}, /* TIOC0C */
+ {P4_3 , 2 , -1}, /* TIOC0D */
+ {P5_7 , 6 , -1}, /* TIOC0D */
+ {P7_3 , 7 , -1}, /* TIOC0D */
+ {P2_11 , 5 , -1}, /* TIOC1A */
+ {P6_0 , 5 , -1}, /* TIOC1A */
+ {P7_4 , 7 , -1}, /* TIOC1A */
+ {P8_8 , 5 , -1}, /* TIOC1A */
+ {P9_7 , 4 , -1}, /* TIOC1A */
+ {P2_12 , 8 , -1}, /* TIOC1B */
+ {P5_2 , 6 , -1}, /* TIOC1B */
+ {P6_1 , 5 , -1}, /* TIOC1B */
+ {P7_5 , 7 , -1}, /* TIOC1B */
+ {P8_9 , 5 , -1}, /* TIOC1B */
+ {P2_1 , 6 , -1}, /* TIOC2A */
+ {P6_2 , 6 , -1}, /* TIOC2A */
+ {P7_6 , 7 , -1}, /* TIOC2A */
+ {P8_14 , 4 , -1}, /* TIOC2A */
+ {P2_2 , 6 , -1}, /* TIOC2B */
+ {P6_3 , 6 , -1}, /* TIOC2B */
+ {P7_7 , 7 , -1}, /* TIOC2B */
+ {P8_15 , 4 , -1}, /* TIOC2B */
+ {P3_4 , 6 , -1}, /* TIOC3A */
+ {P7_8 , 7 , -1}, /* TIOC3A */
+ {P8_10 , 4 , -1}, /* TIOC3A */
+ {P3_5 , 6 , -1}, /* TIOC3B */
+ {P7_9 , 7 , -1}, /* TIOC3B */
+ {P8_11 , 4 , -1}, /* TIOC3B */
+ {P3_6 , 6 , -1}, /* TIOC3C */
+ {P5_3 , 6 , -1}, /* TIOC3C */
+ {P7_10 , 7 , -1}, /* TIOC3C */
+ {P8_12 , 4 , -1}, /* TIOC3C */
+ {P3_7 , 6 , -1}, /* TIOC3D */
+ {P5_4 , 6 , -1}, /* TIOC3D */
+ {P7_11 , 7 , -1}, /* TIOC3D */
+ {P8_13 , 4 , -1}, /* TIOC3D */
+ {P3_8 , 6 , -1}, /* TIOC4A */
+ {P4_4 , 3 , -1}, /* TIOC4A */
+ {P7_12 , 7 , -1}, /* TIOC4A */
+ {P3_9 , 6 , -1}, /* TIOC4B */
+ {P4_5 , 3 , -1}, /* TIOC4B */
+ {P7_13 , 7 , -1}, /* TIOC4B */
+ {P3_10 , 6 , -1}, /* TIOC4C */
+ {P4_6 , 3 , -1}, /* TIOC4C */
+ {P7_14 , 7 , -1}, /* TIOC4C */
+ {P3_11 , 6 , -1}, /* TIOC4D */
+ {P4_7 , 3 , -1}, /* TIOC4D */
+ {P7_15 , 7 , -1}, /* TIOC4D */
+ {P5_7 , 1 , 1 }, /* TXOUT0M */
+ {P5_6 , 1 , 1 }, /* TXOUT0P */
+ {P5_5 , 1 , 1 }, /* TXOUT1M */
+ {P5_4 , 1 , 1 }, /* TXOUT1P */
+ {P5_3 , 1 , 1 }, /* TXOUT2M */
+ {P5_2 , 1 , 1 }, /* TXOUT2P */
+ {P5_1 , 1 , 1 }, /* TXCLKOUTM */
+ {P5_0 , 1 , 1 }, /* TXCLKOUTP */
+ {P2_11 , 4 , 0 }, /* SSITxD0 */
+ {P4_7 , 5 , 0 }, /* SSITxD0 */
+ {P7_4 , 6 , 0 }, /* SSITxD1 */
+ {P4_15 , 6 , 0 }, /* SSITxD3 */
+ {P7_11 , 2 , 0 }, /* SSITxD3 */
+ {P2_7 , 4 , 0 }, /* SSITxD5 */
+ {P4_11 , 5 , 0 }, /* SSITxD5 */
+ {P8_10 , 8 , 0 }, /* SSITxD5 */
+ {P3_7 , 8 , 0 }, /* WDTOVF */
+ {NC , 0 , -1}
+#else
+ // pin func pm
+ {P4_0 , 2 , -1}, // TIOC0A
+ {P5_0 , 6 , -1}, // TIOC0A
+ {P4_2 , 2 , -1}, // TIOC0C
+ {P5_5 , 6 , -1}, // TIOC0C
+ //
+ {P8_14 , 4 , -1}, // TIOC2A
+ //
+ {P8_10 , 4 , -1}, // TIOC3A
+ {P5_3 , 6 , -1}, // TIOC3C
+ {P8_12 , 4 , -1}, // TIOC3C
+ //
+ {P3_8 , 6 , -1}, // TIOC4A
+ {P4_4 , 3 , -1}, // TIOC4A
+ {P3_10 , 6 , -1}, // TIOC4C
+ {P4_6 , 3 , -1}, // TIOC4C
+ //
+ {P5_7 , 1 , 1 }, // TXOUT0M
+ {P5_6 , 1 , 1 }, // TXOUT0P
+ {P5_5 , 1 , 1 }, // TXOUT1M
+ {P5_4 , 1 , 1 }, // TXOUT1P
+ {P5_3 , 1 , 1 }, // TXOUT2M
+ {P5_2 , 1 , 1 }, // TXOUT2P
+ {P5_1 , 1 , 1 }, // TXCLKOUTM
+ {P5_0 , 1 , 1 }, // TXCLKOUTP
+ {P4_7 , 5 , 0 }, // SSITxD0
+ {P8_10 , 8 , 0 }, // SSITxD5
+ {P3_7 , 8 , 0 }, // WDTOVF
+ {NC , 0 , -1}
+#endif
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+#ifdef MAX_PERI
+ {P1_8, AN0, 1},
+ {P1_9, AN1, 1},
+ {P1_10, AN2, 1},
+ {P1_11, AN3, 1},
+ {P1_12, AN4, 1},
+ {P1_13, AN5, 1},
+ {P1_14, AN6, 1},
+ {P1_15, AN7, 1},
+ {NC, NC, 0}
+#else
+ {P1_8, AN0, 1},
+ {P1_9, AN1, 1},
+ {P1_10, AN2, 1},
+ {P1_11, AN3, 1},
+ {P1_12, AN4, 1},
+ {P1_13, AN5, 1},
+ {P1_15, AN7, 1},
+ {NC, NC, 0}
+#endif
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+ {P1_1 , I2C_0, 1},
+ {P1_3 , I2C_1, 1},
+ {P1_5 , I2C_2, 1},
+ {P1_7 , I2C_3, 1},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {P1_0 , I2C_0, 1},
+ {P1_2 , I2C_1, 1},
+ {P1_4 , I2C_2, 1},
+ {P1_6 , I2C_3, 1},
+ {NC , NC, 0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+#ifdef MAX_PERI
+ {P2_14 , UART0, 6},
+ {P4_9 , UART0, 7},
+ {P6_9 , UART0, 5},
+ {P2_5 , UART1, 6},
+ {P4_12 , UART1, 7},
+ {P6_12 , UART1, 5},
+ {P9_3 , UART1, 4},
+ {P3_0 , UART2, 6},
+ {P3_1 , UART2, 4},
+ {P4_2 , UART2, 5},
+ {P4_14 , UART2, 7},
+ {P6_3 , UART2, 7},
+ {P8_6 , UART2, 7},
+ {P3_5 , UART3, 7},
+ {P5_3 , UART3, 5},
+ {P6_1 , UART3, 7},
+ {P8_8 , UART3, 7},
+ {P5_0 , UART4, 5},
+ {P7_1 , UART4, 4},
+ {P8_14 , UART4, 7},
+ {P6_6 , UART5, 5},
+ {P8_1 , UART5, 4},
+ {P8_13 , UART5, 5},
+ {P5_6 , UART6, 5},
+ {P6_14 , UART6, 4},
+ {P7_4 , UART7, 4},
+ {NC , NC , 0}
+#else
+ {P3_0 , UART2, 6},
+ {P3_1 , UART2, 4},
+ {P4_2 , UART2, 5},
+ {P5_3 , UART3, 5},
+ {P8_8 , UART3, 7},
+ {P5_0 , UART4, 5},
+ {P8_14 , UART4, 7},
+ {P8_13 , UART5, 5},
+ {P5_6 , UART6, 5},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_UART_RX[] = {
+#ifdef MAX_PERI
+ {P2_15 , UART0, 6},
+ {P4_10 , UART0, 7},
+ {P6_10 , UART0, 5},
+ {P2_6 , UART1, 6},
+ {P4_13 , UART1, 7},
+ {P6_13 , UART1, 5},
+ {P9_4 , UART1, 4},
+ {P3_2 , UART2, 4},
+ {P4_3 , UART2, 5},
+ {P4_15 , UART2, 7},
+ {P6_2 , UART2, 7},
+ {P8_4 , UART2, 7},
+ {P3_6 , UART3, 7},
+ {P5_4 , UART3, 5},
+ {P6_0 , UART3, 7},
+ {P8_9 , UART3, 7},
+ {P5_1 , UART4, 5},
+ {P7_2 , UART4, 4},
+ {P8_15 , UART4, 7},
+ {P6_7 , UART5, 5},
+ {P8_2 , UART5, 4},
+ {P8_11 , UART5, 5},
+ {P5_7 , UART6, 5},
+ {P6_15 , UART6, 4},
+ {P7_5 , UART7, 4},
+ {NC , NC , 0}
+#else
+ {P3_2 , UART2, 4},
+ {P4_3 , UART2, 5},
+ {P5_4 , UART3, 5},
+ {P8_9 , UART3, 7},
+ {P5_1 , UART4, 5},
+ {P8_15 , UART4, 7},
+ {P8_11 , UART5, 5},
+ {P5_7 , UART6, 5},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_UART_CTS[] = {
+#ifdef MAX_PERI
+ {P2_3 , UART1, 6},
+ {P9_5 , UART1, 4},
+ {P6_3 , UART5, 5},
+ {P7_15 , UART5, 4},
+ {P7_6 , UART7, 4},
+ {NC , NC , 0}
+#else
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_UART_RTS[] = {
+#ifdef MAX_PERI
+ {P2_7 , UART1, 6},
+ {P9_6 , UART1, 4},
+ {P6_4 , UART5, 5},
+ {P8_3 , UART5, 4},
+ {P7_7 , UART7, 4},
+ {NC , NC , 0}
+#else
+ {NC , NC , 0}
+#endif
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+#ifdef MAX_PERI
+ {P2_12 , SPI_0, 2},
+ {P7_15 , SPI_0, 2},
+ {P4_4 , SPI_1, 2},
+ {P6_4 , SPI_1, 7},
+ {P8_3 , SPI_2, 3},
+ {P8_14 , SPI_2, 5},
+ {P3_0 , SPI_3, 8},
+ {P5_0 , SPI_3, 8},
+ {P2_8 , SPI_4, 8},
+ {P4_0 , SPI_4, 7},
+ {NC , NC , 0}
+#else
+ {P4_4 , SPI_1, 2},
+ {P8_14 , SPI_2, 5},
+ {P5_0 , SPI_3, 8},
+ {P4_0 , SPI_4, 7},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+#ifdef MAX_PERI
+ {P2_14 , SPI_0, 2},
+ {P8_1 , SPI_0, 2},
+ {P4_6 , SPI_1, 2},
+ {P6_6 , SPI_1, 7},
+ {P8_5 , SPI_2, 3},
+ {P9_0 , SPI_2, 5},
+ {P3_2 , SPI_3, 8},
+ {P5_2 , SPI_3, 8},
+ {P2_10 , SPI_4, 8},
+ {P4_2 , SPI_4, 7},
+ {NC , NC , 0}
+#else
+ {P4_6 , SPI_1, 2},
+ {P9_0 , SPI_2, 5},
+ {P5_2 , SPI_3, 8},
+ {P4_2 , SPI_4, 7},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+#ifdef MAX_PERI
+ {P2_15 , SPI_0, 2},
+ {P8_2 , SPI_0, 2},
+ {P4_7 , SPI_1, 2},
+ {P6_7 , SPI_1, 7},
+ {P8_6 , SPI_2, 3},
+ {P9_1 , SPI_2, 5},
+ {P3_3 , SPI_3, 8},
+ {P5_3 , SPI_3, 8},
+ {P2_11 , SPI_4, 8},
+ {P4_3 , SPI_4, 7},
+ {NC , NC , 0}
+#else
+ {P4_7 , SPI_1, 2},
+ {P9_1 , SPI_2, 5},
+ {P5_3 , SPI_3, 8},
+ {P4_3 , SPI_4, 7},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+#ifdef MAX_PERI
+ {P2_13 , SPI_0, 2},
+ {P8_0 , SPI_0, 2},
+ {P4_5 , SPI_1, 2},
+ {P6_5 , SPI_1, 7},
+ {P8_4 , SPI_2, 3},
+ {P8_15 , SPI_2, 5},
+ {P3_1 , SPI_3, 8},
+ {P5_1 , SPI_3, 8},
+ {P2_9 , SPI_4, 8},
+ {P4_1 , SPI_4, 7},
+ {NC , NC , 0}
+#else
+ {P4_5 , SPI_1, 2},
+ {P8_15 , SPI_2, 5},
+ {P5_1 , SPI_3, 8},
+ {P4_1 , SPI_4, 7},
+ {NC , NC , 0}
+#endif
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+#ifdef MAX_PERI
+ // TIOC0 A,C
+ {P4_0 , PWM_TIOC0A, 2}, //TIOC0A
+ {P5_0 , PWM_TIOC0A, 6}, //TIOC0A
+ {P7_0 , PWM_TIOC0A, 7}, //TIOC0A
+ {P4_2 , PWM_TIOC0C, 2}, //TIOC0C
+ {P5_5 , PWM_TIOC0C, 6}, //TIOC0C
+ {P7_2 , PWM_TIOC0C, 7}, //TIOC0C
+ //TIOC1 A
+ {P2_11 , PWM_TIOC1A, 5}, //TIOC1A
+ {P6_0 , PWM_TIOC1A, 5}, //TIOC1A
+ {P7_4 , PWM_TIOC1A, 7}, //TIOC1A
+ {P8_8 , PWM_TIOC1A, 5}, //TIOC1A
+ {P9_7 , PWM_TIOC1A, 4}, //TIOC1A
+ //TIOC2 A
+ {P2_1 , PWM_TIOC2A, 6}, //TIOC2A
+ {P6_2 , PWM_TIOC2A, 6}, //TIOC2A
+ {P7_6 , PWM_TIOC2A, 7}, //TIOC2A
+ {P8_14 , PWM_TIOC2A, 4}, //TIOC2A
+ //TIOC3 A,C
+ {P3_4 , PWM_TIOC3A, 6}, //TIOC3A
+ {P7_8 , PWM_TIOC3A, 7}, //TIOC3A
+ {P8_10 , PWM_TIOC3A, 4}, //TIOC3A
+ {P3_6 , PWM_TIOC3C, 6}, //TIOC3C
+ {P7_10 , PWM_TIOC3C, 7}, //TIOC3C
+ {P8_12 , PWM_TIOC3C, 4}, //TIOC3C
+ //TIOC4 A,C
+ {P3_8 , PWM_TIOC4A, 6}, //TIOC4A
+ {P4_4 , PWM_TIOC4A, 3}, //TIOC4A
+ {P7_12 , PWM_TIOC4A, 7}, //TIOC4A
+ {P3_10 , PWM_TIOC4C, 6}, //TIOC4C
+ {P4_6 , PWM_TIOC4C, 3}, //TIOC4C
+ {P7_14 , PWM_TIOC4C, 7}, //TIOC4C
+ //PWM1
+ {P8_8 , PWM_PWM1A , 6}, //PWM1A
+ {P8_9 , PWM_PWM1B , 6}, //PWM1B
+ {P8_10 , PWM_PWM1C , 6}, //PWM1C
+ {P8_11 , PWM_PWM1D , 6}, //PWM1D
+ {P8_12 , PWM_PWM1E , 6}, //PWM1E
+ {P8_13 , PWM_PWM1F , 6}, //PWM1F
+ {P8_14 , PWM_PWM1G , 6}, //PWM1G
+ {P8_15 , PWM_PWM1H , 6}, //PWM1H
+ //PWM2
+ {P3_0 , PWM_PWM2A , 7}, //PWM2A
+ {P3_1 , PWM_PWM2B , 7}, //PWM2B
+ {P3_2 , PWM_PWM2C , 7}, //PWM2C
+ {P3_3 , PWM_PWM2D , 7}, //PWM2D
+ {P4_4 , PWM_PWM2E , 4}, //PWM2E
+ {P4_5 , PWM_PWM2F , 4}, //PWM2F
+ {P4_6 , PWM_PWM2G , 4}, //PWM2G
+ {P4_7 , PWM_PWM2H , 4}, //PWM2H
+ {NC , NC , 0}
+#else
+ //TIOC0 A,C
+ {P4_0 , PWM_TIOC0A, 2}, //TIOC0A
+ {P5_0 , PWM_TIOC0A, 6}, //TIOC0A
+ {P4_2 , PWM_TIOC0C, 2}, //TIOC0C
+ {P5_5 , PWM_TIOC0C, 6}, //TIOC0C
+ //TIOC2 A
+ {P8_14 , PWM_TIOC2A, 4}, //TIOC2A
+ //TIOC3 A,C
+ {P8_10 , PWM_TIOC3A, 4}, //TIOC3A
+ {P5_3 , PWM_TIOC3C, 6}, //TIOC3C
+ {P8_12 , PWM_TIOC3C, 4}, //TIOC3C
+ //TIOC4 A,C
+ {P3_8 , PWM_TIOC4A, 6}, //TIOC4A
+ {P4_4 , PWM_TIOC4A, 3}, //TIOC4A
+ {P3_10 , PWM_TIOC4C, 6}, //TIOC4C
+ {P4_6 , PWM_TIOC4C, 3}, //TIOC4C
+ //PWM1
+ {P8_10 , PWM_PWM1C , 6}, //PWM1C
+ {P8_11 , PWM_PWM1D , 6}, //PWM1D
+ {P8_12 , PWM_PWM1E , 6}, //PWM1E
+ {P8_13 , PWM_PWM1F , 6}, //PWM1F
+ {P8_14 , PWM_PWM1G , 6}, //PWM1G
+ {P8_15 , PWM_PWM1H , 6}, //PWM1H
+ //PWM2
+ {P3_0 , PWM_PWM2A , 7}, //PWM2A
+ {P3_1 , PWM_PWM2B , 7}, //PWM2B
+ {P3_2 , PWM_PWM2C , 7}, //PWM2C
+ {P4_4 , PWM_PWM2E , 4}, //PWM2E
+ {P4_5 , PWM_PWM2F , 4}, //PWM2F
+ {P4_6 , PWM_PWM2G , 4}, //PWM2G
+ {P4_7 , PWM_PWM2H , 4}, //PWM2H
+ {NC , NC , 0}
+#endif
+};
+
+/************CAN***************/
+const PinMap PinMap_CAN_RD[] = {
+#ifdef MAX_PERI
+ {P7_8 , CAN_0, 4},
+ {P9_1 , CAN_0, 3},
+ {P1_4 , CAN_1, 3},
+ {P5_9 , CAN_1, 5},
+ {P7_11 , CAN_1, 4},
+ {P4_9 , CAN_2, 6},
+ {P6_4 , CAN_2, 3},
+ {P7_2 , CAN_2, 5},
+ {P2_12 , CAN_3, 5},
+ {P4_2 , CAN_3, 4},
+ {P1_5 , CAN_4, 3},
+ {P2_14 , CAN_4, 5},
+ {NC , NC , 0}
+#else
+ {P9_1 , CAN_0, 3},
+ {P1_4 , CAN_1, 3},
+ {P5_9 , CAN_1, 5},
+ {P4_2 , CAN_3, 4},
+ {P1_5 , CAN_4, 3},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_CAN_TD[] = {
+#ifdef MAX_PERI
+ {P7_9 , CAN_0, 4},
+ {P9_0 , CAN_0, 3},
+ {P5_10 , CAN_1, 5},
+ {P7_10 , CAN_1, 4},
+ {P4_8 , CAN_2, 6},
+ {P6_5 , CAN_2, 3},
+ {P7_3 , CAN_2, 5},
+ {P2_13 , CAN_3, 5},
+ {P4_3 , CAN_3, 4},
+ {P4_11 , CAN_4, 6},
+ {P8_10 , CAN_4, 5},
+ {NC , NC , 0}
+#else
+ {P9_0 , CAN_0, 3},
+ {P5_10 , CAN_1, 5},
+ {P4_3 , CAN_3, 4},
+ {P8_10 , CAN_4, 5},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_SDHI_D0[] = {
+ {P4_11 , SDHI_0, 3},
+ {P3_11 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_D1[] = {
+ {P4_10 , SDHI_0, 3},
+ {P3_10 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_D2[] = {
+ {P4_15 , SDHI_0, 3},
+ {P3_15 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_D3[] = {
+ {P4_14 , SDHI_0, 3},
+ {P3_14 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_CLK[] = {
+ {P4_12 , SDHI_0, 3},
+ {P3_12 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_CMD[] = {
+ {P4_13 , SDHI_0, 3},
+ {P3_13 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_CD[] = {
+ {P4_8 , SDHI_0, 3},
+ {P3_8 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_WP[] = {
+ {P4_9 , SDHI_0, 3},
+ {P3_9 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
Binary file mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/SDHI_driver/TOOLCHAIN_ARM_STD/lib_RZ_A1H_sd_driver.ar has changed
Binary file mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/SDHI_driver/TOOLCHAIN_GCC_ARM/lib_RZ_A1H_sd_driver.a has changed
Binary file mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/SDHI_driver/TOOLCHAIN_IAR/lib_RZ_A1H_sd_driver.a has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/SDHI_driver/sd_cfg.h Mon Mar 18 16:54:40 2019 +0000 @@ -0,0 +1,371 @@ +/****************************************************************************** +* DISCLAIMER +* +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. +* +* This software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES +* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, +* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY +* DISCLAIMED. +* +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES +* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS +* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Renesas reserves the right, without notice, to make changes to this +* software and to discontinue the availability of this software. +* By using this software, you agree to the additional terms and +* conditions found by accessing the following link: +* http://www.renesas.com/disclaimer +******************************************************************************** +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +**************************** Technical reference data ************************** +* System Name : SD Driver Sample Program +* File Name : sd_cfg.h +* Abstract : SD Memory card driver configration +* Version : 4.00.00 +* Device : Aragon +* Tool-Chain : DS-5 Ver 5.13 +* ARM Complier +* OS : None +* H/W Platform: +* Description : +******************************************************************************** +* History : 2013.05.30 Ver.4.00.00 +*******************************************************************************/ +#ifndef _SD_CFG_H_ +#define _SD_CFG_H_ + +/* ------------------------------------------------------ + Set SDHI Base Address +--------------------------------------------------------*/ +#define SDCFG_IP0_BASE 0xE804E000 +#define SDCFG_IP1_BASE 0xE804E800 + +/* ------------------------------------------------------ + Set the method of check SD Status +--------------------------------------------------------*/ +#define SDCFG_HWINT +//#define SDCFG_POLL + +/* ------------------------------------------------------ + Set the method of data transfer +--------------------------------------------------------*/ +//#define SDCFG_TRNS_DMA +#define SDCFG_TRNS_SW + + #ifdef SDCFG_TRNS_DMA +#define SDCFG_TRANS_DMA_64 + #endif + +/* ------------------------------------------------------ + Set the card type to support +--------------------------------------------------------*/ +#define SDCFG_MEM +//#define SDCFG_IO + +/* ------------------------------------------------------ + Set the speed to support +--------------------------------------------------------*/ +//#define SDCFG_DS +#define SDCFG_HS + +/* ------------------------------------------------------ + Set the version to support +--------------------------------------------------------*/ +//#define SDCFG_VER1X /* Version 1.1 */ +#define SDCFG_VER2X /* Version 2.x */ + +/* ------------------------------------------------------ + Set the method to detect card +--------------------------------------------------------*/ +//#define SDCFG_CD_INT + +#ifdef SDCFG_CD_INT + #ifndef SDCFG_HWINT + #error please define SDCFG_HWINT + #endif +#endif + +/* ------------------------------------------------------ + Set the SD bus width +--------------------------------------------------------*/ +//#define SDCFG_SDMODE_1BIT + + + + +/* ==== end of the setting ==== */ + + #if defined(SDCFG_SDMODE_1BIT) +#if defined(SDCFG_HWINT) + #if defined(SDCFG_TRNS_DMA) + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #endif + #else + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #endif + #endif +#else + #if defined(SDCFG_TRNS_DMA) + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #endif + #else + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #endif + #endif +#endif + #else +#if defined(SDCFG_HWINT) + #if defined(SDCFG_TRNS_DMA) + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #endif + #else + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #endif + #endif +#else + #if defined(SDCFG_TRNS_DMA) + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #endif + #else + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #endif + #endif +#endif + #endif + + #ifdef SDCFG_TRANS_DMA_64 +#define SDCFG_DRIVER_MODE (SDCFG_DRIVER_MODE2 | SD_MODE_DMA_64) + #else +#define SDCFG_DRIVER_MODE SDCFG_DRIVER_MODE2 + #endif + + +#endif /* _SD_CFG_H_ */ + +/* End of File */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/SDHI_driver/sdhi_low.c Mon Mar 18 16:54:40 2019 +0000
@@ -0,0 +1,1055 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : sd_dev_low.c
+* $Rev: $
+* $Date:: $
+* Device(s) : RZ/A1H
+* Tool-Chain : DS-5 Ver 5.8
+* : ARM Complier
+* OS :
+* H/W Platform : RZ/A1H CPU Board
+* Description : RZ/A1H SD Driver Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stdio.h>
+#include <string.h>
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+/*#include "devdrv_intc.h"*/
+#include "sdif.h"
+#include "sd_cfg.h"
+/*#include "sd_dev_dmacdrv.h"*/
+#include "us_ticker_api.h"
+#include "cmsis_os2.h"
+#include "mbed_assert.h"
+#include "pinmap.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+//#define MTU_TIMER_CNT 32 /* P-phy = 32MHz */
+#define INT_LEVEL_SDHI 10 /* SDHI interrupt level */
+#define SDHI_PINS_COMMON 2
+#define SDHI_PINS_SERIAL 3
+#define SDHI_PINS_PARALLEL 6
+
+#if defined(SDCFG_SDMODE_1BIT)
+# define SDHI_PORT_MODE SD_PORT_SERIAL
+#else
+# define SDHI_PORT_MODE SD_PORT_PARALLEL
+#endif
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+#if 0
+static uint8_t g_sdhi_priority_backup;
+#endif
+
+
+
+static const PinName SDHIpin_Common[SDHI_COUNT][SDHI_PINS_COMMON] = { /* WP & CD */
+ {P4_8, P4_9},
+ {P3_8, P3_9}
+};
+
+static const PinName SDHIpin_serial[SDHI_COUNT][SDHI_PINS_SERIAL] = { /* CLK CMD D0 */
+ {P4_11, P4_12, P4_13},
+ {P3_11, P3_12, P3_13}
+};
+
+static const PinName SDHIpin_parallel[SDHI_COUNT][SDHI_PINS_PARALLEL] = { /* CLK CMD D0-D3 */
+ {P4_10, P4_11, P4_12, P4_13, P4_14, P4_15},
+ {P3_10, P3_11, P3_12, P3_13, P3_14, P3_15}
+};
+
+
+static const PinMap PinMap_SDHI_PIN[] = {
+ /* pin | periph| func */
+ {P4_8 , SDHI_0, 3}, /* SD_CD_0 */
+ {P4_9 , SDHI_0, 3}, /* SD_WP_0 */
+ {P4_10 , SDHI_0, 3}, /* SD_D1_0 */
+ {P4_11 , SDHI_0, 3}, /* SD_D0_0 */
+ {P4_12 , SDHI_0, 3}, /* SD_CLK_0 */
+ {P4_13 , SDHI_0, 3}, /* SD_CMD_0 */
+ {P4_14 , SDHI_0, 3}, /* SD_D3_0 */
+ {P4_15 , SDHI_0, 3}, /* SD_D2_0 */
+ /*----------------*/
+ {P3_8 , SDHI_1, 7}, /* SD_CD_1 */
+ {P3_9 , SDHI_1, 7}, /* SD_WP_1 */
+ {P3_10 , SDHI_1, 7}, /* SD_D1_1 */
+ {P3_11 , SDHI_1, 7}, /* SD_D0_1 */
+ {P3_12 , SDHI_1, 7}, /* SD_CLK_1 */
+ {P3_13 , SDHI_1, 7}, /* SD_CMD_1 */
+ {P3_14 , SDHI_1, 7}, /* SD_D3_1 */
+ {P3_15 , SDHI_1, 7}, /* SD_D2_1 */
+ {NC , NC , 0}
+};
+
+
+
+static unsigned long _ulStart = 0;
+static unsigned long _ulDelta = 0;
+static const ticker_data_t *_ticker;
+
+//static int sddev_init_0(void);
+//static int sddev_init_1(void);
+//static int sddev_set_port_0(int mode);
+//static int sddev_set_port_1(int mode);
+
+static int sddev_init_dma_0(unsigned long buff,unsigned long reg,long cnt,int dir);
+static int sddev_init_dma_1(unsigned long buff,unsigned long reg,long cnt,int dir);
+
+static int sddev_wait_dma_end_0(long cnt);
+static int sddev_wait_dma_end_1(long cnt);
+
+static int sddev_disable_dma_0(void);
+static int sddev_disable_dma_1(void);
+
+static void sddev_sd_int_handler_0(uint32_t int_sense);
+static void sddev_sd_int_handler_1(uint32_t int_sense);
+static void sddev_sdio_int_handler_0(uint32_t int_sense);
+static void sddev_sdio_int_handler_1(uint32_t int_sense);
+static void sddev_start_timer(int msec);
+static void sddev_end_timer(void);
+static int sddev_check_timer(void);
+
+/******************************************************************************
+* Function Name: int sddev_cmd0_sdio_mount(int sd_port);
+* Description : Select to issue CMD0 before SDIO Mount
+* Arguments : none
+* Return Value : SD_OK : issue CMD0
+* : SD_ERR : not issue CMD0
+******************************************************************************/
+int sddev_cmd0_sdio_mount(int sd_port)
+{
+#ifdef SDCFG_IO
+ return SD_ERR;
+#else
+ return SD_ERR;
+#endif
+}
+
+/******************************************************************************
+* Function Name: int sddev_cmd8_sdio_mount(int sd_port);
+* Description : Select to issue CMD8 before SDIO Mount
+* Arguments : none
+* Return Value : SD_OK : issue CMD8
+* : SD_ERR : not issue CMD8
+******************************************************************************/
+int sddev_cmd8_sdio_mount(int sd_port)
+{
+#ifdef SDCFG_IO
+ return SD_OK;
+#else
+ return SD_ERR;
+#endif
+}
+
+
+
+/******************************************************************************
+* Function Name: int sddev_init(void);
+* Description : Initialize H/W to use SDHI
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_init(int sd_port)
+{
+ if ( sd_port >= SDHI_COUNT )
+ return SD_ERR;
+
+
+ volatile uint8_t dummy_buf;
+
+ CPG.STBCR12 = 0xF0u; /* [1], [1], [1], [1], SDHI00, SDHI01, SDHI10, SDHI11 */
+ dummy_buf = CPG.STBCR12; /* (Dummy read) */
+
+
+ for( uint32_t no=0; no < SDHI_PINS_COMMON; no++ )
+ {
+ if ( pinmap_peripheral(SDHIpin_Common[sd_port][no], PinMap_SDHI_PIN ) != sd_port)
+ {
+ return SD_ERR;
+ }
+ pinmap_pinout(SDHIpin_Common[sd_port][no], PinMap_SDHI_PIN);
+ }
+
+ sddev_set_port(sd_port, SDHI_PORT_MODE);
+
+#ifdef SDCFG_HWINT
+ if ( sd_port == (uint32_t)SDHI_0 )
+ {
+ InterruptHandlerRegister(SDHI0_0_IRQn, sddev_sd_int_handler_0);
+ GIC_SetPriority(SDHI0_0_IRQn, INT_LEVEL_SDHI);
+ GIC_EnableIRQ(SDHI0_0_IRQn);
+
+ InterruptHandlerRegister(SDHI0_3_IRQn, sddev_sd_int_handler_0);
+ GIC_SetPriority(SDHI0_3_IRQn, INT_LEVEL_SDHI);
+ GIC_EnableIRQ(SDHI0_3_IRQn);
+
+ InterruptHandlerRegister(SDHI0_1_IRQn, sddev_sdio_int_handler_0);
+ GIC_SetPriority(SDHI0_1_IRQn, INT_LEVEL_SDHI);
+ GIC_EnableIRQ(SDHI0_1_IRQn);
+ }
+ else if ( sd_port == (uint32_t)SDHI_1 )
+ {
+ InterruptHandlerRegister(SDHI1_0_IRQn, sddev_sd_int_handler_1);
+ GIC_SetPriority(SDHI1_0_IRQn, INT_LEVEL_SDHI);
+ GIC_EnableIRQ(SDHI1_0_IRQn);
+
+ InterruptHandlerRegister(SDHI1_3_IRQn, sddev_sd_int_handler_1);
+ GIC_SetPriority(SDHI1_3_IRQn, INT_LEVEL_SDHI);
+ GIC_EnableIRQ(SDHI1_3_IRQn);
+
+ InterruptHandlerRegister(SDHI1_1_IRQn, sddev_sdio_int_handler_1);
+ GIC_SetPriority(SDHI1_1_IRQn, INT_LEVEL_SDHI);
+ GIC_EnableIRQ(SDHI1_1_IRQn);
+ }
+#endif
+
+ /* ---- wait card detect ---- */
+ osDelay(1000); /* wait 1s */
+
+ return SD_OK;
+}
+
+
+/******************************************************************************
+* Function Name: int sddev_power_on(int sd_port);
+* Description : Power-on H/W to use SDHI
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_power_on(int sd_port)
+{
+ /* ---Power On SD ---- */
+
+ /* ---- Wait for SD Wake up ---- */
+ osDelay(100); /* wait 100ms */
+
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_power_off(int sd_port);
+* Description : Power-off H/W to use SDHI
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_power_off(int sd_port)
+{
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_read_data(int sd_port, unsigned char *buff,unsigned long reg_addr,long num);
+* Description : read from SDHI buffer FIFO
+* Arguments : unsigned char *buff : buffer addrees to store reading datas
+* : unsigned long reg_addr : SDIP FIFO address
+* : long num : counts to read(unit:byte)
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_read_data(int sd_port, unsigned char *buff,unsigned long reg_addr,long num)
+{
+ long i;
+ long cnt;
+ unsigned long *reg;
+ unsigned long *ptr_l;
+ unsigned char *ptr_c;
+ unsigned long tmp;
+
+ reg = (unsigned long *)(reg_addr);
+
+ cnt = (num / 4);
+ if(((unsigned long)buff & 0x3) != 0)
+ {
+ ptr_c = (unsigned char *)buff;
+ for(i = cnt; i > 0 ; i--)
+ {
+ tmp = *reg;
+ *ptr_c++ = (unsigned char)(tmp);
+ *ptr_c++ = (unsigned char)(tmp >> 8);
+ *ptr_c++ = (unsigned char)(tmp >> 16);
+ *ptr_c++ = (unsigned char)(tmp >> 24);
+ }
+
+ cnt = (num % 4);
+ if( cnt != 0 )
+ {
+ tmp = *reg;
+ for(i = cnt; i > 0 ; i--)
+ {
+ *ptr_c++ = (unsigned char)(tmp);
+ tmp >>= 8;
+ }
+ }
+ }
+ else
+ {
+ ptr_l = (unsigned long *)buff;
+ for(i = cnt; i > 0 ; i--)
+ {
+ *ptr_l++ = *reg;
+ }
+
+ cnt = (num % 4);
+ if( cnt != 0 )
+ {
+ ptr_c = (unsigned char *)ptr_l;
+ tmp = *reg;
+ for(i = cnt; i > 0 ; i--)
+ {
+ *ptr_c++ = (unsigned char)(tmp);
+ tmp >>= 8;
+ }
+ }
+ }
+
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_write_data(int sd_port, unsigned char *buff,unsigned long reg_addr,long num);
+* Description : write to SDHI buffer FIFO
+* Arguments : unsigned char *buff : buffer addrees to store writting datas
+* : unsigned long reg_addr : SDIP FIFO address
+* : long num : counts to write(unit:byte)
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_write_data(int sd_port, unsigned char *buff,unsigned long reg_addr,long num)
+{
+ long i;
+ unsigned long *reg = (unsigned long *)(reg_addr);
+ unsigned long *ptr = (unsigned long *)buff;
+ unsigned long tmp;
+
+ /* dont care non 4byte allignment data */
+ num += 3;
+ num /= 4;
+ if(((unsigned long)buff & 0x3) != 0)
+ {
+ for(i = num; i > 0 ; i--)
+ {
+ tmp = *buff++ ;
+ tmp |= *buff++ << 8;
+ tmp |= *buff++ << 16;
+ tmp |= *buff++ << 24;
+ *reg = tmp;
+ }
+ }
+ else
+ {
+ for(i = num; i > 0 ; i--)
+ {
+ *reg = *ptr++;
+ }
+ }
+
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: unsigned int sddev_get_clockdiv(int sd_port, int clock);
+* Description : write to SDHI buffer FIFO
+* Arguments : int clock : request clock frequency
+* : SD_CLK_50MHz
+* : SD_CLK_25MHz
+* : SD_CLK_20MHz
+* : SD_CLK_10MHz
+* : SD_CLK_5MHz
+* : SD_CLK_1MHz
+* : SD_CLK_400kHz
+* Return Value : clock div value
+* : SD_DIV_2 : 1/2 clock
+* : SD_DIV_2 : 1/4 clock
+* : SD_DIV_2 : 1/8 clock
+* : SD_DIV_2 : 1/16 clock
+* : SD_DIV_2 : 1/128 clock
+* : SD_DIV_2 : 1/256 clock
+******************************************************************************/
+unsigned int sddev_get_clockdiv(int sd_port, int clock)
+{
+ unsigned int div;
+
+ switch(clock)
+ {
+ case SD_CLK_50MHz:
+ div = SD_DIV_2; /* 64MHz/2 = 32MHz */
+ break;
+ case SD_CLK_25MHz:
+ div = SD_DIV_4; /* 64MHz/4 = 16MHz */
+ break;
+ case SD_CLK_20MHz:
+ div = SD_DIV_4; /* 64MHz/4 = 16MHz */
+ break;
+ case SD_CLK_10MHz:
+ div = SD_DIV_8; /* 64MHz/8 = 8MHz */
+ break;
+ case SD_CLK_5MHz:
+ div = SD_DIV_16; /* 64MHz/16 = 4MHz */
+ break;
+ case SD_CLK_1MHz:
+ div = SD_DIV_128; /* 64MHz/128 = 512kHz */
+ break;
+ case SD_CLK_400kHz:
+ div = SD_DIV_256; /* 64MHz/256 = 256kHz */
+ break;
+ default:
+ div = SD_DIV_256;
+ break;
+ }
+
+ return div;
+}
+
+/******************************************************************************
+* Function Name: int sddev_set_port(int sd_port, int mode);
+* Description : setting ports to use MMCHI
+* Arguments : int mode : SD_PORT_PARALLEL : 4bit mode
+* : SD_PORT_SERIAL : 1bit mode
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_set_port(int sd_port, int mode)
+{
+ if ( sd_port >= SDHI_COUNT)
+ return SD_ERR;
+
+ if(mode == SD_PORT_SERIAL)
+ {
+ for( uint32_t no=0; no < SDHI_PINS_SERIAL; no++ )
+ {
+ if ( pinmap_peripheral(SDHIpin_serial[sd_port][no], PinMap_SDHI_PIN ) != sd_port)
+ {
+ return SD_ERR;
+ }
+ pinmap_pinout(SDHIpin_serial[sd_port][no], PinMap_SDHI_PIN);
+ }
+ }
+ else if( mode == SD_PORT_PARALLEL )
+ {
+ for( uint32_t no=0; no < SDHI_PINS_PARALLEL; no++ )
+ {
+ if ( pinmap_peripheral(SDHIpin_parallel[sd_port][no], PinMap_SDHI_PIN ) != sd_port)
+ {
+ return SD_ERR;
+ }
+ pinmap_pinout(SDHIpin_parallel[sd_port][no], PinMap_SDHI_PIN);
+ }
+ }
+ else
+ {
+ return SD_ERR;
+ }
+
+ return SD_OK;
+}
+
+
+/******************************************************************************
+* Function Name: int sddev_int_wait(int sd_port, int time);
+* Description : Waitting for SDHI Interrupt
+* Arguments : int time : time out value to wait interrupt
+* Return Value : get interrupt : SD_OK
+* : time out : SD_ERR
+******************************************************************************/
+int sddev_int_wait(int sd_port, int time)
+{
+ sddev_start_timer(time);
+ while( sddev_check_timer() == SD_OK )
+ {
+ /* interrupt generated? */
+ if(sd_check_int(sd_port) == SD_OK)
+ {
+ sddev_end_timer();
+ return SD_OK;
+ }
+ }
+
+ sddev_end_timer();
+
+ return SD_ERR;
+}
+
+/******************************************************************************
+* Function Name: int sddev_init_dma(unsigned long buff,unsigned long reg,long cnt,int dir);
+* Description : Initialize DMAC to transfer data from SDHI FIFO
+* Arguments : unsigned long buff : buffer addrees to transfer datas
+* : unsigned long reg : SDIP FIFO address
+* : long cnt : counts to transfer(unit:byte)
+* : int dir : direction to transfer
+* : : 0 : FIFO -> buffer
+* : : 1 : buffer -> FIFO
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_init_dma(int sd_port, unsigned long buff,unsigned long reg,long cnt,int dir)
+{
+ int ret;
+
+ if( sd_port == 0 )
+ {
+ ret = sddev_init_dma_0(buff, reg, cnt, dir);
+ }
+ else if( sd_port == 1 )
+ {
+ ret = sddev_init_dma_1(buff, reg, cnt, dir);
+ }
+
+ return ret;
+}
+
+/******************************************************************************
+* Function Name: static int sddev_init_dma_0(unsigned long buff,unsigned long reg,long cnt,int dir);
+* Description : Initialize DMAC to transfer data from SDHI FIFO
+* Arguments : unsigned long buff : buffer addrees to transfer datas
+* : unsigned long reg : SDIP FIFO address
+* : long cnt : counts to transfer(unit:byte)
+* : int dir : direction to transfer
+* : : 0 : FIFO -> buffer
+* : : 1 : buffer -> FIFO
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+static int sddev_init_dma_0(unsigned long buff,unsigned long reg,long cnt,int dir)
+{
+#ifdef SDCFG_TRNS_DMA
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor;
+ int32_t ret;
+
+ trans_info.count = (uint32_t)cnt;
+ #ifdef SDCFG_TRANS_DMA_64
+ if( (cnt % 64) != 0 )
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32;
+ trans_info.dst_size = DMAC_TRANS_SIZE_32;
+ if( reg & 0x0000003f )
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32;
+ trans_info.dst_size = DMAC_TRANS_SIZE_32;
+ }
+ }
+ else
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_512;
+ trans_info.dst_size = DMAC_TRANS_SIZE_512;
+ }
+ #else
+ trans_info.src_size = DMAC_TRANS_SIZE_32;
+ trans_info.dst_size = DMAC_TRANS_SIZE_32;
+ #endif
+
+ if( dir == 0 )
+ {
+ request_factor = DMAC_REQ_SDHI_0_RX;
+ trans_info.src_addr = (uint32_t)reg;
+ trans_info.dst_addr = (uint32_t)buff;
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC;
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC;
+ }
+ else if( dir == 1 )
+ {
+ request_factor = DMAC_REQ_SDHI_0_TX;
+ trans_info.src_addr = (uint32_t)buff;
+ trans_info.dst_addr = (uint32_t)reg;
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC;
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC;
+ }
+
+ sd_DMAC1_PeriReqInit( (const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0 ); /* Dont care DMAC_REQ_REQD is setting in usb0_host_DMAC1_PeriReqInit() */
+
+ ret = sd_DMAC1_Open(DMAC_REQ_MODE_PERI);
+ if( ret != 0 )
+ {
+ printf("DMAC1 Open error!!\n");
+ return SD_ERR;
+ }
+#endif
+
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: static int sddev_init_dma_1(unsigned long buff,unsigned long reg,long cnt,int dir);
+* Description : Initialize DMAC to transfer data from SDHI FIFO
+* Arguments : unsigned long buff : buffer address to transfer datas
+* : unsigned long reg : SDIP FIFO address
+* : long cnt : counts to transfer(unit:byte)
+* : int dir : direction to transfer
+* : : 0 : FIFO -> buffer
+* : : 1 : buffer -> FIFO
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+static int sddev_init_dma_1(unsigned long buff,unsigned long reg,long cnt,int dir)
+{
+#ifdef SDCFG_TRNS_DMA
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor;
+ int32_t ret;
+
+ trans_info.count = (uint32_t)cnt;
+ #ifdef SDCFG_TRANS_DMA_64
+ if( (cnt % 64) != 0 )
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32;
+ trans_info.dst_size = DMAC_TRANS_SIZE_32;
+ if( reg & 0x0000003f )
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32;
+ trans_info.dst_size = DMAC_TRANS_SIZE_32;
+ }
+ }
+ else
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_512;
+ trans_info.dst_size = DMAC_TRANS_SIZE_512;
+ }
+ #else
+ trans_info.src_size = DMAC_TRANS_SIZE_32;
+ trans_info.dst_size = DMAC_TRANS_SIZE_32;
+ #endif
+
+ if( dir == 0 )
+ {
+ request_factor = DMAC_REQ_SDHI_1_RX;
+ trans_info.src_addr = (uint32_t)reg;
+ trans_info.dst_addr = (uint32_t)buff;
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC;
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC;
+ }
+ else if( dir == 1 )
+ {
+ request_factor = DMAC_REQ_SDHI_1_TX;
+ trans_info.src_addr = (uint32_t)buff;
+ trans_info.dst_addr = (uint32_t)reg;
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC;
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC;
+ }
+
+ sd_DMAC2_PeriReqInit( (const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0 ); /* Dont care DMAC_REQ_REQD is setting in usb0_host_DMAC1_PeriReqInit() */
+
+ ret = sd_DMAC2_Open(DMAC_REQ_MODE_PERI);
+ if( ret != 0 )
+ {
+ printf("DMAC1 Open error!!\n");
+ return SD_ERR;
+ }
+#endif
+
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_wait_dma_end(int sd_port, long cnt);
+* Description : Wait to complete DMAC transfer
+* Arguments : long cnt : counts to transfer(unit:byte)
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_wait_dma_end(int sd_port, long cnt)
+{
+ int ret;
+
+ if( sd_port == 0 )
+ {
+ ret = sddev_wait_dma_end_0(cnt);
+ }
+ else if( sd_port == 1 )
+ {
+ ret = sddev_wait_dma_end_1(cnt);
+ }
+
+ return ret;
+}
+
+/******************************************************************************
+* Function Name: static int sddev_wait_dma_end_0(long cnt);
+* Description : Wait to complete DMAC transfer
+* Arguments : long cnt : counts to transfer(unit:byte)
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+static int sddev_wait_dma_end_0(long cnt)
+{
+#ifdef SDCFG_TRNS_DMA
+ int loop;
+ int time;
+
+ time = (cnt / 512);
+ time = ((time * 1000) / 1024);
+ if(time < 1000)
+ {
+ time = 1000;
+ }
+
+ if(time > (0x0000ffff / MTU_TIMER_CNT))
+ {
+ /* @1000ms */
+ loop = (time / 1000);
+ if( (time % 1000) != 0 )
+ {
+ loop++;
+ }
+ time = 1000;
+ }
+ else
+ {
+ loop = 1;
+ }
+
+ do{
+ sddev_start_timer(time);
+
+ while(1)
+ {
+ /* get end flag? */
+ if( sd_DMAC1_Get_Endflag() == 1 )
+ {
+ sddev_end_timer();
+ return SD_OK;
+ }
+ /* detect timeout? */
+ if(sddev_check_timer() == SD_ERR)
+ {
+ break;
+ }
+ }
+
+ loop--;
+ if( loop <= 0 )
+ {
+ break;
+ }
+
+ } while(1);
+
+ sddev_end_timer();
+
+ return SD_ERR;
+#else
+ return SD_OK;
+
+#endif
+}
+
+/******************************************************************************
+* Function Name: static int sddev_wait_dma_end_1(long cnt);
+* Description : Wait to complete DMAC transfer
+* Arguments : long cnt : counts to transfer(unit:byte)
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+static int sddev_wait_dma_end_1(long cnt)
+{
+#ifdef SDCFG_TRNS_DMA
+ int loop;
+ int time;
+
+ time = (cnt / 512);
+ time = ((time * 1000) / 1024);
+ if(time < 1000)
+ {
+ time = 1000;
+ }
+
+ if(time > (0x0000ffff / MTU_TIMER_CNT))
+ {
+ /* @1000ms */
+ loop = (time / 1000);
+ if( (time % 1000) != 0 )
+ {
+ loop++;
+ }
+ time = 1000;
+ }
+ else
+ {
+ loop = 1;
+ }
+
+ do{
+ sddev_start_timer(time);
+
+ while(1)
+ {
+ /* get end flag? */
+ if( sd_DMAC2_Get_Endflag() == 1 )
+ {
+ sddev_end_timer();
+ return SD_OK;
+ }
+ /* detect timeout? */
+ if(sddev_check_timer() == SD_ERR)
+ {
+ break;
+ }
+ }
+
+ loop--;
+ if( loop <= 0 )
+ {
+ break;
+ }
+
+ } while(1);
+
+ sddev_end_timer();
+
+ return SD_ERR;
+#else
+ return SD_OK;
+
+#endif
+}
+
+/******************************************************************************
+* Function Name: int sddev_disable_dma(int sd_port);
+* Description : Disable DMAC transfer
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_disable_dma(int sd_port)
+{
+ int ret;
+
+ if( sd_port == 0 )
+ {
+ ret = sddev_disable_dma_0();
+ }
+ else
+ {
+ ret = sddev_disable_dma_1();
+ }
+ return ret;
+}
+
+/******************************************************************************
+* Function Name: static int sddev_disable_dma_0(void);
+* Description : Disable DMAC transfer
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+static int sddev_disable_dma_0(void)
+{
+#ifdef SDCFG_TRNS_DMA
+ uint32_t remain;
+
+ sd_DMAC1_Close(&remain);
+#endif
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: staticint sddev_disable_dma_1(void);
+* Description : Disable DMAC transfer
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+static int sddev_disable_dma_1(void)
+{
+#ifdef SDCFG_TRNS_DMA
+ uint32_t remain;
+
+ sd_DMAC2_Close(&remain);
+#endif
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_loc_cpu(int sd_port);
+* Description : lock cpu to disable interrupt
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_loc_cpu(int sd_port)
+{
+#if 0
+ R_INTC_GetMaskLevel(&g_sdhi_priority_backup);
+ R_INTC_SetMaskLevel(0);
+ core_util_critical_section_enter();
+#endif
+
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_unl_cpu(int sd_port);
+* Description : unlock cpu to enable interrupt
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_unl_cpu(int sd_port)
+{
+#if 0
+ R_INTC_SetMaskLevel(g_sdhi_priority_backup);
+ core_util_critical_section_exit();
+#endif
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_finalize(int sd_port);
+* Description : finalize SDHI
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+int sddev_finalize(int sd_port)
+{
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: static void sddev_sd_int_handler_0(uint32_t int_sense);
+* Description : Setting Interrupt function for SDHI(INTC_ID_SDHI0_0,INTC_ID_SDHI0_3)
+* Arguments : Interrupt mode
+* Return Value : none
+******************************************************************************/
+static void sddev_sd_int_handler_0(uint32_t int_sense)
+{
+ sd_int_handler(0);
+}
+
+/******************************************************************************
+* Function Name: static void sddev_sd_int_handler_1(uint32_t int_sense);
+* Description : Setting Interrupt function for SDHI(INTC_ID_SDHI0_0,INTC_ID_SDHI0_3)
+* Arguments : Interrupt mode
+* Return Value : none
+******************************************************************************/
+static void sddev_sd_int_handler_1(uint32_t int_sense)
+{
+ sd_int_handler(1);
+}
+
+/******************************************************************************
+* Function Name: static void sddev_sdio_int_handler_0(uint32_t int_sense);
+* Description : Setting Interrupt function for SDHI(INTC_ID_SDHI0_1)
+* Arguments : Interrupt mode
+* Return Value : none
+******************************************************************************/
+static void sddev_sdio_int_handler_0(uint32_t int_sense)
+{
+ sdio_int_handler(0);
+}
+
+/******************************************************************************
+* Function Name: static void sddev_sdio_int_handler_1(uint32_t int_sense);
+* Description : Setting Interrupt function for SDHI(INTC_ID_SDHI1_1)
+* Arguments : Interrupt mode
+* Return Value : none
+******************************************************************************/
+static void sddev_sdio_int_handler_1(uint32_t int_sense)
+{
+ sdio_int_handler(1);
+}
+
+/******************************************************************************
+* Function Name: static void sddev_start_timer(int msec);
+* Description : start timer
+* Arguments :
+* Return Value : none
+******************************************************************************/
+static void sddev_start_timer(int msec)
+{
+ _ticker = get_us_ticker_data();
+ _ulStart = ticker_read(_ticker);
+ _ulDelta = msec*1000ul;
+}
+
+/******************************************************************************
+* Function Name: static void sddev_end_timer(void);
+* Description : end timer
+* Arguments :
+* Return Value : none
+******************************************************************************/
+static void sddev_end_timer(void)
+{
+ _ulStart = 0ul;
+ _ulDelta = 0ul;
+}
+
+/******************************************************************************
+* Function Name: static int sddev_check_timer(void);
+* Description : check
+* Arguments :
+* Return Value : t
+******************************************************************************/
+static int sddev_check_timer(void)
+{
+ if ( _ulStart && _ulDelta )
+ {
+ return ((ticker_read(_ticker)-_ulStart) < _ulDelta) ? SD_OK : SD_ERR;
+ }
+ else
+ {
+ return SD_ERR;
+ }
+}
+
+/* End of File */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/SDHI_driver/sdif.h Mon Mar 18 16:54:40 2019 +0000
@@ -0,0 +1,329 @@
+/******************************************************************************
+* DISCLAIMER
+*
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized.
+*
+* This software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+*
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
+* DISCLAIMED.
+*
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Renesas reserves the right, without notice, to make changes to this
+* software and to discontinue the availability of this software.
+* By using this software, you agree to the additional terms and
+* conditions found by accessing the following link:
+* http://www.renesas.com/disclaimer
+********************************************************************************
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+**************************** Technical reference data **************************
+* System Name : SD Driver Sample Program
+* File Name : sdif.h
+* Abstract : SD Memory card driver configration
+* Version : 4.00.00
+* Device : Aragon
+* Tool-Chain : DS-5 Ver 5.13
+* ARM Complier
+* OS : None
+* H/W Platform:
+* Description :
+********************************************************************************
+* History : 2013.07.12 Ver.4.00.00
+*******************************************************************************/
+#ifndef _SDDRV_H_
+#define _SDDRV_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* ==== define ==== */
+/* ---- SD Driver work buffer ---- */
+#define SD_SIZE_OF_INIT 800
+
+/* ---- error code ---- */
+#define SD_OK_LOCKED_CARD 1 /* OK but card is locked status */
+#define SD_OK 0 /* OK */
+#define SD_ERR -1 /* general error */
+#define SD_ERR_WP -2 /* write protect error */
+#define SD_ERR_RO -3 /* read only error */
+#define SD_ERR_RES_TOE -4 /* response time out error */
+#define SD_ERR_CARD_TOE -5 /* card time out error */
+#define SD_ERR_END_BIT -6 /* end bit error */
+#define SD_ERR_CRC -7 /* CRC error */
+#define SD_ERR_CARD_RES -8 /* card response error */
+#define SD_ERR_HOST_TOE -9 /* host time out error */
+#define SD_ERR_CARD_ERASE -10 /* card erase error */
+#define SD_ERR_CARD_LOCK -11 /* card lock error */
+#define SD_ERR_CARD_UNLOCK -12 /* card unlock error */
+#define SD_ERR_HOST_CRC -13 /* host CRC error */
+#define SD_ERR_CARD_ECC -14 /* card internal ECC error */
+#define SD_ERR_CARD_CC -15 /* card internal error */
+#define SD_ERR_CARD_ERROR -16 /* unknown card error */
+#define SD_ERR_CARD_TYPE -17 /* non support card type */
+#define SD_ERR_NO_CARD -18 /* no card */
+#define SD_ERR_ILL_READ -19 /* illegal buffer read */
+#define SD_ERR_ILL_WRITE -20 /* illegal buffer write */
+#define SD_ERR_AKE_SEQ -21 /* the sequence of authentication process */
+#define SD_ERR_OVERWRITE -22 /* CID/CSD overwrite error */
+/* 23-29 */
+#define SD_ERR_CPU_IF -30 /* target CPU interface function error */
+#define SD_ERR_STOP -31 /* user stop */
+/* 32-49 */
+#define SD_ERR_CSD_VER -50 /* CSD register version error */
+#define SD_ERR_SCR_VER -51 /* SCR register version error */
+#define SD_ERR_FILE_FORMAT -52 /* CSD register file format error */
+#define SD_ERR_NOTSUP_CMD -53 /* not supported command */
+/* 54-59 */
+#define SD_ERR_ILL_FUNC -60 /* invalid function request error */
+#define SD_ERR_IO_VERIFY -61 /* direct write verify error */
+#define SD_ERR_IO_CAPAB -62 /* IO capability error */
+/* 63-69 */
+#define SD_ERR_IFCOND_VER -70 /* Interface condition version error */
+#define SD_ERR_IFCOND_VOLT -71 /* Interface condition voltage error */
+#define SD_ERR_IFCOND_ECHO -72 /* Interface condition echo back pattern error */
+/* 73-79 */
+#define SD_ERR_OUT_OF_RANGE -80 /* the argument was out of range */
+#define SD_ERR_ADDRESS_ERROR -81 /* misassigned address */
+#define SD_ERR_BLOCK_LEN_ERROR -82 /* transfered block length is not allowed */
+#define SD_ERR_ILLEGAL_COMMAND -83 /* Command not legal */
+#define SD_ERR_RESERVED_ERROR18 -84 /* Reserved bit 18 Error */
+#define SD_ERR_RESERVED_ERROR17 -85 /* Reserved bit 17 Error */
+#define SD_ERR_CMD_ERROR -86 /* SD_INFO2 bit 0 CMD error */
+#define SD_ERR_CBSY_ERROR -87 /* SD_INFO2 bit 14 CMD Type Reg Busy error */
+#define SD_ERR_NO_RESP_ERROR -88 /* SD_INFO1 bit 0 No Response error */
+/* 89 */
+/* 90-95 */
+#define SD_ERR_ERROR -96 /* SDIO ERROR */
+#define SD_ERR_FUNCTION_NUMBER -97 /* SDIO FUNCTION NUMBER ERROR */
+#define SD_ERR_COM_CRC_ERROR -98 /* SDIO CRC ERROR */
+#define SD_ERR_INTERNAL -99 /* driver software internal error */
+
+/* ---- driver mode ---- */
+#define SD_MODE_POLL 0x0000ul /* status check mode is software polling */
+#define SD_MODE_HWINT 0x0001ul /* status check mode is hardware interrupt */
+#define SD_MODE_SW 0x0000ul /* data transfer mode is software */
+#define SD_MODE_DMA 0x0002ul /* data transfer mode is DMA */
+#define SD_MODE_DMA_64 0x0004ul /* data transfer mode is DMA with 64 byte burst mode */
+
+/* ---- support mode ---- */
+#define SD_MODE_MEM 0x0000ul /* memory cards only are supported */
+#define SD_MODE_IO 0x0010ul /* memory and io cards are supported */
+#define SD_MODE_COMBO 0x0030ul /* memory ,io and combo cards are supported */
+#define SD_MODE_DS 0x0000ul /* only default speed mode is supported */
+#define SD_MODE_HS 0x0040ul /* high speed mode is also supported */
+#define SD_MODE_VER1X 0x0000ul /* ver1.1 host */
+#define SD_MODE_VER2X 0x0080ul /* ver2.x host (high capacity and dual voltage) */
+#define SD_MODE_1BIT 0x0100ul /* SD Mode 1bit only is supported */
+#define SD_MODE_4BIT 0x0000ul /* SD Mode 1bit and 4bit is supported */
+
+/* ---- media voltage ---- */
+#define SD_VOLT_1_7 0x00000010ul /* low voltage card minimum */
+#define SD_VOLT_1_8 0x00000020ul
+#define SD_VOLT_1_9 0x00000040ul
+#define SD_VOLT_2_0 0x00000080ul
+#define SD_VOLT_2_1 0x00000100ul /* basic communication minimum */
+#define SD_VOLT_2_2 0x00000200ul
+#define SD_VOLT_2_3 0x00000400ul
+#define SD_VOLT_2_4 0x00000800ul
+#define SD_VOLT_2_5 0x00001000ul
+#define SD_VOLT_2_6 0x00002000ul
+#define SD_VOLT_2_7 0x00004000ul
+#define SD_VOLT_2_8 0x00008000ul /* memory access minimum */
+#define SD_VOLT_2_9 0x00010000ul
+#define SD_VOLT_3_0 0x00020000ul
+#define SD_VOLT_3_1 0x00040000ul
+#define SD_VOLT_3_2 0x00080000ul
+#define SD_VOLT_3_3 0x00100000ul
+#define SD_VOLT_3_4 0x00200000ul
+#define SD_VOLT_3_5 0x00400000ul
+#define SD_VOLT_3_6 0x00800000ul
+
+/* ---- memory card write mode ---- */
+#define SD_WRITE_WITH_PREERASE 0x0000u /* pre-erease write */
+#define SD_WRITE_OVERWRITE 0x0001u /* overwrite */
+
+/* ---- io register write mode ---- */
+#define SD_IO_SIMPLE_WRITE 0x0000u /* just write */
+#define SD_IO_VERIFY_WRITE 0x0001u /* read after write */
+
+/* ---- io operation code ---- */
+#define SD_IO_FIXED_ADDR 0x0000u /* R/W fixed address */
+#define SD_IO_INCREMENT_ADDR 0x0001u /* R/W increment address */
+#define SD_IO_FORCE_BYTE 0x0010u /* byte access only */
+
+ /* ---- media type ---- */
+#define SD_MEDIA_UNKNOWN 0x0000u /* unknown media */
+#define SD_MEDIA_MMC 0x0010u /* MMC card */
+#define SD_MEDIA_SD 0x0020u /* SD Memory card */
+#define SD_MEDIA_IO 0x0001u /* SD IO card */
+#define SD_MEDIA_MEM 0x0030u /* Memory card */
+#define SD_MEDIA_COMBO 0x0021u /* SD COMBO card */
+#define SD_MEDIA_EMBEDDED 0x8000u /* embedded media */
+
+/* ---- write protect info --- */
+#define SD_WP_OFF 0x0000u /* card is not write protect */
+#define SD_WP_HW 0x0001u /* card is H/W write protect */
+#define SD_WP_TEMP 0x0002u /* card is TEMP_WRITE_PROTECT */
+#define SD_WP_PERM 0x0004u /* card is PERM_WRITE_PROTECT */
+#define SD_WP_ROM 0x0010u /* card is SD-ROM */
+
+/* ---- SD clock div ---- */ /* IMCLK is host controller clock */
+#define SD_DIV_512 0x0080u /* SDCLOCK = IMCLK/512 */
+#define SD_DIV_256 0x0040u /* SDCLOCK = IMCLK/256 */
+#define SD_DIV_128 0x0020u /* SDCLOCK = IMCLK/128 */
+#define SD_DIV_64 0x0010u /* SDCLOCK = IMCLK/64 */
+#define SD_DIV_32 0x0008u /* SDCLOCK = IMCLK/32 */
+#define SD_DIV_16 0x0004u /* SDCLOCK = IMCLK/16 */
+#define SD_DIV_8 0x0002u /* SDCLOCK = IMCLK/8 */
+#define SD_DIV_4 0x0001u /* SDCLOCK = IMCLK/4 */
+#define SD_DIV_2 0x0000u /* SDCLOCK = IMCLK/2 */
+#define SD_DIV_1 0x00FFu /* SDCLOCK = IMCLK (option) */
+
+/* ---- SD clock define ---- */ /* max frequency */
+#define SD_CLK_400kHz 0x0000u /* 400kHz */
+#define SD_CLK_1MHz 0x0001u /* 1MHz */
+#define SD_CLK_5MHz 0x0002u /* 5MHz */
+#define SD_CLK_10MHz 0x0003u /* 10MHz */
+#define SD_CLK_20MHz 0x0004u /* 20MHz */
+#define SD_CLK_25MHz 0x0005u /* 25MHz */
+#define SD_CLK_50MHz 0x0006u /* 50MHz (phys spec ver1.10) */
+
+/* ---- speed class ---- */
+#define SD_SPEED_CLASS_0 0x00u /* not defined, or less than ver2.0 */
+#define SD_SPEED_CLASS_2 0x01u /* 2MB/sec */
+#define SD_SPEED_CLASS_4 0x02u /* 4MB/sec */
+#define SD_SPEED_CLASS_6 0x03u /* 6MB/sec */
+
+/* ---- IO initialize flags define ---- */ /* add for IO */
+#define SD_IO_INT_ENAB 0x10u /* interrupt enable */
+#define SD_IO_POWER_INIT 0x04u /* power on initialized */
+#define SD_IO_MEM_INIT 0x02u /* memory initialized */
+#define SD_IO_FUNC_INIT 0x01u /* io func initialized */
+
+/* ---- IO function's information ---- */ /* add for IO */
+#define SD_IO_FUNC_READY 0x80u /* io redy */
+#define SD_IO_FUNC_NUM 0x70u /* number of io func */
+#define SD_IO_FUNC_EXISTS 0x04u /* memory present */
+
+/* ---- SD port mode ---- */
+#define SD_PORT_SERIAL 0x0000u /* 1bit mode */
+#define SD_PORT_PARALLEL 0x0001u /* 4bits mode */
+
+/* ---- SD Card detect port ---- */
+#define SD_CD_SOCKET 0x0000u /* CD pin */
+#define SD_CD_DAT3 0x0001u /* DAT3 pin */
+
+/* ---- SD Card detect interrupt ---- */
+#define SD_CD_INT_DISABLE 0x0000u /* card detect interrupt disable */
+#define SD_CD_INT_ENABLE 0x0001u /* card detect interrupt enable */
+
+/* ---- format mode ---- */
+#define SD_FORMAT_QUICK 0x0000u /* quick format */
+#define SD_FORMAT_FULL 0x0001u /* full format */
+
+/* ---- lock/unlock mode ---- */
+#define SD_FORCE_ERASE 0x08
+#define SD_LOCK_CARD 0x04
+#define SD_UNLOCK_CARD 0x00
+#define SD_CLR_PWD 0x02
+#define SD_SET_PWD 0x01
+
+/* ==== API prototype ===== */
+/* ---- access library I/F ---- */
+int sd_init(int sd_port, unsigned long base, void *workarea, int cd_port);
+int sd_cd_int(int sd_port, int enable,int (*callback)(int, int));
+int sd_check_media(int sd_port);
+int sd_format(int sd_port, int mode,int (*callback)(unsigned long,unsigned long));
+int sd_format2(int sd_port, int mode,unsigned long volserial,int (*callback)(unsigned long,unsigned long));
+int sd_mount(int sd_port, unsigned long mode,unsigned long voltage);
+int sd_read_sect(int sd_port, unsigned char *buff,unsigned long psn,long cnt);
+int sd_write_sect(int sd_port, unsigned char *buff,unsigned long psn,long cnt,int writemode);
+int sd_get_type(int sd_port, unsigned char *type,unsigned char *speed,unsigned char *capa);
+int sd_get_size(int sd_port, unsigned long *user,unsigned long *protect);
+int sd_iswp(int sd_port);
+int sd_unmount(int sd_port);
+void sd_stop(int sd_port);
+int sd_set_intcallback(int sd_port, int (*callback)(int, int));
+void sd_int_handler(int sd_port);
+int sd_get_error(int sd_port);
+int sd_check_int(int sd_port);
+int sd_get_reg(int sd_port, unsigned char *ocr,unsigned char *cid,unsigned char *csd, unsigned char *dsr,unsigned char *scr);
+int sd_get_rca(int sd_port, unsigned char *rca);
+int sd_get_sdstatus(int sd_port, unsigned char *sdstatus);
+int sd_get_speed(int sd_port, unsigned char *clss,unsigned char *move);
+int sd_finalize(int sd_port);
+int sd_set_seccnt(int sd_port, short sectors);
+int sd_get_seccnt(int sd_port);
+int sd_get_ver(int sd_port, unsigned short *sdhi_ver,char *sddrv_ver);
+int sd_set_cdtime(int sd_port, unsigned short cdtime);
+int sd_set_responsetime(int sd_port, unsigned short responsetime);
+int sd_set_buffer(int sd_port, void *buff,unsigned long size);
+int sd_inactive(int sd_port);
+int sd_set_softwp(int sd_port, int is_set,unsigned long data);
+int sd_set_tmpwp(int sd_port, int is_set);
+int sd_lock_unlock(int sd_port, unsigned char code,unsigned char *pwd,unsigned char len);
+
+int esd_get_partition_id(int sd_port, int *id);
+int esd_select_partition(int sd_port, int id);
+int esd_query_partition(int sd_port, int sub, unsigned char *data);
+
+int sdio_read_direct(int sd_port, unsigned char *buff,unsigned long func,unsigned long adr);
+int sdio_write_direct(int sd_port, unsigned char *buff,unsigned long func,unsigned long adr,unsigned long raw_flag);
+int sdio_check_int(int sd_port);
+void sdio_int_handler(int sd_port);
+int sdio_set_intcallback(int sd_port, int (*callback)(int));
+int sdio_enable_int(int sd_port);
+int sdio_disable_int(int sd_port);
+int sdio_read(int sd_port, unsigned char *buff,unsigned long func,unsigned long adr,long cnt,unsigned long op_code);
+int sdio_write(int sd_port, unsigned char *buff,unsigned long func,unsigned long adr,long cnt,unsigned long op_code);
+int sdio_reset(int sd_port);
+int sdio_get_ioocr(int sd_port, unsigned long *ioocr);
+int sdio_get_ioinfo(int sd_port, unsigned char *ioinfo);
+int sdio_get_cia(int sd_port, unsigned char *reg, unsigned char *cis, unsigned long func_num, long cnt);
+int sdio_set_enable(int sd_port, unsigned char func_bit);
+int sdio_get_ready(int sd_port, unsigned char *func_bit);
+int sdio_set_int(int sd_port, unsigned char func_bit,int enab);
+int sdio_get_int(int sd_port, unsigned char *func_bit,int *enab);
+int sdio_set_blocklen(int sd_port, unsigned short len, unsigned long func_num);
+int sdio_get_blocklen(int sd_port, unsigned short *len, unsigned long func_num);
+void sdio_abort(int sd_port, unsigned long func_num);
+int sdio_set_blkcnt(int sd_port, short blocks);
+int sdio_get_blkcnt(int sd_port);
+
+/* ---- target CPU I/F ---- */
+int sddev_init(int sd_port);
+int sddev_power_on(int sd_port);
+int sddev_power_off(int sd_port);
+int sddev_read_data(int sd_port, unsigned char *buff,unsigned long reg_addr,long num);
+int sddev_write_data(int sd_port, unsigned char *buff,unsigned long reg_addr,long num);
+unsigned int sddev_get_clockdiv(int sd_port, int clock);
+int sddev_set_port(int sd_port, int mode);
+int sddev_int_wait(int sd_port, int msec);
+int sddev_init_dma(int sd_port, unsigned long buffadr,unsigned long regadr,long cnt,int dir);
+int sddev_wait_dma_end(int sd_port, long cnt);
+int sddev_disable_dma(int sd_port);
+int sddev_finalize(int sd_port);
+int sddev_loc_cpu(int sd_port);
+int sddev_unl_cpu(int sd_port);
+int sddev_cmd0_sdio_mount(int sd_port);
+int sddev_cmd8_sdio_mount(int sd_port);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SDDRV_H_ */
+
+/* End of File */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h Mon Mar 18 16:54:40 2019 +0000
@@ -0,0 +1,923 @@
+/******************************************************************************
+ * @file VK_RZ_A1H.h
+ * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
+ * @version V1.00
+ * @data 10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __VK_RZ_A1H_H__
+#define __VK_RZ_A1H_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/****** SGI Interrupts Numbers ****************************************/
+ SGI0_IRQn = 0,
+ SGI1_IRQn = 1,
+ SGI2_IRQn = 2,
+ SGI3_IRQn = 3,
+ SGI4_IRQn = 4,
+ SGI5_IRQn = 5,
+ SGI6_IRQn = 6,
+ SGI7_IRQn = 7,
+ SGI8_IRQn = 8,
+ SGI9_IRQn = 9,
+ SGI10_IRQn = 10,
+ SGI11_IRQn = 11,
+ SGI12_IRQn = 12,
+ SGI13_IRQn = 13,
+ SGI14_IRQn = 14,
+ SGI15_IRQn = 15,
+
+/****** Cortex-A9 Processor Exceptions Numbers ****************************************/
+ /* 16 - 578 */
+ PMUIRQ0_IRQn = 16,
+ COMMRX0_IRQn = 17,
+ COMMTX0_IRQn = 18,
+ CTIIRQ0_IRQn = 19,
+
+ IRQ0_IRQn = 32,
+ IRQ1_IRQn = 33,
+ IRQ2_IRQn = 34,
+ IRQ3_IRQn = 35,
+ IRQ4_IRQn = 36,
+ IRQ5_IRQn = 37,
+ IRQ6_IRQn = 38,
+ IRQ7_IRQn = 39,
+
+ PL310ERR_IRQn = 40,
+
+ DMAINT0_IRQn = 41, /*!< DMAC Interrupt */
+ DMAINT1_IRQn = 42, /*!< DMAC Interrupt */
+ DMAINT2_IRQn = 43, /*!< DMAC Interrupt */
+ DMAINT3_IRQn = 44, /*!< DMAC Interrupt */
+ DMAINT4_IRQn = 45, /*!< DMAC Interrupt */
+ DMAINT5_IRQn = 46, /*!< DMAC Interrupt */
+ DMAINT6_IRQn = 47, /*!< DMAC Interrupt */
+ DMAINT7_IRQn = 48, /*!< DMAC Interrupt */
+ DMAINT8_IRQn = 49, /*!< DMAC Interrupt */
+ DMAINT9_IRQn = 50, /*!< DMAC Interrupt */
+ DMAINT10_IRQn = 51, /*!< DMAC Interrupt */
+ DMAINT11_IRQn = 52, /*!< DMAC Interrupt */
+ DMAINT12_IRQn = 53, /*!< DMAC Interrupt */
+ DMAINT13_IRQn = 54, /*!< DMAC Interrupt */
+ DMAINT14_IRQn = 55, /*!< DMAC Interrupt */
+ DMAINT15_IRQn = 56, /*!< DMAC Interrupt */
+ DMAERR_IRQn = 57, /*!< DMAC Interrupt */
+
+ /* 58-72 Reserved */
+
+ USBI0_IRQn = 73,
+ USBI1_IRQn = 74,
+
+ S0_VI_VSYNC0_IRQn = 75,
+ S0_LO_VSYNC0_IRQn = 76,
+ S0_VSYNCERR0_IRQn = 77,
+ GR3_VLINE0_IRQn = 78,
+ S0_VFIELD0_IRQn = 79,
+ IV1_VBUFERR0_IRQn = 80,
+ IV3_VBUFERR0_IRQn = 81,
+ IV5_VBUFERR0_IRQn = 82,
+ IV6_VBUFERR0_IRQn = 83,
+ S0_WLINE0_IRQn = 84,
+ S1_VI_VSYNC0_IRQn = 85,
+ S1_LO_VSYNC0_IRQn = 86,
+ S1_VSYNCERR0_IRQn = 87,
+ S1_VFIELD0_IRQn = 88,
+ IV2_VBUFERR0_IRQn = 89,
+ IV4_VBUFERR0_IRQn = 90,
+ S1_WLINE0_IRQn = 91,
+ OIR_VI_VSYNC0_IRQn = 92,
+ OIR_LO_VSYNC0_IRQn = 93,
+ OIR_VSYNCERR0_IRQn = 94,
+ OIR_VFIELD0_IRQn = 95,
+ IV7_VBUFERR0_IRQn = 96,
+ IV8_VBUFERR0_IRQn = 97,
+ /* 98 Reserved */
+ S0_VI_VSYNC1_IRQn = 99,
+ S0_LO_VSYNC1_IRQn = 100,
+ S0_VSYNCERR1_IRQn = 101,
+ GR3_VLINE1_IRQn = 102,
+ S0_VFIELD1_IRQn = 103,
+ IV1_VBUFERR1_IRQn = 104,
+ IV3_VBUFERR1_IRQn = 105,
+ IV5_VBUFERR1_IRQn = 106,
+ IV6_VBUFERR1_IRQn = 107,
+ S0_WLINE1_IRQn = 108,
+ S1_VI_VSYNC1_IRQn = 109,
+ S1_LO_VSYNC1_IRQn = 110,
+ S1_VSYNCERR1_IRQn = 111,
+ S1_VFIELD1_IRQn = 112,
+ IV2_VBUFERR1_IRQn = 113,
+ IV4_VBUFERR1_IRQn = 114,
+ S1_WLINE1_IRQn = 115,
+ OIR_VI_VSYNC1_IRQn = 116,
+ OIR_LO_VSYNC1_IRQn = 117,
+ OIR_VSYNCERR1_IRQn = 118,
+ OIR_VFIELD1_IRQn = 119,
+ IV7_VBUFERR1_IRQn = 120,
+ IV8_VBUFERR1_IRQn = 121,
+ /* Reserved = 122 */
+
+ IMRDI_IRQn = 123,
+ IMR2I0_IRQn = 124,
+ IMR2I1_IRQn = 125,
+
+ JEDI_IRQn = 126,
+ JDTI_IRQn = 127,
+
+ CMP0_IRQn = 128,
+ CMP1_IRQn = 129,
+
+ INT0_IRQn = 130,
+ INT1_IRQn = 131,
+ INT2_IRQn = 132,
+ INT3_IRQn = 133,
+
+ OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */
+ OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */
+
+ CMI_IRQn = 136,
+ WTOUT_IRQn = 137,
+
+ ITI_IRQn = 138,
+
+ TGI0A_IRQn = 139,
+ TGI0B_IRQn = 140,
+ TGI0C_IRQn = 141,
+ TGI0D_IRQn = 142,
+ TGI0V_IRQn = 143,
+ TGI0E_IRQn = 144,
+ TGI0F_IRQn = 145,
+ TGI1A_IRQn = 146,
+ TGI1B_IRQn = 147,
+ TGI1V_IRQn = 148,
+ TGI1U_IRQn = 149,
+ TGI2A_IRQn = 150,
+ TGI2B_IRQn = 151,
+ TGI2V_IRQn = 152,
+ TGI2U_IRQn = 153,
+ TGI3A_IRQn = 154,
+ TGI3B_IRQn = 155,
+ TGI3C_IRQn = 156,
+ TGI3D_IRQn = 157,
+ TGI3V_IRQn = 158,
+ TGI4A_IRQn = 159,
+ TGI4B_IRQn = 160,
+ TGI4C_IRQn = 161,
+ TGI4D_IRQn = 162,
+ TGI4V_IRQn = 163,
+
+ CMI1_IRQn = 164,
+ CMI2_IRQn = 165,
+
+ SGDEI0_IRQn = 166,
+ SGDEI1_IRQn = 167,
+ SGDEI2_IRQn = 168,
+ SGDEI3_IRQn = 169,
+
+ ADI_IRQn = 170,
+ LMTI_IRQn = 171,
+
+ SSII0_IRQn = 172, /*!< SSIF Interrupt */
+ SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */
+ SSITXI0_IRQn = 174, /*!< SSIF Interrupt */
+ SSII1_IRQn = 175, /*!< SSIF Interrupt */
+ SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */
+ SSITXI1_IRQn = 177, /*!< SSIF Interrupt */
+ SSII2_IRQn = 178, /*!< SSIF Interrupt */
+ SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */
+ SSII3_IRQn = 180, /*!< SSIF Interrupt */
+ SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */
+ SSITXI3_IRQn = 182, /*!< SSIF Interrupt */
+ SSII4_IRQn = 183, /*!< SSIF Interrupt */
+ SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */
+ SSII5_IRQn = 185, /*!< SSIF Interrupt */
+ SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */
+ SSITXI5_IRQn = 187, /*!< SSIF Interrupt */
+
+ SPDIFI_IRQn = 188,
+
+ INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */
+ INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */
+ INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */
+ INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */
+ INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */
+ INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */
+ INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */
+ INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */
+ INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */
+ INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */
+ INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */
+ INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */
+ INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */
+ INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */
+ INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */
+ INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */
+ INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */
+ INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */
+ INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */
+ INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */
+ INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */
+ INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */
+ INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */
+ INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */
+ INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */
+ INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */
+ INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */
+ INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */
+ INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */
+ INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */
+ INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */
+ INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */
+
+ SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */
+ SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */
+ SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */
+ SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */
+ SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */
+ SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */
+ SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */
+ SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */
+ SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */
+ SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */
+ SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */
+ SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */
+ SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */
+ SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */
+ SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */
+ SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */
+ SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */
+ SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */
+ SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */
+ SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */
+ SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */
+ SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */
+ SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */
+ SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */
+ SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */
+ SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */
+ SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */
+ SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */
+ SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */
+ SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */
+ SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */
+ SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */
+
+ INTRCANGERR_IRQn = 253,
+ INTRCANGRECC_IRQn = 254,
+ INTRCAN0REC_IRQn = 255,
+ INTRCAN0ERR_IRQn = 256,
+ INTRCAN0TRX_IRQn = 257,
+ INTRCAN1REC_IRQn = 258,
+ INTRCAN1ERR_IRQn = 259,
+ INTRCAN1TRX_IRQn = 260,
+ INTRCAN2REC_IRQn = 261,
+ INTRCAN2ERR_IRQn = 262,
+ INTRCAN2TRX_IRQn = 263,
+ INTRCAN3REC_IRQn = 264,
+ INTRCAN3ERR_IRQn = 265,
+ INTRCAN3TRX_IRQn = 266,
+ INTRCAN4REC_IRQn = 267,
+ INTRCAN4ERR_IRQn = 268,
+ INTRCAN4TRX_IRQn = 269,
+
+ RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */
+ RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */
+ RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */
+ RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */
+ RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */
+ RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */
+ RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */
+ RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */
+ RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */
+ RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */
+ RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */
+ RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */
+ RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */
+ RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */
+ RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */
+
+ IEBBTD_IRQn = 285,
+ IEBBTERR_IRQn = 286,
+ IEBBTSTA_IRQn = 287,
+ IEBBTV_IRQn = 288,
+
+ ISY_IRQn = 289,
+ IERR_IRQn = 290,
+ ITARG_IRQn = 291,
+ ISEC_IRQn = 292,
+ IBUF_IRQn = 293,
+ IREADY_IRQn = 294,
+
+ STERB_IRQn = 295,
+ FLTENDI_IRQn = 296,
+ FLTREQ0I_IRQn = 297,
+ FLTREQ1I_IRQn = 298,
+
+ MMC0_IRQn = 299,
+ MMC1_IRQn = 300,
+ MMC2_IRQn = 301,
+
+ SDHI0_3_IRQn = 302,
+ SDHI0_0_IRQn = 303,
+ SDHI0_1_IRQn = 304,
+ SDHI1_3_IRQn = 305,
+ SDHI1_0_IRQn = 306,
+ SDHI1_1_IRQn = 307,
+
+ ARM_IRQn = 308,
+ PRD_IRQn = 309,
+ CUP_IRQn = 310,
+
+ SCUAI0_IRQn = 311,
+ SCUAI1_IRQn = 312,
+ SCUFDI0_IRQn = 313,
+ SCUFDI1_IRQn = 314,
+ SCUFDI2_IRQn = 315,
+ SCUFDI3_IRQn = 316,
+ SCUFUI0_IRQn = 317,
+ SCUFUI1_IRQn = 318,
+ SCUFUI2_IRQn = 319,
+ SCUFUI3_IRQn = 320,
+ SCUDVI0_IRQn = 321,
+ SCUDVI1_IRQn = 322,
+ SCUDVI2_IRQn = 323,
+ SCUDVI3_IRQn = 324,
+
+ MLB_CINT_IRQn = 325,
+ MLB_SINT_IRQn = 326,
+
+ DRC10_IRQn = 327,
+ DRC11_IRQn = 328,
+
+ /* 329-330 Reserved */
+
+ LINI0_INT_T_IRQn = 331,
+ LINI0_INT_R_IRQn = 332,
+ LINI0_INT_S_IRQn = 333,
+ LINI0_INT_M_IRQn = 334,
+ LINI1_INT_T_IRQn = 335,
+ LINI1_INT_R_IRQn = 336,
+ LINI1_INT_S_IRQn = 337,
+ LINI1_INT_M_IRQn = 338,
+
+ /* 339-346 Reserved */
+
+ SCIERI0_IRQn = 347,
+ SCIRXI0_IRQn = 348,
+ SCITXI0_IRQn = 349,
+ SCITEI0_IRQn = 350,
+ SCIERI1_IRQn = 351,
+ SCIRXI1_IRQn = 352,
+ SCITXI1_IRQn = 353,
+ SCITEI1_IRQn = 354,
+
+ AVBI_DATA = 355,
+ AVBI_ERROR = 356,
+ AVBI_MANAGE = 357,
+ AVBI_MAC = 358,
+
+ ETHERI_IRQn = 359,
+
+ /* 360-363 Reserved */
+
+ CEUI_IRQn = 364,
+
+ /* 365-380 Reserved */
+
+ H2XMLB_ERRINT_IRQn = 381,
+ H2XIC1_ERRINT_IRQn = 382,
+ X2HPERI1_ERRINT_IRQn = 383,
+ X2HPERR2_ERRINT_IRQn = 384,
+ X2HPERR34_ERRINT_IRQn= 385,
+ X2HPERR5_ERRINT_IRQn = 386,
+ X2HPERR67_ERRINT_IRQn= 387,
+ X2HDBGR_ERRINT_IRQn = 388,
+ X2HBSC_ERRINT_IRQn = 389,
+ X2HSPI1_ERRINT_IRQn = 390,
+ X2HSPI2_ERRINT_IRQn = 391,
+ PRRI_IRQn = 392,
+
+ IFEI0_IRQn = 393,
+ OFFI0_IRQn = 394,
+ PFVEI0_IRQn = 395,
+ IFEI1_IRQn = 396,
+ OFFI1_IRQn = 397,
+ PFVEI1_IRQn = 398,
+
+ /* 399-415 Reserved */
+
+ TINT0_IRQn = 416,
+ TINT1_IRQn = 417,
+ TINT2_IRQn = 418,
+ TINT3_IRQn = 419,
+ TINT4_IRQn = 420,
+ TINT5_IRQn = 421,
+ TINT6_IRQn = 422,
+ TINT7_IRQn = 423,
+ TINT8_IRQn = 424,
+ TINT9_IRQn = 425,
+ TINT10_IRQn = 426,
+ TINT11_IRQn = 427,
+ TINT12_IRQn = 428,
+ TINT13_IRQn = 429,
+ TINT14_IRQn = 430,
+ TINT15_IRQn = 431,
+ TINT16_IRQn = 432,
+ TINT17_IRQn = 433,
+ TINT18_IRQn = 434,
+ TINT19_IRQn = 435,
+ TINT20_IRQn = 436,
+ TINT21_IRQn = 437,
+ TINT22_IRQn = 438,
+ TINT23_IRQn = 439,
+ TINT24_IRQn = 440,
+ TINT25_IRQn = 441,
+ TINT26_IRQn = 442,
+ TINT27_IRQn = 443,
+ TINT28_IRQn = 444,
+ TINT29_IRQn = 445,
+ TINT30_IRQn = 446,
+ TINT31_IRQn = 447,
+ TINT32_IRQn = 448,
+ TINT33_IRQn = 449,
+ TINT34_IRQn = 450,
+ TINT35_IRQn = 451,
+ TINT36_IRQn = 452,
+ TINT37_IRQn = 453,
+ TINT38_IRQn = 454,
+ TINT39_IRQn = 455,
+ TINT40_IRQn = 456,
+ TINT41_IRQn = 457,
+ TINT42_IRQn = 458,
+ TINT43_IRQn = 459,
+ TINT44_IRQn = 460,
+ TINT45_IRQn = 461,
+ TINT46_IRQn = 462,
+ TINT47_IRQn = 463,
+ TINT48_IRQn = 464,
+ TINT49_IRQn = 465,
+ TINT50_IRQn = 466,
+ TINT51_IRQn = 467,
+ TINT52_IRQn = 468,
+ TINT53_IRQn = 469,
+ TINT54_IRQn = 470,
+ TINT55_IRQn = 471,
+ TINT56_IRQn = 472,
+ TINT57_IRQn = 473,
+ TINT58_IRQn = 474,
+ TINT59_IRQn = 475,
+ TINT60_IRQn = 476,
+ TINT61_IRQn = 477,
+ TINT62_IRQn = 478,
+ TINT63_IRQn = 479,
+ TINT64_IRQn = 480,
+ TINT65_IRQn = 481,
+ TINT66_IRQn = 482,
+ TINT67_IRQn = 483,
+ TINT68_IRQn = 484,
+ TINT69_IRQn = 485,
+ TINT70_IRQn = 486,
+ TINT71_IRQn = 487,
+ TINT72_IRQn = 488,
+ TINT73_IRQn = 489,
+ TINT74_IRQn = 490,
+ TINT75_IRQn = 491,
+ TINT76_IRQn = 492,
+ TINT77_IRQn = 493,
+ TINT78_IRQn = 494,
+ TINT79_IRQn = 495,
+ TINT80_IRQn = 496,
+ TINT81_IRQn = 497,
+ TINT82_IRQn = 498,
+ TINT83_IRQn = 499,
+ TINT84_IRQn = 500,
+ TINT85_IRQn = 501,
+ TINT86_IRQn = 502,
+ TINT87_IRQn = 503,
+ TINT88_IRQn = 504,
+ TINT89_IRQn = 505,
+ TINT90_IRQn = 506,
+ TINT91_IRQn = 507,
+ TINT92_IRQn = 508,
+ TINT93_IRQn = 509,
+ TINT94_IRQn = 510,
+ TINT95_IRQn = 511,
+ TINT96_IRQn = 512,
+ TINT97_IRQn = 513,
+ TINT98_IRQn = 514,
+ TINT99_IRQn = 515,
+ TINT100_IRQn = 516,
+ TINT101_IRQn = 517,
+ TINT102_IRQn = 518,
+ TINT103_IRQn = 519,
+ TINT104_IRQn = 520,
+ TINT105_IRQn = 521,
+ TINT106_IRQn = 522,
+ TINT107_IRQn = 523,
+ TINT108_IRQn = 524,
+ TINT109_IRQn = 525,
+ TINT110_IRQn = 526,
+ TINT111_IRQn = 527,
+ TINT112_IRQn = 528,
+ TINT113_IRQn = 529,
+ TINT114_IRQn = 530,
+ TINT115_IRQn = 531,
+ TINT116_IRQn = 532,
+ TINT117_IRQn = 533,
+ TINT118_IRQn = 534,
+ TINT119_IRQn = 535,
+ TINT120_IRQn = 536,
+ TINT121_IRQn = 537,
+ TINT122_IRQn = 538,
+ TINT123_IRQn = 539,
+ TINT124_IRQn = 540,
+ TINT125_IRQn = 541,
+ TINT126_IRQn = 542,
+ TINT127_IRQn = 543,
+ TINT128_IRQn = 544,
+ TINT129_IRQn = 545,
+ TINT130_IRQn = 546,
+ TINT131_IRQn = 547,
+ TINT132_IRQn = 548,
+ TINT133_IRQn = 549,
+ TINT134_IRQn = 550,
+ TINT135_IRQn = 551,
+ TINT136_IRQn = 552,
+ TINT137_IRQn = 553,
+ TINT138_IRQn = 554,
+ TINT139_IRQn = 555,
+ TINT140_IRQn = 556,
+ TINT141_IRQn = 557,
+ TINT142_IRQn = 558,
+ TINT143_IRQn = 559,
+ TINT144_IRQn = 560,
+ TINT145_IRQn = 561,
+ TINT146_IRQn = 562,
+ TINT147_IRQn = 563,
+ TINT148_IRQn = 564,
+ TINT149_IRQn = 565,
+ TINT150_IRQn = 566,
+ TINT151_IRQn = 567,
+ TINT152_IRQn = 568,
+ TINT153_IRQn = 569,
+ TINT154_IRQn = 570,
+ TINT155_IRQn = 571,
+ TINT156_IRQn = 572,
+ TINT157_IRQn = 573,
+ TINT158_IRQn = 574,
+ TINT159_IRQn = 575,
+ TINT160_IRQn = 576,
+ TINT161_IRQn = 577,
+ TINT162_IRQn = 578,
+ TINT163_IRQn = 579,
+ TINT164_IRQn = 580,
+ TINT165_IRQn = 581,
+ TINT166_IRQn = 582,
+ TINT167_IRQn = 583,
+ TINT168_IRQn = 584,
+ TINT169_IRQn = 585,
+ TINT170_IRQn = 586
+
+} IRQn_Type;
+
+#define RZ_A1_IRQ_MAX TINT170_IRQn
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+
+#define RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
+#define RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */
+#define RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */
+#define RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */
+#define RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */
+#define RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */
+#define RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */
+#define RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */
+#define RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */
+#define RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
+#define RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
+#define RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
+#define RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
+#define RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */
+#define RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */
+#define RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */
+#define RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */
+#define RZ_A1_PRIVATE_TIMER (0x00000600UL + 0x82000000UL) /*!< (PTIM ) Base Address */
+#define GIC_DISTRIBUTOR_BASE RZ_A1_GIC_DISTRIBUTOR_BASE
+#define GIC_INTERFACE_BASE RZ_A1_GIC_INTERFACE_BASE
+#define L2C_310_BASE RZ_A1_PL310_BASE
+#define TIMER_BASE RZ_A1_PRIVATE_TIMER
+
+/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */
+#define __CA_REV 0x0000U /*!< Core revision r0p0 */
+#define __CORTEX_A 9U /*!< Cortex-A9 Core */
+#if (__FPU_PRESENT != 1)
+#undef __FPU_PRESENT
+#define __FPU_PRESENT 1U /* FPU present */
+#endif
+#define __GIC_PRESENT 1U /* GIC present */
+#define __TIM_PRESENT 0U /* TIM present */
+#define __L2C_PRESENT 1U /* L2C present */
+
+#include "core_ca.h"
+#include "nvic_wrapper.h"
+#include <system_VK_RZ_A1H.h>
+#include "iodefine.h"
+
+/******************************************************************************/
+/* Clock Settings */
+/******************************************************************************/
+/*
+ * Clock Mode 0 settings
+ * SW1-4(MD_CLK):ON
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1035
+ * CLKEN2 = 0b - unstable
+ * CLKEN[1:0]=01b - Output, Low, Low
+ * IFC[1:0] =00b - CPU clock is 1/1 PLL clock
+ * FRQCR2=0x0001
+ * GFC[1:0] =01b - Graphic clock is 2/3 bus clock
+ */
+#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u)
+#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u)
+#define CM0_RENESAS_RZ_A1_I_CLK (400000000u)
+#define CM0_RENESAS_RZ_A1_G_CLK (266666666u)
+#define CM0_RENESAS_RZ_A1_B_CLK (133333333u)
+#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
+#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
+
+/*
+ * Clock Mode 1 settings
+ * SW1-4(MD_CLK):OFF
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1335
+ * CLKEN2 = 0b - unstable
+ * CLKEN[1:0]=01b - Output, Low, Low
+ * IFC[1:0] =11b - CPU clock is 1/3 PLL clock
+ * FRQCR2=0x0003
+ * GFC[1:0] =11b - graphic clock is 1/3 bus clock
+ */
+#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u)
+#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u)
+#define CM1_RENESAS_RZ_A1_I_CLK (128000000u)
+#define CM1_RENESAS_RZ_A1_G_CLK (128000000u)
+#define CM1_RENESAS_RZ_A1_B_CLK (128000000u)
+#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
+#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
+
+/******************************************************************************/
+/* CPG Settings */
+/******************************************************************************/
+#define CPG_FRQCR_SHIFT_CKOEN2 (14)
+#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
+#define CPG_FRQCR_SHIFT_CKOEN0 (12)
+#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
+#define CPG_FRQCR_SHIFT_IFC (8)
+#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC)
+
+#define CPG_FRQCR2_SHIFT_GFC (0)
+#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC)
+
+
+#define CPG_STBCR1_BIT_STBY (0x80u)
+#define CPG_STBCR1_BIT_DEEP (0x40u)
+#define CPG_STBCR2_BIT_HIZ (0x80u)
+#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */
+#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */
+#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */
+#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */
+#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */
+#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */
+#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */
+#define CPG_STBCR3_BIT_MSTP31 (0x02u) /* A/D converter (analog voltage) */
+#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */
+#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */
+#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */
+#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */
+#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */
+#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */
+#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */
+#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */
+#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */
+#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */
+#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */
+#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */
+#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */
+#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */
+#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */
+#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
+#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
+#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* A/D converter (clock) */
+#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */
+#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */
+#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */
+#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range compression0 */
+#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range compression1 */
+#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */
+#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */
+#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */
+#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */
+#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ethernet */
+#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */
+#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */
+#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */
+#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */
+#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */
+#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */
+#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */
+#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */
+#define CPG_STBCR8_BIT_MSTP82 (0x04u) /* EthernetAVB */
+#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */
+#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */
+#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */
+#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */
+#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */
+#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */
+#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */
+#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */
+#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */
+#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
+#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
+#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
+#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
+#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
+#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
+#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
+#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
+#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
+#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
+#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
+#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
+#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
+#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
+#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
+#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
+#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
+#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
+#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */
+#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */
+#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
+#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
+#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
+#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
+#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
+#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
+#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
+#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
+#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
+#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */
+#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */
+#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */
+#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */
+#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */
+#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */
+#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */
+#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */
+#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */
+#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */
+#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */
+#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */
+#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */
+#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */
+#define CPG_CPUSTS_BIT_ISBUSY (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */
+#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */
+#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */
+#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */
+#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */
+#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */
+#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */
+#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */
+#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */
+#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */
+#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */
+#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */
+#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */
+#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */
+#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */
+#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */
+#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */
+#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */
+#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */
+#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */
+#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */
+#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */
+#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */
+#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */
+#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */
+#define CPG_RRAMKP_BIT_RRAMKP3 (0x08u) /* RRAM KP Page3 */
+#define CPG_RRAMKP_BIT_RRAMKP2 (0x04u) /* RRAM KP Page2 */
+#define CPG_RRAMKP_BIT_RRAMKP1 (0x02u) /* RRAM KP Page1 */
+#define CPG_RRAMKP_BIT_RRAMKP0 (0x01u) /* RRAM KP Page0 */
+#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */
+#define CPG_DSCTR_BIT_RAMBOOT (0x40u) /* Selection of Method after Returning from Deep Standby Mode */
+#define CPG_DSSSR_BIT_P6_2 (0x4000u) /* P6_2 */
+#define CPG_DSSSR_BIT_P3_9 (0x2000u) /* P3_9 */
+#define CPG_DSSSR_BIT_P3_1 (0x1000u) /* P3_1 */
+#define CPG_DSSSR_BIT_P2_12 (0x0800u) /* P2_12 */
+#define CPG_DSSSR_BIT_P8_7 (0x0400u) /* P8_7 */
+#define CPG_DSSSR_BIT_P3_3 (0x0200u) /* P3_3 */
+#define CPG_DSSSR_BIT_NMI (0x0100u) /* NMI */
+#define CPG_DSSSR_BIT_RTCAR (0x0040u) /* RTCAR */
+#define CPG_DSSSR_BIT_P6_4 (0x0020u) /* P6_4 */
+#define CPG_DSSSR_BIT_P5_9 (0x0010u) /* P5_9 */
+#define CPG_DSSSR_BIT_P7_8 (0x0008u) /* P7_8 */
+#define CPG_DSSSR_BIT_P2_15 (0x0004u) /* P2_15 */
+#define CPG_DSSSR_BIT_P9_1 (0x0002u) /* P9_1 */
+#define CPG_DSSSR_BIT_P8_2 (0x0001u) /* P8_2 */
+#define CPG_DSESR_BIT_P6_2E (0x4000u) /* P6_2 */
+#define CPG_DSESR_BIT_P3_9E (0x2000u) /* P3_9 */
+#define CPG_DSESR_BIT_P3_1E (0x1000u) /* P3_1 */
+#define CPG_DSESR_BIT_P2_12E (0x0800u) /* P2_12 */
+#define CPG_DSESR_BIT_P8_7E (0x0400u) /* P8_7 */
+#define CPG_DSESR_BIT_P3_3E (0x0200u) /* P3_3 */
+#define CPG_DSESR_BIT_NMIE (0x0100u) /* NMI */
+#define CPG_DSESR_BIT_P6_4E (0x0020u) /* P6_4 */
+#define CPG_DSESR_BIT_P5_9E (0x0010u) /* P5_9 */
+#define CPG_DSESR_BIT_P7_8E (0x0008u) /* P7_8 */
+#define CPG_DSESR_BIT_P2_15E (0x0004u) /* P2_15 */
+#define CPG_DSESR_BIT_P9_1E (0x0002u) /* P9_1 */
+#define CPG_DSESR_BIT_P8_2E (0x0001u) /* P8_2 */
+#define CPG_DSFR_BIT_IOKEEP (0x8000u) /* Release of Pin State Retention */
+#define CPG_DSFR_BIT_P6_2F (0x4000u) /* P6_2 */
+#define CPG_DSFR_BIT_P3_9F (0x2000u) /* P3_9 */
+#define CPG_DSFR_BIT_P3_1F (0x1000u) /* P3_1 */
+#define CPG_DSFR_BIT_P2_12F (0x0800u) /* P2_12 */
+#define CPG_DSFR_BIT_P8_7F (0x0400u) /* P8_7 */
+#define CPG_DSFR_BIT_P3_3F (0x0200u) /* P3_3 */
+#define CPG_DSFR_BIT_NMIF (0x0100u) /* NMI */
+#define CPG_DSFR_BIT_RTCARF (0x0040u) /* RTCAR */
+#define CPG_DSFR_BIT_P6_4F (0x0020u) /* P6_4 */
+#define CPG_DSFR_BIT_P5_9F (0x0010u) /* P5_9 */
+#define CPG_DSFR_BIT_P7_8F (0x0008u) /* P7_8 */
+#define CPG_DSFR_BIT_P2_15F (0x0004u) /* P2_15 */
+#define CPG_DSFR_BIT_P9_1F (0x0002u) /* P9_1 */
+#define CPG_DSFR_BIT_P8_2F (0x0001u) /* P8_2 */
+#define CPG_XTALCTR_BIT_GAIN1 (0x02u) /* RTC_X3, RTC_X4 */
+#define CPG_XTALCTR_BIT_GAIN0 (0x01u) /* EXTAL, XTAL */
+
+/******************************************************************************/
+/* GPIO Settings */
+/******************************************************************************/
+#define GPIO_BIT_N0 (1u << 0)
+#define GPIO_BIT_N1 (1u << 1)
+#define GPIO_BIT_N2 (1u << 2)
+#define GPIO_BIT_N3 (1u << 3)
+#define GPIO_BIT_N4 (1u << 4)
+#define GPIO_BIT_N5 (1u << 5)
+#define GPIO_BIT_N6 (1u << 6)
+#define GPIO_BIT_N7 (1u << 7)
+#define GPIO_BIT_N8 (1u << 8)
+#define GPIO_BIT_N9 (1u << 9)
+#define GPIO_BIT_N10 (1u << 10)
+#define GPIO_BIT_N11 (1u << 11)
+#define GPIO_BIT_N12 (1u << 12)
+#define GPIO_BIT_N13 (1u << 13)
+#define GPIO_BIT_N14 (1u << 14)
+#define GPIO_BIT_N15 (1u << 15)
+
+#define MD_BOOT10_MASK (0x3)
+
+#define MD_BOOT10_BM0 (0x0)
+#define MD_BOOT10_BM1 (0x2)
+#define MD_BOOT10_BM3 (0x1)
+#define MD_BOOT10_BM4_5 (0x3)
+
+#define MD_CLK (1u << 2)
+#define MD_CLKS (1u << 3)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __VK_RZ_A1H_H__
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h Mon Mar 18 16:54:40 2019 +0000 @@ -0,0 +1,75 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) +******************************************************************************/ +#ifndef R7S721000_IODEFINE_H +#define R7S721000_IODEFINE_H + +#include "iodefines/iodefine_typedef.h" /* (V2.00h) */ + +#include "iodefines/adc_iodefine.h" /* (V2.00h) */ +#include "iodefines/bsc_iodefine.h" /* (V2.00h) */ +#include "iodefines/ceu_iodefine.h" /* (V2.00h) */ +#include "iodefines/cpg_iodefine.h" /* (V2.00h) */ +#include "iodefines/disc_iodefine.h" /* (V2.00h) */ +#include "iodefines/dmac_iodefine.h" /* (V2.00h) */ +#include "iodefines/dvdec_iodefine.h" /* (V2.00h) */ +#include "iodefines/ether_iodefine.h" /* (V2.00h) */ +#include "iodefines/flctl_iodefine.h" /* (V2.00h) */ +#include "iodefines/gpio_iodefine.h" /* (V2.00h) */ +#include "iodefines/ieb_iodefine.h" /* (V2.00h) */ +#include "iodefines/inb_iodefine.h" /* (V2.00h) */ +#include "iodefines/intc_iodefine.h" /* (V2.00h) */ +#include "iodefines/irda_iodefine.h" /* (V2.00h) */ +#include "iodefines/jcu_iodefine.h" /* (V2.00h) */ +#include "iodefines/l2c_iodefine.h" /* (V2.00h) */ +#include "iodefines/lin_iodefine.h" /* (V2.00h) */ +#include "iodefines/lvds_iodefine.h" /* (V2.00h) */ +#include "iodefines/mlb_iodefine.h" /* (V2.00h) */ +#include "iodefines/mmc_iodefine.h" /* (V2.00h) */ +#include "iodefines/mtu2_iodefine.h" /* (V2.00h) */ +#include "iodefines/ostm_iodefine.h" /* (V2.00h) */ +#include "iodefines/pfv_iodefine.h" /* (V2.00h) */ +#include "iodefines/pwm_iodefine.h" /* (V2.00h) */ +#include "iodefines/riic_iodefine.h" /* (V2.00h) */ +#include "iodefines/romdec_iodefine.h" /* (V2.00h) */ +#include "iodefines/rscan0_iodefine.h" /* (V2.00h) */ +#include "iodefines/rspi_iodefine.h" /* (V2.00h) */ +#include "iodefines/rtc_iodefine.h" /* (V2.00h) */ +#include "iodefines/scif_iodefine.h" /* (V2.00h) */ +#include "iodefines/scim_iodefine.h" /* (V2.00h) */ +#include "iodefines/scux_iodefine.h" /* (V2.00h) */ +#include "iodefines/sdg_iodefine.h" /* (V2.00h) */ +#include "iodefines/sdhi_iodefine.h" /* */ +#include "iodefines/spdif_iodefine.h" /* (V2.00h) */ +#include "iodefines/spibsc_iodefine.h" /* (V2.00h) */ +#include "iodefines/ssif_iodefine.h" /* (V2.00h) */ +#include "iodefines/usb20_iodefine.h" /* (V2.00h) */ +#include "iodefines/vdc5_iodefine.h" /* (V2.00h) */ +#include "iodefines/wdt_iodefine.h" /* (V2.00h) */ +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/targets/targets.json Mon Mar 18 16:54:40 2019 +0000
@@ -0,0 +1,8275 @@
+{
+ "Target": {
+ "core": null,
+ "default_toolchain": "ARM",
+ "supported_toolchains": null,
+ "extra_labels": [],
+ "components": ["PSA_SRV_IMPL", "PSA_SRV_EMUL", "NSPE"],
+ "is_disk_virtual": false,
+ "macros": [],
+ "device_has": [],
+ "features": [],
+ "detect_code": [],
+ "public": false,
+ "default_lib": "std",
+ "bootloader_supported": false,
+ "static_memory_defines": true,
+ "config": {
+ "console-uart-flow-control": {
+ "help": "Console hardware flow control. Options: null, RTS, CTS, RTSCTS.",
+ "value": null
+ },
+ "network-default-interface-type": {
+ "help": "Default network interface type. Typical options: null, ETHERNET, WIFI, CELLULAR, MESH",
+ "value": null
+ },
+ "deep-sleep-latency": {
+ "help": "Time in ms required to go to and wake up from deep sleep (max 10)",
+ "value": 0
+ },
+ "boot-stack-size": {
+ "help": "Define the boot stack size in bytes. This value must be a multiple of 8",
+ "value": "0x1000"
+ },
+ "mpu-rom-end": {
+ "help": "Last address of ROM protected by the MPU",
+ "value": "0x0fffffff"
+ }
+ }
+ },
+ "PSA_Target": {
+ "public": false,
+ "config": {
+ "secure-rom-start": {
+ "help": "Starting address of Secure ROM",
+ "value": null,
+ "macro_name": "PSA_SECURE_ROM_START",
+ "conflicts": ["target.mbed_rom_start"]
+ },
+ "secure-rom-size": {
+ "help": "Size in bytes of Secure ROM",
+ "value": null,
+ "macro_name": "PSA_SECURE_ROM_SIZE",
+ "conflicts": ["target.mbed_rom_size"]
+ },
+ "non-secure-rom-start": {
+ "help": "Starting address of Non-secure ROM",
+ "value": null,
+ "macro_name": "PSA_NON_SECURE_ROM_START",
+ "conflicts": ["target.mbed_rom_start"]
+ },
+ "non-secure-rom-size": {
+ "help": "Size in bytes of Non-secure ROM",
+ "value": null,
+ "macro_name": "PSA_NON_SECURE_ROM_SIZE",
+ "conflicts": ["target.mbed_rom_size"]
+ },
+ "secure-ram-start": {
+ "help": "Starting address of Secure RAM",
+ "value": null,
+ "macro_name": "PSA_SECURE_RAM_START",
+ "conflicts": ["target.mbed_ram_start"]
+ },
+ "secure-ram-size": {
+ "help": "Size in bytes of Secure RAM",
+ "value": null,
+ "macro_name": "PSA_SECURE_RAM_SIZE",
+ "conflicts": ["target.mbed_ram_size"]
+ },
+ "non-secure-ram-start": {
+ "help": "Starting address of Non-secure RAM",
+ "value": null,
+ "macro_name": "PSA_NON_SECURE_RAM_START",
+ "conflicts": ["target.mbed_ram_start"]
+ },
+ "non-secure-ram-size": {
+ "help": "Size in bytes of Non-secure RAM",
+ "value": null,
+ "macro_name": "PSA_NON_SECURE_RAM_SIZE",
+ "conflicts": ["target.mbed_ram_size"]
+ },
+ "shared-ram-start": {
+ "help": "Starting address of Shared RAM between Secure and Non-secure worlds",
+ "value": null,
+ "macro_name": "PSA_SHARED_RAM_START"
+ },
+ "shared-ram-size": {
+ "help": "Size in bytes of Shared RAM between Secure and Non-secure worlds",
+ "value": null,
+ "macro_name": "PSA_SHARED_RAM_SIZE"
+ }
+ }
+ },
+ "NSPE_Target": {
+ "inherits": ["PSA_Target"],
+ "components": ["PSA_SRV_IPC", "NSPE"],
+ "device_has_add": ["TRNG"],
+ "public": false
+ },
+ "SPE_Target": {
+ "inherits": ["PSA_Target"],
+ "components": ["PSA_SRV_IMPL", "PSA_SRV_IPC", "SPE"],
+ "public": false
+ },
+ "CM4_UARM": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "default_toolchain": "uARM",
+ "public": false,
+ "supported_toolchains": ["uARM"],
+ "default_lib": "small"
+ },
+ "CM4_ARM": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "public": false,
+ "supported_toolchains": ["ARM"]
+ },
+ "CM4F_UARM": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "default_toolchain": "uARM",
+ "public": false,
+ "supported_toolchains": ["uARM"],
+ "default_lib": "small"
+ },
+ "CM4F_ARM": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "public": false,
+ "supported_toolchains": ["ARM"]
+ },
+ "LPCTarget": {
+ "inherits": ["Target"],
+ "post_binary_hook": { "function": "LPCTargetCode.lpc_patch" },
+ "public": false
+ },
+ "LPC11C24": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11CXX"],
+ "OUTPUT_EXT": "hex",
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "device_has": [
+ "ANALOGIN",
+ "CAN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "device_name": "LPC11C24FBD48/301"
+ },
+ "LPC1114": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11XX"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC1114FN28/102"
+ },
+ "LPC11U24": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX", "LPC11U24_401"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "detect_code": ["1040"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "LOCALFILESYSTEM",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SEMIHOST",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC11U24FBD48/401"
+ },
+ "OC_MBUINO": {
+ "inherits": ["LPC11U24"],
+ "macros": [
+ "TARGET_LPC11U24",
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "extra_labels": ["NXP", "LPC11UXX"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "release_versions": ["2"]
+ },
+ "LPC11U24_301": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "extra_labels": ["NXP", "LPC11UXX"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "LOCALFILESYSTEM",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SEMIHOST",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "device_name": "LPC11U24FHI33/301"
+ },
+ "LPC11U34_421": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "default_lib": "small",
+ "device_name": "LPC11U34FBD48/311"
+ },
+ "MICRONFCBOARD": {
+ "inherits": ["LPC11U34_421"],
+ "macros_add": ["LPC11U34_421", "APPNEARME_MICRONFCBOARD"],
+ "extra_labels_add": ["APPNEARME_MICRONFCBOARD"],
+ "release_versions": ["2"],
+ "device_name": "LPC11U34FBD48/311"
+ },
+ "LPC11U35_401": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC11U35FBD48/401"
+ },
+ "LPC11U35_501": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC11U35FHI33/501"
+ },
+ "LPC11U35_501_IBDAP": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "default_lib": "small",
+ "device_name": "LPC11U35FHI33/501"
+ },
+ "XADOW_M0": {
+ "inherits": ["LPC11U35_501"]
+ },
+ "LPC11U35_Y5_MBUG": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "default_lib": "small",
+ "device_name": "LPC11U35FHI33/501"
+ },
+ "LPC11U37_501": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "default_lib": "small",
+ "device_name": "LPC11U37FBD64/501"
+ },
+ "LPCCAPPUCCINO": {
+ "inherits": ["LPC11U37_501"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "device_name": "LPC11U37FBD64/501"
+ },
+ "ARCH_GPRS": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX", "LPC11U37_501"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "inherits": ["LPCTarget"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC11U37FBD64/501"
+ },
+ "LPC11U68": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11U6X"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "inherits": ["LPCTarget"],
+ "detect_code": ["1168"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC11U68JBD100"
+ },
+ "LPC1347": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M3",
+ "extra_labels": ["NXP", "LPC13XX"],
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "release_versions": ["2"],
+ "device_name": "LPC1347FBD48"
+ },
+ "LPC1549": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M3",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC15XX"],
+ "supported_toolchains": ["uARM", "GCC_ARM", "IAR"],
+ "inherits": ["LPCTarget"],
+ "detect_code": ["1549"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "CAN",
+ "I2C",
+ "INTERRUPTIN",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC1549JBD64"
+ },
+ "LPC1768": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M3",
+ "extra_labels": ["NXP", "LPC176X", "MBED_LPC1768", "NXP_EMAC"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "detect_code": ["1010"],
+ "device_has": [
+ "RTC",
+ "USTICKER",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "CAN",
+ "DEBUG_AWARENESS",
+ "EMAC",
+ "ETHERNET",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "LOCALFILESYSTEM",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SEMIHOST",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "LPC1768",
+ "bootloader_supported": true,
+ "config": {
+ "us-ticker-timer": {
+ "help": "Chooses which timer (0-3) to use for us_ticker.c",
+ "value": 3
+ }
+ },
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "LPC1769": {
+ "inherits": ["LPC1768"],
+ "device_name": "LPC1769"
+ },
+ "ARCH_PRO": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["NXP", "LPC176X", "NXP_EMAC"],
+ "macros": ["TARGET_LPC1768"],
+ "inherits": ["LPCTarget"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "CAN",
+ "DEBUG_AWARENESS",
+ "EMAC",
+ "ETHERNET",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "LPC1768",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "UBLOX_C027": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["NXP", "LPC176X", "NXP_EMAC"],
+ "config": {
+ "modem_is_on_board": {
+ "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD"
+ },
+ "modem_data_connection_type": {
+ "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD_UART"
+ }
+ },
+ "macros": ["TARGET_LPC1768"],
+ "inherits": ["LPCTarget"],
+ "device_has": [
+ "USTICKER",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "CAN",
+ "DEBUG_AWARENESS",
+ "EMAC",
+ "ETHERNET",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "LPC1768",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "CELLULAR"
+ }
+ },
+ "XBED_LPC1768": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["NXP", "LPC176X", "XBED_LPC1768"],
+ "macros": ["TARGET_LPC1768"],
+ "detect_code": ["1010"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "CAN",
+ "DEBUG_AWARENESS",
+ "ETHERNET",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "LOCALFILESYSTEM",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SEMIHOST",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "FLASH",
+ "MPU"
+ ],
+ "device_name": "LPC1768"
+ },
+ "LPC810": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC81X"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["uARM", "IAR", "GCC_ARM"],
+ "device_has": [
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "default_lib": "small",
+ "device_name": "LPC810M021FN8"
+ },
+ "LPC812": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC81X"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["uARM", "IAR", "GCC_ARM"],
+ "inherits": ["LPCTarget"],
+ "detect_code": ["1050"],
+ "device_has": [
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC812M101JDH20"
+ },
+ "LPC824": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC82X"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["uARM", "GCC_ARM", "IAR"],
+ "inherits": ["LPCTarget"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC824M201JDH20"
+ },
+ "SSCI824": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC82X"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["uARM", "GCC_ARM"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"]
+ },
+ "MCU_LPC4088": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M4F",
+ "extra_labels": ["NXP", "LPC408X", "NXP_EMAC"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "post_binary_hook": {
+ "function": "LPC4088Code.binary_hook"
+ },
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "CAN",
+ "DEBUG_AWARENESS",
+ "EMAC",
+ "ETHERNET",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "MPU"
+ ],
+ "device_name": "LPC4088FBD144",
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "LPC4088": {
+ "inherits": ["MCU_LPC4088"],
+ "release_versions": ["2", "5"]
+ },
+ "LPC4088_DM": {
+ "inherits": ["MCU_LPC4088"],
+ "release_versions": ["2", "5"]
+ },
+ "LPC4330_M4": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M4F",
+ "extra_labels": ["NXP", "LPC43XX", "LPC4330"],
+ "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "DEBUG_AWARENESS",
+ "ETHERNET",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "MPU"
+ ],
+ "device_name": "LPC4330"
+ },
+ "LPC4330_M0": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "extra_labels": ["NXP", "LPC43XX", "LPC4330"],
+ "supported_toolchains": ["ARM", "IAR"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "DEBUG_AWARENESS",
+ "ETHERNET",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ]
+ },
+ "LPC4337": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M4F",
+ "extra_labels": ["NXP", "LPC43XX", "LPC4337"],
+ "supported_toolchains": ["ARM"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "DEBUG_AWARENESS",
+ "ETHERNET",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "MPU"
+ ],
+ "release_versions": ["2"],
+ "device_name": "LPC4337"
+ },
+ "LPC1800": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M3",
+ "extra_labels": ["NXP", "LPC43XX"],
+ "public": false,
+ "supported_toolchains": ["ARM", "IAR"]
+ },
+ "LPC11U37H_401": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+ "inherits": ["LPCTarget"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC11U37HFBD64/401"
+ },
+ "ELEKTOR_COCORICO": {
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC81X"],
+ "supported_toolchains": ["uARM", "GCC_ARM", "IAR"],
+ "inherits": ["LPCTarget"],
+ "is_disk_virtual": true,
+ "detect_code": ["C000"],
+ "default_lib": "small",
+ "device_name": "LPC812M101JDH16"
+ },
+ "KL05Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["Freescale", "KLXX"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "inherits": ["Target"],
+ "device_has": [
+ "USTICKER",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SEMIHOST",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "MKL05Z32xxx4"
+ },
+ "KL25Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "extra_labels": ["Freescale", "KLXX"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "inherits": ["Target"],
+ "detect_code": ["0200"],
+ "device_has": [
+ "USTICKER",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SEMIHOST",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "MKL25Z128xxx4"
+ },
+ "KL26Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "extra_labels": ["Freescale", "KLXX"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "inherits": ["Target"],
+ "device_has": [
+ "USTICKER",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SEMIHOST",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "device_name": "MKL26Z128xxx4"
+ },
+ "KL46Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "extra_labels": ["Freescale", "KLXX", "FLASH_CMSIS_ALGO"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "inherits": ["Target"],
+ "detect_code": ["0220"],
+ "device_has": [
+ "USTICKER",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SEMIHOST",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "FLASH"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "MKL46Z256xxx4",
+ "bootloader_supported": true
+ },
+ "K20D50M": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "extra_labels": ["Freescale", "K20XX"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "detect_code": ["0230"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SEMIHOST",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "release_versions": ["2"],
+ "device_name": "MK20DX128xxx5"
+ },
+ "TEENSY3_1": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "extra_labels": ["Freescale", "K20XX", "K20DX256"],
+ "OUTPUT_EXT": "hex",
+ "is_disk_virtual": true,
+ "supported_toolchains": ["GCC_ARM", "ARM"],
+ "post_binary_hook": {
+ "function": "TEENSY3_1Code.binary_hook",
+ "toolchains": ["ARM_STD", "ARM_MICRO", "GCC_ARM"]
+ },
+ "detect_code": ["0230"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SEMIHOST",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "release_versions": ["2"],
+ "device_name": "MK20DX256xxx7"
+ },
+ "MCU_K22F512": {
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": [
+ "Freescale",
+ "MCUXpresso_MCUS",
+ "KSDK2_MCUS",
+ "MCU_K22F",
+ "MCU_K22F512",
+ "FRDM",
+ "KPSDK_MCUS",
+ "KPSDK_CODE"
+ ],
+ "is_disk_virtual": true,
+ "public": false,
+ "macros": ["CPU_MK22FN512VLH12", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "detect_code": ["0231"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "TRNG",
+ "FLASH"
+ ],
+ "device_name": "MK22DN512xxx5"
+ },
+ "K22F": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_K22F512"],
+ "release_versions": ["2", "5"],
+ "extra_labels_add": ["FRDM"]
+ },
+ "KL27Z": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0+",
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+ "macros": ["CPU_MKL27Z64VLH4", "FSL_RTOS_MBED"],
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "supported_form_factors": ["ARDUINO"],
+ "is_disk_virtual": true,
+ "default_toolchain": "ARM",
+ "detect_code": ["0261"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "default_lib": "std",
+ "release_versions": ["2"],
+ "device_name": "MKL27Z64xxx4"
+ },
+ "KL43Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+ "macros": ["CPU_MKL43Z256VLH4", "FSL_RTOS_MBED"],
+ "is_disk_virtual": true,
+ "inherits": ["Target"],
+ "detect_code": ["0262"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SEMIHOST",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "FLASH"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "MKL43Z256xxx4"
+ },
+ "KL82Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+ "macros": ["CPU_MKL82Z128VLK7", "FSL_RTOS_MBED"],
+ "is_disk_virtual": true,
+ "inherits": ["Target"],
+ "detect_code": ["0218"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SEMIHOST",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "TRNG",
+ "FLASH",
+ "QSPI"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "MKL82Z128xxx7"
+ },
+ "USENSE": {
+ "inherits": ["KL82Z"],
+ "extra_labels_remove": ["FRDM"],
+ "device_has_remove": ["QSPI"],
+ "supported_form_factors": []
+ },
+ "KW24D": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+ "is_disk_virtual": true,
+ "macros": ["CPU_MKW24D512VHA5", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "detect_code": ["0250"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "TRNG",
+ "FLASH",
+ "802_15_4_PHY"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "MKW24D512xxx5",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "MESH"
+ }
+ },
+ "KW41Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM", "FRAMEWORK_5_3_3", "NXP"],
+ "is_disk_virtual": true,
+ "macros": ["CPU_MKW41Z512VHT4", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "detect_code": ["0201"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "TRNG",
+ "STDIO_MESSAGES",
+ "FLASH",
+ "802_15_4_PHY"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "MKW41Z512xxx4",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "MESH"
+ }
+ },
+ "MCU_K24F1M": {
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": [
+ "Freescale",
+ "MCUXpresso_MCUS",
+ "KSDK2_MCUS",
+ "MCU_K24F",
+ "KPSDK_MCUS",
+ "KPSDK_CODE"
+ ],
+ "is_disk_virtual": true,
+ "public": false,
+ "macros": ["CPU_MK24FN1M0VDC12", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "TRNG",
+ "FLASH"
+ ],
+ "device_name": "MK24FN1M0xxx12"
+ },
+ "RO359B": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_K24F1M"],
+ "detect_code": ["1022"],
+ "release_versions": ["2", "5"]
+ },
+ "K64F": {
+ "supported_form_factors": ["ARDUINO"],
+ "components_add": ["SD", "FLASHIAP"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": [
+ "Freescale",
+ "MCUXpresso_MCUS",
+ "KSDK2_MCUS",
+ "FRDM",
+ "KPSDK_MCUS",
+ "KPSDK_CODE",
+ "MCU_K64F",
+ "Freescale_EMAC",
+ "PSA"
+ ],
+ "is_disk_virtual": true,
+ "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "MBEDTLS_PSA_CRYPTO_C"],
+ "inherits": ["Target"],
+ "detect_code": ["0240"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "CRC",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "EMAC",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "STORAGE",
+ "TRNG",
+ "FLASH"
+ ],
+ "features": ["STORAGE"],
+ "release_versions": ["2", "5"],
+ "device_name": "MK64FN1M0xxx12",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "SDT64B": {
+ "inherits": ["K64F"],
+ "extra_labels_add": ["K64F"],
+ "extra_labels_remove": ["FRDM"],
+ "components_remove": ["SD"],
+ "supported_form_factors": [],
+ "detect_code": ["3105"]
+ },
+ "EV_COG_AD4050LZ": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "macros": ["__ADUCM4050__", "EV_COG_AD4050LZ"],
+ "extra_labels": [
+ "Analog_Devices",
+ "ADUCM4X50",
+ "ADUCM4050",
+ "EV_COG_AD4050LZ",
+ "FLASH_CMSIS_ALGO"
+ ],
+ "device_has": [
+ "FLASH",
+ "USTICKER",
+ "RTC",
+ "SERIAL",
+ "STDIO_MESSAGES",
+ "TRNG",
+ "SLEEP",
+ "INTERRUPTIN",
+ "SPI",
+ "I2C",
+ "ANALOGIN",
+ "MPU"
+ ],
+ "device_name": "ADuCM4050",
+ "detect_code": ["0603"],
+ "release_versions": ["5"],
+ "bootloader_supported": true
+ },
+ "EV_COG_AD3029LZ": {
+ "inherits": ["Target"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "macros": ["__ADUCM3029__", "EV_COG_AD3029LZ"],
+ "extra_labels": [
+ "Analog_Devices",
+ "ADUCM302X",
+ "ADUCM3029",
+ "EV_COG_AD3029LZ",
+ "FLASH_CMSIS_ALGO"
+ ],
+ "device_has": [
+ "FLASH",
+ "USTICKER",
+ "RTC",
+ "SERIAL",
+ "STDIO_MESSAGES",
+ "TRNG",
+ "SLEEP",
+ "INTERRUPTIN",
+ "SPI",
+ "I2C",
+ "ANALOGIN",
+ "MPU"
+ ],
+ "device_name": "ADuCM3029",
+ "detect_code": ["0602"],
+ "release_versions": ["5"],
+ "bootloader_supported": true
+ },
+ "MTS_GAMBIT": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM"],
+ "extra_labels": [
+ "Freescale",
+ "MCUXpresso_MCUS",
+ "KSDK2_MCUS",
+ "KPSDK_MCUS",
+ "KPSDK_CODE",
+ "MCU_K64F"
+ ],
+ "is_disk_virtual": true,
+ "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "FLASH"
+ ],
+ "device_name": "MK64FN1M0xxx12"
+ },
+ "HEXIWEAR": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "extra_labels": [
+ "Freescale",
+ "MCUXpresso_MCUS",
+ "KSDK2_MCUS",
+ "MCU_K64F"
+ ],
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"],
+ "is_disk_virtual": true,
+ "default_toolchain": "ARM",
+ "detect_code": ["0214"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "TRNG",
+ "FLASH"
+ ],
+ "default_lib": "std",
+ "release_versions": ["2", "5"],
+ "device_name": "MK64FN1M0xxx12",
+ "bootloader_supported": true
+ },
+ "RAPIDIOT": {
+ "inherits": ["Target"],
+ "public": false,
+ "core": "null",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "macros": ["FSL_RTOS_MBED", "USE_EXTERNAL_RTC"],
+ "default_toolchain": "ARM",
+ "default_lib": "std",
+ "forced_reset_timeout": 7,
+ "release_versions": ["2", "5"]
+ },
+ "RAPIDIOT_K64F": {
+ "inherits": ["RAPIDIOT"],
+ "core": "Cortex-M4F",
+ "extra_labels": [
+ "Freescale",
+ "MCUXpresso_MCUS",
+ "KSDK2_MCUS",
+ "MCU_K64F"
+ ],
+ "macros_add": ["CPU_MK64FN1M0VMD12", "TARGET_K64F"],
+ "is_disk_virtual": true,
+ "mbed_rom_start": "0x00014000",
+ "mbed_rom_size": "0xEC000",
+ "detect_code": ["0228"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "TRNG",
+ "FLASH"
+ ],
+ "device_name": "MK64FN1M0xxx12",
+ "bootloader_supported": true
+ },
+ "RAPIDIOT_KW41Z": {
+ "inherits": ["RAPIDIOT"],
+ "core": "Cortex-M0+",
+ "extra_labels": [
+ "Freescale",
+ "MCUXpresso_MCUS",
+ "KSDK2_MCUS",
+ "KW41Z"
+ ],
+ "macros_add": ["CPU_MKW41Z512VHT4"],
+ "is_disk_virtual": true,
+ "mbed_rom_start": "0x00004000",
+ "mbed_rom_size": "0x7C000",
+ "detect_code": ["0234"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "TRNG",
+ "STDIO_MESSAGES",
+ "FLASH"
+ ],
+ "device_name": "MKW41Z512xxx4",
+ "bootloader_supported": true
+ },
+ "K66F": {
+ "supported_form_factors": ["ARDUINO"],
+ "components_add": ["SD", "FLASHIAP"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": [
+ "Freescale",
+ "MCUXpresso_MCUS",
+ "KSDK2_MCUS",
+ "FRDM",
+ "Freescale_EMAC",
+ "PSA"
+ ],
+ "is_disk_virtual": true,
+ "macros": ["CPU_MK66FN2M0VMD18", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "detect_code": ["0311"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "EMAC",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "TRNG",
+ "FLASH"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "MK66FN2M0xxx18",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "K82F": {
+ "supported_form_factors": ["ARDUINO"],
+ "components_add": ["SPIF", "FLASHIAP"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+ "is_disk_virtual": true,
+ "macros": ["CPU_MK82FN256VDC15", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "detect_code": ["0217"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "TRNG",
+ "FLASH",
+ "QSPI"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "MK82FN256xxx15"
+ },
+ "UBRIDGE": {
+ "inherits": ["K82F"],
+ "extra_labels_remove": ["FRDM"],
+ "components_remove": ["SPIF"],
+ "device_has_remove": ["QSPI"],
+ "supported_form_factors": []
+ },
+ "FAMILY_STM32": {
+ "inherits": ["Target"],
+ "public": false,
+ "extra_labels": ["STM"],
+ "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
+ "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+ "config": {
+ "lse_available": {
+ "help": "Define if a Low Speed External xtal (LSE) is available on the board (0 = No, 1 = Yes). If Yes, the LSE will be used to clock the RTC, LPUART, ... otherwise the Low Speed Internal clock (LSI) will be used",
+ "value": "1"
+ },
+ "lpuart_clock_source": {
+ "help": "Define the LPUART clock source. Mask values: USE_LPUART_CLK_LSE, USE_LPUART_CLK_PCLK1, USE_LPUART_CLK_HSI",
+ "value": "USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1"
+ },
+ "stdio_uart_tx": {
+ "help": "default TX STDIO pins is defined in PinNames.h file, but it can be overridden"
+ },
+ "stdio_uart_rx": {
+ "help": "default RX STDIO pins is defined in PinNames.h file, but it can be overridden"
+ },
+ "lpticker_delay_ticks": {
+ "help": "https://os.mbed.com/docs/latest/porting/low-power-ticker.html",
+ "value": 1,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ },
+ "lpticker_lptim_clock": {
+ "help": "Default value for LPTIM clock (lpticker_lptim == 1). Value is the dividing factor. Choose 1, 2 or 4",
+ "value": 1
+ }
+ },
+ "overrides": {
+ "deep-sleep-latency": 3
+ },
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES"
+ ]
+ },
+ "MIMXRT1050_EVK": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M7FD",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["NXP", "MCUXpresso_MCUS", "EVK", "MIMXRT1050", "IMX", "NXP_EMAC"],
+ "is_disk_virtual": true,
+ "macros": [
+ "CPU_MIMXRT1052DVL6B",
+ "FSL_RTOS_MBED",
+ "XIP_BOOT_HEADER_ENABLE=1",
+ "XIP_EXTERNAL_FLASH=1",
+ "XIP_BOOT_HEADER_DCD_ENABLE=1",
+ "SKIP_SYSCLK_INIT",
+ "FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE",
+ "SDRAM_IS_SHAREABLE",
+ "MBED_MPU_CUSTOM"
+ ],
+ "inherits": ["Target"],
+ "detect_code": ["0227"],
+ "device_has": [
+ "RTC",
+ "SLEEP",
+ "USTICKER",
+ "LPTICKER",
+ "ANALOGIN",
+ "EMAC",
+ "I2C",
+ "I2CSLAVE",
+ "ERROR_RED",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "release_versions": ["2", "5"],
+ "features": ["LWIP"],
+ "device_name": "MIMXRT1052",
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "LPC54114": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
+ "extra_labels": [
+ "NXP",
+ "MCUXpresso_MCUS",
+ "LPC54114_M4",
+ "LPCXpresso",
+ "LPC"
+ ],
+ "is_disk_virtual": true,
+ "macros": ["CPU_LPC54114J256BD64_cm4", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "detect_code": ["1054"],
+ "device_has": [
+ "USTICKER",
+ "RTC",
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "post_binary_hook": { "function": "LPCTargetCode.lpc_patch" },
+ "device_name": "LPC54114J256BD64"
+ },
+ "MCU_LPC546XX": {
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
+ "extra_labels": [
+ "NXP",
+ "MCUXpresso_MCUS",
+ "LPC",
+ "NXP_EMAC"
+ ],
+ "is_disk_virtual": true,
+ "public": false,
+ "macros": ["CPU_LPC54628J512ET180", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "device_has": [
+ "USTICKER",
+ "RTC",
+ "ANALOGIN",
+ "EMAC",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES",
+ "FLASH",
+ "TRNG",
+ "QSPI",
+ "MPU"
+ ],
+ "device_name": "LPC54628J512ET180",
+ "post_binary_hook": { "function": "LPCTargetCode.lpc_patch" },
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "LPC546XX": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_LPC546XX"],
+ "extra_labels_add": ["LPCXpresso"],
+ "detect_code": ["1056"],
+ "release_versions": ["2", "5"],
+ "components_add": ["QSPIF"]
+ },
+ "FF_LPC546XX": {
+ "inherits": ["MCU_LPC546XX"],
+ "detect_code": ["8081"],
+ "device_has_remove": ["QSPI"],
+ "release_versions": ["2", "5"]
+ },
+ "NUCLEO_F030R8": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M0",
+ "extra_labels_add": ["STM32F0", "STM32F030R8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0725"],
+ "macros_add": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "device_has_add": ["CRC"],
+ "device_has_remove": ["LPTICKER"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F030R8"
+ },
+ "NUCLEO_F031K6": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels_add": ["STM32F0", "STM32F031K6"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0791"],
+ "overrides": { "lse_available": 0 },
+ "macros_add": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "device_has_add": ["CRC"],
+ "device_has_remove": ["LPTICKER"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F031K6"
+ },
+ "NUCLEO_F042K6": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels_add": ["STM32F0", "STM32F042K6"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0785"],
+ "overrides": { "lse_available": 0 },
+ "macros_add": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "device_has_add": [
+ "CAN",
+ "CRC"
+ ],
+ "device_has_remove": ["LPTICKER"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F042K6"
+ },
+ "NUCLEO_F070RB": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M0",
+ "extra_labels_add": ["STM32F0", "STM32F070RB"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0755"],
+ "macros_add": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "device_has_add": [
+ "CRC",
+ "SERIAL_ASYNCH",
+ "FLASH"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F070RB"
+ },
+ "NUCLEO_F072RB": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M0",
+ "extra_labels_add": ["STM32F0", "STM32F072RB"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0730"],
+ "macros_add": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "FLASH"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F072RB"
+ },
+ "NUCLEO_F091RC": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M0",
+ "extra_labels_add": ["STM32F0", "STM32F091RC"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0750"],
+ "macros_add": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "FLASH"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F091RC"
+ },
+ "NUCLEO_F103RB": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M3",
+ "extra_labels_add": ["STM32F1", "STM32F103RB"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (SYSCLK=72 MHz) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI (SYSCLK=64 MHz)",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "clock_source_usb": {
+ "help": "In case of HSI clock source, to get 48 Mhz USB, SYSCLK has to be reduced from 64 to 48 MHz (set 0 for the max SYSCLK value)",
+ "value": "0",
+ "macro_name": "CLOCK_SOURCE_USB"
+ }
+ },
+ "detect_code": ["0700"],
+ "device_has_add": [
+ "CAN",
+ "SERIAL_ASYNCH",
+ "FLASH"
+ ],
+ "device_has_remove": ["LPTICKER"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F103RB"
+ },
+ "NUCLEO_F207ZG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M3",
+ "extra_labels_add": ["STM32F2", "STM32F207ZG", "STM_EMAC"],
+ "config": {
+ "d11_configuration": {
+ "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+ "value": "PA_7",
+ "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0835"],
+ "macros_add": ["USBHOST_OTHER"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "EMAC",
+ "SERIAL_ASYNCH",
+ "FLASH",
+ "TRNG",
+ "MPU"
+ ],
+ "device_has_remove": ["LPTICKER"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F207ZG",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NUCLEO_F302R8": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F3", "STM32F302x8", "STM32F302R8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0705"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "SERIAL_ASYNCH"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F302R8"
+ },
+ "NUCLEO_F303K8": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F3", "STM32F303x8", "STM32F303K8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "overrides": { "lse_available": 0 },
+ "detect_code": ["0775"],
+ "default_lib": "small",
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC"
+ ],
+ "release_versions": ["2"],
+ "device_name": "STM32F303K8"
+ },
+ "NUCLEO_F303RE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F3", "STM32F303xE", "STM32F303RE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0745"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "bootloader_supported": true,
+ "device_name": "STM32F303RE"
+ },
+ "NUCLEO_F303ZE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F3", "STM32F303xE", "STM32F303ZE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0747"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "FLASH", "MPU"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F303ZE"
+ },
+ "NUCLEO_F334R8": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F3", "STM32F334x8", "STM32F334R8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0735"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "SERIAL_ASYNCH"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F334R8"
+ },
+ "NUCLEO_F401RE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F401xE", "STM32F401RE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0720"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": [
+ "SERIAL_ASYNCH",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F401RE"
+ },
+ "STEVAL_3DP001V1": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F401xE", "STM32F401VE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER", "HSE_VALUE=25000000"],
+ "device_has_add": [
+ "SERIAL_ASYNCH",
+ "FLASH",
+ "MPU"
+ ],
+ "overrides": { "lse_available": 0 },
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F401VE"
+ },
+ "NUCLEO_F410RB": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F410RB",
+ "STM32F410xB",
+ "STM32F410Rx"
+ ],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "macros_add": [
+ "MBED_TICKLESS"
+ ],
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0744"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F410RB"
+ },
+ "NUCLEO_F411RE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F411xE", "STM32F411RE", "PSA"],
+ "components_add": ["FLASHIAP"],
+ "detect_code": ["0740"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "clock_source_usb": {
+ "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 100 to 96 MHz (set 0 for the max SYSCLK value)",
+ "value": "0",
+ "macro_name": "CLOCK_SOURCE_USB"
+ }
+ },
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": [
+ "SERIAL_ASYNCH",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F411RE",
+ "bootloader_supported": true
+ },
+ "NUCLEO_F412ZG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F412xG", "STM32F412ZG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0826"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": [
+ "CAN",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F412ZG",
+ "bootloader_supported": true
+ },
+ "MTB_MXCHIP_EMW3166": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F412xG",
+ "STM32F412ZG",
+ "WICED",
+ "CYW43362"
+ ],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": [
+ "CAN",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["5"],
+ "device_name": "STM32F412ZG",
+ "bootloader_supported": true,
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "overrides": {
+ "network-default-interface-type": "WIFI"
+ }
+ },
+ "USI_WM_BN_BM_22": {
+ "inherits": ["FAMILY_STM32"],
+ "components_add": ["SPIF", "FLASHIAP"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F412xG",
+ "STM32F412ZG",
+ "WICED",
+ "CYW4343X",
+ "CORDIO"
+ ],
+ "features": ["BLE", "STORAGE"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": [
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["5"],
+ "device_name": "STM32F412ZG",
+ "bootloader_supported": true,
+ "public": false,
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "overrides": {
+ "network-default-interface-type": "WIFI"
+ }
+ },
+ "MTB_USI_WM_BN_BM_22": {
+ "overrides": {
+ "lse_available": 0
+ },
+ "inherits": ["USI_WM_BN_BM_22"]
+ },
+ "MTB_ADV_WISE_1530": {
+ "inherits": ["USI_WM_BN_BM_22"],
+ "config": {
+ "led1": "PA_4",
+ "led2": "PC_12",
+ "led3": "NC"
+ },
+ "overrides": {
+ "stdio_uart_tx": "PB_10",
+ "stdio_uart_rx": "PC_11"
+ }
+ },
+ "DISCO_F413ZH": {
+ "components_add": ["QSPIF"],
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F413xx",
+ "STM32F413ZH",
+ "STM32F413xH"
+ ],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0743"],
+ "macros_add": [
+ "MBED_TICKLESS",
+ "USB_STM_HAL",
+ "USBHOST_OTHER"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "QSPI",
+ "MPU"
+ ],
+ "bootloader_supported": true,
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F413ZH"
+ },
+ "NUCLEO_F413ZH": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F413xx",
+ "STM32F413ZH",
+ "STM32F413xH"
+ ],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0743"],
+ "macros_add": [
+ "MBED_TICKLESS",
+ "USB_STM_HAL",
+ "USBHOST_OTHER"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "bootloader_supported": true,
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F413ZH"
+ },
+ "ELMO_F411RE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "default_toolchain": "uARM",
+ "extra_labels_add": ["STM32F4", "STM32F411xE", "STM32F411RE"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+ "detect_code": ["----"],
+ "device_has_add": ["MPU"],
+ "device_has_remove": ["SERIAL_FC"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F411RE"
+ },
+ "NUCLEO_F429ZI": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "config": {
+ "d11_configuration": {
+ "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+ "value": "PA_7",
+ "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "clock_source_usb": {
+ "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
+ "value": "1",
+ "macro_name": "CLOCK_SOURCE_USB"
+ }
+ },
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F429",
+ "STM32F429ZI",
+ "STM32F429xx",
+ "STM32F429xI",
+ "STM_EMAC",
+ "PSA"
+ ],
+ "components_add": ["FLASHIAP"],
+ "macros_add": [
+ "USB_STM_HAL",
+ "USBHOST_OTHER"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "EMAC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "detect_code": ["0796"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F429ZI",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NUCLEO_F439ZI": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "config": {
+ "d11_configuration": {
+ "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+ "value": "PA_7",
+ "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "clock_source_usb": {
+ "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
+ "value": "1",
+ "macro_name": "CLOCK_SOURCE_USB"
+ }
+ },
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F439",
+ "STM32F439ZI",
+ "STM32F439xx",
+ "STM32F439xI",
+ "STM_EMAC"
+ ],
+ "macros_add": [
+ "MBEDTLS_CONFIG_HW_SUPPORT",
+ "USB_STM_HAL",
+ "USBHOST_OTHER"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "EMAC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "detect_code": ["0797"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F439ZI",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NUCLEO_F446RE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446RE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0777"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "SERIAL_ASYNCH",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F446RE",
+ "bootloader_supported": true
+ },
+ "NUCLEO_F446ZE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446ZE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0778"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "SERIAL_ASYNCH",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F446ZE"
+ },
+ "B96B_F446VE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446VE"],
+ "detect_code": ["0840"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "SERIAL_ASYNCH",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F446VE"
+ },
+ "NUCLEO_F746ZG": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M7F",
+ "extra_labels_add": [
+ "STM32F7",
+ "STM32F746",
+ "STM32F746xG",
+ "STM32F746ZG",
+ "STM_EMAC"
+ ],
+ "config": {
+ "d11_configuration": {
+ "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+ "value": "PA_7",
+ "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "macros_add": [
+ "MBED_TICKLESS",
+ "USBHOST_OTHER"
+ ],
+ "supported_form_factors": ["ARDUINO"],
+ "detect_code": ["0816"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "EMAC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F746ZG",
+ "bootloader_supported": true,
+ "overrides": {
+ "lpticker_delay_ticks": 4,
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NUCLEO_F756ZG": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M7F",
+ "extra_labels_add": [
+ "STM32F7",
+ "STM32F756",
+ "STM32F756xG",
+ "STM32F756ZG",
+ "STM_EMAC"
+ ],
+ "config": {
+ "d11_configuration": {
+ "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+ "value": "PA_7",
+ "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "macros_add": [
+ "MBED_TICKLESS",
+ "USBHOST_OTHER",
+ "MBEDTLS_CONFIG_HW_SUPPORT"
+ ],
+ "supported_form_factors": ["ARDUINO"],
+ "detect_code": ["0819"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "EMAC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F756ZG",
+ "overrides": {
+ "lpticker_delay_ticks": 4,
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NUCLEO_F767ZI": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M7FD",
+ "extra_labels_add": [
+ "STM32F7",
+ "STM32F767",
+ "STM32F767xI",
+ "STM32F767ZI",
+ "STM_EMAC"
+ ],
+ "config": {
+ "flash_dual_bank": {
+ "help": "Default board configuration is Single Bank Flash. If you enable Dual Bank with ST Link Utility, set value to 1",
+ "value": "0"
+ },
+ "d11_configuration": {
+ "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+ "value": "PA_7",
+ "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "supported_form_factors": ["ARDUINO"],
+ "macros_add": [
+ "MBED_TICKLESS",
+ "USBHOST_OTHER"
+ ],
+ "detect_code": ["0818"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "EMAC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F767ZI",
+ "bootloader_supported": true,
+ "overrides": {
+ "lpticker_delay_ticks": 4,
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NUCLEO_H743ZI": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M7FD",
+ "extra_labels_add": [
+ "STM32H7",
+ "STM32H743",
+ "STM32H743xI",
+ "STM32H743ZI"
+ ],
+ "config": {
+ "d11_configuration": {
+ "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+ "value": "PA_7",
+ "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "hse_value": {
+ "help": "HSE default value is 25MHz in HAL",
+ "value": "8000000",
+ "macro_name": "HSE_VALUE"
+ }
+ },
+ "macros_add": [
+ "MBED_TICKLESS"
+ ],
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "supported_form_factors": ["ARDUINO"],
+ "detect_code": ["0813"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32H743ZI",
+ "bootloader_supported": true
+ },
+ "NUCLEO_L011K4": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": ["STM32L0", "STM32L011K4"],
+ "supported_toolchains": ["uARM"],
+ "default_toolchain": "uARM",
+ "supported_form_factors": ["ARDUINO"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0780"],
+ "device_has_add": [
+ "CRC",
+ "FLASH"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32L011K4"
+ },
+ "NUCLEO_L031K6": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": ["STM32L0", "STM32L031K6"],
+ "default_toolchain": "uARM",
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0790"],
+ "device_has_add": [
+ "CRC",
+ "FLASH"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32L031K6"
+ },
+ "NUCLEO_L053R8": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053R8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0715"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "FLASH",
+ "MPU"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32L053R8"
+ },
+ "NUCLEO_L073RZ": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": ["STM32L0", "STM32L073RZ", "STM32L073xx"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "macros_add": [
+ "MBED_TICKLESS"
+ ],
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0760"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L073RZ"
+ },
+ "NUCLEO_L152RE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M3",
+ "extra_labels_add": ["STM32L1", "STM32L152RE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0710"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "SERIAL_ASYNCH",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L152RE"
+ },
+ "NUCLEO_L432KC": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L432xC", "STM32L432KC"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "macros_add": [
+ "MBED_TICKLESS"
+ ],
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0770"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "CAN",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L432KC",
+ "bootloader_supported": true
+ },
+ "NUCLEO_L433RC_P": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L433xC", "STM32L433RC"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "macros_add": [
+ "MBED_TICKLESS"
+ ],
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0779"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "CAN",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L433RC",
+ "bootloader_supported": true
+ },
+ "MTB_ADV_WISE_1510": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L443xC", "STM32L443RC"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "overrides": { "lse_available": 0 },
+ "release_versions": ["5"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "CAN",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "device_has_remove": ["LPTICKER"],
+ "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT"],
+ "device_name": "STM32L443RC",
+ "detect_code": ["0458"],
+ "bootloader_supported": true
+ },
+ "NUCLEO_L476RG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L476RG", "STM32L476xG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0765"],
+ "macros_add": [
+ "MBED_TICKLESS",
+ "USBHOST_OTHER",
+ "TWO_RAM_REGIONS"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L476RG",
+ "bootloader_supported": true
+ },
+ "SILICA_SENSOR_NODE": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "default_toolchain": "GCC_ARM",
+ "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476JG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0766"],
+ "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["5"],
+ "device_name": "STM32L476JG"
+ },
+ "NUCLEO_L486RG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L486RG", "STM32L486xG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0827"],
+ "macros_add": [
+ "MBED_TICKLESS",
+ "USBHOST_OTHER",
+ "MBEDTLS_CONFIG_HW_SUPPORT",
+ "TWO_RAM_REGIONS"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L486RG"
+ },
+ "MTB_ADV_WISE_1570": {
+ "components_add": ["FLASHIAP"],
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": [
+ "STM32L4",
+ "STM32L486RG",
+ "STM32L486xG",
+ "WISE_1570"
+ ],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_HSE_XTAL",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "overrides": { "lpuart_clock_source": "USE_LPUART_CLK_HSI" },
+ "detect_code": ["0460"],
+ "macros_add": [
+ "MBEDTLS_CONFIG_HW_SUPPORT",
+ "WISE_1570",
+ "TWO_RAM_REGIONS"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "device_has_remove": ["LPTICKER"],
+ "release_versions": ["5"],
+ "device_name": "STM32L486RG",
+ "bootloader_supported": true,
+ "OUTPUT_EXT": "hex"
+ },
+ "ARCH_MAX": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "program_cycle_s": 2,
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F407",
+ "STM32F407xG",
+ "STM32F407VG",
+ "STM_EMAC"
+ ],
+ "device_has_add": ["ANALOGOUT", "TRNG", "FLASH", "EMAC", "MPU"],
+ "device_has_remove": [
+ "LPTICKER",
+ "SERIAL_FC"
+ ],
+ "macros_add": ["USB_STM_HAL"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_HSE_XTAL",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "release_versions": ["2", "5"],
+ "overrides": {"lse_available": 0},
+ "device_name": "STM32F407VG",
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "WIO_3G": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "clock_source_usb": {
+ "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
+ "value": "1",
+ "macro_name": "CLOCK_SOURCE_USB"
+ },
+ "modem_is_on_board": {
+ "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD"
+ },
+ "modem_data_connection_type": {
+ "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD_UART"
+ }
+ },
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F439",
+ "STM32F439VI",
+ "STM32F439xx",
+ "STM32F439xI"
+ ],
+ "macros_add": [
+ "MBEDTLS_CONFIG_HW_SUPPORT",
+ "USB_STM_HAL",
+ "USBHOST_OTHER"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "detect_code": ["9014"],
+ "release_versions": ["2", "5"],
+ "device_name" : "STM32F439VI",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "CELLULAR"
+ }
+ },
+ "WIO_BG96": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "clock_source_usb": {
+ "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
+ "value": "0",
+ "macro_name": "CLOCK_SOURCE_USB"
+ },
+ "modem_is_on_board": {
+ "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD"
+ },
+ "modem_data_connection_type": {
+ "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD_UART"
+ }
+ },
+ "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439VI", "STM32F439xx", "STM32F439xI"],
+ "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "detect_code": ["9015"],
+ "release_versions": ["2", "5"],
+ "device_name" : "STM32F439VI",
+ "components_add": ["SD"],
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "CELLULAR"
+ }
+ },
+ "DISCO_F051R8": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0",
+ "extra_labels_add": ["STM32F0", "STM32F051", "STM32F051R8"],
+ "supported_toolchains": ["GCC_ARM"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "macros_add": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "device_has_add": [
+ "CRC",
+ "MPU"
+ ],
+ "device_has_remove": ["LPTICKER"],
+ "device_name": "STM32F051R8"
+ },
+ "DISCO_F100RB": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M3",
+ "extra_labels_add": ["STM32F1", "STM32F100RB"],
+ "supported_toolchains": ["GCC_ARM"],
+ "device_has_add": [],
+ "device_has_remove": ["LPTICKER"],
+ "device_name": "STM32F100RB"
+ },
+ "DISCO_F303VC": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": [
+ "STM32F3",
+ "STM32F303",
+ "STM32F303xC",
+ "STM32F303VC"
+ ],
+ "overrides": { "lse_available": 0 },
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "MPU"
+ ],
+ "device_name": "STM32F303VC"
+ },
+ "DISCO_F334C8": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F3", "STM32F334x8", "STM32F334C8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "overrides": { "lse_available": 0 },
+ "detect_code": ["0810"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CRC",
+ "SERIAL_ASYNCH"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F334C8"
+ },
+ "DISCO_F407VG": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F407",
+ "STM32F407xG",
+ "STM32F407VG"
+ ],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "macros_add": ["USB_STM_HAL"],
+ "overrides": { "lse_available": 0 },
+ "device_has_add": ["ANALOGOUT", "TRNG", "FLASH", "MPU"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F407VG"
+ },
+ "DISCO_F429ZI": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F429",
+ "STM32F429ZI",
+ "STM32F429xI",
+ "STM32F429xx"
+ ],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "clock_source_usb": {
+ "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
+ "value": "1",
+ "macro_name": "CLOCK_SOURCE_USB"
+ }
+ },
+ "overrides": { "lse_available": 0 },
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F429ZI",
+ "bootloader_supported": true
+ },
+ "DISCO_F469NI": {
+ "components_add": ["QSPIF"],
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F469",
+ "STM32F469NI",
+ "STM32F469xI",
+ "STM32F469xx"
+ ],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0788"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "TRNG",
+ "FLASH",
+ "QSPI",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F469NI",
+ "bootloader_supported": true
+ },
+ "DISCO_L053C8": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053C8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "overrides": {
+ "lse_available": 0,
+ "lpticker_delay_ticks": 4
+ },
+ "device_has_add": [
+ "ANALOGOUT",
+ "CRC",
+ "FLASH",
+ "MPU"
+ ],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32L053C8"
+ },
+ "DISCO_L072CZ_LRWAN1": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": [
+ "STM32L0",
+ "STM32L072CZ",
+ "STM32L072xZ",
+ "STM32L072xx"
+ ],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "macros_add": [
+ "MBED_TICKLESS"
+ ],
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0833"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L072CZ"
+ },
+ "MTB_MURATA_ABZ": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": [
+ "STM32L0",
+ "STM32L0x2xZ",
+ "STM32L082CZ",
+ "STM32L082xx"
+ ],
+ "detect_code": ["0456"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "device_has_remove": ["LPTICKER"],
+ "release_versions": ["5"],
+ "device_name": "STM32L082CZ"
+ },
+ "DISCO_F746NG": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M7F",
+ "extra_labels_add": [
+ "STM32F7",
+ "STM32F746",
+ "STM32F746xG",
+ "STM32F746NG",
+ "STM_EMAC"
+ ],
+ "components_add": ["QSPIF"],
+ "supported_form_factors": ["ARDUINO"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "usb_speed": {
+ "help": "Select the USB speed/connector (0=FullSpeed, 1=HighSpeed)",
+ "value": "1"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "detect_code": ["0815"],
+ "macros_add": [
+ "MBED_TICKLESS",
+ "USB_STM_HAL",
+ "USBHOST_OTHER"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "EMAC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "QSPI",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F746NG",
+ "bootloader_supported": true,
+ "overrides": {
+ "lpticker_delay_ticks": 4,
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "DISCO_F769NI": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M7FD",
+ "extra_labels_add": [
+ "STM32F7",
+ "STM32F769",
+ "STM32F769xI",
+ "STM32F769NI",
+ "STM_EMAC"
+ ],
+ "components_add": ["QSPIF"],
+ "supported_form_factors": ["ARDUINO"],
+ "config": {
+ "flash_dual_bank": {
+ "help": "Default board configuration is Single Bank Flash. If you enable Dual Bank with ST Link Utility, set value to 1",
+ "value": "0"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "detect_code": ["0817"],
+ "macros_add": [
+ "MBED_TICKLESS",
+ "USB_STM_HAL",
+ "USBHOST_OTHER"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "EMAC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU",
+ "QSPI"
+ ],
+ "bootloader_supported": true,
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F769NI",
+ "overrides": {
+ "lpticker_delay_ticks": 4,
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "DISCO_L475VG_IOT01A": {
+ "components_add": ["QSPIF", "FLASHIAP"],
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L475xG", "STM32L475VG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "supported_form_factors": ["ARDUINO"],
+ "detect_code": ["0764"],
+ "macros_add": [
+ "MBED_TICKLESS",
+ "USBHOST_OTHER",
+ "TWO_RAM_REGIONS"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "TRNG",
+ "FLASH",
+ "QSPI",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L475VG",
+ "bootloader_supported": true
+ },
+ "MTB_STM_L475": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L475xG", "STM32L475VG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (8MHz) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_HSE_XTAL",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 0
+ }
+ },
+ "detect_code": ["0468"],
+ "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "SERIAL_FC",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["5"],
+ "device_name": "STM32L475VG",
+ "bootloader_supported": true
+ },
+ "DISCO_L476VG": {
+ "components_add": ["QSPIF", "FLASHIAP"],
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476VG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0820"],
+ "macros_add": [
+ "MBED_TICKLESS",
+ "USBHOST_OTHER",
+ "TWO_RAM_REGIONS"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "TRNG",
+ "FLASH",
+ "QSPI",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L476VG",
+ "bootloader_supported": true
+ },
+ "RHOMBIO_L476DMW1K": {
+ "components_add": ["FLASHIAP"],
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476VG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["1500"],
+ "macros_add": [
+ "MBED_TICKLESS",
+ "USBHOST_OTHER",
+ "TWO_RAM_REGIONS"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "SERIAL_FC",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L476VG",
+ "bootloader_supported": true
+ },
+ "MTS_MDOT_F405RG": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F405RG"],
+ "is_disk_virtual": true,
+ "macros_add": ["HSE_VALUE=26000000"],
+ "device_has_add": ["ANALOGOUT", "MPU"],
+ "release_versions": ["2"],
+ "device_name": "STM32F405RG"
+ },
+ "MTS_MDOT_F411RE": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F411RE"],
+ "macros_add": [
+ "HSE_VALUE=26000000",
+ "USE_PLL_HSE_EXTC=0",
+ "VECT_TAB_OFFSET=0x00010000"
+ ],
+ "post_binary_hook": {
+ "function": "MTSCode.combine_bins_mts_dot",
+ "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
+ },
+ "device_has_add": ["MPU"],
+ "device_has_remove": [
+ "SERIAL_FC"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F411RE"
+ },
+ "MTS_DRAGONFLY_F411RE": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F411RE"],
+ "config": {
+ "modem_is_on_board": {
+ "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD"
+ },
+ "modem_data_connection_type": {
+ "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD_UART"
+ }
+ },
+ "overrides": { "lse_available": 0 },
+ "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000"],
+ "post_binary_hook": {
+ "function": "MTSCode.combine_bins_mts_dragonfly",
+ "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
+ },
+ "device_has_add": ["MPU"],
+ "device_has_remove": [
+ "SERIAL_FC"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F411RE"
+ },
+ "MTS_DRAGONFLY_L471QG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": [
+ "STM32L4",
+ "STM32L471QG",
+ "STM32L471xG",
+ "STM32L471xx"
+ ],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "modem_is_on_board": {
+ "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD"
+ },
+ "modem_data_connection_type": {
+ "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD_UART"
+ }
+ },
+ "macros_add": ["TWO_RAM_REGIONS"],
+ "detect_code": ["0312"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L471QG",
+ "bootloader_supported": true
+ },
+ "MTB_MTS_DRAGONFLY": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F411RE"],
+ "config": {
+ "modem_is_on_board": {
+ "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD"
+ },
+ "modem_data_connection_type": {
+ "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD_UART"
+ }
+ },
+ "overrides": {
+ "lse_available": 0
+ },
+ "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000"],
+ "device_has_add": ["MPU"],
+ "device_has_remove": [
+ "SERIAL_FC"
+ ],
+ "post_binary_hook": {
+ "function": "MTSCode.combine_bins_mtb_mts_dragonfly",
+ "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
+ },
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F411RE",
+ "bootloader_supported": true
+ },
+ "XDOT_L151CC": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M3",
+ "default_toolchain": "ARM",
+ "extra_labels_add": ["STM32L1", "STM32L151CC"],
+ "config": {
+ "hse_value": {
+ "value": "24000000",
+ "macro_name": "HSE_VALUE"
+ }
+ },
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "device_has_add": ["ANALOGOUT", "FLASH", "MPU"],
+ "device_has_remove": [
+ "SERIAL_FC"
+ ],
+ "release_versions": ["5"],
+ "device_name": "STM32L151CC",
+ "bootloader_supported": true
+ },
+ "FF1705_L151CC": {
+ "inherits": ["XDOT_L151CC"],
+ "detect_code": ["8080"]
+ },
+ "MTB_MTS_XDOT": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M3",
+ "default_toolchain": "ARM",
+ "extra_labels_add": ["STM32L1", "STM32L151CC"],
+ "config": {
+ "hse_value": {
+ "value": "24000000",
+ "macro_name": "HSE_VALUE"
+ }
+ },
+ "overrides": {
+ "stdio_uart_tx": "PA_2",
+ "stdio_uart_rx": "PA_3"
+ },
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "device_has_add": ["ANALOGOUT", "FLASH", "MPU"],
+ "device_has_remove": [
+ "SERIAL_FC"
+ ],
+ "release_versions": ["5"],
+ "device_name": "STM32L151CC",
+ "bootloader_supported": true
+ },
+ "MTB_RAK811": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M3",
+ "default_toolchain": "ARM",
+ "extra_labels_add": ["STM32L1", "STM32L151xBA", "STM32L151CBA"],
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "device_has_add": ["ANALOGOUT", "MPU"],
+ "device_has_remove": [
+ "SERIAL_FC"
+ ],
+ "release_versions": ["5"],
+ "device_name": "STM32L151CBxxA",
+ "bootloader_supported": true
+ },
+ "MOTE_L152RC": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M3",
+ "default_toolchain": "ARM",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels_add": ["STM32L1", "STM32L152RC"],
+ "detect_code": ["4100"],
+ "device_has_add": ["ANALOGOUT", "SERIAL_ASYNCH", "FLASH", "MPU"],
+ "device_has_remove": ["SERIAL_FC"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L152RC"
+ },
+ "DISCO_F401VC": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "default_toolchain": "GCC_ARM",
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F401",
+ "STM32F401xC",
+ "STM32F401VC"
+ ],
+ "supported_toolchains": ["GCC_ARM"],
+ "device_has_add": ["MPU"],
+ "device_name": "STM32F401VC"
+ },
+ "MODULE_UBLOX_ODIN_W2": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F439",
+ "STM32F439ZI",
+ "STM32F439xx",
+ "STM32F439xI",
+ "STM_EMAC",
+ "CORDIO",
+ "CORDIO_ODIN_W2"
+ ],
+ "macros": [
+ "MBEDTLS_CONFIG_HW_SUPPORT",
+ "HSE_VALUE=24000000",
+ "HSE_STARTUP_TIMEOUT=5000",
+ "CB_INTERFACE_SDIO",
+ "CB_CHIP_WL18XX",
+ "SUPPORT_80211D_ALWAYS",
+ "WLAN_ENABLED",
+ "CB_FEATURE_802DOT11W",
+ "CB_FEATURE_802DOT11R",
+ "MBEDTLS_ARC4_C",
+ "MBEDTLS_DES_C",
+ "MBEDTLS_MD4_C",
+ "MBEDTLS_MD5_C",
+ "MBEDTLS_SHA1_C",
+ "MBED_MPU_CUSTOM"
+ ],
+ "device_has_add": [
+ "CAN",
+ "EMAC",
+ "TRNG",
+ "FLASH",
+ "WIFI",
+ "SERIAL"
+ ],
+ "features": ["BLE"],
+ "device_has_remove": [],
+ "device_name": "STM32F439ZI",
+ "public": false,
+ "bootloader_supported": true,
+ "config": {
+ "BLE_STACK_UBX": {
+ "help": "It should be set to true to enable ublox ODIN own stack/driver rather than CORDIO",
+ "value": false,
+ "macro_name": "BLE_STACK_UBX"
+ }
+ },
+ "overrides": {
+ "network-default-interface-type": "WIFI"
+ }
+ },
+ "UBLOX_EVK_ODIN_W2": {
+ "inherits": ["MODULE_UBLOX_ODIN_W2"],
+ "supported_form_factors": ["ARDUINO"],
+ "release_versions": ["5"],
+ "device_has_remove": [],
+ "extra_labels_add": ["PSA"],
+ "components_add": ["FLASHIAP"],
+ "config": {
+ "stdio_uart_tx_help": {
+ "help": "Value: D8(default) or D1"
+ },
+ "stdio_uart_rx_help": {
+ "help": "Value: D2(default) or D0"
+ }
+ },
+ "overrides": {
+ "stdio_uart_tx": "D8",
+ "stdio_uart_rx": "D2"
+ }
+ },
+ "MBED_CONNECT_ODIN": {
+ "inherits": ["MODULE_UBLOX_ODIN_W2"],
+ "release_versions": ["5"],
+ "config": {
+ "stdio_uart_tx_help": {
+ "help": "Value: PA_9(default) or PD_8"
+ },
+ "stdio_uart_rx_help": {
+ "help": "Value: PA_10(default) or PD_9"
+ }
+ },
+ "overrides": {
+ "stdio_uart_tx": "PA_9",
+ "stdio_uart_rx": "PA_10"
+ }
+ },
+ "MTB_UBLOX_ODIN_W2": {
+ "inherits": ["MODULE_UBLOX_ODIN_W2"],
+ "device_has_add": [],
+ "overrides": {"lse_available": 0},
+ "release_versions": ["5"]
+ },
+ "UBLOX_C030": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "extra_labels_add": [
+ "STM32F4",
+ "STM32F437",
+ "STM32F437VG",
+ "STM32F437xx",
+ "STM32F437xG",
+ "STM_EMAC"
+ ],
+ "config": {
+ "modem_is_on_board": {
+ "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD"
+ },
+ "modem_data_connection_type": {
+ "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD_UART"
+ }
+ },
+ "macros_add": [
+ "MBEDTLS_CONFIG_HW_SUPPORT",
+ "HSE_VALUE=12000000",
+ "GNSSBAUD=9600"
+ ],
+ "device_has_add": [
+ "ANALOGOUT",
+ "EMAC",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "public": false,
+ "device_name": "STM32F437VG",
+ "bootloader_supported": true,
+ "overrides": {
+ "lse_available": 0,
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "UBLOX_C030_U201": {
+ "inherits": ["UBLOX_C030"],
+ "release_versions": ["5"]
+ },
+ "UBLOX_C030_N211": {
+ "inherits": ["UBLOX_C030"],
+ "release_versions": ["5"]
+ },
+ "UBLOX_C030_R41XM": {
+ "inherits": ["UBLOX_C030"],
+ "release_versions": ["5"]
+ },
+ "UBLOX_C030_R410M": {
+ "inherits": ["UBLOX_C030_R41XM"],
+ "release_versions": ["5"]
+ },
+ "UBLOX_C030_R412M": {
+ "inherits": ["UBLOX_C030_R41XM"],
+ "release_versions": ["5"]
+ },
+ "NZ32_SC151": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M3",
+ "default_toolchain": "uARM",
+ "program_cycle_s": 1.5,
+ "extra_labels_add": ["STM32L1", "STM32L151RC"],
+ "overrides": { "lse_available": 0 },
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+ "device_has_add": ["ANALOGOUT", "MPU"],
+ "default_lib": "small",
+ "device_name": "STM32L151RC"
+ },
+ "MCU_NRF51": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0",
+ "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
+ "macros": [
+ "NRF51",
+ "NRF5x",
+ "TARGET_NRF51822",
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "MERGE_BOOTLOADER": false,
+ "extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822"],
+ "OUTPUT_EXT": "hex",
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "GCC_ARM"],
+ "public": false,
+ "MERGE_SOFT_DEVICE": true,
+ "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+ {
+ "boot": "s130_nrf51_1.0.0_bootloader.hex",
+ "name": "s130_nrf51_1.0.0_softdevice.hex",
+ "offset": 114688
+ },
+ {
+ "boot": "s110_nrf51822_8.0.0_bootloader.hex",
+ "name": "s110_nrf51822_8.0.0_softdevice.hex",
+ "offset": 98304
+ },
+ {
+ "boot": "s110_nrf51822_7.1.0_bootloader.hex",
+ "name": "s110_nrf51822_7.1.0_softdevice.hex",
+ "offset": 90112
+ },
+ {
+ "boot": "s110_nrf51822_7.0.0_bootloader.hex",
+ "name": "s110_nrf51822_7.0.0_softdevice.hex",
+ "offset": 90112
+ },
+ {
+ "boot": "s110_nrf51822_6.0.0_bootloader.hex",
+ "name": "s110_nrf51822_6.0.0_softdevice.hex",
+ "offset": 81920
+ }
+ ],
+ "detect_code": ["1070"],
+ "post_binary_hook": {
+ "function": "MCU_NRF51Code.binary_hook",
+ "toolchains": ["ARM_STD", "GCC_ARM"]
+ },
+ "program_cycle_s": 6,
+ "features": ["BLE"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ]
+ },
+ "MCU_NRF51_16K_BASE": {
+ "inherits": ["MCU_NRF51"],
+ "extra_labels_add": ["MCU_NORDIC_16K", "MCU_NRF51_16K"],
+ "macros_add": ["TARGET_MCU_NORDIC_16K", "TARGET_MCU_NRF51_16K"],
+ "public": false,
+ "default_lib": "small"
+ },
+ "MCU_NRF51_16K_BOOT_BASE": {
+ "inherits": ["MCU_NRF51_16K_BASE"],
+ "MERGE_BOOTLOADER": true,
+ "extra_labels_add": ["MCU_NRF51_16K_BOOT"],
+ "macros_add": ["TARGET_MCU_NRF51_16K_BOOT", "TARGET_OTA_ENABLED"],
+ "public": false
+ },
+ "MCU_NRF51_16K_OTA_BASE": {
+ "inherits": ["MCU_NRF51_16K_BASE"],
+ "public": false,
+ "extra_labels_add": ["MCU_NRF51_16K_OTA"],
+ "macros_add": ["TARGET_MCU_NRF51_16K_OTA", "TARGET_OTA_ENABLED"],
+ "MERGE_SOFT_DEVICE": false
+ },
+ "MCU_NRF51_16K": {
+ "inherits": ["MCU_NRF51_16K_BASE"],
+ "extra_labels_add": ["MCU_NRF51_16K_S130"],
+ "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
+ "public": false
+ },
+ "MCU_NRF51_S110": {
+ "extra_labels_add": ["MCU_NRF51_16K_S110"],
+ "macros_add": ["TARGET_MCU_NRF51_16K_S110"],
+ "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+ {
+ "name": "s110_nrf51822_8.0.0_softdevice.hex",
+ "boot": "s110_nrf51822_8.0.0_bootloader.hex",
+ "offset": 98304
+ },
+ {
+ "name": "s110_nrf51822_7.1.0_softdevice.hex",
+ "boot": "s110_nrf51822_7.1.0_bootloader.hex",
+ "offset": 90112
+ }
+ ],
+ "public": false
+ },
+ "MCU_NRF51_16K_S110": {
+ "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_BASE"],
+ "public": false
+ },
+ "MCU_NRF51_16K_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT_BASE"],
+ "extra_labels_add": ["MCU_NRF51_16K_S130"],
+ "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
+ "public": false
+ },
+ "MCU_NRF51_16K_BOOT_S110": {
+ "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_BOOT_BASE"],
+ "public": false
+ },
+ "MCU_NRF51_16K_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA_BASE"],
+ "extra_labels_add": ["MCU_NRF51_16K_S130"],
+ "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
+ "public": false
+ },
+ "MCU_NRF51_16K_OTA_S110": {
+ "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_OTA_BASE"],
+ "public": false
+ },
+ "MCU_NRF51_32K": {
+ "inherits": ["MCU_NRF51"],
+ "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
+ "macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
+ "public": false
+ },
+ "MCU_NRF51_32K_BOOT": {
+ "inherits": ["MCU_NRF51_32K"],
+ "MERGE_BOOTLOADER": true,
+ "extra_labels_add": ["MCU_NRF51_32K_BOOT"],
+ "macros_add": ["TARGET_MCU_NRF51_32K_BOOT", "TARGET_OTA_ENABLED"],
+ "public": false
+ },
+ "MCU_NRF51_32K_OTA": {
+ "inherits": ["MCU_NRF51_32K"],
+ "public": false,
+ "extra_labels_add": ["MCU_NRF51_32K_OTA"],
+ "macros_add": ["TARGET_MCU_NRF51_32K_OTA", "TARGET_OTA_ENABLED"],
+ "MERGE_SOFT_DEVICE": false
+ },
+ "NRF51822": {
+ "inherits": ["MCU_NRF51_16K"],
+ "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
+ "macros_add": ["TARGET_NRF51822_MKIT"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "NRF51822_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
+ "macros_add": ["TARGET_NRF51822_MKIT"]
+ },
+ "NRF51822_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
+ "macros_add": ["TARGET_NRF51822_MKIT"]
+ },
+ "ARCH_BLE": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "ARCH_BLE_BOOT": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["ARCH_BLE"],
+ "macros_add": ["TARGET_ARCH_BLE"]
+ },
+ "ARCH_BLE_OTA": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["ARCH_BLE"],
+ "macros_add": ["TARGET_ARCH_BLE"]
+ },
+ "ARCH_LINK": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K"],
+ "extra_labels_add": ["ARCH_BLE"],
+ "macros_add": ["TARGET_ARCH_BLE"]
+ },
+ "ARCH_LINK_BOOT": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["ARCH_BLE", "ARCH_LINK"],
+ "macros_add": ["TARGET_ARCH_BLE", "TARGET_ARCH_LINK"]
+ },
+ "ARCH_LINK_OTA": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["ARCH_BLE", "ARCH_LINK"],
+ "macros_add": ["TARGET_ARCH_BLE", "TARGET_ARCH_LINK"]
+ },
+ "SEEED_TINY_BLE": {
+ "inherits": ["MCU_NRF51_16K"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "SEEED_TINY_BLE_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["SEEED_TINY_BLE"],
+ "macros_add": ["TARGET_SEEED_TINY_BLE"]
+ },
+ "SEEED_TINY_BLE_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["SEEED_TINY_BLE"],
+ "macros_add": ["TARGET_SEEED_TINY_BLE"]
+ },
+ "HRM1017": {
+ "inherits": ["MCU_NRF51_16K"],
+ "macros_add": ["TARGET_NRF_LFCLK_RC"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "HRM1017_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["HRM1017"],
+ "macros_add": ["TARGET_HRM1017", "TARGET_NRF_LFCLK_RC"]
+ },
+ "HRM1017_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["HRM1017"],
+ "macros_add": ["TARGET_HRM1017", "TARGET_NRF_LFCLK_RC"]
+ },
+ "RBLAB_NRF51822": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "RBLAB_NRF51822_BOOT": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["RBLAB_NRF51822"],
+ "macros_add": ["TARGET_RBLAB_NRF51822"]
+ },
+ "RBLAB_NRF51822_OTA": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["RBLAB_NRF51822"],
+ "macros_add": ["TARGET_RBLAB_NRF51822"]
+ },
+ "RBLAB_BLENANO": {
+ "inherits": ["MCU_NRF51_16K"],
+ "release_versions": ["2"]
+ },
+ "RBLAB_BLENANO_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["RBLAB_BLENANO"],
+ "macros_add": ["TARGET_RBLAB_BLENANO"]
+ },
+ "RBLAB_BLENANO_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["RBLAB_BLENANO"],
+ "macros_add": ["TARGET_RBLAB_BLENANO"]
+ },
+ "RBLAB_BLENANO2": {
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "NRF51822_Y5_MBUG": {
+ "inherits": ["MCU_NRF51_16K"]
+ },
+ "WALLBOT_BLE": {
+ "inherits": ["MCU_NRF51_16K"],
+ "release_versions": ["2"]
+ },
+ "WALLBOT_BLE_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["WALLBOT_BLE"],
+ "macros_add": ["TARGET_WALLBOT_BLE"]
+ },
+ "WALLBOT_BLE_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["WALLBOT_BLE"],
+ "macros_add": ["TARGET_WALLBOT_BLE"]
+ },
+ "DELTA_DFCM_NNN40": {
+ "inherits": ["MCU_NRF51_32K"],
+ "program_cycle_s": 10,
+ "macros_add": ["TARGET_NRF_LFCLK_RC"],
+ "device_has": [
+ "ANALOGIN",
+ "DEBUG_AWARENESS",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "DELTA_DFCM_NNN40_BOOT": {
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "program_cycle_s": 10,
+ "extra_labels_add": ["DELTA_DFCM_NNN40"],
+ "macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
+ },
+ "DELTA_DFCM_NNN40_OTA": {
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "program_cycle_s": 10,
+ "extra_labels_add": ["DELTA_DFCM_NNN40"],
+ "macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
+ },
+ "DELTA_DFCM_NNN50": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "ANALOGIN",
+ "I2C",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SPISLAVE"
+ ],
+ "device_name": "nRF51822_xxAC"
+ },
+ "DELTA_DFCM_NNN50_BOOT": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "extra_labels_add": ["DELTA_DFCM_NNN50"],
+ "macros_add": ["TARGET_DELTA_DFCM_NNN50"]
+ },
+ "DELTA_DFCM_NNN50_OTA": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "extra_labels_add": ["DELTA_DFCM_NNN50"],
+ "macros_add": ["TARGET_DELTA_DFCM_NNN50"]
+ },
+ "NRF51_DK_LEGACY": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K"],
+ "extra_labels_add": ["NRF51_DK"]
+ },
+ "NRF51_DK_BOOT": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "extra_labels_add": ["NRF51_DK"],
+ "macros_add": ["TARGET_NRF51_DK"]
+ },
+ "NRF51_DK_OTA": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "extra_labels_add": ["NRF51_DK"],
+ "macros_add": ["TARGET_NRF51_DK"]
+ },
+ "NRF51_DONGLE_LEGACY": {
+ "inherits": ["MCU_NRF51_32K"],
+ "extra_labels_add": ["NRF51_DONGLE"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "NRF51_DONGLE_BOOT": {
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "extra_labels_add": ["NRF51_DONGLE"],
+ "macros_add": ["TARGET_NRF51_DONGLE"]
+ },
+ "NRF51_DONGLE_OTA": {
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "extra_labels_add": ["NRF51_DONGLE"],
+ "macros_add": ["TARGET_NRF51_DONGLE"]
+ },
+ "NRF51_MICROBIT": {
+ "inherits": ["MCU_NRF51_16K_S110"],
+ "macros_add": ["TARGET_NRF_LFCLK_RC"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "NRF51_MICROBIT_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT_S110"],
+ "extra_labels_add": ["NRF51_MICROBIT"],
+ "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
+ },
+ "NRF51_MICROBIT_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA_S110"],
+ "extra_labels_add": ["NRF51_MICROBIT"],
+ "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
+ },
+ "NRF51_MICROBIT_B": {
+ "inherits": ["MCU_NRF51_16K"],
+ "extra_labels_add": ["NRF51_MICROBIT"],
+ "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"],
+ "release_versions": ["2"]
+ },
+ "NRF51_MICROBIT_B_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["NRF51_MICROBIT"],
+ "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
+ },
+ "NRF51_MICROBIT_B_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["NRF51_MICROBIT"],
+ "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
+ },
+ "MTM_MTCONNECT04S": {
+ "inherits": ["MCU_NRF51_32K"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "MTM_MTCONNECT04S_BOOT": {
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "extra_labels_add": ["MTM_CONNECT04S"],
+ "macros_add": ["TARGET_MTM_CONNECT04S"]
+ },
+ "MTM_MTCONNECT04S_OTA": {
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "extra_labels_add": ["MTM_CONNECT04S"],
+ "macros_add": ["TARGET_MTM_CONNECT04S"]
+ },
+ "MTB_LAIRD_BL600": {
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "ANALOGIN",
+ "I2C",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SPISLAVE"
+ ],
+ "device_name": "nRF51822_xxAA",
+ "release_versions": ["5"],
+ "extra_labels_add": ["MTB_LAIRD_BL600"],
+ "config": {
+ "usb_tx": {
+ "help": "Value SIO_21",
+ "value": "SIO_21"
+ },
+ "usb_rx": {
+ "help": "Value SIO_22",
+ "value": "SIO_22"
+ },
+ "stdio_uart": {
+ "help": "Value: UART_0",
+ "value": "UART_0",
+ "macro_name": "STDIO_UART"
+ }
+ },
+ "overrides": {
+ "uart_hwfc": 0
+ }
+ },
+ "TY51822R3": {
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "macros_add": ["TARGET_NRF_32MHZ_XTAL"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "ANALOGIN",
+ "I2C",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SPISLAVE"
+ ],
+ "detect_code": ["1019"],
+ "release_versions": ["2", "5"],
+ "overrides": { "uart_hwfc": 0 },
+ "device_name": "nRF51822_xxAA"
+ },
+ "TY51822R3_BOOT": {
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "extra_labels_add": ["TY51822R3"],
+ "macros_add": ["TARGET_TY51822R3", "TARGET_NRF_32MHZ_XTAL"]
+ },
+ "TY51822R3_OTA": {
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "extra_labels_add": ["NRF51_DK"],
+ "macros_add": ["TARGET_TY51822R3", "TARGET_NRF_32MHZ_XTAL"]
+ },
+ "ARM_MPS2_Target": {
+ "inherits": ["Target"],
+ "public": false,
+ "device_has": [
+ "AACI",
+ "ANALOGIN",
+ "CLCD",
+ "ETHERNET",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SPI",
+ "SPISLAVE",
+ "TSC"
+ ]
+ },
+ "ARM_MPS2_M0": {
+ "inherits": ["ARM_MPS2_Target"],
+ "core": "Cortex-M0",
+ "supported_toolchains": ["ARM"],
+ "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0"],
+ "macros": [
+ "CMSDK_CM0",
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "device_has": [
+ "AACI",
+ "ANALOGIN",
+ "CLCD",
+ "ETHERNET",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SPI",
+ "SPISLAVE",
+ "TSC",
+ "MPU"
+ ],
+ "release_versions": ["2"]
+ },
+ "ARM_MPS2_M0P": {
+ "inherits": ["ARM_MPS2_Target"],
+ "core": "Cortex-M0+",
+ "supported_toolchains": ["ARM"],
+ "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0P"],
+ "macros": ["CMSDK_CM0plus"],
+ "device_has": [
+ "AACI",
+ "ANALOGIN",
+ "CLCD",
+ "ETHERNET",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SPI",
+ "SPISLAVE",
+ "TSC",
+ "MPU"
+ ],
+ "release_versions": ["2"]
+ },
+ "ARM_MPS2_M3": {
+ "inherits": ["ARM_MPS2_Target"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM"],
+ "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M3"],
+ "macros": ["CMSDK_CM3"],
+ "device_has": [
+ "AACI",
+ "ANALOGIN",
+ "CLCD",
+ "ETHERNET",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SPI",
+ "SPISLAVE",
+ "TSC",
+ "MPU"
+ ],
+ "release_versions": ["2"]
+ },
+ "ARM_MPS2_M4": {
+ "inherits": ["ARM_MPS2_Target"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM"],
+ "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M4"],
+ "macros": ["CMSDK_CM4"],
+ "device_has": [
+ "AACI",
+ "ANALOGIN",
+ "CLCD",
+ "ETHERNET",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SPI",
+ "SPISLAVE",
+ "TSC",
+ "MPU"
+ ],
+ "release_versions": ["2"]
+ },
+ "ARM_MPS2_M7": {
+ "inherits": ["ARM_MPS2_Target"],
+ "core": "Cortex-M7",
+ "supported_toolchains": ["ARM"],
+ "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M7"],
+ "macros": ["CMSDK_CM7"],
+ "device_has": [
+ "AACI",
+ "ANALOGIN",
+ "CLCD",
+ "ETHERNET",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SPI",
+ "SPISLAVE",
+ "TSC",
+ "MPU"
+ ],
+ "release_versions": ["2"]
+ },
+ "ARM_IOTSS_Target": {
+ "inherits": ["Target"],
+ "public": false,
+ "device_has": [
+ "AACI",
+ "ANALOGIN",
+ "CLCD",
+ "ETHERNET",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SPI",
+ "SPISLAVE",
+ "TSC",
+ "MPU"
+ ]
+ },
+ "ARM_IOTSS_BEID": {
+ "inherits": ["ARM_IOTSS_Target"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM"],
+ "extra_labels": ["ARM_SSG", "IOTSS", "IOTSS_BEID"],
+ "macros": ["CMSDK_BEID"],
+ "device_has": [
+ "AACI",
+ "ANALOGIN",
+ "CLCD",
+ "ETHERNET",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SPI",
+ "SPISLAVE",
+ "TSC",
+ "MPU"
+ ],
+ "release_versions": ["2"]
+ },
+ "ARM_CM3DS_MPS2": {
+ "inherits": ["ARM_IOTSS_Target"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "components_add": ["SMSC9220"],
+ "extra_labels": ["ARM_SSG", "CM3DS_MPS2"],
+ "OUTPUT_EXT": "elf",
+ "macros": ["CMSDK_CM3DS"],
+ "device_has": [
+ "ANALOGIN",
+ "EMAC",
+ "FLASH",
+ "I2C",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "RTC",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "TRNG",
+ "USTICKER",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "copy_method": "mps2",
+ "reset_method": "reboot.txt",
+ "overrides": {
+ "target.network-default-interface-type": "ETHERNET"
+ }
+ },
+ "ARM_BEETLE_SOC": {
+ "inherits": ["ARM_IOTSS_Target"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "default_toolchain": "ARM",
+ "extra_labels": ["ARM_SSG", "BEETLE"],
+ "macros": [
+ "CMSDK_BEETLE",
+ "WSF_MS_PER_TICK=20",
+ "WSF_TOKEN_ENABLED=FALSE",
+ "WSF_TRACE_ENABLED=TRUE",
+ "WSF_ASSERT_ENABLED=FALSE",
+ "WSF_PRINTF_MAX_LEN=128",
+ "ASIC",
+ "CONFIG_HOST_REV=0x20",
+ "CONFIG_ALLOW_DEEP_SLEEP=FALSE",
+ "HCI_VS_TARGET",
+ "CONFIG_ALLOW_SETTING_WRITE=TRUE",
+ "WSF_MAX_HANDLERS=20",
+ "NO_LEDS"
+ ],
+ "device_has": [
+ "ANALOGIN",
+ "CLCD",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "MPU"
+ ],
+ "features": ["BLE"],
+ "release_versions": ["2", "5"]
+ },
+ "RZ_A1XX": {
+ "inherits": ["Target"],
+ "core": "Cortex-A9",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["RENESAS", "RZ_A1XX"],
+ "device_has": [
+ "SLEEP",
+ "USTICKER",
+ "RTC",
+ "ANALOGIN",
+ "CAN",
+ "ETHERNET",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES"
+ ],
+ "program_cycle_s": 2,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "RZ_A1H": {
+ "inherits": ["RZ_A1XX"],
+ "supported_form_factors": ["ARDUINO"],
+ "extra_labels_add": ["RZA1H", "MBRZA1H", "RZ_A1_EMAC"],
+ "components_add": ["SD"],
+ "device_has_add": ["EMAC", "FLASH", "LPTICKER"],
+ "release_versions": ["2", "5"],
+ "device_name": "R7S72100",
+ "bootloader_supported": true
+ },
+ "VK_RZ_A1H": {
+ "inherits": ["RZ_A1XX"],
+ "extra_labels_add": ["RZA1H", "VKRZA1H", "RZ_A1_EMAC"],
+ "components_add": ["SD"],
+ "device_has_add": ["EMAC"],
+ "release_versions": ["2", "5"]
+ },
+ "GR_LYCHEE": {
+ "inherits": ["RZ_A1XX"],
+ "supported_form_factors": ["ARDUINO"],
+ "extra_labels_add": ["RZA1UL", "MBRZA1LU"],
+ "components_add": ["SD"],
+ "device_has_add": ["TRNG", "FLASH", "LPTICKER"],
+ "device_has_remove": ["ETHERNET"],
+ "release_versions": ["2", "5"],
+ "device_name": "R7S72103",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": null
+ }
+ },
+ "MAXWSNENV": {
+ "inherits": ["Target"],
+ "core": "Cortex-M3",
+ "macros": ["__SYSTEM_HFX=24000000"],
+ "extra_labels": ["Maxim", "MAX32610"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "STDIO_MESSAGES"
+ ],
+ "features": ["BLE"],
+ "release_versions": []
+ },
+ "MAX32600MBED": {
+ "inherits": ["Target"],
+ "core": "Cortex-M3",
+ "macros": ["__SYSTEM_HFX=24000000"],
+ "extra_labels": ["Maxim", "MAX32600"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "STDIO_MESSAGES"
+ ],
+ "release_versions": ["2", "5"]
+ },
+ "MAX32620HSP": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "extra_labels": ["Maxim", "MAX32620"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES"
+ ],
+ "features": ["BLE"],
+ "release_versions": []
+ },
+ "MAX32620FTHR": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "macros": [
+ "__SYSTEM_HFX=96000000",
+ "TARGET=MAX32620",
+ "TARGET_REV=0x4332",
+ "OPEN_DRAIN_LEDS"
+ ],
+ "extra_labels": ["Maxim", "MAX32620C"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": [
+ "ANALOGIN",
+ "FLASH",
+ "I2C",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "STDIO_MESSAGES",
+ "USTICKER"
+ ],
+ "release_versions": ["2", "5"]
+ },
+ "SDT32620B": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "macros": [
+ "__SYSTEM_HFX=96000000",
+ "TARGET=MAX32620",
+ "TARGET_REV=0x4332",
+ "OPEN_DRAIN_LEDS"
+ ],
+ "detect_code": ["3101"],
+ "extra_labels": ["Maxim", "MAX32620C"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": [
+ "ANALOGIN",
+ "FLASH",
+ "I2C",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "STDIO_MESSAGES",
+ "USTICKER"
+ ],
+ "release_versions": ["2", "5"]
+ },
+ "MAX32625_BASE": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "macros": ["TARGET=MAX32625", "TARGET_REV=0x4132", "OPEN_DRAIN_LEDS"],
+ "extra_labels": ["Maxim", "MAX32625"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "RTC",
+ "SERIAL",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "STDIO_MESSAGES",
+ "USTICKER"
+ ],
+ "device_name": "MAX32625",
+ "release_versions": ["2", "5"],
+ "public": false
+ },
+ "MAX32625MBED": {
+ "inherits": ["MAX32625_BASE"],
+ "extra_labels_add": ["MAX32625_NO_BOOT"]
+ },
+ "SDT32625B": {
+ "inherits": ["MAX32625_BASE"],
+ "extra_labels_add": ["MAX32625_NO_BOOT"],
+ "detect_code": ["3102"]
+ },
+ "MAX32625PICO": {
+ "inherits": ["MAX32625_BASE"],
+ "extra_labels_add": ["MAX32625_BOOT"],
+ "bootloader_supported": true
+ },
+ "MAX32625NEXPAQ": {
+ "inherits": ["MAX32625_BASE"]
+ },
+ "MAX32630FTHR": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "macros": [
+ "__SYSTEM_HFX=96000000",
+ "TARGET=MAX32630",
+ "TARGET_REV=0x4132",
+ "BLE_HCI_UART",
+ "OPEN_DRAIN_LEDS"
+ ],
+ "extra_labels": ["Maxim", "MAX32630"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SPI",
+ "STDIO_MESSAGES",
+ "USTICKER",
+ "MPU"
+ ],
+ "features": ["BLE"],
+ "release_versions": ["2", "5"]
+ },
+ "EFM32": {
+ "inherits": ["Target"],
+ "extra_labels": ["Silicon_Labs", "EFM32"],
+ "macros": [
+ "MBEDTLS_CONFIG_HW_SUPPORT",
+ "MBED_TICKLESS",
+ "EM_MSC_RUN_FROM_FLASH"
+ ],
+ "public": false
+ },
+ "EFM32GG990F1024": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32GG", "1024K", "SL_AES"],
+ "core": "Cortex-M3",
+ "macros_add": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFM32GG990F1024",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFM32GG_STK3700": {
+ "inherits": ["EFM32GG990F1024"],
+ "progen": { "target": "efm32gg-stk" },
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "RTC",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES",
+ "USTICKER",
+ "FLASH",
+ "ITM",
+ "MPU"
+ ],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "48000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "21000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PF7",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFM32LG990F256": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32LG", "256K", "SL_AES"],
+ "core": "Cortex-M3",
+ "macros_add": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFM32LG990F256",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFM32LG_STK3600": {
+ "inherits": ["EFM32LG990F256"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "RTC",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES",
+ "USTICKER",
+ "FLASH",
+ "MPU"
+ ],
+ "forced_reset_timeout": 2,
+ "device_name": "EFM32LG990F256",
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "48000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "21000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PF7",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFM32WG990F256": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32WG", "256K", "SL_AES"],
+ "core": "Cortex-M4F",
+ "macros_add": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFM32WG990F256",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFM32WG_STK3800": {
+ "inherits": ["EFM32WG990F256"],
+ "progen": { "target": "efm32wg-stk" },
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "RTC",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES",
+ "USTICKER",
+ "FLASH",
+ "MPU"
+ ],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "48000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "21000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PF7",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFM32ZG222F32": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32ZG", "32K", "SL_AES"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "macros_add": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"],
+ "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "EFM32ZG222F32",
+ "public": false
+ },
+ "EFM32ZG_STK3200": {
+ "inherits": ["EFM32ZG222F32"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES",
+ "USTICKER"
+ ],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "24000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "21000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PA9",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFM32HG322F64": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32HG", "64K", "SL_AES"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "macros_add": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"],
+ "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "EFM32HG322F64",
+ "public": false
+ },
+ "EFM32HG_STK3400": {
+ "inherits": ["EFM32HG322F64"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES",
+ "USTICKER"
+ ],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "24000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "21000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PA9",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFM32PG1B100F256GM32": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32PG", "256K", "SL_CRYPTO"],
+ "core": "Cortex-M4F",
+ "macros_add": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFM32PG1B100F256GM32",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFM32PG_STK3401": {
+ "inherits": ["EFM32PG1B100F256GM32"],
+ "device_has": [
+ "ANALOGIN",
+ "CRC",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "RTC",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES",
+ "USTICKER",
+ "FLASH",
+ "MPU"
+ ],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "40000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "32000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "cmuHFRCOFreq_32M0Hz",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PA5",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFR32MG1P132F256GM48": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": [
+ "EFR32MG1",
+ "EFR32_1",
+ "256K",
+ "SL_RAIL",
+ "SL_CRYPTO"
+ ],
+ "core": "Cortex-M4F",
+ "macros_add": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFR32MG1P132F256GM48",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFR32MG1P233F256GM48": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": [
+ "EFR32MG1",
+ "EFR32_1",
+ "256K",
+ "SL_RAIL",
+ "SL_CRYPTO"
+ ],
+ "core": "Cortex-M4F",
+ "macros_add": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFR32MG1_BRD4150": {
+ "inherits": ["EFR32MG1P132F256GM48"],
+ "device_has": [
+ "802_15_4_PHY",
+ "ANALOGIN",
+ "CRC",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "RTC",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES",
+ "USTICKER",
+ "FLASH",
+ "MPU"
+ ],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "38400000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "32000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "cmuHFRCOFreq_32M0Hz",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PA5",
+ "macro_name": "EFM_BC_EN"
+ }
+ },
+ "overrides": {
+ "network-default-interface-type": "MESH"
+ },
+ "public": false
+ },
+ "TB_SENSE_1": {
+ "inherits": ["EFR32MG1P233F256GM48"],
+ "device_has": [
+ "802_15_4_PHY",
+ "ANALOGIN",
+ "CRC",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "RTC",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES",
+ "USTICKER",
+ "FLASH",
+ "MPU"
+ ],
+ "forced_reset_timeout": 5,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "38400000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "32000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "cmuHFRCOFreq_32M0Hz",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ }
+ },
+ "overrides": {
+ "network-default-interface-type": "MESH"
+ }
+ },
+ "EFM32PG12B500F1024GL125": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32PG12", "1024K", "SL_CRYPTO"],
+ "core": "Cortex-M4F",
+ "macros_add": [
+ "EFM32PG12B500F1024GL125",
+ "TRANSACTION_QUEUE_SIZE_SPI=4"
+ ],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFM32PG12B500F1024GL125",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFM32PG12_STK3402": {
+ "inherits": ["EFM32PG12B500F1024GL125"],
+ "device_has": [
+ "ANALOGIN",
+ "CRC",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "RTC",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES",
+ "USTICKER",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "40000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "32000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "cmuHFRCOFreq_32M0Hz",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PA5",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFR32MG12P332F1024GL125": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": [
+ "EFR32MG12",
+ "EFR32_12",
+ "1024K",
+ "SL_RAIL",
+ "SL_CRYPTO"
+ ],
+ "core": "Cortex-M4F",
+ "macros_add": [
+ "EFR32MG12P332F1024GL125",
+ "TRANSACTION_QUEUE_SIZE_SPI=4"
+ ],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFR32MG12P332F1024GL125",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "TB_SENSE_12": {
+ "inherits": ["EFR32MG12P332F1024GL125"],
+ "device_name": "EFR32MG12P332F1024GL125",
+ "device_has": [
+ "802_15_4_PHY",
+ "ANALOGIN",
+ "CRC",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "RTC",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES",
+ "USTICKER",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "forced_reset_timeout": 5,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "38400000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "32000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "cmuHFRCOFreq_32M0Hz",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ }
+ },
+ "overrides": {
+ "network-default-interface-type": "MESH"
+ }
+ },
+ "EFM32GG11B820F2048GL192": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32GG11", "2048K", "SL_CRYPTO"],
+ "core": "Cortex-M4F",
+ "macros_add": [
+ "EFM32GG11B820F2048GL192",
+ "TRANSACTION_QUEUE_SIZE_SPI=4"
+ ],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFM32GG11B820F2048GL192",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFM32GG11_STK3701": {
+ "inherits": ["EFM32GG11B820F2048GL192"],
+ "device_name": "EFM32GG11B820F2048GL192",
+ "device_has": [
+ "ANALOGIN",
+ "CRC",
+ "EMAC",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "QSPI",
+ "RTC",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES",
+ "USTICKER",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "forced_reset_timeout": 5,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "50000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "32000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "cmuHFRCOFreq_32M0Hz",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PE1",
+ "macro_name": "EFM_BC_EN"
+ },
+ "qspi_flash_enable": {
+ "help": "Pin to pull high for enabling the on-board QSPI flash",
+ "value": "PG13",
+ "macro_name": "QSPI_FLASH_EN"
+ }
+ },
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "WIZWIKI_W7500": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0",
+ "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
+ "inherits": ["Target"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "release_versions": ["2", "5"]
+ },
+ "WIZWIKI_W7500P": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0",
+ "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500P"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
+ "inherits": ["Target"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "release_versions": ["2", "5"]
+ },
+ "WIZWIKI_W7500ECO": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0",
+ "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500ECO"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SPI",
+ "SPISLAVE",
+ "STDIO_MESSAGES"
+ ],
+ "release_versions": ["2", "5"]
+ },
+ "SAMR21G18A": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0+",
+ "macros": [
+ "__SAMR21G18A__",
+ "I2C_MASTER_CALLBACK_MODE=true",
+ "EXTINT_CALLBACK_MODE=true",
+ "USART_CALLBACK_MODE=true",
+ "TC_ASYNC=true"
+ ],
+ "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMR21"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH"
+ ],
+ "release_versions": ["2"],
+ "device_name": "ATSAMR21G18A"
+ },
+ "SAMD21J18A": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0+",
+ "macros": [
+ "__SAMD21J18A__",
+ "I2C_MASTER_CALLBACK_MODE=true",
+ "EXTINT_CALLBACK_MODE=true",
+ "USART_CALLBACK_MODE=true",
+ "TC_ASYNC=true"
+ ],
+ "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH"
+ ],
+ "release_versions": ["2"],
+ "device_name": "ATSAMD21J18A"
+ },
+ "SAMD21G18A": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0+",
+ "macros": [
+ "__SAMD21G18A__",
+ "I2C_MASTER_CALLBACK_MODE=true",
+ "EXTINT_CALLBACK_MODE=true",
+ "USART_CALLBACK_MODE=true",
+ "TC_ASYNC=true"
+ ],
+ "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH"
+ ],
+ "release_versions": ["2"],
+ "device_name": "ATSAMD21G18A"
+ },
+ "SAML21J18A": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0+",
+ "macros": [
+ "__SAML21J18A__",
+ "I2C_MASTER_CALLBACK_MODE=true",
+ "EXTINT_CALLBACK_MODE=true",
+ "USART_CALLBACK_MODE=true",
+ "TC_ASYNC=true"
+ ],
+ "extra_labels": ["Atmel", "SAM_CortexM0P", "SAML21"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH"
+ ],
+ "device_name": "ATSAML21J18A"
+ },
+ "SAMG55J19": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "extra_labels": ["Atmel", "SAM_CortexM4", "SAMG55"],
+ "macros": [
+ "__SAMG55J19__",
+ "BOARD=75",
+ "I2C_MASTER_CALLBACK_MODE=true",
+ "EXTINT_CALLBACK_MODE=true",
+ "USART_CALLBACK_MODE=true",
+ "TC_ASYNC=true"
+ ],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+ "default_toolchain": "ARM",
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "MPU"
+ ],
+ "default_lib": "std",
+ "device_name": "ATSAMG55J19"
+ },
+ "MCU_NRF51_UNIFIED": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0",
+ "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
+ "macros": [
+ "BOARD_PCA10028",
+ "NRF51",
+ "TARGET_NRF51822",
+ "BLE_STACK_SUPPORT_REQD",
+ "SOFTDEVICE_PRESENT",
+ "S130",
+ "TARGET_MCU_NRF51822",
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
+ "NO_SYSTICK",
+ "MBED_TICKLESS"
+ ],
+ "MERGE_BOOTLOADER": false,
+ "extra_labels": [
+ "NORDIC",
+ "MCU_NRF51",
+ "MCU_NRF51822_UNIFIED",
+ "NRF5x",
+ "NRF51",
+ "SDK_11",
+ "NORDIC_SOFTDEVICE"
+ ],
+ "OUTPUT_EXT": "hex",
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "public": false,
+ "MERGE_SOFT_DEVICE": true,
+ "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+ {
+ "boot": "",
+ "name": "s130_nrf51_2.0.0_softdevice.hex",
+ "offset": 110592
+ }
+ ],
+ "detect_code": ["1070"],
+ "post_binary_hook": {
+ "function": "MCU_NRF51Code.binary_hook",
+ "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
+ },
+ "program_cycle_s": 6,
+ "features": ["BLE"],
+ "config": {
+ "lf_clock_src": {
+ "value": "NRF_LF_SRC_XTAL",
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
+ },
+ "uart_hwfc": {
+ "help": "Value: 1 for enable, 0 for disable",
+ "value": 1,
+ "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
+ }
+ },
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ]
+ },
+ "MCU_NRF51_16K_UNIFIED_S130": {
+ "inherits": ["MCU_NRF51_UNIFIED"],
+ "extra_labels_add": [
+ "MCU_NORDIC_16K",
+ "MCU_NRF51_16K_S130",
+ "MCU_NRF51_16K"
+ ],
+ "macros_add": [
+ "TARGET_MCU_NORDIC_16K",
+ "TARGET_MCU_NRF51_16K_S130",
+ "TARGET_MCU_NRF51_16K"
+ ],
+ "public": false
+ },
+ "MCU_NRF51_32K_UNIFIED": {
+ "inherits": ["MCU_NRF51_UNIFIED"],
+ "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
+ "macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
+ "public": false
+ },
+ "NRF51_DK": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "ANALOGIN",
+ "I2C",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SPISLAVE"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "SDT51822B": {
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "ANALOGIN",
+ "I2C",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SPISLAVE"
+ ],
+ "detect_code": ["3103"],
+ "release_versions": ["2", "5"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "NRF51_DONGLE": {
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "progen": { "target": "nrf51-dongle" },
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "I2C",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SPISLAVE"
+ ],
+ "release_versions": ["2", "5"]
+ },
+ "OSHCHIP": {
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "overrides": { "lf_clock_src": "NRF_LF_SRC_RC" },
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "ANALOGIN",
+ "I2C",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE"
+ ],
+ "device_name": "nRF51822_xxAC"
+ },
+ "MCU_NRF52832": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "static_memory_defines": false,
+ "macros": [
+ "BOARD_PCA10040",
+ "NRF52",
+ "TARGET_NRF52832",
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
+ "MBED_TICKLESS",
+ "MBED_MPU_CUSTOM"
+ ],
+ "device_has": [
+ "ANALOGIN",
+ "FLASH",
+ "I2C",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "ITM",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SYSTICK_CLK_OFF_DURING_SLEEP",
+ "TRNG",
+ "USTICKER"
+ ],
+ "extra_labels": [
+ "NORDIC",
+ "NRF5x",
+ "NRF52",
+ "SDK_14_2",
+ "NORDIC_SOFTDEVICE",
+ "SOFTDEVICE_COMMON",
+ "SOFTDEVICE_S132_FULL"
+ ],
+ "config": {
+ "lf_clock_src": {
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC",
+ "help": "Select Low Frequency clock source. Options: NRF_LF_SRC_XTAL, NRF_LF_SRC_SYNTH, and NRF_LF_SRC_RC",
+ "value": "NRF_LF_SRC_XTAL"
+ },
+ "lf_clock_rc_calib_timer_interval": {
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL",
+ "value": 16
+ },
+ "lf_clock_rc_calib_mode_config": {
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG",
+ "value": 0
+ }
+ },
+ "OUTPUT_EXT": "hex",
+ "is_disk_virtual": true,
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "public": false,
+ "detect_code": ["1101"],
+ "program_cycle_s": 6,
+ "bootloader_supported": true
+ },
+ "NRF52_DK": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA",
+ "macros_add": [
+ "WSF_MAX_HANDLERS=10"
+ ],
+ "device_has_remove": ["ITM"]
+ },
+ "SDT52832B": {
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "detect_code": ["3104"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "UBLOX_EVA_NINA": {
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "UBLOX_EVK_NINA_B1": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "MTB_UBLOX_NINA_B1": {
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "MTB_LAIRD_BL652": {
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "MTB_MURATA_WSM_BL241": {
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA",
+ "detect_code": ["0466"]
+ },
+ "MTB_ACONNO_ACN52832": {
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "DELTA_DFBM_NQ620": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA",
+ "device_has_remove": ["ITM"]
+ },
+ "MCU_NRF52840": {
+ "inherits": ["Target"],
+ "components_add": ["QSPIF"],
+ "core": "Cortex-M4F",
+ "static_memory_defines": false,
+ "macros": [
+ "BOARD_PCA10056",
+ "NRF52840_XXAA",
+ "TARGET_NRF52840",
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
+ "MBED_TICKLESS",
+ "MBEDTLS_CONFIG_HW_SUPPORT",
+ "WSF_MAX_HANDLERS=10",
+ "MBED_MPU_CUSTOM"
+ ],
+ "features": ["CRYPTOCELL310"],
+ "device_has": [
+ "ANALOGIN",
+ "FLASH",
+ "I2C",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "ITM",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SYSTICK_CLK_OFF_DURING_SLEEP",
+ "TRNG",
+ "USTICKER",
+ "QSPI"
+ ],
+ "extra_labels": [
+ "NORDIC",
+ "NRF5x",
+ "NRF52",
+ "SDK_14_2",
+ "NORDIC_SOFTDEVICE",
+ "SOFTDEVICE_COMMON",
+ "SOFTDEVICE_S140_FULL"
+ ],
+ "config": {
+ "lf_clock_src": {
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC",
+ "help": "Select Low Frequency clock source. Options: NRF_LF_SRC_XTAL, NRF_LF_SRC_SYNTH, and NRF_LF_SRC_RC",
+ "value": "NRF_LF_SRC_XTAL"
+ },
+ "lf_clock_rc_calib_timer_interval": {
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL",
+ "value": 16
+ },
+ "lf_clock_rc_calib_mode_config": {
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG",
+ "value": 0
+ }
+ },
+ "overrides": {
+ "mpu-rom-end": "0x1fffffff"
+ },
+ "OUTPUT_EXT": "hex",
+ "is_disk_virtual": true,
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "public": false,
+ "detect_code": ["1101"],
+ "program_cycle_s": 6,
+ "bootloader_supported": true
+ },
+ "NRF52840_DK": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF52840"],
+ "release_versions": ["5"],
+ "device_name": "nRF52840_xxAA"
+ },
+ "MTB_LAIRD_BL654": {
+ "inherits": ["MCU_NRF52840"],
+ "release_versions": ["5"],
+ "device_name": "nRF52840_xxAA",
+ "detect_code": ["0465"],
+ "features_remove": ["CRYPTOCELL310"],
+ "macros_remove": ["MBEDTLS_CONFIG_HW_SUPPORT"],
+ "overrides": {
+ "lf_clock_src": "NRF_LF_SRC_RC"
+ }
+ },
+ "BLUEPILL_F103C8": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M3",
+ "default_toolchain": "GCC_ARM",
+ "extra_labels_add": ["STM32F1", "STM32F103C8"],
+ "supported_toolchains": ["GCC_ARM"],
+ "device_has_add": [
+ "CAN",
+ "SERIAL_ASYNCH",
+ "FLASH"
+ ],
+ "device_has_remove": ["STDIO_MESSAGES", "LPTICKER"]
+ },
+ "NUMAKER_PFM_NUC472": {
+ "core": "Cortex-M4F",
+ "default_toolchain": "ARM",
+ "extra_labels": [
+ "NUVOTON",
+ "NUC472",
+ "NU_XRAM_SUPPORTED",
+ "FLASH_CMSIS_ALGO",
+ "NUVOTON_EMAC"
+ ],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "config": {
+ "gpio-irq-debounce-enable": {
+ "help": "Enable GPIO IRQ debounce",
+ "value": 0
+ },
+ "gpio-irq-debounce-enable-list": {
+ "help": "Comma separated pin list to enable GPIO IRQ debounce",
+ "value": "NC"
+ },
+ "gpio-irq-debounce-clock-source": {
+ "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_IRC10K",
+ "value": "GPIO_DBCTL_DBCLKSRC_IRC10K"
+ },
+ "gpio-irq-debounce-sample-rate": {
+ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+ "value": "GPIO_DBCTL_DBCLKSEL_16"
+ }
+ },
+ "inherits": ["Target"],
+ "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "LPTICKER_DELAY_TICKS=3"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "STDIO_MESSAGES",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "TRNG",
+ "CAN",
+ "FLASH",
+ "EMAC",
+ "MPU"
+ ],
+ "release_versions": ["5"],
+ "device_name": "NUC472HI8AE",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NCS36510": {
+ "inherits": ["Target"],
+ "core": "Cortex-M3",
+ "extra_labels": ["ONSEMI"],
+ "config": {
+ "mac-addr-low": {
+ "help": "Lower 32 bits of the MAC extended address. All FFs indicates that factory programmed MAC address shall be used. In order to override the factory programmed MAC address this value needs to be changed from 0xFFFFFFFF to any chosen value.",
+ "value": "0xFFFFFFFF"
+ },
+ "mac-addr-high": {
+ "help": "Higher 32 bits of the MAC extended address. All FFs indicates that factory programmed MAC address shall be used. In order to override the factory programmed MAC address this value needs to be changed from 0xFFFFFFFF to any chosen value.",
+ "value": "0xFFFFFFFF"
+ },
+ "32KHz-clk-trim": {
+ "help": "32KHz clock trim",
+ "value": "0x39"
+ },
+ "32MHz-clk-trim": {
+ "help": "32MHz clock trim",
+ "value": "0x17"
+ },
+ "rssi-trim": {
+ "help": "RSSI trim",
+ "value": "0x3D"
+ },
+ "txtune-trim": {
+ "help": "TX tune trim",
+ "value": "0xFFFFFFFF"
+ }
+ },
+ "OUTPUT_EXT": "hex",
+ "post_binary_hook": {
+ "function": "NCS36510TargetCode.ncs36510_addfib"
+ },
+ "macros": [
+ "CM3",
+ "CPU_NCS36510",
+ "TARGET_NCS36510",
+ "LOAD_ADDRESS=0x3000"
+ ],
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "device_has": [
+ "ANALOGIN",
+ "SERIAL",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "TRNG",
+ "SPISLAVE",
+ "802_15_4_PHY",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"]
+ },
+ "NUMAKER_PFM_M453": {
+ "core": "Cortex-M4F",
+ "default_toolchain": "ARM",
+ "extra_labels": [
+ "NUVOTON",
+ "M451",
+ "NUMAKER_PFM_M453",
+ "FLASH_CMSIS_ALGO"
+ ],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "config": {
+ "gpio-irq-debounce-enable": {
+ "help": "Enable GPIO IRQ debounce",
+ "value": 0
+ },
+ "gpio-irq-debounce-enable-list": {
+ "help": "Comma separated pin list to enable GPIO IRQ debounce",
+ "value": "NC"
+ },
+ "gpio-irq-debounce-clock-source": {
+ "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
+ "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
+ },
+ "gpio-irq-debounce-sample-rate": {
+ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+ "value": "GPIO_DBCTL_DBCLKSEL_16"
+ }
+ },
+ "inherits": ["Target"],
+ "macros_add": ["LPTICKER_DELAY_TICKS=3"],
+ "progen": { "target": "numaker-pfm-m453" },
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "STDIO_MESSAGES",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "CAN",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "M453VG6AE",
+ "bootloader_supported": true
+ },
+ "NUMAKER_PFM_NANO130": {
+ "core": "Cortex-M0",
+ "default_toolchain": "ARM",
+ "extra_labels": ["NUVOTON", "NANO100", "NANO130KE3BN"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "config": {
+ "gpio-irq-debounce-enable": {
+ "help": "Enable GPIO IRQ debounce",
+ "value": 0
+ },
+ "gpio-irq-debounce-enable-list": {
+ "help": "Comma separated pin list to enable GPIO IRQ debounce",
+ "value": "NC"
+ },
+ "gpio-irq-debounce-clock-source": {
+ "help": "Select GPIO IRQ debounce clock source: GPIO_DBCLKSRC_HCLK or GPIO_DBCLKSRC_IRC10K",
+ "value": "GPIO_DBCLKSRC_IRC10K"
+ },
+ "gpio-irq-debounce-sample-rate": {
+ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, ..., or GPIO_DBCLKSEL_32768",
+ "value": "GPIO_DBCLKSEL_16"
+ },
+ "clock-pll": {
+ "help": "Choose clock source to clock PLL: NU_HXT_PLL or NU_HIRC_PLL",
+ "macro_name": "NU_CLOCK_PLL",
+ "value": "NU_HIRC_PLL"
+ }
+ },
+ "inherits": ["Target"],
+ "macros": [
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
+ "MBED_FAULT_HANDLER_DISABLED",
+ "LPTICKER_DELAY_TICKS=3"
+ ],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "STDIO_MESSAGES",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH"
+ ],
+ "release_versions": ["5"],
+ "device_name": "NANO130KE3BN"
+ },
+ "HI2110": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0",
+ "default_toolchain": "GCC_ARM",
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "extra_labels": ["ublox"],
+ "macros": [
+ "TARGET_PROCESSOR_FAMILY_BOUDICA",
+ "BOUDICA_SARA",
+ "NDEBUG=1",
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "public": false,
+ "target_overrides": {
+ "*": {
+ "core.stdio-flush-at-exit": false
+ }
+ },
+ "device_has": [
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SLEEP",
+ "STDIO_MESSAGES"
+ ],
+ "default_lib": "std",
+ "release_versions": []
+ },
+ "SARA_NBIOT": {
+ "inherits": ["HI2110"],
+ "extra_labels": ["ublox", "HI2110"],
+ "public": false
+ },
+ "SARA_NBIOT_EVK": {
+ "inherits": ["SARA_NBIOT"],
+ "extra_labels": ["ublox", "HI2110", "SARA_NBIOT"]
+ },
+ "MCU_RTL8195A": {
+ "core": "Cortex-M3",
+ "default_toolchain": "GCC_ARM",
+ "macros": [
+ "__RTL8195A__",
+ "CONFIG_PLATFORM_8195A",
+ "CONFIG_MBED_ENABLED",
+ "PLATFORM_CMSIS_RTOS",
+ "MBED_FAULT_HANDLER_DISABLED",
+ "MBED_MPU_CUSTOM"
+ ],
+ "inherits": ["Target"],
+ "extra_labels": ["Realtek", "AMEBA", "RTW_EMAC"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SPI",
+ "TRNG",
+ "FLASH"
+ ],
+ "public": false,
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "post_binary_hook": {
+ "function": "RTL8195ACode.binary_hook",
+ "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
+ },
+ "release_versions": ["5"],
+ "overrides": {
+ "network-default-interface-type": "WIFI"
+ }
+ },
+ "REALTEK_RTL8195AM": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_RTL8195A"],
+ "detect_code": ["4600"],
+ "extra_labels_add": ["RTL8195A"]
+ },
+ "VBLUNO51_LEGACY": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K"],
+ "detect_code": ["C006"],
+ "overrides": { "uart_hwfc": 0 },
+ "extra_labels_add": ["VBLUNO51"]
+ },
+ "VBLUNO51_BOOT": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "detect_code": ["C006"],
+ "overrides": { "uart_hwfc": 0 },
+ "extra_labels_add": ["VBLUNO51"],
+ "macros_add": ["TARGET_VBLUNO51"]
+ },
+ "VBLUNO51_OTA": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "detect_code": ["C006"],
+ "overrides": { "uart_hwfc": 0 },
+ "extra_labels_add": ["VBLUNO51"],
+ "macros_add": ["TARGET_VBLUNO51"]
+ },
+ "VBLUNO51": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "detect_code": ["C006"],
+ "overrides": { "uart_hwfc": 0 },
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "ANALOGIN",
+ "I2C",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "SPISLAVE"
+ ],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAC"
+ },
+ "DISCO_L496AG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L496AG", "STM32L496xG"],
+ "components_add": ["QSPIF"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "macros_add": [
+ "MBED_TICKLESS"
+ ],
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0822"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU",
+ "QSPI"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L496AG",
+ "bootloader_supported": true
+ },
+ "NUCLEO_L496ZG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L496ZG", "STM32L496xG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "macros_add": [
+ "MBED_TICKLESS"
+ ],
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0823"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L496ZG",
+ "bootloader_supported": true
+ },
+ "NUCLEO_L496ZG_P": {
+ "inherits": ["NUCLEO_L496ZG"],
+ "detect_code": ["0828"]
+ },
+ "NUCLEO_L4R5ZI": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L4R5ZI", "STM32L4R5xI"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
+ },
+ "macros_add": [
+ "MBED_TICKLESS"
+ ],
+ "overrides": { "lpticker_delay_ticks": 4 },
+ "detect_code": ["0776"],
+ "device_has_add": [
+ "ANALOGOUT",
+ "CAN",
+ "CRC",
+ "SERIAL_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L4R5ZI",
+ "bootloader_supported": true
+ },
+ "NUCLEO_L4R5ZI_P": {
+ "inherits": ["NUCLEO_L4R5ZI"],
+ "detect_code": ["0781"]
+ },
+ "VBLUNO52": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "MCU_M480": {
+ "core": "Cortex-M4F",
+ "default_toolchain": "ARM",
+ "public": false,
+ "extra_labels": ["NUVOTON", "M480", "FLASH_CMSIS_ALGO", "NUVOTON_EMAC"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "config": {
+ "gpio-irq-debounce-enable": {
+ "help": "Enable GPIO IRQ debounce",
+ "value": 0
+ },
+ "gpio-irq-debounce-enable-list": {
+ "help": "Comma separated pin list to enable GPIO IRQ debounce",
+ "value": "NC"
+ },
+ "gpio-irq-debounce-clock-source": {
+ "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
+ "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
+ },
+ "gpio-irq-debounce-sample-rate": {
+ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+ "value": "GPIO_DBCTL_DBCLKSEL_16"
+ },
+ "usb-device-hsusbd": {
+ "help": "Select high-speed USB device or not",
+ "value": 1
+ },
+ "ctrl01-enable": {
+ "help": "Enable control_01",
+ "value": 0
+ }
+ },
+ "inherits": ["Target"],
+ "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "LPTICKER_DELAY_TICKS=3"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "STDIO_MESSAGES",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "CAN",
+ "EMAC",
+ "MPU"
+ ],
+ "release_versions": ["5"],
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NUMAKER_PFM_M487": {
+ "inherits": ["MCU_M480"],
+ "device_name": "M487JIDAE"
+ },
+ "NUMAKER_IOT_M487": {
+ "inherits": ["MCU_M480"],
+ "device_name": "M487JIDAE"
+ },
+ "TMPM066": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0",
+ "is_disk_virtual": true,
+ "extra_labels": ["TOSHIBA"],
+ "macros": [
+ "__TMPM066__",
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ ],
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "device_has": [
+ "USTICKER",
+ "ANALOGIN",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SLEEP",
+ "I2C",
+ "I2CSLAVE",
+ "STDIO_MESSAGES",
+ "PWMOUT"
+ ],
+ "device_name": "TMPM066FWUG",
+ "detect_code": ["7011"],
+ "release_versions": ["5"]
+ },
+ "SAKURAIO_EVB_01": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": [],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F411xE", "STM32F411RE"],
+ "device_has": [
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES",
+ "MPU"
+ ],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "device_has_add": [
+ "SERIAL_ASYNCH",
+ "FLASH"
+ ],
+ "release_versions": ["2"],
+ "device_name": "STM32F411RE"
+ },
+ "TMPM46B": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "is_disk_virtual": true,
+ "extra_labels": ["TOSHIBA"],
+ "macros": ["__TMPM46B__"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "device_has": [
+ "USTICKER",
+ "ANALOGIN",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_FC",
+ "SPI",
+ "I2C",
+ "STDIO_MESSAGES",
+ "TRNG",
+ "FLASH",
+ "SLEEP"
+ ],
+ "device_name": "TMPM46BF10FG",
+ "detect_code": ["7013"],
+ "release_versions": ["5"],
+ "bootloader_supported": true
+ },
+ "ARM_FM": {
+ "inherits": ["Target"],
+ "public": false,
+ "macros": ["__ARM_FM"],
+ "extra_labels": ["ARM_FM"]
+ },
+ "FVP_MPS2": {
+ "inherits": ["ARM_FM"],
+ "public": false,
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "OUTPUT_EXT": "elf",
+ "device_has": [
+ "AACI",
+ "ANALOGIN",
+ "CLCD",
+ "EMAC",
+ "FLASH",
+ "I2C",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "SERIAL",
+ "SPI",
+ "SPISLAVE",
+ "TSC",
+ "USTICKER"
+ ],
+ "release_versions": ["5"],
+ "components_add": ["LAN91C111"],
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "FVP_MPS2_M0": {
+ "inherits": ["FVP_MPS2"],
+ "core": "Cortex-M0",
+ "macros_add": ["CMSDK_CM0"]
+ },
+ "FVP_MPS2_M0P": {
+ "inherits": ["FVP_MPS2"],
+ "core": "Cortex-M0+",
+ "macros_add": ["CMSDK_CM0plus"],
+ "device_has_add": ["MPU"]
+ },
+ "FVP_MPS2_M3": {
+ "inherits": ["FVP_MPS2"],
+ "core": "Cortex-M3",
+ "macros_add": ["CMSDK_CM3"],
+ "device_has_add": ["MPU"]
+ },
+ "FVP_MPS2_M4": {
+ "inherits": ["FVP_MPS2"],
+ "core": "Cortex-M4",
+ "macros_add": ["CMSDK_CM4"],
+ "device_has_add": ["MPU"]
+ },
+ "FVP_MPS2_M7": {
+ "inherits": ["FVP_MPS2"],
+ "core": "Cortex-M7",
+ "macros_add": ["CMSDK_CM7"],
+ "device_has_add": ["MPU"]
+ },
+ "NUMAKER_PFM_M2351": {
+ "core": "Cortex-M23-NS",
+ "default_toolchain": "ARMC6",
+ "extra_labels": [
+ "NUVOTON",
+ "M2351",
+ "M2351KIAAEES",
+ "FLASH_CMSIS_ALGO"
+ ],
+ "OUTPUT_EXT": "hex",
+ "macros": [
+ "MBED_FAULT_HANDLER_DISABLED",
+ "MBED_TZ_DEFAULT_ACCESS=1",
+ "LPTICKER_DELAY_TICKS=3"
+ ],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARMC6"],
+ "config": {
+ "gpio-irq-debounce-enable": {
+ "help": "Enable GPIO IRQ debounce",
+ "value": 0
+ },
+ "gpio-irq-debounce-enable-list": {
+ "help": "Comma separated pin list to enable GPIO IRQ debounce",
+ "value": "NC"
+ },
+ "gpio-irq-debounce-clock-source": {
+ "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
+ "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
+ },
+ "gpio-irq-debounce-sample-rate": {
+ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+ "value": "GPIO_DBCTL_DBCLKSEL_16"
+ }
+ },
+ "overrides": {
+ "mpu-rom-end": "0x1fffffff"
+ },
+ "inherits": ["Target"],
+ "device_has": [
+ "USTICKER",
+ "LPTICKER",
+ "RTC",
+ "ANALOGIN",
+ "I2C",
+ "I2CSLAVE",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "STDIO_MESSAGES",
+ "SLEEP",
+ "SPI",
+ "SPISLAVE",
+ "SPI_ASYNCH",
+ "TRNG",
+ "FLASH",
+ "MPU"
+ ],
+ "detect_code": ["1305"],
+ "release_versions": ["5"],
+ "device_name": "M2351KIAAEES",
+ "bootloader_supported": true
+ },
+ "TMPM3H6": {
+ "inherits": ["Target"],
+ "core": "Cortex-M3",
+ "is_disk_virtual": true,
+ "extra_labels": ["TOSHIBA"],
+ "macros": ["__TMPM3H6__"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "device_has": [
+ "USTICKER",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "I2C",
+ "I2CSLAVE",
+ "STDIO_MESSAGES",
+ "MPU"
+ ],
+ "device_name": "TMPM3H6FWFG",
+ "detect_code": ["7012"],
+ "release_versions": ["5"]
+ },
+ "TMPM4G9": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "is_disk_virtual": true,
+ "extra_labels": ["TOSHIBA"],
+ "macros": ["__TMPM4G9__"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "device_has": [
+ "ANALOGIN",
+ "ANALOGOUT",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SPI",
+ "I2C",
+ "I2CSLAVE",
+ "STDIO_MESSAGES",
+ "FLASH",
+ "SLEEP",
+ "USTICKER",
+ "MPU"
+ ],
+ "device_name": "TMPM4G9F15FG",
+ "detect_code": ["7015"],
+ "release_versions": ["5"],
+ "bootloader_supported": true
+ },
+ "MCU_PSOC6": {
+ "inherits": ["Target"],
+ "macros": ["MBED_MPU_CUSTOM"],
+ "default_toolchain": "GCC_ARM",
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "core": "Cortex-M4F",
+ "OUTPUT_EXT": "hex",
+ "device_has": [
+ "USTICKER",
+ "INTERRUPTIN",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "PORTIN",
+ "PORTOUT",
+ "PORTINOUT",
+ "RTC",
+ "PWMOUT",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "I2C",
+ "I2C_ASYNCH",
+ "SPI",
+ "SPI_ASYNCH",
+ "STDIO_MESSAGES",
+ "LPTICKER",
+ "SLEEP",
+ "FLASH",
+ "TRNG",
+ "CRC"
+ ],
+ "release_versions": ["5"],
+ "extra_labels": ["Cypress", "PSOC6"],
+ "public": false
+ },
+ "MCU_PSOC6_M0": {
+ "inherits": ["MCU_PSOC6"],
+ "core": "Cortex-M0+",
+ "macros_add": ["MCU_PSOC6_M0"],
+ "public": false
+ },
+ "MCU_PSOC6_M4": {
+ "inherits": ["MCU_PSOC6"],
+ "macros_add": ["MCU_PSOC6_M4"],
+ "public": false
+ },
+ "CY8CKIT_062_WIFI_BT": {
+ "inherits": ["MCU_PSOC6_M4"],
+ "features": ["BLE"],
+ "supported_form_factors": ["ARDUINO"],
+ "extra_labels_add": ["PSOC6_01", "WICED", "CYW43XXX", "CYW4343X", "CORDIO"],
+ "macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"],
+ "detect_code": ["1900"],
+ "hex_filename": "psoc6_01_cm0p_sleep.hex",
+ "post_binary_hook": {
+ "function": "PSOC6Code.complete"
+ },
+ "overrides": {
+ "network-default-interface-type": "WIFI"
+ }
+ },
+ "CY8CMOD_062_4343W": {
+ "inherits": ["MCU_PSOC6_M4"],
+ "features": ["BLE"],
+ "device_has_remove": ["ANALOGOUT"],
+ "extra_labels_add": ["PSOC6_02", "WICED", "CYW43XXX", "CYW4343X", "CORDIO"],
+ "macros_add": ["CY8C624ABZI_D44", "PSOC6_DYNSRM_DISABLE=1"],
+ "public": false,
+ "overrides": {
+ "network-default-interface-type": "WIFI"
+ }
+ },
+ "CY8CPROTO_062_4343W": {
+ "inherits": ["CY8CMOD_062_4343W"],
+ "detect_code": ["1901"],
+ "hex_filename": "psoc6_02_cm0p_sleep.hex",
+ "post_binary_hook": {
+ "function": "PSOC6Code.complete"
+ }
+ },
+ "CY8CKIT_062_BLE": {
+ "inherits": ["MCU_PSOC6_M4"],
+ "supported_form_factors": ["ARDUINO"],
+ "extra_labels_add": ["PSOC6_01"],
+ "macros_add": ["CY8C6347BZI_BLD53", "PSOC6_DYNSRM_DISABLE=1"],
+ "detect_code": ["1902"],
+ "hex_filename": "psoc6_01_cm0p_sleep.hex",
+ "post_binary_hook": {
+ "function": "PSOC6Code.complete"
+ }
+ },
+ "CY8CKIT_062_4343W": {
+ "inherits": ["MCU_PSOC6_M4"],
+ "features": ["BLE"],
+ "supported_form_factors": ["ARDUINO"],
+ "device_has_remove": ["ANALOGOUT"],
+ "extra_labels_add": ["PSOC6_02", "WICED", "CYW43XXX", "CYW4343X", "CORDIO"],
+ "macros_add": ["CY8C624ABZI_D44", "PSOC6_DYNSRM_DISABLE=1"],
+ "detect_code": ["1905"],
+ "hex_filename": "psoc6_02_cm0p_sleep.hex",
+ "post_binary_hook": {
+ "function": "PSOC6Code.complete"
+ },
+ "overrides": {
+ "network-default-interface-type": "WIFI"
+ }
+ },
+ "CYW943012P6EVB_01": {
+ "inherits": ["MCU_PSOC6_M4"],
+ "features": ["BLE"],
+ "extra_labels_add": ["PSOC6_01", "WICED", "CYW43XXX", "CYW43012", "CORDIO"],
+ "macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"],
+ "detect_code": ["1906"],
+ "hex_filename": "psoc6_01_cm0p_sleep.hex",
+ "post_binary_hook": {
+ "function": "PSOC6Code.complete"
+ },
+ "overrides": {
+ "network-default-interface-type": "WIFI"
+ }
+ },
+ "FUTURE_SEQUANA_M0": {
+ "inherits": ["MCU_PSOC6_M0"],
+ "supported_form_factors": ["ARDUINO"],
+ "extra_labels_add": ["PSOC6_FUTURE", "CY8C63XX", "FUTURE_SEQUANA"],
+ "extra_labels_remove": ["PSOC6"],
+ "device_has_remove": ["TRNG", "CRC"],
+ "macros_add": ["CY8C6347BZI_BLD53"],
+ "detect_code": ["6000"],
+ "post_binary_hook": {
+ "function": "PSOC6Code.complete"
+ },
+ "config": {
+ "system-clock": {
+ "help": "Desired frequency of main clock (Hz)",
+ "value": "100000000UL",
+ "macro_name": "CY_CLK_HFCLK0_FREQ_HZ"
+ },
+ "peri-clock": {
+ "help": "Desired frequency of peripheral clock (Hz)",
+ "value": "50000000UL",
+ "macro_name": "CY_CLK_PERICLK_FREQ_HZ"
+ },
+ "m0-clock": {
+ "help": "Desired frequency of M0+ core clock (Hz)",
+ "value": "50000000UL",
+ "macro_name": "CY_CLK_SLOWCLK_FREQ_HZ"
+ }
+ }
+ },
+ "FUTURE_SEQUANA": {
+ "inherits": ["MCU_PSOC6_M4"],
+ "supported_form_factors": ["ARDUINO"],
+ "extra_labels_add": ["PSOC6_FUTURE", "CY8C63XX", "CORDIO"],
+ "extra_labels_remove": ["PSOC6"],
+ "device_has_remove": ["TRNG", "CRC"],
+ "macros_add": ["CY8C6347BZI_BLD53"],
+ "detect_code": ["6000"],
+ "hex_filename": "psoc63_m0_default_1.03.hex",
+ "post_binary_hook": {
+ "function": "PSOC6Code.complete"
+ },
+ "config": {
+ "system-clock": {
+ "help": "Desired frequency of main clock (Hz)",
+ "value": "100000000UL",
+ "macro_name": "CY_CLK_HFCLK0_FREQ_HZ"
+ },
+ "peri-clock": {
+ "help": "Desired frequency of peripheral clock (Hz)",
+ "value": "50000000UL",
+ "macro_name": "CY_CLK_PERICLK_FREQ_HZ"
+ },
+ "m0-clock": {
+ "help": "Desired frequency of M0+ core clock (Hz)",
+ "value": "50000000UL",
+ "macro_name": "CY_CLK_SLOWCLK_FREQ_HZ"
+ }
+ }
+ },
+ "FUTURE_SEQUANA_M0_PSA": {
+ "inherits": ["SPE_Target", "FUTURE_SEQUANA_M0"],
+ "components_add": ["SPM_MAILBOX", "FLASHIAP"],
+ "extra_labels_add": ["PSA"],
+ "macros_add": [
+ "PSOC6_DYNSRM_DISABLE=1",
+ "MBEDTLS_PSA_CRYPTO_SPM",
+ "MBEDTLS_PSA_CRYPTO_C",
+ "MBEDTLS_ENTROPY_NV_SEED",
+ "MBEDTLS_PLATFORM_NV_SEED_READ_MACRO=mbed_default_seed_read",
+ "MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO=mbed_default_seed_write"
+ ],
+ "deliver_to_target": "FUTURE_SEQUANA_PSA",
+ "overrides": {
+ "secure-rom-start": "0x10000000",
+ "secure-rom-size": "0x80000",
+ "non-secure-rom-start": "0x10080000",
+ "non-secure-rom-size": "0x78000",
+ "secure-ram-start": "0x08000000",
+ "secure-ram-size": "0x10000",
+ "non-secure-ram-start": "0x08010000",
+ "non-secure-ram-size": "0x37700",
+ "shared-ram-start": "0x08047700",
+ "shared-ram-size": "0x100"
+ }
+ },
+ "FUTURE_SEQUANA_PSA": {
+ "inherits": ["NSPE_Target", "FUTURE_SEQUANA"],
+ "extra_labels_add": ["PSA"],
+ "extra_labels_remove": ["CORDIO"],
+ "components_add": ["SPM_MAILBOX"],
+ "macros_add": ["PSOC6_DYNSRM_DISABLE=1", "MBEDTLS_PSA_CRYPTO_C"],
+ "hex_filename": "psa_release_1.0.hex",
+ "overrides": {
+ "secure-rom-start": "0x10000000",
+ "secure-rom-size": "0x80000",
+ "non-secure-rom-start": "0x10080000",
+ "non-secure-rom-size": "0x78000",
+ "secure-ram-start": "0x08000000",
+ "secure-ram-size": "0x10000",
+ "non-secure-ram-start": "0x08010000",
+ "non-secure-ram-size": "0x37700",
+ "shared-ram-start": "0x08047700",
+ "shared-ram-size": "0x100"
+ }
+ },
+ "TMPM3HQ": {
+ "inherits": ["Target"],
+ "core": "Cortex-M3",
+ "is_disk_virtual": true,
+ "extra_labels": ["TOSHIBA"],
+ "macros": ["__TMPM3HQ__"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "device_has": [
+ "USTICKER",
+ "ANALOGIN",
+ "ANALOGOUT",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "I2C",
+ "I2CSLAVE",
+ "STDIO_MESSAGES",
+ "MPU"
+ ],
+ "device_name": "TMPM3HQFDFG",
+ "detect_code": ["7014"],
+ "release_versions": ["5"]
+ },
+ "RDA5981X": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "public": true,
+ "extra_labels": ["RDA", "UNO_91H", "FLASH_CMSIS_ALGO", "RDA_EMAC"],
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "macros": ["TWO_RAM_REGIONS", "CMSIS_NVIC_VIRTUAL", "CMSIS_NVIC_VIRTUAL_HEADER_FILE=\"RDA5981_nvic_virtual.h\""],
+ "device_has": [
+ "USTICKER",
+ "PORTIN",
+ "PORTOUT",
+ "PORTINOUT",
+ "INTERRUPTIN",
+ "EMAC",
+ "SERIAL",
+ "STDIO_MESSAGES",
+ "PWMOUT",
+ "SPI",
+ "SLEEP",
+ "ANALOGIN",
+ "FLASH",
+ "TRNG"
+ ],
+ "release_versions": ["2", "5"]
+ },
+ "UNO_91H": {
+ "inherits": ["RDA5981X"],
+ "detect_code": ["8001"],
+ "overrides": {
+ "network-default-interface-type" : "WIFI"
+ }
+ },
+ "GD32_Target": {
+ "inherits": ["Target"],
+ "public": false,
+ "extra_labels": ["GigaDevice"],
+ "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
+ "device_has": [
+ "USTICKER",
+ "ANALOGIN",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL"
+ ]
+ },
+ "GD32_F307VG": {
+ "inherits": ["GD32_Target"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4",
+ "extra_labels_add": ["GD32F30X", "GD32F307VG", "GD_EMAC"],
+ "device_has_add": [
+ "RTC",
+ "I2C",
+ "CAN",
+ "I2CSLAVE",
+ "ANALOGOUT",
+ "SPI",
+ "SPISLAVE",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "EMAC",
+ "FLASH",
+ "SLEEP",
+ "MPU"
+ ],
+ "detect_code": ["1701"],
+ "macros_add": ["GD32F30X_CL"],
+ "release_versions": ["5"],
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "TT_M3HQ": {
+ "inherits": ["Target"],
+ "core": "Cortex-M3",
+ "is_disk_virtual": true,
+ "extra_labels": ["TT"],
+ "macros": ["__TT_M3HQ__"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "device_has": [
+ "ANALOGIN",
+ "USTICKER",
+ "ANALOGOUT",
+ "INTERRUPTIN",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SLEEP",
+ "SPI",
+ "I2C",
+ "I2CSLAVE",
+ "STDIO_MESSAGES",
+ "MPU"
+ ],
+ "device_name": "TMPM3HQFDFG",
+ "detect_code": ["8012"],
+ "release_versions": ["5"]
+ },
+ "GD32_F450ZI": {
+ "inherits": ["GD32_Target"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4",
+ "extra_labels_add": ["GD32F4XX", "GD32F450ZI", "GD_EMAC"],
+ "device_has_add": [
+ "RTC",
+ "I2C",
+ "CAN",
+ "I2CSLAVE",
+ "ANALOGOUT",
+ "SPI",
+ "SPISLAVE",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "EMAC",
+ "FLASH",
+ "SLEEP",
+ "MPU",
+ "TRNG"
+ ],
+ "device_name": "GD32F450ZI",
+ "detect_code": ["1702"],
+ "macros_add": ["GD32F450"],
+ "release_versions": ["5"],
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "GD32_E103VB": {
+ "inherits": ["GD32_Target"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4",
+ "extra_labels_add": ["GD32E10X", "GD32E103VB"],
+ "device_has_add": [
+ "RTC",
+ "I2C",
+ "CAN",
+ "I2CSLAVE",
+ "ANALOGOUT",
+ "SPI",
+ "SPISLAVE",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "FLASH",
+ "SLEEP"
+ ],
+ "detect_code": ["1703"],
+ "macros_add": ["GD32E10X"],
+ "release_versions": ["5"]
+ }
+}
+