Vekatech / SDHI_driver_variant_II

SDHI_driver patch (mbedOS 5.11.5)

mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h@0:e1f465d87307, 2019-03-18 (annotated)

Committer:
tvendov
Date:
Mon Mar 18 16:54:40 2019 +0000
Revision:
0:e1f465d87307
Initial_II

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tvendov 0:e1f465d87307 1 /******************************************************************************
tvendov 0:e1f465d87307 2 * @file VK_RZ_A1H.h
tvendov 0:e1f465d87307 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
tvendov 0:e1f465d87307 4 * @version V1.00
tvendov 0:e1f465d87307 5 * @data 10 Mar 2017
tvendov 0:e1f465d87307 6 *
tvendov 0:e1f465d87307 7 * @note
tvendov 0:e1f465d87307 8 *
tvendov 0:e1f465d87307 9 ******************************************************************************/
tvendov 0:e1f465d87307 10 /*
tvendov 0:e1f465d87307 11 * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
tvendov 0:e1f465d87307 12 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
tvendov 0:e1f465d87307 13 *
tvendov 0:e1f465d87307 14 * SPDX-License-Identifier: Apache-2.0
tvendov 0:e1f465d87307 15 *
tvendov 0:e1f465d87307 16 * Licensed under the Apache License, Version 2.0 (the License); you may
tvendov 0:e1f465d87307 17 * not use this file except in compliance with the License.
tvendov 0:e1f465d87307 18 * You may obtain a copy of the License at
tvendov 0:e1f465d87307 19 *
tvendov 0:e1f465d87307 20 * www.apache.org/licenses/LICENSE-2.0
tvendov 0:e1f465d87307 21 *
tvendov 0:e1f465d87307 22 * Unless required by applicable law or agreed to in writing, software
tvendov 0:e1f465d87307 23 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
tvendov 0:e1f465d87307 24 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
tvendov 0:e1f465d87307 25 * See the License for the specific language governing permissions and
tvendov 0:e1f465d87307 26 * limitations under the License.
tvendov 0:e1f465d87307 27 */
tvendov 0:e1f465d87307 28
tvendov 0:e1f465d87307 29 #ifndef __VK_RZ_A1H_H__
tvendov 0:e1f465d87307 30 #define __VK_RZ_A1H_H__
tvendov 0:e1f465d87307 31
tvendov 0:e1f465d87307 32 #ifdef __cplusplus
tvendov 0:e1f465d87307 33 extern "C" {
tvendov 0:e1f465d87307 34 #endif
tvendov 0:e1f465d87307 35
tvendov 0:e1f465d87307 36 /* ------------------------- Interrupt Number Definition ------------------------ */
tvendov 0:e1f465d87307 37
tvendov 0:e1f465d87307 38 typedef enum IRQn
tvendov 0:e1f465d87307 39 {
tvendov 0:e1f465d87307 40 /****** SGI Interrupts Numbers ****************************************/
tvendov 0:e1f465d87307 41 SGI0_IRQn = 0,
tvendov 0:e1f465d87307 42 SGI1_IRQn = 1,
tvendov 0:e1f465d87307 43 SGI2_IRQn = 2,
tvendov 0:e1f465d87307 44 SGI3_IRQn = 3,
tvendov 0:e1f465d87307 45 SGI4_IRQn = 4,
tvendov 0:e1f465d87307 46 SGI5_IRQn = 5,
tvendov 0:e1f465d87307 47 SGI6_IRQn = 6,
tvendov 0:e1f465d87307 48 SGI7_IRQn = 7,
tvendov 0:e1f465d87307 49 SGI8_IRQn = 8,
tvendov 0:e1f465d87307 50 SGI9_IRQn = 9,
tvendov 0:e1f465d87307 51 SGI10_IRQn = 10,
tvendov 0:e1f465d87307 52 SGI11_IRQn = 11,
tvendov 0:e1f465d87307 53 SGI12_IRQn = 12,
tvendov 0:e1f465d87307 54 SGI13_IRQn = 13,
tvendov 0:e1f465d87307 55 SGI14_IRQn = 14,
tvendov 0:e1f465d87307 56 SGI15_IRQn = 15,
tvendov 0:e1f465d87307 57
tvendov 0:e1f465d87307 58 /****** Cortex-A9 Processor Exceptions Numbers ****************************************/
tvendov 0:e1f465d87307 59 /* 16 - 578 */
tvendov 0:e1f465d87307 60 PMUIRQ0_IRQn = 16,
tvendov 0:e1f465d87307 61 COMMRX0_IRQn = 17,
tvendov 0:e1f465d87307 62 COMMTX0_IRQn = 18,
tvendov 0:e1f465d87307 63 CTIIRQ0_IRQn = 19,
tvendov 0:e1f465d87307 64
tvendov 0:e1f465d87307 65 IRQ0_IRQn = 32,
tvendov 0:e1f465d87307 66 IRQ1_IRQn = 33,
tvendov 0:e1f465d87307 67 IRQ2_IRQn = 34,
tvendov 0:e1f465d87307 68 IRQ3_IRQn = 35,
tvendov 0:e1f465d87307 69 IRQ4_IRQn = 36,
tvendov 0:e1f465d87307 70 IRQ5_IRQn = 37,
tvendov 0:e1f465d87307 71 IRQ6_IRQn = 38,
tvendov 0:e1f465d87307 72 IRQ7_IRQn = 39,
tvendov 0:e1f465d87307 73
tvendov 0:e1f465d87307 74 PL310ERR_IRQn = 40,
tvendov 0:e1f465d87307 75
tvendov 0:e1f465d87307 76 DMAINT0_IRQn = 41, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 77 DMAINT1_IRQn = 42, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 78 DMAINT2_IRQn = 43, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 79 DMAINT3_IRQn = 44, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 80 DMAINT4_IRQn = 45, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 81 DMAINT5_IRQn = 46, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 82 DMAINT6_IRQn = 47, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 83 DMAINT7_IRQn = 48, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 84 DMAINT8_IRQn = 49, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 85 DMAINT9_IRQn = 50, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 86 DMAINT10_IRQn = 51, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 87 DMAINT11_IRQn = 52, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 88 DMAINT12_IRQn = 53, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 89 DMAINT13_IRQn = 54, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 90 DMAINT14_IRQn = 55, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 91 DMAINT15_IRQn = 56, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 92 DMAERR_IRQn = 57, /*!< DMAC Interrupt */
tvendov 0:e1f465d87307 93
tvendov 0:e1f465d87307 94 /* 58-72 Reserved */
tvendov 0:e1f465d87307 95
tvendov 0:e1f465d87307 96 USBI0_IRQn = 73,
tvendov 0:e1f465d87307 97 USBI1_IRQn = 74,
tvendov 0:e1f465d87307 98
tvendov 0:e1f465d87307 99 S0_VI_VSYNC0_IRQn = 75,
tvendov 0:e1f465d87307 100 S0_LO_VSYNC0_IRQn = 76,
tvendov 0:e1f465d87307 101 S0_VSYNCERR0_IRQn = 77,
tvendov 0:e1f465d87307 102 GR3_VLINE0_IRQn = 78,
tvendov 0:e1f465d87307 103 S0_VFIELD0_IRQn = 79,
tvendov 0:e1f465d87307 104 IV1_VBUFERR0_IRQn = 80,
tvendov 0:e1f465d87307 105 IV3_VBUFERR0_IRQn = 81,
tvendov 0:e1f465d87307 106 IV5_VBUFERR0_IRQn = 82,
tvendov 0:e1f465d87307 107 IV6_VBUFERR0_IRQn = 83,
tvendov 0:e1f465d87307 108 S0_WLINE0_IRQn = 84,
tvendov 0:e1f465d87307 109 S1_VI_VSYNC0_IRQn = 85,
tvendov 0:e1f465d87307 110 S1_LO_VSYNC0_IRQn = 86,
tvendov 0:e1f465d87307 111 S1_VSYNCERR0_IRQn = 87,
tvendov 0:e1f465d87307 112 S1_VFIELD0_IRQn = 88,
tvendov 0:e1f465d87307 113 IV2_VBUFERR0_IRQn = 89,
tvendov 0:e1f465d87307 114 IV4_VBUFERR0_IRQn = 90,
tvendov 0:e1f465d87307 115 S1_WLINE0_IRQn = 91,
tvendov 0:e1f465d87307 116 OIR_VI_VSYNC0_IRQn = 92,
tvendov 0:e1f465d87307 117 OIR_LO_VSYNC0_IRQn = 93,
tvendov 0:e1f465d87307 118 OIR_VSYNCERR0_IRQn = 94,
tvendov 0:e1f465d87307 119 OIR_VFIELD0_IRQn = 95,
tvendov 0:e1f465d87307 120 IV7_VBUFERR0_IRQn = 96,
tvendov 0:e1f465d87307 121 IV8_VBUFERR0_IRQn = 97,
tvendov 0:e1f465d87307 122 /* 98 Reserved */
tvendov 0:e1f465d87307 123 S0_VI_VSYNC1_IRQn = 99,
tvendov 0:e1f465d87307 124 S0_LO_VSYNC1_IRQn = 100,
tvendov 0:e1f465d87307 125 S0_VSYNCERR1_IRQn = 101,
tvendov 0:e1f465d87307 126 GR3_VLINE1_IRQn = 102,
tvendov 0:e1f465d87307 127 S0_VFIELD1_IRQn = 103,
tvendov 0:e1f465d87307 128 IV1_VBUFERR1_IRQn = 104,
tvendov 0:e1f465d87307 129 IV3_VBUFERR1_IRQn = 105,
tvendov 0:e1f465d87307 130 IV5_VBUFERR1_IRQn = 106,
tvendov 0:e1f465d87307 131 IV6_VBUFERR1_IRQn = 107,
tvendov 0:e1f465d87307 132 S0_WLINE1_IRQn = 108,
tvendov 0:e1f465d87307 133 S1_VI_VSYNC1_IRQn = 109,
tvendov 0:e1f465d87307 134 S1_LO_VSYNC1_IRQn = 110,
tvendov 0:e1f465d87307 135 S1_VSYNCERR1_IRQn = 111,
tvendov 0:e1f465d87307 136 S1_VFIELD1_IRQn = 112,
tvendov 0:e1f465d87307 137 IV2_VBUFERR1_IRQn = 113,
tvendov 0:e1f465d87307 138 IV4_VBUFERR1_IRQn = 114,
tvendov 0:e1f465d87307 139 S1_WLINE1_IRQn = 115,
tvendov 0:e1f465d87307 140 OIR_VI_VSYNC1_IRQn = 116,
tvendov 0:e1f465d87307 141 OIR_LO_VSYNC1_IRQn = 117,
tvendov 0:e1f465d87307 142 OIR_VSYNCERR1_IRQn = 118,
tvendov 0:e1f465d87307 143 OIR_VFIELD1_IRQn = 119,
tvendov 0:e1f465d87307 144 IV7_VBUFERR1_IRQn = 120,
tvendov 0:e1f465d87307 145 IV8_VBUFERR1_IRQn = 121,
tvendov 0:e1f465d87307 146 /* Reserved = 122 */
tvendov 0:e1f465d87307 147
tvendov 0:e1f465d87307 148 IMRDI_IRQn = 123,
tvendov 0:e1f465d87307 149 IMR2I0_IRQn = 124,
tvendov 0:e1f465d87307 150 IMR2I1_IRQn = 125,
tvendov 0:e1f465d87307 151
tvendov 0:e1f465d87307 152 JEDI_IRQn = 126,
tvendov 0:e1f465d87307 153 JDTI_IRQn = 127,
tvendov 0:e1f465d87307 154
tvendov 0:e1f465d87307 155 CMP0_IRQn = 128,
tvendov 0:e1f465d87307 156 CMP1_IRQn = 129,
tvendov 0:e1f465d87307 157
tvendov 0:e1f465d87307 158 INT0_IRQn = 130,
tvendov 0:e1f465d87307 159 INT1_IRQn = 131,
tvendov 0:e1f465d87307 160 INT2_IRQn = 132,
tvendov 0:e1f465d87307 161 INT3_IRQn = 133,
tvendov 0:e1f465d87307 162
tvendov 0:e1f465d87307 163 OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */
tvendov 0:e1f465d87307 164 OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */
tvendov 0:e1f465d87307 165
tvendov 0:e1f465d87307 166 CMI_IRQn = 136,
tvendov 0:e1f465d87307 167 WTOUT_IRQn = 137,
tvendov 0:e1f465d87307 168
tvendov 0:e1f465d87307 169 ITI_IRQn = 138,
tvendov 0:e1f465d87307 170
tvendov 0:e1f465d87307 171 TGI0A_IRQn = 139,
tvendov 0:e1f465d87307 172 TGI0B_IRQn = 140,
tvendov 0:e1f465d87307 173 TGI0C_IRQn = 141,
tvendov 0:e1f465d87307 174 TGI0D_IRQn = 142,
tvendov 0:e1f465d87307 175 TGI0V_IRQn = 143,
tvendov 0:e1f465d87307 176 TGI0E_IRQn = 144,
tvendov 0:e1f465d87307 177 TGI0F_IRQn = 145,
tvendov 0:e1f465d87307 178 TGI1A_IRQn = 146,
tvendov 0:e1f465d87307 179 TGI1B_IRQn = 147,
tvendov 0:e1f465d87307 180 TGI1V_IRQn = 148,
tvendov 0:e1f465d87307 181 TGI1U_IRQn = 149,
tvendov 0:e1f465d87307 182 TGI2A_IRQn = 150,
tvendov 0:e1f465d87307 183 TGI2B_IRQn = 151,
tvendov 0:e1f465d87307 184 TGI2V_IRQn = 152,
tvendov 0:e1f465d87307 185 TGI2U_IRQn = 153,
tvendov 0:e1f465d87307 186 TGI3A_IRQn = 154,
tvendov 0:e1f465d87307 187 TGI3B_IRQn = 155,
tvendov 0:e1f465d87307 188 TGI3C_IRQn = 156,
tvendov 0:e1f465d87307 189 TGI3D_IRQn = 157,
tvendov 0:e1f465d87307 190 TGI3V_IRQn = 158,
tvendov 0:e1f465d87307 191 TGI4A_IRQn = 159,
tvendov 0:e1f465d87307 192 TGI4B_IRQn = 160,
tvendov 0:e1f465d87307 193 TGI4C_IRQn = 161,
tvendov 0:e1f465d87307 194 TGI4D_IRQn = 162,
tvendov 0:e1f465d87307 195 TGI4V_IRQn = 163,
tvendov 0:e1f465d87307 196
tvendov 0:e1f465d87307 197 CMI1_IRQn = 164,
tvendov 0:e1f465d87307 198 CMI2_IRQn = 165,
tvendov 0:e1f465d87307 199
tvendov 0:e1f465d87307 200 SGDEI0_IRQn = 166,
tvendov 0:e1f465d87307 201 SGDEI1_IRQn = 167,
tvendov 0:e1f465d87307 202 SGDEI2_IRQn = 168,
tvendov 0:e1f465d87307 203 SGDEI3_IRQn = 169,
tvendov 0:e1f465d87307 204
tvendov 0:e1f465d87307 205 ADI_IRQn = 170,
tvendov 0:e1f465d87307 206 LMTI_IRQn = 171,
tvendov 0:e1f465d87307 207
tvendov 0:e1f465d87307 208 SSII0_IRQn = 172, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 209 SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 210 SSITXI0_IRQn = 174, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 211 SSII1_IRQn = 175, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 212 SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 213 SSITXI1_IRQn = 177, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 214 SSII2_IRQn = 178, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 215 SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 216 SSII3_IRQn = 180, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 217 SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 218 SSITXI3_IRQn = 182, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 219 SSII4_IRQn = 183, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 220 SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 221 SSII5_IRQn = 185, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 222 SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 223 SSITXI5_IRQn = 187, /*!< SSIF Interrupt */
tvendov 0:e1f465d87307 224
tvendov 0:e1f465d87307 225 SPDIFI_IRQn = 188,
tvendov 0:e1f465d87307 226
tvendov 0:e1f465d87307 227 INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 228 INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 229 INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 230 INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 231 INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 232 INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 233 INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 234 INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 235 INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 236 INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 237 INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 238 INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 239 INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 240 INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 241 INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 242 INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 243 INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 244 INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 245 INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 246 INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 247 INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 248 INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 249 INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 250 INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 251 INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 252 INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 253 INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 254 INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 255 INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 256 INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 257 INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 258 INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */
tvendov 0:e1f465d87307 259
tvendov 0:e1f465d87307 260 SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 261 SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 262 SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 263 SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 264 SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 265 SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 266 SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 267 SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 268 SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 269 SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 270 SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 271 SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 272 SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 273 SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 274 SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 275 SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 276 SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 277 SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 278 SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 279 SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 280 SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 281 SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 282 SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 283 SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 284 SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 285 SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 286 SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 287 SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 288 SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 289 SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 290 SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 291 SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */
tvendov 0:e1f465d87307 292
tvendov 0:e1f465d87307 293 INTRCANGERR_IRQn = 253,
tvendov 0:e1f465d87307 294 INTRCANGRECC_IRQn = 254,
tvendov 0:e1f465d87307 295 INTRCAN0REC_IRQn = 255,
tvendov 0:e1f465d87307 296 INTRCAN0ERR_IRQn = 256,
tvendov 0:e1f465d87307 297 INTRCAN0TRX_IRQn = 257,
tvendov 0:e1f465d87307 298 INTRCAN1REC_IRQn = 258,
tvendov 0:e1f465d87307 299 INTRCAN1ERR_IRQn = 259,
tvendov 0:e1f465d87307 300 INTRCAN1TRX_IRQn = 260,
tvendov 0:e1f465d87307 301 INTRCAN2REC_IRQn = 261,
tvendov 0:e1f465d87307 302 INTRCAN2ERR_IRQn = 262,
tvendov 0:e1f465d87307 303 INTRCAN2TRX_IRQn = 263,
tvendov 0:e1f465d87307 304 INTRCAN3REC_IRQn = 264,
tvendov 0:e1f465d87307 305 INTRCAN3ERR_IRQn = 265,
tvendov 0:e1f465d87307 306 INTRCAN3TRX_IRQn = 266,
tvendov 0:e1f465d87307 307 INTRCAN4REC_IRQn = 267,
tvendov 0:e1f465d87307 308 INTRCAN4ERR_IRQn = 268,
tvendov 0:e1f465d87307 309 INTRCAN4TRX_IRQn = 269,
tvendov 0:e1f465d87307 310
tvendov 0:e1f465d87307 311 RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 312 RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 313 RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 314 RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 315 RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 316 RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 317 RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 318 RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 319 RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 320 RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 321 RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 322 RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 323 RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 324 RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 325 RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */
tvendov 0:e1f465d87307 326
tvendov 0:e1f465d87307 327 IEBBTD_IRQn = 285,
tvendov 0:e1f465d87307 328 IEBBTERR_IRQn = 286,
tvendov 0:e1f465d87307 329 IEBBTSTA_IRQn = 287,
tvendov 0:e1f465d87307 330 IEBBTV_IRQn = 288,
tvendov 0:e1f465d87307 331
tvendov 0:e1f465d87307 332 ISY_IRQn = 289,
tvendov 0:e1f465d87307 333 IERR_IRQn = 290,
tvendov 0:e1f465d87307 334 ITARG_IRQn = 291,
tvendov 0:e1f465d87307 335 ISEC_IRQn = 292,
tvendov 0:e1f465d87307 336 IBUF_IRQn = 293,
tvendov 0:e1f465d87307 337 IREADY_IRQn = 294,
tvendov 0:e1f465d87307 338
tvendov 0:e1f465d87307 339 STERB_IRQn = 295,
tvendov 0:e1f465d87307 340 FLTENDI_IRQn = 296,
tvendov 0:e1f465d87307 341 FLTREQ0I_IRQn = 297,
tvendov 0:e1f465d87307 342 FLTREQ1I_IRQn = 298,
tvendov 0:e1f465d87307 343
tvendov 0:e1f465d87307 344 MMC0_IRQn = 299,
tvendov 0:e1f465d87307 345 MMC1_IRQn = 300,
tvendov 0:e1f465d87307 346 MMC2_IRQn = 301,
tvendov 0:e1f465d87307 347
tvendov 0:e1f465d87307 348 SDHI0_3_IRQn = 302,
tvendov 0:e1f465d87307 349 SDHI0_0_IRQn = 303,
tvendov 0:e1f465d87307 350 SDHI0_1_IRQn = 304,
tvendov 0:e1f465d87307 351 SDHI1_3_IRQn = 305,
tvendov 0:e1f465d87307 352 SDHI1_0_IRQn = 306,
tvendov 0:e1f465d87307 353 SDHI1_1_IRQn = 307,
tvendov 0:e1f465d87307 354
tvendov 0:e1f465d87307 355 ARM_IRQn = 308,
tvendov 0:e1f465d87307 356 PRD_IRQn = 309,
tvendov 0:e1f465d87307 357 CUP_IRQn = 310,
tvendov 0:e1f465d87307 358
tvendov 0:e1f465d87307 359 SCUAI0_IRQn = 311,
tvendov 0:e1f465d87307 360 SCUAI1_IRQn = 312,
tvendov 0:e1f465d87307 361 SCUFDI0_IRQn = 313,
tvendov 0:e1f465d87307 362 SCUFDI1_IRQn = 314,
tvendov 0:e1f465d87307 363 SCUFDI2_IRQn = 315,
tvendov 0:e1f465d87307 364 SCUFDI3_IRQn = 316,
tvendov 0:e1f465d87307 365 SCUFUI0_IRQn = 317,
tvendov 0:e1f465d87307 366 SCUFUI1_IRQn = 318,
tvendov 0:e1f465d87307 367 SCUFUI2_IRQn = 319,
tvendov 0:e1f465d87307 368 SCUFUI3_IRQn = 320,
tvendov 0:e1f465d87307 369 SCUDVI0_IRQn = 321,
tvendov 0:e1f465d87307 370 SCUDVI1_IRQn = 322,
tvendov 0:e1f465d87307 371 SCUDVI2_IRQn = 323,
tvendov 0:e1f465d87307 372 SCUDVI3_IRQn = 324,
tvendov 0:e1f465d87307 373
tvendov 0:e1f465d87307 374 MLB_CINT_IRQn = 325,
tvendov 0:e1f465d87307 375 MLB_SINT_IRQn = 326,
tvendov 0:e1f465d87307 376
tvendov 0:e1f465d87307 377 DRC10_IRQn = 327,
tvendov 0:e1f465d87307 378 DRC11_IRQn = 328,
tvendov 0:e1f465d87307 379
tvendov 0:e1f465d87307 380 /* 329-330 Reserved */
tvendov 0:e1f465d87307 381
tvendov 0:e1f465d87307 382 LINI0_INT_T_IRQn = 331,
tvendov 0:e1f465d87307 383 LINI0_INT_R_IRQn = 332,
tvendov 0:e1f465d87307 384 LINI0_INT_S_IRQn = 333,
tvendov 0:e1f465d87307 385 LINI0_INT_M_IRQn = 334,
tvendov 0:e1f465d87307 386 LINI1_INT_T_IRQn = 335,
tvendov 0:e1f465d87307 387 LINI1_INT_R_IRQn = 336,
tvendov 0:e1f465d87307 388 LINI1_INT_S_IRQn = 337,
tvendov 0:e1f465d87307 389 LINI1_INT_M_IRQn = 338,
tvendov 0:e1f465d87307 390
tvendov 0:e1f465d87307 391 /* 339-346 Reserved */
tvendov 0:e1f465d87307 392
tvendov 0:e1f465d87307 393 SCIERI0_IRQn = 347,
tvendov 0:e1f465d87307 394 SCIRXI0_IRQn = 348,
tvendov 0:e1f465d87307 395 SCITXI0_IRQn = 349,
tvendov 0:e1f465d87307 396 SCITEI0_IRQn = 350,
tvendov 0:e1f465d87307 397 SCIERI1_IRQn = 351,
tvendov 0:e1f465d87307 398 SCIRXI1_IRQn = 352,
tvendov 0:e1f465d87307 399 SCITXI1_IRQn = 353,
tvendov 0:e1f465d87307 400 SCITEI1_IRQn = 354,
tvendov 0:e1f465d87307 401
tvendov 0:e1f465d87307 402 AVBI_DATA = 355,
tvendov 0:e1f465d87307 403 AVBI_ERROR = 356,
tvendov 0:e1f465d87307 404 AVBI_MANAGE = 357,
tvendov 0:e1f465d87307 405 AVBI_MAC = 358,
tvendov 0:e1f465d87307 406
tvendov 0:e1f465d87307 407 ETHERI_IRQn = 359,
tvendov 0:e1f465d87307 408
tvendov 0:e1f465d87307 409 /* 360-363 Reserved */
tvendov 0:e1f465d87307 410
tvendov 0:e1f465d87307 411 CEUI_IRQn = 364,
tvendov 0:e1f465d87307 412
tvendov 0:e1f465d87307 413 /* 365-380 Reserved */
tvendov 0:e1f465d87307 414
tvendov 0:e1f465d87307 415 H2XMLB_ERRINT_IRQn = 381,
tvendov 0:e1f465d87307 416 H2XIC1_ERRINT_IRQn = 382,
tvendov 0:e1f465d87307 417 X2HPERI1_ERRINT_IRQn = 383,
tvendov 0:e1f465d87307 418 X2HPERR2_ERRINT_IRQn = 384,
tvendov 0:e1f465d87307 419 X2HPERR34_ERRINT_IRQn= 385,
tvendov 0:e1f465d87307 420 X2HPERR5_ERRINT_IRQn = 386,
tvendov 0:e1f465d87307 421 X2HPERR67_ERRINT_IRQn= 387,
tvendov 0:e1f465d87307 422 X2HDBGR_ERRINT_IRQn = 388,
tvendov 0:e1f465d87307 423 X2HBSC_ERRINT_IRQn = 389,
tvendov 0:e1f465d87307 424 X2HSPI1_ERRINT_IRQn = 390,
tvendov 0:e1f465d87307 425 X2HSPI2_ERRINT_IRQn = 391,
tvendov 0:e1f465d87307 426 PRRI_IRQn = 392,
tvendov 0:e1f465d87307 427
tvendov 0:e1f465d87307 428 IFEI0_IRQn = 393,
tvendov 0:e1f465d87307 429 OFFI0_IRQn = 394,
tvendov 0:e1f465d87307 430 PFVEI0_IRQn = 395,
tvendov 0:e1f465d87307 431 IFEI1_IRQn = 396,
tvendov 0:e1f465d87307 432 OFFI1_IRQn = 397,
tvendov 0:e1f465d87307 433 PFVEI1_IRQn = 398,
tvendov 0:e1f465d87307 434
tvendov 0:e1f465d87307 435 /* 399-415 Reserved */
tvendov 0:e1f465d87307 436
tvendov 0:e1f465d87307 437 TINT0_IRQn = 416,
tvendov 0:e1f465d87307 438 TINT1_IRQn = 417,
tvendov 0:e1f465d87307 439 TINT2_IRQn = 418,
tvendov 0:e1f465d87307 440 TINT3_IRQn = 419,
tvendov 0:e1f465d87307 441 TINT4_IRQn = 420,
tvendov 0:e1f465d87307 442 TINT5_IRQn = 421,
tvendov 0:e1f465d87307 443 TINT6_IRQn = 422,
tvendov 0:e1f465d87307 444 TINT7_IRQn = 423,
tvendov 0:e1f465d87307 445 TINT8_IRQn = 424,
tvendov 0:e1f465d87307 446 TINT9_IRQn = 425,
tvendov 0:e1f465d87307 447 TINT10_IRQn = 426,
tvendov 0:e1f465d87307 448 TINT11_IRQn = 427,
tvendov 0:e1f465d87307 449 TINT12_IRQn = 428,
tvendov 0:e1f465d87307 450 TINT13_IRQn = 429,
tvendov 0:e1f465d87307 451 TINT14_IRQn = 430,
tvendov 0:e1f465d87307 452 TINT15_IRQn = 431,
tvendov 0:e1f465d87307 453 TINT16_IRQn = 432,
tvendov 0:e1f465d87307 454 TINT17_IRQn = 433,
tvendov 0:e1f465d87307 455 TINT18_IRQn = 434,
tvendov 0:e1f465d87307 456 TINT19_IRQn = 435,
tvendov 0:e1f465d87307 457 TINT20_IRQn = 436,
tvendov 0:e1f465d87307 458 TINT21_IRQn = 437,
tvendov 0:e1f465d87307 459 TINT22_IRQn = 438,
tvendov 0:e1f465d87307 460 TINT23_IRQn = 439,
tvendov 0:e1f465d87307 461 TINT24_IRQn = 440,
tvendov 0:e1f465d87307 462 TINT25_IRQn = 441,
tvendov 0:e1f465d87307 463 TINT26_IRQn = 442,
tvendov 0:e1f465d87307 464 TINT27_IRQn = 443,
tvendov 0:e1f465d87307 465 TINT28_IRQn = 444,
tvendov 0:e1f465d87307 466 TINT29_IRQn = 445,
tvendov 0:e1f465d87307 467 TINT30_IRQn = 446,
tvendov 0:e1f465d87307 468 TINT31_IRQn = 447,
tvendov 0:e1f465d87307 469 TINT32_IRQn = 448,
tvendov 0:e1f465d87307 470 TINT33_IRQn = 449,
tvendov 0:e1f465d87307 471 TINT34_IRQn = 450,
tvendov 0:e1f465d87307 472 TINT35_IRQn = 451,
tvendov 0:e1f465d87307 473 TINT36_IRQn = 452,
tvendov 0:e1f465d87307 474 TINT37_IRQn = 453,
tvendov 0:e1f465d87307 475 TINT38_IRQn = 454,
tvendov 0:e1f465d87307 476 TINT39_IRQn = 455,
tvendov 0:e1f465d87307 477 TINT40_IRQn = 456,
tvendov 0:e1f465d87307 478 TINT41_IRQn = 457,
tvendov 0:e1f465d87307 479 TINT42_IRQn = 458,
tvendov 0:e1f465d87307 480 TINT43_IRQn = 459,
tvendov 0:e1f465d87307 481 TINT44_IRQn = 460,
tvendov 0:e1f465d87307 482 TINT45_IRQn = 461,
tvendov 0:e1f465d87307 483 TINT46_IRQn = 462,
tvendov 0:e1f465d87307 484 TINT47_IRQn = 463,
tvendov 0:e1f465d87307 485 TINT48_IRQn = 464,
tvendov 0:e1f465d87307 486 TINT49_IRQn = 465,
tvendov 0:e1f465d87307 487 TINT50_IRQn = 466,
tvendov 0:e1f465d87307 488 TINT51_IRQn = 467,
tvendov 0:e1f465d87307 489 TINT52_IRQn = 468,
tvendov 0:e1f465d87307 490 TINT53_IRQn = 469,
tvendov 0:e1f465d87307 491 TINT54_IRQn = 470,
tvendov 0:e1f465d87307 492 TINT55_IRQn = 471,
tvendov 0:e1f465d87307 493 TINT56_IRQn = 472,
tvendov 0:e1f465d87307 494 TINT57_IRQn = 473,
tvendov 0:e1f465d87307 495 TINT58_IRQn = 474,
tvendov 0:e1f465d87307 496 TINT59_IRQn = 475,
tvendov 0:e1f465d87307 497 TINT60_IRQn = 476,
tvendov 0:e1f465d87307 498 TINT61_IRQn = 477,
tvendov 0:e1f465d87307 499 TINT62_IRQn = 478,
tvendov 0:e1f465d87307 500 TINT63_IRQn = 479,
tvendov 0:e1f465d87307 501 TINT64_IRQn = 480,
tvendov 0:e1f465d87307 502 TINT65_IRQn = 481,
tvendov 0:e1f465d87307 503 TINT66_IRQn = 482,
tvendov 0:e1f465d87307 504 TINT67_IRQn = 483,
tvendov 0:e1f465d87307 505 TINT68_IRQn = 484,
tvendov 0:e1f465d87307 506 TINT69_IRQn = 485,
tvendov 0:e1f465d87307 507 TINT70_IRQn = 486,
tvendov 0:e1f465d87307 508 TINT71_IRQn = 487,
tvendov 0:e1f465d87307 509 TINT72_IRQn = 488,
tvendov 0:e1f465d87307 510 TINT73_IRQn = 489,
tvendov 0:e1f465d87307 511 TINT74_IRQn = 490,
tvendov 0:e1f465d87307 512 TINT75_IRQn = 491,
tvendov 0:e1f465d87307 513 TINT76_IRQn = 492,
tvendov 0:e1f465d87307 514 TINT77_IRQn = 493,
tvendov 0:e1f465d87307 515 TINT78_IRQn = 494,
tvendov 0:e1f465d87307 516 TINT79_IRQn = 495,
tvendov 0:e1f465d87307 517 TINT80_IRQn = 496,
tvendov 0:e1f465d87307 518 TINT81_IRQn = 497,
tvendov 0:e1f465d87307 519 TINT82_IRQn = 498,
tvendov 0:e1f465d87307 520 TINT83_IRQn = 499,
tvendov 0:e1f465d87307 521 TINT84_IRQn = 500,
tvendov 0:e1f465d87307 522 TINT85_IRQn = 501,
tvendov 0:e1f465d87307 523 TINT86_IRQn = 502,
tvendov 0:e1f465d87307 524 TINT87_IRQn = 503,
tvendov 0:e1f465d87307 525 TINT88_IRQn = 504,
tvendov 0:e1f465d87307 526 TINT89_IRQn = 505,
tvendov 0:e1f465d87307 527 TINT90_IRQn = 506,
tvendov 0:e1f465d87307 528 TINT91_IRQn = 507,
tvendov 0:e1f465d87307 529 TINT92_IRQn = 508,
tvendov 0:e1f465d87307 530 TINT93_IRQn = 509,
tvendov 0:e1f465d87307 531 TINT94_IRQn = 510,
tvendov 0:e1f465d87307 532 TINT95_IRQn = 511,
tvendov 0:e1f465d87307 533 TINT96_IRQn = 512,
tvendov 0:e1f465d87307 534 TINT97_IRQn = 513,
tvendov 0:e1f465d87307 535 TINT98_IRQn = 514,
tvendov 0:e1f465d87307 536 TINT99_IRQn = 515,
tvendov 0:e1f465d87307 537 TINT100_IRQn = 516,
tvendov 0:e1f465d87307 538 TINT101_IRQn = 517,
tvendov 0:e1f465d87307 539 TINT102_IRQn = 518,
tvendov 0:e1f465d87307 540 TINT103_IRQn = 519,
tvendov 0:e1f465d87307 541 TINT104_IRQn = 520,
tvendov 0:e1f465d87307 542 TINT105_IRQn = 521,
tvendov 0:e1f465d87307 543 TINT106_IRQn = 522,
tvendov 0:e1f465d87307 544 TINT107_IRQn = 523,
tvendov 0:e1f465d87307 545 TINT108_IRQn = 524,
tvendov 0:e1f465d87307 546 TINT109_IRQn = 525,
tvendov 0:e1f465d87307 547 TINT110_IRQn = 526,
tvendov 0:e1f465d87307 548 TINT111_IRQn = 527,
tvendov 0:e1f465d87307 549 TINT112_IRQn = 528,
tvendov 0:e1f465d87307 550 TINT113_IRQn = 529,
tvendov 0:e1f465d87307 551 TINT114_IRQn = 530,
tvendov 0:e1f465d87307 552 TINT115_IRQn = 531,
tvendov 0:e1f465d87307 553 TINT116_IRQn = 532,
tvendov 0:e1f465d87307 554 TINT117_IRQn = 533,
tvendov 0:e1f465d87307 555 TINT118_IRQn = 534,
tvendov 0:e1f465d87307 556 TINT119_IRQn = 535,
tvendov 0:e1f465d87307 557 TINT120_IRQn = 536,
tvendov 0:e1f465d87307 558 TINT121_IRQn = 537,
tvendov 0:e1f465d87307 559 TINT122_IRQn = 538,
tvendov 0:e1f465d87307 560 TINT123_IRQn = 539,
tvendov 0:e1f465d87307 561 TINT124_IRQn = 540,
tvendov 0:e1f465d87307 562 TINT125_IRQn = 541,
tvendov 0:e1f465d87307 563 TINT126_IRQn = 542,
tvendov 0:e1f465d87307 564 TINT127_IRQn = 543,
tvendov 0:e1f465d87307 565 TINT128_IRQn = 544,
tvendov 0:e1f465d87307 566 TINT129_IRQn = 545,
tvendov 0:e1f465d87307 567 TINT130_IRQn = 546,
tvendov 0:e1f465d87307 568 TINT131_IRQn = 547,
tvendov 0:e1f465d87307 569 TINT132_IRQn = 548,
tvendov 0:e1f465d87307 570 TINT133_IRQn = 549,
tvendov 0:e1f465d87307 571 TINT134_IRQn = 550,
tvendov 0:e1f465d87307 572 TINT135_IRQn = 551,
tvendov 0:e1f465d87307 573 TINT136_IRQn = 552,
tvendov 0:e1f465d87307 574 TINT137_IRQn = 553,
tvendov 0:e1f465d87307 575 TINT138_IRQn = 554,
tvendov 0:e1f465d87307 576 TINT139_IRQn = 555,
tvendov 0:e1f465d87307 577 TINT140_IRQn = 556,
tvendov 0:e1f465d87307 578 TINT141_IRQn = 557,
tvendov 0:e1f465d87307 579 TINT142_IRQn = 558,
tvendov 0:e1f465d87307 580 TINT143_IRQn = 559,
tvendov 0:e1f465d87307 581 TINT144_IRQn = 560,
tvendov 0:e1f465d87307 582 TINT145_IRQn = 561,
tvendov 0:e1f465d87307 583 TINT146_IRQn = 562,
tvendov 0:e1f465d87307 584 TINT147_IRQn = 563,
tvendov 0:e1f465d87307 585 TINT148_IRQn = 564,
tvendov 0:e1f465d87307 586 TINT149_IRQn = 565,
tvendov 0:e1f465d87307 587 TINT150_IRQn = 566,
tvendov 0:e1f465d87307 588 TINT151_IRQn = 567,
tvendov 0:e1f465d87307 589 TINT152_IRQn = 568,
tvendov 0:e1f465d87307 590 TINT153_IRQn = 569,
tvendov 0:e1f465d87307 591 TINT154_IRQn = 570,
tvendov 0:e1f465d87307 592 TINT155_IRQn = 571,
tvendov 0:e1f465d87307 593 TINT156_IRQn = 572,
tvendov 0:e1f465d87307 594 TINT157_IRQn = 573,
tvendov 0:e1f465d87307 595 TINT158_IRQn = 574,
tvendov 0:e1f465d87307 596 TINT159_IRQn = 575,
tvendov 0:e1f465d87307 597 TINT160_IRQn = 576,
tvendov 0:e1f465d87307 598 TINT161_IRQn = 577,
tvendov 0:e1f465d87307 599 TINT162_IRQn = 578,
tvendov 0:e1f465d87307 600 TINT163_IRQn = 579,
tvendov 0:e1f465d87307 601 TINT164_IRQn = 580,
tvendov 0:e1f465d87307 602 TINT165_IRQn = 581,
tvendov 0:e1f465d87307 603 TINT166_IRQn = 582,
tvendov 0:e1f465d87307 604 TINT167_IRQn = 583,
tvendov 0:e1f465d87307 605 TINT168_IRQn = 584,
tvendov 0:e1f465d87307 606 TINT169_IRQn = 585,
tvendov 0:e1f465d87307 607 TINT170_IRQn = 586
tvendov 0:e1f465d87307 608
tvendov 0:e1f465d87307 609 } IRQn_Type;
tvendov 0:e1f465d87307 610
tvendov 0:e1f465d87307 611 #define RZ_A1_IRQ_MAX TINT170_IRQn
tvendov 0:e1f465d87307 612
tvendov 0:e1f465d87307 613 /******************************************************************************/
tvendov 0:e1f465d87307 614 /* Peripheral memory map */
tvendov 0:e1f465d87307 615 /******************************************************************************/
tvendov 0:e1f465d87307 616
tvendov 0:e1f465d87307 617 #define RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
tvendov 0:e1f465d87307 618 #define RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */
tvendov 0:e1f465d87307 619 #define RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */
tvendov 0:e1f465d87307 620 #define RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */
tvendov 0:e1f465d87307 621 #define RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */
tvendov 0:e1f465d87307 622 #define RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */
tvendov 0:e1f465d87307 623 #define RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */
tvendov 0:e1f465d87307 624 #define RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */
tvendov 0:e1f465d87307 625 #define RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */
tvendov 0:e1f465d87307 626 #define RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
tvendov 0:e1f465d87307 627 #define RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
tvendov 0:e1f465d87307 628 #define RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
tvendov 0:e1f465d87307 629 #define RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
tvendov 0:e1f465d87307 630 #define RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */
tvendov 0:e1f465d87307 631 #define RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */
tvendov 0:e1f465d87307 632 #define RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */
tvendov 0:e1f465d87307 633 #define RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */
tvendov 0:e1f465d87307 634 #define RZ_A1_PRIVATE_TIMER (0x00000600UL + 0x82000000UL) /*!< (PTIM ) Base Address */
tvendov 0:e1f465d87307 635 #define GIC_DISTRIBUTOR_BASE RZ_A1_GIC_DISTRIBUTOR_BASE
tvendov 0:e1f465d87307 636 #define GIC_INTERFACE_BASE RZ_A1_GIC_INTERFACE_BASE
tvendov 0:e1f465d87307 637 #define L2C_310_BASE RZ_A1_PL310_BASE
tvendov 0:e1f465d87307 638 #define TIMER_BASE RZ_A1_PRIVATE_TIMER
tvendov 0:e1f465d87307 639
tvendov 0:e1f465d87307 640 /* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */
tvendov 0:e1f465d87307 641 #define __CA_REV 0x0000U /*!< Core revision r0p0 */
tvendov 0:e1f465d87307 642 #define __CORTEX_A 9U /*!< Cortex-A9 Core */
tvendov 0:e1f465d87307 643 #if (__FPU_PRESENT != 1)
tvendov 0:e1f465d87307 644 #undef __FPU_PRESENT
tvendov 0:e1f465d87307 645 #define __FPU_PRESENT 1U /* FPU present */
tvendov 0:e1f465d87307 646 #endif
tvendov 0:e1f465d87307 647 #define __GIC_PRESENT 1U /* GIC present */
tvendov 0:e1f465d87307 648 #define __TIM_PRESENT 0U /* TIM present */
tvendov 0:e1f465d87307 649 #define __L2C_PRESENT 1U /* L2C present */
tvendov 0:e1f465d87307 650
tvendov 0:e1f465d87307 651 #include "core_ca.h"
tvendov 0:e1f465d87307 652 #include "nvic_wrapper.h"
tvendov 0:e1f465d87307 653 #include <system_VK_RZ_A1H.h>
tvendov 0:e1f465d87307 654 #include "iodefine.h"
tvendov 0:e1f465d87307 655
tvendov 0:e1f465d87307 656 /******************************************************************************/
tvendov 0:e1f465d87307 657 /* Clock Settings */
tvendov 0:e1f465d87307 658 /******************************************************************************/
tvendov 0:e1f465d87307 659 /*
tvendov 0:e1f465d87307 660 * Clock Mode 0 settings
tvendov 0:e1f465d87307 661 * SW1-4(MD_CLK):ON
tvendov 0:e1f465d87307 662 * SW1-5(MD_CLKS):ON
tvendov 0:e1f465d87307 663 * FRQCR=0x1035
tvendov 0:e1f465d87307 664 * CLKEN2 = 0b - unstable
tvendov 0:e1f465d87307 665 * CLKEN[1:0]=01b - Output, Low, Low
tvendov 0:e1f465d87307 666 * IFC[1:0] =00b - CPU clock is 1/1 PLL clock
tvendov 0:e1f465d87307 667 * FRQCR2=0x0001
tvendov 0:e1f465d87307 668 * GFC[1:0] =01b - Graphic clock is 2/3 bus clock
tvendov 0:e1f465d87307 669 */
tvendov 0:e1f465d87307 670 #define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u)
tvendov 0:e1f465d87307 671 #define CM0_RENESAS_RZ_A1_CLKO ( 66666666u)
tvendov 0:e1f465d87307 672 #define CM0_RENESAS_RZ_A1_I_CLK (400000000u)
tvendov 0:e1f465d87307 673 #define CM0_RENESAS_RZ_A1_G_CLK (266666666u)
tvendov 0:e1f465d87307 674 #define CM0_RENESAS_RZ_A1_B_CLK (133333333u)
tvendov 0:e1f465d87307 675 #define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
tvendov 0:e1f465d87307 676 #define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
tvendov 0:e1f465d87307 677
tvendov 0:e1f465d87307 678 /*
tvendov 0:e1f465d87307 679 * Clock Mode 1 settings
tvendov 0:e1f465d87307 680 * SW1-4(MD_CLK):OFF
tvendov 0:e1f465d87307 681 * SW1-5(MD_CLKS):ON
tvendov 0:e1f465d87307 682 * FRQCR=0x1335
tvendov 0:e1f465d87307 683 * CLKEN2 = 0b - unstable
tvendov 0:e1f465d87307 684 * CLKEN[1:0]=01b - Output, Low, Low
tvendov 0:e1f465d87307 685 * IFC[1:0] =11b - CPU clock is 1/3 PLL clock
tvendov 0:e1f465d87307 686 * FRQCR2=0x0003
tvendov 0:e1f465d87307 687 * GFC[1:0] =11b - graphic clock is 1/3 bus clock
tvendov 0:e1f465d87307 688 */
tvendov 0:e1f465d87307 689 #define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u)
tvendov 0:e1f465d87307 690 #define CM1_RENESAS_RZ_A1_CLKO ( 64000000u)
tvendov 0:e1f465d87307 691 #define CM1_RENESAS_RZ_A1_I_CLK (128000000u)
tvendov 0:e1f465d87307 692 #define CM1_RENESAS_RZ_A1_G_CLK (128000000u)
tvendov 0:e1f465d87307 693 #define CM1_RENESAS_RZ_A1_B_CLK (128000000u)
tvendov 0:e1f465d87307 694 #define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
tvendov 0:e1f465d87307 695 #define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
tvendov 0:e1f465d87307 696
tvendov 0:e1f465d87307 697 /******************************************************************************/
tvendov 0:e1f465d87307 698 /* CPG Settings */
tvendov 0:e1f465d87307 699 /******************************************************************************/
tvendov 0:e1f465d87307 700 #define CPG_FRQCR_SHIFT_CKOEN2 (14)
tvendov 0:e1f465d87307 701 #define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
tvendov 0:e1f465d87307 702 #define CPG_FRQCR_SHIFT_CKOEN0 (12)
tvendov 0:e1f465d87307 703 #define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
tvendov 0:e1f465d87307 704 #define CPG_FRQCR_SHIFT_IFC (8)
tvendov 0:e1f465d87307 705 #define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC)
tvendov 0:e1f465d87307 706
tvendov 0:e1f465d87307 707 #define CPG_FRQCR2_SHIFT_GFC (0)
tvendov 0:e1f465d87307 708 #define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC)
tvendov 0:e1f465d87307 709
tvendov 0:e1f465d87307 710
tvendov 0:e1f465d87307 711 #define CPG_STBCR1_BIT_STBY (0x80u)
tvendov 0:e1f465d87307 712 #define CPG_STBCR1_BIT_DEEP (0x40u)
tvendov 0:e1f465d87307 713 #define CPG_STBCR2_BIT_HIZ (0x80u)
tvendov 0:e1f465d87307 714 #define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */
tvendov 0:e1f465d87307 715 #define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */
tvendov 0:e1f465d87307 716 #define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */
tvendov 0:e1f465d87307 717 #define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */
tvendov 0:e1f465d87307 718 #define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */
tvendov 0:e1f465d87307 719 #define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */
tvendov 0:e1f465d87307 720 #define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */
tvendov 0:e1f465d87307 721 #define CPG_STBCR3_BIT_MSTP31 (0x02u) /* A/D converter (analog voltage) */
tvendov 0:e1f465d87307 722 #define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */
tvendov 0:e1f465d87307 723 #define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */
tvendov 0:e1f465d87307 724 #define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */
tvendov 0:e1f465d87307 725 #define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */
tvendov 0:e1f465d87307 726 #define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */
tvendov 0:e1f465d87307 727 #define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */
tvendov 0:e1f465d87307 728 #define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */
tvendov 0:e1f465d87307 729 #define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */
tvendov 0:e1f465d87307 730 #define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */
tvendov 0:e1f465d87307 731 #define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */
tvendov 0:e1f465d87307 732 #define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */
tvendov 0:e1f465d87307 733 #define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */
tvendov 0:e1f465d87307 734 #define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */
tvendov 0:e1f465d87307 735 #define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */
tvendov 0:e1f465d87307 736 #define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */
tvendov 0:e1f465d87307 737 #define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
tvendov 0:e1f465d87307 738 #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
tvendov 0:e1f465d87307 739 #define CPG_STBCR6_BIT_MSTP67 (0x80u) /* A/D converter (clock) */
tvendov 0:e1f465d87307 740 #define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */
tvendov 0:e1f465d87307 741 #define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */
tvendov 0:e1f465d87307 742 #define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */
tvendov 0:e1f465d87307 743 #define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range compression0 */
tvendov 0:e1f465d87307 744 #define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range compression1 */
tvendov 0:e1f465d87307 745 #define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */
tvendov 0:e1f465d87307 746 #define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */
tvendov 0:e1f465d87307 747 #define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */
tvendov 0:e1f465d87307 748 #define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */
tvendov 0:e1f465d87307 749 #define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ethernet */
tvendov 0:e1f465d87307 750 #define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */
tvendov 0:e1f465d87307 751 #define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */
tvendov 0:e1f465d87307 752 #define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */
tvendov 0:e1f465d87307 753 #define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */
tvendov 0:e1f465d87307 754 #define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */
tvendov 0:e1f465d87307 755 #define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */
tvendov 0:e1f465d87307 756 #define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */
tvendov 0:e1f465d87307 757 #define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */
tvendov 0:e1f465d87307 758 #define CPG_STBCR8_BIT_MSTP82 (0x04u) /* EthernetAVB */
tvendov 0:e1f465d87307 759 #define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */
tvendov 0:e1f465d87307 760 #define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */
tvendov 0:e1f465d87307 761 #define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */
tvendov 0:e1f465d87307 762 #define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */
tvendov 0:e1f465d87307 763 #define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */
tvendov 0:e1f465d87307 764 #define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */
tvendov 0:e1f465d87307 765 #define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */
tvendov 0:e1f465d87307 766 #define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */
tvendov 0:e1f465d87307 767 #define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */
tvendov 0:e1f465d87307 768 #define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
tvendov 0:e1f465d87307 769 #define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
tvendov 0:e1f465d87307 770 #define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
tvendov 0:e1f465d87307 771 #define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
tvendov 0:e1f465d87307 772 #define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
tvendov 0:e1f465d87307 773 #define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
tvendov 0:e1f465d87307 774 #define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
tvendov 0:e1f465d87307 775 #define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
tvendov 0:e1f465d87307 776 #define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
tvendov 0:e1f465d87307 777 #define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
tvendov 0:e1f465d87307 778 #define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
tvendov 0:e1f465d87307 779 #define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
tvendov 0:e1f465d87307 780 #define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
tvendov 0:e1f465d87307 781 #define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
tvendov 0:e1f465d87307 782 #define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
tvendov 0:e1f465d87307 783 #define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
tvendov 0:e1f465d87307 784 #define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
tvendov 0:e1f465d87307 785 #define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
tvendov 0:e1f465d87307 786 #define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */
tvendov 0:e1f465d87307 787 #define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */
tvendov 0:e1f465d87307 788 #define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
tvendov 0:e1f465d87307 789 #define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
tvendov 0:e1f465d87307 790 #define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
tvendov 0:e1f465d87307 791 #define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
tvendov 0:e1f465d87307 792 #define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
tvendov 0:e1f465d87307 793 #define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
tvendov 0:e1f465d87307 794 #define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
tvendov 0:e1f465d87307 795 #define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
tvendov 0:e1f465d87307 796 #define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
tvendov 0:e1f465d87307 797 #define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */
tvendov 0:e1f465d87307 798 #define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */
tvendov 0:e1f465d87307 799 #define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */
tvendov 0:e1f465d87307 800 #define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */
tvendov 0:e1f465d87307 801 #define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */
tvendov 0:e1f465d87307 802 #define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */
tvendov 0:e1f465d87307 803 #define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */
tvendov 0:e1f465d87307 804 #define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */
tvendov 0:e1f465d87307 805 #define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */
tvendov 0:e1f465d87307 806 #define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */
tvendov 0:e1f465d87307 807 #define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */
tvendov 0:e1f465d87307 808 #define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */
tvendov 0:e1f465d87307 809 #define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */
tvendov 0:e1f465d87307 810 #define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */
tvendov 0:e1f465d87307 811 #define CPG_CPUSTS_BIT_ISBUSY (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */
tvendov 0:e1f465d87307 812 #define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */
tvendov 0:e1f465d87307 813 #define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */
tvendov 0:e1f465d87307 814 #define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */
tvendov 0:e1f465d87307 815 #define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */
tvendov 0:e1f465d87307 816 #define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */
tvendov 0:e1f465d87307 817 #define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */
tvendov 0:e1f465d87307 818 #define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */
tvendov 0:e1f465d87307 819 #define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */
tvendov 0:e1f465d87307 820 #define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */
tvendov 0:e1f465d87307 821 #define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */
tvendov 0:e1f465d87307 822 #define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */
tvendov 0:e1f465d87307 823 #define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */
tvendov 0:e1f465d87307 824 #define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */
tvendov 0:e1f465d87307 825 #define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */
tvendov 0:e1f465d87307 826 #define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */
tvendov 0:e1f465d87307 827 #define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */
tvendov 0:e1f465d87307 828 #define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */
tvendov 0:e1f465d87307 829 #define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */
tvendov 0:e1f465d87307 830 #define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */
tvendov 0:e1f465d87307 831 #define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */
tvendov 0:e1f465d87307 832 #define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */
tvendov 0:e1f465d87307 833 #define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */
tvendov 0:e1f465d87307 834 #define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */
tvendov 0:e1f465d87307 835 #define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */
tvendov 0:e1f465d87307 836 #define CPG_RRAMKP_BIT_RRAMKP3 (0x08u) /* RRAM KP Page3 */
tvendov 0:e1f465d87307 837 #define CPG_RRAMKP_BIT_RRAMKP2 (0x04u) /* RRAM KP Page2 */
tvendov 0:e1f465d87307 838 #define CPG_RRAMKP_BIT_RRAMKP1 (0x02u) /* RRAM KP Page1 */
tvendov 0:e1f465d87307 839 #define CPG_RRAMKP_BIT_RRAMKP0 (0x01u) /* RRAM KP Page0 */
tvendov 0:e1f465d87307 840 #define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */
tvendov 0:e1f465d87307 841 #define CPG_DSCTR_BIT_RAMBOOT (0x40u) /* Selection of Method after Returning from Deep Standby Mode */
tvendov 0:e1f465d87307 842 #define CPG_DSSSR_BIT_P6_2 (0x4000u) /* P6_2 */
tvendov 0:e1f465d87307 843 #define CPG_DSSSR_BIT_P3_9 (0x2000u) /* P3_9 */
tvendov 0:e1f465d87307 844 #define CPG_DSSSR_BIT_P3_1 (0x1000u) /* P3_1 */
tvendov 0:e1f465d87307 845 #define CPG_DSSSR_BIT_P2_12 (0x0800u) /* P2_12 */
tvendov 0:e1f465d87307 846 #define CPG_DSSSR_BIT_P8_7 (0x0400u) /* P8_7 */
tvendov 0:e1f465d87307 847 #define CPG_DSSSR_BIT_P3_3 (0x0200u) /* P3_3 */
tvendov 0:e1f465d87307 848 #define CPG_DSSSR_BIT_NMI (0x0100u) /* NMI */
tvendov 0:e1f465d87307 849 #define CPG_DSSSR_BIT_RTCAR (0x0040u) /* RTCAR */
tvendov 0:e1f465d87307 850 #define CPG_DSSSR_BIT_P6_4 (0x0020u) /* P6_4 */
tvendov 0:e1f465d87307 851 #define CPG_DSSSR_BIT_P5_9 (0x0010u) /* P5_9 */
tvendov 0:e1f465d87307 852 #define CPG_DSSSR_BIT_P7_8 (0x0008u) /* P7_8 */
tvendov 0:e1f465d87307 853 #define CPG_DSSSR_BIT_P2_15 (0x0004u) /* P2_15 */
tvendov 0:e1f465d87307 854 #define CPG_DSSSR_BIT_P9_1 (0x0002u) /* P9_1 */
tvendov 0:e1f465d87307 855 #define CPG_DSSSR_BIT_P8_2 (0x0001u) /* P8_2 */
tvendov 0:e1f465d87307 856 #define CPG_DSESR_BIT_P6_2E (0x4000u) /* P6_2 */
tvendov 0:e1f465d87307 857 #define CPG_DSESR_BIT_P3_9E (0x2000u) /* P3_9 */
tvendov 0:e1f465d87307 858 #define CPG_DSESR_BIT_P3_1E (0x1000u) /* P3_1 */
tvendov 0:e1f465d87307 859 #define CPG_DSESR_BIT_P2_12E (0x0800u) /* P2_12 */
tvendov 0:e1f465d87307 860 #define CPG_DSESR_BIT_P8_7E (0x0400u) /* P8_7 */
tvendov 0:e1f465d87307 861 #define CPG_DSESR_BIT_P3_3E (0x0200u) /* P3_3 */
tvendov 0:e1f465d87307 862 #define CPG_DSESR_BIT_NMIE (0x0100u) /* NMI */
tvendov 0:e1f465d87307 863 #define CPG_DSESR_BIT_P6_4E (0x0020u) /* P6_4 */
tvendov 0:e1f465d87307 864 #define CPG_DSESR_BIT_P5_9E (0x0010u) /* P5_9 */
tvendov 0:e1f465d87307 865 #define CPG_DSESR_BIT_P7_8E (0x0008u) /* P7_8 */
tvendov 0:e1f465d87307 866 #define CPG_DSESR_BIT_P2_15E (0x0004u) /* P2_15 */
tvendov 0:e1f465d87307 867 #define CPG_DSESR_BIT_P9_1E (0x0002u) /* P9_1 */
tvendov 0:e1f465d87307 868 #define CPG_DSESR_BIT_P8_2E (0x0001u) /* P8_2 */
tvendov 0:e1f465d87307 869 #define CPG_DSFR_BIT_IOKEEP (0x8000u) /* Release of Pin State Retention */
tvendov 0:e1f465d87307 870 #define CPG_DSFR_BIT_P6_2F (0x4000u) /* P6_2 */
tvendov 0:e1f465d87307 871 #define CPG_DSFR_BIT_P3_9F (0x2000u) /* P3_9 */
tvendov 0:e1f465d87307 872 #define CPG_DSFR_BIT_P3_1F (0x1000u) /* P3_1 */
tvendov 0:e1f465d87307 873 #define CPG_DSFR_BIT_P2_12F (0x0800u) /* P2_12 */
tvendov 0:e1f465d87307 874 #define CPG_DSFR_BIT_P8_7F (0x0400u) /* P8_7 */
tvendov 0:e1f465d87307 875 #define CPG_DSFR_BIT_P3_3F (0x0200u) /* P3_3 */
tvendov 0:e1f465d87307 876 #define CPG_DSFR_BIT_NMIF (0x0100u) /* NMI */
tvendov 0:e1f465d87307 877 #define CPG_DSFR_BIT_RTCARF (0x0040u) /* RTCAR */
tvendov 0:e1f465d87307 878 #define CPG_DSFR_BIT_P6_4F (0x0020u) /* P6_4 */
tvendov 0:e1f465d87307 879 #define CPG_DSFR_BIT_P5_9F (0x0010u) /* P5_9 */
tvendov 0:e1f465d87307 880 #define CPG_DSFR_BIT_P7_8F (0x0008u) /* P7_8 */
tvendov 0:e1f465d87307 881 #define CPG_DSFR_BIT_P2_15F (0x0004u) /* P2_15 */
tvendov 0:e1f465d87307 882 #define CPG_DSFR_BIT_P9_1F (0x0002u) /* P9_1 */
tvendov 0:e1f465d87307 883 #define CPG_DSFR_BIT_P8_2F (0x0001u) /* P8_2 */
tvendov 0:e1f465d87307 884 #define CPG_XTALCTR_BIT_GAIN1 (0x02u) /* RTC_X3, RTC_X4 */
tvendov 0:e1f465d87307 885 #define CPG_XTALCTR_BIT_GAIN0 (0x01u) /* EXTAL, XTAL */
tvendov 0:e1f465d87307 886
tvendov 0:e1f465d87307 887 /******************************************************************************/
tvendov 0:e1f465d87307 888 /* GPIO Settings */
tvendov 0:e1f465d87307 889 /******************************************************************************/
tvendov 0:e1f465d87307 890 #define GPIO_BIT_N0 (1u << 0)
tvendov 0:e1f465d87307 891 #define GPIO_BIT_N1 (1u << 1)
tvendov 0:e1f465d87307 892 #define GPIO_BIT_N2 (1u << 2)
tvendov 0:e1f465d87307 893 #define GPIO_BIT_N3 (1u << 3)
tvendov 0:e1f465d87307 894 #define GPIO_BIT_N4 (1u << 4)
tvendov 0:e1f465d87307 895 #define GPIO_BIT_N5 (1u << 5)
tvendov 0:e1f465d87307 896 #define GPIO_BIT_N6 (1u << 6)
tvendov 0:e1f465d87307 897 #define GPIO_BIT_N7 (1u << 7)
tvendov 0:e1f465d87307 898 #define GPIO_BIT_N8 (1u << 8)
tvendov 0:e1f465d87307 899 #define GPIO_BIT_N9 (1u << 9)
tvendov 0:e1f465d87307 900 #define GPIO_BIT_N10 (1u << 10)
tvendov 0:e1f465d87307 901 #define GPIO_BIT_N11 (1u << 11)
tvendov 0:e1f465d87307 902 #define GPIO_BIT_N12 (1u << 12)
tvendov 0:e1f465d87307 903 #define GPIO_BIT_N13 (1u << 13)
tvendov 0:e1f465d87307 904 #define GPIO_BIT_N14 (1u << 14)
tvendov 0:e1f465d87307 905 #define GPIO_BIT_N15 (1u << 15)
tvendov 0:e1f465d87307 906
tvendov 0:e1f465d87307 907 #define MD_BOOT10_MASK (0x3)
tvendov 0:e1f465d87307 908
tvendov 0:e1f465d87307 909 #define MD_BOOT10_BM0 (0x0)
tvendov 0:e1f465d87307 910 #define MD_BOOT10_BM1 (0x2)
tvendov 0:e1f465d87307 911 #define MD_BOOT10_BM3 (0x1)
tvendov 0:e1f465d87307 912 #define MD_BOOT10_BM4_5 (0x3)
tvendov 0:e1f465d87307 913
tvendov 0:e1f465d87307 914 #define MD_CLK (1u << 2)
tvendov 0:e1f465d87307 915 #define MD_CLKS (1u << 3)
tvendov 0:e1f465d87307 916
tvendov 0:e1f465d87307 917
tvendov 0:e1f465d87307 918 #ifdef __cplusplus
tvendov 0:e1f465d87307 919 }
tvendov 0:e1f465d87307 920 #endif
tvendov 0:e1f465d87307 921
tvendov 0:e1f465d87307 922 #endif // __VK_RZ_A1H_H__
tvendov 0:e1f465d87307 923