Vekatech / SDHI_driver_variant_II

SDHI_driver patch (mbedOS 5.11.5)

mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdhi_iodefine.h@1:6f9a14a6bcac, 2019-03-20 (annotated)

Committer:
tvendov
Date:
Wed Mar 20 17:51:14 2019 +0000
Revision:
1:6f9a14a6bcac
Fix: No more SYNC_FAIL. SD Tests are running smoothly!

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tvendov 1:6f9a14a6bcac 1 /*******************************************************************************
tvendov 1:6f9a14a6bcac 2 * DISCLAIMER
tvendov 1:6f9a14a6bcac 3 *******************************************************************************/
tvendov 1:6f9a14a6bcac 4 /*******************************************************************************
tvendov 1:6f9a14a6bcac 5 * File Name : sdhi_iodefine.h
tvendov 1:6f9a14a6bcac 6 * $Rev: $
tvendov 1:6f9a14a6bcac 7 * $Date:: $
tvendov 1:6f9a14a6bcac 8 * Description : Definition of I/O Register for RZ/A1
tvendov 1:6f9a14a6bcac 9 ******************************************************************************/
tvendov 1:6f9a14a6bcac 10 #ifndef SDHI_IODEFINE_H
tvendov 1:6f9a14a6bcac 11 #define SDHI_IODEFINE_H
tvendov 1:6f9a14a6bcac 12 /* ->QAC 0639 : Over 127 members (C90) */
tvendov 1:6f9a14a6bcac 13 /* ->QAC 0857 : Over 1024 #define (C90) */
tvendov 1:6f9a14a6bcac 14 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
tvendov 1:6f9a14a6bcac 15 /* ->SEC M1.10.1 : Not magic number */
tvendov 1:6f9a14a6bcac 16
tvendov 1:6f9a14a6bcac 17 #define SDHI0 (*(struct st_sdhi *)0xE804E000uL) /* SDHI0 */
tvendov 1:6f9a14a6bcac 18 #define SDHI1 (*(struct st_sdhi *)0xE804E800uL) /* SDHI1 */
tvendov 1:6f9a14a6bcac 19
tvendov 1:6f9a14a6bcac 20
tvendov 1:6f9a14a6bcac 21 /* Start of channel array defines of SDHI */
tvendov 1:6f9a14a6bcac 22
tvendov 1:6f9a14a6bcac 23 /* Channel array defines of SDHI */
tvendov 1:6f9a14a6bcac 24 /*(Sample) value = SDHI[ channel ]->SD_CMD; */
tvendov 1:6f9a14a6bcac 25 #define SDHI_COUNT (2)
tvendov 1:6f9a14a6bcac 26 #define SDHI_ADDRESS_LIST \
tvendov 1:6f9a14a6bcac 27 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
tvendov 1:6f9a14a6bcac 28 &SDHI0 \
tvendov 1:6f9a14a6bcac 29 &SDHI1 \
tvendov 1:6f9a14a6bcac 30 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
tvendov 1:6f9a14a6bcac 31
tvendov 1:6f9a14a6bcac 32 /* End of channel array defines of SDHI */
tvendov 1:6f9a14a6bcac 33
tvendov 1:6f9a14a6bcac 34
tvendov 1:6f9a14a6bcac 35 #define SD_CMD_0 (SDHI0.SD_CMD)
tvendov 1:6f9a14a6bcac 36 #define SD_ARG0_0 (SDHI0.SD_ARG0)
tvendov 1:6f9a14a6bcac 37 #define SD_ARG1_0 (SDHI0.SD_ARG1)
tvendov 1:6f9a14a6bcac 38 #define SD_STOP_0 (SDHI0.SD_STOP)
tvendov 1:6f9a14a6bcac 39 #define SD_SECCNT_0 (SDHI0.SD_SECCNT)
tvendov 1:6f9a14a6bcac 40 #define SD_RSP00_0 (SDHI0.SD_RSP00)
tvendov 1:6f9a14a6bcac 41 #define SD_RSP01_0 (SDHI0.SD_RSP01)
tvendov 1:6f9a14a6bcac 42 #define SD_RSP02_0 (SDHI0.SD_RSP02)
tvendov 1:6f9a14a6bcac 43 #define SD_RSP03_0 (SDHI0.SD_RSP03)
tvendov 1:6f9a14a6bcac 44 #define SD_RSP04_0 (SDHI0.SD_RSP04)
tvendov 1:6f9a14a6bcac 45 #define SD_RSP05_0 (SDHI0.SD_RSP05)
tvendov 1:6f9a14a6bcac 46 #define SD_RSP06_0 (SDHI0.SD_RSP06)
tvendov 1:6f9a14a6bcac 47 #define SD_RSP07_0 (SDHI0.SD_RSP07)
tvendov 1:6f9a14a6bcac 48 #define SD_INFO1_0 (SDHI0.SD_INFO1)
tvendov 1:6f9a14a6bcac 49 #define SD_INFO2_0 (SDHI0.SD_INFO2)
tvendov 1:6f9a14a6bcac 50 #define SD_INFO1_MASK_0 (SDHI0.SD_INFO1_MASK)
tvendov 1:6f9a14a6bcac 51 #define SD_INFO2_MASK_0 (SDHI0.SD_INFO2_MASK)
tvendov 1:6f9a14a6bcac 52 #define SD_CLK_CTRL_0 (SDHI0.SD_CLK_CTRL)
tvendov 1:6f9a14a6bcac 53 #define SD_SIZE_0 (SDHI0.SD_SIZE)
tvendov 1:6f9a14a6bcac 54 #define SD_OPTION_0 (SDHI0.SD_OPTION)
tvendov 1:6f9a14a6bcac 55 #define SD_ERR_STS1_0 (SDHI0.SD_ERR_STS1)
tvendov 1:6f9a14a6bcac 56 #define SD_ERR_STS2_0 (SDHI0.SD_ERR_STS2)
tvendov 1:6f9a14a6bcac 57 #define SD_BUF0_0 (SDHI0.SD_BUF0)
tvendov 1:6f9a14a6bcac 58 #define SDIO_MODE_0 (SDHI0.SDIO_MODE)
tvendov 1:6f9a14a6bcac 59 #define SDIO_INFO1_0 (SDHI0.SDIO_INFO1)
tvendov 1:6f9a14a6bcac 60 #define SDIO_INFO1_MASK_0 (SDHI0.SDIO_INFO1_MASK)
tvendov 1:6f9a14a6bcac 61 #define CC_EXT_MODE_0 (SDHI0.CC_EXT_MODE)
tvendov 1:6f9a14a6bcac 62 #define SOFT_RST_0 (SDHI0.SOFT_RST)
tvendov 1:6f9a14a6bcac 63 #define VERSION_0 (SDHI0.VERSION)
tvendov 1:6f9a14a6bcac 64 #define EXT_SWAP_0 (SDHI0.EXT_SWAP)
tvendov 1:6f9a14a6bcac 65
tvendov 1:6f9a14a6bcac 66 #define SD_CMD_1 (SDHI1.SD_CMD)
tvendov 1:6f9a14a6bcac 67 #define SD_ARG0_1 (SDHI1.SD_ARG0)
tvendov 1:6f9a14a6bcac 68 #define SD_ARG1_1 (SDHI1.SD_ARG1)
tvendov 1:6f9a14a6bcac 69 #define SD_STOP_1 (SDHI1.SD_STOP)
tvendov 1:6f9a14a6bcac 70 #define SD_SECCNT_1 (SDHI1.SD_SECCNT)
tvendov 1:6f9a14a6bcac 71 #define SD_RSP00_1 (SDHI1.SD_RSP00)
tvendov 1:6f9a14a6bcac 72 #define SD_RSP01_1 (SDHI1.SD_RSP01)
tvendov 1:6f9a14a6bcac 73 #define SD_RSP02_1 (SDHI1.SD_RSP02)
tvendov 1:6f9a14a6bcac 74 #define SD_RSP03_1 (SDHI1.SD_RSP03)
tvendov 1:6f9a14a6bcac 75 #define SD_RSP04_1 (SDHI1.SD_RSP04)
tvendov 1:6f9a14a6bcac 76 #define SD_RSP05_1 (SDHI1.SD_RSP05)
tvendov 1:6f9a14a6bcac 77 #define SD_RSP06_1 (SDHI1.SD_RSP06)
tvendov 1:6f9a14a6bcac 78 #define SD_RSP07_1 (SDHI1.SD_RSP07)
tvendov 1:6f9a14a6bcac 79 #define SD_INFO1_1 (SDHI1.SD_INFO1)
tvendov 1:6f9a14a6bcac 80 #define SD_INFO2_1 (SDHI1.SD_INFO2)
tvendov 1:6f9a14a6bcac 81 #define SD_INFO1_MASK_1 (SDHI1.SD_INFO1_MASK)
tvendov 1:6f9a14a6bcac 82 #define SD_INFO2_MASK_1 (SDHI1.SD_INFO2_MASK)
tvendov 1:6f9a14a6bcac 83 #define SD_CLK_CTRL_1 (SDHI1.SD_CLK_CTRL)
tvendov 1:6f9a14a6bcac 84 #define SD_SIZE_1 (SDHI1.SD_SIZE)
tvendov 1:6f9a14a6bcac 85 #define SD_OPTION_1 (SDHI1.SD_OPTION)
tvendov 1:6f9a14a6bcac 86 #define SD_ERR_STS1_1 (SDHI1.SD_ERR_STS1)
tvendov 1:6f9a14a6bcac 87 #define SD_ERR_STS2_1 (SDHI1.SD_ERR_STS2)
tvendov 1:6f9a14a6bcac 88 #define SD_BUF0_1 (SDHI1.SD_BUF0)
tvendov 1:6f9a14a6bcac 89 #define SDIO_MODE_1 (SDHI1.SDIO_MODE)
tvendov 1:6f9a14a6bcac 90 #define SDIO_INFO1_1 (SDHI1.SDIO_INFO1)
tvendov 1:6f9a14a6bcac 91 #define SDIO_INFO1_MASK_1 (SDHI1.SDIO_INFO1_MASK)
tvendov 1:6f9a14a6bcac 92 #define CC_EXT_MODE_1 (SDHI1.CC_EXT_MODE)
tvendov 1:6f9a14a6bcac 93 #define SOFT_RST_1 (SDHI1.SOFT_RST)
tvendov 1:6f9a14a6bcac 94 #define VERSION_1 (SDHI1.VERSION)
tvendov 1:6f9a14a6bcac 95 #define EXT_SWAP_1 (SDHI1.EXT_SWAP)
tvendov 1:6f9a14a6bcac 96
tvendov 1:6f9a14a6bcac 97 typedef struct st_sdhi
tvendov 1:6f9a14a6bcac 98 {
tvendov 1:6f9a14a6bcac 99 /* SDHI */
tvendov 1:6f9a14a6bcac 100 volatile uint16_t SD_CMD; /* SD_CMD */
tvendov 1:6f9a14a6bcac 101 volatile uint8_t dummy1[2]; /* */
tvendov 1:6f9a14a6bcac 102 volatile uint16_t SD_ARG0; /* SSLDR */
tvendov 1:6f9a14a6bcac 103 volatile uint16_t SD_ARG1; /* SSLDR */
tvendov 1:6f9a14a6bcac 104 volatile uint16_t SD_STOP; /* SPBCR */
tvendov 1:6f9a14a6bcac 105 volatile uint16_t SD_SECCNT; /* SPBCR */
tvendov 1:6f9a14a6bcac 106 volatile uint16_t SD_RSP00; /* SPBCR */
tvendov 1:6f9a14a6bcac 107 volatile uint16_t SD_RSP01; /* SPBCR */
tvendov 1:6f9a14a6bcac 108 volatile uint16_t SD_RSP02; /* SPBCR */
tvendov 1:6f9a14a6bcac 109 volatile uint16_t SD_RSP03; /* SPBCR */
tvendov 1:6f9a14a6bcac 110 volatile uint16_t SD_RSP04; /* SPBCR */
tvendov 1:6f9a14a6bcac 111 volatile uint16_t SD_RSP05; /* SPBCR */
tvendov 1:6f9a14a6bcac 112 volatile uint16_t SD_RSP06; /* SPBCR */
tvendov 1:6f9a14a6bcac 113 volatile uint16_t SD_RSP07; /* SPBCR */
tvendov 1:6f9a14a6bcac 114 volatile uint16_t SD_INFO1; /* SPBCR */
tvendov 1:6f9a14a6bcac 115 volatile uint16_t SD_INFO2; /* SPBCR */
tvendov 1:6f9a14a6bcac 116 volatile uint16_t SD_INFO1_MASK; /* SPBCR */
tvendov 1:6f9a14a6bcac 117 volatile uint16_t SD_INFO2_MASK; /* SPBCR */
tvendov 1:6f9a14a6bcac 118 volatile uint16_t SD_CLK_CTRL; /* SPBCR */
tvendov 1:6f9a14a6bcac 119 volatile uint16_t SD_SIZE; /* SPBCR */
tvendov 1:6f9a14a6bcac 120 volatile uint16_t SD_OPTION; /* SPBCR */
tvendov 1:6f9a14a6bcac 121 volatile uint8_t dummy2[2]; /* */
tvendov 1:6f9a14a6bcac 122 volatile uint16_t SD_ERR_STS1; /* SPBCR */
tvendov 1:6f9a14a6bcac 123 volatile uint16_t SD_ERR_STS2; /* SPBCR */
tvendov 1:6f9a14a6bcac 124 volatile uint32_t SD_BUF0; /* DRCR */
tvendov 1:6f9a14a6bcac 125 volatile uint16_t SDIO_MODE; /* DRCMR */
tvendov 1:6f9a14a6bcac 126 volatile uint16_t SDIO_INFO1; /* DREAR */
tvendov 1:6f9a14a6bcac 127 volatile uint16_t SDIO_INFO1_MASK; /* DROPR */
tvendov 1:6f9a14a6bcac 128 volatile uint8_t dummy3[158]; /* */
tvendov 1:6f9a14a6bcac 129 volatile uint16_t CC_EXT_MODE; /* DRENR */
tvendov 1:6f9a14a6bcac 130 volatile uint8_t dummy4[6]; /* */
tvendov 1:6f9a14a6bcac 131 volatile uint16_t SOFT_RST; /* SMCR */
tvendov 1:6f9a14a6bcac 132 volatile uint16_t VERSION; /* SMCMR */
tvendov 1:6f9a14a6bcac 133 volatile uint8_t dummy5[12]; /* */
tvendov 1:6f9a14a6bcac 134 volatile uint16_t EXT_SWAP; /* SMADR */
tvendov 1:6f9a14a6bcac 135 } r_io_sdhi_t;
tvendov 1:6f9a14a6bcac 136
tvendov 1:6f9a14a6bcac 137
tvendov 1:6f9a14a6bcac 138 /* Channel array defines of SDHI (2)*/
tvendov 1:6f9a14a6bcac 139 #ifdef DECLARE_SDHI_CHANNELS
tvendov 1:6f9a14a6bcac 140 volatile struct st_sdhi* SDHI[ SDHI_COUNT ] =
tvendov 1:6f9a14a6bcac 141 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
tvendov 1:6f9a14a6bcac 142 SDHI_ADDRESS_LIST;
tvendov 1:6f9a14a6bcac 143 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
tvendov 1:6f9a14a6bcac 144 #endif /* DECLARE_SPIBSC_CHANNELS */
tvendov 1:6f9a14a6bcac 145 /* End of channel array defines of SDHI (2)*/
tvendov 1:6f9a14a6bcac 146
tvendov 1:6f9a14a6bcac 147
tvendov 1:6f9a14a6bcac 148 /* <-SEC M1.10.1 */
tvendov 1:6f9a14a6bcac 149 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
tvendov 1:6f9a14a6bcac 150 /* <-QAC 0857 */
tvendov 1:6f9a14a6bcac 151 /* <-QAC 0639 */
tvendov 1:6f9a14a6bcac 152 #endif
tvendov 1:6f9a14a6bcac 153