Vekatech
SDHI_driver patch (mbedOS 5.11.5)
Revision 0:e669d762f08a, committed 2019-03-18
- Comitter:
- tvendov
- Date:
- Mon Mar 18 11:46:29 2019 +0000
- Child:
- 1:b07be64e592e
- Commit message:
- SDHI driver initial release
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/SD_dirs(ARM).log Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,108 @@
+[1552902532.73][HTST][INF] host test executor ver. 0.0.1
+[1552902532.73][HTST][INF] copy image onto target... SKIPPED!
+[1552902532.73][HTST][INF] starting host test process...
+[1552902533.38][CONN][INF] starting connection process...
+[1552902533.38][CONN][INF] notify event queue about extra 60 sec timeout for serial port pooling
+[1552902533.38][CONN][INF] initializing serial port listener...
+[1552902533.38][SERI][INF] serial(port=COM27, baudrate=9600, read_timeout=0.01, write_timeout=5)
+[1552902533.38][SERI][TXD] mbedmbedmbedmbedmbedmbedmbedmbedmbedmbed
+[1552902533.38][CONN][INF] sending up to 2 __sync packets (specified with --sync=2)
+[1552902533.38][CONN][INF] sending preamble '3a5b5d7c-9ab9-43a8-9793-7b1a22f1de86'
+[1552902533.38][HTST][INF] setting timeout to: 60 sec
+[1552902533.43][SERI][TXD] {{__sync;3a5b5d7c-9ab9-43a8-9793-7b1a22f1de86}}
+[1552902533.52][CONN][RXD] mbedmbedmbedmbedmbedmbedmbedmbed
+[1552902533.57][CONN][INF] found SYNC in stream: {{__sync;3a5b5d7c-9ab9-43a8-9793-7b1a22f1de86}} it is #0 sent, queued...
+[1552902533.58][HTST][INF] sync KV found, uuid=3a5b5d7c-9ab9-43a8-9793-7b1a22f1de86, timestamp=1552902533.572000
+[1552902533.59][CONN][INF] found KV pair in stream: {{__version;1.3.0}}, queued...
+[1552902533.60][HTST][INF] DUT greentea-client version: 1.3.0
+[1552902533.61][CONN][INF] found KV pair in stream: {{__timeout;120}}, queued...
+[1552902533.61][HTST][INF] setting timeout to: 120 sec
+[1552902533.65][CONN][INF] found KV pair in stream: {{__host_test_name;default_auto}}, queued...
+[1552902533.65][HTST][INF] host test class: '<class 'mbed_os_tools.test.host_tests.default_auto.DefaultAuto'>'
+[1552902533.65][HTST][INF] host test setup() call...
+[1552902533.65][HTST][INF] CALLBACKs updated
+[1552902533.65][HTST][INF] host test detected: default_auto
+[1552902533.68][CONN][RXD] >>> Running 10 test cases...
+[1552902533.71][CONN][INF] found KV pair in stream: {{__testcase_name;Directory tests}}, queued...
+[1552902533.75][CONN][INF] found KV pair in stream: {{__testcase_name;Root directory}}, queued...
+[1552902533.80][CONN][INF] found KV pair in stream: {{__testcase_name;Directory creation}}, queued...
+[1552902533.83][CONN][INF] found KV pair in stream: {{__testcase_name;File creation}}, queued...
+[1552902533.87][CONN][INF] found KV pair in stream: {{__testcase_name;Directory iteration}}, queued...
+[1552902533.91][CONN][INF] found KV pair in stream: {{__testcase_name;Directory failures}}, queued...
+[1552902533.95][CONN][INF] found KV pair in stream: {{__testcase_name;Nested directories}}, queued...
+[1552902534.00][CONN][INF] found KV pair in stream: {{__testcase_name;Multi-block directory}}, queued...
+[1552902534.04][CONN][INF] found KV pair in stream: {{__testcase_name;Directory remove}}, queued...
+[1552902534.08][CONN][INF] found KV pair in stream: {{__testcase_name;Directory rename}}, queued...
+[1552902534.09][CONN][RXD]
+[1552902534.13][CONN][RXD] >>> Running case #1: 'Directory tests'...
+[1552902534.16][CONN][INF] found KV pair in stream: {{__testcase_start;Directory tests}}, queued...
+[1552902534.29][CONN][RXD] init card = 1
+[1552902534.35][CONN][RXD] CSD is 40 0E 00 5A 5B 59 00 00 74 B7 7F 80 0A 40 00 00
+[1552902534.38][CONN][RXD] SDHC/SDXC Card: hc_c_size: 29879
+[1552902534.41][CONN][RXD] Sectors: 0x1d2e000 : 30597120
+[1552902534.44][CONN][RXD] Capacity: 14940 MB
+[1552902534.74][CONN][INF] found KV pair in stream: {{__testcase_finish;Directory tests;1;0}}, queued...
+[1552902534.79][CONN][RXD] >>> 'Directory tests': 1 passed, 0 failed
+[1552902534.79][CONN][RXD]
+[1552902534.83][CONN][RXD] >>> Running case #2: 'Root directory'...
+[1552902534.87][CONN][INF] found KV pair in stream: {{__testcase_start;Root directory}}, queued...
+[1552902534.91][CONN][INF] found KV pair in stream: {{__testcase_finish;Root directory;1;0}}, queued...
+[1552902534.96][CONN][RXD] >>> 'Root directory': 1 passed, 0 failed
+[1552902534.96][CONN][RXD]
+[1552902535.00][CONN][RXD] >>> Running case #3: 'Directory creation'...
+[1552902535.04][CONN][INF] found KV pair in stream: {{__testcase_start;Directory creation}}, queued...
+[1552902535.10][CONN][INF] found KV pair in stream: {{__testcase_finish;Directory creation;1;0}}, queued...
+[1552902535.14][CONN][RXD] >>> 'Directory creation': 1 passed, 0 failed
+[1552902535.15][CONN][RXD]
+[1552902535.20][CONN][RXD] >>> Running case #4: 'File creation'...
+[1552902535.23][CONN][INF] found KV pair in stream: {{__testcase_start;File creation}}, queued...
+[1552902535.27][CONN][INF] found KV pair in stream: {{__testcase_finish;File creation;1;0}}, queued...
+[1552902535.31][CONN][RXD] >>> 'File creation': 1 passed, 0 failed
+[1552902535.31][CONN][RXD]
+[1552902535.37][CONN][RXD] >>> Running case #5: 'Directory iteration'...
+[1552902535.41][CONN][INF] found KV pair in stream: {{__testcase_start;Directory iteration}}, queued...
+[1552902535.45][CONN][INF] found KV pair in stream: {{__testcase_finish;Directory iteration;1;0}}, queued...
+[1552902535.51][CONN][RXD] >>> 'Directory iteration': 1 passed, 0 failed
+[1552902535.51][CONN][RXD]
+[1552902535.55][CONN][RXD] >>> Running case #6: 'Directory failures'...
+[1552902535.59][CONN][INF] found KV pair in stream: {{__testcase_start;Directory failures}}, queued...
+[1552902535.64][CONN][INF] found KV pair in stream: {{__testcase_finish;Directory failures;1;0}}, queued...
+[1552902535.69][CONN][RXD] >>> 'Directory failures': 1 passed, 0 failed
+[1552902535.69][CONN][RXD]
+[1552902535.74][CONN][RXD] >>> Running case #7: 'Nested directories'...
+[1552902535.79][CONN][INF] found KV pair in stream: {{__testcase_start;Nested directories}}, queued...
+[1552902535.87][CONN][INF] found KV pair in stream: {{__testcase_finish;Nested directories;1;0}}, queued...
+[1552902535.91][CONN][RXD] >>> 'Nested directories': 1 passed, 0 failed
+[1552902535.91][CONN][RXD]
+[1552902535.96][CONN][RXD] >>> Running case #8: 'Multi-block directory'...
+[1552902536.01][CONN][INF] found KV pair in stream: {{__testcase_start;Multi-block directory}}, queued...
+[1552902538.53][CONN][INF] found KV pair in stream: {{__testcase_finish;Multi-block directory;1;0}}, queued...
+[1552902538.59][CONN][RXD] >>> 'Multi-block directory': 1 passed, 0 failed
+[1552902538.59][CONN][RXD]
+[1552902538.63][CONN][RXD] >>> Running case #9: 'Directory remove'...
+[1552902538.67][CONN][INF] found KV pair in stream: {{__testcase_start;Directory remove}}, queued...
+[1552902538.74][CONN][INF] found KV pair in stream: {{__testcase_finish;Directory remove;1;0}}, queued...
+[1552902538.79][CONN][RXD] >>> 'Directory remove': 1 passed, 0 failed
+[1552902538.79][CONN][RXD]
+[1552902538.84][CONN][RXD] >>> Running case #10: 'Directory rename'...
+[1552902538.88][CONN][INF] found KV pair in stream: {{__testcase_start;Directory rename}}, queued...
+[1552902539.06][CONN][INF] found KV pair in stream: {{__testcase_finish;Directory rename;1;0}}, queued...
+[1552902539.11][CONN][RXD] >>> 'Directory rename': 1 passed, 0 failed
+[1552902539.11][CONN][RXD]
+[1552902539.15][CONN][RXD] >>> Test cases: 10 passed, 0 failed
+[1552902539.18][CONN][INF] found KV pair in stream: {{__testcase_summary;10;0}}, queued...
+[1552902539.19][CONN][INF] found KV pair in stream: {{end;success}}, queued...
+[1552902539.20][HTST][INF] __notify_complete(True)
+[1552902539.20][HTST][INF] __exit_event_queue received
+[1552902539.20][HTST][INF] test suite run finished after 5.60 sec...
+[1552902539.21][CONN][INF] found KV pair in stream: {{__exit;0}}, queued...
+[1552902539.21][CONN][INF] received special event '__host_test_finished' value='True', finishing
+[1552902539.22][HTST][INF] CONN exited with code: 0
+[1552902539.22][HTST][INF] Some events in queue
+[1552902539.22][HTST][INF] stopped consuming events
+[1552902539.22][HTST][INF] host test result() call skipped, received: True
+[1552902539.22][HTST][WRN] missing __exit event from DUT
+[1552902539.22][HTST][INF] calling blocking teardown()
+[1552902539.22][HTST][INF] teardown() finished
+[1552902539.22][HTST][INF] {{result;success}}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/SD_files(ARM).log Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,101 @@
+[1552902322.04][HTST][INF] host test executor ver. 0.0.1
+[1552902322.04][HTST][INF] copy image onto target... SKIPPED!
+[1552902322.04][HTST][INF] starting host test process...
+[1552902322.72][CONN][INF] starting connection process...
+[1552902322.72][CONN][INF] notify event queue about extra 60 sec timeout for serial port pooling
+[1552902322.72][CONN][INF] initializing serial port listener...
+[1552902322.72][SERI][INF] serial(port=COM27, baudrate=9600, read_timeout=0.01, write_timeout=5)
+[1552902322.72][SERI][TXD] mbedmbedmbedmbedmbedmbedmbedmbedmbedmbed
+[1552902322.73][CONN][INF] sending up to 2 __sync packets (specified with --sync=2)
+[1552902322.73][CONN][INF] sending preamble '14eb128e-b7f4-43fb-a6ba-f9ee48bbe45a'
+[1552902322.74][HTST][INF] setting timeout to: 60 sec
+[1552902322.77][SERI][TXD] {{__sync;14eb128e-b7f4-43fb-a6ba-f9ee48bbe45a}}
+[1552902322.86][CONN][RXD] mbedmbedmbedmbedmbedmbedmbedmbed
+[1552902322.90][CONN][INF] found SYNC in stream: {{__sync;14eb128e-b7f4-43fb-a6ba-f9ee48bbe45a}} it is #0 sent, queued...
+[1552902322.91][HTST][INF] sync KV found, uuid=14eb128e-b7f4-43fb-a6ba-f9ee48bbe45a, timestamp=1552902322.905000
+[1552902322.94][CONN][INF] found KV pair in stream: {{__version;1.3.0}}, queued...
+[1552902322.94][HTST][INF] DUT greentea-client version: 1.3.0
+[1552902322.95][CONN][INF] found KV pair in stream: {{__timeout;120}}, queued...
+[1552902322.95][HTST][INF] setting timeout to: 120 sec
+[1552902322.99][CONN][INF] found KV pair in stream: {{__host_test_name;default_auto}}, queued...
+[1552902322.99][HTST][INF] host test class: '<class 'mbed_os_tools.test.host_tests.default_auto.DefaultAuto'>'
+[1552902322.99][HTST][INF] host test setup() call...
+[1552902322.99][HTST][INF] CALLBACKs updated
+[1552902322.99][HTST][INF] host test detected: default_auto
+[1552902323.02][CONN][RXD] >>> Running 9 test cases...
+[1552902323.05][CONN][INF] found KV pair in stream: {{__testcase_name;File tests}}, queued...
+[1552902323.10][CONN][INF] found KV pair in stream: {{__testcase_name;Simple file test}}, queued...
+[1552902323.13][CONN][INF] found KV pair in stream: {{__testcase_name;Small file test}}, queued...
+[1552902323.17][CONN][INF] found KV pair in stream: {{__testcase_name;Medium file test}}, queued...
+[1552902323.21][CONN][INF] found KV pair in stream: {{__testcase_name;Large file test}}, queued...
+[1552902323.25][CONN][INF] found KV pair in stream: {{__testcase_name;Block Size file test}}, queued...
+[1552902323.30][CONN][INF] found KV pair in stream: {{__testcase_name;Multiple block size file test}}, queued...
+[1552902323.34][CONN][INF] found KV pair in stream: {{__testcase_name;Non-overlap check}}, queued...
+[1552902323.38][CONN][RXD]
+[1552902323.38][CONN][INF] found KV pair in stream: {{__testcase_name;Dir check}}, queued...
+[1552902323.42][CONN][RXD] >>> Running case #1: 'File tests'...
+[1552902323.45][CONN][INF] found KV pair in stream: {{__testcase_start;File tests}}, queued...
+[1552902323.57][CONN][RXD] init card = 1
+[1552902323.64][CONN][RXD] CSD is 40 0E 00 5A 5B 59 00 00 74 B7 7F 80 0A 40 00 00
+[1552902323.67][CONN][RXD] SDHC/SDXC Card: hc_c_size: 29879
+[1552902323.70][CONN][RXD] Sectors: 0x1d2e000 : 30597120
+[1552902323.72][CONN][RXD] Capacity: 14940 MB
+[1552902324.03][CONN][INF] found KV pair in stream: {{__testcase_finish;File tests;1;0}}, queued...
+[1552902324.07][CONN][RXD] >>> 'File tests': 1 passed, 0 failed
+[1552902324.07][CONN][RXD]
+[1552902324.11][CONN][RXD] >>> Running case #2: 'Simple file test'...
+[1552902324.15][CONN][INF] found KV pair in stream: {{__testcase_start;Simple file test}}, queued...
+[1552902324.20][CONN][INF] found KV pair in stream: {{__testcase_finish;Simple file test;1;0}}, queued...
+[1552902324.25][CONN][RXD] >>> 'Simple file test': 1 passed, 0 failed
+[1552902324.25][CONN][RXD]
+[1552902324.30][CONN][RXD] >>> Running case #3: 'Small file test'...
+[1552902324.34][CONN][INF] found KV pair in stream: {{__testcase_start;Small file test}}, queued...
+[1552902324.39][CONN][INF] found KV pair in stream: {{__testcase_finish;Small file test;1;0}}, queued...
+[1552902324.43][CONN][RXD] >>> 'Small file test': 1 passed, 0 failed
+[1552902324.43][CONN][RXD]
+[1552902324.48][CONN][RXD] >>> Running case #4: 'Medium file test'...
+[1552902324.52][CONN][INF] found KV pair in stream: {{__testcase_start;Medium file test}}, queued...
+[1552902324.62][CONN][INF] found KV pair in stream: {{__testcase_finish;Medium file test;1;0}}, queued...
+[1552902324.66][CONN][RXD] >>> 'Medium file test': 1 passed, 0 failed
+[1552902324.66][CONN][RXD]
+[1552902324.70][CONN][RXD] >>> Running case #5: 'Large file test'...
+[1552902324.75][CONN][INF] found KV pair in stream: {{__testcase_start;Large file test}}, queued...
+[1552902326.09][CONN][INF] found KV pair in stream: {{__testcase_finish;Large file test;1;0}}, queued...
+[1552902326.13][CONN][RXD] >>> 'Large file test': 1 passed, 0 failed
+[1552902326.13][CONN][RXD]
+[1552902326.19][CONN][RXD] >>> Running case #6: 'Block Size file test'...
+[1552902326.23][CONN][INF] found KV pair in stream: {{__testcase_start;Block Size file test}}, queued...
+[1552902326.35][CONN][INF] found KV pair in stream: {{__testcase_finish;Block Size file test;1;0}}, queued...
+[1552902326.40][CONN][RXD] >>> 'Block Size file test': 1 passed, 0 failed
+[1552902326.40][CONN][RXD]
+[1552902326.46][CONN][RXD] >>> Running case #7: 'Multiple block size file test'...
+[1552902326.52][CONN][INF] found KV pair in stream: {{__testcase_start;Multiple block size file test}}, queued...
+[1552902326.61][CONN][INF] found KV pair in stream: {{__testcase_finish;Multiple block size file test;1;0}}, queued...
+[1552902326.67][CONN][RXD] >>> 'Multiple block size file test': 1 passed, 0 failed
+[1552902326.67][CONN][RXD]
+[1552902326.72][CONN][RXD] >>> Running case #8: 'Non-overlap check'...
+[1552902326.76][CONN][INF] found KV pair in stream: {{__testcase_start;Non-overlap check}}, queued...
+[1552902327.10][CONN][INF] found KV pair in stream: {{__testcase_finish;Non-overlap check;1;0}}, queued...
+[1552902327.14][CONN][RXD] >>> 'Non-overlap check': 1 passed, 0 failed
+[1552902327.14][CONN][RXD]
+[1552902327.18][CONN][RXD] >>> Running case #9: 'Dir check'...
+[1552902327.21][CONN][INF] found KV pair in stream: {{__testcase_start;Dir check}}, queued...
+[1552902327.25][CONN][INF] found KV pair in stream: {{__testcase_finish;Dir check;1;0}}, queued...
+[1552902327.29][CONN][RXD] >>> 'Dir check': 1 passed, 0 failed
+[1552902327.29][CONN][RXD]
+[1552902327.33][CONN][RXD] >>> Test cases: 9 passed, 0 failed
+[1552902327.36][CONN][INF] found KV pair in stream: {{__testcase_summary;9;0}}, queued...
+[1552902327.37][CONN][INF] found KV pair in stream: {{end;success}}, queued...
+[1552902327.37][HTST][INF] __notify_complete(True)
+[1552902327.38][HTST][INF] __exit_event_queue received
+[1552902327.38][HTST][INF] test suite run finished after 4.43 sec...
+[1552902327.38][CONN][INF] received special event '__host_test_finished' value='True', finishing
+[1552902327.38][HTST][INF] CONN exited with code: 0
+[1552902327.38][HTST][INF] No events in queue
+[1552902327.38][HTST][INF] stopped consuming events
+[1552902327.38][HTST][INF] host test result() call skipped, received: True
+[1552902327.38][HTST][WRN] missing __exit event from DUT
+[1552902327.38][HTST][INF] calling blocking teardown()
+[1552902327.38][HTST][INF] teardown() finished
+[1552902327.38][HTST][INF] {{result;success}}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/SD_fopen(ARM).log Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,141 @@
+[1552903233.10][HTST][INF] host test executor ver. 0.0.1
+[1552903233.10][HTST][INF] copy image onto target... SKIPPED!
+[1552903233.11][HTST][INF] starting host test process...
+[1552903233.81][CONN][INF] starting connection process...
+[1552903233.81][CONN][INF] notify event queue about extra 60 sec timeout for serial port pooling
+[1552903233.81][CONN][INF] initializing serial port listener...
+[1552903233.81][SERI][INF] serial(port=COM27, baudrate=9600, read_timeout=0.01, write_timeout=5)
+[1552903233.82][SERI][TXD] mbedmbedmbedmbedmbedmbedmbedmbedmbedmbed
+[1552903233.82][CONN][INF] sending up to 2 __sync packets (specified with --sync=2)
+[1552903233.82][CONN][INF] sending preamble '5b118ab0-efab-4c9e-87f4-d4c32f818d65'
+[1552903233.82][HTST][INF] setting timeout to: 60 sec
+[1552903233.86][SERI][TXD] {{__sync;5b118ab0-efab-4c9e-87f4-d4c32f818d65}}
+[1552903233.92][CONN][RXD] nit card = 1
+[1552903233.95][CONN][RXD] CSD is 40 0E 00 5A 5B 59 00 00 74 B7 7F 80 0A 40 0mbedmbedmbedmbedmbedmbedmbedmbed
+[1552903234.00][CONN][INF] found SYNC in stream: {{__sync;5b118ab0-efab-4c9e-87f4-d4c32f818d65}} it is #0 sent, queued...
+[1552903234.00][HTST][INF] sync KV found, uuid=5b118ab0-efab-4c9e-87f4-d4c32f818d65, timestamp=1552903234.000000
+[1552903234.02][CONN][INF] found KV pair in stream: {{__version;1.3.0}}, queued...
+[1552903234.02][HTST][INF] DUT greentea-client version: 1.3.0
+[1552903234.04][CONN][INF] found KV pair in stream: {{__timeout;1000}}, queued...
+[1552903234.05][HTST][INF] setting timeout to: 1000 sec
+[1552903234.08][CONN][INF] found KV pair in stream: {{__host_test_name;default_auto}}, queued...
+[1552903234.08][HTST][INF] host test class: '<class 'mbed_os_tools.test.host_tests.default_auto.DefaultAuto'>'
+[1552903234.08][HTST][INF] host test setup() call...
+[1552903234.08][HTST][INF] CALLBACKs updated
+[1552903234.08][HTST][INF] host test detected: default_auto
+[1552903234.11][CONN][INF] found KV pair in stream: {{__testcase_count;16}}, queued...
+[1552903234.13][CONN][RXD] >>> Running 16 test cases...
+[1552903234.20][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_00: format sd card to FAT FS.}}, queued...
+[1552903234.32][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_01: fopen()/fwrite()/fclose() directories/file in multi-dir filepath.}}, queued...
+[1552903234.41][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_02: fopen(r) pre-existing file try to write it.}}, queued...
+[1552903234.49][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_03: fopen(w+) pre-existing file try to write it.}}, queued...
+[1552903234.60][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_04: fopen() with a filename exceeding the maximum length.}}, queued...
+[1552903234.68][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_06: fopen() with bad filenames (minimal).}}, queued...
+[1552903234.75][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_07: fopen()/errno handling.}}, queued...
+[1552903234.83][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_08: ferror()/clearerr()/errno handling.}}, queued...
+[1552903234.90][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_09: ftell() handling.}}, queued...
+[1552903234.95][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_10: remove() test.}}, queued...
+[1552903235.00][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_11: rename().}}, queued...
+[1552903235.10][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_12: opendir(), readdir(), closedir() test.}}, queued...
+[1552903235.15][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_13: mkdir() test.}}, queued...
+[1552903235.21][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_14: stat() test.}}, queued...
+[1552903235.27][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_15: format() test.}}, queued...
+[1552903235.35][CONN][RXD]
+[1552903235.35][CONN][INF] found KV pair in stream: {{__testcase_name;FSFAT_FOPEN_TEST_16: write/check n x 25kB data files.}}, queued...
+[1552903235.42][CONN][RXD] >>> Running case #1: 'FSFAT_FOPEN_TEST_00: format sd card to FAT FS.'...
+[1552903235.49][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_00: format sd card to FAT FS.}}, queued...
+[1552903235.86][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_00: format sd card to FAT FS.;1;0}}, queued...
+[1552903235.93][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_00: format sd card to FAT FS.': 1 passed, 0 failed
+[1552903235.93][CONN][RXD]
+[1552903236.05][CONN][RXD] >>> Running case #2: 'FSFAT_FOPEN_TEST_01: fopen()/fwrite()/fclose() directories/file in multi-dir filepath.'...
+[1552903236.16][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_01: fopen()/fwrite()/fclose() directories/file in multi-dir filepath.}}, queued...
+[1552903236.40][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_01: fopen()/fwrite()/fclose() directories/file in multi-dir filepath.;1;0}}, queued...
+[1552903236.51][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_01: fopen()/fwrite()/fclose() directories/file in multi-dir filepath.': 1 passed, 0 failed
+[1552903236.51][CONN][RXD]
+[1552903236.61][CONN][RXD] >>> Running case #3: 'FSFAT_FOPEN_TEST_02: fopen(r) pre-existing file try to write it.'...
+[1552903236.70][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_02: fopen(r) pre-existing file try to write it.}}, queued...
+[1552903236.80][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_02: fopen(r) pre-existing file try to write it.;1;0}}, queued...
+[1552903236.89][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_02: fopen(r) pre-existing file try to write it.': 1 passed, 0 failed
+[1552903236.90][CONN][RXD]
+[1552903237.00][CONN][RXD] >>> Running case #4: 'FSFAT_FOPEN_TEST_03: fopen(w+) pre-existing file try to write it.'...
+[1552903237.09][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_03: fopen(w+) pre-existing file try to write it.}}, queued...
+[1552903237.21][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_03: fopen(w+) pre-existing file try to write it.;1;0}}, queued...
+[1552903237.31][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_03: fopen(w+) pre-existing file try to write it.': 1 passed, 0 failed
+[1552903237.31][CONN][RXD]
+[1552903237.41][CONN][RXD] >>> Running case #5: 'FSFAT_FOPEN_TEST_04: fopen() with a filename exceeding the maximum length.'...
+[1552903237.52][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_04: fopen() with a filename exceeding the maximum length.}}, queued...
+[1552903237.62][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_04: fopen() with a filename exceeding the maximum length.;1;0}}, queued...
+[1552903237.73][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_04: fopen() with a filename exceeding the maximum length.': 1 passed, 0 failed
+[1552903237.73][CONN][RXD]
+[1552903237.81][CONN][RXD] >>> Running case #6: 'FSFAT_FOPEN_TEST_06: fopen() with bad filenames (minimal).'...
+[1552903237.89][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_06: fopen() with bad filenames (minimal).}}, queued...
+[1552903237.99][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_06: fopen() with bad filenames (minimal).;1;0}}, queued...
+[1552903238.08][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_06: fopen() with bad filenames (minimal).': 1 passed, 0 failed
+[1552903238.08][CONN][RXD]
+[1552903238.15][CONN][RXD] >>> Running case #7: 'FSFAT_FOPEN_TEST_07: fopen()/errno handling.'...
+[1552903238.22][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_07: fopen()/errno handling.}}, queued...
+[1552903238.30][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_07: fopen()/errno handling.;1;0}}, queued...
+[1552903238.37][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_07: fopen()/errno handling.': 1 passed, 0 failed
+[1552903238.37][CONN][RXD]
+[1552903238.46][CONN][RXD] >>> Running case #8: 'FSFAT_FOPEN_TEST_08: ferror()/clearerr()/errno handling.'...
+[1552903238.54][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_08: ferror()/clearerr()/errno handling.}}, queued...
+[1552903238.62][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_08: ferror()/clearerr()/errno handling.;1;0}}, queued...
+[1552903238.72][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_08: ferror()/clearerr()/errno handling.': 1 passed, 0 failed
+[1552903238.72][CONN][RXD]
+[1552903238.78][CONN][RXD] >>> Running case #9: 'FSFAT_FOPEN_TEST_09: ftell() handling.'...
+[1552903238.84][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_09: ftell() handling.}}, queued...
+[1552903238.92][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_09: ftell() handling.;1;0}}, queued...
+[1552903238.99][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_09: ftell() handling.': 1 passed, 0 failed
+[1552903238.99][CONN][RXD]
+[1552903239.05][CONN][RXD] >>> Running case #10: 'FSFAT_FOPEN_TEST_10: remove() test.'...
+[1552903239.12][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_10: remove() test.}}, queued...
+[1552903239.22][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_10: remove() test.;1;0}}, queued...
+[1552903239.28][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_10: remove() test.': 1 passed, 0 failed
+[1552903239.28][CONN][RXD]
+[1552903239.35][CONN][RXD] >>> Running case #11: 'FSFAT_FOPEN_TEST_11: rename().'...
+[1552903239.40][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_11: rename().}}, queued...
+[1552903239.50][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_11: rename().;1;0}}, queued...
+[1552903239.56][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_11: rename().': 1 passed, 0 failed
+[1552903239.56][CONN][RXD]
+[1552903239.64][CONN][RXD] >>> Running case #12: 'FSFAT_FOPEN_TEST_12: opendir(), readdir(), closedir() test.'...
+[1552903239.73][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_12: opendir(), readdir(), closedir() test.}}, queued...
+[1552903239.82][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_12: opendir(), readdir(), closedir() test.;1;0}}, queued...
+[1552903239.92][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_12: opendir(), readdir(), closedir() test.': 1 passed, 0 failed
+[1552903239.92][CONN][RXD]
+[1552903239.98][CONN][RXD] >>> Running case #13: 'FSFAT_FOPEN_TEST_13: mkdir() test.'...
+[1552903240.04][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_13: mkdir() test.}}, queued...
+[1552903240.26][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_13: mkdir() test.;1;0}}, queued...
+[1552903240.33][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_13: mkdir() test.': 1 passed, 0 failed
+[1552903240.33][CONN][RXD]
+[1552903240.39][CONN][RXD] >>> Running case #14: 'FSFAT_FOPEN_TEST_14: stat() test.'...
+[1552903240.45][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_14: stat() test.}}, queued...
+[1552903240.52][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_14: stat() test.;1;0}}, queued...
+[1552903240.58][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_14: stat() test.': 1 passed, 0 failed
+[1552903240.58][CONN][RXD]
+[1552903240.64][CONN][RXD] >>> Running case #15: 'FSFAT_FOPEN_TEST_15: format() test.'...
+[1552903240.70][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_15: format() test.}}, queued...
+[1552903241.00][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_15: format() test.;1;0}}, queued...
+[1552903241.07][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_15: format() test.': 1 passed, 0 failed
+[1552903241.07][CONN][RXD]
+[1552903241.15][CONN][RXD] >>> Running case #16: 'FSFAT_FOPEN_TEST_16: write/check n x 25kB data files.'...
+[1552903241.23][CONN][INF] found KV pair in stream: {{__testcase_start;FSFAT_FOPEN_TEST_16: write/check n x 25kB data files.}}, queued...
+[1552903245.07][CONN][INF] found KV pair in stream: {{__testcase_finish;FSFAT_FOPEN_TEST_16: write/check n x 25kB data files.;1;0}}, queued...
+[1552903245.15][CONN][RXD] >>> 'FSFAT_FOPEN_TEST_16: write/check n x 25kB data files.': 1 passed, 0 failed
+[1552903245.15][CONN][RXD]
+[1552903245.19][CONN][RXD] >>> Test cases: 16 passed, 0 failed
+[1552903245.22][CONN][INF] found KV pair in stream: {{__testcase_summary;16;0}}, queued...
+[1552903245.25][CONN][INF] found KV pair in stream: {{end;success}}, queued...
+[1552903245.25][HTST][INF] __notify_complete(True)
+[1552903245.26][HTST][INF] __exit_event_queue received
+[1552903245.26][HTST][INF] test suite run finished after 11.20 sec...
+[1552903245.26][CONN][INF] found KV pair in stream: {{__exit;0}}, queued...
+[1552903245.26][CONN][INF] received special event '__host_test_finished' value='True', finishing
+[1552903245.27][HTST][INF] CONN exited with code: 0
+[1552903245.27][HTST][INF] Some events in queue
+[1552903245.27][HTST][INF] stopped consuming events
+[1552903245.27][HTST][INF] host test result() call skipped, received: True
+[1552903245.27][HTST][WRN] missing __exit event from DUT
+[1552903245.27][HTST][INF] calling blocking teardown()
+[1552903245.27][HTST][INF] teardown() finished
+[1552903245.27][HTST][INF] {{result;success}}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/SD_paralel(ARM).log Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,60 @@
+[1552903415.89][HTST][INF] host test executor ver. 0.0.1
+[1552903415.90][HTST][INF] copy image onto target... SKIPPED!
+[1552903415.91][HTST][INF] starting host test process...
+[1552903416.68][CONN][INF] starting connection process...
+[1552903416.68][CONN][INF] notify event queue about extra 60 sec timeout for serial port pooling
+[1552903416.68][CONN][INF] initializing serial port listener...
+[1552903416.68][SERI][INF] serial(port=COM27, baudrate=9600, read_timeout=0.01, write_timeout=5)
+[1552903416.68][SERI][TXD] mbedmbedmbedmbedmbedmbedmbedmbedmbedmbed
+[1552903416.68][CONN][INF] sending up to 2 __sync packets (specified with --sync=2)
+[1552903416.68][CONN][INF] sending preamble 'a16d2d32-d657-4722-a025-ced87722193e'
+[1552903416.69][HTST][INF] setting timeout to: 60 sec
+[1552903416.73][SERI][TXD] {{__sync;a16d2d32-d657-4722-a025-ced87722193e}}
+[1552903416.82][CONN][RXD] mbedmbedmbedmbedmbedmbedmbedmbed
+[1552903416.87][CONN][INF] found SYNC in stream: {{__sync;a16d2d32-d657-4722-a025-ced87722193e}} it is #0 sent, queued...
+[1552903416.88][HTST][INF] sync KV found, uuid=a16d2d32-d657-4722-a025-ced87722193e, timestamp=1552903416.870000
+[1552903416.89][CONN][INF] found KV pair in stream: {{__version;1.3.0}}, queued...
+[1552903416.90][HTST][INF] DUT greentea-client version: 1.3.0
+[1552903416.91][CONN][INF] found KV pair in stream: {{__timeout;120}}, queued...
+[1552903416.91][HTST][INF] setting timeout to: 120 sec
+[1552903416.94][CONN][INF] found KV pair in stream: {{__host_test_name;default_auto}}, queued...
+[1552903416.95][HTST][INF] host test class: '<class 'mbed_os_tools.test.host_tests.default_auto.DefaultAuto'>'
+[1552903416.95][HTST][INF] host test setup() call...
+[1552903416.95][HTST][INF] CALLBACKs updated
+[1552903416.95][HTST][INF] host test detected: default_auto
+[1552903416.98][CONN][RXD] >>> Running 2 test cases...
+[1552903417.01][CONN][INF] found KV pair in stream: {{__testcase_name;File tests}}, queued...
+[1552903417.07][CONN][RXD]
+[1552903417.07][CONN][INF] found KV pair in stream: {{__testcase_name;Filesystem access from multiple threads}}, queued...
+[1552903417.11][CONN][RXD] >>> Running case #1: 'File tests'...
+[1552903417.14][CONN][INF] found KV pair in stream: {{__testcase_start;File tests}}, queued...
+[1552903417.27][CONN][RXD] init card = 1
+[1552903417.33][CONN][RXD] CSD is 40 0E 00 5A 5B 59 00 00 74 B7 7F 80 0A 40 00 00
+[1552903417.37][CONN][RXD] SDHC/SDXC Card: hc_c_size: 29879
+[1552903417.40][CONN][RXD] Sectors: 0x1d2e000 : 30597120
+[1552903417.42][CONN][RXD] Capacity: 14940 MB
+[1552903417.85][CONN][INF] found KV pair in stream: {{__testcase_finish;File tests;1;0}}, queued...
+[1552903417.88][CONN][RXD] >>> 'File tests': 1 passed, 0 failed
+[1552903417.89][CONN][RXD]
+[1552903417.95][CONN][RXD] >>> Running case #2: 'Filesystem access from multiple threads'...
+[1552903418.02][CONN][INF] found KV pair in stream: {{__testcase_start;Filesystem access from multiple threads}}, queued...
+[1552903418.17][CONN][INF] found KV pair in stream: {{__testcase_finish;Filesystem access from multiple threads;1;0}}, queued...
+[1552903418.25][CONN][RXD] >>> 'Filesystem access from multiple threads': 1 passed, 0 failed
+[1552903418.25][CONN][RXD]
+[1552903418.28][CONN][RXD] >>> Test cases: 2 passed, 0 failed
+[1552903418.31][CONN][INF] found KV pair in stream: {{__testcase_summary;2;0}}, queued...
+[1552903418.33][CONN][INF] found KV pair in stream: {{end;success}}, queued...
+[1552903418.34][HTST][INF] __notify_complete(True)
+[1552903418.35][HTST][INF] __exit_event_queue received
+[1552903418.35][HTST][INF] test suite run finished after 1.43 sec...
+[1552903418.35][CONN][INF] found KV pair in stream: {{__exit;0}}, queued...
+[1552903418.36][CONN][INF] received special event '__host_test_finished' value='True', finishing
+[1552903418.36][HTST][INF] CONN exited with code: 0
+[1552903418.36][HTST][INF] Some events in queue
+[1552903418.36][HTST][INF] stopped consuming events
+[1552903418.36][HTST][INF] host test result() call skipped, received: True
+[1552903418.36][HTST][WRN] missing __exit event from DUT
+[1552903418.36][HTST][INF] calling blocking teardown()
+[1552903418.36][HTST][INF] teardown() finished
+[1552903418.36][HTST][INF] {{result;success}}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/SD_seek(ARM).log Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,102 @@
+[1552903540.93][HTST][INF] host test executor ver. 0.0.1
+[1552903540.93][HTST][INF] copy image onto target... SKIPPED!
+[1552903540.94][HTST][INF] starting host test process...
+[1552903541.65][CONN][INF] starting connection process...
+[1552903541.65][CONN][INF] notify event queue about extra 60 sec timeout for serial port pooling
+[1552903541.65][CONN][INF] initializing serial port listener...
+[1552903541.65][SERI][INF] serial(port=COM27, baudrate=9600, read_timeout=0.01, write_timeout=5)
+[1552903541.66][SERI][TXD] mbedmbedmbedmbedmbedmbedmbedmbedmbedmbed
+[1552903541.66][CONN][INF] sending up to 2 __sync packets (specified with --sync=2)
+[1552903541.66][CONN][INF] sending preamble '6346031d-5e4a-470b-b3a1-567ed5d74623'
+[1552903541.67][HTST][INF] setting timeout to: 60 sec
+[1552903541.70][SERI][TXD] {{__sync;6346031d-5e4a-470b-b3a1-567ed5d74623}}
+[1552903541.79][CONN][RXD] mbedmbedmbedmbedmbedmbedmbedmbed
+[1552903541.85][CONN][INF] found SYNC in stream: {{__sync;6346031d-5e4a-470b-b3a1-567ed5d74623}} it is #0 sent, queued...
+[1552903541.85][HTST][INF] sync KV found, uuid=6346031d-5e4a-470b-b3a1-567ed5d74623, timestamp=1552903541.846000
+[1552903541.87][CONN][INF] found KV pair in stream: {{__version;1.3.0}}, queued...
+[1552903541.87][HTST][INF] DUT greentea-client version: 1.3.0
+[1552903541.89][CONN][INF] found KV pair in stream: {{__timeout;120}}, queued...
+[1552903541.89][HTST][INF] setting timeout to: 120 sec
+[1552903541.92][CONN][INF] found KV pair in stream: {{__host_test_name;default_auto}}, queued...
+[1552903541.93][HTST][INF] host test class: '<class 'mbed_os_tools.test.host_tests.default_auto.DefaultAuto'>'
+[1552903541.93][HTST][INF] host test setup() call...
+[1552903541.93][HTST][INF] CALLBACKs updated
+[1552903541.93][HTST][INF] host test detected: default_auto
+[1552903541.95][CONN][RXD] >>> Running 9 test cases...
+[1552903541.98][CONN][INF] found KV pair in stream: {{__testcase_name;Seek tests}}, queued...
+[1552903542.03][CONN][INF] found KV pair in stream: {{__testcase_name;Simple dir seek}}, queued...
+[1552903542.06][CONN][INF] found KV pair in stream: {{__testcase_name;Large dir seek}}, queued...
+[1552903542.10][CONN][INF] found KV pair in stream: {{__testcase_name;Simple file seek}}, queued...
+[1552903542.14][CONN][INF] found KV pair in stream: {{__testcase_name;Large file seek}}, queued...
+[1552903542.18][CONN][INF] found KV pair in stream: {{__testcase_name;Simple file seek and write}}, queued...
+[1552903542.24][CONN][INF] found KV pair in stream: {{__testcase_name;Large file seek and write}}, queued...
+[1552903542.28][CONN][INF] found KV pair in stream: {{__testcase_name;Boundary seek and write}}, queued...
+[1552903542.32][CONN][RXD]
+[1552903542.32][CONN][INF] found KV pair in stream: {{__testcase_name;Out-of-bounds seek}}, queued...
+[1552903542.36][CONN][RXD] >>> Running case #1: 'Seek tests'...
+[1552903542.39][CONN][INF] found KV pair in stream: {{__testcase_start;Seek tests}}, queued...
+[1552903542.53][CONN][RXD] init card = 1
+[1552903542.58][CONN][RXD] CSD is 40 0E 00 5A 5B 59 00 00 74 B7 7F 80 0A 40 00 00
+[1552903542.62][CONN][RXD] SDHC/SDXC Card: hc_c_size: 29879
+[1552903542.65][CONN][RXD] Sectors: 0x1d2e000 : 30597120
+[1552903542.67][CONN][RXD] Capacity: 14940 MB
+[1552903545.45][CONN][INF] found KV pair in stream: {{__testcase_finish;Seek tests;1;0}}, queued...
+[1552903545.48][CONN][RXD] >>> 'Seek tests': 1 passed, 0 failed
+[1552903545.48][CONN][RXD]
+[1552903545.53][CONN][RXD] >>> Running case #2: 'Simple dir seek'...
+[1552903545.57][CONN][INF] found KV pair in stream: {{__testcase_start;Simple dir seek}}, queued...
+[1552903545.62][CONN][INF] found KV pair in stream: {{__testcase_finish;Simple dir seek;1;0}}, queued...
+[1552903545.66][CONN][RXD] >>> 'Simple dir seek': 1 passed, 0 failed
+[1552903545.66][CONN][RXD]
+[1552903545.70][CONN][RXD] >>> Running case #3: 'Large dir seek'...
+[1552903545.75][CONN][INF] found KV pair in stream: {{__testcase_start;Large dir seek}}, queued...
+[1552903545.80][CONN][INF] found KV pair in stream: {{__testcase_finish;Large dir seek;1;0}}, queued...
+[1552903545.84][CONN][RXD] >>> 'Large dir seek': 1 passed, 0 failed
+[1552903545.84][CONN][RXD]
+[1552903545.88][CONN][RXD] >>> Running case #4: 'Simple file seek'...
+[1552903545.93][CONN][INF] found KV pair in stream: {{__testcase_start;Simple file seek}}, queued...
+[1552903545.97][CONN][INF] found KV pair in stream: {{__testcase_finish;Simple file seek;1;0}}, queued...
+[1552903546.01][CONN][RXD] >>> 'Simple file seek': 1 passed, 0 failed
+[1552903546.02][CONN][RXD]
+[1552903546.07][CONN][RXD] >>> Running case #5: 'Large file seek'...
+[1552903546.10][CONN][INF] found KV pair in stream: {{__testcase_start;Large file seek}}, queued...
+[1552903546.15][CONN][INF] found KV pair in stream: {{__testcase_finish;Large file seek;1;0}}, queued...
+[1552903546.19][CONN][RXD] >>> 'Large file seek': 1 passed, 0 failed
+[1552903546.19][CONN][RXD]
+[1552903546.24][CONN][RXD] >>> Running case #6: 'Simple file seek and write'...
+[1552903546.30][CONN][INF] found KV pair in stream: {{__testcase_start;Simple file seek and write}}, queued...
+[1552903546.36][CONN][INF] found KV pair in stream: {{__testcase_finish;Simple file seek and write;1;0}}, queued...
+[1552903546.42][CONN][RXD] >>> 'Simple file seek and write': 1 passed, 0 failed
+[1552903546.42][CONN][RXD]
+[1552903546.47][CONN][RXD] >>> Running case #7: 'Large file seek and write'...
+[1552903546.52][CONN][INF] found KV pair in stream: {{__testcase_start;Large file seek and write}}, queued...
+[1552903546.59][CONN][INF] found KV pair in stream: {{__testcase_finish;Large file seek and write;1;0}}, queued...
+[1552903546.64][CONN][RXD] >>> 'Large file seek and write': 1 passed, 0 failed
+[1552903546.64][CONN][RXD]
+[1552903546.69][CONN][RXD] >>> Running case #8: 'Boundary seek and write'...
+[1552903546.73][CONN][INF] found KV pair in stream: {{__testcase_start;Boundary seek and write}}, queued...
+[1552903546.83][CONN][INF] found KV pair in stream: {{__testcase_finish;Boundary seek and write;1;0}}, queued...
+[1552903546.88][CONN][RXD] >>> 'Boundary seek and write': 1 passed, 0 failed
+[1552903546.88][CONN][RXD]
+[1552903546.93][CONN][RXD] >>> Running case #9: 'Out-of-bounds seek'...
+[1552903546.98][CONN][INF] found KV pair in stream: {{__testcase_start;Out-of-bounds seek}}, queued...
+[1552903547.03][CONN][INF] found KV pair in stream: {{__testcase_finish;Out-of-bounds seek;1;0}}, queued...
+[1552903547.07][CONN][RXD] >>> 'Out-of-bounds seek': 1 passed, 0 failed
+[1552903547.07][CONN][RXD]
+[1552903547.12][CONN][RXD] >>> Test cases: 9 passed, 0 failed
+[1552903547.14][CONN][INF] found KV pair in stream: {{__testcase_summary;9;0}}, queued...
+[1552903547.16][CONN][INF] found KV pair in stream: {{end;success}}, queued...
+[1552903547.16][HTST][INF] __notify_complete(True)
+[1552903547.16][HTST][INF] __exit_event_queue received
+[1552903547.16][HTST][INF] test suite run finished after 5.27 sec...
+[1552903547.17][CONN][INF] found KV pair in stream: {{__exit;0}}, queued...
+[1552903547.17][CONN][INF] received special event '__host_test_finished' value='True', finishing
+[1552903547.18][HTST][INF] CONN exited with code: 0
+[1552903547.18][HTST][INF] Some events in queue
+[1552903547.18][HTST][INF] stopped consuming events
+[1552903547.18][HTST][INF] host test result() call skipped, received: True
+[1552903547.18][HTST][WRN] missing __exit event from DUT
+[1552903547.18][HTST][INF] calling blocking teardown()
+[1552903547.18][HTST][INF] teardown() finished
+[1552903547.18][HTST][INF] {{result;success}}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/components/storage/blockdevice/COMPONENT_RZ_SDHI/RZ_SDHIBlockDevice.cpp Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,635 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "RZ_SDHIBlockDevice.hpp"
+#include "mbed_debug.h"
+#include <errno.h>
+
+#include "iodefine.h"
+#include "PeripheralPins.h"
+
+/* Required version: 5.6.1 and above */
+#ifdef MBED_MAJOR_VERSION
+#if (MBED_VERSION < MBED_ENCODE_VERSION(5,6,1))
+#error "Incompatible mbed-os version detected! Required 5.5.4 and above"
+#endif
+#else
+#warning "mbed-os version 5.6.1 or above required"
+#endif
+
+
+
+//#define SD_COMMAND_TIMEOUT 5000 /*!< Timeout in ms for response */
+//#define SD_CMD0_GO_IDLE_STATE_RETRIES 5 /*!< Number of retries for sending CMDO */
+#define SD_CMD_TRACE 0 /*!< 1 - Enable SD command tracing */
+
+//#define SD_BLOCK_DEVICE_ERROR_WOULD_BLOCK -5001 /*!< operation would block */
+#define SD_BLOCK_DEVICE_ERROR_UNSUPPORTED -5002 /*!< unsupported operation */
+#define SD_BLOCK_DEVICE_ERROR_PARAMETER -5003 /*!< invalid parameter */
+#define SD_BLOCK_DEVICE_ERROR_NO_INIT -5004 /*!< uninitialized */
+#define SD_BLOCK_DEVICE_ERROR_NO_DEVICE -5005 /*!< device is missing or not connected */
+#define SD_BLOCK_DEVICE_ERROR_WRITE_PROTECTED -5006 /*!< write protected */
+#define SD_BLOCK_DEVICE_ERROR_UNUSABLE -5007 /*!< unusable card */
+#define SD_BLOCK_DEVICE_ERROR_NO_RESPONSE -5008 /*!< No response from device */
+#define SD_BLOCK_DEVICE_ERROR_CRC -5009 /*!< CRC error */
+#define SD_BLOCK_DEVICE_ERROR_ERASE -5010 /*!< Erase error: reset/sequence */
+#define SD_BLOCK_DEVICE_ERROR_WRITE -5011 /*!< SPI Write error: !SPI_DATA_ACCEPTED */
+
+#define BLOCK_SIZE_HC 512 /*!< Block size supported for SD card is 512 bytes */
+#define WRITE_BL_PARTIAL 0 /*!< Partial block write - Not supported */
+//
+// Types
+#define SDCARD_NONE 0 /**< No card is present */
+#define SDCARD_V1 1 /**< v1.x Standard Capacity */
+#define SDCARD_V2 2 /**< v2.x Standard capacity SD card */
+#define SDCARD_V2HC 3 /**< v2.x High capacity SD card */
+#define CARD_UNKNOWN 4 /**< Unknown or unsupported card */
+
+/* R3 Response : OCR Register */
+#define OCR_HCS_CCS (0x1 << 30)
+#define OCR_LOW_VOLTAGE (0x01 << 24)
+#define OCR_3_3V (0x1 << 20)
+
+#define ESD_SECTOR_SIZE BLOCK_SIZE_HC
+
+#define REG_CSD_HACK
+
+#define CSD_CID_LENGTH 16
+
+#define ARRAYSIZE(arr) (size_t)(sizeof(arr)/sizeof(arr[0]))
+
+static uint32_t _sd_workbuf[SD_SIZE_OF_INIT/ sizeof(uint32_t)] __attribute__ ((section ("NC_BSS")));
+static uint32_t _sd_rw_buf[ESD_SECTOR_SIZE/sizeof(uint32_t)] __attribute__ ((section ("NC_BSS")));
+//static uint8_t _sectorBuff[ESD_SECTOR_SIZE] __attribute__ ((section ("NC_BSS")));
+
+
+static uint32_t ext_bits(unsigned char *data, size_t datasize, unsigned int msb, unsigned int lsb) {
+ uint32_t bits = 0;
+
+ if ((datasize > 0) && (msb < (datasize<<3)))
+ {
+ uint32_t size = 1 + msb - lsb;
+ for (uint32_t i = 0; i < size; i++)
+ {
+ uint32_t position = lsb + i;
+ int32_t byte = (datasize-1) - (position >> 3);
+ if( byte < 0 )
+ break;
+ uint32_t bit = position & 0x7;
+ uint32_t value = (data[byte] >> bit) & 1;
+ bits |= value << i;
+ }
+ }
+ return bits;
+}
+
+#if SDHI_DBG
+const sderr_t SDHIBlockDevice::_sd_error_msg[]= {
+ {"SD_OK", 0}, /* OK */
+ {"SD_ERR", -1}, /* general error */
+ {"SD_ERR_WP", -2}, /* write protect error */
+ {"SD_ERR_RO", -3}, /* read only error */
+ {"SD_ERR_RES_TOE", -4}, /* response time out error */
+ {"SD_ERR_CARD_TOE", -5}, /* card time out error */
+ {"SD_ERR_END_BIT", -6}, /* end bit error */
+ {"SD_ERR_CRC", -7}, /* CRC error */
+ {"SD_ERR_CARD_RES", -8}, /* card response error */
+ {"SD_ERR_HOST_TOE", -9}, /* host time out error */
+ {"SD_ERR_CARD_ERASE", -10}, /* card erase error */
+ {"SD_ERR_CARD_LOCK", -11}, /* card lock error */
+ {"SD_ERR_CARD_UNLOCK", -12}, /* card unlock error */
+ {"SD_ERR_HOST_CRC", -13}, /* host CRC error */
+ {"SD_ERR_CARD_ECC", -14}, /* card internal ECC error */
+ {"SD_ERR_CARD_CC", -15}, /* card internal error */
+ {"SD_ERR_CARD_ERROR", -16}, /* unknown card error */
+ {"SD_ERR_CARD_TYPE", -17}, /* non support card type */
+ {"SD_ERR_NO_CARD", -18}, /* no card */
+ {"SD_ERR_ILL_READ", -19}, /* illegal buffer read */
+ {"SD_ERR_ILL_WRITE", -20}, /* illegal buffer write */
+ {"SD_ERR_AKE_SEQ", -21}, /* the sequence of authentication process */
+ {"SD_ERR_OVERWRITE", -22}, /* CID/CSD overwrite error */
+ /* 23-29 */
+ {"SD_ERR_CPU_IF", -30}, /* target CPU interface function error */
+ {"SD_ERR_STOP", -31}, /* user stop */
+ /* 32-49 */
+ {"SD_ERR_CSD_VER", -50}, /* CSD register version error */
+ {"SD_ERR_SCR_VER", -51}, /* SCR register version error */
+ {"SD_ERR_FILE_FORMAT", -52}, /* CSD register file format error */
+ {"SD_ERR_NOTSUP_CMD", -53}, /* not supported command */
+ /* 54-59 */
+ {"SD_ERR_ILL_FUNC", -60}, /* invalid function request error */
+ {"SD_ERR_IO_VERIFY", -61}, /* direct write verify error */
+ {"SD_ERR_IO_CAPAB", -62}, /* IO capability error */
+ /* 63-69 */
+ {"SD_ERR_IFCOND_VER", -70}, /* Interface condition version error */
+ {"SD_ERR_IFCOND_VOLT", -71}, /* Interface condition voltage error */
+ {"SD_ERR_IFCOND_ECHO", -72}, /* Interface condition echo back pattern error */
+ /* 73-79 */
+ {"SD_ERR_OUT_OF_RANGE", -80}, /* the argument was out of range */
+ {"SD_ERR_ADDRESS_ERROR", -81},
+ {"SD_ERR_BLOCK_LEN_ERROR", -82},
+ {"SD_ERR_ILLEGAL_COMMAND", -83},
+ {"SD_ERR_RESERVED_ERROR18", -84},
+ {"SD_ERR_RESERVED_ERROR17", -85},
+ {"SD_ERR_CMD_ERROR", -86},
+ {"SD_ERR_CBSY_ERROR", -87},
+ {"SD_ERR_NO_RESP_ERROR", -88},
+ /* 89 */
+ /* 90-95 */
+ {"SD_ERR_ERROR", -96},
+ {"SD_ERR_FUNCTION_NUMBER", -97},
+ {"SD_ERR_COM_CRC_ERROR", -98},
+ {"SD_ERR_INTERNAL", -99}, /* driver software internal error */
+};
+
+#endif
+
+SDHIBlockDevice::SDHIBlockDevice(uint32_t sdport)
+{
+ _init_ref_count = 0;
+ Initialize(sdport);
+// for( uint32_t n=0; n < ARRAYSIZE(_sd_error_msg); n++ )
+// {
+// _sd_err_map[_sd_error_msg[n].errorno] = _sd_error_msg[n].msg;
+// }
+//
+// if ( sdport < SDHI_COUNT )
+// {
+// _sd_channel = sdport;
+// _regbase = (uint32_t)((_sd_channel == 0ul) ? &SDHI0 : &SDHI1);
+//
+// _card_type = SDCARD_NONE;
+//
+// // Set default to 100kHz for initialisation and 1MHz for data transfer
+// _init_sck = 100000;
+// _transfer_sck = hz;
+//
+// // Only HC block size is supported.
+// _block_size = BLOCK_SIZE_HC;
+// _erase_size = BLOCK_SIZE_HC;
+// _mtx_lock = false;
+//
+// int32_t sd_err = sd_init( _sd_channel, _regbase, &_sd_workbuf[0], SD_CD_SOCKET );
+// if ( sd_err != SD_OK)
+// {
+// _error(sd_err);
+//// return SD_BLOCK_DEVICE_ERROR_NO_DEVICE;
+// }
+//
+// void *rw_buff = (void *)&_sd_rw_buf[0];
+//
+// sd_err = sd_set_buffer( _sd_channel, rw_buff, (unsigned long)sizeof(_sd_rw_buf) );
+// if ( sd_err != SD_OK )
+// {
+// _error(sd_err);
+// }
+//
+// }
+// else
+// {
+// _sd_channel = -1;
+// _regbase = 0ul;
+//
+// }
+}
+
+SDHIBlockDevice::SDHIBlockDevice(PinName sd_CLK, PinName sd_CMD, PinName sd_CD, PinName sd_WP,
+ PinName sd_D0, PinName sd_D1, PinName sd_D2, PinName sd_D3 )
+{
+ _init_ref_count = 0;
+
+ uint32_t sd_wp = pinmap_peripheral(sd_WP, PinMap_SDHI_WP);
+ uint32_t sd_cd = pinmap_peripheral(sd_CD, PinMap_SDHI_CD);
+ uint32_t sd_clk = pinmap_peripheral(sd_CLK, PinMap_SDHI_CLK);
+ uint32_t sd_cmd = pinmap_peripheral(sd_CMD, PinMap_SDHI_CMD);
+ uint32_t sd_d0 = pinmap_peripheral(sd_D0, PinMap_SDHI_D0);
+ uint32_t sd_d1 = pinmap_peripheral(sd_D1, PinMap_SDHI_D1);
+ uint32_t sd_d2 = pinmap_peripheral(sd_D2, PinMap_SDHI_D2);
+ uint32_t sd_d3 = pinmap_peripheral(sd_D3, PinMap_SDHI_D3);
+
+ uint32_t sd_cntl_1 = pinmap_merge(sd_wp, sd_cd);
+ uint32_t sd_cntl_2 = pinmap_merge(sd_clk, sd_cmd);
+ uint32_t sd_cntl = pinmap_merge(sd_cntl_1, sd_cntl_2);
+
+ uint32_t sd_data_1 = pinmap_merge(sd_d0, sd_d1);
+ uint32_t sd_data_2 = pinmap_merge(sd_d2, sd_d3);
+ uint32_t sd_data = pinmap_merge(sd_data_1, sd_data_2);
+
+ uint32_t sdport = pinmap_merge(sd_cntl, sd_data);
+
+ MBED_ASSERT((int)sdport != NC);
+
+ Initialize(sdport);
+}
+
+
+
+SDHIBlockDevice::~SDHIBlockDevice()
+{
+ if (_is_initialized) {
+ deinit();
+ }
+}
+
+void SDHIBlockDevice::Initialize( uint32_t sdport )
+{
+#if SDHI_DBG
+ for( uint32_t n=0; n < ARRAYSIZE(_sd_error_msg); n++ )
+ {
+ _sd_err_map[_sd_error_msg[n].errorno] = _sd_error_msg[n].msg;
+ }
+#endif
+ _sectors = 0;
+ _is_initialized = 0;
+ if ( sdport < SDHI_COUNT )
+ {
+ _sd_channel = sdport;
+ _regbase = (uint32_t)((_sd_channel == SDHI_0) ? &SDHI0 : &SDHI1);
+
+ _card_type = SDCARD_NONE;
+
+ // Only HC block size is supported.
+ _block_size = BLOCK_SIZE_HC;
+ _erase_size = BLOCK_SIZE_HC;
+
+ int32_t sd_err = sd_init( _sd_channel, _regbase, &_sd_workbuf[0], SD_CD_SOCKET );
+ if ( sd_err != SD_OK)
+ {
+ _error(sd_err);
+ }
+
+ void *rw_buff = (void *)&_sd_rw_buf[0];
+
+ sd_err = sd_set_buffer( _sd_channel, rw_buff, (unsigned long)sizeof(_sd_rw_buf) );
+ if ( sd_err != SD_OK )
+ {
+ _error(sd_err);
+ }
+ }
+ else
+ {
+ _sd_channel = -1;
+ _regbase = 0ul;
+
+ }
+
+}
+
+int SDHIBlockDevice::_initialise_card()
+{
+ // Detail debugging is for commands
+ _dbg = SDHI_DBG ? SD_CMD_TRACE : 0;
+
+ int32_t status = BD_ERROR_OK;
+
+ int32_t sd_err;
+
+ if( _regbase )
+ {
+ sd_err = sd_mount(_sd_channel, SDCFG_DRIVER_MODE, SD_VOLT_3_3);
+
+ if ( sd_err != SD_OK )
+ {
+ _error(sd_err);
+ return SD_BLOCK_DEVICE_ERROR_UNUSABLE;
+ }
+ uint8_t card_type;
+ uint8_t card_speed;
+ uint8_t card_capa;
+
+ sd_err=sd_get_type(_sd_channel, &card_type, &card_speed, &card_capa);
+ if( sd_err != SD_OK)
+ {
+ return _error(sd_err);
+ }
+
+ if( (card_type & SD_MEDIA_SD) != SD_MEDIA_SD )
+ {
+ return SD_BLOCK_DEVICE_ERROR_UNUSABLE;
+ }
+
+ uint32_t regOCR;
+ uint8_t regCID[CSD_CID_LENGTH];
+ uint8_t regCSD[CSD_CID_LENGTH];
+ uint8_t regDSR[2];
+ uint8_t regSCR[8];
+
+ sd_err = sd_get_reg(_sd_channel, (uint8_t *)®OCR, regCID, regCSD, regDSR, regSCR);
+ if (sd_err != SD_OK)
+ {
+ return _error(sd_err);
+ }
+ regOCR = __REV(regOCR);
+ // Check if card supports voltage range: 3.3V
+ if (!(regOCR & OCR_3_3V)) {
+ _card_type = CARD_UNKNOWN;
+ status = SD_BLOCK_DEVICE_ERROR_UNUSABLE;
+ return status;
+ }
+ }
+ else
+ {
+ status = SD_BLOCK_DEVICE_ERROR_NO_INIT;
+ }
+
+ return status;
+}
+
+
+int SDHIBlockDevice::init()
+{
+ vMutex l(&_mutex);
+
+ if(!_is_initialized)
+ _init_ref_count = 0;
+
+ _init_ref_count++;
+
+ if(_init_ref_count != 1)
+ return BD_ERROR_OK;
+
+ int err = _initialise_card();
+ _is_initialized = (err == BD_ERROR_OK);
+ if (!_is_initialized) {
+ debug_if(SDHI_DBG, "Fail to initialize card\n");
+ return err;
+ }
+ debug_if(SDHI_DBG, "init card = %d\r\n", _is_initialized);
+ _sectors = _sd_sectors();
+
+ if (0 == _sectors) {
+ return BD_ERROR_DEVICE_ERROR;
+ }
+
+ return BD_ERROR_OK;
+}
+
+int SDHIBlockDevice::deinit()
+{
+ vMutex l(&_mutex);
+
+ if(!_is_initialized)
+ _init_ref_count = 0;
+
+ _init_ref_count--; //!!!
+
+ if(_init_ref_count)
+ return BD_ERROR_OK;
+
+ _sectors = 0;
+ if ( _is_initialized )
+ {
+ sd_unmount(_sd_channel);
+ debug_if(SDHI_DBG, "card deinited![%d]\r\n", _is_initialized);
+ _is_initialized = false;
+ }
+ return 0;
+}
+
+
+int SDHIBlockDevice::program(const void *b, bd_addr_t addr, bd_size_t size)
+{
+ if (!is_valid_program(addr, size)) {
+ return SD_BLOCK_DEVICE_ERROR_PARAMETER;
+ }
+
+ vMutex l(&_mutex);
+
+ if (!_is_initialized) {
+ return SD_BLOCK_DEVICE_ERROR_NO_INIT;
+ }
+
+ uint8_t* buffer = const_cast<uint8_t*>(static_cast<const uint8_t*>(b));
+ int status = BD_ERROR_OK;
+
+ // Get block count
+ bd_addr_t blockCnt = size / _block_size;
+
+ addr = addr / _block_size;
+
+ // Send command to perform write operation
+ int32_t sd_err = sd_write_sect( _sd_channel, buffer, addr, blockCnt, SD_WRITE_OVERWRITE);
+
+ if (sd_err != SD_OK)
+ {
+ _error(sd_err);
+ status = SD_BLOCK_DEVICE_ERROR_WRITE;
+ }
+
+ return status;
+}
+
+int SDHIBlockDevice::read(void *b, bd_addr_t addr, bd_size_t size)
+{
+ if (!is_valid_read(addr, size)) {
+ return SD_BLOCK_DEVICE_ERROR_PARAMETER;
+ }
+
+ vMutex l(&_mutex);
+
+ if (!_is_initialized) {
+ return SD_BLOCK_DEVICE_ERROR_NO_INIT;
+ }
+ uint8_t *buffer = static_cast<uint8_t*>(b);
+ int status = BD_ERROR_OK;
+ bd_addr_t blockCnt = size / _block_size;
+
+ addr = addr / _block_size;
+
+ int32_t sd_err = sd_read_sect(_sd_channel, buffer, addr, blockCnt);
+
+ if (sd_err != SD_OK)
+ {
+ _error(sd_err);
+ status = SD_BLOCK_DEVICE_ERROR_NO_RESPONSE;
+ }
+
+ return status;
+}
+
+int SDHIBlockDevice::erase(bd_addr_t addr, bd_size_t size)
+{
+ return 0;
+}
+
+
+bool SDHIBlockDevice::_is_valid_trim(bd_addr_t addr, bd_size_t size)
+{
+ return (
+ addr % _erase_size == 0 &&
+ size % _erase_size == 0 &&
+ addr + size <= this->size());
+}
+
+int SDHIBlockDevice::trim(bd_addr_t addr, bd_size_t size)
+{
+ if (!_is_valid_trim(addr, size)) {
+ return SD_BLOCK_DEVICE_ERROR_PARAMETER;
+ }
+
+ vMutex l(&_mutex);
+
+ if (!_is_initialized) {
+ return SD_BLOCK_DEVICE_ERROR_NO_INIT;
+ }
+ int status = BD_ERROR_OK;
+
+ size -= _block_size;
+ // SDSC Card (CCS=0) uses byte unit address
+ // SDHC and SDXC Cards (CCS=1) use block unit address (512 Bytes unit)
+ if (SDCARD_V2HC == _card_type) {
+ size = size / _block_size;
+ addr = addr / _block_size;
+ }
+
+ return status;
+}
+
+bd_size_t SDHIBlockDevice::get_read_size() const
+{
+ return _block_size;
+}
+
+bd_size_t SDHIBlockDevice::get_program_size() const
+{
+ return _block_size;
+}
+
+/*
+bd_size_t SDHIBlockDevice::get_erase_size() const
+{
+ return _block_size;
+}
+*/
+
+bd_size_t SDHIBlockDevice::size() const
+{
+ return _block_size*_sectors;
+}
+
+void SDHIBlockDevice::debug(bool dbg)
+{
+ _dbg = dbg;
+}
+
+const char *SDHIBlockDevice::get_type() const
+{
+ return "RZ-SDHI";
+}
+
+// PRIVATE FUNCTIONS
+
+bd_size_t SDHIBlockDevice::_sd_sectors() {
+ uint32_t c_size, c_size_mult, read_bl_len;
+ uint32_t block_len, mult, blocknr;
+ uint32_t hc_c_size;
+ bd_size_t blocks = 0, capacity = 0;
+ uint8_t csd[CSD_CID_LENGTH];
+
+ int32_t sd_err = sd_get_reg(_sd_channel, NULL, NULL, csd, NULL, NULL);
+ if ( sd_err != SD_OK )
+ {
+ debug_if(SDHI_DBG, "Couldn't read csd response from disk\r\n");
+ _error(sd_err);
+ return 0;
+ }
+ for(int i = 0; i < (CSD_CID_LENGTH-1); i++)
+ {
+ csd[i] = csd[i+1];
+ }
+
+ debug_if(SDHI_DBG,"CSD is ");
+ for(unsigned int i = 0; i < sizeof(csd); i++)
+ {
+ debug_if(SDHI_DBG, "%02X ", csd[i]);
+ }
+ debug_if(SDHI_DBG,"\r\n");
+
+ // csd_structure : csd[127:126]
+ int csd_structure = ext_bits(csd, CSD_CID_LENGTH, 127, 126);
+ switch (csd_structure) {
+ case 0:
+ c_size = ext_bits(csd, CSD_CID_LENGTH, 73, 62); // c_size : csd[73:62]
+ c_size_mult = ext_bits(csd, CSD_CID_LENGTH, 49, 47); // c_size_mult : csd[49:47]
+ read_bl_len = ext_bits(csd, CSD_CID_LENGTH, 83, 80); // read_bl_len : csd[83:80] - the *maximum* read block length
+ block_len = 1 << read_bl_len; // BLOCK_LEN = 2^READ_BL_LEN
+ mult = 1 << (c_size_mult + 2); // MULT = 2^C_SIZE_MULT+2 (C_SIZE_MULT < 8)
+ blocknr = (c_size + 1) * mult; // BLOCKNR = (C_SIZE+1) * MULT
+ capacity = blocknr * block_len; // memory capacity = BLOCKNR * BLOCK_LEN
+ blocks = capacity / _block_size;
+ debug_if(SDHI_DBG, "Standard Capacity: c_size: %lu\r\n", c_size);
+ debug_if(SDHI_DBG, "Sectors: 0x%llx : %llu\r\n", blocks, blocks);
+ debug_if(SDHI_DBG, "Capacity: 0x%llx : %llu MB\r\n", capacity, (capacity/(1024U*1024U)));
+
+ // ERASE_BLK_EN = 1: Erase in multiple of 512 bytes supported
+ if (ext_bits(csd, CSD_CID_LENGTH, 46, 46)) {
+ _erase_size = BLOCK_SIZE_HC;
+ } else {
+ // ERASE_BLK_EN = 1: Erase in multiple of SECTOR_SIZE supported
+ _erase_size = BLOCK_SIZE_HC * (ext_bits(csd, CSD_CID_LENGTH, 45, 39) + 1);
+ }
+ break;
+
+ case 1:
+ hc_c_size = ext_bits(csd, CSD_CID_LENGTH, 69, 48); // device size : C_SIZE : [69:48]
+ blocks = (hc_c_size+1) << 10; // block count = C_SIZE+1) * 1K byte (512B is block size)
+ debug_if(SDHI_DBG, "SDHC/SDXC Card: hc_c_size: %lu\r\n", hc_c_size);
+ debug_if(SDHI_DBG, "Sectors: 0x%llx : %llu\r\n", blocks, blocks);
+ debug_if(SDHI_DBG, "Capacity: %llu MB\r\n", (blocks/(2048U)));
+ // ERASE_BLK_EN is fixed to 1, which means host can erase one or multiple of 512 bytes.
+ _erase_size = BLOCK_SIZE_HC;
+ break;
+
+ default:
+ debug_if(SDHI_DBG, "CSD struct unsupported\r\n");
+ return 0;
+ };
+ return blocks;
+}
+
+const char * SDHIBlockDevice::_sderr_msg(int32_t errorno)
+{
+#if SDHI_DBG
+ map<int32_t, const char *>::iterator it = _sd_err_map.find(errorno);
+
+ if ( it != _sd_err_map.end() )
+ return it->second;
+ else
+ return "SD UNKNWON ERROR NO\n";
+#else
+ return (const char *)0;
+#endif
+}
+
+int SDHIBlockDevice::_error(int32_t errcode)
+{
+ int32_t sd_err = errcode;
+ if(_sd_channel >= 0 && _sd_channel < SDHI_COUNT )
+ {
+ int32_t err = sd_get_error(_sd_channel);
+ if ( err != SD_OK)
+ sd_err = err;
+ debug_if(SDHI_DBG, _sderr_msg(sd_err));
+ }
+ return sd_err;
+}
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/components/storage/blockdevice/COMPONENT_RZ_SDHI/RZ_SDHIBlockDevice.hpp Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,242 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_RZ_SDHI_BLOCK_DEVICE_HPP
+#define MBED_RZ_SDHI_BLOCK_DEVICE_HPP
+
+/* If the target has no SPI support then SDCard is not supported */
+#ifdef DEVICE_SPI
+
+#include "BlockDevice.h"
+#include "mbed.h"
+#include "platform/PlatformMutex.h"
+#include <map>
+
+//#include "r_typedefs.h"
+
+#include "sdif.h"
+#include "sd_cfg.h"
+
+#define SDHI_DBG 1 /*!< 1 - Enable debugging */
+
+/** Access an SD Card using SDHI
+ *
+ * @code
+ * #include "mbed.h"
+ * #include "SDHIBlockDevice.h"
+ *
+ * SDHIBlockDevice rz_sdhi(p5, p6, p7, p12, p13, p14, p15, p2); // CLK, CMD, CD, WP, D0, D1, D2, D3
+ * -- or --
+ * #define SDHI_CHANNEL 0
+ * SDHIBlockDevice rz_sdhi(SDHI_CHANNEL); // use channel 0
+ *
+ * uint8_t block[512] = "Hello World!\n";
+ *
+ * int main() {
+ * rz_sdhi.init();
+ * rz_sdhi.write(block, 0, 512);
+ * rz_sdhi.read(block, 0, 512);
+ * printf("%s", block);
+ * rz_sdhi.deinit();
+ * }
+ */
+
+class vMutex
+{
+public:
+ vMutex(PlatformMutex * mtx) :
+ _mutex(mtx)
+ {
+ if (_mutex)
+ _mutex->lock();
+ }
+ virtual ~vMutex()
+ {
+ if(_mutex)
+ _mutex->unlock();
+ }
+
+private:
+ PlatformMutex * _mutex;
+};
+
+typedef struct {
+ const char *msg;
+ int32_t errorno;
+} sderr_t;
+
+
+
+class SDHIBlockDevice : public BlockDevice {
+public:
+ /** Lifetime of an SD card
+ */
+ SDHIBlockDevice(uint32_t sdport);
+ SDHIBlockDevice(PinName sd_CLK, PinName sd_CMD, PinName sd_CD, PinName sd_WP,
+ PinName sd_D0, PinName sd_D1, PinName sd_D2, PinName sd_D3 );
+ virtual ~SDHIBlockDevice();
+
+ /** Initialize a block device
+ *
+ * @return 0 on success or a negative error code on failure
+ */
+ virtual int init();
+
+ /** Deinitialize a block device
+ *
+ * @return 0 on success or a negative error code on failure
+ */
+ virtual int deinit();
+
+ /** Read blocks from a block device
+ *
+ * @param buffer Buffer to write blocks to
+ * @param addr Address of block to begin reading from
+ * @param size Size to read in bytes, must be a multiple of read block size
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int read(void *buffer, bd_addr_t addr, bd_size_t size);
+
+ /** Program blocks to a block device
+ *
+ * The blocks must have been erased prior to being programmed
+ *
+ * @param buffer Buffer of data to write to blocks
+ * @param addr Address of block to begin writing to
+ * @param size Size to write in bytes, must be a multiple of program block size
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int program(const void *buffer, bd_addr_t addr, bd_size_t size);
+
+ /** Erase blocks on a block device
+ *
+ * The state of an erased block is undefined until it has been programmed
+ *
+ * @param addr Address of block to begin erasing
+ * @param size Size to erase in bytes, must be a multiple of erase block size
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int erase(bd_addr_t addr, bd_size_t size);
+
+
+ /** Mark blocks as no longer in use
+ *
+ * This function provides a hint to the underlying block device that a region of blocks
+ * is no longer in use and may be erased without side effects. Erase must still be called
+ * before programming, but trimming allows flash-translation-layers to schedule erases when
+ * the device is not busy.
+ *
+ * @param addr Address of block to mark as unused
+ * @param size Size to mark as unused in bytes, must be a multiple of erase block size
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int trim(bd_addr_t addr, bd_size_t size);
+
+ /** Get the size of a readable block
+ *
+ * @return Size of a readable block in bytes
+ */
+ virtual bd_size_t get_read_size() const;
+
+ /** Get the size of a programable block
+ *
+ * @return Size of a programable block in bytes
+ * @note Must be a multiple of the read size
+ */
+ virtual bd_size_t get_program_size() const;
+
+ /** Get the size of a eraseable block
+ *
+ * @return Size of a eraseable block in bytes
+ * @note Must be a multiple of the program size
+ */
+ /*virtual bd_size_t get_erase_size() const; */
+
+
+ /** Get the total size of the underlying device
+ *
+ * @return Size of the underlying device in bytes
+ */
+ virtual bd_size_t size() const;
+
+ /** Enable or disable debugging
+ *
+ * @param State of debugging
+ */
+ virtual void debug(bool dbg);
+
+ /** Get the BlockDevice class type.
+ *
+ * @return A string represent the BlockDevice class type.
+ */
+
+ virtual const char *get_type() const;
+
+protected:
+ void Initialize( uint32_t sdport );
+
+private:
+
+ uint8_t _card_type;
+
+ /* Move the SDCard into the SPI Mode idle state
+ *
+ * The card is transitioned from SDCard mode to SPI mode by sending the
+ * CMD0 (GO_IDLE_STATE) command with CS asserted. See the notes in the
+ * "SPI Startup" section of the comments at the head of the
+ * implementation file for further details and specification references.
+ *
+ * @return Response form the card. R1_IDLE_STATE (0x1), the successful
+ * response from CMD0. R1_XXX_XXX for more response
+ */
+// uint32_t _go_idle_state();
+ int _initialise_card();
+
+ bd_size_t _sectors;
+ bd_size_t _sd_sectors();
+
+ bool _is_valid_trim(bd_addr_t addr, bd_size_t size);
+
+ const char * _sderr_msg(int32_t errorno);
+
+ int _error(int32_t errcode);
+
+ PlatformMutex _mutex;
+
+ bd_size_t _block_size;
+ bd_size_t _erase_size;
+ bool _is_initialized;
+ bool _dbg;
+ uint32_t _init_ref_count;
+
+ int32_t _sd_channel;
+ uint32_t _regbase;
+#if SDHI_DBG
+ static const sderr_t _sd_error_msg[];
+
+ map<int32_t, const char *> _sd_err_map;
+#endif
+};
+
+#endif /* DEVICE_SPI */
+
+#endif /* MBED_RZ_SDHI_BLOCK_DEVICE_HPP */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-os-program/mbed-os/components/storage/blockdevice/COMPONENT_RZ_SDHI/TESTS/Same as TESTS in COMPONENT_SD.txt Mon Mar 18 11:46:29 2019 +0000 @@ -0,0 +1,1 @@ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/components/storage/blockdevice/COMPONENT_RZ_SDHI/mbed_lib.json Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,21 @@
+{
+ "name": "sd",
+ "config": {
+ "SDHI_CH": "SDHI_CH",
+ "FSFAT_SDCARD_INSTALLED": 1,
+ "CMD_TIMEOUT": 10000,
+ "CMD0_IDLE_STATE_RETRIES": 5,
+ "INIT_FREQUENCY": 100000,
+ "CRC_ENABLED": 1,
+ "TEST_BUFFER": 8192
+ },
+ "target_overrides": {
+ "VK_RZ_A1H": {
+ "SDHI_CH": 0
+ },
+ "VK_RZ_A1LU": {
+ "SDHI_CH": 1
+ }
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/PeripheralPins.h Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+typedef struct {
+ PinName pin;
+ int function;
+ int pm;
+} PinFunc;
+
+/************IRQ***************/
+extern const PinMap PinMap_IRQ[];
+
+/************PINMAP***************/
+extern const PinFunc PIPC_0_tbl[];
+
+/************ADC***************/
+extern const PinMap PinMap_ADC[];
+
+/************DAC***************/
+extern const PinMap PinMap_DAC[];
+
+/************I2C***************/
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+
+/************UART***************/
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+extern const PinMap PinMap_UART_CTS[];
+extern const PinMap PinMap_UART_RTS[];
+
+/************SPI***************/
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SSEL[];
+
+/************PWM***************/
+extern const PinMap PinMap_PWM[];
+
+/************CAN***************/
+extern const PinMap PinMap_CAN_RD[];
+extern const PinMap PinMap_CAN_TD[];
+
+#if (defined(TARGET_VK_RZ_A1H) || defined(TARGET_VK_RZ_A1LU))
+/************SDHI***************/
+extern const PinMap PinMap_SDHI_WP[];
+extern const PinMap PinMap_SDHI_CD[];
+extern const PinMap PinMap_SDHI_CLK[];
+extern const PinMap PinMap_SDHI_CMD[];
+extern const PinMap PinMap_SDHI_D0[];
+extern const PinMap PinMap_SDHI_D1[];
+extern const PinMap PinMap_SDHI_D2[];
+extern const PinMap PinMap_SDHI_D3[];
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART0,
+ UART1,
+ UART2,
+ UART3,
+ UART4,
+ UART5,
+ UART6,
+ UART7,
+} UARTName;
+
+typedef enum {
+ PWM_PWM1A = 0,
+ PWM_PWM1B,
+ PWM_PWM1C,
+ PWM_PWM1D,
+ PWM_PWM1E,
+ PWM_PWM1F,
+ PWM_PWM1G,
+ PWM_PWM1H,
+ PWM_PWM2A,
+ PWM_PWM2B,
+ PWM_PWM2C,
+ PWM_PWM2D,
+ PWM_PWM2E,
+ PWM_PWM2F,
+ PWM_PWM2G,
+ PWM_PWM2H,
+ PWM_TIOC0A = 0x20,
+ PWM_TIOC0C,
+ PWM_TIOC1A,
+ PWM_TIOC2A,
+ PWM_TIOC3A,
+ PWM_TIOC3C,
+ PWM_TIOC4A,
+ PWM_TIOC4C,
+} PWMName;
+
+typedef enum {
+ AN0= 0,
+ AN1= 1,
+ AN2= 2,
+ AN3= 3,
+ AN4= 4,
+ AN5= 5,
+ AN6= 6,
+ AN7= 7,
+} ADCName;
+
+typedef enum {
+ SPI_0 = 0,
+ SPI_1,
+ SPI_2,
+ SPI_3,
+ SPI_4,
+} SPIName;
+
+typedef enum {
+ I2C_0 = 0,
+ I2C_1,
+ I2C_2,
+ I2C_3,
+} I2CName;
+
+typedef enum {
+ CAN_0 = 0,
+ CAN_1,
+ CAN_2,
+ CAN_3,
+ CAN_4,
+} CANName;
+
+typedef enum {
+ SDHI_0 = 0,
+ SDHI_1
+} SDHIName;
+
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART3
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,588 @@
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+/************IRQ***************/
+enum {
+ IRQ0,IRQ1,
+ IRQ2,IRQ3,
+ IRQ4,IRQ5,
+ IRQ6,IRQ7,
+} IRQNo;
+const PinMap PinMap_IRQ[] = {
+#ifdef MAX_PERI
+ {P1_0, IRQ0, 4}, {P4_8, IRQ0, 8}, {P6_8, IRQ0, 8}, {P7_9, IRQ0, 8}, {P8_2, IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8, IRQ0, 2}, {P9_1, IRQ0, 4},
+ {P1_1, IRQ1, 4}, {P4_9, IRQ1, 8}, {P6_9, IRQ1, 8}, {P7_8, IRQ1, 8}, {P8_3, IRQ1, 6}, {P2_15, IRQ1, 8},
+ {P1_2, IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, {P6_3, IRQ2, 4},
+ {P1_3, IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9, IRQ3, 3}, {P6_4, IRQ3, 4},
+ {P1_4, IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3, IRQ4, 3}, {P6_1, IRQ4, 4},
+ {P1_5, IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0, IRQ5, 6}, {P6_0, IRQ5, 6}, {P8_7, IRQ5, 4},
+ {P1_6, IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6},
+ {P1_7, IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2, IRQ7, 4}, {P2_13, IRQ7, 8},
+ {NC, NC, 0}
+#else
+ {P9_1, IRQ0, 4},
+ {P7_8, IRQ1, 8},
+ {P1_2, IRQ2, 4}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4},
+ {P1_3, IRQ3, 4}, {P1_9, IRQ3, 3},
+ {P1_4, IRQ4, 4}, {P1_10, IRQ4, 3},
+ {P1_5, IRQ5, 4}, {P1_11, IRQ5, 3},
+ {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6},
+ {NC, NC, 0}
+#endif
+};
+
+/************PINMAP***************/
+const PinFunc PIPC_0_tbl[] = {
+#ifdef MAX_PERI
+// pin func pm
+ {P4_0 , 2 , -1}, /* TIOC0A */
+ {P5_0 , 6 , -1}, /* TIOC0A */
+ {P7_0 , 7 , -1}, /* TIOC0A */
+ {P4_1 , 2 , -1}, /* TIOC0B */
+ {P5_1 , 6 , -1}, /* TIOC0B */
+ {P7_1 , 7 , -1}, /* TIOC0B */
+ {P4_2 , 2 , -1}, /* TIOC0C */
+ {P5_5 , 6 , -1}, /* TIOC0C */
+ {P7_2 , 7 , -1}, /* TIOC0C */
+ {P4_3 , 2 , -1}, /* TIOC0D */
+ {P5_7 , 6 , -1}, /* TIOC0D */
+ {P7_3 , 7 , -1}, /* TIOC0D */
+ {P2_11 , 5 , -1}, /* TIOC1A */
+ {P6_0 , 5 , -1}, /* TIOC1A */
+ {P7_4 , 7 , -1}, /* TIOC1A */
+ {P8_8 , 5 , -1}, /* TIOC1A */
+ {P9_7 , 4 , -1}, /* TIOC1A */
+ {P2_12 , 8 , -1}, /* TIOC1B */
+ {P5_2 , 6 , -1}, /* TIOC1B */
+ {P6_1 , 5 , -1}, /* TIOC1B */
+ {P7_5 , 7 , -1}, /* TIOC1B */
+ {P8_9 , 5 , -1}, /* TIOC1B */
+ {P2_1 , 6 , -1}, /* TIOC2A */
+ {P6_2 , 6 , -1}, /* TIOC2A */
+ {P7_6 , 7 , -1}, /* TIOC2A */
+ {P8_14 , 4 , -1}, /* TIOC2A */
+ {P2_2 , 6 , -1}, /* TIOC2B */
+ {P6_3 , 6 , -1}, /* TIOC2B */
+ {P7_7 , 7 , -1}, /* TIOC2B */
+ {P8_15 , 4 , -1}, /* TIOC2B */
+ {P3_4 , 6 , -1}, /* TIOC3A */
+ {P7_8 , 7 , -1}, /* TIOC3A */
+ {P8_10 , 4 , -1}, /* TIOC3A */
+ {P3_5 , 6 , -1}, /* TIOC3B */
+ {P7_9 , 7 , -1}, /* TIOC3B */
+ {P8_11 , 4 , -1}, /* TIOC3B */
+ {P3_6 , 6 , -1}, /* TIOC3C */
+ {P5_3 , 6 , -1}, /* TIOC3C */
+ {P7_10 , 7 , -1}, /* TIOC3C */
+ {P8_12 , 4 , -1}, /* TIOC3C */
+ {P3_7 , 6 , -1}, /* TIOC3D */
+ {P5_4 , 6 , -1}, /* TIOC3D */
+ {P7_11 , 7 , -1}, /* TIOC3D */
+ {P8_13 , 4 , -1}, /* TIOC3D */
+ {P3_8 , 6 , -1}, /* TIOC4A */
+ {P4_4 , 3 , -1}, /* TIOC4A */
+ {P7_12 , 7 , -1}, /* TIOC4A */
+ {P3_9 , 6 , -1}, /* TIOC4B */
+ {P4_5 , 3 , -1}, /* TIOC4B */
+ {P7_13 , 7 , -1}, /* TIOC4B */
+ {P3_10 , 6 , -1}, /* TIOC4C */
+ {P4_6 , 3 , -1}, /* TIOC4C */
+ {P7_14 , 7 , -1}, /* TIOC4C */
+ {P3_11 , 6 , -1}, /* TIOC4D */
+ {P4_7 , 3 , -1}, /* TIOC4D */
+ {P7_15 , 7 , -1}, /* TIOC4D */
+ {P5_7 , 1 , 1 }, /* TXOUT0M */
+ {P5_6 , 1 , 1 }, /* TXOUT0P */
+ {P5_5 , 1 , 1 }, /* TXOUT1M */
+ {P5_4 , 1 , 1 }, /* TXOUT1P */
+ {P5_3 , 1 , 1 }, /* TXOUT2M */
+ {P5_2 , 1 , 1 }, /* TXOUT2P */
+ {P5_1 , 1 , 1 }, /* TXCLKOUTM */
+ {P5_0 , 1 , 1 }, /* TXCLKOUTP */
+ {P2_11 , 4 , 0 }, /* SSITxD0 */
+ {P4_7 , 5 , 0 }, /* SSITxD0 */
+ {P7_4 , 6 , 0 }, /* SSITxD1 */
+ {P4_15 , 6 , 0 }, /* SSITxD3 */
+ {P7_11 , 2 , 0 }, /* SSITxD3 */
+ {P2_7 , 4 , 0 }, /* SSITxD5 */
+ {P4_11 , 5 , 0 }, /* SSITxD5 */
+ {P8_10 , 8 , 0 }, /* SSITxD5 */
+ {P3_7 , 8 , 0 }, /* WDTOVF */
+ {NC , 0 , -1}
+#else
+ // pin func pm
+ {P4_0 , 2 , -1}, // TIOC0A
+ {P5_0 , 6 , -1}, // TIOC0A
+ {P4_2 , 2 , -1}, // TIOC0C
+ {P5_5 , 6 , -1}, // TIOC0C
+ //
+ {P8_14 , 4 , -1}, // TIOC2A
+ //
+ {P8_10 , 4 , -1}, // TIOC3A
+ {P5_3 , 6 , -1}, // TIOC3C
+ {P8_12 , 4 , -1}, // TIOC3C
+ //
+ {P3_8 , 6 , -1}, // TIOC4A
+ {P4_4 , 3 , -1}, // TIOC4A
+ {P3_10 , 6 , -1}, // TIOC4C
+ {P4_6 , 3 , -1}, // TIOC4C
+ //
+ {P5_7 , 1 , 1 }, // TXOUT0M
+ {P5_6 , 1 , 1 }, // TXOUT0P
+ {P5_5 , 1 , 1 }, // TXOUT1M
+ {P5_4 , 1 , 1 }, // TXOUT1P
+ {P5_3 , 1 , 1 }, // TXOUT2M
+ {P5_2 , 1 , 1 }, // TXOUT2P
+ {P5_1 , 1 , 1 }, // TXCLKOUTM
+ {P5_0 , 1 , 1 }, // TXCLKOUTP
+ {P4_7 , 5 , 0 }, // SSITxD0
+ {P8_10 , 8 , 0 }, // SSITxD5
+ {P3_7 , 8 , 0 }, // WDTOVF
+ {NC , 0 , -1}
+#endif
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+#ifdef MAX_PERI
+ {P1_8, AN0, 1},
+ {P1_9, AN1, 1},
+ {P1_10, AN2, 1},
+ {P1_11, AN3, 1},
+ {P1_12, AN4, 1},
+ {P1_13, AN5, 1},
+ {P1_14, AN6, 1},
+ {P1_15, AN7, 1},
+ {NC, NC, 0}
+#else
+ {P1_8, AN0, 1},
+ {P1_9, AN1, 1},
+ {P1_10, AN2, 1},
+ {P1_11, AN3, 1},
+ {P1_12, AN4, 1},
+ {P1_13, AN5, 1},
+ {P1_15, AN7, 1},
+ {NC, NC, 0}
+#endif
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+ {P1_1 , I2C_0, 1},
+ {P1_3 , I2C_1, 1},
+ {P1_5 , I2C_2, 1},
+ {P1_7 , I2C_3, 1},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {P1_0 , I2C_0, 1},
+ {P1_2 , I2C_1, 1},
+ {P1_4 , I2C_2, 1},
+ {P1_6 , I2C_3, 1},
+ {NC , NC, 0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+#ifdef MAX_PERI
+ {P2_14 , UART0, 6},
+ {P4_9 , UART0, 7},
+ {P6_9 , UART0, 5},
+ {P2_5 , UART1, 6},
+ {P4_12 , UART1, 7},
+ {P6_12 , UART1, 5},
+ {P9_3 , UART1, 4},
+ {P3_0 , UART2, 6},
+ {P3_1 , UART2, 4},
+ {P4_2 , UART2, 5},
+ {P4_14 , UART2, 7},
+ {P6_3 , UART2, 7},
+ {P8_6 , UART2, 7},
+ {P3_5 , UART3, 7},
+ {P5_3 , UART3, 5},
+ {P6_1 , UART3, 7},
+ {P8_8 , UART3, 7},
+ {P5_0 , UART4, 5},
+ {P7_1 , UART4, 4},
+ {P8_14 , UART4, 7},
+ {P6_6 , UART5, 5},
+ {P8_1 , UART5, 4},
+ {P8_13 , UART5, 5},
+ {P5_6 , UART6, 5},
+ {P6_14 , UART6, 4},
+ {P7_4 , UART7, 4},
+ {NC , NC , 0}
+#else
+ {P3_0 , UART2, 6},
+ {P3_1 , UART2, 4},
+ {P4_2 , UART2, 5},
+ {P5_3 , UART3, 5},
+ {P8_8 , UART3, 7},
+ {P5_0 , UART4, 5},
+ {P8_14 , UART4, 7},
+ {P8_13 , UART5, 5},
+ {P5_6 , UART6, 5},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_UART_RX[] = {
+#ifdef MAX_PERI
+ {P2_15 , UART0, 6},
+ {P4_10 , UART0, 7},
+ {P6_10 , UART0, 5},
+ {P2_6 , UART1, 6},
+ {P4_13 , UART1, 7},
+ {P6_13 , UART1, 5},
+ {P9_4 , UART1, 4},
+ {P3_2 , UART2, 4},
+ {P4_3 , UART2, 5},
+ {P4_15 , UART2, 7},
+ {P6_2 , UART2, 7},
+ {P8_4 , UART2, 7},
+ {P3_6 , UART3, 7},
+ {P5_4 , UART3, 5},
+ {P6_0 , UART3, 7},
+ {P8_9 , UART3, 7},
+ {P5_1 , UART4, 5},
+ {P7_2 , UART4, 4},
+ {P8_15 , UART4, 7},
+ {P6_7 , UART5, 5},
+ {P8_2 , UART5, 4},
+ {P8_11 , UART5, 5},
+ {P5_7 , UART6, 5},
+ {P6_15 , UART6, 4},
+ {P7_5 , UART7, 4},
+ {NC , NC , 0}
+#else
+ {P3_2 , UART2, 4},
+ {P4_3 , UART2, 5},
+ {P5_4 , UART3, 5},
+ {P8_9 , UART3, 7},
+ {P5_1 , UART4, 5},
+ {P8_15 , UART4, 7},
+ {P8_11 , UART5, 5},
+ {P5_7 , UART6, 5},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_UART_CTS[] = {
+#ifdef MAX_PERI
+ {P2_3 , UART1, 6},
+ {P9_5 , UART1, 4},
+ {P6_3 , UART5, 5},
+ {P7_15 , UART5, 4},
+ {P7_6 , UART7, 4},
+ {NC , NC , 0}
+#else
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_UART_RTS[] = {
+#ifdef MAX_PERI
+ {P2_7 , UART1, 6},
+ {P9_6 , UART1, 4},
+ {P6_4 , UART5, 5},
+ {P8_3 , UART5, 4},
+ {P7_7 , UART7, 4},
+ {NC , NC , 0}
+#else
+ {NC , NC , 0}
+#endif
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+#ifdef MAX_PERI
+ {P2_12 , SPI_0, 2},
+ {P7_15 , SPI_0, 2},
+ {P4_4 , SPI_1, 2},
+ {P6_4 , SPI_1, 7},
+ {P8_3 , SPI_2, 3},
+ {P8_14 , SPI_2, 5},
+ {P3_0 , SPI_3, 8},
+ {P5_0 , SPI_3, 8},
+ {P2_8 , SPI_4, 8},
+ {P4_0 , SPI_4, 7},
+ {NC , NC , 0}
+#else
+ {P4_4 , SPI_1, 2},
+ {P8_14 , SPI_2, 5},
+ {P5_0 , SPI_3, 8},
+ {P4_0 , SPI_4, 7},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+#ifdef MAX_PERI
+ {P2_14 , SPI_0, 2},
+ {P8_1 , SPI_0, 2},
+ {P4_6 , SPI_1, 2},
+ {P6_6 , SPI_1, 7},
+ {P8_5 , SPI_2, 3},
+ {P9_0 , SPI_2, 5},
+ {P3_2 , SPI_3, 8},
+ {P5_2 , SPI_3, 8},
+ {P2_10 , SPI_4, 8},
+ {P4_2 , SPI_4, 7},
+ {NC , NC , 0}
+#else
+ {P4_6 , SPI_1, 2},
+ {P9_0 , SPI_2, 5},
+ {P5_2 , SPI_3, 8},
+ {P4_2 , SPI_4, 7},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+#ifdef MAX_PERI
+ {P2_15 , SPI_0, 2},
+ {P8_2 , SPI_0, 2},
+ {P4_7 , SPI_1, 2},
+ {P6_7 , SPI_1, 7},
+ {P8_6 , SPI_2, 3},
+ {P9_1 , SPI_2, 5},
+ {P3_3 , SPI_3, 8},
+ {P5_3 , SPI_3, 8},
+ {P2_11 , SPI_4, 8},
+ {P4_3 , SPI_4, 7},
+ {NC , NC , 0}
+#else
+ {P4_7 , SPI_1, 2},
+ {P9_1 , SPI_2, 5},
+ {P5_3 , SPI_3, 8},
+ {P4_3 , SPI_4, 7},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+#ifdef MAX_PERI
+ {P2_13 , SPI_0, 2},
+ {P8_0 , SPI_0, 2},
+ {P4_5 , SPI_1, 2},
+ {P6_5 , SPI_1, 7},
+ {P8_4 , SPI_2, 3},
+ {P8_15 , SPI_2, 5},
+ {P3_1 , SPI_3, 8},
+ {P5_1 , SPI_3, 8},
+ {P2_9 , SPI_4, 8},
+ {P4_1 , SPI_4, 7},
+ {NC , NC , 0}
+#else
+ {P4_5 , SPI_1, 2},
+ {P8_15 , SPI_2, 5},
+ {P5_1 , SPI_3, 8},
+ {P4_1 , SPI_4, 7},
+ {NC , NC , 0}
+#endif
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+#ifdef MAX_PERI
+ // TIOC0 A,C
+ {P4_0 , PWM_TIOC0A, 2}, //TIOC0A
+ {P5_0 , PWM_TIOC0A, 6}, //TIOC0A
+ {P7_0 , PWM_TIOC0A, 7}, //TIOC0A
+ {P4_2 , PWM_TIOC0C, 2}, //TIOC0C
+ {P5_5 , PWM_TIOC0C, 6}, //TIOC0C
+ {P7_2 , PWM_TIOC0C, 7}, //TIOC0C
+ //TIOC1 A
+ {P2_11 , PWM_TIOC1A, 5}, //TIOC1A
+ {P6_0 , PWM_TIOC1A, 5}, //TIOC1A
+ {P7_4 , PWM_TIOC1A, 7}, //TIOC1A
+ {P8_8 , PWM_TIOC1A, 5}, //TIOC1A
+ {P9_7 , PWM_TIOC1A, 4}, //TIOC1A
+ //TIOC2 A
+ {P2_1 , PWM_TIOC2A, 6}, //TIOC2A
+ {P6_2 , PWM_TIOC2A, 6}, //TIOC2A
+ {P7_6 , PWM_TIOC2A, 7}, //TIOC2A
+ {P8_14 , PWM_TIOC2A, 4}, //TIOC2A
+ //TIOC3 A,C
+ {P3_4 , PWM_TIOC3A, 6}, //TIOC3A
+ {P7_8 , PWM_TIOC3A, 7}, //TIOC3A
+ {P8_10 , PWM_TIOC3A, 4}, //TIOC3A
+ {P3_6 , PWM_TIOC3C, 6}, //TIOC3C
+ {P7_10 , PWM_TIOC3C, 7}, //TIOC3C
+ {P8_12 , PWM_TIOC3C, 4}, //TIOC3C
+ //TIOC4 A,C
+ {P3_8 , PWM_TIOC4A, 6}, //TIOC4A
+ {P4_4 , PWM_TIOC4A, 3}, //TIOC4A
+ {P7_12 , PWM_TIOC4A, 7}, //TIOC4A
+ {P3_10 , PWM_TIOC4C, 6}, //TIOC4C
+ {P4_6 , PWM_TIOC4C, 3}, //TIOC4C
+ {P7_14 , PWM_TIOC4C, 7}, //TIOC4C
+ //PWM1
+ {P8_8 , PWM_PWM1A , 6}, //PWM1A
+ {P8_9 , PWM_PWM1B , 6}, //PWM1B
+ {P8_10 , PWM_PWM1C , 6}, //PWM1C
+ {P8_11 , PWM_PWM1D , 6}, //PWM1D
+ {P8_12 , PWM_PWM1E , 6}, //PWM1E
+ {P8_13 , PWM_PWM1F , 6}, //PWM1F
+ {P8_14 , PWM_PWM1G , 6}, //PWM1G
+ {P8_15 , PWM_PWM1H , 6}, //PWM1H
+ //PWM2
+ {P3_0 , PWM_PWM2A , 7}, //PWM2A
+ {P3_1 , PWM_PWM2B , 7}, //PWM2B
+ {P3_2 , PWM_PWM2C , 7}, //PWM2C
+ {P3_3 , PWM_PWM2D , 7}, //PWM2D
+ {P4_4 , PWM_PWM2E , 4}, //PWM2E
+ {P4_5 , PWM_PWM2F , 4}, //PWM2F
+ {P4_6 , PWM_PWM2G , 4}, //PWM2G
+ {P4_7 , PWM_PWM2H , 4}, //PWM2H
+ {NC , NC , 0}
+#else
+ //TIOC0 A,C
+ {P4_0 , PWM_TIOC0A, 2}, //TIOC0A
+ {P5_0 , PWM_TIOC0A, 6}, //TIOC0A
+ {P4_2 , PWM_TIOC0C, 2}, //TIOC0C
+ {P5_5 , PWM_TIOC0C, 6}, //TIOC0C
+ //TIOC2 A
+ {P8_14 , PWM_TIOC2A, 4}, //TIOC2A
+ //TIOC3 A,C
+ {P8_10 , PWM_TIOC3A, 4}, //TIOC3A
+ {P5_3 , PWM_TIOC3C, 6}, //TIOC3C
+ {P8_12 , PWM_TIOC3C, 4}, //TIOC3C
+ //TIOC4 A,C
+ {P3_8 , PWM_TIOC4A, 6}, //TIOC4A
+ {P4_4 , PWM_TIOC4A, 3}, //TIOC4A
+ {P3_10 , PWM_TIOC4C, 6}, //TIOC4C
+ {P4_6 , PWM_TIOC4C, 3}, //TIOC4C
+ //PWM1
+ {P8_10 , PWM_PWM1C , 6}, //PWM1C
+ {P8_11 , PWM_PWM1D , 6}, //PWM1D
+ {P8_12 , PWM_PWM1E , 6}, //PWM1E
+ {P8_13 , PWM_PWM1F , 6}, //PWM1F
+ {P8_14 , PWM_PWM1G , 6}, //PWM1G
+ {P8_15 , PWM_PWM1H , 6}, //PWM1H
+ //PWM2
+ {P3_0 , PWM_PWM2A , 7}, //PWM2A
+ {P3_1 , PWM_PWM2B , 7}, //PWM2B
+ {P3_2 , PWM_PWM2C , 7}, //PWM2C
+ {P4_4 , PWM_PWM2E , 4}, //PWM2E
+ {P4_5 , PWM_PWM2F , 4}, //PWM2F
+ {P4_6 , PWM_PWM2G , 4}, //PWM2G
+ {P4_7 , PWM_PWM2H , 4}, //PWM2H
+ {NC , NC , 0}
+#endif
+};
+
+/************CAN***************/
+const PinMap PinMap_CAN_RD[] = {
+#ifdef MAX_PERI
+ {P7_8 , CAN_0, 4},
+ {P9_1 , CAN_0, 3},
+ {P1_4 , CAN_1, 3},
+ {P5_9 , CAN_1, 5},
+ {P7_11 , CAN_1, 4},
+ {P4_9 , CAN_2, 6},
+ {P6_4 , CAN_2, 3},
+ {P7_2 , CAN_2, 5},
+ {P2_12 , CAN_3, 5},
+ {P4_2 , CAN_3, 4},
+ {P1_5 , CAN_4, 3},
+ {P2_14 , CAN_4, 5},
+ {NC , NC , 0}
+#else
+ {P9_1 , CAN_0, 3},
+ {P1_4 , CAN_1, 3},
+ {P5_9 , CAN_1, 5},
+ {P4_2 , CAN_3, 4},
+ {P1_5 , CAN_4, 3},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_CAN_TD[] = {
+#ifdef MAX_PERI
+ {P7_9 , CAN_0, 4},
+ {P9_0 , CAN_0, 3},
+ {P5_10 , CAN_1, 5},
+ {P7_10 , CAN_1, 4},
+ {P4_8 , CAN_2, 6},
+ {P6_5 , CAN_2, 3},
+ {P7_3 , CAN_2, 5},
+ {P2_13 , CAN_3, 5},
+ {P4_3 , CAN_3, 4},
+ {P4_11 , CAN_4, 6},
+ {P8_10 , CAN_4, 5},
+ {NC , NC , 0}
+#else
+ {P9_0 , CAN_0, 3},
+ {P5_10 , CAN_1, 5},
+ {P4_3 , CAN_3, 4},
+ {P8_10 , CAN_4, 5},
+ {NC , NC , 0}
+#endif
+};
+
+const PinMap PinMap_SDHI_D0[] = {
+ {P4_11 , SDHI_0, 3},
+ {P3_11 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_D1[] = {
+ {P4_10 , SDHI_0, 3},
+ {P3_10 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_D2[] = {
+ {P4_15 , SDHI_0, 3},
+ {P3_15 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_D3[] = {
+ {P4_14 , SDHI_0, 3},
+ {P3_14 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_CLK[] = {
+ {P4_12 , SDHI_0, 3},
+ {P3_12 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_CMD[] = {
+ {P4_13 , SDHI_0, 3},
+ {P3_13 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_CD[] = {
+ {P4_8 , SDHI_0, 3},
+ {P3_8 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SDHI_WP[] = {
+ {P4_9 , SDHI_0, 3},
+ {P3_9 , SDHI_1, 7},
+ {NC , NC , 0}
+};
+
Binary file mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/SDHI_driver/TOOLCHAIN_ARM_STD/lib_RZ_A1H_sd_driver.ar has changed
Binary file mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/SDHI_driver/TOOLCHAIN_GCC_ARM/lib_RZ_A1H_sd_driver.a has changed
Binary file mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/SDHI_driver/TOOLCHAIN_IAR/lib_RZ_A1H_sd_driver.a has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/SDHI_driver/sd_cfg.h Mon Mar 18 11:46:29 2019 +0000 @@ -0,0 +1,371 @@ +/****************************************************************************** +* DISCLAIMER +* +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. +* +* This software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES +* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, +* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY +* DISCLAIMED. +* +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES +* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS +* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Renesas reserves the right, without notice, to make changes to this +* software and to discontinue the availability of this software. +* By using this software, you agree to the additional terms and +* conditions found by accessing the following link: +* http://www.renesas.com/disclaimer +******************************************************************************** +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +**************************** Technical reference data ************************** +* System Name : SD Driver Sample Program +* File Name : sd_cfg.h +* Abstract : SD Memory card driver configration +* Version : 4.00.00 +* Device : Aragon +* Tool-Chain : DS-5 Ver 5.13 +* ARM Complier +* OS : None +* H/W Platform: +* Description : +******************************************************************************** +* History : 2013.05.30 Ver.4.00.00 +*******************************************************************************/ +#ifndef _SD_CFG_H_ +#define _SD_CFG_H_ + +/* ------------------------------------------------------ + Set SDHI Base Address +--------------------------------------------------------*/ +#define SDCFG_IP0_BASE 0xE804E000 +#define SDCFG_IP1_BASE 0xE804E800 + +/* ------------------------------------------------------ + Set the method of check SD Status +--------------------------------------------------------*/ +#define SDCFG_HWINT +//#define SDCFG_POLL + +/* ------------------------------------------------------ + Set the method of data transfer +--------------------------------------------------------*/ +//#define SDCFG_TRNS_DMA +#define SDCFG_TRNS_SW + + #ifdef SDCFG_TRNS_DMA +#define SDCFG_TRANS_DMA_64 + #endif + +/* ------------------------------------------------------ + Set the card type to support +--------------------------------------------------------*/ +#define SDCFG_MEM +//#define SDCFG_IO + +/* ------------------------------------------------------ + Set the speed to support +--------------------------------------------------------*/ +//#define SDCFG_DS +#define SDCFG_HS + +/* ------------------------------------------------------ + Set the version to support +--------------------------------------------------------*/ +//#define SDCFG_VER1X /* Version 1.1 */ +#define SDCFG_VER2X /* Version 2.x */ + +/* ------------------------------------------------------ + Set the method to detect card +--------------------------------------------------------*/ +//#define SDCFG_CD_INT + +#ifdef SDCFG_CD_INT + #ifndef SDCFG_HWINT + #error please define SDCFG_HWINT + #endif +#endif + +/* ------------------------------------------------------ + Set the SD bus width +--------------------------------------------------------*/ +//#define SDCFG_SDMODE_1BIT + + + + +/* ==== end of the setting ==== */ + + #if defined(SDCFG_SDMODE_1BIT) +#if defined(SDCFG_HWINT) + #if defined(SDCFG_TRNS_DMA) + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #endif + #else + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #endif + #endif +#else + #if defined(SDCFG_TRNS_DMA) + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #endif + #else + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X|SD_MODE_1BIT) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X|SD_MODE_1BIT) + #endif + #endif + #endif + #endif +#endif + #else +#if defined(SDCFG_HWINT) + #if defined(SDCFG_TRNS_DMA) + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #endif + #else + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #endif + #endif +#else + #if defined(SDCFG_TRNS_DMA) + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #endif + #else + #if defined(SDCFG_IO) + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_IO|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #else + #if defined(SDCFG_HS) + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_HS|SD_MODE_VER1X) + #endif + #else + #if defined(SDCFG_VER2X) + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X) + #else + #define SDCFG_DRIVER_MODE2 (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X) + #endif + #endif + #endif + #endif +#endif + #endif + + #ifdef SDCFG_TRANS_DMA_64 +#define SDCFG_DRIVER_MODE (SDCFG_DRIVER_MODE2 | SD_MODE_DMA_64) + #else +#define SDCFG_DRIVER_MODE SDCFG_DRIVER_MODE2 + #endif + + +#endif /* _SD_CFG_H_ */ + +/* End of File */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/SDHI_driver/sdhi_low.c Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,1055 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : sd_dev_low.c
+* $Rev: $
+* $Date:: $
+* Device(s) : RZ/A1H
+* Tool-Chain : DS-5 Ver 5.8
+* : ARM Complier
+* OS :
+* H/W Platform : RZ/A1H CPU Board
+* Description : RZ/A1H SD Driver Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stdio.h>
+#include <string.h>
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+/*#include "devdrv_intc.h"*/
+#include "sdif.h"
+#include "sd_cfg.h"
+/*#include "sd_dev_dmacdrv.h"*/
+#include "us_ticker_api.h"
+#include "cmsis_os2.h"
+#include "mbed_assert.h"
+#include "pinmap.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+//#define MTU_TIMER_CNT 32 /* P-phy = 32MHz */
+#define INT_LEVEL_SDHI 10 /* SDHI interrupt level */
+#define SDHI_PINS_COMMON 2
+#define SDHI_PINS_SERIAL 3
+#define SDHI_PINS_PARALLEL 6
+
+#if defined(SDCFG_SDMODE_1BIT)
+# define SDHI_PORT_MODE SD_PORT_SERIAL
+#else
+# define SDHI_PORT_MODE SD_PORT_PARALLEL
+#endif
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+#if 0
+static uint8_t g_sdhi_priority_backup;
+#endif
+
+
+
+static const PinName SDHIpin_Common[SDHI_COUNT][SDHI_PINS_COMMON] = { /* WP & CD */
+ {P4_8, P4_9},
+ {P3_8, P3_9}
+};
+
+static const PinName SDHIpin_serial[SDHI_COUNT][SDHI_PINS_SERIAL] = { /* CLK CMD D0 */
+ {P4_11, P4_12, P4_13},
+ {P3_11, P3_12, P3_13}
+};
+
+static const PinName SDHIpin_parallel[SDHI_COUNT][SDHI_PINS_PARALLEL] = { /* CLK CMD D0-D3 */
+ {P4_10, P4_11, P4_12, P4_13, P4_14, P4_15},
+ {P3_10, P3_11, P3_12, P3_13, P3_14, P3_15}
+};
+
+
+static const PinMap PinMap_SDHI_PIN[] = {
+ /* pin | periph| func */
+ {P4_8 , SDHI_0, 3}, /* SD_CD_0 */
+ {P4_9 , SDHI_0, 3}, /* SD_WP_0 */
+ {P4_10 , SDHI_0, 3}, /* SD_D1_0 */
+ {P4_11 , SDHI_0, 3}, /* SD_D0_0 */
+ {P4_12 , SDHI_0, 3}, /* SD_CLK_0 */
+ {P4_13 , SDHI_0, 3}, /* SD_CMD_0 */
+ {P4_14 , SDHI_0, 3}, /* SD_D3_0 */
+ {P4_15 , SDHI_0, 3}, /* SD_D2_0 */
+ /*----------------*/
+ {P3_8 , SDHI_1, 7}, /* SD_CD_1 */
+ {P3_9 , SDHI_1, 7}, /* SD_WP_1 */
+ {P3_10 , SDHI_1, 7}, /* SD_D1_1 */
+ {P3_11 , SDHI_1, 7}, /* SD_D0_1 */
+ {P3_12 , SDHI_1, 7}, /* SD_CLK_1 */
+ {P3_13 , SDHI_1, 7}, /* SD_CMD_1 */
+ {P3_14 , SDHI_1, 7}, /* SD_D3_1 */
+ {P3_15 , SDHI_1, 7}, /* SD_D2_1 */
+ {NC , NC , 0}
+};
+
+
+
+static unsigned long _ulStart = 0;
+static unsigned long _ulDelta = 0;
+static const ticker_data_t *_ticker;
+
+//static int sddev_init_0(void);
+//static int sddev_init_1(void);
+//static int sddev_set_port_0(int mode);
+//static int sddev_set_port_1(int mode);
+
+static int sddev_init_dma_0(unsigned long buff,unsigned long reg,long cnt,int dir);
+static int sddev_init_dma_1(unsigned long buff,unsigned long reg,long cnt,int dir);
+
+static int sddev_wait_dma_end_0(long cnt);
+static int sddev_wait_dma_end_1(long cnt);
+
+static int sddev_disable_dma_0(void);
+static int sddev_disable_dma_1(void);
+
+static void sddev_sd_int_handler_0(uint32_t int_sense);
+static void sddev_sd_int_handler_1(uint32_t int_sense);
+static void sddev_sdio_int_handler_0(uint32_t int_sense);
+static void sddev_sdio_int_handler_1(uint32_t int_sense);
+static void sddev_start_timer(int msec);
+static void sddev_end_timer(void);
+static int sddev_check_timer(void);
+
+/******************************************************************************
+* Function Name: int sddev_cmd0_sdio_mount(int sd_port);
+* Description : Select to issue CMD0 before SDIO Mount
+* Arguments : none
+* Return Value : SD_OK : issue CMD0
+* : SD_ERR : not issue CMD0
+******************************************************************************/
+int sddev_cmd0_sdio_mount(int sd_port)
+{
+#ifdef SDCFG_IO
+ return SD_ERR;
+#else
+ return SD_ERR;
+#endif
+}
+
+/******************************************************************************
+* Function Name: int sddev_cmd8_sdio_mount(int sd_port);
+* Description : Select to issue CMD8 before SDIO Mount
+* Arguments : none
+* Return Value : SD_OK : issue CMD8
+* : SD_ERR : not issue CMD8
+******************************************************************************/
+int sddev_cmd8_sdio_mount(int sd_port)
+{
+#ifdef SDCFG_IO
+ return SD_OK;
+#else
+ return SD_ERR;
+#endif
+}
+
+
+
+/******************************************************************************
+* Function Name: int sddev_init(void);
+* Description : Initialize H/W to use SDHI
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_init(int sd_port)
+{
+ if ( sd_port >= SDHI_COUNT )
+ return SD_ERR;
+
+
+ volatile uint8_t dummy_buf;
+
+ CPG.STBCR12 = 0xF0u; /* [1], [1], [1], [1], SDHI00, SDHI01, SDHI10, SDHI11 */
+ dummy_buf = CPG.STBCR12; /* (Dummy read) */
+
+
+ for( uint32_t no=0; no < SDHI_PINS_COMMON; no++ )
+ {
+ if ( pinmap_peripheral(SDHIpin_Common[sd_port][no], PinMap_SDHI_PIN ) != sd_port)
+ {
+ return SD_ERR;
+ }
+ pinmap_pinout(SDHIpin_Common[sd_port][no], PinMap_SDHI_PIN);
+ }
+
+ sddev_set_port(sd_port, SDHI_PORT_MODE);
+
+#ifdef SDCFG_HWINT
+ if ( sd_port == (uint32_t)SDHI_0 )
+ {
+ InterruptHandlerRegister(SDHI0_0_IRQn, sddev_sd_int_handler_0);
+ GIC_SetPriority(SDHI0_0_IRQn, INT_LEVEL_SDHI);
+ GIC_EnableIRQ(SDHI0_0_IRQn);
+
+ InterruptHandlerRegister(SDHI0_3_IRQn, sddev_sd_int_handler_0);
+ GIC_SetPriority(SDHI0_3_IRQn, INT_LEVEL_SDHI);
+ GIC_EnableIRQ(SDHI0_3_IRQn);
+
+ InterruptHandlerRegister(SDHI0_1_IRQn, sddev_sdio_int_handler_0);
+ GIC_SetPriority(SDHI0_1_IRQn, INT_LEVEL_SDHI);
+ GIC_EnableIRQ(SDHI0_1_IRQn);
+ }
+ else if ( sd_port == (uint32_t)SDHI_1 )
+ {
+ InterruptHandlerRegister(SDHI1_0_IRQn, sddev_sd_int_handler_1);
+ GIC_SetPriority(SDHI1_0_IRQn, INT_LEVEL_SDHI);
+ GIC_EnableIRQ(SDHI1_0_IRQn);
+
+ InterruptHandlerRegister(SDHI1_3_IRQn, sddev_sd_int_handler_1);
+ GIC_SetPriority(SDHI1_3_IRQn, INT_LEVEL_SDHI);
+ GIC_EnableIRQ(SDHI1_3_IRQn);
+
+ InterruptHandlerRegister(SDHI1_1_IRQn, sddev_sdio_int_handler_1);
+ GIC_SetPriority(SDHI1_1_IRQn, INT_LEVEL_SDHI);
+ GIC_EnableIRQ(SDHI1_1_IRQn);
+ }
+#endif
+
+ /* ---- wait card detect ---- */
+ osDelay(1000); /* wait 1s */
+
+ return SD_OK;
+}
+
+
+/******************************************************************************
+* Function Name: int sddev_power_on(int sd_port);
+* Description : Power-on H/W to use SDHI
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_power_on(int sd_port)
+{
+ /* ---Power On SD ---- */
+
+ /* ---- Wait for SD Wake up ---- */
+ osDelay(100); /* wait 100ms */
+
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_power_off(int sd_port);
+* Description : Power-off H/W to use SDHI
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_power_off(int sd_port)
+{
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_read_data(int sd_port, unsigned char *buff,unsigned long reg_addr,long num);
+* Description : read from SDHI buffer FIFO
+* Arguments : unsigned char *buff : buffer addrees to store reading datas
+* : unsigned long reg_addr : SDIP FIFO address
+* : long num : counts to read(unit:byte)
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_read_data(int sd_port, unsigned char *buff,unsigned long reg_addr,long num)
+{
+ long i;
+ long cnt;
+ unsigned long *reg;
+ unsigned long *ptr_l;
+ unsigned char *ptr_c;
+ unsigned long tmp;
+
+ reg = (unsigned long *)(reg_addr);
+
+ cnt = (num / 4);
+ if(((unsigned long)buff & 0x3) != 0)
+ {
+ ptr_c = (unsigned char *)buff;
+ for(i = cnt; i > 0 ; i--)
+ {
+ tmp = *reg;
+ *ptr_c++ = (unsigned char)(tmp);
+ *ptr_c++ = (unsigned char)(tmp >> 8);
+ *ptr_c++ = (unsigned char)(tmp >> 16);
+ *ptr_c++ = (unsigned char)(tmp >> 24);
+ }
+
+ cnt = (num % 4);
+ if( cnt != 0 )
+ {
+ tmp = *reg;
+ for(i = cnt; i > 0 ; i--)
+ {
+ *ptr_c++ = (unsigned char)(tmp);
+ tmp >>= 8;
+ }
+ }
+ }
+ else
+ {
+ ptr_l = (unsigned long *)buff;
+ for(i = cnt; i > 0 ; i--)
+ {
+ *ptr_l++ = *reg;
+ }
+
+ cnt = (num % 4);
+ if( cnt != 0 )
+ {
+ ptr_c = (unsigned char *)ptr_l;
+ tmp = *reg;
+ for(i = cnt; i > 0 ; i--)
+ {
+ *ptr_c++ = (unsigned char)(tmp);
+ tmp >>= 8;
+ }
+ }
+ }
+
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_write_data(int sd_port, unsigned char *buff,unsigned long reg_addr,long num);
+* Description : write to SDHI buffer FIFO
+* Arguments : unsigned char *buff : buffer addrees to store writting datas
+* : unsigned long reg_addr : SDIP FIFO address
+* : long num : counts to write(unit:byte)
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_write_data(int sd_port, unsigned char *buff,unsigned long reg_addr,long num)
+{
+ long i;
+ unsigned long *reg = (unsigned long *)(reg_addr);
+ unsigned long *ptr = (unsigned long *)buff;
+ unsigned long tmp;
+
+ /* dont care non 4byte allignment data */
+ num += 3;
+ num /= 4;
+ if(((unsigned long)buff & 0x3) != 0)
+ {
+ for(i = num; i > 0 ; i--)
+ {
+ tmp = *buff++ ;
+ tmp |= *buff++ << 8;
+ tmp |= *buff++ << 16;
+ tmp |= *buff++ << 24;
+ *reg = tmp;
+ }
+ }
+ else
+ {
+ for(i = num; i > 0 ; i--)
+ {
+ *reg = *ptr++;
+ }
+ }
+
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: unsigned int sddev_get_clockdiv(int sd_port, int clock);
+* Description : write to SDHI buffer FIFO
+* Arguments : int clock : request clock frequency
+* : SD_CLK_50MHz
+* : SD_CLK_25MHz
+* : SD_CLK_20MHz
+* : SD_CLK_10MHz
+* : SD_CLK_5MHz
+* : SD_CLK_1MHz
+* : SD_CLK_400kHz
+* Return Value : clock div value
+* : SD_DIV_2 : 1/2 clock
+* : SD_DIV_2 : 1/4 clock
+* : SD_DIV_2 : 1/8 clock
+* : SD_DIV_2 : 1/16 clock
+* : SD_DIV_2 : 1/128 clock
+* : SD_DIV_2 : 1/256 clock
+******************************************************************************/
+unsigned int sddev_get_clockdiv(int sd_port, int clock)
+{
+ unsigned int div;
+
+ switch(clock)
+ {
+ case SD_CLK_50MHz:
+ div = SD_DIV_2; /* 64MHz/2 = 32MHz */
+ break;
+ case SD_CLK_25MHz:
+ div = SD_DIV_4; /* 64MHz/4 = 16MHz */
+ break;
+ case SD_CLK_20MHz:
+ div = SD_DIV_4; /* 64MHz/4 = 16MHz */
+ break;
+ case SD_CLK_10MHz:
+ div = SD_DIV_8; /* 64MHz/8 = 8MHz */
+ break;
+ case SD_CLK_5MHz:
+ div = SD_DIV_16; /* 64MHz/16 = 4MHz */
+ break;
+ case SD_CLK_1MHz:
+ div = SD_DIV_128; /* 64MHz/128 = 512kHz */
+ break;
+ case SD_CLK_400kHz:
+ div = SD_DIV_256; /* 64MHz/256 = 256kHz */
+ break;
+ default:
+ div = SD_DIV_256;
+ break;
+ }
+
+ return div;
+}
+
+/******************************************************************************
+* Function Name: int sddev_set_port(int sd_port, int mode);
+* Description : setting ports to use MMCHI
+* Arguments : int mode : SD_PORT_PARALLEL : 4bit mode
+* : SD_PORT_SERIAL : 1bit mode
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_set_port(int sd_port, int mode)
+{
+ if ( sd_port >= SDHI_COUNT)
+ return SD_ERR;
+
+ if(mode == SD_PORT_SERIAL)
+ {
+ for( uint32_t no=0; no < SDHI_PINS_SERIAL; no++ )
+ {
+ if ( pinmap_peripheral(SDHIpin_serial[sd_port][no], PinMap_SDHI_PIN ) != sd_port)
+ {
+ return SD_ERR;
+ }
+ pinmap_pinout(SDHIpin_serial[sd_port][no], PinMap_SDHI_PIN);
+ }
+ }
+ else if( mode == SD_PORT_PARALLEL )
+ {
+ for( uint32_t no=0; no < SDHI_PINS_PARALLEL; no++ )
+ {
+ if ( pinmap_peripheral(SDHIpin_parallel[sd_port][no], PinMap_SDHI_PIN ) != sd_port)
+ {
+ return SD_ERR;
+ }
+ pinmap_pinout(SDHIpin_parallel[sd_port][no], PinMap_SDHI_PIN);
+ }
+ }
+ else
+ {
+ return SD_ERR;
+ }
+
+ return SD_OK;
+}
+
+
+/******************************************************************************
+* Function Name: int sddev_int_wait(int sd_port, int time);
+* Description : Waitting for SDHI Interrupt
+* Arguments : int time : time out value to wait interrupt
+* Return Value : get interrupt : SD_OK
+* : time out : SD_ERR
+******************************************************************************/
+int sddev_int_wait(int sd_port, int time)
+{
+ sddev_start_timer(time);
+ while( sddev_check_timer() == SD_OK )
+ {
+ /* interrupt generated? */
+ if(sd_check_int(sd_port) == SD_OK)
+ {
+ sddev_end_timer();
+ return SD_OK;
+ }
+ }
+
+ sddev_end_timer();
+
+ return SD_ERR;
+}
+
+/******************************************************************************
+* Function Name: int sddev_init_dma(unsigned long buff,unsigned long reg,long cnt,int dir);
+* Description : Initialize DMAC to transfer data from SDHI FIFO
+* Arguments : unsigned long buff : buffer addrees to transfer datas
+* : unsigned long reg : SDIP FIFO address
+* : long cnt : counts to transfer(unit:byte)
+* : int dir : direction to transfer
+* : : 0 : FIFO -> buffer
+* : : 1 : buffer -> FIFO
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_init_dma(int sd_port, unsigned long buff,unsigned long reg,long cnt,int dir)
+{
+ int ret;
+
+ if( sd_port == 0 )
+ {
+ ret = sddev_init_dma_0(buff, reg, cnt, dir);
+ }
+ else if( sd_port == 1 )
+ {
+ ret = sddev_init_dma_1(buff, reg, cnt, dir);
+ }
+
+ return ret;
+}
+
+/******************************************************************************
+* Function Name: static int sddev_init_dma_0(unsigned long buff,unsigned long reg,long cnt,int dir);
+* Description : Initialize DMAC to transfer data from SDHI FIFO
+* Arguments : unsigned long buff : buffer addrees to transfer datas
+* : unsigned long reg : SDIP FIFO address
+* : long cnt : counts to transfer(unit:byte)
+* : int dir : direction to transfer
+* : : 0 : FIFO -> buffer
+* : : 1 : buffer -> FIFO
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+static int sddev_init_dma_0(unsigned long buff,unsigned long reg,long cnt,int dir)
+{
+#ifdef SDCFG_TRNS_DMA
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor;
+ int32_t ret;
+
+ trans_info.count = (uint32_t)cnt;
+ #ifdef SDCFG_TRANS_DMA_64
+ if( (cnt % 64) != 0 )
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32;
+ trans_info.dst_size = DMAC_TRANS_SIZE_32;
+ if( reg & 0x0000003f )
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32;
+ trans_info.dst_size = DMAC_TRANS_SIZE_32;
+ }
+ }
+ else
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_512;
+ trans_info.dst_size = DMAC_TRANS_SIZE_512;
+ }
+ #else
+ trans_info.src_size = DMAC_TRANS_SIZE_32;
+ trans_info.dst_size = DMAC_TRANS_SIZE_32;
+ #endif
+
+ if( dir == 0 )
+ {
+ request_factor = DMAC_REQ_SDHI_0_RX;
+ trans_info.src_addr = (uint32_t)reg;
+ trans_info.dst_addr = (uint32_t)buff;
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC;
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC;
+ }
+ else if( dir == 1 )
+ {
+ request_factor = DMAC_REQ_SDHI_0_TX;
+ trans_info.src_addr = (uint32_t)buff;
+ trans_info.dst_addr = (uint32_t)reg;
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC;
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC;
+ }
+
+ sd_DMAC1_PeriReqInit( (const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0 ); /* Dont care DMAC_REQ_REQD is setting in usb0_host_DMAC1_PeriReqInit() */
+
+ ret = sd_DMAC1_Open(DMAC_REQ_MODE_PERI);
+ if( ret != 0 )
+ {
+ printf("DMAC1 Open error!!\n");
+ return SD_ERR;
+ }
+#endif
+
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: static int sddev_init_dma_1(unsigned long buff,unsigned long reg,long cnt,int dir);
+* Description : Initialize DMAC to transfer data from SDHI FIFO
+* Arguments : unsigned long buff : buffer address to transfer datas
+* : unsigned long reg : SDIP FIFO address
+* : long cnt : counts to transfer(unit:byte)
+* : int dir : direction to transfer
+* : : 0 : FIFO -> buffer
+* : : 1 : buffer -> FIFO
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+static int sddev_init_dma_1(unsigned long buff,unsigned long reg,long cnt,int dir)
+{
+#ifdef SDCFG_TRNS_DMA
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor;
+ int32_t ret;
+
+ trans_info.count = (uint32_t)cnt;
+ #ifdef SDCFG_TRANS_DMA_64
+ if( (cnt % 64) != 0 )
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32;
+ trans_info.dst_size = DMAC_TRANS_SIZE_32;
+ if( reg & 0x0000003f )
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32;
+ trans_info.dst_size = DMAC_TRANS_SIZE_32;
+ }
+ }
+ else
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_512;
+ trans_info.dst_size = DMAC_TRANS_SIZE_512;
+ }
+ #else
+ trans_info.src_size = DMAC_TRANS_SIZE_32;
+ trans_info.dst_size = DMAC_TRANS_SIZE_32;
+ #endif
+
+ if( dir == 0 )
+ {
+ request_factor = DMAC_REQ_SDHI_1_RX;
+ trans_info.src_addr = (uint32_t)reg;
+ trans_info.dst_addr = (uint32_t)buff;
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC;
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC;
+ }
+ else if( dir == 1 )
+ {
+ request_factor = DMAC_REQ_SDHI_1_TX;
+ trans_info.src_addr = (uint32_t)buff;
+ trans_info.dst_addr = (uint32_t)reg;
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC;
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC;
+ }
+
+ sd_DMAC2_PeriReqInit( (const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0 ); /* Dont care DMAC_REQ_REQD is setting in usb0_host_DMAC1_PeriReqInit() */
+
+ ret = sd_DMAC2_Open(DMAC_REQ_MODE_PERI);
+ if( ret != 0 )
+ {
+ printf("DMAC1 Open error!!\n");
+ return SD_ERR;
+ }
+#endif
+
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_wait_dma_end(int sd_port, long cnt);
+* Description : Wait to complete DMAC transfer
+* Arguments : long cnt : counts to transfer(unit:byte)
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_wait_dma_end(int sd_port, long cnt)
+{
+ int ret;
+
+ if( sd_port == 0 )
+ {
+ ret = sddev_wait_dma_end_0(cnt);
+ }
+ else if( sd_port == 1 )
+ {
+ ret = sddev_wait_dma_end_1(cnt);
+ }
+
+ return ret;
+}
+
+/******************************************************************************
+* Function Name: static int sddev_wait_dma_end_0(long cnt);
+* Description : Wait to complete DMAC transfer
+* Arguments : long cnt : counts to transfer(unit:byte)
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+static int sddev_wait_dma_end_0(long cnt)
+{
+#ifdef SDCFG_TRNS_DMA
+ int loop;
+ int time;
+
+ time = (cnt / 512);
+ time = ((time * 1000) / 1024);
+ if(time < 1000)
+ {
+ time = 1000;
+ }
+
+ if(time > (0x0000ffff / MTU_TIMER_CNT))
+ {
+ /* @1000ms */
+ loop = (time / 1000);
+ if( (time % 1000) != 0 )
+ {
+ loop++;
+ }
+ time = 1000;
+ }
+ else
+ {
+ loop = 1;
+ }
+
+ do{
+ sddev_start_timer(time);
+
+ while(1)
+ {
+ /* get end flag? */
+ if( sd_DMAC1_Get_Endflag() == 1 )
+ {
+ sddev_end_timer();
+ return SD_OK;
+ }
+ /* detect timeout? */
+ if(sddev_check_timer() == SD_ERR)
+ {
+ break;
+ }
+ }
+
+ loop--;
+ if( loop <= 0 )
+ {
+ break;
+ }
+
+ } while(1);
+
+ sddev_end_timer();
+
+ return SD_ERR;
+#else
+ return SD_OK;
+
+#endif
+}
+
+/******************************************************************************
+* Function Name: static int sddev_wait_dma_end_1(long cnt);
+* Description : Wait to complete DMAC transfer
+* Arguments : long cnt : counts to transfer(unit:byte)
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+static int sddev_wait_dma_end_1(long cnt)
+{
+#ifdef SDCFG_TRNS_DMA
+ int loop;
+ int time;
+
+ time = (cnt / 512);
+ time = ((time * 1000) / 1024);
+ if(time < 1000)
+ {
+ time = 1000;
+ }
+
+ if(time > (0x0000ffff / MTU_TIMER_CNT))
+ {
+ /* @1000ms */
+ loop = (time / 1000);
+ if( (time % 1000) != 0 )
+ {
+ loop++;
+ }
+ time = 1000;
+ }
+ else
+ {
+ loop = 1;
+ }
+
+ do{
+ sddev_start_timer(time);
+
+ while(1)
+ {
+ /* get end flag? */
+ if( sd_DMAC2_Get_Endflag() == 1 )
+ {
+ sddev_end_timer();
+ return SD_OK;
+ }
+ /* detect timeout? */
+ if(sddev_check_timer() == SD_ERR)
+ {
+ break;
+ }
+ }
+
+ loop--;
+ if( loop <= 0 )
+ {
+ break;
+ }
+
+ } while(1);
+
+ sddev_end_timer();
+
+ return SD_ERR;
+#else
+ return SD_OK;
+
+#endif
+}
+
+/******************************************************************************
+* Function Name: int sddev_disable_dma(int sd_port);
+* Description : Disable DMAC transfer
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_disable_dma(int sd_port)
+{
+ int ret;
+
+ if( sd_port == 0 )
+ {
+ ret = sddev_disable_dma_0();
+ }
+ else
+ {
+ ret = sddev_disable_dma_1();
+ }
+ return ret;
+}
+
+/******************************************************************************
+* Function Name: static int sddev_disable_dma_0(void);
+* Description : Disable DMAC transfer
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+static int sddev_disable_dma_0(void)
+{
+#ifdef SDCFG_TRNS_DMA
+ uint32_t remain;
+
+ sd_DMAC1_Close(&remain);
+#endif
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: staticint sddev_disable_dma_1(void);
+* Description : Disable DMAC transfer
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+static int sddev_disable_dma_1(void)
+{
+#ifdef SDCFG_TRNS_DMA
+ uint32_t remain;
+
+ sd_DMAC2_Close(&remain);
+#endif
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_loc_cpu(int sd_port);
+* Description : lock cpu to disable interrupt
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_loc_cpu(int sd_port)
+{
+#if 0
+ R_INTC_GetMaskLevel(&g_sdhi_priority_backup);
+ R_INTC_SetMaskLevel(0);
+ core_util_critical_section_enter();
+#endif
+
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_unl_cpu(int sd_port);
+* Description : unlock cpu to enable interrupt
+* Arguments : none
+* Return Value : success : SD_OK
+* : fail : SD_ERR
+******************************************************************************/
+int sddev_unl_cpu(int sd_port)
+{
+#if 0
+ R_INTC_SetMaskLevel(g_sdhi_priority_backup);
+ core_util_critical_section_exit();
+#endif
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: int sddev_finalize(int sd_port);
+* Description : finalize SDHI
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+int sddev_finalize(int sd_port)
+{
+ return SD_OK;
+}
+
+/******************************************************************************
+* Function Name: static void sddev_sd_int_handler_0(uint32_t int_sense);
+* Description : Setting Interrupt function for SDHI(INTC_ID_SDHI0_0,INTC_ID_SDHI0_3)
+* Arguments : Interrupt mode
+* Return Value : none
+******************************************************************************/
+static void sddev_sd_int_handler_0(uint32_t int_sense)
+{
+ sd_int_handler(0);
+}
+
+/******************************************************************************
+* Function Name: static void sddev_sd_int_handler_1(uint32_t int_sense);
+* Description : Setting Interrupt function for SDHI(INTC_ID_SDHI0_0,INTC_ID_SDHI0_3)
+* Arguments : Interrupt mode
+* Return Value : none
+******************************************************************************/
+static void sddev_sd_int_handler_1(uint32_t int_sense)
+{
+ sd_int_handler(1);
+}
+
+/******************************************************************************
+* Function Name: static void sddev_sdio_int_handler_0(uint32_t int_sense);
+* Description : Setting Interrupt function for SDHI(INTC_ID_SDHI0_1)
+* Arguments : Interrupt mode
+* Return Value : none
+******************************************************************************/
+static void sddev_sdio_int_handler_0(uint32_t int_sense)
+{
+ sdio_int_handler(0);
+}
+
+/******************************************************************************
+* Function Name: static void sddev_sdio_int_handler_1(uint32_t int_sense);
+* Description : Setting Interrupt function for SDHI(INTC_ID_SDHI1_1)
+* Arguments : Interrupt mode
+* Return Value : none
+******************************************************************************/
+static void sddev_sdio_int_handler_1(uint32_t int_sense)
+{
+ sdio_int_handler(1);
+}
+
+/******************************************************************************
+* Function Name: static void sddev_start_timer(int msec);
+* Description : start timer
+* Arguments :
+* Return Value : none
+******************************************************************************/
+static void sddev_start_timer(int msec)
+{
+ _ticker = get_us_ticker_data();
+ _ulStart = ticker_read(_ticker);
+ _ulDelta = msec*1000ul;
+}
+
+/******************************************************************************
+* Function Name: static void sddev_end_timer(void);
+* Description : end timer
+* Arguments :
+* Return Value : none
+******************************************************************************/
+static void sddev_end_timer(void)
+{
+ _ulStart = 0ul;
+ _ulDelta = 0ul;
+}
+
+/******************************************************************************
+* Function Name: static int sddev_check_timer(void);
+* Description : check
+* Arguments :
+* Return Value : t
+******************************************************************************/
+static int sddev_check_timer(void)
+{
+ if ( _ulStart && _ulDelta )
+ {
+ return ((ticker_read(_ticker)-_ulStart) < _ulDelta) ? SD_OK : SD_ERR;
+ }
+ else
+ {
+ return SD_ERR;
+ }
+}
+
+/* End of File */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/SDHI_driver/sdif.h Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,329 @@
+/******************************************************************************
+* DISCLAIMER
+*
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized.
+*
+* This software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+*
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
+* DISCLAIMED.
+*
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Renesas reserves the right, without notice, to make changes to this
+* software and to discontinue the availability of this software.
+* By using this software, you agree to the additional terms and
+* conditions found by accessing the following link:
+* http://www.renesas.com/disclaimer
+********************************************************************************
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+**************************** Technical reference data **************************
+* System Name : SD Driver Sample Program
+* File Name : sdif.h
+* Abstract : SD Memory card driver configration
+* Version : 4.00.00
+* Device : Aragon
+* Tool-Chain : DS-5 Ver 5.13
+* ARM Complier
+* OS : None
+* H/W Platform:
+* Description :
+********************************************************************************
+* History : 2013.07.12 Ver.4.00.00
+*******************************************************************************/
+#ifndef _SDDRV_H_
+#define _SDDRV_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* ==== define ==== */
+/* ---- SD Driver work buffer ---- */
+#define SD_SIZE_OF_INIT 800
+
+/* ---- error code ---- */
+#define SD_OK_LOCKED_CARD 1 /* OK but card is locked status */
+#define SD_OK 0 /* OK */
+#define SD_ERR -1 /* general error */
+#define SD_ERR_WP -2 /* write protect error */
+#define SD_ERR_RO -3 /* read only error */
+#define SD_ERR_RES_TOE -4 /* response time out error */
+#define SD_ERR_CARD_TOE -5 /* card time out error */
+#define SD_ERR_END_BIT -6 /* end bit error */
+#define SD_ERR_CRC -7 /* CRC error */
+#define SD_ERR_CARD_RES -8 /* card response error */
+#define SD_ERR_HOST_TOE -9 /* host time out error */
+#define SD_ERR_CARD_ERASE -10 /* card erase error */
+#define SD_ERR_CARD_LOCK -11 /* card lock error */
+#define SD_ERR_CARD_UNLOCK -12 /* card unlock error */
+#define SD_ERR_HOST_CRC -13 /* host CRC error */
+#define SD_ERR_CARD_ECC -14 /* card internal ECC error */
+#define SD_ERR_CARD_CC -15 /* card internal error */
+#define SD_ERR_CARD_ERROR -16 /* unknown card error */
+#define SD_ERR_CARD_TYPE -17 /* non support card type */
+#define SD_ERR_NO_CARD -18 /* no card */
+#define SD_ERR_ILL_READ -19 /* illegal buffer read */
+#define SD_ERR_ILL_WRITE -20 /* illegal buffer write */
+#define SD_ERR_AKE_SEQ -21 /* the sequence of authentication process */
+#define SD_ERR_OVERWRITE -22 /* CID/CSD overwrite error */
+/* 23-29 */
+#define SD_ERR_CPU_IF -30 /* target CPU interface function error */
+#define SD_ERR_STOP -31 /* user stop */
+/* 32-49 */
+#define SD_ERR_CSD_VER -50 /* CSD register version error */
+#define SD_ERR_SCR_VER -51 /* SCR register version error */
+#define SD_ERR_FILE_FORMAT -52 /* CSD register file format error */
+#define SD_ERR_NOTSUP_CMD -53 /* not supported command */
+/* 54-59 */
+#define SD_ERR_ILL_FUNC -60 /* invalid function request error */
+#define SD_ERR_IO_VERIFY -61 /* direct write verify error */
+#define SD_ERR_IO_CAPAB -62 /* IO capability error */
+/* 63-69 */
+#define SD_ERR_IFCOND_VER -70 /* Interface condition version error */
+#define SD_ERR_IFCOND_VOLT -71 /* Interface condition voltage error */
+#define SD_ERR_IFCOND_ECHO -72 /* Interface condition echo back pattern error */
+/* 73-79 */
+#define SD_ERR_OUT_OF_RANGE -80 /* the argument was out of range */
+#define SD_ERR_ADDRESS_ERROR -81 /* misassigned address */
+#define SD_ERR_BLOCK_LEN_ERROR -82 /* transfered block length is not allowed */
+#define SD_ERR_ILLEGAL_COMMAND -83 /* Command not legal */
+#define SD_ERR_RESERVED_ERROR18 -84 /* Reserved bit 18 Error */
+#define SD_ERR_RESERVED_ERROR17 -85 /* Reserved bit 17 Error */
+#define SD_ERR_CMD_ERROR -86 /* SD_INFO2 bit 0 CMD error */
+#define SD_ERR_CBSY_ERROR -87 /* SD_INFO2 bit 14 CMD Type Reg Busy error */
+#define SD_ERR_NO_RESP_ERROR -88 /* SD_INFO1 bit 0 No Response error */
+/* 89 */
+/* 90-95 */
+#define SD_ERR_ERROR -96 /* SDIO ERROR */
+#define SD_ERR_FUNCTION_NUMBER -97 /* SDIO FUNCTION NUMBER ERROR */
+#define SD_ERR_COM_CRC_ERROR -98 /* SDIO CRC ERROR */
+#define SD_ERR_INTERNAL -99 /* driver software internal error */
+
+/* ---- driver mode ---- */
+#define SD_MODE_POLL 0x0000ul /* status check mode is software polling */
+#define SD_MODE_HWINT 0x0001ul /* status check mode is hardware interrupt */
+#define SD_MODE_SW 0x0000ul /* data transfer mode is software */
+#define SD_MODE_DMA 0x0002ul /* data transfer mode is DMA */
+#define SD_MODE_DMA_64 0x0004ul /* data transfer mode is DMA with 64 byte burst mode */
+
+/* ---- support mode ---- */
+#define SD_MODE_MEM 0x0000ul /* memory cards only are supported */
+#define SD_MODE_IO 0x0010ul /* memory and io cards are supported */
+#define SD_MODE_COMBO 0x0030ul /* memory ,io and combo cards are supported */
+#define SD_MODE_DS 0x0000ul /* only default speed mode is supported */
+#define SD_MODE_HS 0x0040ul /* high speed mode is also supported */
+#define SD_MODE_VER1X 0x0000ul /* ver1.1 host */
+#define SD_MODE_VER2X 0x0080ul /* ver2.x host (high capacity and dual voltage) */
+#define SD_MODE_1BIT 0x0100ul /* SD Mode 1bit only is supported */
+#define SD_MODE_4BIT 0x0000ul /* SD Mode 1bit and 4bit is supported */
+
+/* ---- media voltage ---- */
+#define SD_VOLT_1_7 0x00000010ul /* low voltage card minimum */
+#define SD_VOLT_1_8 0x00000020ul
+#define SD_VOLT_1_9 0x00000040ul
+#define SD_VOLT_2_0 0x00000080ul
+#define SD_VOLT_2_1 0x00000100ul /* basic communication minimum */
+#define SD_VOLT_2_2 0x00000200ul
+#define SD_VOLT_2_3 0x00000400ul
+#define SD_VOLT_2_4 0x00000800ul
+#define SD_VOLT_2_5 0x00001000ul
+#define SD_VOLT_2_6 0x00002000ul
+#define SD_VOLT_2_7 0x00004000ul
+#define SD_VOLT_2_8 0x00008000ul /* memory access minimum */
+#define SD_VOLT_2_9 0x00010000ul
+#define SD_VOLT_3_0 0x00020000ul
+#define SD_VOLT_3_1 0x00040000ul
+#define SD_VOLT_3_2 0x00080000ul
+#define SD_VOLT_3_3 0x00100000ul
+#define SD_VOLT_3_4 0x00200000ul
+#define SD_VOLT_3_5 0x00400000ul
+#define SD_VOLT_3_6 0x00800000ul
+
+/* ---- memory card write mode ---- */
+#define SD_WRITE_WITH_PREERASE 0x0000u /* pre-erease write */
+#define SD_WRITE_OVERWRITE 0x0001u /* overwrite */
+
+/* ---- io register write mode ---- */
+#define SD_IO_SIMPLE_WRITE 0x0000u /* just write */
+#define SD_IO_VERIFY_WRITE 0x0001u /* read after write */
+
+/* ---- io operation code ---- */
+#define SD_IO_FIXED_ADDR 0x0000u /* R/W fixed address */
+#define SD_IO_INCREMENT_ADDR 0x0001u /* R/W increment address */
+#define SD_IO_FORCE_BYTE 0x0010u /* byte access only */
+
+ /* ---- media type ---- */
+#define SD_MEDIA_UNKNOWN 0x0000u /* unknown media */
+#define SD_MEDIA_MMC 0x0010u /* MMC card */
+#define SD_MEDIA_SD 0x0020u /* SD Memory card */
+#define SD_MEDIA_IO 0x0001u /* SD IO card */
+#define SD_MEDIA_MEM 0x0030u /* Memory card */
+#define SD_MEDIA_COMBO 0x0021u /* SD COMBO card */
+#define SD_MEDIA_EMBEDDED 0x8000u /* embedded media */
+
+/* ---- write protect info --- */
+#define SD_WP_OFF 0x0000u /* card is not write protect */
+#define SD_WP_HW 0x0001u /* card is H/W write protect */
+#define SD_WP_TEMP 0x0002u /* card is TEMP_WRITE_PROTECT */
+#define SD_WP_PERM 0x0004u /* card is PERM_WRITE_PROTECT */
+#define SD_WP_ROM 0x0010u /* card is SD-ROM */
+
+/* ---- SD clock div ---- */ /* IMCLK is host controller clock */
+#define SD_DIV_512 0x0080u /* SDCLOCK = IMCLK/512 */
+#define SD_DIV_256 0x0040u /* SDCLOCK = IMCLK/256 */
+#define SD_DIV_128 0x0020u /* SDCLOCK = IMCLK/128 */
+#define SD_DIV_64 0x0010u /* SDCLOCK = IMCLK/64 */
+#define SD_DIV_32 0x0008u /* SDCLOCK = IMCLK/32 */
+#define SD_DIV_16 0x0004u /* SDCLOCK = IMCLK/16 */
+#define SD_DIV_8 0x0002u /* SDCLOCK = IMCLK/8 */
+#define SD_DIV_4 0x0001u /* SDCLOCK = IMCLK/4 */
+#define SD_DIV_2 0x0000u /* SDCLOCK = IMCLK/2 */
+#define SD_DIV_1 0x00FFu /* SDCLOCK = IMCLK (option) */
+
+/* ---- SD clock define ---- */ /* max frequency */
+#define SD_CLK_400kHz 0x0000u /* 400kHz */
+#define SD_CLK_1MHz 0x0001u /* 1MHz */
+#define SD_CLK_5MHz 0x0002u /* 5MHz */
+#define SD_CLK_10MHz 0x0003u /* 10MHz */
+#define SD_CLK_20MHz 0x0004u /* 20MHz */
+#define SD_CLK_25MHz 0x0005u /* 25MHz */
+#define SD_CLK_50MHz 0x0006u /* 50MHz (phys spec ver1.10) */
+
+/* ---- speed class ---- */
+#define SD_SPEED_CLASS_0 0x00u /* not defined, or less than ver2.0 */
+#define SD_SPEED_CLASS_2 0x01u /* 2MB/sec */
+#define SD_SPEED_CLASS_4 0x02u /* 4MB/sec */
+#define SD_SPEED_CLASS_6 0x03u /* 6MB/sec */
+
+/* ---- IO initialize flags define ---- */ /* add for IO */
+#define SD_IO_INT_ENAB 0x10u /* interrupt enable */
+#define SD_IO_POWER_INIT 0x04u /* power on initialized */
+#define SD_IO_MEM_INIT 0x02u /* memory initialized */
+#define SD_IO_FUNC_INIT 0x01u /* io func initialized */
+
+/* ---- IO function's information ---- */ /* add for IO */
+#define SD_IO_FUNC_READY 0x80u /* io redy */
+#define SD_IO_FUNC_NUM 0x70u /* number of io func */
+#define SD_IO_FUNC_EXISTS 0x04u /* memory present */
+
+/* ---- SD port mode ---- */
+#define SD_PORT_SERIAL 0x0000u /* 1bit mode */
+#define SD_PORT_PARALLEL 0x0001u /* 4bits mode */
+
+/* ---- SD Card detect port ---- */
+#define SD_CD_SOCKET 0x0000u /* CD pin */
+#define SD_CD_DAT3 0x0001u /* DAT3 pin */
+
+/* ---- SD Card detect interrupt ---- */
+#define SD_CD_INT_DISABLE 0x0000u /* card detect interrupt disable */
+#define SD_CD_INT_ENABLE 0x0001u /* card detect interrupt enable */
+
+/* ---- format mode ---- */
+#define SD_FORMAT_QUICK 0x0000u /* quick format */
+#define SD_FORMAT_FULL 0x0001u /* full format */
+
+/* ---- lock/unlock mode ---- */
+#define SD_FORCE_ERASE 0x08
+#define SD_LOCK_CARD 0x04
+#define SD_UNLOCK_CARD 0x00
+#define SD_CLR_PWD 0x02
+#define SD_SET_PWD 0x01
+
+/* ==== API prototype ===== */
+/* ---- access library I/F ---- */
+int sd_init(int sd_port, unsigned long base, void *workarea, int cd_port);
+int sd_cd_int(int sd_port, int enable,int (*callback)(int, int));
+int sd_check_media(int sd_port);
+int sd_format(int sd_port, int mode,int (*callback)(unsigned long,unsigned long));
+int sd_format2(int sd_port, int mode,unsigned long volserial,int (*callback)(unsigned long,unsigned long));
+int sd_mount(int sd_port, unsigned long mode,unsigned long voltage);
+int sd_read_sect(int sd_port, unsigned char *buff,unsigned long psn,long cnt);
+int sd_write_sect(int sd_port, unsigned char *buff,unsigned long psn,long cnt,int writemode);
+int sd_get_type(int sd_port, unsigned char *type,unsigned char *speed,unsigned char *capa);
+int sd_get_size(int sd_port, unsigned long *user,unsigned long *protect);
+int sd_iswp(int sd_port);
+int sd_unmount(int sd_port);
+void sd_stop(int sd_port);
+int sd_set_intcallback(int sd_port, int (*callback)(int, int));
+void sd_int_handler(int sd_port);
+int sd_get_error(int sd_port);
+int sd_check_int(int sd_port);
+int sd_get_reg(int sd_port, unsigned char *ocr,unsigned char *cid,unsigned char *csd, unsigned char *dsr,unsigned char *scr);
+int sd_get_rca(int sd_port, unsigned char *rca);
+int sd_get_sdstatus(int sd_port, unsigned char *sdstatus);
+int sd_get_speed(int sd_port, unsigned char *clss,unsigned char *move);
+int sd_finalize(int sd_port);
+int sd_set_seccnt(int sd_port, short sectors);
+int sd_get_seccnt(int sd_port);
+int sd_get_ver(int sd_port, unsigned short *sdhi_ver,char *sddrv_ver);
+int sd_set_cdtime(int sd_port, unsigned short cdtime);
+int sd_set_responsetime(int sd_port, unsigned short responsetime);
+int sd_set_buffer(int sd_port, void *buff,unsigned long size);
+int sd_inactive(int sd_port);
+int sd_set_softwp(int sd_port, int is_set,unsigned long data);
+int sd_set_tmpwp(int sd_port, int is_set);
+int sd_lock_unlock(int sd_port, unsigned char code,unsigned char *pwd,unsigned char len);
+
+int esd_get_partition_id(int sd_port, int *id);
+int esd_select_partition(int sd_port, int id);
+int esd_query_partition(int sd_port, int sub, unsigned char *data);
+
+int sdio_read_direct(int sd_port, unsigned char *buff,unsigned long func,unsigned long adr);
+int sdio_write_direct(int sd_port, unsigned char *buff,unsigned long func,unsigned long adr,unsigned long raw_flag);
+int sdio_check_int(int sd_port);
+void sdio_int_handler(int sd_port);
+int sdio_set_intcallback(int sd_port, int (*callback)(int));
+int sdio_enable_int(int sd_port);
+int sdio_disable_int(int sd_port);
+int sdio_read(int sd_port, unsigned char *buff,unsigned long func,unsigned long adr,long cnt,unsigned long op_code);
+int sdio_write(int sd_port, unsigned char *buff,unsigned long func,unsigned long adr,long cnt,unsigned long op_code);
+int sdio_reset(int sd_port);
+int sdio_get_ioocr(int sd_port, unsigned long *ioocr);
+int sdio_get_ioinfo(int sd_port, unsigned char *ioinfo);
+int sdio_get_cia(int sd_port, unsigned char *reg, unsigned char *cis, unsigned long func_num, long cnt);
+int sdio_set_enable(int sd_port, unsigned char func_bit);
+int sdio_get_ready(int sd_port, unsigned char *func_bit);
+int sdio_set_int(int sd_port, unsigned char func_bit,int enab);
+int sdio_get_int(int sd_port, unsigned char *func_bit,int *enab);
+int sdio_set_blocklen(int sd_port, unsigned short len, unsigned long func_num);
+int sdio_get_blocklen(int sd_port, unsigned short *len, unsigned long func_num);
+void sdio_abort(int sd_port, unsigned long func_num);
+int sdio_set_blkcnt(int sd_port, short blocks);
+int sdio_get_blkcnt(int sd_port);
+
+/* ---- target CPU I/F ---- */
+int sddev_init(int sd_port);
+int sddev_power_on(int sd_port);
+int sddev_power_off(int sd_port);
+int sddev_read_data(int sd_port, unsigned char *buff,unsigned long reg_addr,long num);
+int sddev_write_data(int sd_port, unsigned char *buff,unsigned long reg_addr,long num);
+unsigned int sddev_get_clockdiv(int sd_port, int clock);
+int sddev_set_port(int sd_port, int mode);
+int sddev_int_wait(int sd_port, int msec);
+int sddev_init_dma(int sd_port, unsigned long buffadr,unsigned long regadr,long cnt,int dir);
+int sddev_wait_dma_end(int sd_port, long cnt);
+int sddev_disable_dma(int sd_port);
+int sddev_finalize(int sd_port);
+int sddev_loc_cpu(int sd_port);
+int sddev_unl_cpu(int sd_port);
+int sddev_cmd0_sdio_mount(int sd_port);
+int sddev_cmd8_sdio_mount(int sd_port);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SDDRV_H_ */
+
+/* End of File */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h Mon Mar 18 11:46:29 2019 +0000
@@ -0,0 +1,923 @@
+/******************************************************************************
+ * @file VK_RZ_A1H.h
+ * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
+ * @version V1.00
+ * @data 10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __VK_RZ_A1H_H__
+#define __VK_RZ_A1H_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/****** SGI Interrupts Numbers ****************************************/
+ SGI0_IRQn = 0,
+ SGI1_IRQn = 1,
+ SGI2_IRQn = 2,
+ SGI3_IRQn = 3,
+ SGI4_IRQn = 4,
+ SGI5_IRQn = 5,
+ SGI6_IRQn = 6,
+ SGI7_IRQn = 7,
+ SGI8_IRQn = 8,
+ SGI9_IRQn = 9,
+ SGI10_IRQn = 10,
+ SGI11_IRQn = 11,
+ SGI12_IRQn = 12,
+ SGI13_IRQn = 13,
+ SGI14_IRQn = 14,
+ SGI15_IRQn = 15,
+
+/****** Cortex-A9 Processor Exceptions Numbers ****************************************/
+ /* 16 - 578 */
+ PMUIRQ0_IRQn = 16,
+ COMMRX0_IRQn = 17,
+ COMMTX0_IRQn = 18,
+ CTIIRQ0_IRQn = 19,
+
+ IRQ0_IRQn = 32,
+ IRQ1_IRQn = 33,
+ IRQ2_IRQn = 34,
+ IRQ3_IRQn = 35,
+ IRQ4_IRQn = 36,
+ IRQ5_IRQn = 37,
+ IRQ6_IRQn = 38,
+ IRQ7_IRQn = 39,
+
+ PL310ERR_IRQn = 40,
+
+ DMAINT0_IRQn = 41, /*!< DMAC Interrupt */
+ DMAINT1_IRQn = 42, /*!< DMAC Interrupt */
+ DMAINT2_IRQn = 43, /*!< DMAC Interrupt */
+ DMAINT3_IRQn = 44, /*!< DMAC Interrupt */
+ DMAINT4_IRQn = 45, /*!< DMAC Interrupt */
+ DMAINT5_IRQn = 46, /*!< DMAC Interrupt */
+ DMAINT6_IRQn = 47, /*!< DMAC Interrupt */
+ DMAINT7_IRQn = 48, /*!< DMAC Interrupt */
+ DMAINT8_IRQn = 49, /*!< DMAC Interrupt */
+ DMAINT9_IRQn = 50, /*!< DMAC Interrupt */
+ DMAINT10_IRQn = 51, /*!< DMAC Interrupt */
+ DMAINT11_IRQn = 52, /*!< DMAC Interrupt */
+ DMAINT12_IRQn = 53, /*!< DMAC Interrupt */
+ DMAINT13_IRQn = 54, /*!< DMAC Interrupt */
+ DMAINT14_IRQn = 55, /*!< DMAC Interrupt */
+ DMAINT15_IRQn = 56, /*!< DMAC Interrupt */
+ DMAERR_IRQn = 57, /*!< DMAC Interrupt */
+
+ /* 58-72 Reserved */
+
+ USBI0_IRQn = 73,
+ USBI1_IRQn = 74,
+
+ S0_VI_VSYNC0_IRQn = 75,
+ S0_LO_VSYNC0_IRQn = 76,
+ S0_VSYNCERR0_IRQn = 77,
+ GR3_VLINE0_IRQn = 78,
+ S0_VFIELD0_IRQn = 79,
+ IV1_VBUFERR0_IRQn = 80,
+ IV3_VBUFERR0_IRQn = 81,
+ IV5_VBUFERR0_IRQn = 82,
+ IV6_VBUFERR0_IRQn = 83,
+ S0_WLINE0_IRQn = 84,
+ S1_VI_VSYNC0_IRQn = 85,
+ S1_LO_VSYNC0_IRQn = 86,
+ S1_VSYNCERR0_IRQn = 87,
+ S1_VFIELD0_IRQn = 88,
+ IV2_VBUFERR0_IRQn = 89,
+ IV4_VBUFERR0_IRQn = 90,
+ S1_WLINE0_IRQn = 91,
+ OIR_VI_VSYNC0_IRQn = 92,
+ OIR_LO_VSYNC0_IRQn = 93,
+ OIR_VSYNCERR0_IRQn = 94,
+ OIR_VFIELD0_IRQn = 95,
+ IV7_VBUFERR0_IRQn = 96,
+ IV8_VBUFERR0_IRQn = 97,
+ /* 98 Reserved */
+ S0_VI_VSYNC1_IRQn = 99,
+ S0_LO_VSYNC1_IRQn = 100,
+ S0_VSYNCERR1_IRQn = 101,
+ GR3_VLINE1_IRQn = 102,
+ S0_VFIELD1_IRQn = 103,
+ IV1_VBUFERR1_IRQn = 104,
+ IV3_VBUFERR1_IRQn = 105,
+ IV5_VBUFERR1_IRQn = 106,
+ IV6_VBUFERR1_IRQn = 107,
+ S0_WLINE1_IRQn = 108,
+ S1_VI_VSYNC1_IRQn = 109,
+ S1_LO_VSYNC1_IRQn = 110,
+ S1_VSYNCERR1_IRQn = 111,
+ S1_VFIELD1_IRQn = 112,
+ IV2_VBUFERR1_IRQn = 113,
+ IV4_VBUFERR1_IRQn = 114,
+ S1_WLINE1_IRQn = 115,
+ OIR_VI_VSYNC1_IRQn = 116,
+ OIR_LO_VSYNC1_IRQn = 117,
+ OIR_VSYNCERR1_IRQn = 118,
+ OIR_VFIELD1_IRQn = 119,
+ IV7_VBUFERR1_IRQn = 120,
+ IV8_VBUFERR1_IRQn = 121,
+ /* Reserved = 122 */
+
+ IMRDI_IRQn = 123,
+ IMR2I0_IRQn = 124,
+ IMR2I1_IRQn = 125,
+
+ JEDI_IRQn = 126,
+ JDTI_IRQn = 127,
+
+ CMP0_IRQn = 128,
+ CMP1_IRQn = 129,
+
+ INT0_IRQn = 130,
+ INT1_IRQn = 131,
+ INT2_IRQn = 132,
+ INT3_IRQn = 133,
+
+ OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */
+ OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */
+
+ CMI_IRQn = 136,
+ WTOUT_IRQn = 137,
+
+ ITI_IRQn = 138,
+
+ TGI0A_IRQn = 139,
+ TGI0B_IRQn = 140,
+ TGI0C_IRQn = 141,
+ TGI0D_IRQn = 142,
+ TGI0V_IRQn = 143,
+ TGI0E_IRQn = 144,
+ TGI0F_IRQn = 145,
+ TGI1A_IRQn = 146,
+ TGI1B_IRQn = 147,
+ TGI1V_IRQn = 148,
+ TGI1U_IRQn = 149,
+ TGI2A_IRQn = 150,
+ TGI2B_IRQn = 151,
+ TGI2V_IRQn = 152,
+ TGI2U_IRQn = 153,
+ TGI3A_IRQn = 154,
+ TGI3B_IRQn = 155,
+ TGI3C_IRQn = 156,
+ TGI3D_IRQn = 157,
+ TGI3V_IRQn = 158,
+ TGI4A_IRQn = 159,
+ TGI4B_IRQn = 160,
+ TGI4C_IRQn = 161,
+ TGI4D_IRQn = 162,
+ TGI4V_IRQn = 163,
+
+ CMI1_IRQn = 164,
+ CMI2_IRQn = 165,
+
+ SGDEI0_IRQn = 166,
+ SGDEI1_IRQn = 167,
+ SGDEI2_IRQn = 168,
+ SGDEI3_IRQn = 169,
+
+ ADI_IRQn = 170,
+ LMTI_IRQn = 171,
+
+ SSII0_IRQn = 172, /*!< SSIF Interrupt */
+ SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */
+ SSITXI0_IRQn = 174, /*!< SSIF Interrupt */
+ SSII1_IRQn = 175, /*!< SSIF Interrupt */
+ SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */
+ SSITXI1_IRQn = 177, /*!< SSIF Interrupt */
+ SSII2_IRQn = 178, /*!< SSIF Interrupt */
+ SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */
+ SSII3_IRQn = 180, /*!< SSIF Interrupt */
+ SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */
+ SSITXI3_IRQn = 182, /*!< SSIF Interrupt */
+ SSII4_IRQn = 183, /*!< SSIF Interrupt */
+ SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */
+ SSII5_IRQn = 185, /*!< SSIF Interrupt */
+ SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */
+ SSITXI5_IRQn = 187, /*!< SSIF Interrupt */
+
+ SPDIFI_IRQn = 188,
+
+ INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */
+ INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */
+ INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */
+ INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */
+ INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */
+ INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */
+ INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */
+ INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */
+ INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */
+ INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */
+ INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */
+ INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */
+ INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */
+ INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */
+ INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */
+ INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */
+ INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */
+ INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */
+ INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */
+ INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */
+ INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */
+ INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */
+ INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */
+ INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */
+ INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */
+ INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */
+ INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */
+ INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */
+ INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */
+ INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */
+ INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */
+ INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */
+
+ SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */
+ SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */
+ SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */
+ SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */
+ SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */
+ SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */
+ SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */
+ SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */
+ SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */
+ SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */
+ SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */
+ SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */
+ SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */
+ SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */
+ SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */
+ SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */
+ SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */
+ SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */
+ SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */
+ SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */
+ SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */
+ SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */
+ SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */
+ SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */
+ SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */
+ SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */
+ SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */
+ SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */
+ SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */
+ SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */
+ SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */
+ SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */
+
+ INTRCANGERR_IRQn = 253,
+ INTRCANGRECC_IRQn = 254,
+ INTRCAN0REC_IRQn = 255,
+ INTRCAN0ERR_IRQn = 256,
+ INTRCAN0TRX_IRQn = 257,
+ INTRCAN1REC_IRQn = 258,
+ INTRCAN1ERR_IRQn = 259,
+ INTRCAN1TRX_IRQn = 260,
+ INTRCAN2REC_IRQn = 261,
+ INTRCAN2ERR_IRQn = 262,
+ INTRCAN2TRX_IRQn = 263,
+ INTRCAN3REC_IRQn = 264,
+ INTRCAN3ERR_IRQn = 265,
+ INTRCAN3TRX_IRQn = 266,
+ INTRCAN4REC_IRQn = 267,
+ INTRCAN4ERR_IRQn = 268,
+ INTRCAN4TRX_IRQn = 269,
+
+ RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */
+ RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */
+ RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */
+ RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */
+ RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */
+ RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */
+ RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */
+ RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */
+ RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */
+ RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */
+ RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */
+ RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */
+ RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */
+ RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */
+ RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */
+
+ IEBBTD_IRQn = 285,
+ IEBBTERR_IRQn = 286,
+ IEBBTSTA_IRQn = 287,
+ IEBBTV_IRQn = 288,
+
+ ISY_IRQn = 289,
+ IERR_IRQn = 290,
+ ITARG_IRQn = 291,
+ ISEC_IRQn = 292,
+ IBUF_IRQn = 293,
+ IREADY_IRQn = 294,
+
+ STERB_IRQn = 295,
+ FLTENDI_IRQn = 296,
+ FLTREQ0I_IRQn = 297,
+ FLTREQ1I_IRQn = 298,
+
+ MMC0_IRQn = 299,
+ MMC1_IRQn = 300,
+ MMC2_IRQn = 301,
+
+ SDHI0_3_IRQn = 302,
+ SDHI0_0_IRQn = 303,
+ SDHI0_1_IRQn = 304,
+ SDHI1_3_IRQn = 305,
+ SDHI1_0_IRQn = 306,
+ SDHI1_1_IRQn = 307,
+
+ ARM_IRQn = 308,
+ PRD_IRQn = 309,
+ CUP_IRQn = 310,
+
+ SCUAI0_IRQn = 311,
+ SCUAI1_IRQn = 312,
+ SCUFDI0_IRQn = 313,
+ SCUFDI1_IRQn = 314,
+ SCUFDI2_IRQn = 315,
+ SCUFDI3_IRQn = 316,
+ SCUFUI0_IRQn = 317,
+ SCUFUI1_IRQn = 318,
+ SCUFUI2_IRQn = 319,
+ SCUFUI3_IRQn = 320,
+ SCUDVI0_IRQn = 321,
+ SCUDVI1_IRQn = 322,
+ SCUDVI2_IRQn = 323,
+ SCUDVI3_IRQn = 324,
+
+ MLB_CINT_IRQn = 325,
+ MLB_SINT_IRQn = 326,
+
+ DRC10_IRQn = 327,
+ DRC11_IRQn = 328,
+
+ /* 329-330 Reserved */
+
+ LINI0_INT_T_IRQn = 331,
+ LINI0_INT_R_IRQn = 332,
+ LINI0_INT_S_IRQn = 333,
+ LINI0_INT_M_IRQn = 334,
+ LINI1_INT_T_IRQn = 335,
+ LINI1_INT_R_IRQn = 336,
+ LINI1_INT_S_IRQn = 337,
+ LINI1_INT_M_IRQn = 338,
+
+ /* 339-346 Reserved */
+
+ SCIERI0_IRQn = 347,
+ SCIRXI0_IRQn = 348,
+ SCITXI0_IRQn = 349,
+ SCITEI0_IRQn = 350,
+ SCIERI1_IRQn = 351,
+ SCIRXI1_IRQn = 352,
+ SCITXI1_IRQn = 353,
+ SCITEI1_IRQn = 354,
+
+ AVBI_DATA = 355,
+ AVBI_ERROR = 356,
+ AVBI_MANAGE = 357,
+ AVBI_MAC = 358,
+
+ ETHERI_IRQn = 359,
+
+ /* 360-363 Reserved */
+
+ CEUI_IRQn = 364,
+
+ /* 365-380 Reserved */
+
+ H2XMLB_ERRINT_IRQn = 381,
+ H2XIC1_ERRINT_IRQn = 382,
+ X2HPERI1_ERRINT_IRQn = 383,
+ X2HPERR2_ERRINT_IRQn = 384,
+ X2HPERR34_ERRINT_IRQn= 385,
+ X2HPERR5_ERRINT_IRQn = 386,
+ X2HPERR67_ERRINT_IRQn= 387,
+ X2HDBGR_ERRINT_IRQn = 388,
+ X2HBSC_ERRINT_IRQn = 389,
+ X2HSPI1_ERRINT_IRQn = 390,
+ X2HSPI2_ERRINT_IRQn = 391,
+ PRRI_IRQn = 392,
+
+ IFEI0_IRQn = 393,
+ OFFI0_IRQn = 394,
+ PFVEI0_IRQn = 395,
+ IFEI1_IRQn = 396,
+ OFFI1_IRQn = 397,
+ PFVEI1_IRQn = 398,
+
+ /* 399-415 Reserved */
+
+ TINT0_IRQn = 416,
+ TINT1_IRQn = 417,
+ TINT2_IRQn = 418,
+ TINT3_IRQn = 419,
+ TINT4_IRQn = 420,
+ TINT5_IRQn = 421,
+ TINT6_IRQn = 422,
+ TINT7_IRQn = 423,
+ TINT8_IRQn = 424,
+ TINT9_IRQn = 425,
+ TINT10_IRQn = 426,
+ TINT11_IRQn = 427,
+ TINT12_IRQn = 428,
+ TINT13_IRQn = 429,
+ TINT14_IRQn = 430,
+ TINT15_IRQn = 431,
+ TINT16_IRQn = 432,
+ TINT17_IRQn = 433,
+ TINT18_IRQn = 434,
+ TINT19_IRQn = 435,
+ TINT20_IRQn = 436,
+ TINT21_IRQn = 437,
+ TINT22_IRQn = 438,
+ TINT23_IRQn = 439,
+ TINT24_IRQn = 440,
+ TINT25_IRQn = 441,
+ TINT26_IRQn = 442,
+ TINT27_IRQn = 443,
+ TINT28_IRQn = 444,
+ TINT29_IRQn = 445,
+ TINT30_IRQn = 446,
+ TINT31_IRQn = 447,
+ TINT32_IRQn = 448,
+ TINT33_IRQn = 449,
+ TINT34_IRQn = 450,
+ TINT35_IRQn = 451,
+ TINT36_IRQn = 452,
+ TINT37_IRQn = 453,
+ TINT38_IRQn = 454,
+ TINT39_IRQn = 455,
+ TINT40_IRQn = 456,
+ TINT41_IRQn = 457,
+ TINT42_IRQn = 458,
+ TINT43_IRQn = 459,
+ TINT44_IRQn = 460,
+ TINT45_IRQn = 461,
+ TINT46_IRQn = 462,
+ TINT47_IRQn = 463,
+ TINT48_IRQn = 464,
+ TINT49_IRQn = 465,
+ TINT50_IRQn = 466,
+ TINT51_IRQn = 467,
+ TINT52_IRQn = 468,
+ TINT53_IRQn = 469,
+ TINT54_IRQn = 470,
+ TINT55_IRQn = 471,
+ TINT56_IRQn = 472,
+ TINT57_IRQn = 473,
+ TINT58_IRQn = 474,
+ TINT59_IRQn = 475,
+ TINT60_IRQn = 476,
+ TINT61_IRQn = 477,
+ TINT62_IRQn = 478,
+ TINT63_IRQn = 479,
+ TINT64_IRQn = 480,
+ TINT65_IRQn = 481,
+ TINT66_IRQn = 482,
+ TINT67_IRQn = 483,
+ TINT68_IRQn = 484,
+ TINT69_IRQn = 485,
+ TINT70_IRQn = 486,
+ TINT71_IRQn = 487,
+ TINT72_IRQn = 488,
+ TINT73_IRQn = 489,
+ TINT74_IRQn = 490,
+ TINT75_IRQn = 491,
+ TINT76_IRQn = 492,
+ TINT77_IRQn = 493,
+ TINT78_IRQn = 494,
+ TINT79_IRQn = 495,
+ TINT80_IRQn = 496,
+ TINT81_IRQn = 497,
+ TINT82_IRQn = 498,
+ TINT83_IRQn = 499,
+ TINT84_IRQn = 500,
+ TINT85_IRQn = 501,
+ TINT86_IRQn = 502,
+ TINT87_IRQn = 503,
+ TINT88_IRQn = 504,
+ TINT89_IRQn = 505,
+ TINT90_IRQn = 506,
+ TINT91_IRQn = 507,
+ TINT92_IRQn = 508,
+ TINT93_IRQn = 509,
+ TINT94_IRQn = 510,
+ TINT95_IRQn = 511,
+ TINT96_IRQn = 512,
+ TINT97_IRQn = 513,
+ TINT98_IRQn = 514,
+ TINT99_IRQn = 515,
+ TINT100_IRQn = 516,
+ TINT101_IRQn = 517,
+ TINT102_IRQn = 518,
+ TINT103_IRQn = 519,
+ TINT104_IRQn = 520,
+ TINT105_IRQn = 521,
+ TINT106_IRQn = 522,
+ TINT107_IRQn = 523,
+ TINT108_IRQn = 524,
+ TINT109_IRQn = 525,
+ TINT110_IRQn = 526,
+ TINT111_IRQn = 527,
+ TINT112_IRQn = 528,
+ TINT113_IRQn = 529,
+ TINT114_IRQn = 530,
+ TINT115_IRQn = 531,
+ TINT116_IRQn = 532,
+ TINT117_IRQn = 533,
+ TINT118_IRQn = 534,
+ TINT119_IRQn = 535,
+ TINT120_IRQn = 536,
+ TINT121_IRQn = 537,
+ TINT122_IRQn = 538,
+ TINT123_IRQn = 539,
+ TINT124_IRQn = 540,
+ TINT125_IRQn = 541,
+ TINT126_IRQn = 542,
+ TINT127_IRQn = 543,
+ TINT128_IRQn = 544,
+ TINT129_IRQn = 545,
+ TINT130_IRQn = 546,
+ TINT131_IRQn = 547,
+ TINT132_IRQn = 548,
+ TINT133_IRQn = 549,
+ TINT134_IRQn = 550,
+ TINT135_IRQn = 551,
+ TINT136_IRQn = 552,
+ TINT137_IRQn = 553,
+ TINT138_IRQn = 554,
+ TINT139_IRQn = 555,
+ TINT140_IRQn = 556,
+ TINT141_IRQn = 557,
+ TINT142_IRQn = 558,
+ TINT143_IRQn = 559,
+ TINT144_IRQn = 560,
+ TINT145_IRQn = 561,
+ TINT146_IRQn = 562,
+ TINT147_IRQn = 563,
+ TINT148_IRQn = 564,
+ TINT149_IRQn = 565,
+ TINT150_IRQn = 566,
+ TINT151_IRQn = 567,
+ TINT152_IRQn = 568,
+ TINT153_IRQn = 569,
+ TINT154_IRQn = 570,
+ TINT155_IRQn = 571,
+ TINT156_IRQn = 572,
+ TINT157_IRQn = 573,
+ TINT158_IRQn = 574,
+ TINT159_IRQn = 575,
+ TINT160_IRQn = 576,
+ TINT161_IRQn = 577,
+ TINT162_IRQn = 578,
+ TINT163_IRQn = 579,
+ TINT164_IRQn = 580,
+ TINT165_IRQn = 581,
+ TINT166_IRQn = 582,
+ TINT167_IRQn = 583,
+ TINT168_IRQn = 584,
+ TINT169_IRQn = 585,
+ TINT170_IRQn = 586
+
+} IRQn_Type;
+
+#define RZ_A1_IRQ_MAX TINT170_IRQn
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+
+#define RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
+#define RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */
+#define RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */
+#define RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */
+#define RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */
+#define RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */
+#define RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */
+#define RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */
+#define RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */
+#define RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
+#define RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
+#define RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
+#define RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
+#define RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */
+#define RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */
+#define RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */
+#define RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */
+#define RZ_A1_PRIVATE_TIMER (0x00000600UL + 0x82000000UL) /*!< (PTIM ) Base Address */
+#define GIC_DISTRIBUTOR_BASE RZ_A1_GIC_DISTRIBUTOR_BASE
+#define GIC_INTERFACE_BASE RZ_A1_GIC_INTERFACE_BASE
+#define L2C_310_BASE RZ_A1_PL310_BASE
+#define TIMER_BASE RZ_A1_PRIVATE_TIMER
+
+/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */
+#define __CA_REV 0x0000U /*!< Core revision r0p0 */
+#define __CORTEX_A 9U /*!< Cortex-A9 Core */
+#if (__FPU_PRESENT != 1)
+#undef __FPU_PRESENT
+#define __FPU_PRESENT 1U /* FPU present */
+#endif
+#define __GIC_PRESENT 1U /* GIC present */
+#define __TIM_PRESENT 0U /* TIM present */
+#define __L2C_PRESENT 1U /* L2C present */
+
+#include "core_ca.h"
+#include "nvic_wrapper.h"
+#include <system_VK_RZ_A1H.h>
+#include "iodefine.h"
+
+/******************************************************************************/
+/* Clock Settings */
+/******************************************************************************/
+/*
+ * Clock Mode 0 settings
+ * SW1-4(MD_CLK):ON
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1035
+ * CLKEN2 = 0b - unstable
+ * CLKEN[1:0]=01b - Output, Low, Low
+ * IFC[1:0] =00b - CPU clock is 1/1 PLL clock
+ * FRQCR2=0x0001
+ * GFC[1:0] =01b - Graphic clock is 2/3 bus clock
+ */
+#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u)
+#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u)
+#define CM0_RENESAS_RZ_A1_I_CLK (400000000u)
+#define CM0_RENESAS_RZ_A1_G_CLK (266666666u)
+#define CM0_RENESAS_RZ_A1_B_CLK (133333333u)
+#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
+#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
+
+/*
+ * Clock Mode 1 settings
+ * SW1-4(MD_CLK):OFF
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1335
+ * CLKEN2 = 0b - unstable
+ * CLKEN[1:0]=01b - Output, Low, Low
+ * IFC[1:0] =11b - CPU clock is 1/3 PLL clock
+ * FRQCR2=0x0003
+ * GFC[1:0] =11b - graphic clock is 1/3 bus clock
+ */
+#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u)
+#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u)
+#define CM1_RENESAS_RZ_A1_I_CLK (128000000u)
+#define CM1_RENESAS_RZ_A1_G_CLK (128000000u)
+#define CM1_RENESAS_RZ_A1_B_CLK (128000000u)
+#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
+#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
+
+/******************************************************************************/
+/* CPG Settings */
+/******************************************************************************/
+#define CPG_FRQCR_SHIFT_CKOEN2 (14)
+#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
+#define CPG_FRQCR_SHIFT_CKOEN0 (12)
+#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
+#define CPG_FRQCR_SHIFT_IFC (8)
+#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC)
+
+#define CPG_FRQCR2_SHIFT_GFC (0)
+#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC)
+
+
+#define CPG_STBCR1_BIT_STBY (0x80u)
+#define CPG_STBCR1_BIT_DEEP (0x40u)
+#define CPG_STBCR2_BIT_HIZ (0x80u)
+#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */
+#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */
+#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */
+#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */
+#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */
+#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */
+#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */
+#define CPG_STBCR3_BIT_MSTP31 (0x02u) /* A/D converter (analog voltage) */
+#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */
+#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */
+#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */
+#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */
+#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */
+#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */
+#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */
+#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */
+#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */
+#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */
+#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */
+#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */
+#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */
+#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */
+#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */
+#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
+#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
+#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* A/D converter (clock) */
+#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */
+#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */
+#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */
+#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range compression0 */
+#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range compression1 */
+#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */
+#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */
+#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */
+#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */
+#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ethernet */
+#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */
+#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */
+#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */
+#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */
+#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */
+#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */
+#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */
+#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */
+#define CPG_STBCR8_BIT_MSTP82 (0x04u) /* EthernetAVB */
+#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */
+#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */
+#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */
+#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */
+#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */
+#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */
+#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */
+#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */
+#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */
+#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
+#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
+#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
+#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
+#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
+#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
+#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
+#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
+#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
+#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
+#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
+#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
+#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
+#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
+#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
+#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
+#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
+#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
+#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */
+#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */
+#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
+#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
+#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
+#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
+#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
+#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
+#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
+#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
+#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
+#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */
+#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */
+#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */
+#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */
+#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */
+#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */
+#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */
+#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */
+#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */
+#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */
+#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */
+#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */
+#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */
+#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */
+#define CPG_CPUSTS_BIT_ISBUSY (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */
+#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */
+#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */
+#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */
+#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */
+#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */
+#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */
+#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */
+#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */
+#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */
+#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */
+#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */
+#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */
+#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */
+#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */
+#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */
+#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */
+#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */
+#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */
+#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */
+#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */
+#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */
+#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */
+#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */
+#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */
+#define CPG_RRAMKP_BIT_RRAMKP3 (0x08u) /* RRAM KP Page3 */
+#define CPG_RRAMKP_BIT_RRAMKP2 (0x04u) /* RRAM KP Page2 */
+#define CPG_RRAMKP_BIT_RRAMKP1 (0x02u) /* RRAM KP Page1 */
+#define CPG_RRAMKP_BIT_RRAMKP0 (0x01u) /* RRAM KP Page0 */
+#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */
+#define CPG_DSCTR_BIT_RAMBOOT (0x40u) /* Selection of Method after Returning from Deep Standby Mode */
+#define CPG_DSSSR_BIT_P6_2 (0x4000u) /* P6_2 */
+#define CPG_DSSSR_BIT_P3_9 (0x2000u) /* P3_9 */
+#define CPG_DSSSR_BIT_P3_1 (0x1000u) /* P3_1 */
+#define CPG_DSSSR_BIT_P2_12 (0x0800u) /* P2_12 */
+#define CPG_DSSSR_BIT_P8_7 (0x0400u) /* P8_7 */
+#define CPG_DSSSR_BIT_P3_3 (0x0200u) /* P3_3 */
+#define CPG_DSSSR_BIT_NMI (0x0100u) /* NMI */
+#define CPG_DSSSR_BIT_RTCAR (0x0040u) /* RTCAR */
+#define CPG_DSSSR_BIT_P6_4 (0x0020u) /* P6_4 */
+#define CPG_DSSSR_BIT_P5_9 (0x0010u) /* P5_9 */
+#define CPG_DSSSR_BIT_P7_8 (0x0008u) /* P7_8 */
+#define CPG_DSSSR_BIT_P2_15 (0x0004u) /* P2_15 */
+#define CPG_DSSSR_BIT_P9_1 (0x0002u) /* P9_1 */
+#define CPG_DSSSR_BIT_P8_2 (0x0001u) /* P8_2 */
+#define CPG_DSESR_BIT_P6_2E (0x4000u) /* P6_2 */
+#define CPG_DSESR_BIT_P3_9E (0x2000u) /* P3_9 */
+#define CPG_DSESR_BIT_P3_1E (0x1000u) /* P3_1 */
+#define CPG_DSESR_BIT_P2_12E (0x0800u) /* P2_12 */
+#define CPG_DSESR_BIT_P8_7E (0x0400u) /* P8_7 */
+#define CPG_DSESR_BIT_P3_3E (0x0200u) /* P3_3 */
+#define CPG_DSESR_BIT_NMIE (0x0100u) /* NMI */
+#define CPG_DSESR_BIT_P6_4E (0x0020u) /* P6_4 */
+#define CPG_DSESR_BIT_P5_9E (0x0010u) /* P5_9 */
+#define CPG_DSESR_BIT_P7_8E (0x0008u) /* P7_8 */
+#define CPG_DSESR_BIT_P2_15E (0x0004u) /* P2_15 */
+#define CPG_DSESR_BIT_P9_1E (0x0002u) /* P9_1 */
+#define CPG_DSESR_BIT_P8_2E (0x0001u) /* P8_2 */
+#define CPG_DSFR_BIT_IOKEEP (0x8000u) /* Release of Pin State Retention */
+#define CPG_DSFR_BIT_P6_2F (0x4000u) /* P6_2 */
+#define CPG_DSFR_BIT_P3_9F (0x2000u) /* P3_9 */
+#define CPG_DSFR_BIT_P3_1F (0x1000u) /* P3_1 */
+#define CPG_DSFR_BIT_P2_12F (0x0800u) /* P2_12 */
+#define CPG_DSFR_BIT_P8_7F (0x0400u) /* P8_7 */
+#define CPG_DSFR_BIT_P3_3F (0x0200u) /* P3_3 */
+#define CPG_DSFR_BIT_NMIF (0x0100u) /* NMI */
+#define CPG_DSFR_BIT_RTCARF (0x0040u) /* RTCAR */
+#define CPG_DSFR_BIT_P6_4F (0x0020u) /* P6_4 */
+#define CPG_DSFR_BIT_P5_9F (0x0010u) /* P5_9 */
+#define CPG_DSFR_BIT_P7_8F (0x0008u) /* P7_8 */
+#define CPG_DSFR_BIT_P2_15F (0x0004u) /* P2_15 */
+#define CPG_DSFR_BIT_P9_1F (0x0002u) /* P9_1 */
+#define CPG_DSFR_BIT_P8_2F (0x0001u) /* P8_2 */
+#define CPG_XTALCTR_BIT_GAIN1 (0x02u) /* RTC_X3, RTC_X4 */
+#define CPG_XTALCTR_BIT_GAIN0 (0x01u) /* EXTAL, XTAL */
+
+/******************************************************************************/
+/* GPIO Settings */
+/******************************************************************************/
+#define GPIO_BIT_N0 (1u << 0)
+#define GPIO_BIT_N1 (1u << 1)
+#define GPIO_BIT_N2 (1u << 2)
+#define GPIO_BIT_N3 (1u << 3)
+#define GPIO_BIT_N4 (1u << 4)
+#define GPIO_BIT_N5 (1u << 5)
+#define GPIO_BIT_N6 (1u << 6)
+#define GPIO_BIT_N7 (1u << 7)
+#define GPIO_BIT_N8 (1u << 8)
+#define GPIO_BIT_N9 (1u << 9)
+#define GPIO_BIT_N10 (1u << 10)
+#define GPIO_BIT_N11 (1u << 11)
+#define GPIO_BIT_N12 (1u << 12)
+#define GPIO_BIT_N13 (1u << 13)
+#define GPIO_BIT_N14 (1u << 14)
+#define GPIO_BIT_N15 (1u << 15)
+
+#define MD_BOOT10_MASK (0x3)
+
+#define MD_BOOT10_BM0 (0x0)
+#define MD_BOOT10_BM1 (0x2)
+#define MD_BOOT10_BM3 (0x1)
+#define MD_BOOT10_BM4_5 (0x3)
+
+#define MD_CLK (1u << 2)
+#define MD_CLKS (1u << 3)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __VK_RZ_A1H_H__
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-os-program/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h Mon Mar 18 11:46:29 2019 +0000 @@ -0,0 +1,75 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) +******************************************************************************/ +#ifndef R7S721000_IODEFINE_H +#define R7S721000_IODEFINE_H + +#include "iodefines/iodefine_typedef.h" /* (V2.00h) */ + +#include "iodefines/adc_iodefine.h" /* (V2.00h) */ +#include "iodefines/bsc_iodefine.h" /* (V2.00h) */ +#include "iodefines/ceu_iodefine.h" /* (V2.00h) */ +#include "iodefines/cpg_iodefine.h" /* (V2.00h) */ +#include "iodefines/disc_iodefine.h" /* (V2.00h) */ +#include "iodefines/dmac_iodefine.h" /* (V2.00h) */ +#include "iodefines/dvdec_iodefine.h" /* (V2.00h) */ +#include "iodefines/ether_iodefine.h" /* (V2.00h) */ +#include "iodefines/flctl_iodefine.h" /* (V2.00h) */ +#include "iodefines/gpio_iodefine.h" /* (V2.00h) */ +#include "iodefines/ieb_iodefine.h" /* (V2.00h) */ +#include "iodefines/inb_iodefine.h" /* (V2.00h) */ +#include "iodefines/intc_iodefine.h" /* (V2.00h) */ +#include "iodefines/irda_iodefine.h" /* (V2.00h) */ +#include "iodefines/jcu_iodefine.h" /* (V2.00h) */ +#include "iodefines/l2c_iodefine.h" /* (V2.00h) */ +#include "iodefines/lin_iodefine.h" /* (V2.00h) */ +#include "iodefines/lvds_iodefine.h" /* (V2.00h) */ +#include "iodefines/mlb_iodefine.h" /* (V2.00h) */ +#include "iodefines/mmc_iodefine.h" /* (V2.00h) */ +#include "iodefines/mtu2_iodefine.h" /* (V2.00h) */ +#include "iodefines/ostm_iodefine.h" /* (V2.00h) */ +#include "iodefines/pfv_iodefine.h" /* (V2.00h) */ +#include "iodefines/pwm_iodefine.h" /* (V2.00h) */ +#include "iodefines/riic_iodefine.h" /* (V2.00h) */ +#include "iodefines/romdec_iodefine.h" /* (V2.00h) */ +#include "iodefines/rscan0_iodefine.h" /* (V2.00h) */ +#include "iodefines/rspi_iodefine.h" /* (V2.00h) */ +#include "iodefines/rtc_iodefine.h" /* (V2.00h) */ +#include "iodefines/scif_iodefine.h" /* (V2.00h) */ +#include "iodefines/scim_iodefine.h" /* (V2.00h) */ +#include "iodefines/scux_iodefine.h" /* (V2.00h) */ +#include "iodefines/sdg_iodefine.h" /* (V2.00h) */ +#include "iodefines/sdhi_iodefine.h" /* */ +#include "iodefines/spdif_iodefine.h" /* (V2.00h) */ +#include "iodefines/spibsc_iodefine.h" /* (V2.00h) */ +#include "iodefines/ssif_iodefine.h" /* (V2.00h) */ +#include "iodefines/usb20_iodefine.h" /* (V2.00h) */ +#include "iodefines/vdc5_iodefine.h" /* (V2.00h) */ +#include "iodefines/wdt_iodefine.h" /* (V2.00h) */ +#endif +