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HAL_L476/stm32l4xx_hal_rcc_ex.c@1:d0dfbce63a89, 2017-02-24 (annotated)

Committer:
elmot
Date:
Fri Feb 24 21:13:56 2017 +0000
Revision:
1:d0dfbce63a89
Ready-to-copy

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elmot 1:d0dfbce63a89 1 /**
elmot 1:d0dfbce63a89 2 ******************************************************************************
elmot 1:d0dfbce63a89 3 * @file stm32l4xx_hal_rcc_ex.c
elmot 1:d0dfbce63a89 4 * @author MCD Application Team
elmot 1:d0dfbce63a89 5 * @version V1.5.1
elmot 1:d0dfbce63a89 6 * @date 31-May-2016
elmot 1:d0dfbce63a89 7 * @brief Extended RCC HAL module driver.
elmot 1:d0dfbce63a89 8 * This file provides firmware functions to manage the following
elmot 1:d0dfbce63a89 9 * functionalities RCC extended peripheral:
elmot 1:d0dfbce63a89 10 * + Extended Peripheral Control functions
elmot 1:d0dfbce63a89 11 * + Extended Clock management functions
elmot 1:d0dfbce63a89 12 * + Extended Clock Recovery System Control functions
elmot 1:d0dfbce63a89 13 *
elmot 1:d0dfbce63a89 14 ******************************************************************************
elmot 1:d0dfbce63a89 15 * @attention
elmot 1:d0dfbce63a89 16 *
elmot 1:d0dfbce63a89 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
elmot 1:d0dfbce63a89 18 *
elmot 1:d0dfbce63a89 19 * Redistribution and use in source and binary forms, with or without modification,
elmot 1:d0dfbce63a89 20 * are permitted provided that the following conditions are met:
elmot 1:d0dfbce63a89 21 * 1. Redistributions of source code must retain the above copyright notice,
elmot 1:d0dfbce63a89 22 * this list of conditions and the following disclaimer.
elmot 1:d0dfbce63a89 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
elmot 1:d0dfbce63a89 24 * this list of conditions and the following disclaimer in the documentation
elmot 1:d0dfbce63a89 25 * and/or other materials provided with the distribution.
elmot 1:d0dfbce63a89 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
elmot 1:d0dfbce63a89 27 * may be used to endorse or promote products derived from this software
elmot 1:d0dfbce63a89 28 * without specific prior written permission.
elmot 1:d0dfbce63a89 29 *
elmot 1:d0dfbce63a89 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elmot 1:d0dfbce63a89 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elmot 1:d0dfbce63a89 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elmot 1:d0dfbce63a89 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elmot 1:d0dfbce63a89 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elmot 1:d0dfbce63a89 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elmot 1:d0dfbce63a89 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elmot 1:d0dfbce63a89 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elmot 1:d0dfbce63a89 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elmot 1:d0dfbce63a89 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elmot 1:d0dfbce63a89 40 *
elmot 1:d0dfbce63a89 41 ******************************************************************************
elmot 1:d0dfbce63a89 42 */
elmot 1:d0dfbce63a89 43
elmot 1:d0dfbce63a89 44 /* Includes ------------------------------------------------------------------*/
elmot 1:d0dfbce63a89 45 #include "stm32l4xx_hal.h"
elmot 1:d0dfbce63a89 46
elmot 1:d0dfbce63a89 47 /** @addtogroup STM32L4xx_HAL_Driver
elmot 1:d0dfbce63a89 48 * @{
elmot 1:d0dfbce63a89 49 */
elmot 1:d0dfbce63a89 50
elmot 1:d0dfbce63a89 51 /** @defgroup RCCEx RCCEx
elmot 1:d0dfbce63a89 52 * @brief RCC Extended HAL module driver
elmot 1:d0dfbce63a89 53 * @{
elmot 1:d0dfbce63a89 54 */
elmot 1:d0dfbce63a89 55
elmot 1:d0dfbce63a89 56 #ifdef HAL_RCC_MODULE_ENABLED
elmot 1:d0dfbce63a89 57
elmot 1:d0dfbce63a89 58 /* Private typedef -----------------------------------------------------------*/
elmot 1:d0dfbce63a89 59 /* Private defines -----------------------------------------------------------*/
elmot 1:d0dfbce63a89 60 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
elmot 1:d0dfbce63a89 61 * @{
elmot 1:d0dfbce63a89 62 */
elmot 1:d0dfbce63a89 63 #define PLLSAI1_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
elmot 1:d0dfbce63a89 64 #define PLLSAI2_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
elmot 1:d0dfbce63a89 65 #define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
elmot 1:d0dfbce63a89 66
elmot 1:d0dfbce63a89 67 #define DIVIDER_P_UPDATE 0U
elmot 1:d0dfbce63a89 68 #define DIVIDER_Q_UPDATE 1U
elmot 1:d0dfbce63a89 69 #define DIVIDER_R_UPDATE 2U
elmot 1:d0dfbce63a89 70
elmot 1:d0dfbce63a89 71 #define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
elmot 1:d0dfbce63a89 72 #define LSCO_GPIO_PORT GPIOA
elmot 1:d0dfbce63a89 73 #define LSCO_PIN GPIO_PIN_2
elmot 1:d0dfbce63a89 74 /**
elmot 1:d0dfbce63a89 75 * @}
elmot 1:d0dfbce63a89 76 */
elmot 1:d0dfbce63a89 77
elmot 1:d0dfbce63a89 78 /* Private macros ------------------------------------------------------------*/
elmot 1:d0dfbce63a89 79 /* Private variables ---------------------------------------------------------*/
elmot 1:d0dfbce63a89 80 /* Private function prototypes -----------------------------------------------*/
elmot 1:d0dfbce63a89 81 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
elmot 1:d0dfbce63a89 82 * @{
elmot 1:d0dfbce63a89 83 */
elmot 1:d0dfbce63a89 84 static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider);
elmot 1:d0dfbce63a89 85
elmot 1:d0dfbce63a89 86 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 87
elmot 1:d0dfbce63a89 88 static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider);
elmot 1:d0dfbce63a89 89
elmot 1:d0dfbce63a89 90 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 91
elmot 1:d0dfbce63a89 92 /**
elmot 1:d0dfbce63a89 93 * @}
elmot 1:d0dfbce63a89 94 */
elmot 1:d0dfbce63a89 95
elmot 1:d0dfbce63a89 96 /* Exported functions --------------------------------------------------------*/
elmot 1:d0dfbce63a89 97
elmot 1:d0dfbce63a89 98 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
elmot 1:d0dfbce63a89 99 * @{
elmot 1:d0dfbce63a89 100 */
elmot 1:d0dfbce63a89 101
elmot 1:d0dfbce63a89 102 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
elmot 1:d0dfbce63a89 103 * @brief Extended Peripheral Control functions
elmot 1:d0dfbce63a89 104 *
elmot 1:d0dfbce63a89 105 @verbatim
elmot 1:d0dfbce63a89 106 ===============================================================================
elmot 1:d0dfbce63a89 107 ##### Extended Peripheral Control functions #####
elmot 1:d0dfbce63a89 108 ===============================================================================
elmot 1:d0dfbce63a89 109 [..]
elmot 1:d0dfbce63a89 110 This subsection provides a set of functions allowing to control the RCC Clocks
elmot 1:d0dfbce63a89 111 frequencies.
elmot 1:d0dfbce63a89 112 [..]
elmot 1:d0dfbce63a89 113 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
elmot 1:d0dfbce63a89 114 select the RTC clock source; in this case the Backup domain will be reset in
elmot 1:d0dfbce63a89 115 order to modify the RTC Clock source, as consequence RTC registers (including
elmot 1:d0dfbce63a89 116 the backup registers) are set to their reset values.
elmot 1:d0dfbce63a89 117
elmot 1:d0dfbce63a89 118 @endverbatim
elmot 1:d0dfbce63a89 119 * @{
elmot 1:d0dfbce63a89 120 */
elmot 1:d0dfbce63a89 121 /**
elmot 1:d0dfbce63a89 122 * @brief Initialize the RCC extended peripherals clocks according to the specified
elmot 1:d0dfbce63a89 123 * parameters in the RCC_PeriphCLKInitTypeDef.
elmot 1:d0dfbce63a89 124 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
elmot 1:d0dfbce63a89 125 * contains a field PeriphClockSelection which can be a combination of the following values:
elmot 1:d0dfbce63a89 126 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
elmot 1:d0dfbce63a89 127 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
elmot 1:d0dfbce63a89 128 @if STM32L486xx
elmot 1:d0dfbce63a89 129 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1)
elmot 1:d0dfbce63a89 130 @endif
elmot 1:d0dfbce63a89 131 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
elmot 1:d0dfbce63a89 132 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
elmot 1:d0dfbce63a89 133 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
elmot 1:d0dfbce63a89 134 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
elmot 1:d0dfbce63a89 135 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
elmot 1:d0dfbce63a89 136 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
elmot 1:d0dfbce63a89 137 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
elmot 1:d0dfbce63a89 138 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
elmot 1:d0dfbce63a89 139 @if STM32L486xx
elmot 1:d0dfbce63a89 140 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2)
elmot 1:d0dfbce63a89 141 @endif
elmot 1:d0dfbce63a89 142 * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock
elmot 1:d0dfbce63a89 143 @if STM32L443xx
elmot 1:d0dfbce63a89 144 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1)
elmot 1:d0dfbce63a89 145 @endif
elmot 1:d0dfbce63a89 146 @if STM32L486xx
elmot 1:d0dfbce63a89 147 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1)
elmot 1:d0dfbce63a89 148 @endif
elmot 1:d0dfbce63a89 149 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
elmot 1:d0dfbce63a89 150 * @arg @ref RCC_PERIPHCLK_USART2 USART1 peripheral clock
elmot 1:d0dfbce63a89 151 * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock
elmot 1:d0dfbce63a89 152 @if STM32L486xx
elmot 1:d0dfbce63a89 153 * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4)
elmot 1:d0dfbce63a89 154 * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5)
elmot 1:d0dfbce63a89 155 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
elmot 1:d0dfbce63a89 156 @endif
elmot 1:d0dfbce63a89 157 *
elmot 1:d0dfbce63a89 158 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
elmot 1:d0dfbce63a89 159 * the RTC clock source: in this case the access to Backup domain is enabled.
elmot 1:d0dfbce63a89 160 *
elmot 1:d0dfbce63a89 161 * @retval HAL status
elmot 1:d0dfbce63a89 162 */
elmot 1:d0dfbce63a89 163 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
elmot 1:d0dfbce63a89 164 {
elmot 1:d0dfbce63a89 165 uint32_t tmpregister = 0;
elmot 1:d0dfbce63a89 166 uint32_t tickstart = 0U;
elmot 1:d0dfbce63a89 167 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
elmot 1:d0dfbce63a89 168 HAL_StatusTypeDef status = HAL_OK; /* Final status */
elmot 1:d0dfbce63a89 169
elmot 1:d0dfbce63a89 170 /* Check the parameters */
elmot 1:d0dfbce63a89 171 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
elmot 1:d0dfbce63a89 172
elmot 1:d0dfbce63a89 173 /*-------------------------- SAI1 clock source configuration ---------------------*/
elmot 1:d0dfbce63a89 174 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
elmot 1:d0dfbce63a89 175 {
elmot 1:d0dfbce63a89 176 /* Check the parameters */
elmot 1:d0dfbce63a89 177 assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
elmot 1:d0dfbce63a89 178
elmot 1:d0dfbce63a89 179 switch(PeriphClkInit->Sai1ClockSelection)
elmot 1:d0dfbce63a89 180 {
elmot 1:d0dfbce63a89 181 case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
elmot 1:d0dfbce63a89 182 /* Enable SAI Clock output generated form System PLL . */
elmot 1:d0dfbce63a89 183 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 184 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
elmot 1:d0dfbce63a89 185 #else
elmot 1:d0dfbce63a89 186 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
elmot 1:d0dfbce63a89 187 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 188 /* SAI1 clock source config set later after clock selection check */
elmot 1:d0dfbce63a89 189 break;
elmot 1:d0dfbce63a89 190
elmot 1:d0dfbce63a89 191 case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
elmot 1:d0dfbce63a89 192 /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
elmot 1:d0dfbce63a89 193 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
elmot 1:d0dfbce63a89 194 /* SAI1 clock source config set later after clock selection check */
elmot 1:d0dfbce63a89 195 break;
elmot 1:d0dfbce63a89 196
elmot 1:d0dfbce63a89 197 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 198
elmot 1:d0dfbce63a89 199 case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
elmot 1:d0dfbce63a89 200 /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
elmot 1:d0dfbce63a89 201 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
elmot 1:d0dfbce63a89 202 /* SAI1 clock source config set later after clock selection check */
elmot 1:d0dfbce63a89 203 break;
elmot 1:d0dfbce63a89 204
elmot 1:d0dfbce63a89 205 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 206
elmot 1:d0dfbce63a89 207 case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
elmot 1:d0dfbce63a89 208 /* SAI1 clock source config set later after clock selection check */
elmot 1:d0dfbce63a89 209 break;
elmot 1:d0dfbce63a89 210
elmot 1:d0dfbce63a89 211 default:
elmot 1:d0dfbce63a89 212 ret = HAL_ERROR;
elmot 1:d0dfbce63a89 213 break;
elmot 1:d0dfbce63a89 214 }
elmot 1:d0dfbce63a89 215
elmot 1:d0dfbce63a89 216 if(ret == HAL_OK)
elmot 1:d0dfbce63a89 217 {
elmot 1:d0dfbce63a89 218 /* Set the source of SAI1 clock*/
elmot 1:d0dfbce63a89 219 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
elmot 1:d0dfbce63a89 220 }
elmot 1:d0dfbce63a89 221 else
elmot 1:d0dfbce63a89 222 {
elmot 1:d0dfbce63a89 223 /* set overall return value */
elmot 1:d0dfbce63a89 224 status = ret;
elmot 1:d0dfbce63a89 225 }
elmot 1:d0dfbce63a89 226 }
elmot 1:d0dfbce63a89 227
elmot 1:d0dfbce63a89 228 #if defined(SAI2)
elmot 1:d0dfbce63a89 229
elmot 1:d0dfbce63a89 230 /*-------------------------- SAI2 clock source configuration ---------------------*/
elmot 1:d0dfbce63a89 231 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
elmot 1:d0dfbce63a89 232 {
elmot 1:d0dfbce63a89 233 /* Check the parameters */
elmot 1:d0dfbce63a89 234 assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
elmot 1:d0dfbce63a89 235
elmot 1:d0dfbce63a89 236 switch(PeriphClkInit->Sai2ClockSelection)
elmot 1:d0dfbce63a89 237 {
elmot 1:d0dfbce63a89 238 case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
elmot 1:d0dfbce63a89 239 /* Enable SAI Clock output generated form System PLL . */
elmot 1:d0dfbce63a89 240 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
elmot 1:d0dfbce63a89 241 /* SAI2 clock source config set later after clock selection check */
elmot 1:d0dfbce63a89 242 break;
elmot 1:d0dfbce63a89 243
elmot 1:d0dfbce63a89 244 case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
elmot 1:d0dfbce63a89 245 /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
elmot 1:d0dfbce63a89 246 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
elmot 1:d0dfbce63a89 247 /* SAI2 clock source config set later after clock selection check */
elmot 1:d0dfbce63a89 248 break;
elmot 1:d0dfbce63a89 249
elmot 1:d0dfbce63a89 250 case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
elmot 1:d0dfbce63a89 251 /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
elmot 1:d0dfbce63a89 252 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
elmot 1:d0dfbce63a89 253 /* SAI2 clock source config set later after clock selection check */
elmot 1:d0dfbce63a89 254 break;
elmot 1:d0dfbce63a89 255
elmot 1:d0dfbce63a89 256 case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/
elmot 1:d0dfbce63a89 257 /* SAI2 clock source config set later after clock selection check */
elmot 1:d0dfbce63a89 258 break;
elmot 1:d0dfbce63a89 259
elmot 1:d0dfbce63a89 260 default:
elmot 1:d0dfbce63a89 261 ret = HAL_ERROR;
elmot 1:d0dfbce63a89 262 break;
elmot 1:d0dfbce63a89 263 }
elmot 1:d0dfbce63a89 264
elmot 1:d0dfbce63a89 265 if(ret == HAL_OK)
elmot 1:d0dfbce63a89 266 {
elmot 1:d0dfbce63a89 267 /* Set the source of SAI2 clock*/
elmot 1:d0dfbce63a89 268 __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
elmot 1:d0dfbce63a89 269 }
elmot 1:d0dfbce63a89 270 else
elmot 1:d0dfbce63a89 271 {
elmot 1:d0dfbce63a89 272 /* set overall return value */
elmot 1:d0dfbce63a89 273 status = ret;
elmot 1:d0dfbce63a89 274 }
elmot 1:d0dfbce63a89 275 }
elmot 1:d0dfbce63a89 276 #endif /* SAI2 */
elmot 1:d0dfbce63a89 277
elmot 1:d0dfbce63a89 278 /*-------------------------- RTC clock source configuration ----------------------*/
elmot 1:d0dfbce63a89 279 if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
elmot 1:d0dfbce63a89 280 {
elmot 1:d0dfbce63a89 281 FlagStatus pwrclkchanged = RESET;
elmot 1:d0dfbce63a89 282
elmot 1:d0dfbce63a89 283 /* Check for RTC Parameters used to output RTCCLK */
elmot 1:d0dfbce63a89 284 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
elmot 1:d0dfbce63a89 285
elmot 1:d0dfbce63a89 286 /* Enable Power Clock */
elmot 1:d0dfbce63a89 287 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
elmot 1:d0dfbce63a89 288 {
elmot 1:d0dfbce63a89 289 __HAL_RCC_PWR_CLK_ENABLE();
elmot 1:d0dfbce63a89 290 pwrclkchanged = SET;
elmot 1:d0dfbce63a89 291 }
elmot 1:d0dfbce63a89 292
elmot 1:d0dfbce63a89 293 /* Enable write access to Backup domain */
elmot 1:d0dfbce63a89 294 SET_BIT(PWR->CR1, PWR_CR1_DBP);
elmot 1:d0dfbce63a89 295
elmot 1:d0dfbce63a89 296 /* Wait for Backup domain Write protection disable */
elmot 1:d0dfbce63a89 297 tickstart = HAL_GetTick();
elmot 1:d0dfbce63a89 298
elmot 1:d0dfbce63a89 299 while((PWR->CR1 & PWR_CR1_DBP) == RESET)
elmot 1:d0dfbce63a89 300 {
elmot 1:d0dfbce63a89 301 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
elmot 1:d0dfbce63a89 302 {
elmot 1:d0dfbce63a89 303 ret = HAL_TIMEOUT;
elmot 1:d0dfbce63a89 304 break;
elmot 1:d0dfbce63a89 305 }
elmot 1:d0dfbce63a89 306 }
elmot 1:d0dfbce63a89 307
elmot 1:d0dfbce63a89 308 if(ret == HAL_OK)
elmot 1:d0dfbce63a89 309 {
elmot 1:d0dfbce63a89 310 /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
elmot 1:d0dfbce63a89 311 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
elmot 1:d0dfbce63a89 312
elmot 1:d0dfbce63a89 313 if((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != PeriphClkInit->RTCClockSelection))
elmot 1:d0dfbce63a89 314 {
elmot 1:d0dfbce63a89 315 /* Store the content of BDCR register before the reset of Backup Domain */
elmot 1:d0dfbce63a89 316 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
elmot 1:d0dfbce63a89 317 /* RTC Clock selection can be changed only if the Backup Domain is reset */
elmot 1:d0dfbce63a89 318 __HAL_RCC_BACKUPRESET_FORCE();
elmot 1:d0dfbce63a89 319 __HAL_RCC_BACKUPRESET_RELEASE();
elmot 1:d0dfbce63a89 320 /* Restore the Content of BDCR register */
elmot 1:d0dfbce63a89 321 RCC->BDCR = tmpregister;
elmot 1:d0dfbce63a89 322 }
elmot 1:d0dfbce63a89 323
elmot 1:d0dfbce63a89 324 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
elmot 1:d0dfbce63a89 325 if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
elmot 1:d0dfbce63a89 326 {
elmot 1:d0dfbce63a89 327 /* Get Start Tick*/
elmot 1:d0dfbce63a89 328 tickstart = HAL_GetTick();
elmot 1:d0dfbce63a89 329
elmot 1:d0dfbce63a89 330 /* Wait till LSE is ready */
elmot 1:d0dfbce63a89 331 while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET)
elmot 1:d0dfbce63a89 332 {
elmot 1:d0dfbce63a89 333 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
elmot 1:d0dfbce63a89 334 {
elmot 1:d0dfbce63a89 335 ret = HAL_TIMEOUT;
elmot 1:d0dfbce63a89 336 break;
elmot 1:d0dfbce63a89 337 }
elmot 1:d0dfbce63a89 338 }
elmot 1:d0dfbce63a89 339 }
elmot 1:d0dfbce63a89 340
elmot 1:d0dfbce63a89 341 if(ret == HAL_OK)
elmot 1:d0dfbce63a89 342 {
elmot 1:d0dfbce63a89 343 /* Apply new RTC clock source selection */
elmot 1:d0dfbce63a89 344 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
elmot 1:d0dfbce63a89 345 }
elmot 1:d0dfbce63a89 346 else
elmot 1:d0dfbce63a89 347 {
elmot 1:d0dfbce63a89 348 /* set overall return value */
elmot 1:d0dfbce63a89 349 status = ret;
elmot 1:d0dfbce63a89 350 }
elmot 1:d0dfbce63a89 351 }
elmot 1:d0dfbce63a89 352 else
elmot 1:d0dfbce63a89 353 {
elmot 1:d0dfbce63a89 354 /* set overall return value */
elmot 1:d0dfbce63a89 355 status = ret;
elmot 1:d0dfbce63a89 356 }
elmot 1:d0dfbce63a89 357
elmot 1:d0dfbce63a89 358 /* Restore clock configuration if changed */
elmot 1:d0dfbce63a89 359 if(pwrclkchanged == SET)
elmot 1:d0dfbce63a89 360 {
elmot 1:d0dfbce63a89 361 __HAL_RCC_PWR_CLK_DISABLE();
elmot 1:d0dfbce63a89 362 }
elmot 1:d0dfbce63a89 363 }
elmot 1:d0dfbce63a89 364
elmot 1:d0dfbce63a89 365 /*-------------------------- USART1 clock source configuration -------------------*/
elmot 1:d0dfbce63a89 366 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
elmot 1:d0dfbce63a89 367 {
elmot 1:d0dfbce63a89 368 /* Check the parameters */
elmot 1:d0dfbce63a89 369 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
elmot 1:d0dfbce63a89 370
elmot 1:d0dfbce63a89 371 /* Configure the USART1 clock source */
elmot 1:d0dfbce63a89 372 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
elmot 1:d0dfbce63a89 373 }
elmot 1:d0dfbce63a89 374
elmot 1:d0dfbce63a89 375 /*-------------------------- USART2 clock source configuration -------------------*/
elmot 1:d0dfbce63a89 376 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
elmot 1:d0dfbce63a89 377 {
elmot 1:d0dfbce63a89 378 /* Check the parameters */
elmot 1:d0dfbce63a89 379 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
elmot 1:d0dfbce63a89 380
elmot 1:d0dfbce63a89 381 /* Configure the USART2 clock source */
elmot 1:d0dfbce63a89 382 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
elmot 1:d0dfbce63a89 383 }
elmot 1:d0dfbce63a89 384
elmot 1:d0dfbce63a89 385 #if defined(USART3)
elmot 1:d0dfbce63a89 386
elmot 1:d0dfbce63a89 387 /*-------------------------- USART3 clock source configuration -------------------*/
elmot 1:d0dfbce63a89 388 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
elmot 1:d0dfbce63a89 389 {
elmot 1:d0dfbce63a89 390 /* Check the parameters */
elmot 1:d0dfbce63a89 391 assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
elmot 1:d0dfbce63a89 392
elmot 1:d0dfbce63a89 393 /* Configure the USART3 clock source */
elmot 1:d0dfbce63a89 394 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
elmot 1:d0dfbce63a89 395 }
elmot 1:d0dfbce63a89 396
elmot 1:d0dfbce63a89 397 #endif /* USART3 */
elmot 1:d0dfbce63a89 398
elmot 1:d0dfbce63a89 399 #if defined(UART4)
elmot 1:d0dfbce63a89 400
elmot 1:d0dfbce63a89 401 /*-------------------------- UART4 clock source configuration --------------------*/
elmot 1:d0dfbce63a89 402 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
elmot 1:d0dfbce63a89 403 {
elmot 1:d0dfbce63a89 404 /* Check the parameters */
elmot 1:d0dfbce63a89 405 assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
elmot 1:d0dfbce63a89 406
elmot 1:d0dfbce63a89 407 /* Configure the UART4 clock source */
elmot 1:d0dfbce63a89 408 __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
elmot 1:d0dfbce63a89 409 }
elmot 1:d0dfbce63a89 410
elmot 1:d0dfbce63a89 411 #endif /* UART4 */
elmot 1:d0dfbce63a89 412
elmot 1:d0dfbce63a89 413 #if defined(UART5)
elmot 1:d0dfbce63a89 414
elmot 1:d0dfbce63a89 415 /*-------------------------- UART5 clock source configuration --------------------*/
elmot 1:d0dfbce63a89 416 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
elmot 1:d0dfbce63a89 417 {
elmot 1:d0dfbce63a89 418 /* Check the parameters */
elmot 1:d0dfbce63a89 419 assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
elmot 1:d0dfbce63a89 420
elmot 1:d0dfbce63a89 421 /* Configure the UART5 clock source */
elmot 1:d0dfbce63a89 422 __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
elmot 1:d0dfbce63a89 423 }
elmot 1:d0dfbce63a89 424
elmot 1:d0dfbce63a89 425 #endif /* UART5 */
elmot 1:d0dfbce63a89 426
elmot 1:d0dfbce63a89 427 /*-------------------------- LPUART1 clock source configuration ------------------*/
elmot 1:d0dfbce63a89 428 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
elmot 1:d0dfbce63a89 429 {
elmot 1:d0dfbce63a89 430 /* Check the parameters */
elmot 1:d0dfbce63a89 431 assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
elmot 1:d0dfbce63a89 432
elmot 1:d0dfbce63a89 433 /* Configure the LPUAR1 clock source */
elmot 1:d0dfbce63a89 434 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
elmot 1:d0dfbce63a89 435 }
elmot 1:d0dfbce63a89 436
elmot 1:d0dfbce63a89 437 /*-------------------------- LPTIM1 clock source configuration -------------------*/
elmot 1:d0dfbce63a89 438 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
elmot 1:d0dfbce63a89 439 {
elmot 1:d0dfbce63a89 440 assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
elmot 1:d0dfbce63a89 441 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
elmot 1:d0dfbce63a89 442 }
elmot 1:d0dfbce63a89 443
elmot 1:d0dfbce63a89 444 /*-------------------------- LPTIM2 clock source configuration -------------------*/
elmot 1:d0dfbce63a89 445 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
elmot 1:d0dfbce63a89 446 {
elmot 1:d0dfbce63a89 447 assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
elmot 1:d0dfbce63a89 448 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
elmot 1:d0dfbce63a89 449 }
elmot 1:d0dfbce63a89 450
elmot 1:d0dfbce63a89 451 /*-------------------------- I2C1 clock source configuration ---------------------*/
elmot 1:d0dfbce63a89 452 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
elmot 1:d0dfbce63a89 453 {
elmot 1:d0dfbce63a89 454 /* Check the parameters */
elmot 1:d0dfbce63a89 455 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
elmot 1:d0dfbce63a89 456
elmot 1:d0dfbce63a89 457 /* Configure the I2C1 clock source */
elmot 1:d0dfbce63a89 458 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
elmot 1:d0dfbce63a89 459 }
elmot 1:d0dfbce63a89 460
elmot 1:d0dfbce63a89 461 #if defined(I2C2)
elmot 1:d0dfbce63a89 462
elmot 1:d0dfbce63a89 463 /*-------------------------- I2C2 clock source configuration ---------------------*/
elmot 1:d0dfbce63a89 464 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
elmot 1:d0dfbce63a89 465 {
elmot 1:d0dfbce63a89 466 /* Check the parameters */
elmot 1:d0dfbce63a89 467 assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
elmot 1:d0dfbce63a89 468
elmot 1:d0dfbce63a89 469 /* Configure the I2C2 clock source */
elmot 1:d0dfbce63a89 470 __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
elmot 1:d0dfbce63a89 471 }
elmot 1:d0dfbce63a89 472
elmot 1:d0dfbce63a89 473 #endif /* I2C2 */
elmot 1:d0dfbce63a89 474
elmot 1:d0dfbce63a89 475 /*-------------------------- I2C3 clock source configuration ---------------------*/
elmot 1:d0dfbce63a89 476 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
elmot 1:d0dfbce63a89 477 {
elmot 1:d0dfbce63a89 478 /* Check the parameters */
elmot 1:d0dfbce63a89 479 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
elmot 1:d0dfbce63a89 480
elmot 1:d0dfbce63a89 481 /* Configure the I2C3 clock source */
elmot 1:d0dfbce63a89 482 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
elmot 1:d0dfbce63a89 483 }
elmot 1:d0dfbce63a89 484
elmot 1:d0dfbce63a89 485 #if defined(USB_OTG_FS) || defined(USB)
elmot 1:d0dfbce63a89 486
elmot 1:d0dfbce63a89 487 /*-------------------------- USB clock source configuration ----------------------*/
elmot 1:d0dfbce63a89 488 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
elmot 1:d0dfbce63a89 489 {
elmot 1:d0dfbce63a89 490 assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
elmot 1:d0dfbce63a89 491 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
elmot 1:d0dfbce63a89 492
elmot 1:d0dfbce63a89 493 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
elmot 1:d0dfbce63a89 494 {
elmot 1:d0dfbce63a89 495 /* Enable PLL48M1CLK output */
elmot 1:d0dfbce63a89 496 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
elmot 1:d0dfbce63a89 497 }
elmot 1:d0dfbce63a89 498 else if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
elmot 1:d0dfbce63a89 499 {
elmot 1:d0dfbce63a89 500 /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
elmot 1:d0dfbce63a89 501 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
elmot 1:d0dfbce63a89 502
elmot 1:d0dfbce63a89 503 if(ret != HAL_OK)
elmot 1:d0dfbce63a89 504 {
elmot 1:d0dfbce63a89 505 /* set overall return value */
elmot 1:d0dfbce63a89 506 status = ret;
elmot 1:d0dfbce63a89 507 }
elmot 1:d0dfbce63a89 508 }
elmot 1:d0dfbce63a89 509 }
elmot 1:d0dfbce63a89 510
elmot 1:d0dfbce63a89 511 #endif /* USB_OTG_FS || USB */
elmot 1:d0dfbce63a89 512
elmot 1:d0dfbce63a89 513 #if defined(SDMMC1)
elmot 1:d0dfbce63a89 514
elmot 1:d0dfbce63a89 515 /*-------------------------- SDMMC1 clock source configuration -------------------*/
elmot 1:d0dfbce63a89 516 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
elmot 1:d0dfbce63a89 517 {
elmot 1:d0dfbce63a89 518 assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
elmot 1:d0dfbce63a89 519 __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
elmot 1:d0dfbce63a89 520
elmot 1:d0dfbce63a89 521 if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL)
elmot 1:d0dfbce63a89 522 {
elmot 1:d0dfbce63a89 523 /* Enable PLL48M1CLK output */
elmot 1:d0dfbce63a89 524 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
elmot 1:d0dfbce63a89 525 }
elmot 1:d0dfbce63a89 526 else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
elmot 1:d0dfbce63a89 527 {
elmot 1:d0dfbce63a89 528 /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
elmot 1:d0dfbce63a89 529 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
elmot 1:d0dfbce63a89 530
elmot 1:d0dfbce63a89 531 if(ret != HAL_OK)
elmot 1:d0dfbce63a89 532 {
elmot 1:d0dfbce63a89 533 /* set overall return value */
elmot 1:d0dfbce63a89 534 status = ret;
elmot 1:d0dfbce63a89 535 }
elmot 1:d0dfbce63a89 536 }
elmot 1:d0dfbce63a89 537 }
elmot 1:d0dfbce63a89 538
elmot 1:d0dfbce63a89 539 #endif /* SDMMC1 */
elmot 1:d0dfbce63a89 540
elmot 1:d0dfbce63a89 541 /*-------------------------- RNG clock source configuration ----------------------*/
elmot 1:d0dfbce63a89 542 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
elmot 1:d0dfbce63a89 543 {
elmot 1:d0dfbce63a89 544 assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
elmot 1:d0dfbce63a89 545 __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
elmot 1:d0dfbce63a89 546
elmot 1:d0dfbce63a89 547 if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
elmot 1:d0dfbce63a89 548 {
elmot 1:d0dfbce63a89 549 /* Enable PLL48M1CLK output */
elmot 1:d0dfbce63a89 550 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
elmot 1:d0dfbce63a89 551 }
elmot 1:d0dfbce63a89 552 else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
elmot 1:d0dfbce63a89 553 {
elmot 1:d0dfbce63a89 554 /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
elmot 1:d0dfbce63a89 555 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
elmot 1:d0dfbce63a89 556
elmot 1:d0dfbce63a89 557 if(ret != HAL_OK)
elmot 1:d0dfbce63a89 558 {
elmot 1:d0dfbce63a89 559 /* set overall return value */
elmot 1:d0dfbce63a89 560 status = ret;
elmot 1:d0dfbce63a89 561 }
elmot 1:d0dfbce63a89 562 }
elmot 1:d0dfbce63a89 563 }
elmot 1:d0dfbce63a89 564
elmot 1:d0dfbce63a89 565 /*-------------------------- ADC clock source configuration ----------------------*/
elmot 1:d0dfbce63a89 566 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
elmot 1:d0dfbce63a89 567 {
elmot 1:d0dfbce63a89 568 /* Check the parameters */
elmot 1:d0dfbce63a89 569 assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
elmot 1:d0dfbce63a89 570
elmot 1:d0dfbce63a89 571 /* Configure the ADC interface clock source */
elmot 1:d0dfbce63a89 572 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
elmot 1:d0dfbce63a89 573
elmot 1:d0dfbce63a89 574 if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
elmot 1:d0dfbce63a89 575 {
elmot 1:d0dfbce63a89 576 /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
elmot 1:d0dfbce63a89 577 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
elmot 1:d0dfbce63a89 578
elmot 1:d0dfbce63a89 579 if(ret != HAL_OK)
elmot 1:d0dfbce63a89 580 {
elmot 1:d0dfbce63a89 581 /* set overall return value */
elmot 1:d0dfbce63a89 582 status = ret;
elmot 1:d0dfbce63a89 583 }
elmot 1:d0dfbce63a89 584 }
elmot 1:d0dfbce63a89 585
elmot 1:d0dfbce63a89 586 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
elmot 1:d0dfbce63a89 587
elmot 1:d0dfbce63a89 588 else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
elmot 1:d0dfbce63a89 589 {
elmot 1:d0dfbce63a89 590 /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
elmot 1:d0dfbce63a89 591 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
elmot 1:d0dfbce63a89 592
elmot 1:d0dfbce63a89 593 if(ret != HAL_OK)
elmot 1:d0dfbce63a89 594 {
elmot 1:d0dfbce63a89 595 /* set overall return value */
elmot 1:d0dfbce63a89 596 status = ret;
elmot 1:d0dfbce63a89 597 }
elmot 1:d0dfbce63a89 598 }
elmot 1:d0dfbce63a89 599
elmot 1:d0dfbce63a89 600 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
elmot 1:d0dfbce63a89 601
elmot 1:d0dfbce63a89 602 }
elmot 1:d0dfbce63a89 603
elmot 1:d0dfbce63a89 604 #if defined(SWPMI1)
elmot 1:d0dfbce63a89 605
elmot 1:d0dfbce63a89 606 /*-------------------------- SWPMI1 clock source configuration -------------------*/
elmot 1:d0dfbce63a89 607 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
elmot 1:d0dfbce63a89 608 {
elmot 1:d0dfbce63a89 609 /* Check the parameters */
elmot 1:d0dfbce63a89 610 assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
elmot 1:d0dfbce63a89 611
elmot 1:d0dfbce63a89 612 /* Configure the SWPMI1 clock source */
elmot 1:d0dfbce63a89 613 __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
elmot 1:d0dfbce63a89 614 }
elmot 1:d0dfbce63a89 615
elmot 1:d0dfbce63a89 616 #endif /* SWPMI1 */
elmot 1:d0dfbce63a89 617
elmot 1:d0dfbce63a89 618 #if defined(DFSDM1_Filter0)
elmot 1:d0dfbce63a89 619
elmot 1:d0dfbce63a89 620 /*-------------------------- DFSDM1 clock source configuration -------------------*/
elmot 1:d0dfbce63a89 621 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
elmot 1:d0dfbce63a89 622 {
elmot 1:d0dfbce63a89 623 /* Check the parameters */
elmot 1:d0dfbce63a89 624 assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
elmot 1:d0dfbce63a89 625
elmot 1:d0dfbce63a89 626 /* Configure the DFSDM1 interface clock source */
elmot 1:d0dfbce63a89 627 __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
elmot 1:d0dfbce63a89 628 }
elmot 1:d0dfbce63a89 629
elmot 1:d0dfbce63a89 630 #endif /* DFSDM1_Filter0 */
elmot 1:d0dfbce63a89 631
elmot 1:d0dfbce63a89 632 return status;
elmot 1:d0dfbce63a89 633 }
elmot 1:d0dfbce63a89 634
elmot 1:d0dfbce63a89 635 /**
elmot 1:d0dfbce63a89 636 * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
elmot 1:d0dfbce63a89 637 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
elmot 1:d0dfbce63a89 638 * returns the configuration information for the Extended Peripherals
elmot 1:d0dfbce63a89 639 * clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, LPUART,
elmot 1:d0dfbce63a89 640 * USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG).
elmot 1:d0dfbce63a89 641 * @retval None
elmot 1:d0dfbce63a89 642 */
elmot 1:d0dfbce63a89 643 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
elmot 1:d0dfbce63a89 644 {
elmot 1:d0dfbce63a89 645 /* Set all possible values for the extended clock type parameter------------*/
elmot 1:d0dfbce63a89 646
elmot 1:d0dfbce63a89 647 #if defined(STM32L431xx)
elmot 1:d0dfbce63a89 648
elmot 1:d0dfbce63a89 649 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
elmot 1:d0dfbce63a89 650 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
elmot 1:d0dfbce63a89 651 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \
elmot 1:d0dfbce63a89 652 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
elmot 1:d0dfbce63a89 653 RCC_PERIPHCLK_RTC ;
elmot 1:d0dfbce63a89 654
elmot 1:d0dfbce63a89 655 #elif defined(STM32L432xx) || defined(STM32L442xx)
elmot 1:d0dfbce63a89 656
elmot 1:d0dfbce63a89 657 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
elmot 1:d0dfbce63a89 658 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \
elmot 1:d0dfbce63a89 659 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \
elmot 1:d0dfbce63a89 660 RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
elmot 1:d0dfbce63a89 661 RCC_PERIPHCLK_RTC ;
elmot 1:d0dfbce63a89 662
elmot 1:d0dfbce63a89 663 #elif defined(STM32L433xx) || defined(STM32L443xx)
elmot 1:d0dfbce63a89 664
elmot 1:d0dfbce63a89 665 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
elmot 1:d0dfbce63a89 666 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
elmot 1:d0dfbce63a89 667 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \
elmot 1:d0dfbce63a89 668 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
elmot 1:d0dfbce63a89 669 RCC_PERIPHCLK_RTC ;
elmot 1:d0dfbce63a89 670 #elif defined(STM32L471xx)
elmot 1:d0dfbce63a89 671
elmot 1:d0dfbce63a89 672 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
elmot 1:d0dfbce63a89 673 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
elmot 1:d0dfbce63a89 674 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
elmot 1:d0dfbce63a89 675 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
elmot 1:d0dfbce63a89 676 RCC_PERIPHCLK_RTC ;
elmot 1:d0dfbce63a89 677
elmot 1:d0dfbce63a89 678 #elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
elmot 1:d0dfbce63a89 679
elmot 1:d0dfbce63a89 680 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
elmot 1:d0dfbce63a89 681 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
elmot 1:d0dfbce63a89 682 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
elmot 1:d0dfbce63a89 683 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
elmot 1:d0dfbce63a89 684 RCC_PERIPHCLK_RTC ;
elmot 1:d0dfbce63a89 685
elmot 1:d0dfbce63a89 686 #endif /* STM32L431xx */
elmot 1:d0dfbce63a89 687
elmot 1:d0dfbce63a89 688 /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
elmot 1:d0dfbce63a89 689
elmot 1:d0dfbce63a89 690 PeriphClkInit->PLLSAI1.PLLSAI1Source = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC));
elmot 1:d0dfbce63a89 691 PeriphClkInit->PLLSAI1.PLLSAI1M = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U;
elmot 1:d0dfbce63a89 692 PeriphClkInit->PLLSAI1.PLLSAI1N = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N));
elmot 1:d0dfbce63a89 693 PeriphClkInit->PLLSAI1.PLLSAI1P = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1P) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) << 4U) + 7U;
elmot 1:d0dfbce63a89 694 PeriphClkInit->PLLSAI1.PLLSAI1Q = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))+1U) * 2U;
elmot 1:d0dfbce63a89 695 PeriphClkInit->PLLSAI1.PLLSAI1R = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))+1U) * 2U;
elmot 1:d0dfbce63a89 696
elmot 1:d0dfbce63a89 697 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 698
elmot 1:d0dfbce63a89 699 /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/
elmot 1:d0dfbce63a89 700
elmot 1:d0dfbce63a89 701 PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source;
elmot 1:d0dfbce63a89 702 PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M;
elmot 1:d0dfbce63a89 703 PeriphClkInit->PLLSAI2.PLLSAI2N = (uint32_t)((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N));
elmot 1:d0dfbce63a89 704 PeriphClkInit->PLLSAI2.PLLSAI2P = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2P) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) << 4U) + 7U;
elmot 1:d0dfbce63a89 705 PeriphClkInit->PLLSAI2.PLLSAI2R = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2R)>> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))+1U) * 2U;
elmot 1:d0dfbce63a89 706
elmot 1:d0dfbce63a89 707 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 708
elmot 1:d0dfbce63a89 709 /* Get the USART1 clock source ---------------------------------------------*/
elmot 1:d0dfbce63a89 710 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
elmot 1:d0dfbce63a89 711 /* Get the USART2 clock source ---------------------------------------------*/
elmot 1:d0dfbce63a89 712 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
elmot 1:d0dfbce63a89 713
elmot 1:d0dfbce63a89 714 #if defined(USART3)
elmot 1:d0dfbce63a89 715 /* Get the USART3 clock source ---------------------------------------------*/
elmot 1:d0dfbce63a89 716 PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
elmot 1:d0dfbce63a89 717 #endif /* USART3 */
elmot 1:d0dfbce63a89 718
elmot 1:d0dfbce63a89 719 #if defined(UART4)
elmot 1:d0dfbce63a89 720 /* Get the UART4 clock source ----------------------------------------------*/
elmot 1:d0dfbce63a89 721 PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
elmot 1:d0dfbce63a89 722 #endif /* UART4 */
elmot 1:d0dfbce63a89 723
elmot 1:d0dfbce63a89 724 #if defined(UART5)
elmot 1:d0dfbce63a89 725 /* Get the UART5 clock source ----------------------------------------------*/
elmot 1:d0dfbce63a89 726 PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
elmot 1:d0dfbce63a89 727 #endif /* UART5 */
elmot 1:d0dfbce63a89 728
elmot 1:d0dfbce63a89 729 /* Get the LPUART1 clock source --------------------------------------------*/
elmot 1:d0dfbce63a89 730 PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
elmot 1:d0dfbce63a89 731
elmot 1:d0dfbce63a89 732 /* Get the I2C1 clock source -----------------------------------------------*/
elmot 1:d0dfbce63a89 733 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
elmot 1:d0dfbce63a89 734
elmot 1:d0dfbce63a89 735 #if defined(I2C2)
elmot 1:d0dfbce63a89 736 /* Get the I2C2 clock source ----------------------------------------------*/
elmot 1:d0dfbce63a89 737 PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
elmot 1:d0dfbce63a89 738 #endif /* I2C2 */
elmot 1:d0dfbce63a89 739
elmot 1:d0dfbce63a89 740 /* Get the I2C3 clock source -----------------------------------------------*/
elmot 1:d0dfbce63a89 741 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
elmot 1:d0dfbce63a89 742
elmot 1:d0dfbce63a89 743 /* Get the LPTIM1 clock source ---------------------------------------------*/
elmot 1:d0dfbce63a89 744 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
elmot 1:d0dfbce63a89 745
elmot 1:d0dfbce63a89 746 /* Get the LPTIM2 clock source ---------------------------------------------*/
elmot 1:d0dfbce63a89 747 PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
elmot 1:d0dfbce63a89 748
elmot 1:d0dfbce63a89 749 /* Get the SAI1 clock source -----------------------------------------------*/
elmot 1:d0dfbce63a89 750 PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
elmot 1:d0dfbce63a89 751
elmot 1:d0dfbce63a89 752 #if defined(SAI2)
elmot 1:d0dfbce63a89 753 /* Get the SAI2 clock source -----------------------------------------------*/
elmot 1:d0dfbce63a89 754 PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
elmot 1:d0dfbce63a89 755 #endif /* SAI2 */
elmot 1:d0dfbce63a89 756
elmot 1:d0dfbce63a89 757 /* Get the RTC clock source ------------------------------------------------*/
elmot 1:d0dfbce63a89 758 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
elmot 1:d0dfbce63a89 759
elmot 1:d0dfbce63a89 760 #if defined(USB_OTG_FS) || defined(USB)
elmot 1:d0dfbce63a89 761 /* Get the USB clock source ------------------------------------------------*/
elmot 1:d0dfbce63a89 762 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
elmot 1:d0dfbce63a89 763 #endif /* USB_OTG_FS || USB */
elmot 1:d0dfbce63a89 764
elmot 1:d0dfbce63a89 765 #if defined(SDMMC1)
elmot 1:d0dfbce63a89 766 /* Get the SDMMC1 clock source ---------------------------------------------*/
elmot 1:d0dfbce63a89 767 PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
elmot 1:d0dfbce63a89 768 #endif /* SDMMC1 */
elmot 1:d0dfbce63a89 769
elmot 1:d0dfbce63a89 770 /* Get the RNG clock source ------------------------------------------------*/
elmot 1:d0dfbce63a89 771 PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
elmot 1:d0dfbce63a89 772
elmot 1:d0dfbce63a89 773 /* Get the ADC clock source ------------------------------------------------*/
elmot 1:d0dfbce63a89 774 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
elmot 1:d0dfbce63a89 775
elmot 1:d0dfbce63a89 776 #if defined(SWPMI1)
elmot 1:d0dfbce63a89 777 /* Get the SWPMI1 clock source ---------------------------------------------*/
elmot 1:d0dfbce63a89 778 PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE();
elmot 1:d0dfbce63a89 779 #endif /* SWPMI1 */
elmot 1:d0dfbce63a89 780
elmot 1:d0dfbce63a89 781 #if defined(DFSDM1_Filter0)
elmot 1:d0dfbce63a89 782 /* Get the DFSDM1 clock source ---------------------------------------------*/
elmot 1:d0dfbce63a89 783 PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
elmot 1:d0dfbce63a89 784 #endif /* DFSDM1_Filter0 */
elmot 1:d0dfbce63a89 785 }
elmot 1:d0dfbce63a89 786
elmot 1:d0dfbce63a89 787 /**
elmot 1:d0dfbce63a89 788 * @brief Return the peripheral clock frequency for peripherals with clock source from PLLSAIs
elmot 1:d0dfbce63a89 789 * @note Return 0 if peripheral clock identifier not managed by this API
elmot 1:d0dfbce63a89 790 * @param PeriphClk Peripheral clock identifier
elmot 1:d0dfbce63a89 791 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 792 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
elmot 1:d0dfbce63a89 793 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
elmot 1:d0dfbce63a89 794 @if STM32L486xx
elmot 1:d0dfbce63a89 795 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM)
elmot 1:d0dfbce63a89 796 @endif
elmot 1:d0dfbce63a89 797 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
elmot 1:d0dfbce63a89 798 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
elmot 1:d0dfbce63a89 799 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
elmot 1:d0dfbce63a89 800 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
elmot 1:d0dfbce63a89 801 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
elmot 1:d0dfbce63a89 802 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
elmot 1:d0dfbce63a89 803 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
elmot 1:d0dfbce63a89 804 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
elmot 1:d0dfbce63a89 805 @if STM32L486xx
elmot 1:d0dfbce63a89 806 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2)
elmot 1:d0dfbce63a89 807 @endif
elmot 1:d0dfbce63a89 808 * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock
elmot 1:d0dfbce63a89 809 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock
elmot 1:d0dfbce63a89 810 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
elmot 1:d0dfbce63a89 811 * @arg @ref RCC_PERIPHCLK_USART2 USART1 peripheral clock
elmot 1:d0dfbce63a89 812 * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock
elmot 1:d0dfbce63a89 813 @if STM32L486xx
elmot 1:d0dfbce63a89 814 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4)
elmot 1:d0dfbce63a89 815 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5)
elmot 1:d0dfbce63a89 816 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
elmot 1:d0dfbce63a89 817 @endif
elmot 1:d0dfbce63a89 818 * @retval Frequency in Hz
elmot 1:d0dfbce63a89 819 */
elmot 1:d0dfbce63a89 820 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
elmot 1:d0dfbce63a89 821 {
elmot 1:d0dfbce63a89 822 uint32_t frequency = 0U;
elmot 1:d0dfbce63a89 823 uint32_t srcclk = 0U;
elmot 1:d0dfbce63a89 824 uint32_t pllvco = 0U, plln = 0U, pllp = 0U;
elmot 1:d0dfbce63a89 825
elmot 1:d0dfbce63a89 826 /* Check the parameters */
elmot 1:d0dfbce63a89 827 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
elmot 1:d0dfbce63a89 828
elmot 1:d0dfbce63a89 829 if(PeriphClk == RCC_PERIPHCLK_RTC)
elmot 1:d0dfbce63a89 830 {
elmot 1:d0dfbce63a89 831 /* Get the current RTC source */
elmot 1:d0dfbce63a89 832 srcclk = __HAL_RCC_GET_RTC_SOURCE();
elmot 1:d0dfbce63a89 833
elmot 1:d0dfbce63a89 834 /* Check if LSE is ready and if RTC clock selection is LSE */
elmot 1:d0dfbce63a89 835 if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
elmot 1:d0dfbce63a89 836 {
elmot 1:d0dfbce63a89 837 frequency = LSE_VALUE;
elmot 1:d0dfbce63a89 838 }
elmot 1:d0dfbce63a89 839 /* Check if LSI is ready and if RTC clock selection is LSI */
elmot 1:d0dfbce63a89 840 else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
elmot 1:d0dfbce63a89 841 {
elmot 1:d0dfbce63a89 842 frequency = LSI_VALUE;
elmot 1:d0dfbce63a89 843 }
elmot 1:d0dfbce63a89 844 /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
elmot 1:d0dfbce63a89 845 else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
elmot 1:d0dfbce63a89 846 {
elmot 1:d0dfbce63a89 847 frequency = HSE_VALUE / 32;
elmot 1:d0dfbce63a89 848 }
elmot 1:d0dfbce63a89 849 /* Clock not enabled for RTC*/
elmot 1:d0dfbce63a89 850 else
elmot 1:d0dfbce63a89 851 {
elmot 1:d0dfbce63a89 852 frequency = 0U;
elmot 1:d0dfbce63a89 853 }
elmot 1:d0dfbce63a89 854 }
elmot 1:d0dfbce63a89 855 else
elmot 1:d0dfbce63a89 856 {
elmot 1:d0dfbce63a89 857 /* Other external peripheral clock source than RTC */
elmot 1:d0dfbce63a89 858
elmot 1:d0dfbce63a89 859 /* Compute PLL clock input */
elmot 1:d0dfbce63a89 860 if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) /* MSI ? */
elmot 1:d0dfbce63a89 861 {
elmot 1:d0dfbce63a89 862 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
elmot 1:d0dfbce63a89 863 {
elmot 1:d0dfbce63a89 864 pllvco = (1U << ((__HAL_RCC_GET_MSI_RANGE() >> 4U) - 4U)) * 1000000U;
elmot 1:d0dfbce63a89 865 }
elmot 1:d0dfbce63a89 866 else
elmot 1:d0dfbce63a89 867 {
elmot 1:d0dfbce63a89 868 pllvco = 0U;
elmot 1:d0dfbce63a89 869 }
elmot 1:d0dfbce63a89 870 }
elmot 1:d0dfbce63a89 871 else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */
elmot 1:d0dfbce63a89 872 {
elmot 1:d0dfbce63a89 873 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
elmot 1:d0dfbce63a89 874 {
elmot 1:d0dfbce63a89 875 pllvco = HSI_VALUE;
elmot 1:d0dfbce63a89 876 }
elmot 1:d0dfbce63a89 877 else
elmot 1:d0dfbce63a89 878 {
elmot 1:d0dfbce63a89 879 pllvco = 0U;
elmot 1:d0dfbce63a89 880 }
elmot 1:d0dfbce63a89 881 }
elmot 1:d0dfbce63a89 882 else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */
elmot 1:d0dfbce63a89 883 {
elmot 1:d0dfbce63a89 884 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
elmot 1:d0dfbce63a89 885 {
elmot 1:d0dfbce63a89 886 pllvco = HSE_VALUE;
elmot 1:d0dfbce63a89 887 }
elmot 1:d0dfbce63a89 888 else
elmot 1:d0dfbce63a89 889 {
elmot 1:d0dfbce63a89 890 pllvco = 0U;
elmot 1:d0dfbce63a89 891 }
elmot 1:d0dfbce63a89 892 }
elmot 1:d0dfbce63a89 893 else /* No source */
elmot 1:d0dfbce63a89 894 {
elmot 1:d0dfbce63a89 895 pllvco = 0U;
elmot 1:d0dfbce63a89 896 }
elmot 1:d0dfbce63a89 897
elmot 1:d0dfbce63a89 898 /* f(PLL Source) / PLLM */
elmot 1:d0dfbce63a89 899 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U));
elmot 1:d0dfbce63a89 900
elmot 1:d0dfbce63a89 901 switch(PeriphClk)
elmot 1:d0dfbce63a89 902 {
elmot 1:d0dfbce63a89 903 #if defined(SAI2)
elmot 1:d0dfbce63a89 904
elmot 1:d0dfbce63a89 905 case RCC_PERIPHCLK_SAI1:
elmot 1:d0dfbce63a89 906 case RCC_PERIPHCLK_SAI2:
elmot 1:d0dfbce63a89 907
elmot 1:d0dfbce63a89 908 if(PeriphClk == RCC_PERIPHCLK_SAI1)
elmot 1:d0dfbce63a89 909 {
elmot 1:d0dfbce63a89 910 srcclk = __HAL_RCC_GET_SAI1_SOURCE();
elmot 1:d0dfbce63a89 911
elmot 1:d0dfbce63a89 912 if(srcclk == RCC_SAI1CLKSOURCE_PIN)
elmot 1:d0dfbce63a89 913 {
elmot 1:d0dfbce63a89 914 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
elmot 1:d0dfbce63a89 915 }
elmot 1:d0dfbce63a89 916 /* Else, PLL clock output to check below */
elmot 1:d0dfbce63a89 917 }
elmot 1:d0dfbce63a89 918 else /* RCC_PERIPHCLK_SAI2 */
elmot 1:d0dfbce63a89 919 {
elmot 1:d0dfbce63a89 920 srcclk = __HAL_RCC_GET_SAI2_SOURCE();
elmot 1:d0dfbce63a89 921
elmot 1:d0dfbce63a89 922 if(srcclk == RCC_SAI2CLKSOURCE_PIN)
elmot 1:d0dfbce63a89 923 {
elmot 1:d0dfbce63a89 924 frequency = EXTERNAL_SAI2_CLOCK_VALUE;
elmot 1:d0dfbce63a89 925 }
elmot 1:d0dfbce63a89 926 /* Else, PLL clock output to check below */
elmot 1:d0dfbce63a89 927 }
elmot 1:d0dfbce63a89 928
elmot 1:d0dfbce63a89 929 #else
elmot 1:d0dfbce63a89 930
elmot 1:d0dfbce63a89 931 case RCC_PERIPHCLK_SAI1:
elmot 1:d0dfbce63a89 932
elmot 1:d0dfbce63a89 933 if(PeriphClk == RCC_PERIPHCLK_SAI1)
elmot 1:d0dfbce63a89 934 {
elmot 1:d0dfbce63a89 935 srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL);
elmot 1:d0dfbce63a89 936
elmot 1:d0dfbce63a89 937 if(srcclk == RCC_SAI1CLKSOURCE_PIN)
elmot 1:d0dfbce63a89 938 {
elmot 1:d0dfbce63a89 939 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
elmot 1:d0dfbce63a89 940 }
elmot 1:d0dfbce63a89 941 /* Else, PLL clock output to check below */
elmot 1:d0dfbce63a89 942 }
elmot 1:d0dfbce63a89 943
elmot 1:d0dfbce63a89 944 #endif /* SAI2 */
elmot 1:d0dfbce63a89 945
elmot 1:d0dfbce63a89 946 if(frequency == 0U)
elmot 1:d0dfbce63a89 947 {
elmot 1:d0dfbce63a89 948 #if defined(SAI2)
elmot 1:d0dfbce63a89 949 if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL))
elmot 1:d0dfbce63a89 950 {
elmot 1:d0dfbce63a89 951 if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET)
elmot 1:d0dfbce63a89 952 {
elmot 1:d0dfbce63a89 953 /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */
elmot 1:d0dfbce63a89 954 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
elmot 1:d0dfbce63a89 955 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 956 pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV);
elmot 1:d0dfbce63a89 957 #endif
elmot 1:d0dfbce63a89 958 if(pllp == 0U)
elmot 1:d0dfbce63a89 959 {
elmot 1:d0dfbce63a89 960 if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET)
elmot 1:d0dfbce63a89 961 {
elmot 1:d0dfbce63a89 962 pllp = 17U;
elmot 1:d0dfbce63a89 963 }
elmot 1:d0dfbce63a89 964 else
elmot 1:d0dfbce63a89 965 {
elmot 1:d0dfbce63a89 966 pllp = 7U;
elmot 1:d0dfbce63a89 967 }
elmot 1:d0dfbce63a89 968 }
elmot 1:d0dfbce63a89 969 frequency = (pllvco * plln) / pllp;
elmot 1:d0dfbce63a89 970 }
elmot 1:d0dfbce63a89 971 }
elmot 1:d0dfbce63a89 972 else if(srcclk == 0U) /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */
elmot 1:d0dfbce63a89 973 {
elmot 1:d0dfbce63a89 974 if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET)
elmot 1:d0dfbce63a89 975 {
elmot 1:d0dfbce63a89 976 /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
elmot 1:d0dfbce63a89 977 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
elmot 1:d0dfbce63a89 978 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 979 pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV);
elmot 1:d0dfbce63a89 980 #endif
elmot 1:d0dfbce63a89 981 if(pllp == 0U)
elmot 1:d0dfbce63a89 982 {
elmot 1:d0dfbce63a89 983 if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET)
elmot 1:d0dfbce63a89 984 {
elmot 1:d0dfbce63a89 985 pllp = 17U;
elmot 1:d0dfbce63a89 986 }
elmot 1:d0dfbce63a89 987 else
elmot 1:d0dfbce63a89 988 {
elmot 1:d0dfbce63a89 989 pllp = 7U;
elmot 1:d0dfbce63a89 990 }
elmot 1:d0dfbce63a89 991 }
elmot 1:d0dfbce63a89 992 frequency = (pllvco * plln) / pllp;
elmot 1:d0dfbce63a89 993 }
elmot 1:d0dfbce63a89 994 }
elmot 1:d0dfbce63a89 995 #else
elmot 1:d0dfbce63a89 996 if(srcclk == RCC_SAI1CLKSOURCE_PLL)
elmot 1:d0dfbce63a89 997 {
elmot 1:d0dfbce63a89 998 if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != RESET)
elmot 1:d0dfbce63a89 999 {
elmot 1:d0dfbce63a89 1000 /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */
elmot 1:d0dfbce63a89 1001 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
elmot 1:d0dfbce63a89 1002 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 1003 pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV);
elmot 1:d0dfbce63a89 1004 #endif
elmot 1:d0dfbce63a89 1005 if(pllp == 0U)
elmot 1:d0dfbce63a89 1006 {
elmot 1:d0dfbce63a89 1007 if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET)
elmot 1:d0dfbce63a89 1008 {
elmot 1:d0dfbce63a89 1009 pllp = 17U;
elmot 1:d0dfbce63a89 1010 }
elmot 1:d0dfbce63a89 1011 else
elmot 1:d0dfbce63a89 1012 {
elmot 1:d0dfbce63a89 1013 pllp = 7U;
elmot 1:d0dfbce63a89 1014 }
elmot 1:d0dfbce63a89 1015 }
elmot 1:d0dfbce63a89 1016
elmot 1:d0dfbce63a89 1017 frequency = (pllvco * plln) / pllp;
elmot 1:d0dfbce63a89 1018 }
elmot 1:d0dfbce63a89 1019 else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
elmot 1:d0dfbce63a89 1020 {
elmot 1:d0dfbce63a89 1021 /* HSI automatically selected as clock source if PLLs not enabled */
elmot 1:d0dfbce63a89 1022 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1023 }
elmot 1:d0dfbce63a89 1024 else
elmot 1:d0dfbce63a89 1025 {
elmot 1:d0dfbce63a89 1026 /* No clock source */
elmot 1:d0dfbce63a89 1027 frequency = 0U;
elmot 1:d0dfbce63a89 1028 }
elmot 1:d0dfbce63a89 1029 }
elmot 1:d0dfbce63a89 1030 else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1)
elmot 1:d0dfbce63a89 1031 {
elmot 1:d0dfbce63a89 1032 if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET)
elmot 1:d0dfbce63a89 1033 {
elmot 1:d0dfbce63a89 1034 /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
elmot 1:d0dfbce63a89 1035 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
elmot 1:d0dfbce63a89 1036 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 1037 pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV);
elmot 1:d0dfbce63a89 1038 #endif
elmot 1:d0dfbce63a89 1039 if(pllp == 0U)
elmot 1:d0dfbce63a89 1040 {
elmot 1:d0dfbce63a89 1041 if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET)
elmot 1:d0dfbce63a89 1042 {
elmot 1:d0dfbce63a89 1043 pllp = 17U;
elmot 1:d0dfbce63a89 1044 }
elmot 1:d0dfbce63a89 1045 else
elmot 1:d0dfbce63a89 1046 {
elmot 1:d0dfbce63a89 1047 pllp = 7U;
elmot 1:d0dfbce63a89 1048 }
elmot 1:d0dfbce63a89 1049 }
elmot 1:d0dfbce63a89 1050
elmot 1:d0dfbce63a89 1051 frequency = (pllvco * plln) / pllp;
elmot 1:d0dfbce63a89 1052 }
elmot 1:d0dfbce63a89 1053 else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
elmot 1:d0dfbce63a89 1054 {
elmot 1:d0dfbce63a89 1055 /* HSI automatically selected as clock source if PLLs not enabled */
elmot 1:d0dfbce63a89 1056 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1057 }
elmot 1:d0dfbce63a89 1058 else
elmot 1:d0dfbce63a89 1059 {
elmot 1:d0dfbce63a89 1060 /* No clock source */
elmot 1:d0dfbce63a89 1061 frequency = 0U;
elmot 1:d0dfbce63a89 1062 }
elmot 1:d0dfbce63a89 1063 }
elmot 1:d0dfbce63a89 1064 #endif /* SAI2 */
elmot 1:d0dfbce63a89 1065
elmot 1:d0dfbce63a89 1066 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 1067
elmot 1:d0dfbce63a89 1068 else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2))
elmot 1:d0dfbce63a89 1069 {
elmot 1:d0dfbce63a89 1070 if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET)
elmot 1:d0dfbce63a89 1071 {
elmot 1:d0dfbce63a89 1072 /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */
elmot 1:d0dfbce63a89 1073 plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N);
elmot 1:d0dfbce63a89 1074 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 1075 pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV);
elmot 1:d0dfbce63a89 1076 #endif
elmot 1:d0dfbce63a89 1077 if(pllp == 0U)
elmot 1:d0dfbce63a89 1078 {
elmot 1:d0dfbce63a89 1079 if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET)
elmot 1:d0dfbce63a89 1080 {
elmot 1:d0dfbce63a89 1081 pllp = 17U;
elmot 1:d0dfbce63a89 1082 }
elmot 1:d0dfbce63a89 1083 else
elmot 1:d0dfbce63a89 1084 {
elmot 1:d0dfbce63a89 1085 pllp = 7U;
elmot 1:d0dfbce63a89 1086 }
elmot 1:d0dfbce63a89 1087 }
elmot 1:d0dfbce63a89 1088 frequency = (pllvco * plln) / pllp;
elmot 1:d0dfbce63a89 1089 }
elmot 1:d0dfbce63a89 1090 }
elmot 1:d0dfbce63a89 1091
elmot 1:d0dfbce63a89 1092 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 1093
elmot 1:d0dfbce63a89 1094 else
elmot 1:d0dfbce63a89 1095 {
elmot 1:d0dfbce63a89 1096 /* No clock source */
elmot 1:d0dfbce63a89 1097 frequency = 0U;
elmot 1:d0dfbce63a89 1098 }
elmot 1:d0dfbce63a89 1099 }
elmot 1:d0dfbce63a89 1100 break;
elmot 1:d0dfbce63a89 1101
elmot 1:d0dfbce63a89 1102 #if defined(USB_OTG_FS) || defined(USB)
elmot 1:d0dfbce63a89 1103
elmot 1:d0dfbce63a89 1104 case RCC_PERIPHCLK_USB:
elmot 1:d0dfbce63a89 1105
elmot 1:d0dfbce63a89 1106 #endif /* USB_OTG_FS || USB */
elmot 1:d0dfbce63a89 1107
elmot 1:d0dfbce63a89 1108 case RCC_PERIPHCLK_RNG:
elmot 1:d0dfbce63a89 1109
elmot 1:d0dfbce63a89 1110 #if defined(SDMMC1)
elmot 1:d0dfbce63a89 1111
elmot 1:d0dfbce63a89 1112 case RCC_PERIPHCLK_SDMMC1:
elmot 1:d0dfbce63a89 1113
elmot 1:d0dfbce63a89 1114 #endif /* SDMMC1 */
elmot 1:d0dfbce63a89 1115
elmot 1:d0dfbce63a89 1116 srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);
elmot 1:d0dfbce63a89 1117
elmot 1:d0dfbce63a89 1118 if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */
elmot 1:d0dfbce63a89 1119 {
elmot 1:d0dfbce63a89 1120 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
elmot 1:d0dfbce63a89 1121 {
elmot 1:d0dfbce63a89 1122 frequency = (1U << ((__HAL_RCC_GET_MSI_RANGE() >> 4U) - 4U)) * 1000000U;
elmot 1:d0dfbce63a89 1123 }
elmot 1:d0dfbce63a89 1124 else
elmot 1:d0dfbce63a89 1125 {
elmot 1:d0dfbce63a89 1126 frequency = 0U;
elmot 1:d0dfbce63a89 1127 }
elmot 1:d0dfbce63a89 1128 }
elmot 1:d0dfbce63a89 1129 else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL ? */
elmot 1:d0dfbce63a89 1130 {
elmot 1:d0dfbce63a89 1131 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
elmot 1:d0dfbce63a89 1132 {
elmot 1:d0dfbce63a89 1133 /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */
elmot 1:d0dfbce63a89 1134 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
elmot 1:d0dfbce63a89 1135 frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U);
elmot 1:d0dfbce63a89 1136 }
elmot 1:d0dfbce63a89 1137 else
elmot 1:d0dfbce63a89 1138 {
elmot 1:d0dfbce63a89 1139 frequency = 0U;
elmot 1:d0dfbce63a89 1140 }
elmot 1:d0dfbce63a89 1141 }
elmot 1:d0dfbce63a89 1142 else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */
elmot 1:d0dfbce63a89 1143 {
elmot 1:d0dfbce63a89 1144 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))
elmot 1:d0dfbce63a89 1145 {
elmot 1:d0dfbce63a89 1146 /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */
elmot 1:d0dfbce63a89 1147 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
elmot 1:d0dfbce63a89 1148 frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) + 1U) << 1U);
elmot 1:d0dfbce63a89 1149 }
elmot 1:d0dfbce63a89 1150 else
elmot 1:d0dfbce63a89 1151 {
elmot 1:d0dfbce63a89 1152 frequency = 0U;
elmot 1:d0dfbce63a89 1153 }
elmot 1:d0dfbce63a89 1154 }
elmot 1:d0dfbce63a89 1155 #if defined(RCC_HSI48_SUPPORT)
elmot 1:d0dfbce63a89 1156 else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */
elmot 1:d0dfbce63a89 1157 {
elmot 1:d0dfbce63a89 1158 frequency = HSI48_VALUE;
elmot 1:d0dfbce63a89 1159 }
elmot 1:d0dfbce63a89 1160 else /* No clock source */
elmot 1:d0dfbce63a89 1161 {
elmot 1:d0dfbce63a89 1162 frequency = 0U;
elmot 1:d0dfbce63a89 1163 }
elmot 1:d0dfbce63a89 1164 #else
elmot 1:d0dfbce63a89 1165 else /* No clock source */
elmot 1:d0dfbce63a89 1166 {
elmot 1:d0dfbce63a89 1167 frequency = 0U;
elmot 1:d0dfbce63a89 1168 }
elmot 1:d0dfbce63a89 1169 #endif /* RCC_HSI48_SUPPORT */
elmot 1:d0dfbce63a89 1170 break;
elmot 1:d0dfbce63a89 1171
elmot 1:d0dfbce63a89 1172 case RCC_PERIPHCLK_USART1:
elmot 1:d0dfbce63a89 1173 /* Get the current USART1 source */
elmot 1:d0dfbce63a89 1174 srcclk = __HAL_RCC_GET_USART1_SOURCE();
elmot 1:d0dfbce63a89 1175
elmot 1:d0dfbce63a89 1176 if(srcclk == RCC_USART1CLKSOURCE_PCLK2)
elmot 1:d0dfbce63a89 1177 {
elmot 1:d0dfbce63a89 1178 frequency = HAL_RCC_GetPCLK2Freq();
elmot 1:d0dfbce63a89 1179 }
elmot 1:d0dfbce63a89 1180 else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK)
elmot 1:d0dfbce63a89 1181 {
elmot 1:d0dfbce63a89 1182 frequency = HAL_RCC_GetSysClockFreq();
elmot 1:d0dfbce63a89 1183 }
elmot 1:d0dfbce63a89 1184 else if((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
elmot 1:d0dfbce63a89 1185 {
elmot 1:d0dfbce63a89 1186 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1187 }
elmot 1:d0dfbce63a89 1188 else if((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
elmot 1:d0dfbce63a89 1189 {
elmot 1:d0dfbce63a89 1190 frequency = LSE_VALUE;
elmot 1:d0dfbce63a89 1191 }
elmot 1:d0dfbce63a89 1192 /* Clock not enabled for USART1 */
elmot 1:d0dfbce63a89 1193 else
elmot 1:d0dfbce63a89 1194 {
elmot 1:d0dfbce63a89 1195 frequency = 0U;
elmot 1:d0dfbce63a89 1196 }
elmot 1:d0dfbce63a89 1197 break;
elmot 1:d0dfbce63a89 1198
elmot 1:d0dfbce63a89 1199 case RCC_PERIPHCLK_USART2:
elmot 1:d0dfbce63a89 1200 /* Get the current USART2 source */
elmot 1:d0dfbce63a89 1201 srcclk = __HAL_RCC_GET_USART2_SOURCE();
elmot 1:d0dfbce63a89 1202
elmot 1:d0dfbce63a89 1203 if(srcclk == RCC_USART2CLKSOURCE_PCLK1)
elmot 1:d0dfbce63a89 1204 {
elmot 1:d0dfbce63a89 1205 frequency = HAL_RCC_GetPCLK1Freq();
elmot 1:d0dfbce63a89 1206 }
elmot 1:d0dfbce63a89 1207 else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK)
elmot 1:d0dfbce63a89 1208 {
elmot 1:d0dfbce63a89 1209 frequency = HAL_RCC_GetSysClockFreq();
elmot 1:d0dfbce63a89 1210 }
elmot 1:d0dfbce63a89 1211 else if((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
elmot 1:d0dfbce63a89 1212 {
elmot 1:d0dfbce63a89 1213 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1214 }
elmot 1:d0dfbce63a89 1215 else if((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
elmot 1:d0dfbce63a89 1216 {
elmot 1:d0dfbce63a89 1217 frequency = LSE_VALUE;
elmot 1:d0dfbce63a89 1218 }
elmot 1:d0dfbce63a89 1219 /* Clock not enabled for USART2 */
elmot 1:d0dfbce63a89 1220 else
elmot 1:d0dfbce63a89 1221 {
elmot 1:d0dfbce63a89 1222 frequency = 0U;
elmot 1:d0dfbce63a89 1223 }
elmot 1:d0dfbce63a89 1224 break;
elmot 1:d0dfbce63a89 1225
elmot 1:d0dfbce63a89 1226 #if defined(USART3)
elmot 1:d0dfbce63a89 1227
elmot 1:d0dfbce63a89 1228 case RCC_PERIPHCLK_USART3:
elmot 1:d0dfbce63a89 1229 /* Get the current USART3 source */
elmot 1:d0dfbce63a89 1230 srcclk = __HAL_RCC_GET_USART3_SOURCE();
elmot 1:d0dfbce63a89 1231
elmot 1:d0dfbce63a89 1232 if(srcclk == RCC_USART3CLKSOURCE_PCLK1)
elmot 1:d0dfbce63a89 1233 {
elmot 1:d0dfbce63a89 1234 frequency = HAL_RCC_GetPCLK1Freq();
elmot 1:d0dfbce63a89 1235 }
elmot 1:d0dfbce63a89 1236 else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK)
elmot 1:d0dfbce63a89 1237 {
elmot 1:d0dfbce63a89 1238 frequency = HAL_RCC_GetSysClockFreq();
elmot 1:d0dfbce63a89 1239 }
elmot 1:d0dfbce63a89 1240 else if((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
elmot 1:d0dfbce63a89 1241 {
elmot 1:d0dfbce63a89 1242 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1243 }
elmot 1:d0dfbce63a89 1244 else if((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
elmot 1:d0dfbce63a89 1245 {
elmot 1:d0dfbce63a89 1246 frequency = LSE_VALUE;
elmot 1:d0dfbce63a89 1247 }
elmot 1:d0dfbce63a89 1248 /* Clock not enabled for USART3 */
elmot 1:d0dfbce63a89 1249 else
elmot 1:d0dfbce63a89 1250 {
elmot 1:d0dfbce63a89 1251 frequency = 0U;
elmot 1:d0dfbce63a89 1252 }
elmot 1:d0dfbce63a89 1253 break;
elmot 1:d0dfbce63a89 1254
elmot 1:d0dfbce63a89 1255 #endif /* USART3 */
elmot 1:d0dfbce63a89 1256
elmot 1:d0dfbce63a89 1257 #if defined(UART4)
elmot 1:d0dfbce63a89 1258
elmot 1:d0dfbce63a89 1259 case RCC_PERIPHCLK_UART4:
elmot 1:d0dfbce63a89 1260 /* Get the current UART4 source */
elmot 1:d0dfbce63a89 1261 srcclk = __HAL_RCC_GET_UART4_SOURCE();
elmot 1:d0dfbce63a89 1262
elmot 1:d0dfbce63a89 1263 if(srcclk == RCC_UART4CLKSOURCE_PCLK1)
elmot 1:d0dfbce63a89 1264 {
elmot 1:d0dfbce63a89 1265 frequency = HAL_RCC_GetPCLK1Freq();
elmot 1:d0dfbce63a89 1266 }
elmot 1:d0dfbce63a89 1267 else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK)
elmot 1:d0dfbce63a89 1268 {
elmot 1:d0dfbce63a89 1269 frequency = HAL_RCC_GetSysClockFreq();
elmot 1:d0dfbce63a89 1270 }
elmot 1:d0dfbce63a89 1271 else if((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
elmot 1:d0dfbce63a89 1272 {
elmot 1:d0dfbce63a89 1273 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1274 }
elmot 1:d0dfbce63a89 1275 else if((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
elmot 1:d0dfbce63a89 1276 {
elmot 1:d0dfbce63a89 1277 frequency = LSE_VALUE;
elmot 1:d0dfbce63a89 1278 }
elmot 1:d0dfbce63a89 1279 /* Clock not enabled for UART4 */
elmot 1:d0dfbce63a89 1280 else
elmot 1:d0dfbce63a89 1281 {
elmot 1:d0dfbce63a89 1282 frequency = 0U;
elmot 1:d0dfbce63a89 1283 }
elmot 1:d0dfbce63a89 1284 break;
elmot 1:d0dfbce63a89 1285
elmot 1:d0dfbce63a89 1286 #endif /* UART4 */
elmot 1:d0dfbce63a89 1287
elmot 1:d0dfbce63a89 1288 #if defined(UART5)
elmot 1:d0dfbce63a89 1289
elmot 1:d0dfbce63a89 1290 case RCC_PERIPHCLK_UART5:
elmot 1:d0dfbce63a89 1291 /* Get the current UART5 source */
elmot 1:d0dfbce63a89 1292 srcclk = __HAL_RCC_GET_UART5_SOURCE();
elmot 1:d0dfbce63a89 1293
elmot 1:d0dfbce63a89 1294 if(srcclk == RCC_UART5CLKSOURCE_PCLK1)
elmot 1:d0dfbce63a89 1295 {
elmot 1:d0dfbce63a89 1296 frequency = HAL_RCC_GetPCLK1Freq();
elmot 1:d0dfbce63a89 1297 }
elmot 1:d0dfbce63a89 1298 else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK)
elmot 1:d0dfbce63a89 1299 {
elmot 1:d0dfbce63a89 1300 frequency = HAL_RCC_GetSysClockFreq();
elmot 1:d0dfbce63a89 1301 }
elmot 1:d0dfbce63a89 1302 else if((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
elmot 1:d0dfbce63a89 1303 {
elmot 1:d0dfbce63a89 1304 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1305 }
elmot 1:d0dfbce63a89 1306 else if((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
elmot 1:d0dfbce63a89 1307 {
elmot 1:d0dfbce63a89 1308 frequency = LSE_VALUE;
elmot 1:d0dfbce63a89 1309 }
elmot 1:d0dfbce63a89 1310 /* Clock not enabled for UART5 */
elmot 1:d0dfbce63a89 1311 else
elmot 1:d0dfbce63a89 1312 {
elmot 1:d0dfbce63a89 1313 frequency = 0U;
elmot 1:d0dfbce63a89 1314 }
elmot 1:d0dfbce63a89 1315 break;
elmot 1:d0dfbce63a89 1316
elmot 1:d0dfbce63a89 1317 #endif /* UART5 */
elmot 1:d0dfbce63a89 1318
elmot 1:d0dfbce63a89 1319 case RCC_PERIPHCLK_LPUART1:
elmot 1:d0dfbce63a89 1320 /* Get the current LPUART1 source */
elmot 1:d0dfbce63a89 1321 srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
elmot 1:d0dfbce63a89 1322
elmot 1:d0dfbce63a89 1323 if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
elmot 1:d0dfbce63a89 1324 {
elmot 1:d0dfbce63a89 1325 frequency = HAL_RCC_GetPCLK1Freq();
elmot 1:d0dfbce63a89 1326 }
elmot 1:d0dfbce63a89 1327 else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
elmot 1:d0dfbce63a89 1328 {
elmot 1:d0dfbce63a89 1329 frequency = HAL_RCC_GetSysClockFreq();
elmot 1:d0dfbce63a89 1330 }
elmot 1:d0dfbce63a89 1331 else if((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
elmot 1:d0dfbce63a89 1332 {
elmot 1:d0dfbce63a89 1333 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1334 }
elmot 1:d0dfbce63a89 1335 else if((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
elmot 1:d0dfbce63a89 1336 {
elmot 1:d0dfbce63a89 1337 frequency = LSE_VALUE;
elmot 1:d0dfbce63a89 1338 }
elmot 1:d0dfbce63a89 1339 /* Clock not enabled for LPUART1 */
elmot 1:d0dfbce63a89 1340 else
elmot 1:d0dfbce63a89 1341 {
elmot 1:d0dfbce63a89 1342 frequency = 0U;
elmot 1:d0dfbce63a89 1343 }
elmot 1:d0dfbce63a89 1344 break;
elmot 1:d0dfbce63a89 1345
elmot 1:d0dfbce63a89 1346 case RCC_PERIPHCLK_ADC:
elmot 1:d0dfbce63a89 1347
elmot 1:d0dfbce63a89 1348 srcclk = __HAL_RCC_GET_ADC_SOURCE();
elmot 1:d0dfbce63a89 1349
elmot 1:d0dfbce63a89 1350 if(srcclk == RCC_ADCCLKSOURCE_SYSCLK)
elmot 1:d0dfbce63a89 1351 {
elmot 1:d0dfbce63a89 1352 frequency = HAL_RCC_GetSysClockFreq();
elmot 1:d0dfbce63a89 1353 }
elmot 1:d0dfbce63a89 1354 else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI1)
elmot 1:d0dfbce63a89 1355 {
elmot 1:d0dfbce63a89 1356 if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET)
elmot 1:d0dfbce63a89 1357 {
elmot 1:d0dfbce63a89 1358 /* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */
elmot 1:d0dfbce63a89 1359 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
elmot 1:d0dfbce63a89 1360 frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) + 1U) << 1U);
elmot 1:d0dfbce63a89 1361 }
elmot 1:d0dfbce63a89 1362 }
elmot 1:d0dfbce63a89 1363 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
elmot 1:d0dfbce63a89 1364 else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI2)
elmot 1:d0dfbce63a89 1365 {
elmot 1:d0dfbce63a89 1366 if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET)
elmot 1:d0dfbce63a89 1367 {
elmot 1:d0dfbce63a89 1368 /* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */
elmot 1:d0dfbce63a89 1369 plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N);
elmot 1:d0dfbce63a89 1370 frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) + 1U) << 1U);
elmot 1:d0dfbce63a89 1371 }
elmot 1:d0dfbce63a89 1372 }
elmot 1:d0dfbce63a89 1373 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
elmot 1:d0dfbce63a89 1374 /* Clock not enabled for ADC */
elmot 1:d0dfbce63a89 1375 else
elmot 1:d0dfbce63a89 1376 {
elmot 1:d0dfbce63a89 1377 frequency = 0U;
elmot 1:d0dfbce63a89 1378 }
elmot 1:d0dfbce63a89 1379 break;
elmot 1:d0dfbce63a89 1380
elmot 1:d0dfbce63a89 1381 #if defined(DFSDM1_Filter0)
elmot 1:d0dfbce63a89 1382
elmot 1:d0dfbce63a89 1383 case RCC_PERIPHCLK_DFSDM1:
elmot 1:d0dfbce63a89 1384 /* Get the current DFSDM1 source */
elmot 1:d0dfbce63a89 1385 srcclk = __HAL_RCC_GET_DFSDM1_SOURCE();
elmot 1:d0dfbce63a89 1386
elmot 1:d0dfbce63a89 1387 if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK)
elmot 1:d0dfbce63a89 1388 {
elmot 1:d0dfbce63a89 1389 frequency = HAL_RCC_GetPCLK1Freq();
elmot 1:d0dfbce63a89 1390 }
elmot 1:d0dfbce63a89 1391 else
elmot 1:d0dfbce63a89 1392 {
elmot 1:d0dfbce63a89 1393 frequency = HAL_RCC_GetSysClockFreq();
elmot 1:d0dfbce63a89 1394 }
elmot 1:d0dfbce63a89 1395 break;
elmot 1:d0dfbce63a89 1396
elmot 1:d0dfbce63a89 1397 #endif /* DFSDM1_Filter0 */
elmot 1:d0dfbce63a89 1398
elmot 1:d0dfbce63a89 1399 case RCC_PERIPHCLK_I2C1:
elmot 1:d0dfbce63a89 1400 /* Get the current I2C1 source */
elmot 1:d0dfbce63a89 1401 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
elmot 1:d0dfbce63a89 1402
elmot 1:d0dfbce63a89 1403 if(srcclk == RCC_I2C1CLKSOURCE_PCLK1)
elmot 1:d0dfbce63a89 1404 {
elmot 1:d0dfbce63a89 1405 frequency = HAL_RCC_GetPCLK1Freq();
elmot 1:d0dfbce63a89 1406 }
elmot 1:d0dfbce63a89 1407 else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
elmot 1:d0dfbce63a89 1408 {
elmot 1:d0dfbce63a89 1409 frequency = HAL_RCC_GetSysClockFreq();
elmot 1:d0dfbce63a89 1410 }
elmot 1:d0dfbce63a89 1411 else if((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
elmot 1:d0dfbce63a89 1412 {
elmot 1:d0dfbce63a89 1413 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1414 }
elmot 1:d0dfbce63a89 1415 /* Clock not enabled for I2C1 */
elmot 1:d0dfbce63a89 1416 else
elmot 1:d0dfbce63a89 1417 {
elmot 1:d0dfbce63a89 1418 frequency = 0U;
elmot 1:d0dfbce63a89 1419 }
elmot 1:d0dfbce63a89 1420 break;
elmot 1:d0dfbce63a89 1421
elmot 1:d0dfbce63a89 1422 #if defined(I2C2)
elmot 1:d0dfbce63a89 1423
elmot 1:d0dfbce63a89 1424 case RCC_PERIPHCLK_I2C2:
elmot 1:d0dfbce63a89 1425 /* Get the current I2C2 source */
elmot 1:d0dfbce63a89 1426 srcclk = __HAL_RCC_GET_I2C2_SOURCE();
elmot 1:d0dfbce63a89 1427
elmot 1:d0dfbce63a89 1428 if(srcclk == RCC_I2C2CLKSOURCE_PCLK1)
elmot 1:d0dfbce63a89 1429 {
elmot 1:d0dfbce63a89 1430 frequency = HAL_RCC_GetPCLK1Freq();
elmot 1:d0dfbce63a89 1431 }
elmot 1:d0dfbce63a89 1432 else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
elmot 1:d0dfbce63a89 1433 {
elmot 1:d0dfbce63a89 1434 frequency = HAL_RCC_GetSysClockFreq();
elmot 1:d0dfbce63a89 1435 }
elmot 1:d0dfbce63a89 1436 else if((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
elmot 1:d0dfbce63a89 1437 {
elmot 1:d0dfbce63a89 1438 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1439 }
elmot 1:d0dfbce63a89 1440 /* Clock not enabled for I2C2 */
elmot 1:d0dfbce63a89 1441 else
elmot 1:d0dfbce63a89 1442 {
elmot 1:d0dfbce63a89 1443 frequency = 0U;
elmot 1:d0dfbce63a89 1444 }
elmot 1:d0dfbce63a89 1445 break;
elmot 1:d0dfbce63a89 1446
elmot 1:d0dfbce63a89 1447 #endif /* I2C2 */
elmot 1:d0dfbce63a89 1448
elmot 1:d0dfbce63a89 1449 case RCC_PERIPHCLK_I2C3:
elmot 1:d0dfbce63a89 1450 /* Get the current I2C3 source */
elmot 1:d0dfbce63a89 1451 srcclk = __HAL_RCC_GET_I2C3_SOURCE();
elmot 1:d0dfbce63a89 1452
elmot 1:d0dfbce63a89 1453 if(srcclk == RCC_I2C3CLKSOURCE_PCLK1)
elmot 1:d0dfbce63a89 1454 {
elmot 1:d0dfbce63a89 1455 frequency = HAL_RCC_GetPCLK1Freq();
elmot 1:d0dfbce63a89 1456 }
elmot 1:d0dfbce63a89 1457 else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
elmot 1:d0dfbce63a89 1458 {
elmot 1:d0dfbce63a89 1459 frequency = HAL_RCC_GetSysClockFreq();
elmot 1:d0dfbce63a89 1460 }
elmot 1:d0dfbce63a89 1461 else if((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
elmot 1:d0dfbce63a89 1462 {
elmot 1:d0dfbce63a89 1463 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1464 }
elmot 1:d0dfbce63a89 1465 /* Clock not enabled for I2C3 */
elmot 1:d0dfbce63a89 1466 else
elmot 1:d0dfbce63a89 1467 {
elmot 1:d0dfbce63a89 1468 frequency = 0U;
elmot 1:d0dfbce63a89 1469 }
elmot 1:d0dfbce63a89 1470 break;
elmot 1:d0dfbce63a89 1471
elmot 1:d0dfbce63a89 1472 case RCC_PERIPHCLK_LPTIM1:
elmot 1:d0dfbce63a89 1473 /* Get the current LPTIM1 source */
elmot 1:d0dfbce63a89 1474 srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
elmot 1:d0dfbce63a89 1475
elmot 1:d0dfbce63a89 1476 if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK)
elmot 1:d0dfbce63a89 1477 {
elmot 1:d0dfbce63a89 1478 frequency = HAL_RCC_GetPCLK1Freq();
elmot 1:d0dfbce63a89 1479 }
elmot 1:d0dfbce63a89 1480 else if((srcclk == RCC_LPTIM1CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
elmot 1:d0dfbce63a89 1481 {
elmot 1:d0dfbce63a89 1482 frequency = LSI_VALUE;
elmot 1:d0dfbce63a89 1483 }
elmot 1:d0dfbce63a89 1484 else if((srcclk == RCC_LPTIM1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
elmot 1:d0dfbce63a89 1485 {
elmot 1:d0dfbce63a89 1486 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1487 }
elmot 1:d0dfbce63a89 1488 else if ((srcclk == RCC_LPTIM1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
elmot 1:d0dfbce63a89 1489 {
elmot 1:d0dfbce63a89 1490 frequency = LSE_VALUE;
elmot 1:d0dfbce63a89 1491 }
elmot 1:d0dfbce63a89 1492 /* Clock not enabled for LPTIM1 */
elmot 1:d0dfbce63a89 1493 else
elmot 1:d0dfbce63a89 1494 {
elmot 1:d0dfbce63a89 1495 frequency = 0U;
elmot 1:d0dfbce63a89 1496 }
elmot 1:d0dfbce63a89 1497 break;
elmot 1:d0dfbce63a89 1498
elmot 1:d0dfbce63a89 1499 case RCC_PERIPHCLK_LPTIM2:
elmot 1:d0dfbce63a89 1500 /* Get the current LPTIM2 source */
elmot 1:d0dfbce63a89 1501 srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
elmot 1:d0dfbce63a89 1502
elmot 1:d0dfbce63a89 1503 if(srcclk == RCC_LPTIM2CLKSOURCE_PCLK)
elmot 1:d0dfbce63a89 1504 {
elmot 1:d0dfbce63a89 1505 frequency = HAL_RCC_GetPCLK1Freq();
elmot 1:d0dfbce63a89 1506 }
elmot 1:d0dfbce63a89 1507 else if((srcclk == RCC_LPTIM2CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
elmot 1:d0dfbce63a89 1508 {
elmot 1:d0dfbce63a89 1509 frequency = LSI_VALUE;
elmot 1:d0dfbce63a89 1510 }
elmot 1:d0dfbce63a89 1511 else if((srcclk == RCC_LPTIM2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
elmot 1:d0dfbce63a89 1512 {
elmot 1:d0dfbce63a89 1513 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1514 }
elmot 1:d0dfbce63a89 1515 else if ((srcclk == RCC_LPTIM2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
elmot 1:d0dfbce63a89 1516 {
elmot 1:d0dfbce63a89 1517 frequency = LSE_VALUE;
elmot 1:d0dfbce63a89 1518 }
elmot 1:d0dfbce63a89 1519 /* Clock not enabled for LPTIM2 */
elmot 1:d0dfbce63a89 1520 else
elmot 1:d0dfbce63a89 1521 {
elmot 1:d0dfbce63a89 1522 frequency = 0U;
elmot 1:d0dfbce63a89 1523 }
elmot 1:d0dfbce63a89 1524 break;
elmot 1:d0dfbce63a89 1525
elmot 1:d0dfbce63a89 1526 #if defined(SWPMI1)
elmot 1:d0dfbce63a89 1527
elmot 1:d0dfbce63a89 1528 case RCC_PERIPHCLK_SWPMI1:
elmot 1:d0dfbce63a89 1529 /* Get the current SWPMI1 source */
elmot 1:d0dfbce63a89 1530 srcclk = __HAL_RCC_GET_SWPMI1_SOURCE();
elmot 1:d0dfbce63a89 1531
elmot 1:d0dfbce63a89 1532 if(srcclk == RCC_SWPMI1CLKSOURCE_PCLK)
elmot 1:d0dfbce63a89 1533 {
elmot 1:d0dfbce63a89 1534 frequency = HAL_RCC_GetPCLK1Freq();
elmot 1:d0dfbce63a89 1535 }
elmot 1:d0dfbce63a89 1536 else if((srcclk == RCC_SWPMI1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
elmot 1:d0dfbce63a89 1537 {
elmot 1:d0dfbce63a89 1538 frequency = HSI_VALUE;
elmot 1:d0dfbce63a89 1539 }
elmot 1:d0dfbce63a89 1540 /* Clock not enabled for SWPMI1 */
elmot 1:d0dfbce63a89 1541 else
elmot 1:d0dfbce63a89 1542 {
elmot 1:d0dfbce63a89 1543 frequency = 0U;
elmot 1:d0dfbce63a89 1544 }
elmot 1:d0dfbce63a89 1545 break;
elmot 1:d0dfbce63a89 1546
elmot 1:d0dfbce63a89 1547 #endif /* SWPMI1 */
elmot 1:d0dfbce63a89 1548
elmot 1:d0dfbce63a89 1549 default:
elmot 1:d0dfbce63a89 1550 break;
elmot 1:d0dfbce63a89 1551 }
elmot 1:d0dfbce63a89 1552 }
elmot 1:d0dfbce63a89 1553
elmot 1:d0dfbce63a89 1554 return(frequency);
elmot 1:d0dfbce63a89 1555 }
elmot 1:d0dfbce63a89 1556
elmot 1:d0dfbce63a89 1557 /**
elmot 1:d0dfbce63a89 1558 * @}
elmot 1:d0dfbce63a89 1559 */
elmot 1:d0dfbce63a89 1560
elmot 1:d0dfbce63a89 1561 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
elmot 1:d0dfbce63a89 1562 * @brief Extended Clock management functions
elmot 1:d0dfbce63a89 1563 *
elmot 1:d0dfbce63a89 1564 @verbatim
elmot 1:d0dfbce63a89 1565 ===============================================================================
elmot 1:d0dfbce63a89 1566 ##### Extended clock management functions #####
elmot 1:d0dfbce63a89 1567 ===============================================================================
elmot 1:d0dfbce63a89 1568 [..]
elmot 1:d0dfbce63a89 1569 This subsection provides a set of functions allowing to control the
elmot 1:d0dfbce63a89 1570 activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS,
elmot 1:d0dfbce63a89 1571 Low speed clock output and clock after wake-up from STOP mode.
elmot 1:d0dfbce63a89 1572 @endverbatim
elmot 1:d0dfbce63a89 1573 * @{
elmot 1:d0dfbce63a89 1574 */
elmot 1:d0dfbce63a89 1575
elmot 1:d0dfbce63a89 1576 /**
elmot 1:d0dfbce63a89 1577 * @brief Enable PLLSAI1.
elmot 1:d0dfbce63a89 1578 * @param PLLSAI1Init pointer to an RCC_PLLSAI1InitTypeDef structure that
elmot 1:d0dfbce63a89 1579 * contains the configuration information for the PLLSAI1
elmot 1:d0dfbce63a89 1580 * @retval HAL status
elmot 1:d0dfbce63a89 1581 */
elmot 1:d0dfbce63a89 1582 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init)
elmot 1:d0dfbce63a89 1583 {
elmot 1:d0dfbce63a89 1584 uint32_t tickstart = 0U;
elmot 1:d0dfbce63a89 1585 HAL_StatusTypeDef status = HAL_OK;
elmot 1:d0dfbce63a89 1586
elmot 1:d0dfbce63a89 1587 /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
elmot 1:d0dfbce63a89 1588 assert_param(IS_RCC_PLLSAI1SOURCE(PLLSAI1Init->PLLSAI1Source));
elmot 1:d0dfbce63a89 1589 assert_param(IS_RCC_PLLSAI1M_VALUE(PLLSAI1Init->PLLSAI1M));
elmot 1:d0dfbce63a89 1590 assert_param(IS_RCC_PLLSAI1N_VALUE(PLLSAI1Init->PLLSAI1N));
elmot 1:d0dfbce63a89 1591 assert_param(IS_RCC_PLLSAI1P_VALUE(PLLSAI1Init->PLLSAI1P));
elmot 1:d0dfbce63a89 1592 assert_param(IS_RCC_PLLSAI1Q_VALUE(PLLSAI1Init->PLLSAI1Q));
elmot 1:d0dfbce63a89 1593 assert_param(IS_RCC_PLLSAI1R_VALUE(PLLSAI1Init->PLLSAI1R));
elmot 1:d0dfbce63a89 1594 assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut));
elmot 1:d0dfbce63a89 1595
elmot 1:d0dfbce63a89 1596 /* Disable the PLLSAI1 */
elmot 1:d0dfbce63a89 1597 __HAL_RCC_PLLSAI1_DISABLE();
elmot 1:d0dfbce63a89 1598
elmot 1:d0dfbce63a89 1599 /* Get Start Tick*/
elmot 1:d0dfbce63a89 1600 tickstart = HAL_GetTick();
elmot 1:d0dfbce63a89 1601
elmot 1:d0dfbce63a89 1602 /* Wait till PLLSAI1 is ready to be updated */
elmot 1:d0dfbce63a89 1603 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
elmot 1:d0dfbce63a89 1604 {
elmot 1:d0dfbce63a89 1605 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
elmot 1:d0dfbce63a89 1606 {
elmot 1:d0dfbce63a89 1607 status = HAL_TIMEOUT;
elmot 1:d0dfbce63a89 1608 break;
elmot 1:d0dfbce63a89 1609 }
elmot 1:d0dfbce63a89 1610 }
elmot 1:d0dfbce63a89 1611
elmot 1:d0dfbce63a89 1612 if(status == HAL_OK)
elmot 1:d0dfbce63a89 1613 {
elmot 1:d0dfbce63a89 1614 /* Configure the PLLSAI1 Multiplication factor N */
elmot 1:d0dfbce63a89 1615 /* Configure the PLLSAI1 Division factors P, Q and R */
elmot 1:d0dfbce63a89 1616 __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R);
elmot 1:d0dfbce63a89 1617 /* Configure the PLLSAI1 Clock output(s) */
elmot 1:d0dfbce63a89 1618 __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut);
elmot 1:d0dfbce63a89 1619
elmot 1:d0dfbce63a89 1620 /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
elmot 1:d0dfbce63a89 1621 __HAL_RCC_PLLSAI1_ENABLE();
elmot 1:d0dfbce63a89 1622
elmot 1:d0dfbce63a89 1623 /* Get Start Tick*/
elmot 1:d0dfbce63a89 1624 tickstart = HAL_GetTick();
elmot 1:d0dfbce63a89 1625
elmot 1:d0dfbce63a89 1626 /* Wait till PLLSAI1 is ready */
elmot 1:d0dfbce63a89 1627 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
elmot 1:d0dfbce63a89 1628 {
elmot 1:d0dfbce63a89 1629 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
elmot 1:d0dfbce63a89 1630 {
elmot 1:d0dfbce63a89 1631 status = HAL_TIMEOUT;
elmot 1:d0dfbce63a89 1632 break;
elmot 1:d0dfbce63a89 1633 }
elmot 1:d0dfbce63a89 1634 }
elmot 1:d0dfbce63a89 1635 }
elmot 1:d0dfbce63a89 1636
elmot 1:d0dfbce63a89 1637 return status;
elmot 1:d0dfbce63a89 1638 }
elmot 1:d0dfbce63a89 1639
elmot 1:d0dfbce63a89 1640 /**
elmot 1:d0dfbce63a89 1641 * @brief Disable PLLSAI1.
elmot 1:d0dfbce63a89 1642 * @retval HAL status
elmot 1:d0dfbce63a89 1643 */
elmot 1:d0dfbce63a89 1644 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void)
elmot 1:d0dfbce63a89 1645 {
elmot 1:d0dfbce63a89 1646 uint32_t tickstart = 0U;
elmot 1:d0dfbce63a89 1647 HAL_StatusTypeDef status = HAL_OK;
elmot 1:d0dfbce63a89 1648
elmot 1:d0dfbce63a89 1649 /* Disable the PLLSAI1 */
elmot 1:d0dfbce63a89 1650 __HAL_RCC_PLLSAI1_DISABLE();
elmot 1:d0dfbce63a89 1651
elmot 1:d0dfbce63a89 1652 /* Get Start Tick*/
elmot 1:d0dfbce63a89 1653 tickstart = HAL_GetTick();
elmot 1:d0dfbce63a89 1654
elmot 1:d0dfbce63a89 1655 /* Wait till PLLSAI1 is ready */
elmot 1:d0dfbce63a89 1656 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
elmot 1:d0dfbce63a89 1657 {
elmot 1:d0dfbce63a89 1658 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
elmot 1:d0dfbce63a89 1659 {
elmot 1:d0dfbce63a89 1660 status = HAL_TIMEOUT;
elmot 1:d0dfbce63a89 1661 break;
elmot 1:d0dfbce63a89 1662 }
elmot 1:d0dfbce63a89 1663 }
elmot 1:d0dfbce63a89 1664
elmot 1:d0dfbce63a89 1665 /* Disable the PLLSAI1 Clock outputs */
elmot 1:d0dfbce63a89 1666 __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN);
elmot 1:d0dfbce63a89 1667
elmot 1:d0dfbce63a89 1668 /* Reset PLL source to save power if no PLLs on */
elmot 1:d0dfbce63a89 1669 if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
elmot 1:d0dfbce63a89 1670 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 1671 &&
elmot 1:d0dfbce63a89 1672 (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
elmot 1:d0dfbce63a89 1673 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 1674 )
elmot 1:d0dfbce63a89 1675 {
elmot 1:d0dfbce63a89 1676 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
elmot 1:d0dfbce63a89 1677 }
elmot 1:d0dfbce63a89 1678
elmot 1:d0dfbce63a89 1679 return status;
elmot 1:d0dfbce63a89 1680 }
elmot 1:d0dfbce63a89 1681
elmot 1:d0dfbce63a89 1682 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 1683
elmot 1:d0dfbce63a89 1684 /**
elmot 1:d0dfbce63a89 1685 * @brief Enable PLLSAI2.
elmot 1:d0dfbce63a89 1686 * @param PLLSAI2Init pointer to an RCC_PLLSAI2InitTypeDef structure that
elmot 1:d0dfbce63a89 1687 * contains the configuration information for the PLLSAI2
elmot 1:d0dfbce63a89 1688 * @retval HAL status
elmot 1:d0dfbce63a89 1689 */
elmot 1:d0dfbce63a89 1690 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init)
elmot 1:d0dfbce63a89 1691 {
elmot 1:d0dfbce63a89 1692 uint32_t tickstart = 0U;
elmot 1:d0dfbce63a89 1693 HAL_StatusTypeDef status = HAL_OK;
elmot 1:d0dfbce63a89 1694
elmot 1:d0dfbce63a89 1695 /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */
elmot 1:d0dfbce63a89 1696 assert_param(IS_RCC_PLLSAI2SOURCE(PLLSAI2Init->PLLSAI2Source));
elmot 1:d0dfbce63a89 1697 assert_param(IS_RCC_PLLSAI2M_VALUE(PLLSAI2Init->PLLSAI2M));
elmot 1:d0dfbce63a89 1698 assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N));
elmot 1:d0dfbce63a89 1699 assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P));
elmot 1:d0dfbce63a89 1700 assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R));
elmot 1:d0dfbce63a89 1701 assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut));
elmot 1:d0dfbce63a89 1702
elmot 1:d0dfbce63a89 1703 /* Disable the PLLSAI2 */
elmot 1:d0dfbce63a89 1704 __HAL_RCC_PLLSAI2_DISABLE();
elmot 1:d0dfbce63a89 1705
elmot 1:d0dfbce63a89 1706 /* Get Start Tick*/
elmot 1:d0dfbce63a89 1707 tickstart = HAL_GetTick();
elmot 1:d0dfbce63a89 1708
elmot 1:d0dfbce63a89 1709 /* Wait till PLLSAI2 is ready to be updated */
elmot 1:d0dfbce63a89 1710 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET)
elmot 1:d0dfbce63a89 1711 {
elmot 1:d0dfbce63a89 1712 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
elmot 1:d0dfbce63a89 1713 {
elmot 1:d0dfbce63a89 1714 status = HAL_TIMEOUT;
elmot 1:d0dfbce63a89 1715 break;
elmot 1:d0dfbce63a89 1716 }
elmot 1:d0dfbce63a89 1717 }
elmot 1:d0dfbce63a89 1718
elmot 1:d0dfbce63a89 1719 if(status == HAL_OK)
elmot 1:d0dfbce63a89 1720 {
elmot 1:d0dfbce63a89 1721 /* Configure the PLLSAI2 Multiplication factor N */
elmot 1:d0dfbce63a89 1722 /* Configure the PLLSAI2 Division factors P and R */
elmot 1:d0dfbce63a89 1723 __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R);
elmot 1:d0dfbce63a89 1724 /* Configure the PLLSAI2 Clock output(s) */
elmot 1:d0dfbce63a89 1725 __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut);
elmot 1:d0dfbce63a89 1726
elmot 1:d0dfbce63a89 1727 /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
elmot 1:d0dfbce63a89 1728 __HAL_RCC_PLLSAI2_ENABLE();
elmot 1:d0dfbce63a89 1729
elmot 1:d0dfbce63a89 1730 /* Get Start Tick*/
elmot 1:d0dfbce63a89 1731 tickstart = HAL_GetTick();
elmot 1:d0dfbce63a89 1732
elmot 1:d0dfbce63a89 1733 /* Wait till PLLSAI2 is ready */
elmot 1:d0dfbce63a89 1734 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
elmot 1:d0dfbce63a89 1735 {
elmot 1:d0dfbce63a89 1736 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
elmot 1:d0dfbce63a89 1737 {
elmot 1:d0dfbce63a89 1738 status = HAL_TIMEOUT;
elmot 1:d0dfbce63a89 1739 break;
elmot 1:d0dfbce63a89 1740 }
elmot 1:d0dfbce63a89 1741 }
elmot 1:d0dfbce63a89 1742 }
elmot 1:d0dfbce63a89 1743
elmot 1:d0dfbce63a89 1744 return status;
elmot 1:d0dfbce63a89 1745 }
elmot 1:d0dfbce63a89 1746
elmot 1:d0dfbce63a89 1747 /**
elmot 1:d0dfbce63a89 1748 * @brief Disable PLLISAI2.
elmot 1:d0dfbce63a89 1749 * @retval HAL status
elmot 1:d0dfbce63a89 1750 */
elmot 1:d0dfbce63a89 1751 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void)
elmot 1:d0dfbce63a89 1752 {
elmot 1:d0dfbce63a89 1753 uint32_t tickstart = 0U;
elmot 1:d0dfbce63a89 1754 HAL_StatusTypeDef status = HAL_OK;
elmot 1:d0dfbce63a89 1755
elmot 1:d0dfbce63a89 1756 /* Disable the PLLSAI2 */
elmot 1:d0dfbce63a89 1757 __HAL_RCC_PLLSAI2_DISABLE();
elmot 1:d0dfbce63a89 1758
elmot 1:d0dfbce63a89 1759 /* Get Start Tick*/
elmot 1:d0dfbce63a89 1760 tickstart = HAL_GetTick();
elmot 1:d0dfbce63a89 1761
elmot 1:d0dfbce63a89 1762 /* Wait till PLLSAI2 is ready */
elmot 1:d0dfbce63a89 1763 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET)
elmot 1:d0dfbce63a89 1764 {
elmot 1:d0dfbce63a89 1765 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
elmot 1:d0dfbce63a89 1766 {
elmot 1:d0dfbce63a89 1767 status = HAL_TIMEOUT;
elmot 1:d0dfbce63a89 1768 break;
elmot 1:d0dfbce63a89 1769 }
elmot 1:d0dfbce63a89 1770 }
elmot 1:d0dfbce63a89 1771
elmot 1:d0dfbce63a89 1772 /* Disable the PLLSAI2 Clock outputs */
elmot 1:d0dfbce63a89 1773 __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2REN);
elmot 1:d0dfbce63a89 1774
elmot 1:d0dfbce63a89 1775 /* Reset PLL source to save power if no PLLs on */
elmot 1:d0dfbce63a89 1776 if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
elmot 1:d0dfbce63a89 1777 &&
elmot 1:d0dfbce63a89 1778 (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
elmot 1:d0dfbce63a89 1779 )
elmot 1:d0dfbce63a89 1780 {
elmot 1:d0dfbce63a89 1781 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
elmot 1:d0dfbce63a89 1782 }
elmot 1:d0dfbce63a89 1783
elmot 1:d0dfbce63a89 1784 return status;
elmot 1:d0dfbce63a89 1785 }
elmot 1:d0dfbce63a89 1786
elmot 1:d0dfbce63a89 1787 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 1788
elmot 1:d0dfbce63a89 1789 /**
elmot 1:d0dfbce63a89 1790 * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
elmot 1:d0dfbce63a89 1791 * @param WakeUpClk Wakeup clock
elmot 1:d0dfbce63a89 1792 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1793 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection
elmot 1:d0dfbce63a89 1794 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection
elmot 1:d0dfbce63a89 1795 * @note This function shall not be called after the Clock Security System on HSE has been
elmot 1:d0dfbce63a89 1796 * enabled.
elmot 1:d0dfbce63a89 1797 * @retval None
elmot 1:d0dfbce63a89 1798 */
elmot 1:d0dfbce63a89 1799 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
elmot 1:d0dfbce63a89 1800 {
elmot 1:d0dfbce63a89 1801 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
elmot 1:d0dfbce63a89 1802
elmot 1:d0dfbce63a89 1803 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
elmot 1:d0dfbce63a89 1804 }
elmot 1:d0dfbce63a89 1805
elmot 1:d0dfbce63a89 1806 /**
elmot 1:d0dfbce63a89 1807 * @brief Configure the MSI range after standby mode.
elmot 1:d0dfbce63a89 1808 * @note After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
elmot 1:d0dfbce63a89 1809 * @param MSIRange MSI range
elmot 1:d0dfbce63a89 1810 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1811 * @arg @ref RCC_MSIRANGE_4 Range 4 around 1 MHz
elmot 1:d0dfbce63a89 1812 * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz
elmot 1:d0dfbce63a89 1813 * @arg @ref RCC_MSIRANGE_6 Range 6 around 4 MHz (reset value)
elmot 1:d0dfbce63a89 1814 * @arg @ref RCC_MSIRANGE_7 Range 7 around 8 MHz
elmot 1:d0dfbce63a89 1815 * @retval None
elmot 1:d0dfbce63a89 1816 */
elmot 1:d0dfbce63a89 1817 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)
elmot 1:d0dfbce63a89 1818 {
elmot 1:d0dfbce63a89 1819 assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange));
elmot 1:d0dfbce63a89 1820
elmot 1:d0dfbce63a89 1821 __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange);
elmot 1:d0dfbce63a89 1822 }
elmot 1:d0dfbce63a89 1823
elmot 1:d0dfbce63a89 1824 /**
elmot 1:d0dfbce63a89 1825 * @brief Enable the LSE Clock Security System.
elmot 1:d0dfbce63a89 1826 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
elmot 1:d0dfbce63a89 1827 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
elmot 1:d0dfbce63a89 1828 * clock with HAL_RCCEx_PeriphCLKConfig().
elmot 1:d0dfbce63a89 1829 * @retval None
elmot 1:d0dfbce63a89 1830 */
elmot 1:d0dfbce63a89 1831 void HAL_RCCEx_EnableLSECSS(void)
elmot 1:d0dfbce63a89 1832 {
elmot 1:d0dfbce63a89 1833 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
elmot 1:d0dfbce63a89 1834 }
elmot 1:d0dfbce63a89 1835
elmot 1:d0dfbce63a89 1836 /**
elmot 1:d0dfbce63a89 1837 * @brief Disable the LSE Clock Security System.
elmot 1:d0dfbce63a89 1838 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
elmot 1:d0dfbce63a89 1839 * @retval None
elmot 1:d0dfbce63a89 1840 */
elmot 1:d0dfbce63a89 1841 void HAL_RCCEx_DisableLSECSS(void)
elmot 1:d0dfbce63a89 1842 {
elmot 1:d0dfbce63a89 1843 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
elmot 1:d0dfbce63a89 1844
elmot 1:d0dfbce63a89 1845 /* Disable LSE CSS IT if any */
elmot 1:d0dfbce63a89 1846 __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
elmot 1:d0dfbce63a89 1847 }
elmot 1:d0dfbce63a89 1848
elmot 1:d0dfbce63a89 1849 /**
elmot 1:d0dfbce63a89 1850 * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
elmot 1:d0dfbce63a89 1851 * @note LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
elmot 1:d0dfbce63a89 1852 * @retval None
elmot 1:d0dfbce63a89 1853 */
elmot 1:d0dfbce63a89 1854 void HAL_RCCEx_EnableLSECSS_IT(void)
elmot 1:d0dfbce63a89 1855 {
elmot 1:d0dfbce63a89 1856 /* Enable LSE CSS */
elmot 1:d0dfbce63a89 1857 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
elmot 1:d0dfbce63a89 1858
elmot 1:d0dfbce63a89 1859 /* Enable LSE CSS IT */
elmot 1:d0dfbce63a89 1860 __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
elmot 1:d0dfbce63a89 1861
elmot 1:d0dfbce63a89 1862 /* Enable IT on EXTI Line 19 */
elmot 1:d0dfbce63a89 1863 __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
elmot 1:d0dfbce63a89 1864 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
elmot 1:d0dfbce63a89 1865 }
elmot 1:d0dfbce63a89 1866
elmot 1:d0dfbce63a89 1867 /**
elmot 1:d0dfbce63a89 1868 * @brief Handle the RCC LSE Clock Security System interrupt request.
elmot 1:d0dfbce63a89 1869 * @retval None
elmot 1:d0dfbce63a89 1870 */
elmot 1:d0dfbce63a89 1871 void HAL_RCCEx_LSECSS_IRQHandler(void)
elmot 1:d0dfbce63a89 1872 {
elmot 1:d0dfbce63a89 1873 /* Check RCC LSE CSSF flag */
elmot 1:d0dfbce63a89 1874 if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
elmot 1:d0dfbce63a89 1875 {
elmot 1:d0dfbce63a89 1876 /* RCC LSE Clock Security System interrupt user callback */
elmot 1:d0dfbce63a89 1877 HAL_RCCEx_LSECSS_Callback();
elmot 1:d0dfbce63a89 1878
elmot 1:d0dfbce63a89 1879 /* Clear RCC LSE CSS pending bit */
elmot 1:d0dfbce63a89 1880 __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
elmot 1:d0dfbce63a89 1881 }
elmot 1:d0dfbce63a89 1882 }
elmot 1:d0dfbce63a89 1883
elmot 1:d0dfbce63a89 1884 /**
elmot 1:d0dfbce63a89 1885 * @brief RCCEx LSE Clock Security System interrupt callback.
elmot 1:d0dfbce63a89 1886 * @retval none
elmot 1:d0dfbce63a89 1887 */
elmot 1:d0dfbce63a89 1888 __weak void HAL_RCCEx_LSECSS_Callback(void)
elmot 1:d0dfbce63a89 1889 {
elmot 1:d0dfbce63a89 1890 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 1891 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
elmot 1:d0dfbce63a89 1892 */
elmot 1:d0dfbce63a89 1893 }
elmot 1:d0dfbce63a89 1894
elmot 1:d0dfbce63a89 1895 /**
elmot 1:d0dfbce63a89 1896 * @brief Select the Low Speed clock source to output on LSCO pin (PA2).
elmot 1:d0dfbce63a89 1897 * @param LSCOSource specifies the Low Speed clock source to output.
elmot 1:d0dfbce63a89 1898 * This parameter can be one of the following values:
elmot 1:d0dfbce63a89 1899 * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
elmot 1:d0dfbce63a89 1900 * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
elmot 1:d0dfbce63a89 1901 * @retval None
elmot 1:d0dfbce63a89 1902 */
elmot 1:d0dfbce63a89 1903 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
elmot 1:d0dfbce63a89 1904 {
elmot 1:d0dfbce63a89 1905 GPIO_InitTypeDef GPIO_InitStruct;
elmot 1:d0dfbce63a89 1906 FlagStatus pwrclkchanged = RESET;
elmot 1:d0dfbce63a89 1907 FlagStatus backupchanged = RESET;
elmot 1:d0dfbce63a89 1908
elmot 1:d0dfbce63a89 1909 /* Check the parameters */
elmot 1:d0dfbce63a89 1910 assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
elmot 1:d0dfbce63a89 1911
elmot 1:d0dfbce63a89 1912 /* LSCO Pin Clock Enable */
elmot 1:d0dfbce63a89 1913 __LSCO_CLK_ENABLE();
elmot 1:d0dfbce63a89 1914
elmot 1:d0dfbce63a89 1915 /* Configue the LSCO pin in analog mode */
elmot 1:d0dfbce63a89 1916 GPIO_InitStruct.Pin = LSCO_PIN;
elmot 1:d0dfbce63a89 1917 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
elmot 1:d0dfbce63a89 1918 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
elmot 1:d0dfbce63a89 1919 GPIO_InitStruct.Pull = GPIO_NOPULL;
elmot 1:d0dfbce63a89 1920 HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
elmot 1:d0dfbce63a89 1921
elmot 1:d0dfbce63a89 1922 /* Update LSCOSEL clock source in Backup Domain control register */
elmot 1:d0dfbce63a89 1923 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
elmot 1:d0dfbce63a89 1924 {
elmot 1:d0dfbce63a89 1925 __HAL_RCC_PWR_CLK_ENABLE();
elmot 1:d0dfbce63a89 1926 pwrclkchanged = SET;
elmot 1:d0dfbce63a89 1927 }
elmot 1:d0dfbce63a89 1928 if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
elmot 1:d0dfbce63a89 1929 {
elmot 1:d0dfbce63a89 1930 HAL_PWR_EnableBkUpAccess();
elmot 1:d0dfbce63a89 1931 backupchanged = SET;
elmot 1:d0dfbce63a89 1932 }
elmot 1:d0dfbce63a89 1933
elmot 1:d0dfbce63a89 1934 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
elmot 1:d0dfbce63a89 1935
elmot 1:d0dfbce63a89 1936 if(backupchanged == SET)
elmot 1:d0dfbce63a89 1937 {
elmot 1:d0dfbce63a89 1938 HAL_PWR_DisableBkUpAccess();
elmot 1:d0dfbce63a89 1939 }
elmot 1:d0dfbce63a89 1940 if(pwrclkchanged == SET)
elmot 1:d0dfbce63a89 1941 {
elmot 1:d0dfbce63a89 1942 __HAL_RCC_PWR_CLK_DISABLE();
elmot 1:d0dfbce63a89 1943 }
elmot 1:d0dfbce63a89 1944 }
elmot 1:d0dfbce63a89 1945
elmot 1:d0dfbce63a89 1946 /**
elmot 1:d0dfbce63a89 1947 * @brief Disable the Low Speed clock output.
elmot 1:d0dfbce63a89 1948 * @retval None
elmot 1:d0dfbce63a89 1949 */
elmot 1:d0dfbce63a89 1950 void HAL_RCCEx_DisableLSCO(void)
elmot 1:d0dfbce63a89 1951 {
elmot 1:d0dfbce63a89 1952 FlagStatus pwrclkchanged = RESET;
elmot 1:d0dfbce63a89 1953 FlagStatus backupchanged = RESET;
elmot 1:d0dfbce63a89 1954
elmot 1:d0dfbce63a89 1955 /* Update LSCOEN bit in Backup Domain control register */
elmot 1:d0dfbce63a89 1956 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
elmot 1:d0dfbce63a89 1957 {
elmot 1:d0dfbce63a89 1958 __HAL_RCC_PWR_CLK_ENABLE();
elmot 1:d0dfbce63a89 1959 pwrclkchanged = SET;
elmot 1:d0dfbce63a89 1960 }
elmot 1:d0dfbce63a89 1961 if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
elmot 1:d0dfbce63a89 1962 {
elmot 1:d0dfbce63a89 1963 /* Enable access to the backup domain */
elmot 1:d0dfbce63a89 1964 HAL_PWR_EnableBkUpAccess();
elmot 1:d0dfbce63a89 1965 backupchanged = SET;
elmot 1:d0dfbce63a89 1966 }
elmot 1:d0dfbce63a89 1967
elmot 1:d0dfbce63a89 1968 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
elmot 1:d0dfbce63a89 1969
elmot 1:d0dfbce63a89 1970 /* Restore previous configuration */
elmot 1:d0dfbce63a89 1971 if(backupchanged == SET)
elmot 1:d0dfbce63a89 1972 {
elmot 1:d0dfbce63a89 1973 /* Disable access to the backup domain */
elmot 1:d0dfbce63a89 1974 HAL_PWR_DisableBkUpAccess();
elmot 1:d0dfbce63a89 1975 }
elmot 1:d0dfbce63a89 1976 if(pwrclkchanged == SET)
elmot 1:d0dfbce63a89 1977 {
elmot 1:d0dfbce63a89 1978 __HAL_RCC_PWR_CLK_DISABLE();
elmot 1:d0dfbce63a89 1979 }
elmot 1:d0dfbce63a89 1980 }
elmot 1:d0dfbce63a89 1981
elmot 1:d0dfbce63a89 1982 /**
elmot 1:d0dfbce63a89 1983 * @brief Enable the PLL-mode of the MSI.
elmot 1:d0dfbce63a89 1984 * @note Prior to enable the PLL-mode of the MSI for automatic hardware
elmot 1:d0dfbce63a89 1985 * calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
elmot 1:d0dfbce63a89 1986 * @retval None
elmot 1:d0dfbce63a89 1987 */
elmot 1:d0dfbce63a89 1988 void HAL_RCCEx_EnableMSIPLLMode(void)
elmot 1:d0dfbce63a89 1989 {
elmot 1:d0dfbce63a89 1990 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
elmot 1:d0dfbce63a89 1991 }
elmot 1:d0dfbce63a89 1992
elmot 1:d0dfbce63a89 1993 /**
elmot 1:d0dfbce63a89 1994 * @brief Disable the PLL-mode of the MSI.
elmot 1:d0dfbce63a89 1995 * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
elmot 1:d0dfbce63a89 1996 * @retval None
elmot 1:d0dfbce63a89 1997 */
elmot 1:d0dfbce63a89 1998 void HAL_RCCEx_DisableMSIPLLMode(void)
elmot 1:d0dfbce63a89 1999 {
elmot 1:d0dfbce63a89 2000 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
elmot 1:d0dfbce63a89 2001 }
elmot 1:d0dfbce63a89 2002
elmot 1:d0dfbce63a89 2003 /**
elmot 1:d0dfbce63a89 2004 * @}
elmot 1:d0dfbce63a89 2005 */
elmot 1:d0dfbce63a89 2006
elmot 1:d0dfbce63a89 2007 #if defined(CRS)
elmot 1:d0dfbce63a89 2008
elmot 1:d0dfbce63a89 2009 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
elmot 1:d0dfbce63a89 2010 * @brief Extended Clock Recovery System Control functions
elmot 1:d0dfbce63a89 2011 *
elmot 1:d0dfbce63a89 2012 @verbatim
elmot 1:d0dfbce63a89 2013 ===============================================================================
elmot 1:d0dfbce63a89 2014 ##### Extended Clock Recovery System Control functions #####
elmot 1:d0dfbce63a89 2015 ===============================================================================
elmot 1:d0dfbce63a89 2016 [..]
elmot 1:d0dfbce63a89 2017 For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:
elmot 1:d0dfbce63a89 2018
elmot 1:d0dfbce63a89 2019 (#) In System clock config, HSI48 needs to be enabled
elmot 1:d0dfbce63a89 2020
elmot 1:d0dfbce63a89 2021 (#) Enable CRS clock in IP MSP init which will use CRS functions
elmot 1:d0dfbce63a89 2022
elmot 1:d0dfbce63a89 2023 (#) Call CRS functions as follows:
elmot 1:d0dfbce63a89 2024 (##) Prepare synchronization configuration necessary for HSI48 calibration
elmot 1:d0dfbce63a89 2025 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
elmot 1:d0dfbce63a89 2026 and also HSI48 oscillator smooth trimming.
elmot 1:d0dfbce63a89 2027 (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
elmot 1:d0dfbce63a89 2028 directly reload value with target and sychronization frequencies values
elmot 1:d0dfbce63a89 2029 (##) Call function HAL_RCCEx_CRSConfig which
elmot 1:d0dfbce63a89 2030 (+++) Resets CRS registers to their default values.
elmot 1:d0dfbce63a89 2031 (+++) Configures CRS registers with synchronization configuration
elmot 1:d0dfbce63a89 2032 (+++) Enables automatic calibration and frequency error counter feature
elmot 1:d0dfbce63a89 2033 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
elmot 1:d0dfbce63a89 2034 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
elmot 1:d0dfbce63a89 2035 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
elmot 1:d0dfbce63a89 2036 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
elmot 1:d0dfbce63a89 2037 should be used as SYNC signal.
elmot 1:d0dfbce63a89 2038
elmot 1:d0dfbce63a89 2039 (##) A polling function is provided to wait for complete synchronization
elmot 1:d0dfbce63a89 2040 (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
elmot 1:d0dfbce63a89 2041 (+++) According to CRS status, user can decide to adjust again the calibration or continue
elmot 1:d0dfbce63a89 2042 application if synchronization is OK
elmot 1:d0dfbce63a89 2043
elmot 1:d0dfbce63a89 2044 (#) User can retrieve information related to synchronization in calling function
elmot 1:d0dfbce63a89 2045 HAL_RCCEx_CRSGetSynchronizationInfo()
elmot 1:d0dfbce63a89 2046
elmot 1:d0dfbce63a89 2047 (#) Regarding synchronization status and synchronization information, user can try a new calibration
elmot 1:d0dfbce63a89 2048 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
elmot 1:d0dfbce63a89 2049 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
elmot 1:d0dfbce63a89 2050 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
elmot 1:d0dfbce63a89 2051 incremented), while when it is detected during the upcounting phase it means that the actual frequency
elmot 1:d0dfbce63a89 2052 is higher (and that the TRIM value should be decremented).
elmot 1:d0dfbce63a89 2053
elmot 1:d0dfbce63a89 2054 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
elmot 1:d0dfbce63a89 2055 through CRS Handler (CRS_IRQn/CRS_IRQHandler)
elmot 1:d0dfbce63a89 2056 (++) Call function HAL_RCCEx_CRSConfig()
elmot 1:d0dfbce63a89 2057 (++) Enable CRS_IRQn (thanks to NVIC functions)
elmot 1:d0dfbce63a89 2058 (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
elmot 1:d0dfbce63a89 2059 (++) Implement CRS status management in the following user callbacks called from
elmot 1:d0dfbce63a89 2060 HAL_RCCEx_CRS_IRQHandler():
elmot 1:d0dfbce63a89 2061 (+++) HAL_RCCEx_CRS_SyncOkCallback()
elmot 1:d0dfbce63a89 2062 (+++) HAL_RCCEx_CRS_SyncWarnCallback()
elmot 1:d0dfbce63a89 2063 (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
elmot 1:d0dfbce63a89 2064 (+++) HAL_RCCEx_CRS_ErrorCallback()
elmot 1:d0dfbce63a89 2065
elmot 1:d0dfbce63a89 2066 (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
elmot 1:d0dfbce63a89 2067 This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
elmot 1:d0dfbce63a89 2068
elmot 1:d0dfbce63a89 2069 @endverbatim
elmot 1:d0dfbce63a89 2070 * @{
elmot 1:d0dfbce63a89 2071 */
elmot 1:d0dfbce63a89 2072
elmot 1:d0dfbce63a89 2073 /**
elmot 1:d0dfbce63a89 2074 * @brief Start automatic synchronization for polling mode
elmot 1:d0dfbce63a89 2075 * @param pInit Pointer on RCC_CRSInitTypeDef structure
elmot 1:d0dfbce63a89 2076 * @retval None
elmot 1:d0dfbce63a89 2077 */
elmot 1:d0dfbce63a89 2078 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
elmot 1:d0dfbce63a89 2079 {
elmot 1:d0dfbce63a89 2080 uint32_t value = 0;
elmot 1:d0dfbce63a89 2081
elmot 1:d0dfbce63a89 2082 /* Check the parameters */
elmot 1:d0dfbce63a89 2083 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
elmot 1:d0dfbce63a89 2084 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
elmot 1:d0dfbce63a89 2085 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
elmot 1:d0dfbce63a89 2086 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
elmot 1:d0dfbce63a89 2087 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
elmot 1:d0dfbce63a89 2088 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
elmot 1:d0dfbce63a89 2089
elmot 1:d0dfbce63a89 2090 /* CONFIGURATION */
elmot 1:d0dfbce63a89 2091
elmot 1:d0dfbce63a89 2092 /* Before configuration, reset CRS registers to their default values*/
elmot 1:d0dfbce63a89 2093 __HAL_RCC_CRS_FORCE_RESET();
elmot 1:d0dfbce63a89 2094 __HAL_RCC_CRS_RELEASE_RESET();
elmot 1:d0dfbce63a89 2095
elmot 1:d0dfbce63a89 2096 /* Set the SYNCDIV[2:0] bits according to Prescaler value */
elmot 1:d0dfbce63a89 2097 /* Set the SYNCSRC[1:0] bits according to Source value */
elmot 1:d0dfbce63a89 2098 /* Set the SYNCSPOL bit according to Polarity value */
elmot 1:d0dfbce63a89 2099 value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
elmot 1:d0dfbce63a89 2100 /* Set the RELOAD[15:0] bits according to ReloadValue value */
elmot 1:d0dfbce63a89 2101 value |= pInit->ReloadValue;
elmot 1:d0dfbce63a89 2102 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
elmot 1:d0dfbce63a89 2103 value |= (pInit->ErrorLimitValue << POSITION_VAL(CRS_CFGR_FELIM));
elmot 1:d0dfbce63a89 2104 WRITE_REG(CRS->CFGR, value);
elmot 1:d0dfbce63a89 2105
elmot 1:d0dfbce63a89 2106 /* Adjust HSI48 oscillator smooth trimming */
elmot 1:d0dfbce63a89 2107 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
elmot 1:d0dfbce63a89 2108 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << POSITION_VAL(CRS_CR_TRIM)));
elmot 1:d0dfbce63a89 2109
elmot 1:d0dfbce63a89 2110 /* START AUTOMATIC SYNCHRONIZATION*/
elmot 1:d0dfbce63a89 2111
elmot 1:d0dfbce63a89 2112 /* Enable Automatic trimming & Frequency error counter */
elmot 1:d0dfbce63a89 2113 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
elmot 1:d0dfbce63a89 2114 }
elmot 1:d0dfbce63a89 2115
elmot 1:d0dfbce63a89 2116 /**
elmot 1:d0dfbce63a89 2117 * @brief Generate the software synchronization event
elmot 1:d0dfbce63a89 2118 * @retval None
elmot 1:d0dfbce63a89 2119 */
elmot 1:d0dfbce63a89 2120 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
elmot 1:d0dfbce63a89 2121 {
elmot 1:d0dfbce63a89 2122 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
elmot 1:d0dfbce63a89 2123 }
elmot 1:d0dfbce63a89 2124
elmot 1:d0dfbce63a89 2125 /**
elmot 1:d0dfbce63a89 2126 * @brief Return synchronization info
elmot 1:d0dfbce63a89 2127 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
elmot 1:d0dfbce63a89 2128 * @retval None
elmot 1:d0dfbce63a89 2129 */
elmot 1:d0dfbce63a89 2130 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
elmot 1:d0dfbce63a89 2131 {
elmot 1:d0dfbce63a89 2132 /* Check the parameter */
elmot 1:d0dfbce63a89 2133 assert_param(pSynchroInfo != NULL);
elmot 1:d0dfbce63a89 2134
elmot 1:d0dfbce63a89 2135 /* Get the reload value */
elmot 1:d0dfbce63a89 2136 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
elmot 1:d0dfbce63a89 2137
elmot 1:d0dfbce63a89 2138 /* Get HSI48 oscillator smooth trimming */
elmot 1:d0dfbce63a89 2139 pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> POSITION_VAL(CRS_CR_TRIM));
elmot 1:d0dfbce63a89 2140
elmot 1:d0dfbce63a89 2141 /* Get Frequency error capture */
elmot 1:d0dfbce63a89 2142 pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> POSITION_VAL(CRS_ISR_FECAP));
elmot 1:d0dfbce63a89 2143
elmot 1:d0dfbce63a89 2144 /* Get Frequency error direction */
elmot 1:d0dfbce63a89 2145 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
elmot 1:d0dfbce63a89 2146 }
elmot 1:d0dfbce63a89 2147
elmot 1:d0dfbce63a89 2148 /**
elmot 1:d0dfbce63a89 2149 * @brief Wait for CRS Synchronization status.
elmot 1:d0dfbce63a89 2150 * @param Timeout Duration of the timeout
elmot 1:d0dfbce63a89 2151 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
elmot 1:d0dfbce63a89 2152 * frequency.
elmot 1:d0dfbce63a89 2153 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
elmot 1:d0dfbce63a89 2154 * @retval Combination of Synchronization status
elmot 1:d0dfbce63a89 2155 * This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 2156 * @arg @ref RCC_CRS_TIMEOUT
elmot 1:d0dfbce63a89 2157 * @arg @ref RCC_CRS_SYNCOK
elmot 1:d0dfbce63a89 2158 * @arg @ref RCC_CRS_SYNCWARN
elmot 1:d0dfbce63a89 2159 * @arg @ref RCC_CRS_SYNCERR
elmot 1:d0dfbce63a89 2160 * @arg @ref RCC_CRS_SYNCMISS
elmot 1:d0dfbce63a89 2161 * @arg @ref RCC_CRS_TRIMOVF
elmot 1:d0dfbce63a89 2162 */
elmot 1:d0dfbce63a89 2163 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
elmot 1:d0dfbce63a89 2164 {
elmot 1:d0dfbce63a89 2165 uint32_t crsstatus = RCC_CRS_NONE;
elmot 1:d0dfbce63a89 2166 uint32_t tickstart = 0U;
elmot 1:d0dfbce63a89 2167
elmot 1:d0dfbce63a89 2168 /* Get timeout */
elmot 1:d0dfbce63a89 2169 tickstart = HAL_GetTick();
elmot 1:d0dfbce63a89 2170
elmot 1:d0dfbce63a89 2171 /* Wait for CRS flag or timeout detection */
elmot 1:d0dfbce63a89 2172 do
elmot 1:d0dfbce63a89 2173 {
elmot 1:d0dfbce63a89 2174 if(Timeout != HAL_MAX_DELAY)
elmot 1:d0dfbce63a89 2175 {
elmot 1:d0dfbce63a89 2176 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
elmot 1:d0dfbce63a89 2177 {
elmot 1:d0dfbce63a89 2178 crsstatus = RCC_CRS_TIMEOUT;
elmot 1:d0dfbce63a89 2179 }
elmot 1:d0dfbce63a89 2180 }
elmot 1:d0dfbce63a89 2181 /* Check CRS SYNCOK flag */
elmot 1:d0dfbce63a89 2182 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
elmot 1:d0dfbce63a89 2183 {
elmot 1:d0dfbce63a89 2184 /* CRS SYNC event OK */
elmot 1:d0dfbce63a89 2185 crsstatus |= RCC_CRS_SYNCOK;
elmot 1:d0dfbce63a89 2186
elmot 1:d0dfbce63a89 2187 /* Clear CRS SYNC event OK bit */
elmot 1:d0dfbce63a89 2188 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
elmot 1:d0dfbce63a89 2189 }
elmot 1:d0dfbce63a89 2190
elmot 1:d0dfbce63a89 2191 /* Check CRS SYNCWARN flag */
elmot 1:d0dfbce63a89 2192 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
elmot 1:d0dfbce63a89 2193 {
elmot 1:d0dfbce63a89 2194 /* CRS SYNC warning */
elmot 1:d0dfbce63a89 2195 crsstatus |= RCC_CRS_SYNCWARN;
elmot 1:d0dfbce63a89 2196
elmot 1:d0dfbce63a89 2197 /* Clear CRS SYNCWARN bit */
elmot 1:d0dfbce63a89 2198 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
elmot 1:d0dfbce63a89 2199 }
elmot 1:d0dfbce63a89 2200
elmot 1:d0dfbce63a89 2201 /* Check CRS TRIM overflow flag */
elmot 1:d0dfbce63a89 2202 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
elmot 1:d0dfbce63a89 2203 {
elmot 1:d0dfbce63a89 2204 /* CRS SYNC Error */
elmot 1:d0dfbce63a89 2205 crsstatus |= RCC_CRS_TRIMOVF;
elmot 1:d0dfbce63a89 2206
elmot 1:d0dfbce63a89 2207 /* Clear CRS Error bit */
elmot 1:d0dfbce63a89 2208 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
elmot 1:d0dfbce63a89 2209 }
elmot 1:d0dfbce63a89 2210
elmot 1:d0dfbce63a89 2211 /* Check CRS Error flag */
elmot 1:d0dfbce63a89 2212 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
elmot 1:d0dfbce63a89 2213 {
elmot 1:d0dfbce63a89 2214 /* CRS SYNC Error */
elmot 1:d0dfbce63a89 2215 crsstatus |= RCC_CRS_SYNCERR;
elmot 1:d0dfbce63a89 2216
elmot 1:d0dfbce63a89 2217 /* Clear CRS Error bit */
elmot 1:d0dfbce63a89 2218 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
elmot 1:d0dfbce63a89 2219 }
elmot 1:d0dfbce63a89 2220
elmot 1:d0dfbce63a89 2221 /* Check CRS SYNC Missed flag */
elmot 1:d0dfbce63a89 2222 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
elmot 1:d0dfbce63a89 2223 {
elmot 1:d0dfbce63a89 2224 /* CRS SYNC Missed */
elmot 1:d0dfbce63a89 2225 crsstatus |= RCC_CRS_SYNCMISS;
elmot 1:d0dfbce63a89 2226
elmot 1:d0dfbce63a89 2227 /* Clear CRS SYNC Missed bit */
elmot 1:d0dfbce63a89 2228 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
elmot 1:d0dfbce63a89 2229 }
elmot 1:d0dfbce63a89 2230
elmot 1:d0dfbce63a89 2231 /* Check CRS Expected SYNC flag */
elmot 1:d0dfbce63a89 2232 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
elmot 1:d0dfbce63a89 2233 {
elmot 1:d0dfbce63a89 2234 /* frequency error counter reached a zero value */
elmot 1:d0dfbce63a89 2235 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
elmot 1:d0dfbce63a89 2236 }
elmot 1:d0dfbce63a89 2237 } while(RCC_CRS_NONE == crsstatus);
elmot 1:d0dfbce63a89 2238
elmot 1:d0dfbce63a89 2239 return crsstatus;
elmot 1:d0dfbce63a89 2240 }
elmot 1:d0dfbce63a89 2241
elmot 1:d0dfbce63a89 2242 /**
elmot 1:d0dfbce63a89 2243 * @brief Handle the Clock Recovery System interrupt request.
elmot 1:d0dfbce63a89 2244 * @retval None
elmot 1:d0dfbce63a89 2245 */
elmot 1:d0dfbce63a89 2246 void HAL_RCCEx_CRS_IRQHandler(void)
elmot 1:d0dfbce63a89 2247 {
elmot 1:d0dfbce63a89 2248 uint32_t crserror = RCC_CRS_NONE;
elmot 1:d0dfbce63a89 2249 /* Get current IT flags and IT sources values */
elmot 1:d0dfbce63a89 2250 uint32_t itflags = READ_REG(CRS->ISR);
elmot 1:d0dfbce63a89 2251 uint32_t itsources = READ_REG(CRS->CR);
elmot 1:d0dfbce63a89 2252
elmot 1:d0dfbce63a89 2253 /* Check CRS SYNCOK flag */
elmot 1:d0dfbce63a89 2254 if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET))
elmot 1:d0dfbce63a89 2255 {
elmot 1:d0dfbce63a89 2256 /* Clear CRS SYNC event OK flag */
elmot 1:d0dfbce63a89 2257 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
elmot 1:d0dfbce63a89 2258
elmot 1:d0dfbce63a89 2259 /* user callback */
elmot 1:d0dfbce63a89 2260 HAL_RCCEx_CRS_SyncOkCallback();
elmot 1:d0dfbce63a89 2261 }
elmot 1:d0dfbce63a89 2262 /* Check CRS SYNCWARN flag */
elmot 1:d0dfbce63a89 2263 else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET))
elmot 1:d0dfbce63a89 2264 {
elmot 1:d0dfbce63a89 2265 /* Clear CRS SYNCWARN flag */
elmot 1:d0dfbce63a89 2266 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
elmot 1:d0dfbce63a89 2267
elmot 1:d0dfbce63a89 2268 /* user callback */
elmot 1:d0dfbce63a89 2269 HAL_RCCEx_CRS_SyncWarnCallback();
elmot 1:d0dfbce63a89 2270 }
elmot 1:d0dfbce63a89 2271 /* Check CRS Expected SYNC flag */
elmot 1:d0dfbce63a89 2272 else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET))
elmot 1:d0dfbce63a89 2273 {
elmot 1:d0dfbce63a89 2274 /* frequency error counter reached a zero value */
elmot 1:d0dfbce63a89 2275 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
elmot 1:d0dfbce63a89 2276
elmot 1:d0dfbce63a89 2277 /* user callback */
elmot 1:d0dfbce63a89 2278 HAL_RCCEx_CRS_ExpectedSyncCallback();
elmot 1:d0dfbce63a89 2279 }
elmot 1:d0dfbce63a89 2280 /* Check CRS Error flags */
elmot 1:d0dfbce63a89 2281 else
elmot 1:d0dfbce63a89 2282 {
elmot 1:d0dfbce63a89 2283 if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET))
elmot 1:d0dfbce63a89 2284 {
elmot 1:d0dfbce63a89 2285 if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET)
elmot 1:d0dfbce63a89 2286 {
elmot 1:d0dfbce63a89 2287 crserror |= RCC_CRS_SYNCERR;
elmot 1:d0dfbce63a89 2288 }
elmot 1:d0dfbce63a89 2289 if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET)
elmot 1:d0dfbce63a89 2290 {
elmot 1:d0dfbce63a89 2291 crserror |= RCC_CRS_SYNCMISS;
elmot 1:d0dfbce63a89 2292 }
elmot 1:d0dfbce63a89 2293 if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET)
elmot 1:d0dfbce63a89 2294 {
elmot 1:d0dfbce63a89 2295 crserror |= RCC_CRS_TRIMOVF;
elmot 1:d0dfbce63a89 2296 }
elmot 1:d0dfbce63a89 2297
elmot 1:d0dfbce63a89 2298 /* Clear CRS Error flags */
elmot 1:d0dfbce63a89 2299 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
elmot 1:d0dfbce63a89 2300
elmot 1:d0dfbce63a89 2301 /* user error callback */
elmot 1:d0dfbce63a89 2302 HAL_RCCEx_CRS_ErrorCallback(crserror);
elmot 1:d0dfbce63a89 2303 }
elmot 1:d0dfbce63a89 2304 }
elmot 1:d0dfbce63a89 2305 }
elmot 1:d0dfbce63a89 2306
elmot 1:d0dfbce63a89 2307 /**
elmot 1:d0dfbce63a89 2308 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
elmot 1:d0dfbce63a89 2309 * @retval none
elmot 1:d0dfbce63a89 2310 */
elmot 1:d0dfbce63a89 2311 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
elmot 1:d0dfbce63a89 2312 {
elmot 1:d0dfbce63a89 2313 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 2314 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
elmot 1:d0dfbce63a89 2315 */
elmot 1:d0dfbce63a89 2316 }
elmot 1:d0dfbce63a89 2317
elmot 1:d0dfbce63a89 2318 /**
elmot 1:d0dfbce63a89 2319 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
elmot 1:d0dfbce63a89 2320 * @retval none
elmot 1:d0dfbce63a89 2321 */
elmot 1:d0dfbce63a89 2322 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
elmot 1:d0dfbce63a89 2323 {
elmot 1:d0dfbce63a89 2324 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 2325 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
elmot 1:d0dfbce63a89 2326 */
elmot 1:d0dfbce63a89 2327 }
elmot 1:d0dfbce63a89 2328
elmot 1:d0dfbce63a89 2329 /**
elmot 1:d0dfbce63a89 2330 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
elmot 1:d0dfbce63a89 2331 * @retval none
elmot 1:d0dfbce63a89 2332 */
elmot 1:d0dfbce63a89 2333 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
elmot 1:d0dfbce63a89 2334 {
elmot 1:d0dfbce63a89 2335 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 2336 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
elmot 1:d0dfbce63a89 2337 */
elmot 1:d0dfbce63a89 2338 }
elmot 1:d0dfbce63a89 2339
elmot 1:d0dfbce63a89 2340 /**
elmot 1:d0dfbce63a89 2341 * @brief RCCEx Clock Recovery System Error interrupt callback.
elmot 1:d0dfbce63a89 2342 * @param Error Combination of Error status.
elmot 1:d0dfbce63a89 2343 * This parameter can be a combination of the following values:
elmot 1:d0dfbce63a89 2344 * @arg @ref RCC_CRS_SYNCERR
elmot 1:d0dfbce63a89 2345 * @arg @ref RCC_CRS_SYNCMISS
elmot 1:d0dfbce63a89 2346 * @arg @ref RCC_CRS_TRIMOVF
elmot 1:d0dfbce63a89 2347 * @retval none
elmot 1:d0dfbce63a89 2348 */
elmot 1:d0dfbce63a89 2349 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
elmot 1:d0dfbce63a89 2350 {
elmot 1:d0dfbce63a89 2351 /* Prevent unused argument(s) compilation warning */
elmot 1:d0dfbce63a89 2352 UNUSED(Error);
elmot 1:d0dfbce63a89 2353
elmot 1:d0dfbce63a89 2354 /* NOTE : This function should not be modified, when the callback is needed,
elmot 1:d0dfbce63a89 2355 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
elmot 1:d0dfbce63a89 2356 */
elmot 1:d0dfbce63a89 2357 }
elmot 1:d0dfbce63a89 2358
elmot 1:d0dfbce63a89 2359 /**
elmot 1:d0dfbce63a89 2360 * @}
elmot 1:d0dfbce63a89 2361 */
elmot 1:d0dfbce63a89 2362
elmot 1:d0dfbce63a89 2363 #endif /* CRS */
elmot 1:d0dfbce63a89 2364
elmot 1:d0dfbce63a89 2365 /**
elmot 1:d0dfbce63a89 2366 * @}
elmot 1:d0dfbce63a89 2367 */
elmot 1:d0dfbce63a89 2368
elmot 1:d0dfbce63a89 2369 /** @addtogroup RCCEx_Private_Functions
elmot 1:d0dfbce63a89 2370 * @{
elmot 1:d0dfbce63a89 2371 */
elmot 1:d0dfbce63a89 2372
elmot 1:d0dfbce63a89 2373 /**
elmot 1:d0dfbce63a89 2374 * @brief Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s).
elmot 1:d0dfbce63a89 2375 * @param PllSai1 pointer to an RCC_PLLSAI1InitTypeDef structure that
elmot 1:d0dfbce63a89 2376 * contains the configuration parameters N & P & optionally M as well as PLLSAI1 output clock(s)
elmot 1:d0dfbce63a89 2377 * @param Divider divider parameter to be updated
elmot 1:d0dfbce63a89 2378 *
elmot 1:d0dfbce63a89 2379 * @note PLLSAI1 is temporary disable to apply new parameters
elmot 1:d0dfbce63a89 2380 *
elmot 1:d0dfbce63a89 2381 * @retval HAL status
elmot 1:d0dfbce63a89 2382 */
elmot 1:d0dfbce63a89 2383 static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
elmot 1:d0dfbce63a89 2384 {
elmot 1:d0dfbce63a89 2385 uint32_t tickstart = 0U;
elmot 1:d0dfbce63a89 2386 HAL_StatusTypeDef status = HAL_OK;
elmot 1:d0dfbce63a89 2387
elmot 1:d0dfbce63a89 2388 /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
elmot 1:d0dfbce63a89 2389 /* P, Q and R dividers are verified in each specific divider case below */
elmot 1:d0dfbce63a89 2390 assert_param(IS_RCC_PLLSAI1SOURCE(PllSai1->PLLSAI1Source));
elmot 1:d0dfbce63a89 2391 assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
elmot 1:d0dfbce63a89 2392 assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
elmot 1:d0dfbce63a89 2393 assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
elmot 1:d0dfbce63a89 2394
elmot 1:d0dfbce63a89 2395 /* Check that PLLSAI1 clock source and divider M can be applied */
elmot 1:d0dfbce63a89 2396 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
elmot 1:d0dfbce63a89 2397 {
elmot 1:d0dfbce63a89 2398 /* PLL clock source and divider M already set, check that no request for change */
elmot 1:d0dfbce63a89 2399 if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
elmot 1:d0dfbce63a89 2400 ||
elmot 1:d0dfbce63a89 2401 (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
elmot 1:d0dfbce63a89 2402 ||
elmot 1:d0dfbce63a89 2403 (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai1->PLLSAI1M)
elmot 1:d0dfbce63a89 2404 )
elmot 1:d0dfbce63a89 2405 {
elmot 1:d0dfbce63a89 2406 status = HAL_ERROR;
elmot 1:d0dfbce63a89 2407 }
elmot 1:d0dfbce63a89 2408 }
elmot 1:d0dfbce63a89 2409 else
elmot 1:d0dfbce63a89 2410 {
elmot 1:d0dfbce63a89 2411 /* Check PLLSAI1 clock source availability */
elmot 1:d0dfbce63a89 2412 switch(PllSai1->PLLSAI1Source)
elmot 1:d0dfbce63a89 2413 {
elmot 1:d0dfbce63a89 2414 case RCC_PLLSOURCE_MSI:
elmot 1:d0dfbce63a89 2415 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
elmot 1:d0dfbce63a89 2416 {
elmot 1:d0dfbce63a89 2417 status = HAL_ERROR;
elmot 1:d0dfbce63a89 2418 }
elmot 1:d0dfbce63a89 2419 break;
elmot 1:d0dfbce63a89 2420 case RCC_PLLSOURCE_HSI:
elmot 1:d0dfbce63a89 2421 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
elmot 1:d0dfbce63a89 2422 {
elmot 1:d0dfbce63a89 2423 status = HAL_ERROR;
elmot 1:d0dfbce63a89 2424 }
elmot 1:d0dfbce63a89 2425 break;
elmot 1:d0dfbce63a89 2426 case RCC_PLLSOURCE_HSE:
elmot 1:d0dfbce63a89 2427 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
elmot 1:d0dfbce63a89 2428 {
elmot 1:d0dfbce63a89 2429 status = HAL_ERROR;
elmot 1:d0dfbce63a89 2430 }
elmot 1:d0dfbce63a89 2431 break;
elmot 1:d0dfbce63a89 2432 default:
elmot 1:d0dfbce63a89 2433 status = HAL_ERROR;
elmot 1:d0dfbce63a89 2434 break;
elmot 1:d0dfbce63a89 2435 }
elmot 1:d0dfbce63a89 2436
elmot 1:d0dfbce63a89 2437 if(status == HAL_OK)
elmot 1:d0dfbce63a89 2438 {
elmot 1:d0dfbce63a89 2439 /* Set PLLSAI1 clock source and divider M */
elmot 1:d0dfbce63a89 2440 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLM));
elmot 1:d0dfbce63a89 2441 }
elmot 1:d0dfbce63a89 2442 }
elmot 1:d0dfbce63a89 2443
elmot 1:d0dfbce63a89 2444 if(status == HAL_OK)
elmot 1:d0dfbce63a89 2445 {
elmot 1:d0dfbce63a89 2446 /* Disable the PLLSAI1 */
elmot 1:d0dfbce63a89 2447 __HAL_RCC_PLLSAI1_DISABLE();
elmot 1:d0dfbce63a89 2448
elmot 1:d0dfbce63a89 2449 /* Get Start Tick*/
elmot 1:d0dfbce63a89 2450 tickstart = HAL_GetTick();
elmot 1:d0dfbce63a89 2451
elmot 1:d0dfbce63a89 2452 /* Wait till PLLSAI1 is ready to be updated */
elmot 1:d0dfbce63a89 2453 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
elmot 1:d0dfbce63a89 2454 {
elmot 1:d0dfbce63a89 2455 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
elmot 1:d0dfbce63a89 2456 {
elmot 1:d0dfbce63a89 2457 status = HAL_TIMEOUT;
elmot 1:d0dfbce63a89 2458 break;
elmot 1:d0dfbce63a89 2459 }
elmot 1:d0dfbce63a89 2460 }
elmot 1:d0dfbce63a89 2461
elmot 1:d0dfbce63a89 2462 if(status == HAL_OK)
elmot 1:d0dfbce63a89 2463 {
elmot 1:d0dfbce63a89 2464 if(Divider == DIVIDER_P_UPDATE)
elmot 1:d0dfbce63a89 2465 {
elmot 1:d0dfbce63a89 2466 assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P));
elmot 1:d0dfbce63a89 2467 /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/
elmot 1:d0dfbce63a89 2468 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 2469 MODIFY_REG(RCC->PLLSAI1CFGR,
elmot 1:d0dfbce63a89 2470 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
elmot 1:d0dfbce63a89 2471 (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) |
elmot 1:d0dfbce63a89 2472 (PllSai1->PLLSAI1P << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)));
elmot 1:d0dfbce63a89 2473 #else
elmot 1:d0dfbce63a89 2474 MODIFY_REG(RCC->PLLSAI1CFGR,
elmot 1:d0dfbce63a89 2475 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P,
elmot 1:d0dfbce63a89 2476 (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) |
elmot 1:d0dfbce63a89 2477 ((PllSai1->PLLSAI1P >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)));
elmot 1:d0dfbce63a89 2478 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 2479 }
elmot 1:d0dfbce63a89 2480 else if(Divider == DIVIDER_Q_UPDATE)
elmot 1:d0dfbce63a89 2481 {
elmot 1:d0dfbce63a89 2482 assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q));
elmot 1:d0dfbce63a89 2483 /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
elmot 1:d0dfbce63a89 2484 MODIFY_REG(RCC->PLLSAI1CFGR,
elmot 1:d0dfbce63a89 2485 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
elmot 1:d0dfbce63a89 2486 (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) |
elmot 1:d0dfbce63a89 2487 (((PllSai1->PLLSAI1Q >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)));
elmot 1:d0dfbce63a89 2488 }
elmot 1:d0dfbce63a89 2489 else
elmot 1:d0dfbce63a89 2490 {
elmot 1:d0dfbce63a89 2491 assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R));
elmot 1:d0dfbce63a89 2492 /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
elmot 1:d0dfbce63a89 2493 MODIFY_REG(RCC->PLLSAI1CFGR,
elmot 1:d0dfbce63a89 2494 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
elmot 1:d0dfbce63a89 2495 (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) |
elmot 1:d0dfbce63a89 2496 (((PllSai1->PLLSAI1R >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)));
elmot 1:d0dfbce63a89 2497 }
elmot 1:d0dfbce63a89 2498
elmot 1:d0dfbce63a89 2499 /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
elmot 1:d0dfbce63a89 2500 __HAL_RCC_PLLSAI1_ENABLE();
elmot 1:d0dfbce63a89 2501
elmot 1:d0dfbce63a89 2502 /* Get Start Tick*/
elmot 1:d0dfbce63a89 2503 tickstart = HAL_GetTick();
elmot 1:d0dfbce63a89 2504
elmot 1:d0dfbce63a89 2505 /* Wait till PLLSAI1 is ready */
elmot 1:d0dfbce63a89 2506 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
elmot 1:d0dfbce63a89 2507 {
elmot 1:d0dfbce63a89 2508 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
elmot 1:d0dfbce63a89 2509 {
elmot 1:d0dfbce63a89 2510 status = HAL_TIMEOUT;
elmot 1:d0dfbce63a89 2511 break;
elmot 1:d0dfbce63a89 2512 }
elmot 1:d0dfbce63a89 2513 }
elmot 1:d0dfbce63a89 2514
elmot 1:d0dfbce63a89 2515 if(status == HAL_OK)
elmot 1:d0dfbce63a89 2516 {
elmot 1:d0dfbce63a89 2517 /* Configure the PLLSAI1 Clock output(s) */
elmot 1:d0dfbce63a89 2518 __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
elmot 1:d0dfbce63a89 2519 }
elmot 1:d0dfbce63a89 2520 }
elmot 1:d0dfbce63a89 2521 }
elmot 1:d0dfbce63a89 2522
elmot 1:d0dfbce63a89 2523 return status;
elmot 1:d0dfbce63a89 2524 }
elmot 1:d0dfbce63a89 2525
elmot 1:d0dfbce63a89 2526 #if defined(RCC_PLLSAI2_SUPPORT)
elmot 1:d0dfbce63a89 2527
elmot 1:d0dfbce63a89 2528 /**
elmot 1:d0dfbce63a89 2529 * @brief Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s).
elmot 1:d0dfbce63a89 2530 * @param PllSai2 pointer to an RCC_PLLSAI2InitTypeDef structure that
elmot 1:d0dfbce63a89 2531 * contains the configuration parameters N & P & optionally M as well as PLLSAI2 output clock(s)
elmot 1:d0dfbce63a89 2532 * @param Divider divider parameter to be updated
elmot 1:d0dfbce63a89 2533 *
elmot 1:d0dfbce63a89 2534 * @note PLLSAI2 is temporary disable to apply new parameters
elmot 1:d0dfbce63a89 2535 *
elmot 1:d0dfbce63a89 2536 * @retval HAL status
elmot 1:d0dfbce63a89 2537 */
elmot 1:d0dfbce63a89 2538 static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
elmot 1:d0dfbce63a89 2539 {
elmot 1:d0dfbce63a89 2540 uint32_t tickstart = 0U;
elmot 1:d0dfbce63a89 2541 HAL_StatusTypeDef status = HAL_OK;
elmot 1:d0dfbce63a89 2542
elmot 1:d0dfbce63a89 2543 /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */
elmot 1:d0dfbce63a89 2544 /* P, Q and R dividers are verified in each specific divider case below */
elmot 1:d0dfbce63a89 2545 assert_param(IS_RCC_PLLSAI2SOURCE(PllSai2->PLLSAI2Source));
elmot 1:d0dfbce63a89 2546 assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
elmot 1:d0dfbce63a89 2547 assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
elmot 1:d0dfbce63a89 2548 assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
elmot 1:d0dfbce63a89 2549
elmot 1:d0dfbce63a89 2550 /* Check that PLLSAI2 clock source and divider M can be applied */
elmot 1:d0dfbce63a89 2551 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
elmot 1:d0dfbce63a89 2552 {
elmot 1:d0dfbce63a89 2553 /* PLL clock source and divider M already set, check that no request for change */
elmot 1:d0dfbce63a89 2554 if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
elmot 1:d0dfbce63a89 2555 ||
elmot 1:d0dfbce63a89 2556 (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
elmot 1:d0dfbce63a89 2557 ||
elmot 1:d0dfbce63a89 2558 (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai2->PLLSAI2M)
elmot 1:d0dfbce63a89 2559 )
elmot 1:d0dfbce63a89 2560 {
elmot 1:d0dfbce63a89 2561 status = HAL_ERROR;
elmot 1:d0dfbce63a89 2562 }
elmot 1:d0dfbce63a89 2563 }
elmot 1:d0dfbce63a89 2564 else
elmot 1:d0dfbce63a89 2565 {
elmot 1:d0dfbce63a89 2566 /* Check PLLSAI2 clock source availability */
elmot 1:d0dfbce63a89 2567 switch(PllSai2->PLLSAI2Source)
elmot 1:d0dfbce63a89 2568 {
elmot 1:d0dfbce63a89 2569 case RCC_PLLSOURCE_MSI:
elmot 1:d0dfbce63a89 2570 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
elmot 1:d0dfbce63a89 2571 {
elmot 1:d0dfbce63a89 2572 status = HAL_ERROR;
elmot 1:d0dfbce63a89 2573 }
elmot 1:d0dfbce63a89 2574 break;
elmot 1:d0dfbce63a89 2575 case RCC_PLLSOURCE_HSI:
elmot 1:d0dfbce63a89 2576 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
elmot 1:d0dfbce63a89 2577 {
elmot 1:d0dfbce63a89 2578 status = HAL_ERROR;
elmot 1:d0dfbce63a89 2579 }
elmot 1:d0dfbce63a89 2580 break;
elmot 1:d0dfbce63a89 2581 case RCC_PLLSOURCE_HSE:
elmot 1:d0dfbce63a89 2582 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
elmot 1:d0dfbce63a89 2583 {
elmot 1:d0dfbce63a89 2584 status = HAL_ERROR;
elmot 1:d0dfbce63a89 2585 }
elmot 1:d0dfbce63a89 2586 break;
elmot 1:d0dfbce63a89 2587 default:
elmot 1:d0dfbce63a89 2588 status = HAL_ERROR;
elmot 1:d0dfbce63a89 2589 break;
elmot 1:d0dfbce63a89 2590 }
elmot 1:d0dfbce63a89 2591
elmot 1:d0dfbce63a89 2592 if(status == HAL_OK)
elmot 1:d0dfbce63a89 2593 {
elmot 1:d0dfbce63a89 2594 /* Set PLLSAI2 clock source and divider M */
elmot 1:d0dfbce63a89 2595 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLM));
elmot 1:d0dfbce63a89 2596 }
elmot 1:d0dfbce63a89 2597 }
elmot 1:d0dfbce63a89 2598
elmot 1:d0dfbce63a89 2599 if(status == HAL_OK)
elmot 1:d0dfbce63a89 2600 {
elmot 1:d0dfbce63a89 2601 /* Disable the PLLSAI2 */
elmot 1:d0dfbce63a89 2602 __HAL_RCC_PLLSAI2_DISABLE();
elmot 1:d0dfbce63a89 2603
elmot 1:d0dfbce63a89 2604 /* Get Start Tick*/
elmot 1:d0dfbce63a89 2605 tickstart = HAL_GetTick();
elmot 1:d0dfbce63a89 2606
elmot 1:d0dfbce63a89 2607 /* Wait till PLLSAI2 is ready to be updated */
elmot 1:d0dfbce63a89 2608 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET)
elmot 1:d0dfbce63a89 2609 {
elmot 1:d0dfbce63a89 2610 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
elmot 1:d0dfbce63a89 2611 {
elmot 1:d0dfbce63a89 2612 status = HAL_TIMEOUT;
elmot 1:d0dfbce63a89 2613 break;
elmot 1:d0dfbce63a89 2614 }
elmot 1:d0dfbce63a89 2615 }
elmot 1:d0dfbce63a89 2616
elmot 1:d0dfbce63a89 2617 if(status == HAL_OK)
elmot 1:d0dfbce63a89 2618 {
elmot 1:d0dfbce63a89 2619 if(Divider == DIVIDER_P_UPDATE)
elmot 1:d0dfbce63a89 2620 {
elmot 1:d0dfbce63a89 2621 assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P));
elmot 1:d0dfbce63a89 2622 /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/
elmot 1:d0dfbce63a89 2623 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
elmot 1:d0dfbce63a89 2624 MODIFY_REG(RCC->PLLSAI2CFGR,
elmot 1:d0dfbce63a89 2625 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
elmot 1:d0dfbce63a89 2626 (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) |
elmot 1:d0dfbce63a89 2627 (PllSai2->PLLSAI2P << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV)));
elmot 1:d0dfbce63a89 2628 #else
elmot 1:d0dfbce63a89 2629 MODIFY_REG(RCC->PLLSAI2CFGR,
elmot 1:d0dfbce63a89 2630 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P,
elmot 1:d0dfbce63a89 2631 (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) |
elmot 1:d0dfbce63a89 2632 ((PllSai2->PLLSAI2P >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)));
elmot 1:d0dfbce63a89 2633 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
elmot 1:d0dfbce63a89 2634 }
elmot 1:d0dfbce63a89 2635 else
elmot 1:d0dfbce63a89 2636 {
elmot 1:d0dfbce63a89 2637 assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R));
elmot 1:d0dfbce63a89 2638 /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
elmot 1:d0dfbce63a89 2639 MODIFY_REG(RCC->PLLSAI2CFGR,
elmot 1:d0dfbce63a89 2640 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R,
elmot 1:d0dfbce63a89 2641 (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) |
elmot 1:d0dfbce63a89 2642 (((PllSai2->PLLSAI2R >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)));
elmot 1:d0dfbce63a89 2643 }
elmot 1:d0dfbce63a89 2644
elmot 1:d0dfbce63a89 2645 /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
elmot 1:d0dfbce63a89 2646 __HAL_RCC_PLLSAI2_ENABLE();
elmot 1:d0dfbce63a89 2647
elmot 1:d0dfbce63a89 2648 /* Get Start Tick*/
elmot 1:d0dfbce63a89 2649 tickstart = HAL_GetTick();
elmot 1:d0dfbce63a89 2650
elmot 1:d0dfbce63a89 2651 /* Wait till PLLSAI2 is ready */
elmot 1:d0dfbce63a89 2652 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
elmot 1:d0dfbce63a89 2653 {
elmot 1:d0dfbce63a89 2654 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
elmot 1:d0dfbce63a89 2655 {
elmot 1:d0dfbce63a89 2656 status = HAL_TIMEOUT;
elmot 1:d0dfbce63a89 2657 break;
elmot 1:d0dfbce63a89 2658 }
elmot 1:d0dfbce63a89 2659 }
elmot 1:d0dfbce63a89 2660
elmot 1:d0dfbce63a89 2661 if(status == HAL_OK)
elmot 1:d0dfbce63a89 2662 {
elmot 1:d0dfbce63a89 2663 /* Configure the PLLSAI2 Clock output(s) */
elmot 1:d0dfbce63a89 2664 __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
elmot 1:d0dfbce63a89 2665 }
elmot 1:d0dfbce63a89 2666 }
elmot 1:d0dfbce63a89 2667 }
elmot 1:d0dfbce63a89 2668
elmot 1:d0dfbce63a89 2669 return status;
elmot 1:d0dfbce63a89 2670 }
elmot 1:d0dfbce63a89 2671
elmot 1:d0dfbce63a89 2672 #endif /* RCC_PLLSAI2_SUPPORT */
elmot 1:d0dfbce63a89 2673
elmot 1:d0dfbce63a89 2674 /**
elmot 1:d0dfbce63a89 2675 * @}
elmot 1:d0dfbce63a89 2676 */
elmot 1:d0dfbce63a89 2677
elmot 1:d0dfbce63a89 2678 /**
elmot 1:d0dfbce63a89 2679 * @}
elmot 1:d0dfbce63a89 2680 */
elmot 1:d0dfbce63a89 2681
elmot 1:d0dfbce63a89 2682 #endif /* HAL_RCC_MODULE_ENABLED */
elmot 1:d0dfbce63a89 2683 /**
elmot 1:d0dfbce63a89 2684 * @}
elmot 1:d0dfbce63a89 2685 */
elmot 1:d0dfbce63a89 2686
elmot 1:d0dfbce63a89 2687 /**
elmot 1:d0dfbce63a89 2688 * @}
elmot 1:d0dfbce63a89 2689 */
elmot 1:d0dfbce63a89 2690
elmot 1:d0dfbce63a89 2691 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
elmot 1:d0dfbce63a89 2692