Progetto STM32 / Mbed 2 deprecated EncoderFinal

Encoder

Dependencies:   mbed

Fork of HardwareQuadratureEncoderABZ by Nigel Webb

main.cpp@1:7a96e635f7a7, 2017-04-29 (annotated)

Committer:
schille
Date:
Sat Apr 29 09:54:34 2017 +0000
Revision:
1:7a96e635f7a7
Parent:
0:25c34018702c 
Encoder

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Nigel945426 0:25c34018702c 1 #include "mbed.h"
Nigel945426 0:25c34018702c 2
Nigel945426 0:25c34018702c 3 // Hardware Quadrature Encoder ABZ for Nucleo F401RE
Nigel945426 0:25c34018702c 4 // Output on debug port to host PC @ 9600 baud
Nigel945426 0:25c34018702c 5 //
Nigel945426 0:25c34018702c 6 // By Nigel Webb, November 2014
Nigel945426 0:25c34018702c 7
schille 1:7a96e635f7a7 8 /* Encoder Connections
schille 1:7a96e635f7a7 9 PA8 = CH1
schille 1:7a96e635f7a7 10 PA9 = CH2
schille 1:7a96e635f7a7 11
schille 1:7a96e635f7a7 12 PA6 = CH1
schille 1:7a96e635f7a7 13 PA7 = CH2
Nigel945426 0:25c34018702c 14 */
Nigel945426 0:25c34018702c 15
Nigel945426 0:25c34018702c 16
Nigel945426 0:25c34018702c 17 void EncoderInitialise(void) {
schille 1:7a96e635f7a7 18 // configure GPIO PA8 & PA9 as CH1 & CH2 inputs for Encoder1
Nigel945426 0:25c34018702c 19 RCC->AHB1ENR |= 0x00000001; // Enable clock for GPIOA
schille 1:7a96e635f7a7 20 GPIOA->MODER |= GPIO_MODER_MODER8_1 | GPIO_MODER_MODER9_1 ; //PA8 & PA9 as Alternate Function /*!< GPIO port mode register, Address offset: 0x00 */
schille 1:7a96e635f7a7 21 GPIOA->OTYPER |= GPIO_OTYPER_OT_8 | GPIO_OTYPER_OT_9 ; //PA8 & PA9 as Inputs /*!< GPIO port output type register, Address offset: 0x04 */
schille 1:7a96e635f7a7 22 GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8_1 | GPIO_OSPEEDER_OSPEEDR9_1 ; // High speed /*!< GPIO port output speed register, Address offset: 0x08 */
schille 1:7a96e635f7a7 23 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR8_1 | GPIO_PUPDR_PUPDR9_1 ; // Pull Down /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
schille 1:7a96e635f7a7 24 //GPIOA->AFR[0] |= 0x11000000 ; // AF02 for PA8 & PA9 /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
schille 1:7a96e635f7a7 25 //GPIOA->AFR[1] |= 0x00000011 ; // /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
Nigel945426 0:25c34018702c 26
schille 1:7a96e635f7a7 27 // configure GPIO PA6 & PA7 as CH1 & CH2 inputs for Encoder2
schille 1:7a96e635f7a7 28 RCC->AHB1ENR |= 0x00000001; // Enable clock for GPIOA
schille 1:7a96e635f7a7 29 GPIOA->MODER |= GPIO_MODER_MODER6_1 | GPIO_MODER_MODER7_1 ; //PA6 & PA7 as Alternate Function /*!< GPIO port mode register, Address offset: 0x00 */
schille 1:7a96e635f7a7 30 GPIOA->OTYPER |= GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_7 ; //PA6 & PA7 as Inputs /*!< GPIO port output type register, Address offset: 0x04 */
schille 1:7a96e635f7a7 31 GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR6_1 | GPIO_OSPEEDER_OSPEEDR7_1 ; // High speed /*!< GPIO port output speed register, Address offset: 0x08 */
schille 1:7a96e635f7a7 32 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR6_1 | GPIO_PUPDR_PUPDR7_1 ; // Pull Down /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
schille 1:7a96e635f7a7 33 GPIOA->AFR[0] |= 0x22000000 ; // AF02 for PA6 & PA7 /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
schille 1:7a96e635f7a7 34 GPIOA->AFR[1] |= 0x00000011 ; // /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
Nigel945426 0:25c34018702c 35
schille 1:7a96e635f7a7 36 // configure TIM1 & TIM3 as Encoder input
schille 1:7a96e635f7a7 37 RCC->APB2ENR |= 0x00000001; // Enable clock for TIM1
schille 1:7a96e635f7a7 38 RCC->APB1ENR |= 0x00000002; // Enable clock for TIM3
schille 1:7a96e635f7a7 39
schille 1:7a96e635f7a7 40 TIM1->CR1 = 0x0001; // CEN(Counter ENable)='1' < TIM control register 1
schille 1:7a96e635f7a7 41 TIM1->SMCR = 0x0001; // SMS='001' (Encoder mode 1) < TIM CH2 Edge
schille 1:7a96e635f7a7 42 TIM1->CCMR1 = 0xF1F1; // CC1S='01' CC2S='01' < TIM capture/compare mode register 1
schille 1:7a96e635f7a7 43 TIM1->CCMR2 = 0x0000; // < TIM capture/compare mode register 2
schille 1:7a96e635f7a7 44 TIM1->CCER = 0x0011; // CC1P CC2P < TIM capture/compare enable register
schille 1:7a96e635f7a7 45 TIM1->PSC = 0x0000; // Prescaler = (0+1) < TIM prescaler
schille 1:7a96e635f7a7 46 TIM1->ARR = 0x0000000a; // reload at 10 < TIM auto-reload register
schille 1:7a96e635f7a7 47 TIM1->CNT = 0x0000; //reset the counter before we use it
schille 1:7a96e635f7a7 48
schille 1:7a96e635f7a7 49 TIM3->CR1 = 0x0001; // CEN(Counter ENable)='1' < TIM control register 1
schille 1:7a96e635f7a7 50 TIM3->SMCR = 0x0001; // SMS='001' (Encoder mode 1) < TIM CH2 Edge
schille 1:7a96e635f7a7 51 TIM3->CCMR1 = 0xF1F1; // CC1S='01' CC2S='01' < TIM capture/compare mode register 1
schille 1:7a96e635f7a7 52 TIM3->CCMR2 = 0x0000; // < TIM capture/compare mode register 2
schille 1:7a96e635f7a7 53 TIM3->CCER = 0x0011; // CC1P CC2P < TIM capture/compare enable register
schille 1:7a96e635f7a7 54 TIM3->PSC = 0x0000; // Prescaler = (0+1) < TIM prescaler
schille 1:7a96e635f7a7 55 TIM3->ARR = 0x0000000a; // reload at 10 < TIM auto-reload register
schille 1:7a96e635f7a7 56 TIM3->CNT = 0x0000; //reset the counter before we use it
schille 1:7a96e635f7a7 57
Nigel945426 0:25c34018702c 58 }
Nigel945426 0:25c34018702c 59
Nigel945426 0:25c34018702c 60 int main() {
schille 1:7a96e635f7a7 61
schille 1:7a96e635f7a7 62 printf("\e[1;1H\e[2J");
Nigel945426 0:25c34018702c 63 EncoderInitialise() ;
Nigel945426 0:25c34018702c 64
schille 1:7a96e635f7a7 65 uint16_t count1=0, count2=0;
Nigel945426 0:25c34018702c 66
schille 1:7a96e635f7a7 67 while (1) {
schille 1:7a96e635f7a7 68 // Print Encoder count to debug port every 0.5 seconds
schille 1:7a96e635f7a7 69 count1 = TIM1->CNT ; // Get current position from Encoder1
schille 1:7a96e635f7a7 70 count2 = TIM3->CNT ; // Get current position from Encoder2
schille 1:7a96e635f7a7 71 printf("COUNT1 %d COUNT2 %d\r\n", count1, count2);
Nigel945426 0:25c34018702c 72 wait(0.5);
Nigel945426 0:25c34018702c 73 }
schille 1:7a96e635f7a7 74
Nigel945426 0:25c34018702c 75 }