To get started with Seeed Tiny BLE, include detecting motion, button and battery level.

Dependencies:   BLE_API eMPL_MPU6050 mbed nRF51822

Files at this revision

API Documentation at this revision

Comitter:
yihui
Date:
Thu Nov 05 06:58:30 2015 +0000
Parent:
2:b61ddbb8528e
Commit message:
update ble libraries

Changed in this revision

BLE_API.lib Show annotated file Show diff for this revision Revisions of this file
main.cpp Show annotated file Show diff for this revision Revisions of this file
mbed.bld Show annotated file Show diff for this revision Revisions of this file
nRF51822.lib Show annotated file Show diff for this revision Revisions of this file
nRF51822/btle/btle.cpp Show diff for this revision Revisions of this file
nRF51822/btle/btle.h Show diff for this revision Revisions of this file
nRF51822/btle/btle_advertising.cpp Show diff for this revision Revisions of this file
nRF51822/btle/btle_advertising.h Show diff for this revision Revisions of this file
nRF51822/btle/btle_gap.cpp Show diff for this revision Revisions of this file
nRF51822/btle/btle_gap.h Show diff for this revision Revisions of this file
nRF51822/btle/custom/custom_helper.cpp Show diff for this revision Revisions of this file
nRF51822/btle/custom/custom_helper.h Show diff for this revision Revisions of this file
nRF51822/common/ansi_escape.h Show diff for this revision Revisions of this file
nRF51822/common/assertion.h Show diff for this revision Revisions of this file
nRF51822/common/binary.h Show diff for this revision Revisions of this file
nRF51822/common/ble_error.h Show diff for this revision Revisions of this file
nRF51822/common/common.h Show diff for this revision Revisions of this file
nRF51822/common/compiler.h Show diff for this revision Revisions of this file
nRF51822/nRF51822n.cpp Show diff for this revision Revisions of this file
nRF51822/nRF51822n.h Show diff for this revision Revisions of this file
nRF51822/nRF51Gap.cpp Show diff for this revision Revisions of this file
nRF51822/nRF51Gap.h Show diff for this revision Revisions of this file
nRF51822/nRF51GattServer.cpp Show diff for this revision Revisions of this file
nRF51822/nRF51GattServer.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/ble_radio_notification/ble_radio_notification.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/ble_radio_notification/ble_radio_notification.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/ble_services/ble_dfu/ble_dfu.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/ble_services/ble_dfu/ble_dfu.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/common/ble_advdata.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/common/ble_advdata.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/common/ble_advdata_parser.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/common/ble_advdata_parser.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/common/ble_conn_params.cpp Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/common/ble_conn_params.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/common/ble_date_time.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/common/ble_sensor_location.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/common/ble_srv_common.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/common/ble_srv_common.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/device_manager/config/device_manager_cnfg.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/ble/device_manager/device_manager.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/ble_flash/ble_flash.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/ble_flash/ble_flash.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/hal/compiler_abstraction.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf51.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf51_bitfields.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf51_deprecated.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_delay.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_ecb.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_ecb.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_gpio.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_gpiote.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_nvmc.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_nvmc.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_temp.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/pstorage/config/pstorage_platform.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/pstorage/pstorage.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/drivers_nrf/pstorage/pstorage.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/bootloader.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/bootloader_types.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/bootloader_util.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/bootloader_util_arm.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/dfu.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/dfu_bank_internal.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/dfu_ble_svc.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/dfu_ble_svc_internal.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/dfu_init.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/dfu_init_template.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/dfu_transport.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/dfu_types.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/experimental/dfu_app_handler.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/experimental/dfu_app_handler.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/crc16/crc16.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/crc16/crc16.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/gpiote/app_gpiote.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/hci/hci_mem_pool.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/hci/hci_mem_pool.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/scheduler/app_scheduler.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/scheduler/app_scheduler.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/util/app_error.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/util/app_error.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/util/app_util.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/util/app_util_platform.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/util/app_util_platform.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/util/common.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/util/nordic_common.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/util/nrf_assert.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/util/nrf_assert.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/util/sdk_common.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/util/sdk_errors.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/libraries/util/sdk_os.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/common/softdevice_handler/ant_stack_handler_types.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/common/softdevice_handler/ble_stack_handler_types.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/common/softdevice_handler/softdevice_handler.c Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/common/softdevice_handler/softdevice_handler.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/doc/s110_nrf51822_7.1.0_licence_agreement.pdf Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/doc/s110_nrf51822_7.1.0_readme.txt Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/doc/s110_nrf51822_7.1.0_releasenotes.pdf Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/ble.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/ble_err.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/ble_gap.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/ble_gatt.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/ble_gattc.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/ble_gatts.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/ble_hci.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/ble_l2cap.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/ble_ranges.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/ble_types.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/nrf_error.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/nrf_error_sdm.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/nrf_error_soc.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/nrf_mbr.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/nrf_sdm.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/nrf_soc.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/nrf_svc.h Show diff for this revision Revisions of this file
nRF51822/nordic-sdk/components/softdevice/s110/headers/softdevice_assert.h Show diff for this revision Revisions of this file
nRF51822/projectconfig.h Show diff for this revision Revisions of this file
diff -r b61ddbb8528e -r 24e365bd1b97 BLE_API.lib
--- a/BLE_API.lib	Thu Nov 05 02:46:37 2015 +0000
+++ b/BLE_API.lib	Thu Nov 05 06:58:30 2015 +0000
@@ -1,1 +1,1 @@
-http://mbed.org/teams/Bluetooth-Low-Energy/code/BLE_API/#8a104d9d80c1
+http://mbed.org/teams/Bluetooth-Low-Energy/code/BLE_API/#a097e1be76f4
diff -r b61ddbb8528e -r 24e365bd1b97 main.cpp
--- a/main.cpp	Thu Nov 05 02:46:37 2015 +0000
+++ b/main.cpp	Thu Nov 05 06:58:30 2015 +0000
@@ -6,7 +6,7 @@
 #include "nrf51.h"
 #include "nrf51_bitfields.h"
 
-#include "BLEDevice.h"
+#include "BLE.h"
 #include "DFUService.h"
 #include "UARTService.h"
 
@@ -28,7 +28,7 @@
 #define UART_RTS    p10
 
 /* Starting sampling rate. */
-#define DEFAULT_MPU_HZ  (200)
+#define DEFAULT_MPU_HZ  (100)
 
 DigitalOut blue(LED_BLUE);
 DigitalOut green(LED_GREEN);
@@ -59,13 +59,13 @@
 unsigned short inv_orientation_matrix_to_scalar( const signed char *mtx);
 
 
-void connectionCallback(Gap::Handle_t handle, Gap::addr_type_t peerAddrType, const Gap::address_t peerAddr, const Gap::ConnectionParams_t *params)
+void connectionCallback(const Gap::ConnectionCallbackParams_t *params)
 {
     LOG("Connected!\n");
     bleIsConnected = true;
 }
 
-void disconnectionCallback(Gap::Handle_t handle, Gap::DisconnectionReason_t reason)
+void disconnectionCallback(const Gap::DisconnectionCallbackParams_t *cbParams)
 {
     LOG("Disconnected!\n");
     LOG("Restarting the advertising process\n");
@@ -75,6 +75,9 @@
 
 void tick(void)
 {
+    static uint32_t count = 0;
+    
+    LOG("%d\r\n", count++);
     green = !green;
 }
 
@@ -87,61 +90,6 @@
 void motion_interrupt_handle(void)
 {
     motion_event = 1;
-    
-    {
-        unsigned long sensor_timestamp;
-        short gyro[3], accel[3], sensors;
-        long quat[4];
-        unsigned char more = 1;
-        
-        while (more) {
-            /* This function gets new data from the FIFO when the DMP is in
-             * use. The FIFO can contain any combination of gyro, accel,
-             * quaternion, and gesture data. The sensors parameter tells the
-             * caller which data fields were actually populated with new data.
-             * For example, if sensors == (INV_XYZ_GYRO | INV_WXYZ_QUAT), then
-             * the FIFO isn't being filled with accel data.
-             * The driver parses the gesture data to determine if a gesture
-             * event has occurred; on an event, the application will be notified
-             * via a callback (assuming that a callback function was properly
-             * registered). The more parameter is non-zero if there are
-             * leftover packets in the FIFO.
-             */
-            dmp_read_fifo(gyro, accel, quat, &sensor_timestamp, &sensors,
-                          &more);
-            /* Gyro and accel data are written to the FIFO by the DMP in chip
-             * frame and hardware units. This behavior is convenient because it
-             * keeps the gyro and accel outputs of dmp_read_fifo and
-             * mpu_read_fifo consistent.
-             */
-            if (sensors & INV_XYZ_GYRO) {
-                // LOG("GYRO: %d, %d, %d\n", gyro[0], gyro[1], gyro[2]);
-            }
-            if (sensors & INV_XYZ_ACCEL) {
-                LOG("ACC: %d, %d, %d\n", accel[0], accel[1], accel[2]);
-            }
-            
-            /* Unlike gyro and accel, quaternions are written to the FIFO in
-             * the body frame, q30. The orientation is set by the scalar passed
-             * to dmp_set_orientation during initialization.
-             */
-            if (sensors & INV_WXYZ_QUAT) {
-                // LOG("QUAT: %ld, %ld, %ld, %ld\n", quat[0], quat[1], quat[2], quat[3]);
-            }
-            
-            if (sensors) {
-                read_none_count = 0;
-            } else {
-                read_none_count++;
-                if (read_none_count > 3) {
-                    read_none_count = 0;
-                    
-                    LOG("I2C may be stuck\r\n");
-                    mbed_i2c_clear(MPU6050_SDA, MPU6050_SCL);
-                }
-            }
-        }
-    }
 }
 
 void tap_cb(unsigned char direction, unsigned char count)
@@ -202,12 +150,13 @@
     dmp_set_fifo_rate(DEFAULT_MPU_HZ);
     mpu_set_dmp_state(1);
     
-//     dmp_set_interrupt_mode(DMP_INT_GESTURE);
+    dmp_set_interrupt_mode(DMP_INT_GESTURE);
     dmp_set_tap_thresh(TAP_XYZ, 50);
     
     
     motion_probe.fall(motion_interrupt_handle);
 
+
     
     Ticker ticker;
     ticker.attach(tick, 3);
@@ -216,8 +165,8 @@
 
     LOG("Initialising the nRF51822\n");
     ble.init();
-    ble.onDisconnection(disconnectionCallback);
-    ble.onConnection(connectionCallback);
+    ble.gap().onDisconnection(disconnectionCallback);
+    ble.gap().onConnection(connectionCallback);
 
 
     /* setup advertising */
@@ -233,13 +182,67 @@
     //uartService.retargetStdout();
 
     ble.setAdvertisingInterval(160); /* 100ms; in multiples of 0.625ms. */
-    ble.startAdvertising();
+    ble.gap().startAdvertising();
     
     while (true) {
         if (motion_event) {
-            motion_event = 0;
+            
+            unsigned long sensor_timestamp;
+            short gyro[3], accel[3], sensors;
+            long quat[4];
+            unsigned char more = 1;
             
-           
+            while (more) {
+                /* This function gets new data from the FIFO when the DMP is in
+                 * use. The FIFO can contain any combination of gyro, accel,
+                 * quaternion, and gesture data. The sensors parameter tells the
+                 * caller which data fields were actually populated with new data.
+                 * For example, if sensors == (INV_XYZ_GYRO | INV_WXYZ_QUAT), then
+                 * the FIFO isn't being filled with accel data.
+                 * The driver parses the gesture data to determine if a gesture
+                 * event has occurred; on an event, the application will be notified
+                 * via a callback (assuming that a callback function was properly
+                 * registered). The more parameter is non-zero if there are
+                 * leftover packets in the FIFO.
+                 */
+                dmp_read_fifo(gyro, accel, quat, &sensor_timestamp, &sensors,
+                              &more);
+                
+                
+                /* Gyro and accel data are written to the FIFO by the DMP in chip
+                 * frame and hardware units. This behavior is convenient because it
+                 * keeps the gyro and accel outputs of dmp_read_fifo and
+                 * mpu_read_fifo consistent.
+                 */
+                if (sensors & INV_XYZ_GYRO) {
+                    // LOG("GYRO: %d, %d, %d\n", gyro[0], gyro[1], gyro[2]);
+                }
+                if (sensors & INV_XYZ_ACCEL) {
+                    //LOG("ACC: %d, %d, %d\n", accel[0], accel[1], accel[2]);
+                }
+                
+                /* Unlike gyro and accel, quaternions are written to the FIFO in
+                 * the body frame, q30. The orientation is set by the scalar passed
+                 * to dmp_set_orientation during initialization.
+                 */
+                if (sensors & INV_WXYZ_QUAT) {
+                    // LOG("QUAT: %ld, %ld, %ld, %ld\n", quat[0], quat[1], quat[2], quat[3]);
+                }
+                
+                if (sensors) {
+                    read_none_count = 0;
+                } else {
+                    read_none_count++;
+                    if (read_none_count > 3) {
+                        read_none_count = 0;
+                        
+                        LOG("I2C may be stuck @ %d\r\n", sensor_timestamp);
+                        mbed_i2c_clear(MPU6050_SDA, MPU6050_SCL);
+                    }
+                }
+            }
+            
+            motion_event = 0;
         } else {
             ble.waitForEvent();
         }
diff -r b61ddbb8528e -r 24e365bd1b97 mbed.bld
--- a/mbed.bld	Thu Nov 05 02:46:37 2015 +0000
+++ b/mbed.bld	Thu Nov 05 06:58:30 2015 +0000
@@ -1,1 +1,1 @@
-http://mbed.org/users/mbed_official/code/mbed/builds/433970e64889
\ No newline at end of file
+http://mbed.org/users/mbed_official/code/mbed/builds/9296ab0bfc11
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822.lib
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nRF51822.lib	Thu Nov 05 06:58:30 2015 +0000
@@ -0,0 +1,1 @@
+http://mbed.org/teams/Nordic-Semiconductor/code/nRF51822/#bf85bf7e73d5
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/btle/btle.cpp
--- a/nRF51822/btle/btle.cpp	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,281 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "common/common.h"
-#include "nordic_common.h"
-
-#include "btle.h"
-
-#include "ble_stack_handler_types.h"
-#include "ble_flash.h"
-#if NEED_BOND_MANAGER
-#include "ble_bondmngr.h"
-#endif
-#include "ble_conn_params.h"
-
-#include "btle_gap.h"
-#include "btle_advertising.h"
-#include "custom/custom_helper.h"
-
-#include "softdevice_handler.h"
-#include "pstorage.h"
-
-#include "GapEvents.h"
-#include "nRF51Gap.h"
-#include "nRF51GattServer.h"
-
-#include "ble_hci.h"
-
-#if NEED_BOND_MANAGER /* disabled by default */
-static void service_error_callback(uint32_t nrf_error);
-#endif
-extern "C" void assert_nrf_callback(uint16_t line_num, const uint8_t *p_file_name);
-void            app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t *p_file_name);
-
-#if NEED_BOND_MANAGER /* disabled by default */
-static error_t bond_manager_init(void);
-#endif
-
-static void btle_handler(ble_evt_t *p_ble_evt);
-
-static void sys_evt_dispatch(uint32_t sys_evt)
-{
-    pstorage_sys_event_handler(sys_evt);
-}
-
-error_t btle_init(void)
-{
-    const bool useScheduler = false;
-#if defined(TARGET_DELTA_DFCM_NNN40) || defined(TARGET_HRM1017)
-    SOFTDEVICE_HANDLER_INIT(NRF_CLOCK_LFCLKSRC_RC_250_PPM_4000MS_CALIBRATION, useScheduler);
-#else
-    SOFTDEVICE_HANDLER_INIT(NRF_CLOCK_LFCLKSRC_XTAL_20_PPM, useScheduler);
-#endif
-
-    // Enable BLE stack
-    /**
-     * Using this call, the application can select whether to include the
-     * Service Changed characteristic in the GATT Server. The default in all
-     * previous releases has been to include the Service Changed characteristic,
-     * but this affects how GATT clients behave. Specifically, it requires
-     * clients to subscribe to this attribute and not to cache attribute handles
-     * between connections unless the devices are bonded. If the application
-     * does not need to change the structure of the GATT server attributes at
-     * runtime this adds unnecessary complexity to the interaction with peer
-     * clients. If the SoftDevice is enabled with the Service Changed
-     * Characteristics turned off, then clients are allowed to cache attribute
-     * handles making applications simpler on both sides.
-     */
-    static const bool IS_SRVC_CHANGED_CHARACT_PRESENT = true;
-    ble_enable_params_t enableParams = {
-        .gatts_enable_params = {
-            .service_changed = IS_SRVC_CHANGED_CHARACT_PRESENT
-        }
-    };
-    if (sd_ble_enable(&enableParams) != NRF_SUCCESS) {
-        return ERROR_INVALID_PARAM;
-    }
-
-    ble_gap_addr_t addr;
-    if (sd_ble_gap_address_get(&addr) != NRF_SUCCESS) {
-        return ERROR_INVALID_PARAM;
-    }
-    if (sd_ble_gap_address_set(BLE_GAP_ADDR_CYCLE_MODE_NONE, &addr) != NRF_SUCCESS) {
-        return ERROR_INVALID_PARAM;
-    }
-
-    ASSERT_STATUS( softdevice_ble_evt_handler_set(btle_handler));
-    ASSERT_STATUS( softdevice_sys_evt_handler_set(sys_evt_dispatch));
-
-#if NEED_BOND_MANAGER /* disabled by default */
-    bond_manager_init();
-#endif
-    btle_gap_init();
-
-    return ERROR_NONE;
-}
-
-static void btle_handler(ble_evt_t *p_ble_evt)
-{
-    /* Library service handlers */
-#if NEED_BOND_MANAGER /* disabled by default */
-    ble_bondmngr_on_ble_evt(p_ble_evt);
-#endif
-#if SDK_CONN_PARAMS_MODULE_ENABLE
-    ble_conn_params_on_ble_evt(p_ble_evt);
-#endif
-
-    /* Custom event handler */
-    switch (p_ble_evt->header.evt_id) {
-        case BLE_GAP_EVT_CONNECTED: {
-            Gap::Handle_t handle = p_ble_evt->evt.gap_evt.conn_handle;
-            nRF51Gap::getInstance().setConnectionHandle(handle);
-            const Gap::ConnectionParams_t *params = reinterpret_cast<Gap::ConnectionParams_t *>(&(p_ble_evt->evt.gap_evt.params.connected.conn_params));
-            const ble_gap_addr_t *peer = &p_ble_evt->evt.gap_evt.params.connected.peer_addr;
-            nRF51Gap::getInstance().processConnectionEvent(handle, static_cast<Gap::addr_type_t>(peer->addr_type), peer->addr, params);
-            break;
-        }
-
-        case BLE_GAP_EVT_DISCONNECTED: {
-            Gap::Handle_t handle = p_ble_evt->evt.gap_evt.conn_handle;
-            // Since we are not in a connection and have not started advertising,
-            // store bonds
-            nRF51Gap::getInstance().setConnectionHandle (BLE_CONN_HANDLE_INVALID);
-#if NEED_BOND_MANAGER /* disabled by default */
-            ASSERT_STATUS_RET_VOID ( ble_bondmngr_bonded_centrals_store());
-#endif
-
-            Gap::DisconnectionReason_t reason;
-            switch (p_ble_evt->evt.gap_evt.params.disconnected.reason) {
-                case BLE_HCI_LOCAL_HOST_TERMINATED_CONNECTION:
-                    reason = Gap::LOCAL_HOST_TERMINATED_CONNECTION;
-                    break;
-                case BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION:
-                    reason = Gap::REMOTE_USER_TERMINATED_CONNECTION;
-                    break;
-                case BLE_HCI_CONN_INTERVAL_UNACCEPTABLE:
-                    reason = Gap::CONN_INTERVAL_UNACCEPTABLE;
-                    break;
-                default:
-                    /* Please refer to the underlying transport library for an
-                     * interpretion of this reason's value. */
-                    reason = static_cast<Gap::DisconnectionReason_t>(p_ble_evt->evt.gap_evt.params.disconnected.reason);
-                    break;
-            }
-            nRF51Gap::getInstance().processDisconnectionEvent(handle, reason);
-            break;
-        }
-
-        case BLE_GAP_EVT_SEC_PARAMS_REQUEST: {
-            ble_gap_sec_params_t sec_params = {0};
-
-            sec_params.timeout      = 30; /*< Timeout for Pairing Request or
-                                   * Security Request (in seconds). */
-            sec_params.bond         = 1;  /**< Perform bonding. */
-            sec_params.mitm         = CFG_BLE_SEC_PARAM_MITM;
-            sec_params.io_caps      = CFG_BLE_SEC_PARAM_IO_CAPABILITIES;
-            sec_params.oob          = CFG_BLE_SEC_PARAM_OOB;
-            sec_params.min_key_size = CFG_BLE_SEC_PARAM_MIN_KEY_SIZE;
-            sec_params.max_key_size = CFG_BLE_SEC_PARAM_MAX_KEY_SIZE;
-
-            ASSERT_STATUS_RET_VOID(sd_ble_gap_sec_params_reply(nRF51Gap::getInstance().getConnectionHandle(),
-                                                               BLE_GAP_SEC_STATUS_SUCCESS, &sec_params));
-        }
-        break;
-
-        case BLE_GAP_EVT_TIMEOUT:
-            if (p_ble_evt->evt.gap_evt.params.timeout.src == BLE_GAP_TIMEOUT_SRC_ADVERTISEMENT) {
-                nRF51Gap::getInstance().processEvent(GapEvents::GAP_EVENT_TIMEOUT);
-            }
-            break;
-
-        case BLE_GATTC_EVT_TIMEOUT:
-        case BLE_GATTS_EVT_TIMEOUT:
-            // Disconnect on GATT Server and Client timeout events.
-            // ASSERT_STATUS_RET_VOID (sd_ble_gap_disconnect(m_conn_handle,
-            // BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION));
-            break;
-
-        default:
-            break;
-    }
-
-    nRF51GattServer::getInstance().hwCallback(p_ble_evt);
-}
-
-#if NEED_BOND_MANAGER /* disabled by default */
-/**************************************************************************/
-/*!
-    @brief      Initialises the bond manager
-
-    @note       Bond data will be cleared on reset if the bond delete
-                button is pressed during initialisation (the button is
-                defined as CFG_BLE_BOND_DELETE_BUTTON_NUM).
-
-    @returns
-*/
-/**************************************************************************/
-static error_t bond_manager_init(void)
-{
-    ble_bondmngr_init_t bond_para = {0};
-
-    ASSERT_STATUS ( pstorage_init());
-
-    bond_para.flash_page_num_bond     = CFG_BLE_BOND_FLASH_PAGE_BOND;
-    bond_para.flash_page_num_sys_attr = CFG_BLE_BOND_FLASH_PAGE_SYS_ATTR;
-    //bond_para.bonds_delete            = boardButtonCheck(CFG_BLE_BOND_DELETE_BUTTON_NUM) ;
-    bond_para.evt_handler   = NULL;
-    bond_para.error_handler = service_error_callback;
-
-    ASSERT_STATUS( ble_bondmngr_init( &bond_para ));
-
-    /* Init radio active/inactive notification to flash (to only perform flashing when the radio is inactive) */
-    //  ASSERT_STATUS( ble_radio_notification_init(NRF_APP_PRIORITY_HIGH,
-    //                                             NRF_RADIO_NOTIFICATION_DISTANCE_4560US,
-    //                                             ble_flash_on_radio_active_evt) );
-
-    return ERROR_NONE;
-}
-#endif // #if NEED_BOND_MANAGER
-
-#if NEED_BOND_MANAGER /* disabled by default */
-/**************************************************************************/
-/*!
-    @brief
-    @param[in]  nrf_error
-    @returns
-*/
-/**************************************************************************/
-static void service_error_callback(uint32_t nrf_error)
-{
-    ASSERT_STATUS_RET_VOID( nrf_error );
-}
-#endif // #if NEED_BOND_MANAGER
-
-/**************************************************************************/
-/*!
-    @brief      Callback when an error occurs inside the SoftDevice
-
-    @param[in]  line_num
-    @param[in]  p-file_name
-
-    @returns
-*/
-/**************************************************************************/
-void assert_nrf_callback(uint16_t line_num, const uint8_t *p_file_name)
-{
-    ASSERT(false, (void) 0);
-}
-
-/**************************************************************************/
-/*!
-    @brief      Handler for general errors above the SoftDevice layer.
-                Typically we can' recover from this so we do a reset.
-
-    @param[in]  error_code
-    @param[in]  line_num
-    @param[in]  p-file_name
-
-    @returns
-*/
-/**************************************************************************/
-void app_error_handler(uint32_t       error_code,
-                       uint32_t       line_num,
-                       const uint8_t *p_file_name)
-{
-    ASSERT_STATUS_RET_VOID( error_code );
-    NVIC_SystemReset();
-}
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/btle/btle.h
--- a/nRF51822/btle/btle.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,35 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _BTLE_H_
-#define _BTLE_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "common/common.h"
-
-#include "ble_srv_common.h"
-#include "ble.h"
-
-error_t btle_init(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // ifndef _BTLE_H_
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/btle/btle_advertising.cpp
--- a/nRF51822/btle/btle_advertising.cpp	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,46 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "common/common.h"
-
-#include "ble_advdata.h"
-#include "btle.h"
-
-/**************************************************************************/
-/*!
-    @brief      Starts the advertising process
-
-    @returns
-*/
-/**************************************************************************/
-error_t btle_advertising_start(void)
-{
-    ble_gap_adv_params_t adv_para = {0};
-
-    /* Set the default advertising parameters */
-    adv_para.type        = BLE_GAP_ADV_TYPE_ADV_IND;
-    adv_para.p_peer_addr = NULL; /* Undirected advertising */
-    adv_para.fp          = BLE_GAP_ADV_FP_ANY;
-    adv_para.p_whitelist = NULL;
-    adv_para.interval    = (CFG_GAP_ADV_INTERVAL_MS * 8) / 5; /* Advertising
-                                                               * interval in
-                                                               * units of 0.625
-                                                               * ms */
-    adv_para.timeout     = CFG_GAP_ADV_TIMEOUT_S;
-
-    ASSERT_STATUS( sd_ble_gap_adv_start(&adv_para));
-
-    return ERROR_NONE;
-}
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/btle/btle_advertising.h
--- a/nRF51822/btle/btle_advertising.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,24 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _BTLE_ADVERTISING_H_
-#define _BTLE_ADVERTISING_H_
-
-#include "common/common.h"
-
-error_t btle_advertising_start(void);
-
-#endif // ifndef _BTLE_ADVERTISING_H_
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/btle/btle_gap.cpp
--- a/nRF51822/btle/btle_gap.cpp	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,99 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "common/common.h"
-
-#include "ble_gap.h"
-#include "ble_conn_params.h"
-
-static inline uint32_t msec_to_1_25msec(uint32_t interval_ms) ATTR_ALWAYS_INLINE ATTR_CONST;
-#if SDK_CONN_PARAMS_MODULE_ENABLE
-static void   error_callback(uint32_t nrf_error);
-#endif // SDK_CONN_PARAMS_MODULE_ENABLE
-
-/**************************************************************************/
-/*!
-    @brief      Initialise GAP in the underlying SoftDevice
-
-    @returns
-*/
-/**************************************************************************/
-error_t btle_gap_init(void)
-{
-    ble_gap_conn_params_t gap_conn_params = {0};
-
-    gap_conn_params.min_conn_interval = msec_to_1_25msec(CFG_GAP_CONNECTION_MIN_INTERVAL_MS);  // in 1.25ms units
-    gap_conn_params.max_conn_interval = msec_to_1_25msec(CFG_GAP_CONNECTION_MAX_INTERVAL_MS);  // in 1.25ms unit
-    gap_conn_params.slave_latency     = CFG_GAP_CONNECTION_SLAVE_LATENCY;
-    gap_conn_params.conn_sup_timeout  = CFG_GAP_CONNECTION_SUPERVISION_TIMEOUT_MS / 10; // in 10ms unit
-
-    ble_gap_conn_sec_mode_t sec_mode;
-    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); // no security is needed
-
-    ASSERT_STATUS( sd_ble_gap_device_name_set(&sec_mode, (const uint8_t *) CFG_GAP_LOCAL_NAME, strlen(CFG_GAP_LOCAL_NAME)));
-    ASSERT_STATUS( sd_ble_gap_appearance_set(CFG_GAP_APPEARANCE));
-    ASSERT_STATUS( sd_ble_gap_ppcp_set(&gap_conn_params));
-    ASSERT_STATUS( sd_ble_gap_tx_power_set(CFG_BLE_TX_POWER_LEVEL));
-
-    /**
-     * Call to conn_params_init() is not necessary; and so is disabled by default.
-     * This API should be exposed to the user to be invoked when necessary.
-     */
-#if SDK_CONN_PARAMS_MODULE_ENABLE
-    /* Connection Parameters */
-    enum {
-        FIRST_UPDATE_DELAY = APP_TIMER_TICKS(5000, CFG_TIMER_PRESCALER),
-        NEXT_UPDATE_DELAY  = APP_TIMER_TICKS(5000, CFG_TIMER_PRESCALER),
-        MAX_UPDATE_COUNT   = 3
-    };
-
-    ble_conn_params_init_t cp_init = {0};
-
-    cp_init.p_conn_params                  = NULL;
-    cp_init.first_conn_params_update_delay = FIRST_UPDATE_DELAY;
-    cp_init.next_conn_params_update_delay  = NEXT_UPDATE_DELAY;
-    cp_init.max_conn_params_update_count   = MAX_UPDATE_COUNT;
-    cp_init.start_on_notify_cccd_handle    = BLE_GATT_HANDLE_INVALID;
-    cp_init.disconnect_on_fail             = true;
-    cp_init.evt_handler                    = NULL;
-    cp_init.error_handler                  = error_callback;
-
-    ASSERT_STATUS ( ble_conn_params_init(&cp_init));
-#endif // SDK_CONN_PARAMS_MODULE_ENABLE
-
-    return ERROR_NONE;
-}
-
-/**************************************************************************/
-/*!
-    @brief      Converts msecs to an integer representing 1.25ms units
-
-    @param[in]  ms
-                The number of milliseconds to conver to 1.25ms units
-
-    @returns    The number of 1.25ms units in the supplied number of ms
-*/
-/**************************************************************************/
-static inline uint32_t msec_to_1_25msec(uint32_t interval_ms)
-{
-    return (interval_ms * 4) / 5;
-}
-
-#if SDK_CONN_PARAMS_MODULE_ENABLE
-static void error_callback(uint32_t nrf_error)
-{
-    ASSERT_STATUS_RET_VOID( nrf_error );
-}
-#endif // SDK_CONN_PARAMS_MODULE_ENABLE
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/btle/btle_gap.h
--- a/nRF51822/btle/btle_gap.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,24 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _BTLE_GAP_H_
-#define _BTLE_GAP_H_
-
-#include "common/common.h"
-
-error_t btle_gap_init(void);
-
-#endif // ifndef _BTLE_GAP_H_
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/btle/custom/custom_helper.cpp
--- a/nRF51822/btle/custom/custom_helper.cpp	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,311 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "custom_helper.h"
-
-/*
- * The current version of the soft-device doesn't handle duplicate 128-bit UUIDs
- * very  well. It is therefore necessary to filter away duplicates before
- * passing long UUIDs to sd_ble_uuid_vs_add(). The following types and data
- * structures involved in maintaining a local cache of 128-bit UUIDs.
- */
-typedef struct {
-    LongUUIDBytes_t uuid;
-    uint8_t         type;
-} converted_uuid_table_entry_t;
-static const unsigned UUID_TABLE_MAX_ENTRIES = 8; /* This is the maximum number of 128-bit UUIDs with distinct bases that
-                                                   * we expect to be in use; increase this limit if needed. */
-static unsigned uuidTableEntries = 0; /* current usage of the table */
-converted_uuid_table_entry_t convertedUUIDTable[UUID_TABLE_MAX_ENTRIES];
-
-/**
- * lookup the cache of previously converted 128-bit UUIDs to find a type value.
- * @param  uuid          base 128-bit UUID
- * @param  recoveredType the type field of the 3-byte nRF's uuid.
- * @return               true if a match is found.
- */
-static bool
-lookupConvertedUUIDTable(const LongUUIDBytes_t uuid, uint8_t *recoveredType)
-{
-    unsigned i;
-    for (i = 0; i < uuidTableEntries; i++) {
-        unsigned byteIndex;
-        for (byteIndex = 0; byteIndex < LENGTH_OF_LONG_UUID; byteIndex++) {
-            /* Skip bytes 2 and 3, because they contain the shortUUID (16-bit) version of the
-             * long UUID; and we're comparing against the remainder. */
-            if ((byteIndex == 2) || (byteIndex == 3)) {
-                continue;
-            }
-
-            if (convertedUUIDTable[i].uuid[byteIndex] != uuid[byteIndex]) {
-                break;
-            }
-        }
-
-        if (byteIndex == LENGTH_OF_LONG_UUID) {
-            *recoveredType = convertedUUIDTable[i].type;
-            return true;
-        }
-    }
-
-    return false;
-}
-
-static void
-addToConvertedUUIDTable(const LongUUIDBytes_t uuid, uint8_t type)
-{
-    if (uuidTableEntries == UUID_TABLE_MAX_ENTRIES) {
-        return; /* recovery needed; or at least the user should be warned about this fact.*/
-    }
-
-    memcpy(convertedUUIDTable[uuidTableEntries].uuid, uuid, LENGTH_OF_LONG_UUID);
-    convertedUUIDTable[uuidTableEntries].uuid[2] = 0;
-    convertedUUIDTable[uuidTableEntries].uuid[3] = 0;
-    convertedUUIDTable[uuidTableEntries].type    = type;
-    uuidTableEntries++;
-}
-
-/**
- * The nRF transport has its own 3-byte representation of a UUID. If the user-
- * specified UUID is 128-bits wide, then the UUID base needs to be added to the
- * soft-device and converted to a 3-byte handle before being used further. This
- * function is responsible for this translation of user-specified UUIDs into
- * nRF's representation.
- *
- * @param[in]  uuid
- *                 user-specified UUID
- * @return nRF
- *              3-byte UUID (containing a type and 16-bit UUID) representation
- *              to be used with SVC calls.
- */
-ble_uuid_t custom_convert_to_nordic_uuid(const UUID &uuid)
-{
-    ble_uuid_t nordicUUID;
-    nordicUUID.uuid = uuid.getShortUUID();
-    nordicUUID.type = BLE_UUID_TYPE_UNKNOWN; /* to be set below */
-
-    if (uuid.shortOrLong() == UUID::UUID_TYPE_SHORT) {
-        nordicUUID.type = BLE_UUID_TYPE_BLE;
-    } else {
-        if (!lookupConvertedUUIDTable(uuid.getBaseUUID(), &nordicUUID.type)) {
-            nordicUUID.type = custom_add_uuid_base(uuid.getBaseUUID());
-            addToConvertedUUIDTable(uuid.getBaseUUID(), nordicUUID.type);
-        }
-    }
-
-    return nordicUUID;
-}
-
-/**************************************************************************/
-/*!
-    @brief      Adds the base UUID to the custom service. All UUIDs used
-                by this service are based on this 128-bit UUID.
-
-    @note       This UUID needs to be added to the SoftDevice stack before
-                adding the service's primary service via
-                'sd_ble_gatts_service_add'
-
-    @param[in]  p_uuid_base   A pointer to the 128-bit UUID array (8*16)
-
-    @returns    The UUID type.
-                A return value of 0 should be considered an error.
-
-    @retval     0x00    BLE_UUID_TYPE_UNKNOWN
-    @retval     0x01    BLE_UUID_TYPE_BLE
-    @retval     0x02    BLE_UUID_TYPE_VENDOR_BEGIN
-
-    @section EXAMPLE
-    @code
-
-    // Take note that bytes 2/3 are blank since these are used to identify
-    // the primary service and individual characteristics
-    #define CFG_CUSTOM_UUID_BASE  "\x6E\x40\x00\x00\xB5\xA3\xF3\x93\xE0\xA9\xE5\x0E\x24\xDC\xCA\x9E"
-
-    uint8_t uuid_type = custom_add_uuid_base(CFG_CUSTOM_UUID_BASE);
-    ASSERT(uuid_type > 0, ERROR_NOT_FOUND);
-
-    // We can now safely add the primary service and any characteristics
-    // for our custom service ...
-
-    @endcode
-*/
-/**************************************************************************/
-uint8_t custom_add_uuid_base(uint8_t const *const p_uuid_base)
-{
-    ble_uuid128_t base_uuid;
-    uint8_t       uuid_type = 0;
-
-    /* Reverse the bytes since ble_uuid128_t is LSB */
-    for (unsigned i = 0; i < LENGTH_OF_LONG_UUID; i++) {
-        base_uuid.uuid128[i] = p_uuid_base[LENGTH_OF_LONG_UUID - 1 - i];
-    }
-
-    ASSERT_INT( ERROR_NONE, sd_ble_uuid_vs_add( &base_uuid, &uuid_type ), 0);
-
-    return uuid_type;
-}
-
-/**************************************************************************/
-/*!
-
-*/
-/**************************************************************************/
-error_t custom_decode_uuid_base(uint8_t const *const p_uuid_base,
-                                ble_uuid_t          *p_uuid)
-{
-    LongUUIDBytes_t uuid_base_le;
-
-    /* Reverse the bytes since ble_uuid128_t is LSB */
-    for (uint8_t i = 0; i < LENGTH_OF_LONG_UUID; i++) {
-        uuid_base_le[i] = p_uuid_base[LENGTH_OF_LONG_UUID - 1 - i];
-    }
-
-    ASSERT_STATUS( sd_ble_uuid_decode(LENGTH_OF_LONG_UUID, uuid_base_le, p_uuid));
-
-    return ERROR_NONE;
-}
-
-/**************************************************************************/
-/*!
-    @brief      Adds a new characteristic to the custom service, assigning
-                properties, a UUID add-on value, etc.
-
-    @param[in]  service_handle
-    @param[in]  p_uuid            The 16-bit value to add to the base UUID
-                                  for this characteristic (normally >1
-                                  since 1 is typically used by the primary
-                                  service).
-    @param[in]  char_props        The characteristic properties, as
-                                  defined by ble_gatt_char_props_t
-    @param[in]  max_length        The maximum length of this characeristic
-    @param[in]  p_char_handle
-
-    @returns
-    @retval     ERROR_NONE        Everything executed normally
-*/
-/**************************************************************************/
-error_t custom_add_in_characteristic(uint16_t    service_handle,
-                                     ble_uuid_t *p_uuid,
-                                     uint8_t     properties,
-                                     uint8_t    *p_data,
-                                     uint16_t    min_length,
-                                     uint16_t    max_length,
-                                     bool        readAuthorization,
-                                     bool        writeAuthorization,
-                                     ble_gatts_char_handles_t *p_char_handle)
-{
-    /* Characteristic metadata */
-    ble_gatts_attr_md_t   cccd_md;
-    ble_gatt_char_props_t char_props;
-
-    memcpy(&char_props, &properties, 1);
-
-    if (char_props.notify || char_props.indicate) {
-        /* Notification requires cccd */
-        memclr_( &cccd_md, sizeof(ble_gatts_attr_md_t));
-        cccd_md.vloc = BLE_GATTS_VLOC_STACK;
-        BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.read_perm);
-        BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.write_perm);
-    }
-
-    ble_gatts_char_md_t char_md = {0};
-
-    char_md.char_props = char_props;
-    char_md.p_cccd_md  =
-        (char_props.notify || char_props.indicate) ? &cccd_md : NULL;
-
-    /* Attribute declaration */
-    ble_gatts_attr_md_t attr_md = {0};
-
-    attr_md.rd_auth = readAuthorization;
-    attr_md.wr_auth = writeAuthorization;
-
-    attr_md.vloc = BLE_GATTS_VLOC_STACK;
-    attr_md.vlen = (min_length == max_length) ? 0 : 1;
-
-    if (char_props.read || char_props.notify || char_props.indicate) {
-        BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.read_perm);
-    }
-
-    if (char_props.write || char_props.write_wo_resp) {
-        BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.write_perm);
-    }
-
-    ble_gatts_attr_t attr_char_value = {0};
-
-    attr_char_value.p_uuid    = p_uuid;
-    attr_char_value.p_attr_md = &attr_md;
-    attr_char_value.init_len  = min_length;
-    attr_char_value.max_len   = max_length;
-    attr_char_value.p_value   = p_data;
-
-    ASSERT_STATUS ( sd_ble_gatts_characteristic_add(service_handle,
-                                                    &char_md,
-                                                    &attr_char_value,
-                                                    p_char_handle));
-
-    return ERROR_NONE;
-}
-
-
-
-/**************************************************************************/
-/*!
-    @brief      Adds a new descriptor to the custom service, assigning
-                value, a UUID add-on value, etc.
-
-    @param[in]  char_handle
-    @param[in]  p_uuid            The 16-bit value to add to the base UUID
-                                  for this descriptor (normally >1
-                                  since 1 is typically used by the primary
-                                  service).
-    @param[in]  max_length        The maximum length of this descriptor
-
-    @returns
-    @retval     ERROR_NONE        Everything executed normally
-*/
-/**************************************************************************/
-error_t custom_add_in_descriptor(uint16_t    char_handle,
-                                             ble_uuid_t *p_uuid,
-                                             uint8_t    *p_data,
-                                             uint16_t    min_length,
-                                             uint16_t    max_length,
-                                             uint16_t   *p_desc_handle)
-{
-    /* Descriptor metadata */
-    ble_gatts_attr_md_t   desc_md = {0};
-
-    desc_md.vloc = BLE_GATTS_VLOC_STACK;
-    desc_md.vlen = (min_length == max_length) ? 0 : 1;
-
-    /* Make it readable and writable */
-    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&desc_md.read_perm);
-    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&desc_md.write_perm);
-
-    ble_gatts_attr_t attr_desc = {0};
-
-    attr_desc.p_uuid    = p_uuid;
-    attr_desc.p_attr_md = &desc_md;
-    attr_desc.init_len  = min_length;
-    attr_desc.max_len   = max_length;
-    attr_desc.p_value   = p_data;
-
-    ASSERT_STATUS ( sd_ble_gatts_descriptor_add(char_handle,
-                                                &attr_desc,
-                                                p_desc_handle));
-
-    return ERROR_NONE;
-}
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/btle/custom/custom_helper.h
--- a/nRF51822/btle/custom/custom_helper.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _CUSTOM_HELPER_H_
-#define _CUSTOM_HELPER_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "common/common.h"
-#include "ble.h"
-#include "UUID.h"
-
-uint8_t custom_add_uuid_base(uint8_t const *const p_uuid_base);
-error_t custom_decode_uuid(uint8_t const *const p_uuid_base,
-                           ble_uuid_t          *p_uuid);
-ble_uuid_t custom_convert_to_nordic_uuid(const UUID &uuid);
-
-error_t custom_add_in_characteristic(uint16_t                  service_handle,
-                                     ble_uuid_t               *p_uuid,
-                                     uint8_t                   properties,
-                                     uint8_t                  *p_data,
-                                     uint16_t                  min_length,
-                                     uint16_t                  max_length,
-                                     bool                      readAuthorization,
-                                     bool                      writeAuthorization,
-                                     ble_gatts_char_handles_t *p_char_handle);
-
-error_t custom_add_in_descriptor(uint16_t                      char_handle,
-                                     ble_uuid_t               *p_uuid,
-                                     uint8_t                  *p_data,
-                                     uint16_t                  min_length,
-                                     uint16_t                  max_length,
-                                     uint16_t                 *p_desc_handle);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // ifndef _CUSTOM_HELPER_H_
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/common/ansi_escape.h
--- a/nRF51822/common/ansi_escape.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,103 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     ansi_esc_code.h
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-/** \file
- *  \brief TBD
- *
- *  \note TBD
- */
-
-/** \ingroup TBD
- *  \defgroup TBD
- *  \brief TBD
- *
- *  @{
- */
-
-#ifndef _ANSI_ESC_CODE_H_
-#define _ANSI_ESC_CODE_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define CSI_CODE(seq)   "\33[" seq
-#define CSI_SGR(x)      CSI_CODE(#x) "m"
-
-//------------- Cursor movement -------------//
-#define ANSI_CURSOR_UP(n)        CSI_CODE(#n "A")
-#define ANSI_CURSOR_DOWN(n)      CSI_CODE(#n "B")
-#define ANSI_CURSOR_FORWARD(n)   CSI_CODE(#n "C")
-#define ANSI_CURSOR_BACKWARD(n)  CSI_CODE(#n "D")
-#define ANSI_CURSOR_LINE_DOWN(n) CSI_CODE(#n "E")
-#define ANSI_CURSOR_LINE_UP(n)   CSI_CODE(#n "F")
-#define ANSI_CURSOR_POSITION(n, m) CSI_CODE(#n ";" #m "H")
-
-#define ANSI_ERASE_SCREEN(n)     CSI_CODE(#n "J")
-#define ANSI_ERASE_LINE(n)       CSI_CODE(#n "K")
-
-/** text color */
-#define ANSI_TEXT_BLACK          CSI_SGR(30)
-#define ANSI_TEXT_RED            CSI_SGR(31)
-#define ANSI_TEXT_GREEN          CSI_SGR(32)
-#define ANSI_TEXT_YELLOW         CSI_SGR(33)
-#define ANSI_TEXT_BLUE           CSI_SGR(34)
-#define ANSI_TEXT_MAGENTA        CSI_SGR(35)
-#define ANSI_TEXT_CYAN           CSI_SGR(36)
-#define ANSI_TEXT_WHITE          CSI_SGR(37)
-#define ANSI_TEXT_DEFAULT        CSI_SGR(39)
-
-/** background color */
-#define ANSI_BG_BLACK            CSI_SGR(40)
-#define ANSI_BG_RED              CSI_SGR(41)
-#define ANSI_BG_GREEN            CSI_SGR(42)
-#define ANSI_BG_YELLOW           CSI_SGR(43)
-#define ANSI_BG_BLUE             CSI_SGR(44)
-#define ANSI_BG_MAGENTA          CSI_SGR(45)
-#define ANSI_BG_CYAN             CSI_SGR(46)
-#define ANSI_BG_WHITE            CSI_SGR(47)
-#define ANSI_BG_DEFAULT          CSI_SGR(49)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _TUSB_ANSI_ESC_CODE_H_ */
-
-/** @} */
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/common/assertion.h
--- a/nRF51822/common/assertion.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,200 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     assertion.h
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, K. Townsend (microBuilder.eu)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-/**************************************************************************/
-
-/** \file
- *  \brief TBD
- *
- *  \note TBD
- */
-
-/** \ingroup TBD
- *  \defgroup TBD
- *  \brief TBD
- *
- *  @{
- */
-
-#ifndef _ASSERTION_H_
-#define _ASSERTION_H_
-
-#include "projectconfig.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-static inline void debugger_breakpoint(void) ATTR_ALWAYS_INLINE;
-static inline void debugger_breakpoint(void)
-{
-#ifndef _TEST_
-  __asm("BKPT #0\n");
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Compile-time Assert
-//--------------------------------------------------------------------+
-#if defined __COUNTER__ && __COUNTER__ != __COUNTER__
-  #define _ASSERT_COUNTER __COUNTER__
-#else
-  #define _ASSERT_COUNTER __LINE__
-#endif
-
-#define ASSERT_STATIC(const_expr, message) enum { XSTRING_CONCAT_(static_assert_, _ASSERT_COUNTER) = 1/(!!(const_expr)) }
-
-//--------------------------------------------------------------------+
-// Assert Helper
-//--------------------------------------------------------------------+
-//#ifndef _TEST_
-//  #define ASSERT_MESSAGE(format, ...)\
-//    _PRINTF("Assert at %s: %s: %d: " format "\n", __BASE_FILE__, __PRETTY_FUNCTION__, __LINE__, __VA_ARGS__)
-//#else
-//  #define ASSERT_MESSAGE(format, ...)\
-//    _PRINTF("%d:note: Assert " format "\n", __LINE__, __VA_ARGS__)
-//#endif
-
-#if CFG_DEBUG == 3
-  #define ASSERT_MESSAGE(format, ...) debugger_breakpoint()
-#elif CFG_DEBUG == 2
-  #define ASSERT_MESSAGE(format, ...) printf("Assert at %s: %s: %d: " format "\n", __BASE_FILE__, __PRETTY_FUNCTION__, __LINE__, __VA_ARGS__)
-#else
-  #define ASSERT_MESSAGE(format, ...)
-#endif
-
-#define ASSERT_ERROR_HANDLER(x, para)  \
-    return (x)
-
-#define ASSERT_DEFINE_WITH_HANDLER(error_handler, handler_para, setup_statement, condition, error, format, ...) \
-  do{\
-    setup_statement;\
-	  if (!(condition)) {\
-	    ASSERT_MESSAGE(format, __VA_ARGS__);\
-	    error_handler(error, handler_para);\
-	  }\
-	}while(0)
-
-#define ASSERT_DEFINE(...) ASSERT_DEFINE_WITH_HANDLER(ASSERT_ERROR_HANDLER, NULL, __VA_ARGS__)
-
-//--------------------------------------------------------------------+
-// error_t Status Assert TODO use ASSERT_DEFINE
-//--------------------------------------------------------------------+
-#define ASSERT_STATUS_MESSAGE(sts, message) \
-    ASSERT_DEFINE(error_t status = (error_t)(sts),\
-                  ERROR_NONE == status, status, "%s: %s", ErrorStr[status], message)
-
-#define ASSERT_STATUS(sts) \
-    ASSERT_DEFINE(error_t status = (error_t)(sts),\
-                  ERROR_NONE == status, status, "error = %d", status)
-
-#define ASSERT_STATUS_RET_VOID(sts) \
-    ASSERT_DEFINE(error_t status = (error_t)(sts),\
-                  ERROR_NONE == status, (void) 0, "error = %d", status)
-
-//--------------------------------------------------------------------+
-// Logical Assert
-//--------------------------------------------------------------------+
-#define ASSERT(...)                      ASSERT_TRUE(__VA_ARGS__)
-#define ASSERT_TRUE(condition  , error)  ASSERT_DEFINE( , (condition), error, "%s", "evaluated to false")
-#define ASSERT_FALSE(condition , error)  ASSERT_DEFINE( ,!(condition), error, "%s", "evaluated to true")
-
-//--------------------------------------------------------------------+
-// Pointer Assert
-//--------------------------------------------------------------------+
-#define ASSERT_PTR(...)                    ASSERT_PTR_NOT_NULL(__VA_ARGS__)
-#define ASSERT_PTR_NOT_NULL(pointer, error) ASSERT_DEFINE( , NULL != (pointer), error, "%s", "pointer is NULL")
-#define ASSERT_PTR_NULL(pointer, error)    ASSERT_DEFINE( , NULL == (pointer), error, "%s", "pointer is not NULL")
-
-//--------------------------------------------------------------------+
-// Integral Assert
-//--------------------------------------------------------------------+
-#define ASSERT_XXX_EQUAL(type_format, expected, actual, error) \
-    ASSERT_DEFINE(\
-                  uint32_t exp = (expected); uint32_t act = (actual),\
-                  exp==act,\
-                  error,\
-                  "expected " type_format ", actual " type_format, exp, act)
-
-#define ASSERT_XXX_WITHIN(type_format, lower, upper, actual, error) \
-    ASSERT_DEFINE(\
-                  uint32_t low = (lower); uint32_t up = (upper); uint32_t act = (actual),\
-                  (low <= act) && (act <= up),\
-                  error,\
-                  "expected within " type_format " - " type_format ", actual " type_format, low, up, act)
-
-//--------------------------------------------------------------------+
-// Integer Assert
-//--------------------------------------------------------------------+
-#define ASSERT_INT(...)        ASSERT_INT_EQUAL(__VA_ARGS__)
-#define ASSERT_INT_EQUAL(...)  ASSERT_XXX_EQUAL("%d", __VA_ARGS__)
-#define ASSERT_INT_WITHIN(...) ASSERT_XXX_WITHIN("%d", __VA_ARGS__)
-
-//--------------------------------------------------------------------+
-// Hex Assert
-//--------------------------------------------------------------------+
-#define ASSERT_HEX(...)        ASSERT_HEX_EQUAL(__VA_ARGS__)
-#define ASSERT_HEX_EQUAL(...)  ASSERT_XXX_EQUAL("0x%x", __VA_ARGS__)
-#define ASSERT_HEX_WITHIN(...) ASSERT_XXX_WITHIN("0x%x", __VA_ARGS__)
-
-//--------------------------------------------------------------------+
-// Bin Assert
-//--------------------------------------------------------------------+
-#define BIN8_PRINTF_PATTERN "%d%d%d%d%d%d%d%d"
-#define BIN8_PRINTF_CONVERT(byte)  \
-  ((byte) & 0x80 ? 1 : 0), \
-  ((byte) & 0x40 ? 1 : 0), \
-  ((byte) & 0x20 ? 1 : 0), \
-  ((byte) & 0x10 ? 1 : 0), \
-  ((byte) & 0x08 ? 1 : 0), \
-  ((byte) & 0x04 ? 1 : 0), \
-  ((byte) & 0x02 ? 1 : 0), \
-  ((byte) & 0x01 ? 1 : 0)
-
-#define ASSERT_BIN8(...)        ASSERT_BIN8_EQUAL(__VA_ARGS__)
-#define ASSERT_BIN8_EQUAL(expected, actual, error)\
-    ASSERT_DEFINE(\
-                  uint8_t exp = (expected); uint8_t act = (actual),\
-                  exp==act,\
-                  error,\
-                  "expected " BIN8_PRINTF_PATTERN ", actual " BIN8_PRINTF_PATTERN, BIN8_PRINTF_CONVERT(exp), BIN8_PRINTF_CONVERT(act) )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ASSERTION_H_ */
-
-/** @} */
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/common/binary.h
--- a/nRF51822/common/binary.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,96 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     binary.h
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, K. Townsend (microBuilder.eu)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-/**************************************************************************/
-
-/** \ingroup TBD
- *  \defgroup TBD
- *  \brief TBD
- *
- *  @{
- */
-
-#ifndef _BINARY_H_
-#define _BINARY_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/// n-th Bit
-#define BIT(n) (1 << (n))
-
-/// set n-th bit of x to 1
-#define BIT_SET(x, n) ( (x) | BIT(n) )
-
-/// clear n-th bit of x
-#define BIT_CLR(x, n) ( (x) & (~BIT(n)) )
-
-/// test n-th bit of x
-#define BIT_TEST(x, n) ( (x) & BIT(n) )
-
-#if defined(__GNUC__) && !defined(__CC_ARM) // keil does not support binary format
-
-#define BIN8(x)               ((uint8_t)  (0b##x))
-#define BIN16(b1, b2)         ((uint16_t) (0b##b1##b2))
-#define BIN32(b1, b2, b3, b4) ((uint32_t) (0b##b1##b2##b3##b4))
-
-#else
-
-//  internal macro of B8, B16, B32
-#define _B8__(x) (((x&0x0000000FUL)?1:0) \
-                +((x&0x000000F0UL)?2:0) \
-                +((x&0x00000F00UL)?4:0) \
-                +((x&0x0000F000UL)?8:0) \
-                +((x&0x000F0000UL)?16:0) \
-                +((x&0x00F00000UL)?32:0) \
-                +((x&0x0F000000UL)?64:0) \
-                +((x&0xF0000000UL)?128:0))
-
-#define BIN8(d) ((uint8_t) _B8__(0x##d##UL))
-#define BIN16(dmsb,dlsb) (((uint16_t)BIN8(dmsb)<<8) + BIN8(dlsb))
-#define BIN32(dmsb,db2,db3,dlsb) \
-            (((uint32_t)BIN8(dmsb)<<24) \
-            + ((uint32_t)BIN8(db2)<<16) \
-            + ((uint32_t)BIN8(db3)<<8) \
-            + BIN8(dlsb))
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _BINARY_H_ */
-
-/** @} */
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/common/ble_error.h
--- a/nRF51822/common/ble_error.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,151 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     ble_error.h
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, K. Townsend (microBuilder.eu)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-/**************************************************************************/
-
-/** \file
- *  \brief Error Header
- *
- *  \note TBD
- */
-
-/** \ingroup Group_Common
- *  \defgroup Group_Error Error Codes
- *  @{
- */
-
-#ifndef _BLE_ERROR_H_
-#define _BLE_ERROR_H_
-
-#include "projectconfig.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-typedef enum 
-{
-  /*=======================================================================
-    NORDIC GLOBAL ERRORS                                   0x0000 .. 0x00FF
-    -----------------------------------------------------------------------
-    Errors mapped from nrf_error.h
-    -----------------------------------------------------------------------*/
-    ERROR_NONE                                    = 0x0000 , ///< Successful command
-    ERROR_SVC_HANDLER_MISSING                     = 0x0001 , ///< SVC handler is missing
-    ERROR_SOFTDEVICE_NOT_ENABLED                  = 0x0002 , ///< SoftDevice has not been enabled
-    ERROR_INTERNAL                                = 0x0003 , ///< Internal Error
-    ERROR_NO_MEM                                  = 0x0004 , ///< No Memory for operation
-    ERROR_NOT_FOUND                               = 0x0005 , ///< Not found
-    ERROR_NOT_SUPPORTED                           = 0x0006 , ///< Not supported
-    ERROR_INVALID_PARAM                           = 0x0007 , ///< Invalid Parameter
-    ERROR_INVALID_STATE                           = 0x0008 , ///< Invalid state, operation disallowed in this state
-    ERROR_INVALID_LENGTH                          = 0x0009 , ///< Invalid Length
-    ERROR_INVALID_FLAGS                           = 0x000A , ///< Invalid Flags
-    ERROR_INVALID_DATA                            = 0x000B , ///< Invalid Data
-    ERROR_DATA_SIZE                               = 0x000C , ///< Data size exceeds limit
-    ERROR_TIMEOUT                                 = 0x000D , ///< Operation timed out
-    ERROR_NULL                                    = 0x000E , ///< Null Pointer
-    ERROR_FORBIDDEN                               = 0x000F , ///< Forbidden Operation
-    ERROR_INVALID_ADDR                            = 0x0010 , ///< Bad Memory Address
-    ERROR_BUSY                                    = 0x0011 , ///< Busy
-  /*=======================================================================*/
-
-  ERROR_INVALIDPARAMETER                        = 0x0100 , /**< An invalid parameter value was provided */
-  ERROR_I2C_XFER_FAILED                         = 0x0101 , /**< an failed attempt to make I2C transfer */
-
-  /*=======================================================================
-    SIMPLE BINARY PROTOCOL ERRORS                          0x0120 .. 0x013F
-    -----------------------------------------------------------------------
-    Errors relating to the simple binary protocol (/src//protocol)
-    -----------------------------------------------------------------------*/
-    ERROR_PROT_INVALIDMSGTYPE                   = 0x121,  /**< Unexpected msg type encountered */
-    ERROR_PROT_INVALIDCOMMANDID                 = 0x122,  /**< Unknown or out of range command ID */
-    ERROR_PROT_INVALIDPAYLOAD                   = 0x123,  /**< Message payload has a problem (invalid len, etc.) */
-  /*=======================================================================*/
-
-  //------------- based on Nordic SDM nrf_error_sdm.h -------------//
-  ERROR_SDM_LFCLK_SOURCE_UNKNOWN                = 0x1000 , ///< Unknown lfclk source
-  ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION   = 0x1001 , ///< Incorrect interrupt configuration (can be caused by using illegal priority levels, or having enabled SoftDevice interrupts)
-  ERROR_SDM_INCORRECT_CLENR0                    = 0x1002 , ///< Incorrect CLENR0 (can be caused by erronous SoftDevice flashing)
-
-  //------------- based on Nordic SOC nrf_error_soc.h -------------//
-  /* Mutex Errors */
-  ERROR_SOC_MUTEX_ALREADY_TAKEN                 = 0x2000 ,  ///< Mutex already taken
-
-  /* NVIC errors */
-  ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE        = 0x2001 ,  ///< NVIC interrupt not available
-  ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED = 0x2002 ,  ///< NVIC interrupt priority not allowed
-  ERROR_SOC_NVIC_SHOULD_NOT_RETURN              = 0x2003 ,  ///< NVIC should not return
-
-  /* Power errors */
-  ERROR_SOC_POWER_MODE_UNKNOWN                  = 0x2004 ,  ///< Power mode unknown
-  ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN         = 0x2005 ,  ///< Power POF threshold unknown
-  ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN         = 0x2006 ,  ///< Power off should not return
-
-  /* Rand errors */
-  ERROR_SOC_RAND_NOT_ENOUGH_VALUES              = 0x2007 ,  ///< RAND not enough values
-
-  /* PPI errors */
-  ERROR_SOC_PPI_INVALID_CHANNEL                 = 0x2008 ,  ///< Invalid PPI Channel
-  ERROR_SOC_PPI_INVALID_GROUP                   = 0x2009 ,  ///< Invalid PPI Group
-
-  //------------- based on Nordic STK (ble) ble_err.h -------------//
-  ERROR_BLE_INVALID_CONN_HANDLE                 = 0x3001 , /**< Invalid connection handle. */
-  ERROR_BLE_INVALID_ATTR_HANDLE                 = 0x3002 , /**< Invalid attribute handle. */
-  ERROR_BLE_NO_TX_BUFFERS                       = 0x3003 , /**< Buffer capacity exceeded. */
-
-  // L2CAP
-  ERROR_BLE_L2CAP_CID_IN_USE                    = 0x3100 , /**< CID already in use. */
-
-  // GAP
-  ERROR_BLE_GAP_UUID_LIST_MISMATCH              = 0x3200 , /**< UUID list does not contain an integral number of UUIDs. */
-  ERROR_BLE_GAP_DISCOVERABLE_WITH_WHITELIST     = 0x3201 , /**< Use of Whitelist not permitted with discoverable advertising. */
-  ERROR_BLE_GAP_INVALID_BLE_ADDR                = 0x3202 , /**< The upper two bits of the address do not correspond to the specified address type. */
-
-  // GATTC
-  ERROR_BLE_GATTC_PROC_NOT_PERMITTED            = 0x3300 ,
-
-  // GATTS
-  ERROR_BLEGATTS_INVALID_ATTR_TYPE              = 0x3400 , /**< Invalid attribute type. */
-  ERROR_BLEGATTS_SYS_ATTR_MISSING               = 0x3401 , /**< System Attributes missing. */
-
-}error_t;
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _BLE_ERROR_H_ */
-
- /**  @} */
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/common/common.h
--- a/nRF51822/common/common.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,236 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     common.h
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, K. Townsend (microBuilder.eu)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-/**************************************************************************/
-
-/** \defgroup Group_Common Common Files
- * @{
- *
- *  \defgroup Group_CommonH common.h
- *
- *  @{
- */
-
-#ifndef _COMMON_H_
-#define _COMMON_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-//--------------------------------------------------------------------+
-// INCLUDES
-//--------------------------------------------------------------------+
-
-//------------- Standard Header -------------//
-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <string.h>
-#include <stdio.h>
-
-//------------- General Header -------------//
-#include "projectconfig.h"
-#include "compiler.h"
-#include "assertion.h"
-#include "binary.h"
-#include "ble_error.h"
-
-//------------- MCU header -------------//
-//#include "nrf.h"
-
-//--------------------------------------------------------------------+
-// TYPEDEFS
-//--------------------------------------------------------------------+
-typedef unsigned char byte_t;
-typedef float  float32_t;
-typedef double float64_t;
-
-//--------------------------------------------------------------------+
-// MACROS
-//--------------------------------------------------------------------+
-#define STRING_(x)  #x                             // stringify without expand
-#define XSTRING_(x) STRING_(x)                     // expand then stringify
-#define STRING_CONCAT_(a, b) a##b                  // concat without expand
-#define XSTRING_CONCAT_(a, b) STRING_CONCAT_(a, b) // expand then concat
-
-#define U16_HIGH_U8(u16) ((uint8_t) (((u16) >> 8) & 0x00ff))
-#define U16_LOW_U8(u16)  ((uint8_t) ((u16)       & 0x00ff))
-#define U16_TO_U8S_BE(u16)  U16_HIGH_U8(u16), U16_LOW_U8(u16)
-#define U16_TO_U8S_LE(u16)  U16_LOW_U8(u16), U16_HIGH_U8(u16)
-
-#define U32_B1_U8(u32) ((uint8_t) (((u32) >> 24) & 0x000000ff)) // MSB
-#define U32_B2_U8(u32) ((uint8_t) (((u32) >> 16) & 0x000000ff))
-#define U32_B3_U8(u32) ((uint8_t) (((u32) >>  8) & 0x000000ff))
-#define U32_B4_U8(u32) ((uint8_t) ((u32)        & 0x000000ff)) // LSB
-
-#define U32_TO_U8S_BE(u32) U32_B1_U8(u32), U32_B2_U8(u32), U32_B3_U8(u32), U32_B4_U8(u32)
-#define U32_TO_U8S_LE(u32) U32_B4_U8(u32), U32_B3_U8(u32), U32_B2_U8(u32), U32_B1_U8(u32)
-
-//--------------------------------------------------------------------+
-// INLINE FUNCTION
-//--------------------------------------------------------------------+
-#define memclr_(buffer, size)  memset(buffer, 0, size)
-
-//------------- Conversion -------------//
-/// form an uint32_t from 4 x uint8_t
-static inline uint32_t u32_from_u8(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline uint32_t u32_from_u8(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4)
-{
-  return (b1 << 24) + (b2 << 16) + (b3 << 8) + b4;
-}
-
-static inline uint8_t u16_high_u8(uint16_t u16) ATTR_CONST ATTR_ALWAYS_INLINE;
-static inline uint8_t u16_high_u8(uint16_t u16)
-{
-  return (uint8_t) ((u16 >> 8) & 0x00ff);
-}
-
-static inline uint8_t u16_low_u8(uint16_t u16) ATTR_CONST ATTR_ALWAYS_INLINE;
-static inline uint8_t u16_low_u8(uint16_t u16)
-{
-  return (uint8_t) (u16 & 0x00ff);
-}
-
-//------------- Min -------------//
-static inline uint8_t min8_of(uint8_t x, uint8_t y) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline uint8_t min8_of(uint8_t x, uint8_t y)
-{
-  return (x < y) ? x : y;
-}
-
-static inline uint16_t min16_of(uint16_t x, uint16_t y) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline uint16_t min16_of(uint16_t x, uint16_t y)
-{
-  return (x < y) ? x : y;
-}
-
-static inline uint32_t min32_of(uint32_t x, uint32_t y) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline uint32_t min32_of(uint32_t x, uint32_t y)
-{
-  return (x < y) ? x : y;
-}
-
-//------------- Max -------------//
-static inline uint32_t max32_of(uint32_t x, uint32_t y) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline uint32_t max32_of(uint32_t x, uint32_t y)
-{
-  return (x > y) ? x : y;
-}
-
-//------------- Align -------------//
-static inline uint32_t align32 (uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline uint32_t align32 (uint32_t value)
-{
-	return (value & 0xFFFFFFE0UL);
-}
-
-static inline uint32_t align16 (uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline uint32_t align16 (uint32_t value)
-{
-	return (value & 0xFFFFFFF0UL);
-}
-
-static inline uint32_t align_n (uint32_t alignment, uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline uint32_t align_n (uint32_t alignment, uint32_t value)
-{
-	return value & (~(alignment-1));
-}
-
-static inline uint32_t align4k (uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline uint32_t align4k (uint32_t value)
-{
-	return (value & 0xFFFFF000UL);
-}
-
-static inline uint32_t offset4k(uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline uint32_t offset4k(uint32_t value)
-{
-	return (value & 0xFFFUL);
-}
-
-//------------- Mathematics -------------//
-/// inclusive range checking
-static inline bool is_in_range(uint32_t lower, uint32_t value, uint32_t upper) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline bool is_in_range(uint32_t lower, uint32_t value, uint32_t upper)
-{
-  return (lower <= value) && (value <= upper);
-}
-
-/// exclusive range checking
-static inline bool is_in_range_exclusive(uint32_t lower, uint32_t value, uint32_t upper) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline bool is_in_range_exclusive(uint32_t lower, uint32_t value, uint32_t upper)
-{
-  return (lower < value) && (value < upper);
-}
-
-static inline uint8_t log2_of(uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline uint8_t log2_of(uint32_t value)
-{
-  uint8_t result = 0; // log2 of a value is its MSB's position
-
-  while (value >>= 1)
-  {
-    result++;
-  }
-  return result;
-}
-
-// return the number of set bits in value
-static inline uint8_t cardinality_of(uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
-static inline uint8_t cardinality_of(uint32_t value)
-{
-  // Brian Kernighan's method goes through as many iterations as there are set bits. So if we have a 32-bit word with only
-  // the high bit set, then it will only go once through the loop
-  // Published in 1988, the C Programming Language 2nd Ed. (by Brian W. Kernighan and Dennis M. Ritchie)
-  // mentions this in exercise 2-9. On April 19, 2006 Don Knuth pointed out to me that this method
-  // "was first published by Peter Wegner in CACM 3 (1960), 322. (Also discovered independently by Derrick Lehmer and
-  // published in 1964 in a book edited by Beckenbach.)"
-  uint8_t count;
-  for (count = 0; value; count++)
-  {
-    value &= value - 1; // clear the least significant bit set
-  }
-
-  return count;
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _COMMON_H_ */
-
-/**  @} */
-/**  @} */
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/common/compiler.h
--- a/nRF51822/common/compiler.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,152 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     compiler.h
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, K. Townsend (microBuilder.eu)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-/**************************************************************************/
-
-/** \file
- *  \brief GCC Header
- */
-
-/** \ingroup Group_Compiler
- *  \defgroup Group_GCC GNU GCC
- *  @{
- */
-
-#ifndef _COMPILER_GCC_H_
-#define _COMPILER_GCC_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "projectconfig.h"
-
-//#ifndef __GNUC__
-//  #define ATTR_ALWAYS_INLINE
-//  #define ATTR_CONST
-//#else
-
-#ifdef _TEST_
-  #define ATTR_ALWAYS_INLINE
-  #define STATIC_
-  #define INLINE_
-#else
-  #define STATIC_ static
-  #define INLINE_ inline
-
-  #if CFG_DEBUG == 3
-    #define ATTR_ALWAYS_INLINE  // no inline for debug = 3
-  #endif
-#endif
-
-#define ALIGN_OF(x)                __alignof__(x)
-
-/// Normally, the compiler places the objects it generates in sections like data or bss & function in text. Sometimes, however, you need additional sections, or you need certain particular variables to appear in special sections, for example to map to special hardware. The section attribute specifies that a variable (or function) lives in a particular section
-#define ATTR_SECTION(section)      __attribute__ ((#section))
-
-/// If this attribute is used on a function declaration and a call to such a function is not eliminated through dead code elimination or other optimizations, an error that includes message is diagnosed. This is useful for compile-time checking
-#define ATTR_ERROR(Message)        __attribute__ ((error(Message)))
-
-/// If this attribute is used on a function declaration and a call to such a function is not eliminated through dead code elimination or other optimizations, a warning that includes message is diagnosed. This is useful for compile-time checking
-#define ATTR_WARNING(Message)      __attribute__ ((warning(Message)))
-
-/**
- *  \defgroup Group_VariableAttr Variable Attributes
- *  @{
- */
-
-/// This attribute specifies a minimum alignment for the variable or structure field, measured in bytes
-#define ATTR_ALIGNED(Bytes)        __attribute__ ((aligned(Bytes)))
-
-/// The packed attribute specifies that a variable or structure field should have the smallest possible alignment—one byte for a variable, and one bit for a field, unless you specify a larger value with the aligned attribute
-#define ATTR_PACKED                __attribute__ ((packed))
-
-#define ATTR_PREPACKED
-
-#define ATTR_PACKED_STRUCT(x)    x __attribute__ ((packed))
-/** @} */
-
-/**
- *  \defgroup Group_FuncAttr Function Attributes
- *  @{
- */
-
-#ifndef ATTR_ALWAYS_INLINE
-/// Generally, functions are not inlined unless optimization is specified. For functions declared inline, this attribute inlines the function even if no optimization level is specified
-#define ATTR_ALWAYS_INLINE         __attribute__ ((always_inline))
-#endif
-
-/// The nonnull attribute specifies that some function parameters should be non-null pointers. f the compiler determines that a null pointer is passed in an argument slot marked as non-null, and the -Wnonnull option is enabled, a warning is issued. All pointer arguments are marked as non-null
-#define ATTR_NON_NULL              __attribute__ ((nonull))
-
-/// Many functions have no effects except the return value and their return value depends only on the parameters and/or global variables. Such a function can be subject to common subexpression elimination and loop optimization just as an arithmetic operator would be. These functions should be declared with the attribute pure
-#define ATTR_PURE                  __attribute__ ((pure))
-
-/// Many functions do not examine any values except their arguments, and have no effects except the return value. Basically this is just slightly more strict class than the pure attribute below, since function is not allowed to read global memory.
-/// Note that a function that has pointer arguments and examines the data pointed to must not be declared const. Likewise, a function that calls a non-const function usually must not be const. It does not make sense for a const function to return void
-#define ATTR_CONST                 __attribute__ ((const))
-
-/// The deprecated attribute results in a warning if the function is used anywhere in the source file. This is useful when identifying functions that are expected to be removed in a future version of a program. The warning also includes the location of the declaration of the deprecated function, to enable users to easily find further information about why the function is deprecated, or what they should do instead. Note that the warnings only occurs for uses
-#define ATTR_DEPRECATED            __attribute__ ((deprecated))
-
-/// Same as the deprecated attribute with optional message in the warning
-#define ATTR_DEPRECATED_MESS(mess) __attribute__ ((deprecated(mess)))
-
-/// The weak attribute causes the declaration to be emitted as a weak symbol rather than a global. This is primarily useful in defining library functions that can be overridden in user code
-#define ATTR_WEAK                  __attribute__ ((weak))
-
-/// The alias attribute causes the declaration to be emitted as an alias for another symbol, which must be specified
-#define ATTR_ALIAS(func)           __attribute__ ((alias(#func)))
-
-/// The weakref attribute marks a declaration as a weak reference. It is equivalent with weak + alias attribute, but require function is static
-#define ATTR_WEAKREF(func)         __attribute__ ((weakref(#func)))
-
-/// The warn_unused_result attribute causes a warning to be emitted if a caller of the function with this attribute does not use its return value. This is useful for functions where not checking the result is either a security problem or always a bug
-#define ATTR_WARN_UNUSED_RESULT    __attribute__ ((warn_unused_result))
-
-/// This attribute, attached to a function, means that code must be emitted for the function even if it appears that the function is not referenced. This is useful, for example, when the function is referenced only in inline assembly.
-#define ATTR_USED                  __attribute__ ((used))
-
-/// This attribute, attached to a function, means that the function is meant to be possibly unused. GCC does not produce a warning for this function.
-#define ATTR_UNUSED                __attribute__ ((unused))
-
-/** @} */
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _COMPILER_GCC_H_ */
-
-/// @}
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nRF51822n.cpp
--- a/nRF51822/nRF51822n.cpp	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,123 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "mbed.h"
-#include "nRF51822n.h"
-#include "nrf_soc.h"
-
-#include "btle/btle.h"
-#include "nrf_delay.h"
-
-#include "softdevice_handler.h"
-
-/**
- * The singleton which represents the nRF51822 transport for the BLEDevice.
- */
-static nRF51822n deviceInstance;
-
-/**
- * BLE-API requires an implementation of the following function in order to
- * obtain its transport handle.
- */
-BLEDeviceInstanceBase *
-createBLEDeviceInstance(void)
-{
-    return (&deviceInstance);
-}
-
-nRF51822n::nRF51822n(void)
-{
-}
-
-nRF51822n::~nRF51822n(void)
-{
-}
-
-const char *nRF51822n::getVersion(void)
-{
-    static char versionString[10];
-    static bool versionFetched = false;
-
-    if (!versionFetched) {
-        ble_version_t version;
-        if (sd_ble_version_get(&version) == NRF_SUCCESS) {
-            snprintf(versionString, sizeof(versionString), "%u.%u", version.version_number, version.subversion_number);
-            versionFetched = true;
-        } else {
-            strncpy(versionString, "unknown", sizeof(versionString));
-        }
-    }
-
-    return versionString;
-}
-
-/* (Valid values are -40, -20, -16, -12, -8, -4, 0, 4) */
-ble_error_t nRF51822n::setTxPower(int8_t txPower)
-{
-    unsigned rc;
-    if ((rc = sd_ble_gap_tx_power_set(txPower)) != NRF_SUCCESS) {
-        switch (rc) {
-            case NRF_ERROR_BUSY:
-                return BLE_STACK_BUSY;
-            case NRF_ERROR_INVALID_PARAM:
-            default:
-                return BLE_ERROR_PARAM_OUT_OF_RANGE;
-        }
-    }
-
-    return BLE_ERROR_NONE;
-}
-
-void nRF51822n::getPermittedTxPowerValues(const int8_t **valueArrayPP, size_t *countP)
-{
-    static const int8_t permittedTxValues[] = {
-        -40, -30, -20, -16, -12, -8, -4, 0, 4
-    };
-
-    *valueArrayPP = permittedTxValues;
-    *countP = sizeof(permittedTxValues) / sizeof(int8_t);
-}
-
-ble_error_t nRF51822n::init(void)
-{
-    /* ToDo: Clear memory contents, reset the SD, etc. */
-    btle_init();
-
-    reset();
-
-    return BLE_ERROR_NONE;
-}
-
-ble_error_t nRF51822n::shutdown(void)
-{
-    return (softdevice_handler_sd_disable() == NRF_SUCCESS) ? BLE_ERROR_NONE : BLE_STACK_BUSY;
-}
-
-ble_error_t nRF51822n::reset(void)
-{
-    nrf_delay_us(500000);
-
-    /* Wait for the radio to come back up */
-    nrf_delay_us(1000000);
-
-    return BLE_ERROR_NONE;
-}
-
-void
-nRF51822n::waitForEvent(void)
-{
-    sd_app_evt_wait();
-}
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nRF51822n.h
--- a/nRF51822/nRF51822n.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,50 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __NRF51822_H__
-#define __NRF51822_H__
-
-#include "mbed.h"
-#include "blecommon.h"
-#include "BLEDevice.h"
-#include "nRF51Gap.h"
-#include "nRF51GattServer.h"
-
-class nRF51822n : public BLEDeviceInstanceBase
-{
-public:
-    nRF51822n(void);
-    virtual ~nRF51822n(void);
-
-    virtual const char *getVersion(void);
-
-    virtual Gap        &getGap()        {
-        return nRF51Gap::getInstance();
-    };
-    virtual GattServer &getGattServer() {
-        return nRF51GattServer::getInstance();
-    };
-
-    virtual ble_error_t setTxPower(int8_t txPower);
-    virtual void        getPermittedTxPowerValues(const int8_t **valueArrayPP, size_t *countP);
-
-    virtual ble_error_t init(void);
-    virtual ble_error_t shutdown(void);
-    virtual ble_error_t reset(void);
-    virtual void        waitForEvent(void);
-};
-
-#endif
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nRF51Gap.cpp
--- a/nRF51822/nRF51Gap.cpp	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,375 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "nRF51Gap.h"
-#include "mbed.h"
-
-#include "common/common.h"
-#include "ble_advdata.h"
-#include "ble_hci.h"
-
-/**************************************************************************/
-/*!
-    @brief  Sets the advertising parameters and payload for the device
-
-    @param[in]  params
-                Basic advertising details, including the advertising
-                delay, timeout and how the device should be advertised
-    @params[in] advData
-                The primary advertising data payload
-    @params[in] scanResponse
-                The optional Scan Response payload if the advertising
-                type is set to \ref GapAdvertisingParams::ADV_SCANNABLE_UNDIRECTED
-                in \ref GapAdveritinngParams
-
-    @returns    \ref ble_error_t
-
-    @retval     BLE_ERROR_NONE
-                Everything executed properly
-
-    @retval     BLE_ERROR_BUFFER_OVERFLOW
-                The proposed action would cause a buffer overflow.  All
-                advertising payloads must be <= 31 bytes, for example.
-
-    @retval     BLE_ERROR_NOT_IMPLEMENTED
-                A feature was requested that is not yet supported in the
-                nRF51 firmware or hardware.
-
-    @retval     BLE_ERROR_PARAM_OUT_OF_RANGE
-                One of the proposed values is outside the valid range.
-
-    @section EXAMPLE
-
-    @code
-
-    @endcode
-*/
-/**************************************************************************/
-ble_error_t nRF51Gap::setAdvertisingData(const GapAdvertisingData &advData, const GapAdvertisingData &scanResponse)
-{
-    /* Make sure we don't exceed the advertising payload length */
-    if (advData.getPayloadLen() > GAP_ADVERTISING_DATA_MAX_PAYLOAD) {
-        return BLE_ERROR_BUFFER_OVERFLOW;
-    }
-
-    /* Make sure we have a payload! */
-    if (advData.getPayloadLen() == 0) {
-        return BLE_ERROR_PARAM_OUT_OF_RANGE;
-    }
-
-    /* Check the scan response payload limits */
-    //if ((params.getAdvertisingType() == GapAdvertisingParams::ADV_SCANNABLE_UNDIRECTED))
-    //{
-    //    /* Check if we're within the upper limit */
-    //    if (advData.getPayloadLen() > GAP_ADVERTISING_DATA_MAX_PAYLOAD)
-    //    {
-    //        return BLE_ERROR_BUFFER_OVERFLOW;
-    //    }
-    //    /* Make sure we have a payload! */
-    //    if (advData.getPayloadLen() == 0)
-    //    {
-    //        return BLE_ERROR_PARAM_OUT_OF_RANGE;
-    //    }
-    //}
-
-    /* Send advertising data! */
-    ASSERT(ERROR_NONE ==
-           sd_ble_gap_adv_data_set(advData.getPayload(),
-                                   advData.getPayloadLen(),
-                                   scanResponse.getPayload(),
-                                   scanResponse.getPayloadLen()),
-           BLE_ERROR_PARAM_OUT_OF_RANGE);
-
-    /* Make sure the GAP Service appearance value is aligned with the
-     *appearance from GapAdvertisingData */
-    ASSERT(ERROR_NONE == sd_ble_gap_appearance_set(advData.getAppearance()),
-           BLE_ERROR_PARAM_OUT_OF_RANGE);
-
-    /* ToDo: Perform some checks on the payload, for example the Scan Response can't */
-    /* contains a flags AD type, etc. */
-
-    return BLE_ERROR_NONE;
-}
-
-/**************************************************************************/
-/*!
-    @brief  Starts the BLE HW, initialising any services that were
-            added before this function was called.
-
-    @note   All services must be added before calling this function!
-
-    @returns    ble_error_t
-
-    @retval     BLE_ERROR_NONE
-                Everything executed properly
-
-    @section EXAMPLE
-
-    @code
-
-    @endcode
-*/
-/**************************************************************************/
-ble_error_t nRF51Gap::startAdvertising(const GapAdvertisingParams &params)
-{
-    /* Make sure we support the advertising type */
-    if (params.getAdvertisingType() == GapAdvertisingParams::ADV_CONNECTABLE_DIRECTED) {
-        /* ToDo: This requires a propery security implementation, etc. */
-        return BLE_ERROR_NOT_IMPLEMENTED;
-    }
-
-    /* Check interval range */
-    if (params.getAdvertisingType() == GapAdvertisingParams::ADV_NON_CONNECTABLE_UNDIRECTED) {
-        /* Min delay is slightly longer for unconnectable devices */
-        if ((params.getInterval() < GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MIN_NONCON) ||
-            (params.getInterval() > GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MAX)) {
-            return BLE_ERROR_PARAM_OUT_OF_RANGE;
-        }
-    } else {
-        if ((params.getInterval() < GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MIN) ||
-            (params.getInterval() > GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MAX)) {
-            return BLE_ERROR_PARAM_OUT_OF_RANGE;
-        }
-    }
-
-    /* Check timeout is zero for Connectable Directed */
-    if ((params.getAdvertisingType() == GapAdvertisingParams::ADV_CONNECTABLE_DIRECTED) && (params.getTimeout() != 0)) {
-        /* Timeout must be 0 with this type, although we'll never get here */
-        /* since this isn't implemented yet anyway */
-        return BLE_ERROR_PARAM_OUT_OF_RANGE;
-    }
-
-    /* Check timeout for other advertising types */
-    if ((params.getAdvertisingType() != GapAdvertisingParams::ADV_CONNECTABLE_DIRECTED) &&
-        (params.getTimeout() > GapAdvertisingParams::GAP_ADV_PARAMS_TIMEOUT_MAX)) {
-        return BLE_ERROR_PARAM_OUT_OF_RANGE;
-    }
-
-    /* Start Advertising */
-    ble_gap_adv_params_t adv_para = {0};
-
-    adv_para.type        = params.getAdvertisingType();
-    adv_para.p_peer_addr = NULL;                         // Undirected advertisement
-    adv_para.fp          = BLE_GAP_ADV_FP_ANY;
-    adv_para.p_whitelist = NULL;
-    adv_para.interval    = params.getInterval();         // advertising interval (in units of 0.625 ms)
-    adv_para.timeout     = params.getTimeout();
-
-    ASSERT(ERROR_NONE == sd_ble_gap_adv_start(&adv_para), BLE_ERROR_PARAM_OUT_OF_RANGE);
-
-    state.advertising = 1;
-
-    return BLE_ERROR_NONE;
-}
-
-/**************************************************************************/
-/*!
-    @brief  Stops the BLE HW and disconnects from any devices
-
-    @returns    ble_error_t
-
-    @retval     BLE_ERROR_NONE
-                Everything executed properly
-
-    @section EXAMPLE
-
-    @code
-
-    @endcode
-*/
-/**************************************************************************/
-ble_error_t nRF51Gap::stopAdvertising(void)
-{
-    /* Stop Advertising */
-    ASSERT(ERROR_NONE == sd_ble_gap_adv_stop(), BLE_ERROR_PARAM_OUT_OF_RANGE);
-
-    state.advertising = 0;
-
-    return BLE_ERROR_NONE;
-}
-
-/**************************************************************************/
-/*!
-    @brief  Disconnects if we are connected to a central device
-
-    @returns    ble_error_t
-
-    @retval     BLE_ERROR_NONE
-                Everything executed properly
-
-    @section EXAMPLE
-
-    @code
-
-    @endcode
-*/
-/**************************************************************************/
-ble_error_t nRF51Gap::disconnect(DisconnectionReason_t reason)
-{
-    state.advertising = 0;
-    state.connected   = 0;
-
-    uint8_t code = BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION;
-    switch (reason) {
-        case REMOTE_USER_TERMINATED_CONNECTION:
-            code = BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION;
-            break;
-        case CONN_INTERVAL_UNACCEPTABLE:
-            code = BLE_HCI_CONN_INTERVAL_UNACCEPTABLE;
-            break;
-    }
-
-    /* Disconnect if we are connected to a central device */
-    ASSERT_INT(ERROR_NONE, sd_ble_gap_disconnect(m_connectionHandle, code), BLE_ERROR_PARAM_OUT_OF_RANGE);
-
-    return BLE_ERROR_NONE;
-}
-
-ble_error_t nRF51Gap::getPreferredConnectionParams(ConnectionParams_t *params)
-{
-    ASSERT_INT(NRF_SUCCESS,
-        sd_ble_gap_ppcp_get(reinterpret_cast<ble_gap_conn_params_t *>(params)),
-        BLE_ERROR_PARAM_OUT_OF_RANGE);
-
-    return BLE_ERROR_NONE;
-}
-
-ble_error_t nRF51Gap::setPreferredConnectionParams(const ConnectionParams_t *params)
-{
-    ASSERT_INT(NRF_SUCCESS,
-        sd_ble_gap_ppcp_set(reinterpret_cast<const ble_gap_conn_params_t *>(params)),
-        BLE_ERROR_PARAM_OUT_OF_RANGE);
-
-    return BLE_ERROR_NONE;
-}
-
-ble_error_t nRF51Gap::updateConnectionParams(Handle_t handle, const ConnectionParams_t *newParams)
-{
-    uint32_t rc;
-
-    rc = sd_ble_gap_conn_param_update(handle, reinterpret_cast<ble_gap_conn_params_t *>(const_cast<ConnectionParams_t*>(newParams)));
-    if (rc == NRF_SUCCESS) {
-        return BLE_ERROR_NONE;
-    } else {
-        return BLE_ERROR_PARAM_OUT_OF_RANGE;
-    }
-}
-
-/**************************************************************************/
-/*!
-    @brief  Sets the 16-bit connection handle
-*/
-/**************************************************************************/
-void nRF51Gap::setConnectionHandle(uint16_t con_handle)
-{
-    m_connectionHandle = con_handle;
-}
-
-/**************************************************************************/
-/*!
-    @brief  Gets the 16-bit connection handle
-*/
-/**************************************************************************/
-uint16_t nRF51Gap::getConnectionHandle(void)
-{
-    return m_connectionHandle;
-}
-
-/**************************************************************************/
-/*!
-    @brief      Sets the BLE device address
-
-    @returns    ble_error_t
-
-    @section EXAMPLE
-
-    @code
-
-    uint8_t device_address[6] = { 0xca, 0xfe, 0xf0, 0xf0, 0xf0, 0xf0 };
-    nrf.getGap().setAddress(Gap::ADDR_TYPE_RANDOM_STATIC, device_address);
-
-    @endcode
-*/
-/**************************************************************************/
-ble_error_t nRF51Gap::setAddress(addr_type_t type, const address_t address)
-{
-    if (type > ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE) {
-        return BLE_ERROR_PARAM_OUT_OF_RANGE;
-    }
-
-    ble_gap_addr_t dev_addr;
-    dev_addr.addr_type = type;
-    memcpy(dev_addr.addr, address, ADDR_LEN);
-
-    ASSERT_INT(ERROR_NONE, sd_ble_gap_address_set(BLE_GAP_ADDR_CYCLE_MODE_NONE, &dev_addr), BLE_ERROR_PARAM_OUT_OF_RANGE);
-
-    return BLE_ERROR_NONE;
-}
-
-ble_error_t nRF51Gap::getAddress(addr_type_t *typeP, address_t address)
-{
-    ble_gap_addr_t dev_addr;
-    if (sd_ble_gap_address_get(&dev_addr) != NRF_SUCCESS) {
-        return BLE_ERROR_PARAM_OUT_OF_RANGE;
-    }
-
-    if (typeP != NULL) {
-        *typeP = static_cast<addr_type_t>(dev_addr.addr_type);
-    }
-    if (address != NULL) {
-        memcpy(address, dev_addr.addr, ADDR_LEN);
-    }
-    return BLE_ERROR_NONE;
-}
-
-ble_error_t nRF51Gap::setDeviceName(const uint8_t *deviceName)
-{
-    ble_gap_conn_sec_mode_t sec_mode;
-    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); // no security is needed
-
-    if (sd_ble_gap_device_name_set(&sec_mode, deviceName, strlen((const char *)deviceName)) == NRF_SUCCESS) {
-        return BLE_ERROR_NONE;
-    } else {
-        return BLE_ERROR_PARAM_OUT_OF_RANGE;
-    }
-}
-
-ble_error_t nRF51Gap::getDeviceName(uint8_t *deviceName, unsigned *lengthP)
-{
-    if (sd_ble_gap_device_name_get(deviceName, (uint16_t *)lengthP) == NRF_SUCCESS) {
-        return BLE_ERROR_NONE;
-    } else {
-        return BLE_ERROR_PARAM_OUT_OF_RANGE;
-    }
-}
-
-ble_error_t nRF51Gap::setAppearance(uint16_t appearance)
-{
-    if (sd_ble_gap_appearance_set(appearance) == NRF_SUCCESS) {
-        return BLE_ERROR_NONE;
-    } else {
-        return BLE_ERROR_PARAM_OUT_OF_RANGE;
-    }
-}
-
-ble_error_t nRF51Gap::getAppearance(uint16_t *appearanceP)
-{
-    if (sd_ble_gap_appearance_get(appearanceP)) {
-        return BLE_ERROR_NONE;
-    } else {
-        return BLE_ERROR_PARAM_OUT_OF_RANGE;
-    }
-}
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nRF51Gap.h
--- a/nRF51822/nRF51Gap.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,84 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __NRF51822_GAP_H__
-#define __NRF51822_GAP_H__
-
-#include "mbed.h"
-#include "blecommon.h"
-#include "ble.h"
-#include "GapAdvertisingParams.h"
-#include "GapAdvertisingData.h"
-#include "public/Gap.h"
-
-#include "nrf_soc.h"
-#include "ble_radio_notification.h"
-
-/**************************************************************************/
-/*!
-    \brief
-
-*/
-/**************************************************************************/
-class nRF51Gap : public Gap
-{
-public:
-    static nRF51Gap &getInstance() {
-        static nRF51Gap m_instance;
-        return m_instance;
-    }
-
-    /* Functions that must be implemented from Gap */
-    virtual ble_error_t setAddress(addr_type_t  type,  const address_t address);
-    virtual ble_error_t getAddress(addr_type_t *typeP, address_t address);
-    virtual ble_error_t setAdvertisingData(const GapAdvertisingData &, const GapAdvertisingData &);
-
-    virtual uint16_t    getMinAdvertisingInterval(void) const {return GAP_DURATION_UNITS_TO_MS(BLE_GAP_ADV_INTERVAL_MIN);}
-    virtual uint16_t    getMinNonConnectableAdvertisingInterval(void) const {return GAP_DURATION_UNITS_TO_MS(BLE_GAP_ADV_NONCON_INTERVAL_MIN);}
-    virtual uint16_t    getMaxAdvertisingInterval(void) const {return GAP_DURATION_UNITS_TO_MS(BLE_GAP_ADV_INTERVAL_MAX);}
-
-    virtual ble_error_t startAdvertising(const GapAdvertisingParams &);
-    virtual ble_error_t stopAdvertising(void);
-    virtual ble_error_t disconnect(DisconnectionReason_t reason);
-
-    virtual ble_error_t setDeviceName(const uint8_t *deviceName);
-    virtual ble_error_t getDeviceName(uint8_t *deviceName, unsigned *lengthP);
-    virtual ble_error_t setAppearance(uint16_t appearance);
-    virtual ble_error_t getAppearance(uint16_t *appearanceP);
-
-    void     setConnectionHandle(uint16_t con_handle);
-    uint16_t getConnectionHandle(void);
-
-    virtual ble_error_t getPreferredConnectionParams(ConnectionParams_t *params);
-    virtual ble_error_t setPreferredConnectionParams(const ConnectionParams_t *params);
-    virtual ble_error_t updateConnectionParams(Handle_t handle, const ConnectionParams_t *params);
-
-    virtual void setOnRadioNotification(RadioNotificationEventCallback_t callback) {
-        Gap::setOnRadioNotification(callback);
-        ble_radio_notification_init(NRF_APP_PRIORITY_HIGH, NRF_RADIO_NOTIFICATION_DISTANCE_800US, onRadioNotification);
-    }
-
-private:
-    uint16_t m_connectionHandle;
-    nRF51Gap() {
-        m_connectionHandle = BLE_CONN_HANDLE_INVALID;
-    }
-
-    nRF51Gap(nRF51Gap const &);
-    void operator=(nRF51Gap const &);
-};
-
-#endif // ifndef __NRF51822_GAP_H__
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nRF51GattServer.cpp
--- a/nRF51822/nRF51GattServer.cpp	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,400 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "nRF51GattServer.h"
-#include "mbed.h"
-
-#include "common/common.h"
-#include "btle/custom/custom_helper.h"
-
-#include "nRF51Gap.h"
-
-/**************************************************************************/
-/*!
-    @brief  Adds a new service to the GATT table on the peripheral
-
-    @returns    ble_error_t
-
-    @retval     BLE_ERROR_NONE
-                Everything executed properly
-
-    @section EXAMPLE
-
-    @code
-
-    @endcode
-*/
-/**************************************************************************/
-ble_error_t nRF51GattServer::addService(GattService &service)
-{
-    /* ToDo: Make sure we don't overflow the array, etc. */
-    /* ToDo: Make sure this service UUID doesn't already exist (?) */
-    /* ToDo: Basic validation */
-
-    /* Add the service to the nRF51 */
-    ble_uuid_t nordicUUID;
-    nordicUUID = custom_convert_to_nordic_uuid(service.getUUID());
-
-    uint16_t serviceHandle;
-    ASSERT( ERROR_NONE ==
-            sd_ble_gatts_service_add(BLE_GATTS_SRVC_TYPE_PRIMARY,
-                                     &nordicUUID,
-                                     &serviceHandle),
-            BLE_ERROR_PARAM_OUT_OF_RANGE );
-    service.setHandle(serviceHandle);
-
-    /* Add characteristics to the service */
-    for (uint8_t i = 0; i < service.getCharacteristicCount(); i++) {
-        GattCharacteristic *p_char = service.getCharacteristic(i);
-
-        /* Skip any incompletely defined, read-only characteristics. */
-        if ((p_char->getValueAttribute().getValuePtr() == NULL) &&
-            (p_char->getValueAttribute().getInitialLength() == 0) &&
-            (p_char->getProperties() == GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_READ)) {
-            continue;
-        }
-
-        nordicUUID = custom_convert_to_nordic_uuid(p_char->getValueAttribute().getUUID());
-
-        ASSERT ( ERROR_NONE ==
-                 custom_add_in_characteristic(BLE_GATT_HANDLE_INVALID,
-                                              &nordicUUID,
-                                              p_char->getProperties(),
-                                              p_char->getValueAttribute().getValuePtr(),
-                                              p_char->getValueAttribute().getInitialLength(),
-                                              p_char->getValueAttribute().getMaxLength(),
-                                              p_char->isReadAuthorizationEnabled(),
-                                              p_char->isWriteAuthorizationEnabled(),
-                                              &nrfCharacteristicHandles[characteristicCount]),
-                 BLE_ERROR_PARAM_OUT_OF_RANGE );
-
-        /* Update the characteristic handle */
-        uint16_t charHandle = characteristicCount;
-        p_characteristics[characteristicCount++] = p_char;
-
-        p_char->getValueAttribute().setHandle(charHandle);
-
-        /* Add optional descriptors if any */
-        /* ToDo: Make sure we don't overflow the array */
-        for (uint8_t j = 0; j < p_char->getDescriptorCount(); j++) {
-             GattAttribute *p_desc = p_char->getDescriptor(j);
-
-             nordicUUID = custom_convert_to_nordic_uuid(p_desc->getUUID());
-
-             ASSERT ( ERROR_NONE ==
-                      custom_add_in_descriptor(BLE_GATT_HANDLE_INVALID,
-                                               &nordicUUID,
-                                               p_desc->getValuePtr(),
-                                               p_desc->getInitialLength(),
-                                               p_desc->getMaxLength(),
-                                               &nrfDescriptorHandles[descriptorCount]),
-                 BLE_ERROR_PARAM_OUT_OF_RANGE );
-
-            uint16_t descHandle = descriptorCount;
-            p_descriptors[descriptorCount++] = p_desc;
-            p_desc->setHandle(descHandle);
-        }
-    }
-
-    serviceCount++;
-
-    return BLE_ERROR_NONE;
-}
-
-/**************************************************************************/
-/*!
-    @brief  Reads the value of a characteristic, based on the service
-            and characteristic index fields
-
-    @param[in]  charHandle
-                The handle of the GattCharacteristic to read from
-    @param[in]  buffer
-                Buffer to hold the the characteristic's value
-                (raw byte array in LSB format)
-    @param[in]  len
-                The number of bytes read into the buffer
-
-    @returns    ble_error_t
-
-    @retval     BLE_ERROR_NONE
-                Everything executed properly
-
-    @section EXAMPLE
-
-    @code
-
-    @endcode
-*/
-/**************************************************************************/
-ble_error_t nRF51GattServer::readValue(GattAttribute::Handle_t charHandle, uint8_t buffer[], uint16_t *const lengthP)
-{
-    ASSERT( ERROR_NONE ==
-            sd_ble_gatts_value_get(nrfCharacteristicHandles[charHandle].value_handle, 0, lengthP, buffer),
-            BLE_ERROR_PARAM_OUT_OF_RANGE);
-
-    return BLE_ERROR_NONE;
-}
-
-/**************************************************************************/
-/*!
-    @brief  Updates the value of a characteristic, based on the service
-            and characteristic index fields
-
-    @param[in]  charHandle
-                The handle of the GattCharacteristic to write to
-    @param[in]  buffer
-                Data to use when updating the characteristic's value
-                (raw byte array in LSB format)
-    @param[in]  len
-                The number of bytes in buffer
-
-    @returns    ble_error_t
-
-    @retval     BLE_ERROR_NONE
-                Everything executed properly
-
-    @section EXAMPLE
-
-    @code
-
-    @endcode
-*/
-/**************************************************************************/
-ble_error_t nRF51GattServer::updateValue(GattAttribute::Handle_t charHandle, const uint8_t buffer[], uint16_t len, bool localOnly)
-{
-    uint16_t gapConnectionHandle = nRF51Gap::getInstance().getConnectionHandle();
-    ble_error_t returnValue = BLE_ERROR_NONE;
-
-    if (localOnly) {
-        /* Only update locally regardless of notify/indicate */
-        ASSERT_INT( ERROR_NONE,
-                    sd_ble_gatts_value_set(nrfCharacteristicHandles[charHandle].value_handle, 0, &len, buffer),
-                    BLE_ERROR_PARAM_OUT_OF_RANGE );
-		return BLE_ERROR_NONE;
-    }
-
-    if ((p_characteristics[charHandle]->getProperties() &
-         (GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_INDICATE |
-          GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY)) &&
-        (gapConnectionHandle != BLE_CONN_HANDLE_INVALID)) {
-        /* HVX update for the characteristic value */
-        ble_gatts_hvx_params_t hvx_params;
-
-        hvx_params.handle = nrfCharacteristicHandles[charHandle].value_handle;
-        hvx_params.type   =
-            (p_characteristics[charHandle]->getProperties() &
-             GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY)  ?
-            BLE_GATT_HVX_NOTIFICATION : BLE_GATT_HVX_INDICATION;
-        hvx_params.offset = 0;
-        hvx_params.p_data = const_cast<uint8_t *>(buffer);
-        hvx_params.p_len  = &len;
-
-        error_t error = (error_t) sd_ble_gatts_hvx(gapConnectionHandle, &hvx_params);
-
-        /* ERROR_INVALID_STATE, ERROR_BUSY, ERROR_GATTS_SYS_ATTR_MISSING and
-         *ERROR_NO_TX_BUFFERS the ATT table has been updated. */
-        if ((error != ERROR_NONE) && (error != ERROR_INVALID_STATE) &&
-                (error != ERROR_BLE_NO_TX_BUFFERS) && (error != ERROR_BUSY) &&
-                (error != ERROR_BLEGATTS_SYS_ATTR_MISSING)) {
-            ASSERT_INT( ERROR_NONE,
-                        sd_ble_gatts_value_set(nrfCharacteristicHandles[charHandle].value_handle, 0, &len, buffer),
-                        BLE_ERROR_PARAM_OUT_OF_RANGE );
-        }
-
-        /*  Notifications consume application buffers. The return value can
-            be used for resending notifications.
-        */
-        if (error != ERROR_NONE) {
-            returnValue = BLE_STACK_BUSY;
-        }
-    } else {
-        ASSERT_INT( ERROR_NONE,
-                    sd_ble_gatts_value_set(nrfCharacteristicHandles[charHandle].value_handle, 0, &len, buffer),
-                    BLE_ERROR_PARAM_OUT_OF_RANGE );
-    }
-
-    return returnValue;
-}
-
-/**************************************************************************/
-/*!
-    @brief  Callback handler for events getting pushed up from the SD
-*/
-/**************************************************************************/
-void nRF51GattServer::hwCallback(ble_evt_t *p_ble_evt)
-{
-    uint16_t                       handle_value;
-    GattServerEvents::gattEvent_t  eventType;
-    const ble_gatts_evt_t         *gattsEventP = &p_ble_evt->evt.gatts_evt;
-
-    switch (p_ble_evt->header.evt_id) {
-        case BLE_GATTS_EVT_WRITE:
-            /* There are 2 use case here: Values being updated & CCCD (indicate/notify) enabled */
-
-            /* 1.) Handle CCCD changes */
-            handle_value = gattsEventP->params.write.handle;
-            for (uint8_t i = 0; i<characteristicCount; i++) {
-                if ((p_characteristics[i]->getProperties() & (GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_INDICATE | GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY)) &&
-                    (nrfCharacteristicHandles[i].cccd_handle == handle_value)) {
-                    uint16_t cccd_value =
-                        (gattsEventP->params.write.data[1] << 8) |
-                        gattsEventP->params.write.data[0]; /* Little Endian but M0 may be mis-aligned */
-
-                    if (((p_characteristics[i]->getProperties() & GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_INDICATE) && (cccd_value & BLE_GATT_HVX_INDICATION)) ||
-                        ((p_characteristics[i]->getProperties() & GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY) && (cccd_value & BLE_GATT_HVX_NOTIFICATION))) {
-                        eventType = GattServerEvents::GATT_EVENT_UPDATES_ENABLED;
-                    } else {
-                        eventType = GattServerEvents::GATT_EVENT_UPDATES_DISABLED;
-                    }
-
-                    handleEvent(eventType, i);
-                    return;
-                }
-            }
-
-            /* 2.) Changes to the characteristic value will be handled with other events below */
-            eventType = GattServerEvents::GATT_EVENT_DATA_WRITTEN;
-            break;
-
-        case BLE_GATTS_EVT_HVC:
-            /* Indication confirmation received */
-            eventType    = GattServerEvents::GATT_EVENT_CONFIRMATION_RECEIVED;
-            handle_value = gattsEventP->params.hvc.handle;
-            break;
-
-        case BLE_EVT_TX_COMPLETE: {
-            handleDataSentEvent(p_ble_evt->evt.common_evt.params.tx_complete.count);
-            return;
-        }
-
-        case BLE_GATTS_EVT_SYS_ATTR_MISSING:
-            sd_ble_gatts_sys_attr_set(gattsEventP->conn_handle, NULL, 0);
-            return;
-
-        case BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST:
-            switch (gattsEventP->params.authorize_request.type) {
-                case BLE_GATTS_AUTHORIZE_TYPE_READ:
-                    eventType    = GattServerEvents::GATT_EVENT_READ_AUTHORIZATION_REQ;
-                    handle_value = gattsEventP->params.authorize_request.request.read.handle;
-                    break;
-                case BLE_GATTS_AUTHORIZE_TYPE_WRITE:
-                    eventType    = GattServerEvents::GATT_EVENT_WRITE_AUTHORIZATION_REQ;
-                    handle_value = gattsEventP->params.authorize_request.request.write.handle;
-                    break;
-                default:
-                    return;
-            }
-            break;
-
-        default:
-            return;
-    }
-
-    /* Find index (charHandle) in the pool */
-    for (uint8_t i = 0; i < characteristicCount; i++) {
-        if (nrfCharacteristicHandles[i].value_handle == handle_value) {
-            switch (eventType) {
-                case GattServerEvents::GATT_EVENT_DATA_WRITTEN: {
-                    GattCharacteristicWriteCBParams cbParams = {
-                        .charHandle = i,
-                        .op     = static_cast<GattCharacteristicWriteCBParams::Type>(gattsEventP->params.write.op),
-                        .offset = gattsEventP->params.write.offset,
-                        .len    = gattsEventP->params.write.len,
-                        .data   = gattsEventP->params.write.data
-                    };
-                    handleDataWrittenEvent(&cbParams);
-                    break;
-                }
-                case GattServerEvents::GATT_EVENT_WRITE_AUTHORIZATION_REQ: {
-                    GattCharacteristicWriteAuthCBParams cbParams = {
-                        .charHandle = i,
-                        .offset     = gattsEventP->params.authorize_request.request.write.offset,
-                        .len        = gattsEventP->params.authorize_request.request.write.len,
-                        .data       = gattsEventP->params.authorize_request.request.write.data,
-                    };
-                    ble_gatts_rw_authorize_reply_params_t reply = {
-                        .type = BLE_GATTS_AUTHORIZE_TYPE_WRITE,
-                        .params = {
-                            .write = {
-                                .gatt_status = p_characteristics[i]->authorizeWrite(&cbParams)
-                            }
-                        }
-                    };
-                    sd_ble_gatts_rw_authorize_reply(gattsEventP->conn_handle, &reply);
-
-                    /*
-                     * If write-authorization is enabled for a characteristic,
-                     * AUTHORIZATION_REQ event (if replied with true) is *not*
-                     * followed by another DATA_WRITTEN event; so we still need
-                     * to invoke handleDataWritten(), much the same as we would
-                     * have done if write-authorization had not been enabled.
-                     */
-                    if (reply.params.write.gatt_status == BLE_GATT_STATUS_SUCCESS) {
-                        GattCharacteristicWriteCBParams cbParams = {
-                            .charHandle = i,
-                            .op         = static_cast<GattCharacteristicWriteCBParams::Type>(gattsEventP->params.authorize_request.request.write.op),
-                            .offset     = gattsEventP->params.authorize_request.request.write.offset,
-                            .len        = gattsEventP->params.authorize_request.request.write.len,
-                            .data       = gattsEventP->params.authorize_request.request.write.data,
-                        };
-                        handleDataWrittenEvent(&cbParams);
-                    }
-                    break;
-                }
-                case GattServerEvents::GATT_EVENT_READ_AUTHORIZATION_REQ: {
-                    GattCharacteristicReadAuthCBParams cbParams = {
-                        .charHandle = i,
-                        .offset     = gattsEventP->params.authorize_request.request.read.offset,
-                        .len        = 0,
-                        .data       = NULL
-                    };
-
-                    ble_gatts_rw_authorize_reply_params_t reply = {
-                        .type = BLE_GATTS_AUTHORIZE_TYPE_READ,
-                        .params = {
-                            .read = {
-                                .gatt_status = p_characteristics[i]->authorizeRead(&cbParams)
-                            }
-                        }
-                    };
-
-                    if (cbParams.authorizationReply == BLE_GATT_STATUS_SUCCESS) {
-                        if (cbParams.data != NULL) {
-                            reply.params.read.update = 1;
-                            reply.params.read.offset = cbParams.offset;
-                            reply.params.read.len    = cbParams.len;
-                            reply.params.read.p_data = cbParams.data;
-                        }
-                    }
-
-                    sd_ble_gatts_rw_authorize_reply(gattsEventP->conn_handle, &reply);
-                    break;
-                }
-
-                default:
-                    handleEvent(eventType, i);
-                    break;
-            }
-        }
-    }
-}
-
-ble_error_t
-nRF51GattServer::initializeGATTDatabase(void)
-{
-    /* Empty. Services are populated in the GattDatabase through addService(). */
-    return BLE_ERROR_NONE;
-}
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nRF51GattServer.h
--- a/nRF51822/nRF51GattServer.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __NRF51822_GATT_SERVER_H__
-#define __NRF51822_GATT_SERVER_H__
-
-#include <stddef.h>
-
-#include "blecommon.h"
-#include "ble.h" /* nordic ble */
-#include "GattServer.h"
-
-class nRF51GattServer : public GattServer
-{
-public:
-    static nRF51GattServer &getInstance() {
-        static nRF51GattServer m_instance;
-        return m_instance;
-    }
-
-    /* Functions that must be implemented from GattServer */
-    virtual ble_error_t addService(GattService &);
-    virtual ble_error_t readValue(GattAttribute::Handle_t handle, uint8_t buffer[], uint16_t *const lengthP);
-    virtual ble_error_t updateValue(GattAttribute::Handle_t, const uint8_t[], uint16_t, bool localOnly = false);
-    virtual ble_error_t initializeGATTDatabase(void);
-
-    /* nRF51 Functions */
-    void eventCallback(void);
-    void hwCallback(ble_evt_t *p_ble_evt);
-
-private:
-    const static unsigned BLE_TOTAL_CHARACTERISTICS = 24;
-    const static unsigned BLE_TOTAL_DESCRIPTORS     = 24;
-
-    GattCharacteristic       *p_characteristics[BLE_TOTAL_CHARACTERISTICS];
-    ble_gatts_char_handles_t  nrfCharacteristicHandles[BLE_TOTAL_CHARACTERISTICS];
-    GattAttribute            *p_descriptors[BLE_TOTAL_DESCRIPTORS];
-    uint8_t                   descriptorCount;
-    uint16_t                  nrfDescriptorHandles[BLE_TOTAL_DESCRIPTORS];
-
-    nRF51GattServer() : GattServer(), p_characteristics(), nrfCharacteristicHandles(), p_descriptors(), descriptorCount(0), nrfDescriptorHandles() {
-        /* empty */
-    }
-
-private:
-    nRF51GattServer(const nRF51GattServer &);
-    const nRF51GattServer& operator=(const nRF51GattServer &);
-};
-
-#endif // ifndef __NRF51822_GATT_SERVER_H__
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/ble_radio_notification/ble_radio_notification.c
--- a/nRF51822/nordic-sdk/components/ble/ble_radio_notification/ble_radio_notification.c	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,59 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- */
-
-#include "ble_radio_notification.h"
-#include <stdlib.h>
-
-
-static bool                                 m_radio_active = false;  /**< Current radio state. */
-static ble_radio_notification_evt_handler_t m_evt_handler  = NULL;   /**< Application event handler for handling Radio Notification events. */
-
-
-void SWI1_IRQHandler(void)
-{
-    m_radio_active = !m_radio_active;
-    if (m_evt_handler != NULL)
-    {
-        m_evt_handler(m_radio_active);
-    }
-}
-
-
-uint32_t ble_radio_notification_init(nrf_app_irq_priority_t               irq_priority,
-                                     nrf_radio_notification_distance_t    distance,
-                                     ble_radio_notification_evt_handler_t evt_handler)
-{
-    uint32_t err_code;
-
-    m_evt_handler = evt_handler;
-
-    // Initialize Radio Notification software interrupt
-    err_code = sd_nvic_ClearPendingIRQ(SWI1_IRQn);
-    if (err_code != NRF_SUCCESS)
-    {
-        return err_code;
-    }
-
-    err_code = sd_nvic_SetPriority(SWI1_IRQn, irq_priority);
-    if (err_code != NRF_SUCCESS)
-    {
-        return err_code;
-    }
-
-    err_code = sd_nvic_EnableIRQ(SWI1_IRQn);
-    if (err_code != NRF_SUCCESS)
-    {
-        return err_code;
-    }
-
-    // Configure the event
-    return sd_radio_notification_cfg_set(NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, distance);
-}
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/ble_radio_notification/ble_radio_notification.h
--- a/nRF51822/nordic-sdk/components/ble/ble_radio_notification/ble_radio_notification.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- */
-
-/** @file
- *
- * @defgroup ble_radio_notification Radio Notification Event Handler
- * @{
- * @ingroup ble_sdk_lib
- * @brief Module for propagating Radio Notification events to the application.
- */
-
-#ifndef BLE_RADIO_NOTIFICATION_H__
-#define BLE_RADIO_NOTIFICATION_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "nrf_soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**@brief Application radio notification event handler type. */
-typedef void (*ble_radio_notification_evt_handler_t) (bool radio_active);
-
-/**@brief Function for initializing the Radio Notification module.
- *
- * @param[in]  irq_priority   Interrupt priority for the Radio Notification interrupt handler.
- * @param[in]  distance       The time from an Active event until the radio is activated.
- * @param[in]  evt_handler    Handler to be executed when a radio notification event has been
- *                            received.
- *
- * @return     NRF_SUCCESS on successful initialization, otherwise an error code.
- */
-uint32_t ble_radio_notification_init(nrf_app_irq_priority_t               irq_priority,
-                                     nrf_radio_notification_distance_t    distance,
-                                     ble_radio_notification_evt_handler_t evt_handler);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // BLE_RADIO_NOTIFICATION_H__
-
-/** @} */
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/ble_services/ble_dfu/ble_dfu.c
--- a/nRF51822/nordic-sdk/components/ble/ble_services/ble_dfu/ble_dfu.c	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,654 +0,0 @@
-/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#include "ble_dfu.h"
-#include "nrf_error.h"
-#include "ble_types.h"
-#include "ble_gatts.h"
-#include "app_util.h"
-#include "ble_srv_common.h"
-#include "nordic_common.h"
-#include <stdint.h>
-#include <string.h>
-#include <stddef.h>
-
-#define MAX_DFU_PKT_LEN         20                                              /**< Maximum length (in bytes) of the DFU Packet characteristic. */
-#define PKT_START_DFU_PARAM_LEN 2                                               /**< Length (in bytes) of the parameters for Packet Start DFU Request. */
-#define PKT_INIT_DFU_PARAM_LEN  2                                               /**< Length (in bytes) of the parameters for Packet Init DFU Request. */
-#define PKT_RCPT_NOTIF_REQ_LEN  3                                               /**< Length (in bytes) of the Packet Receipt Notification Request. */
-#define MAX_PKTS_RCPT_NOTIF_LEN 6                                               /**< Maximum length (in bytes) of the Packets Receipt Notification. */
-#define MAX_RESPONSE_LEN        7                                               /**< Maximum length (in bytes) of the response to a Control Point command. */
-#define MAX_NOTIF_BUFFER_LEN    MAX(MAX_PKTS_RCPT_NOTIF_LEN, MAX_RESPONSE_LEN)  /**< Maximum length (in bytes) of the buffer needed by DFU Service while sending notifications to peer. */
-
-enum
-{
-    OP_CODE_START_DFU          = 1,                                             /**< Value of the Op code field for 'Start DFU' command.*/
-    OP_CODE_RECEIVE_INIT       = 2,                                             /**< Value of the Op code field for 'Initialize DFU parameters' command.*/
-    OP_CODE_RECEIVE_FW         = 3,                                             /**< Value of the Op code field for 'Receive firmware image' command.*/
-    OP_CODE_VALIDATE           = 4,                                             /**< Value of the Op code field for 'Validate firmware' command.*/
-    OP_CODE_ACTIVATE_N_RESET   = 5,                                             /**< Value of the Op code field for 'Activate & Reset' command.*/
-    OP_CODE_SYS_RESET          = 6,                                             /**< Value of the Op code field for 'Reset System' command.*/
-    OP_CODE_IMAGE_SIZE_REQ     = 7,                                             /**< Value of the Op code field for 'Report received image size' command.*/
-    OP_CODE_PKT_RCPT_NOTIF_REQ = 8,                                             /**< Value of the Op code field for 'Request packet receipt notification.*/
-    OP_CODE_RESPONSE           = 16,                                            /**< Value of the Op code field for 'Response.*/
-    OP_CODE_PKT_RCPT_NOTIF     = 17                                             /**< Value of the Op code field for 'Packets Receipt Notification'.*/
-};
-
-static bool     m_is_dfu_service_initialized = false;                           /**< Variable to check if the DFU service was initialized by the application.*/
-static uint8_t  m_notif_buffer[MAX_NOTIF_BUFFER_LEN];                           /**< Buffer used for sending notifications to peer. */
-
-/**@brief       Function for adding DFU Packet characteristic to the BLE Stack.
- *
- * @param[in]   p_dfu DFU Service structure.
- *
- * @return      NRF_SUCCESS on success. Otherwise an error code.
- */
-static uint32_t dfu_pkt_char_add(ble_dfu_t * const p_dfu)
-{
-    ble_gatts_char_md_t char_md;
-    ble_gatts_attr_t    attr_char_value;
-    ble_uuid_t          char_uuid;
-    ble_gatts_attr_md_t attr_md;
-
-    memset(&char_md, 0, sizeof(char_md));
-
-    char_md.char_props.write_wo_resp = 1;
-    char_md.p_char_user_desc         = NULL;
-    char_md.p_char_pf                = NULL;
-    char_md.p_user_desc_md           = NULL;
-    char_md.p_cccd_md                = NULL;
-    char_md.p_sccd_md                = NULL;
-
-    char_uuid.type = p_dfu->uuid_type;
-    char_uuid.uuid = BLE_DFU_PKT_CHAR_UUID;
-
-    memset(&attr_md, 0, sizeof(attr_md));
-
-    BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(&attr_md.read_perm);
-    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.write_perm);
-
-    attr_md.vloc    = BLE_GATTS_VLOC_STACK;
-    attr_md.rd_auth = 0;
-    attr_md.wr_auth = 0;
-    attr_md.vlen    = 1;
-
-    memset(&attr_char_value, 0, sizeof(attr_char_value));
-
-    attr_char_value.p_uuid    = &char_uuid;
-    attr_char_value.p_attr_md = &attr_md;
-    attr_char_value.init_len  = 0;
-    attr_char_value.init_offs = 0;
-    attr_char_value.max_len   = MAX_DFU_PKT_LEN;
-    attr_char_value.p_value   = NULL;
-
-    return sd_ble_gatts_characteristic_add(p_dfu->service_handle,
-                                           &char_md,
-                                           &attr_char_value,
-                                           &p_dfu->dfu_pkt_handles);
-}
-
-
-/**@brief       Function for adding DFU Revision characteristic to the BLE Stack.
- *
- * @param[in]   p_dfu DFU Service structure.
- *
- * @return      NRF_SUCCESS on success. Otherwise an error code.
- */
-static uint32_t dfu_rev_char_add(ble_dfu_t * const p_dfu, ble_dfu_init_t const * const p_dfu_init)
-{
-    ble_gatts_char_md_t char_md;
-    ble_gatts_attr_t    attr_char_value;
-    ble_uuid_t          char_uuid;
-    ble_gatts_attr_md_t attr_md;
-
-    memset(&char_md, 0, sizeof(char_md));
-
-    char_md.char_props.read          = 1;
-    char_md.p_char_user_desc         = NULL;
-    char_md.p_char_pf                = NULL;
-    char_md.p_user_desc_md           = NULL;
-    char_md.p_cccd_md                = NULL;
-    char_md.p_sccd_md                = NULL;
-
-    char_uuid.type = p_dfu->uuid_type;
-    char_uuid.uuid = BLE_DFU_REV_CHAR_UUID;
-
-    memset(&attr_md, 0, sizeof(attr_md));
-
-    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.read_perm);
-    BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(&attr_md.write_perm);
-
-    attr_md.vloc    = BLE_GATTS_VLOC_STACK;
-    attr_md.rd_auth = 0;
-    attr_md.wr_auth = 0;
-    attr_md.vlen    = 1;
-
-    memset(&attr_char_value, 0, sizeof(attr_char_value));
-
-    attr_char_value.p_uuid    = &char_uuid;
-    attr_char_value.p_attr_md = &attr_md;
-    attr_char_value.init_len  = sizeof(uint16_t);
-    attr_char_value.init_offs = 0;
-    attr_char_value.max_len   = sizeof(uint16_t);
-    attr_char_value.p_value   = (uint8_t *)&p_dfu_init->revision;
-
-    return sd_ble_gatts_characteristic_add(p_dfu->service_handle,
-                                           &char_md,
-                                           &attr_char_value,
-                                           &p_dfu->dfu_rev_handles);
-}
-
-
-/**@brief       Function for adding DFU Control Point characteristic to the BLE Stack.
- *
- * @param[in]   p_dfu DFU Service structure.
- *
- * @return      NRF_SUCCESS on success. Otherwise an error code.
- */
-static uint32_t dfu_ctrl_pt_add(ble_dfu_t * const p_dfu)
-{
-    ble_gatts_char_md_t char_md;
-    ble_gatts_attr_t    attr_char_value;
-    ble_uuid_t          char_uuid;
-    ble_gatts_attr_md_t attr_md;
-
-    memset(&char_md, 0, sizeof(char_md));
-
-    char_md.char_props.write  = 1;
-    char_md.char_props.notify = 1;
-    char_md.p_char_user_desc  = NULL;
-    char_md.p_char_pf         = NULL;
-    char_md.p_user_desc_md    = NULL;
-    char_md.p_cccd_md         = NULL;
-    char_md.p_sccd_md         = NULL;
-
-    char_uuid.type = p_dfu->uuid_type;
-    char_uuid.uuid = BLE_DFU_CTRL_PT_UUID;
-
-    memset(&attr_md, 0, sizeof(attr_md));
-
-    BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(&attr_md.read_perm);
-    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.write_perm);
-
-    attr_md.vloc    = BLE_GATTS_VLOC_STACK;
-    attr_md.rd_auth = 0;
-    attr_md.wr_auth = 1;
-    attr_md.vlen    = 1;
-
-    memset(&attr_char_value, 0, sizeof(attr_char_value));
-
-    attr_char_value.p_uuid    = &char_uuid;
-    attr_char_value.p_attr_md = &attr_md;
-    attr_char_value.init_len  = 0;
-    attr_char_value.init_offs = 0;
-    attr_char_value.max_len   = BLE_L2CAP_MTU_DEF;
-    attr_char_value.p_value   = NULL;
-
-    return sd_ble_gatts_characteristic_add(p_dfu->service_handle,
-                                           &char_md,
-                                           &attr_char_value,
-                                           &p_dfu->dfu_ctrl_pt_handles);
-}
-
-
-/**@brief     Function for handling the @ref BLE_GAP_EVT_CONNECTED event from the S110 SoftDevice.
- *
- * @param[in] p_dfu     DFU Service Structure.
- * @param[in] p_ble_evt Pointer to the event received from BLE stack.
- */
-static void on_connect(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
-{
-    p_dfu->conn_handle = p_ble_evt->evt.gap_evt.conn_handle;
-}
-
-
-/**@brief     Function for checking if the CCCD of DFU Control point is configured for Notification.
- *
- * @details   This function checks if the CCCD of DFU Control Point characteristic is configured
- *            for Notification by the DFU Controller.
- *
- * @param[in] p_dfu DFU Service structure.
- *
- * @return    True if the CCCD of DFU Control Point characteristic is configured for Notification.
- *            False otherwise.
- */
-static bool is_cccd_configured(ble_dfu_t * p_dfu)
-{
-    // Check if the CCCDs are configured.
-    uint16_t cccd_len = BLE_CCCD_VALUE_LEN;
-    uint8_t  cccd_val_buf[BLE_CCCD_VALUE_LEN];
-
-    // Check the CCCD Value of DFU Control Point.
-    uint32_t err_code = sd_ble_gatts_value_get(p_dfu->dfu_ctrl_pt_handles.cccd_handle,
-                                               0,
-                                               &cccd_len,
-                                               cccd_val_buf);
-    if (err_code != NRF_SUCCESS)
-    {
-        if (p_dfu->error_handler != NULL)
-        {
-            p_dfu->error_handler(err_code);
-        }
-        return false;
-    }
-
-    return ble_srv_is_notification_enabled(cccd_val_buf);
-}
-
-
-/**@brief     Function for handling a Write event on the Control Point characteristic.
- *
- * @param[in] p_dfu             DFU Service Structure.
- * @param[in] p_ble_write_evt   Pointer to the write event received from BLE stack.
- *
- * @return    NRF_SUCCESS on successful processing of control point write. Otherwise an error code.
- */
-static uint32_t on_ctrl_pt_write(ble_dfu_t * p_dfu, ble_gatts_evt_write_t * p_ble_write_evt)
-{
-    ble_gatts_rw_authorize_reply_params_t write_authorize_reply;
-
-    write_authorize_reply.type = BLE_GATTS_AUTHORIZE_TYPE_WRITE;
-
-    if (!is_cccd_configured(p_dfu))
-    {
-        // Send an error response to the peer indicating that the CCCD is improperly configured.
-        write_authorize_reply.params.write.gatt_status =
-            BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR;
-
-        return (sd_ble_gatts_rw_authorize_reply(p_dfu->conn_handle, &write_authorize_reply));
-
-    }
-    else
-    {
-        uint32_t err_code;
-
-        write_authorize_reply.params.write.gatt_status = BLE_GATT_STATUS_SUCCESS;
-
-        err_code = (sd_ble_gatts_rw_authorize_reply(p_dfu->conn_handle, &write_authorize_reply));
-
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-    }
-
-    ble_dfu_evt_t ble_dfu_evt;
-
-    switch (p_ble_write_evt->data[0])
-    {
-        case OP_CODE_START_DFU:
-            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_START;
-
-            if (p_ble_write_evt->len < PKT_START_DFU_PARAM_LEN)
-            {
-                return ble_dfu_response_send(p_dfu,
-                                             (ble_dfu_procedure_t) p_ble_write_evt->data[0],
-                                             BLE_DFU_RESP_VAL_OPER_FAILED);
-            }
-
-            ble_dfu_evt.evt.ble_dfu_pkt_write.len    = 1;
-            ble_dfu_evt.evt.ble_dfu_pkt_write.p_data = &(p_ble_write_evt->data[1]);
-
-            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
-            break;
-
-        case OP_CODE_RECEIVE_INIT:
-            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_RECEIVE_INIT_DATA;
-
-            if (p_ble_write_evt->len < PKT_INIT_DFU_PARAM_LEN)
-            {
-                return ble_dfu_response_send(p_dfu,
-                                             (ble_dfu_procedure_t) p_ble_write_evt->data[0],
-                                             BLE_DFU_RESP_VAL_OPER_FAILED);
-            }
-            
-            ble_dfu_evt.evt.ble_dfu_pkt_write.len    = 1;
-            ble_dfu_evt.evt.ble_dfu_pkt_write.p_data = &(p_ble_write_evt->data[1]);
-
-            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
-            break;
-
-        case OP_CODE_RECEIVE_FW:
-            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_RECEIVE_APP_DATA;
-
-            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
-            break;
-
-        case OP_CODE_VALIDATE:
-            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_VALIDATE;
-
-            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
-            break;
-
-        case OP_CODE_ACTIVATE_N_RESET:
-            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_ACTIVATE_N_RESET;
-
-            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
-            break;
-
-        case OP_CODE_SYS_RESET:
-            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_SYS_RESET;
-
-            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
-            break;
-
-        case OP_CODE_PKT_RCPT_NOTIF_REQ:
-            if (p_ble_write_evt->len < PKT_RCPT_NOTIF_REQ_LEN)
-            {
-                return (ble_dfu_response_send(p_dfu,
-                                              BLE_DFU_PKT_RCPT_REQ_PROCEDURE,
-                                              BLE_DFU_RESP_VAL_NOT_SUPPORTED));
-            }
-
-            ble_dfu_evt.evt.pkt_rcpt_notif_req.num_of_pkts =
-                uint16_decode(&(p_ble_write_evt->data[1]));
-
-            if (ble_dfu_evt.evt.pkt_rcpt_notif_req.num_of_pkts == 0)
-            {
-                ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_PKT_RCPT_NOTIF_DISABLED;
-            }
-            else
-            {
-                ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_PKT_RCPT_NOTIF_ENABLED;
-            }
-
-            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
-
-            break;
-
-        case OP_CODE_IMAGE_SIZE_REQ:
-            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_BYTES_RECEIVED_SEND;
-
-            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
-            break;
-
-        default:
-            // Unsupported op code.
-            return ble_dfu_response_send(p_dfu,
-                                         (ble_dfu_procedure_t) p_ble_write_evt->data[0],
-                                         BLE_DFU_RESP_VAL_NOT_SUPPORTED);
-    }
-    return NRF_SUCCESS;
-}
-
-
-/**@brief     Function for handling the @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event from the S110
- *            Stack.
- *
- * @param[in] p_dfu     DFU Service Structure.
- * @param[in] p_ble_evt Pointer to the event received from BLE stack.
- */
-static void on_rw_auth_req(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
-{
-    ble_gatts_evt_rw_authorize_request_t * p_authorize_request;
-
-    p_authorize_request = &(p_ble_evt->evt.gatts_evt.params.authorize_request);
-
-    if (
-        (p_authorize_request->type == BLE_GATTS_AUTHORIZE_TYPE_WRITE)
-        &&
-        (p_authorize_request->request.write.handle == p_dfu->dfu_ctrl_pt_handles.value_handle)
-       )
-    {
-        uint32_t err_code;
-
-        err_code = on_ctrl_pt_write(p_dfu, &(p_authorize_request->request.write));
-
-        if (err_code != NRF_SUCCESS && p_dfu->error_handler != NULL)
-        {
-            p_dfu->error_handler(err_code);
-        }
-    }
-}
-
-
-/**@brief     Function for handling the @ref BLE_GATTS_EVT_WRITE event from the S110 SoftDevice.
- *
- * @param[in] p_dfu     DFU Service Structure.
- * @param[in] p_ble_evt Pointer to the event received from BLE stack.
- */
-static void on_write(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
-{
-    if (p_ble_evt->evt.gatts_evt.params.write.handle == p_dfu->dfu_pkt_handles.value_handle)
-    {
-        // DFU Packet written
-
-        ble_dfu_evt_t ble_dfu_evt;
-
-        ble_dfu_evt.ble_dfu_evt_type             = BLE_DFU_PACKET_WRITE;
-        ble_dfu_evt.evt.ble_dfu_pkt_write.len    = p_ble_evt->evt.gatts_evt.params.write.len;
-        ble_dfu_evt.evt.ble_dfu_pkt_write.p_data = p_ble_evt->evt.gatts_evt.params.write.data;
-
-        p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
-    }
-}
-
-
-/**@brief     Function for handling the BLE_GAP_EVT_DISCONNECTED event from the S110 SoftDevice.
- *
- * @param[in] p_dfu     DFU Service Structure.
- * @param[in] p_ble_evt Pointer to the event received from BLE stack.
- */
-static void on_disconnect(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
-{
-    p_dfu->conn_handle = BLE_CONN_HANDLE_INVALID;
-}
-
-
-uint32_t ble_dfu_init(ble_dfu_t * p_dfu, ble_dfu_init_t * p_dfu_init)
-{
-    if ((p_dfu == NULL) || (p_dfu_init == NULL) || (p_dfu_init->evt_handler == NULL))
-    {
-        return NRF_ERROR_NULL;
-    }
-
-    p_dfu->conn_handle = BLE_CONN_HANDLE_INVALID;
-
-    ble_uuid_t service_uuid;
-    uint32_t   err_code;
-
-    const ble_uuid128_t base_uuid128 =
-    {
-        {
-            0x23, 0xD1, 0xBC, 0xEA, 0x5F, 0x78, 0x23, 0x15,
-            0xDE, 0xEF, 0x12, 0x12, 0x00, 0x00, 0x00, 0x00
-        }
-    };
-
-    service_uuid.uuid = BLE_DFU_SERVICE_UUID;
-
-    err_code = sd_ble_uuid_vs_add(&base_uuid128, &(service_uuid.type));
-    if (err_code != NRF_SUCCESS)
-    {
-        return err_code;
-    }
-
-    err_code = sd_ble_gatts_service_add(BLE_GATTS_SRVC_TYPE_PRIMARY,
-                                        &service_uuid,
-                                        &(p_dfu->service_handle));
-    if (err_code != NRF_SUCCESS)
-    {
-        return err_code;
-    }
-
-    p_dfu->uuid_type = service_uuid.type;
-
-    err_code = dfu_pkt_char_add(p_dfu);
-    if (err_code != NRF_SUCCESS)
-    {
-        return err_code;
-    }
-
-    err_code = dfu_ctrl_pt_add(p_dfu);
-    if (err_code != NRF_SUCCESS)
-    {
-        return err_code;
-    }
-
-    err_code = dfu_rev_char_add(p_dfu, p_dfu_init);
-    if (err_code != NRF_SUCCESS)
-    {
-        return err_code;
-    }
-
-    p_dfu->evt_handler = p_dfu_init->evt_handler;
-
-    if (p_dfu_init->error_handler != NULL)
-    {
-        p_dfu->error_handler = p_dfu_init->error_handler;
-    }
-
-    m_is_dfu_service_initialized = true;
-
-    return NRF_SUCCESS;
-}
-
-
-void ble_dfu_on_ble_evt(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
-{
-    if ((p_dfu == NULL) || (p_ble_evt == NULL))
-    {
-        return;
-    }
-
-    if (p_dfu->evt_handler != NULL)
-    {
-        switch (p_ble_evt->header.evt_id)
-        {
-            case BLE_GAP_EVT_CONNECTED:
-                on_connect(p_dfu, p_ble_evt);
-                break;
-
-            case BLE_GATTS_EVT_WRITE:
-                on_write(p_dfu, p_ble_evt);
-                break;
-
-            case BLE_GAP_EVT_DISCONNECTED:
-                on_disconnect(p_dfu, p_ble_evt);
-                break;
-
-            case BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST:
-                on_rw_auth_req(p_dfu, p_ble_evt);
-                break;
-
-            default:
-                // No implementation needed.
-                break;
-        }
-    }
-}
-
-
-uint32_t ble_dfu_bytes_rcvd_report(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd)
-{
-    if (p_dfu == NULL)
-    {
-        return NRF_ERROR_NULL;
-    }
-
-    if ((p_dfu->conn_handle == BLE_CONN_HANDLE_INVALID) || !m_is_dfu_service_initialized)
-    {
-        return NRF_ERROR_INVALID_STATE;
-    }
-
-    ble_gatts_hvx_params_t hvx_params;
-    uint16_t               index = 0;
-
-    // Encode the Op Code.
-    m_notif_buffer[index++] = OP_CODE_RESPONSE;
-
-    // Encode the Reqest Op Code.
-    m_notif_buffer[index++] = OP_CODE_IMAGE_SIZE_REQ;
-
-    // Encode the Response Value.
-    m_notif_buffer[index++] = (uint8_t)BLE_DFU_RESP_VAL_SUCCESS;
-
-    index += uint32_encode(num_of_firmware_bytes_rcvd, &m_notif_buffer[index]);
-
-    memset(&hvx_params, 0, sizeof(hvx_params));
-
-    hvx_params.handle = p_dfu->dfu_ctrl_pt_handles.value_handle;
-    hvx_params.type   = BLE_GATT_HVX_NOTIFICATION;
-    hvx_params.offset = 0;
-    hvx_params.p_len  = &index;
-    hvx_params.p_data = m_notif_buffer;
-
-    return sd_ble_gatts_hvx(p_dfu->conn_handle, &hvx_params);
-}
-
-
-uint32_t ble_dfu_pkts_rcpt_notify(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd)
-{
-    if (p_dfu == NULL)
-    {
-        return NRF_ERROR_NULL;
-    }
-
-    if ((p_dfu->conn_handle == BLE_CONN_HANDLE_INVALID) || !m_is_dfu_service_initialized)
-    {
-        return NRF_ERROR_INVALID_STATE;
-    }
-
-    ble_gatts_hvx_params_t hvx_params;
-    uint16_t               index = 0;
-
-    m_notif_buffer[index++] = OP_CODE_PKT_RCPT_NOTIF;
-
-    index += uint32_encode(num_of_firmware_bytes_rcvd, &m_notif_buffer[index]);
-
-    memset(&hvx_params, 0, sizeof(hvx_params));
-
-    hvx_params.handle = p_dfu->dfu_ctrl_pt_handles.value_handle;
-    hvx_params.type   = BLE_GATT_HVX_NOTIFICATION;
-    hvx_params.offset = 0;
-    hvx_params.p_len  = &index;
-    hvx_params.p_data = m_notif_buffer;
-
-    return sd_ble_gatts_hvx(p_dfu->conn_handle, &hvx_params);
-}
-
-
-uint32_t ble_dfu_response_send(ble_dfu_t         * p_dfu,
-                               ble_dfu_procedure_t dfu_proc,
-                               ble_dfu_resp_val_t  resp_val)
-{
-    if (p_dfu == NULL)
-    {
-        return NRF_ERROR_NULL;
-    }
-
-    if ((p_dfu->conn_handle == BLE_CONN_HANDLE_INVALID) || !m_is_dfu_service_initialized)
-    {
-        return NRF_ERROR_INVALID_STATE;
-    }
-
-    ble_gatts_hvx_params_t hvx_params;
-    uint16_t               index = 0;
-
-    m_notif_buffer[index++] = OP_CODE_RESPONSE;
-
-    // Encode the Request Op code
-    m_notif_buffer[index++] = (uint8_t)dfu_proc;
-
-    // Encode the Response Value.
-    m_notif_buffer[index++] = (uint8_t)resp_val;
-
-    memset(&hvx_params, 0, sizeof(hvx_params));
-
-    hvx_params.handle = p_dfu->dfu_ctrl_pt_handles.value_handle;
-    hvx_params.type   = BLE_GATT_HVX_NOTIFICATION;
-    hvx_params.offset = 0;
-    hvx_params.p_len  = &index;
-    hvx_params.p_data = m_notif_buffer;
-
-    return sd_ble_gatts_hvx(p_dfu->conn_handle, &hvx_params);
-}
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/ble_services/ble_dfu/ble_dfu.h
--- a/nRF51822/nordic-sdk/components/ble/ble_services/ble_dfu/ble_dfu.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,239 +0,0 @@
-/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/**@file
- *
- * @defgroup ble_sdk_srv_dfu Device Firmware Update Service
- * @{
- * @ingroup  ble_sdk_srv
- * @brief    Device Firmware Update Service
- *
- * @details  The Device Firmware Update (DFU) service is a GATT based service that can be used for
- *           performing firmware updates over BLE. Note that this implementation uses vendor
- *           specific UUIDs for service and characteristics and is intended to demonstrate the
- *           firmware updates over BLE. Refer @ref ota_spec_sec and @ref
- *            ota_profile_section for more information on the service and profile respectively.
- */
-
-#ifndef BLE_DFU_H__
-#define BLE_DFU_H__
-
-#include <stdint.h>
-#include "ble_gatts.h"
-#include "ble_gap.h"
-#include "ble.h"
-#include "ble_srv_common.h"
-
-#define BLE_DFU_SERVICE_UUID                 0x1530                       /**< The UUID of the DFU Service. */
-#define BLE_DFU_PKT_CHAR_UUID                0x1532                       /**< The UUID of the DFU Packet Characteristic. */
-#define BLE_DFU_CTRL_PT_UUID                 0x1531                       /**< The UUID of the DFU Control Point. */
-#define BLE_DFU_STATUS_REP_UUID              0x1533                       /**< The UUID of the DFU Status Report Characteristic. */
-#define BLE_DFU_REV_CHAR_UUID                0x1534                       /**< The UUID of the DFU Revision Characteristic. */
-
-/**@brief   DFU Event type.
- *
- * @details This enumeration contains the types of events that will be received from the DFU Service.
- */
-typedef enum
-{
-    BLE_DFU_START,                                                      /**< The event indicating that the peer wants the application to prepare for a new firmware update. */
-    BLE_DFU_RECEIVE_INIT_DATA,                                          /**< The event indicating that the peer wants the application to prepare to receive init parameters. */
-    BLE_DFU_RECEIVE_APP_DATA,                                           /**< The event indicating that the peer wants the application to prepare to receive the new firmware image. */
-    BLE_DFU_VALIDATE,                                                   /**< The event indicating that the peer wants the application to validate the newly received firmware image. */
-    BLE_DFU_ACTIVATE_N_RESET,                                           /**< The event indicating that the peer wants the application to undergo activate new firmware and restart with new valid application */
-    BLE_DFU_SYS_RESET,                                                  /**< The event indicating that the peer wants the application to undergo a reset and start the currently valid application image.*/
-    BLE_DFU_PKT_RCPT_NOTIF_ENABLED,                                     /**< The event indicating that the peer has enabled packet receipt notifications. It is the responsibility of the application to call @ref ble_dfu_pkts_rcpt_notify each time the number of packets indicated by num_of_pkts field in @ref ble_dfu_evt_t is received.*/
-    BLE_DFU_PKT_RCPT_NOTIF_DISABLED,                                    /**< The event indicating that the peer has disabled the packet receipt notifications.*/
-    BLE_DFU_PACKET_WRITE,                                               /**< The event indicating that the peer has written a value to the 'DFU Packet' characteristic. The data received from the peer will be present in the @ref BLE_DFU_PACKET_WRITE element contained within @ref ble_dfu_evt_t.*/
-    BLE_DFU_BYTES_RECEIVED_SEND                                         /**< The event indicating that the peer is requesting for the number of bytes of firmware data last received by the application. It is the responsibility of the application to call @ref ble_dfu_pkts_rcpt_notify in response to this event. */
-} ble_dfu_evt_type_t;
-
-/**@brief   DFU Procedure type.
- *
- * @details This enumeration contains the types of DFU procedures.
- */
-typedef enum
-{
-    BLE_DFU_START_PROCEDURE        = 1,                                 /**< DFU Start procedure.*/
-    BLE_DFU_INIT_PROCEDURE         = 2,                                 /**< DFU Initialization procedure.*/
-    BLE_DFU_RECEIVE_APP_PROCEDURE  = 3,                                 /**< Firmware receiving procedure.*/
-    BLE_DFU_VALIDATE_PROCEDURE     = 4,                                 /**< Firmware image validation procedure .*/
-    BLE_DFU_PKT_RCPT_REQ_PROCEDURE = 8                                  /**< Packet receipt notification request procedure. */
-} ble_dfu_procedure_t;
-
-/**@brief   DFU Response value type.
- */
-typedef enum
-{
-    BLE_DFU_RESP_VAL_SUCCESS = 1,                                       /**< Success.*/
-    BLE_DFU_RESP_VAL_INVALID_STATE,                                     /**< Invalid state.*/
-    BLE_DFU_RESP_VAL_NOT_SUPPORTED,                                     /**< Operation not supported.*/
-    BLE_DFU_RESP_VAL_DATA_SIZE,                                         /**< Data size exceeds limit.*/
-    BLE_DFU_RESP_VAL_CRC_ERROR,                                         /**< CRC Error.*/
-    BLE_DFU_RESP_VAL_OPER_FAILED                                        /**< Operation failed.*/
-} ble_dfu_resp_val_t;
-
-
-/**@brief   DFU Packet structure.
- *
- * @details This structure contains the value of the DFU Packet characteristic as written by the
- *          peer and the length of the value written. It will be filled by the DFU Service when the
- *          peer writes to the DFU Packet characteristic.
- */
-typedef struct
-{
-    uint8_t                      len;                                   /**< Length of the packet received. */
-    uint8_t *                    p_data;                                /**< Pointer to the received packet. This will point to a word aligned memory location.*/
-} ble_dfu_pkt_write_t;
-
-/**@brief   Packet receipt notification request structure.
- *
- * @details This structure contains the contents of the packet receipt notification request
- *          sent by the DFU Controller.
- */
-typedef struct
-{
-    uint16_t                     num_of_pkts;                           /**< The number of packets of firmware data to be received by application before sending the next Packet Receipt Notification to the peer. */
-} ble_pkt_rcpt_notif_req_t;
-
-/**@brief   DFU Event structure.
- *
- * @details This structure contains the event generated by the DFU Service based on the data
- *          received from the peer.
- */
-typedef struct
-{
-    ble_dfu_evt_type_t           ble_dfu_evt_type;                      /**< Type of the event.*/
-    union
-    {
-        ble_dfu_pkt_write_t      ble_dfu_pkt_write;                     /**< The DFU packet received. This field is when the @ref ble_dfu_evt_type field is set to @ref BLE_DFU_PACKET_WRITE.*/
-        ble_pkt_rcpt_notif_req_t pkt_rcpt_notif_req;                    /**< Packet receipt notification request. This field is when the @ref ble_dfu_evt_type field is set to @ref BLE_DFU_PKT_RCPT_NOTIF_ENABLED.*/
-    } evt;
-} ble_dfu_evt_t;
-
-// Forward declaration of the ble_dfu_t type.
-typedef struct ble_dfu_s ble_dfu_t;
-
-/**@brief DFU Service event handler type. */
-typedef void (*ble_dfu_evt_handler_t) (ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt);
-
-/**@brief   DFU service structure.
- *
- * @details This structure contains status information related to the service.
- */
-typedef struct ble_dfu_s
-{
-    uint16_t                     conn_handle;                           /**< Handle of the current connection (as provided by the S110 SoftDevice). This will be BLE_CONN_HANDLE_INVALID when not in a connection. */
-    uint16_t                     revision;                              /**< Handle of DFU Service (as provided by the S110 SoftDevice). */
-    uint16_t                     service_handle;                        /**< Handle of DFU Service (as provided by the S110 SoftDevice). */
-    uint8_t                      uuid_type;                             /**< UUID type assigned for DFU Service by the S110 SoftDevice. */
-    ble_gatts_char_handles_t     dfu_pkt_handles;                       /**< Handles related to the DFU Packet characteristic. */
-    ble_gatts_char_handles_t     dfu_ctrl_pt_handles;                   /**< Handles related to the DFU Control Point characteristic. */
-    ble_gatts_char_handles_t     dfu_status_rep_handles;                /**< Handles related to the DFU Status Report characteristic. */
-    ble_gatts_char_handles_t     dfu_rev_handles;                       /**< Handles related to the DFU Revision characteristic. */
-    ble_dfu_evt_handler_t        evt_handler;                           /**< The event handler to be called when an event is to be sent to the application.*/
-    ble_srv_error_handler_t      error_handler;                         /**< Function to be called in case of an error. */
-} ble_dfu_t;
-
-/**@brief      DFU service initialization structure.
- *
- * @details    This structure contains the initialization information for the DFU Service. The
- *             application needs to fill this structure and pass it to the DFU Service using the
- *             @ref ble_dfu_init function.
- */
-typedef struct
-{
-    uint16_t                     revision;                              /**< Revision number to be exposed by the DFU service. */
-    ble_dfu_evt_handler_t        evt_handler;                           /**< Event handler to be called for handling events in the Device Firmware Update Service. */
-    ble_srv_error_handler_t      error_handler;                         /**< Function to be called in case of an error. */
-} ble_dfu_init_t;
-
-/**@brief      Function for handling a BLE event.
- *
- * @details    The DFU service expects the application to call this function each time an event
- *             is received from the S110 SoftDevice. This function processes the event, if it is
- *             relevant for the DFU service and calls the DFU event handler of the application if
- *             necessary.
- *
- * @param[in]  p_dfu        Pointer to the DFU service structure.
- * @param[in]  p_ble_evt    Pointer to the event received from S110 SoftDevice.
- */
-void ble_dfu_on_ble_evt(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt);
-
-/**@brief      Function for initializing the DFU service.
- *
- * @param[out] p_dfu        Device Firmware Update service structure. This structure will have to be
- *                          supplied by the application. It will be initialized by this function,
- *                          and will later be used to identify the service instance.
- * @param[in]  p_dfu_init   Information needed to initialize the service.
- *
- * @return     NRF_SUCCESS if the DFU service and its characteristics were successfully added to the
- *             S110 SoftDevice. Otherwise an error code.
- *             This function returns NRF_ERROR_NULL if the value of evt_handler in p_dfu_init
- *             structure provided is NULL or if the pointers supplied as input are NULL.
- */
-uint32_t ble_dfu_init(ble_dfu_t * p_dfu, ble_dfu_init_t * p_dfu_init);
-
-/**@brief       Function for sending response to a control point command.
- *
- * @details     This function will encode a DFU Control Point response using the given input
- *              parameters and will send a notification of the same to the peer.
- *
- * @param[in]   p_dfu       Pointer to the DFU service structure.
- * @param[in]   dfu_proc    Procedure for which this response is to be sent.
- * @param[in]   resp_val    Response value.
- *
- * @return      NRF_SUCCESS if the DFU Service has successfully requested the S110 SoftDevice to
- *              send the notification. Otherwise an error code.
- *              This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a
- *              peer or if the DFU service is not initialized or if the notification of the DFU
- *              Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL
- *              if the pointer p_dfu is NULL.
- */
-uint32_t ble_dfu_response_send(ble_dfu_t *          p_dfu,
-                               ble_dfu_procedure_t  dfu_proc,
-                               ble_dfu_resp_val_t   resp_val);
-
-/**@brief      Function for notifying the peer about the number of bytes of firmware data received.
- *
- * @param[in]  p_dfu                      Pointer to the DFU service structure.
- * @param[in]  num_of_firmware_bytes_rcvd Number of bytes.
- *
- * @return     NRF_SUCCESS if the DFU Service has successfully requested the S110 SoftDevice to send
- *             the notification. Otherwise an error code.
- *             This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a
- *             peer or if the DFU service is not initialized or if the notification of the DFU
- *             Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL
- *             if the pointer p_dfu is NULL.
- */
-uint32_t ble_dfu_bytes_rcvd_report(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd);
-
-/**@brief      Function for sending Packet Receipt Notification to the peer.
- *
- *             This function will encode the number of bytes received as input parameter into a
- *             notification of the control point characteristic and send it to the peer.
- *
- * @param[in]  p_dfu                      Pointer to the DFU service structure.
- * @param[in]  num_of_firmware_bytes_rcvd Number of bytes of firmware image received.
- *
- * @return     NRF_SUCCESS if the DFU Service has successfully requested the S110 SoftDevice to send
- *             the notification. Otherwise an error code.
- *             This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a
- *             peer or if the DFU service is not initialized or if the notification of the DFU
- *             Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL
- *             if the pointer p_dfu is NULL.
- */
-uint32_t ble_dfu_pkts_rcpt_notify(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd);
-
-#endif // BLE_DFU_H__
-
-/** @} */
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/common/ble_advdata.c
--- a/nRF51822/nordic-sdk/components/ble/common/ble_advdata.c	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,624 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#include "ble_advdata.h"
-#include "nordic_common.h"
-#include "nrf_error.h"
-#include "ble_gap.h"
-#include "ble_srv_common.h"
-#include "app_util.h"
-
-
-// Offset from where advertisement data other than flags information can start.
-#define ADV_FLAG_OFFSET 2
-
-// Offset for Advertising Data.
-// Offset is 2 as each Advertising Data contain 1 octet of Adveritising Data Type and
-// one octet Advertising Data Length.
-#define ADV_DATA_OFFSET 2
-
-// NOTE: For now, Security Manager TK Value and Security Manager Out of Band Flags (OOB) are omitted
-//       from the advertising data.
-
-
-static uint32_t name_encode(const ble_advdata_t * p_advdata,
-                            uint8_t             * p_encoded_data,
-                            uint8_t             * p_len)
-{
-    uint32_t err_code;
-    uint16_t rem_adv_data_len;
-    uint16_t actual_length;
-    uint8_t  adv_data_format;
-    uint8_t  adv_offset;
-
-    adv_offset = *p_len;
-
-
-    // Check for buffer overflow.
-    if ((adv_offset + ADV_DATA_OFFSET > BLE_GAP_ADV_MAX_SIZE) ||
-        ((p_advdata->short_name_len + ADV_DATA_OFFSET) > BLE_GAP_ADV_MAX_SIZE))
-    {
-        return NRF_ERROR_DATA_SIZE;
-    }
-    actual_length = rem_adv_data_len = (BLE_GAP_ADV_MAX_SIZE - adv_offset - ADV_FLAG_OFFSET);
-
-    // Get GAP device name and length
-    err_code = sd_ble_gap_device_name_get(&p_encoded_data[adv_offset + ADV_DATA_OFFSET],
-                                          &actual_length);
-    if (err_code != NRF_SUCCESS)
-    {
-        return err_code;
-    }
-    
-    // Check if device internd to use short name and it can fit available data size.
-    if ((p_advdata->name_type == BLE_ADVDATA_FULL_NAME) && (actual_length <= rem_adv_data_len))
-    {
-        // Complete device name can fit, setting Complete Name in Adv Data.
-        adv_data_format  = BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME;
-        rem_adv_data_len = actual_length;
-    }
-    else
-    {
-        // Else short name needs to be used. Or application has requested use of short name.
-        adv_data_format = BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME;
-
-        // If application has set a preference on the short name size, it needs to be considered,
-        // else fit what can be fit.
-        if ((p_advdata->short_name_len != 0) && (p_advdata->short_name_len <= rem_adv_data_len))
-        {
-            // Short name fits available size.
-            rem_adv_data_len = p_advdata->short_name_len;
-        }
-        // Else whatever can fit the data buffer will be packed.
-        else
-        {
-            rem_adv_data_len = actual_length;
-        }
-    }
-
-    // Complete name field in encoded data.
-    p_encoded_data[adv_offset++] = rem_adv_data_len + 1;
-    p_encoded_data[adv_offset++] = adv_data_format;
-    (*p_len)                    += (rem_adv_data_len + ADV_DATA_OFFSET);
-
-    return NRF_SUCCESS;
-}
-
-
-static uint32_t appearance_encode(uint8_t * p_encoded_data, uint8_t * p_len)
-{
-    uint32_t err_code;
-    uint16_t appearance;
-
-    // Check for buffer overflow.
-    if ((*p_len) + 4 > BLE_GAP_ADV_MAX_SIZE)
-    {
-        return NRF_ERROR_DATA_SIZE;
-    }
-
-    // Get GAP appearance field.
-    err_code = sd_ble_gap_appearance_get(&appearance);
-    if (err_code != NRF_SUCCESS)
-    {
-        return err_code;
-    }
-
-    // Encode Length, AD Type and Appearance.
-    p_encoded_data[(*p_len)++] = 3;
-    p_encoded_data[(*p_len)++] = BLE_GAP_AD_TYPE_APPEARANCE;
-
-    (*p_len) += uint16_encode(appearance, &p_encoded_data[*p_len]);
-
-    return NRF_SUCCESS;
-}
-
-
-static uint32_t uint8_array_encode(const uint8_array_t * p_uint8_array,
-                                   uint8_t               adv_type,
-                                   uint8_t             * p_encoded_data,
-                                   uint8_t             * p_len)
-{
-    // Check parameter consistency.
-    if (p_uint8_array->p_data == NULL)
-    {
-        return NRF_ERROR_INVALID_PARAM;
-    }
-
-    // Check for buffer overflow.
-    if ((*p_len) + ADV_DATA_OFFSET + p_uint8_array->size > BLE_GAP_ADV_MAX_SIZE)
-    {
-        return NRF_ERROR_DATA_SIZE;
-    }
-
-    // Encode Length and AD Type.
-    p_encoded_data[(*p_len)++] = 1 + p_uint8_array->size;
-    p_encoded_data[(*p_len)++] = adv_type;
-
-    // Encode array.
-    memcpy(&p_encoded_data[*p_len], p_uint8_array->p_data, p_uint8_array->size);
-    (*p_len) += p_uint8_array->size;
-
-    return NRF_SUCCESS;
-}
-
-
-static uint32_t tx_power_level_encode(int8_t    tx_power_level,
-                                      uint8_t * p_encoded_data,
-                                      uint8_t * p_len)
-{
-    // Check for buffer overflow.
-    if ((*p_len) + 3 > BLE_GAP_ADV_MAX_SIZE)
-    {
-        return NRF_ERROR_DATA_SIZE;
-    }
-
-    // Encode TX Power Level.
-    p_encoded_data[(*p_len)++] = 2;
-    p_encoded_data[(*p_len)++] = BLE_GAP_AD_TYPE_TX_POWER_LEVEL;
-    p_encoded_data[(*p_len)++] = (uint8_t)tx_power_level;
-
-    return NRF_SUCCESS;
-}
-
-
-static uint32_t uuid_list_sized_encode(const ble_advdata_uuid_list_t * p_uuid_list,
-                                       uint8_t                         adv_type,
-                                       uint8_t                         uuid_size,
-                                       uint8_t                       * p_encoded_data,
-                                       uint8_t                       * p_len)
-{
-    int     i;
-    bool    is_heading_written = false;
-    uint8_t start_pos          = *p_len;
-
-    for (i = 0; i < p_uuid_list->uuid_cnt; i++)
-    {
-        uint32_t   err_code;
-        uint8_t    encoded_size;
-        ble_uuid_t uuid = p_uuid_list->p_uuids[i];
-        
-        // Find encoded uuid size.
-        err_code = sd_ble_uuid_encode(&uuid, &encoded_size, NULL);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-
-        // Check size.
-        if (encoded_size == uuid_size)
-        {
-            uint8_t heading_bytes = (is_heading_written) ? 0 : 2;
-            
-            // Check for buffer overflow
-            if (*p_len + encoded_size + heading_bytes > BLE_GAP_ADV_MAX_SIZE)
-            {
-                return NRF_ERROR_DATA_SIZE;
-            }
-
-            if (!is_heading_written)
-            {
-                // Write AD structure heading.
-                (*p_len)++;
-                p_encoded_data[(*p_len)++] = adv_type;
-                is_heading_written         = true;
-            }
-
-            // Write UUID.
-            err_code = sd_ble_uuid_encode(&uuid, &encoded_size, &p_encoded_data[*p_len]);
-            if (err_code != NRF_SUCCESS)
-            {
-                return err_code;
-            }
-            (*p_len) += encoded_size;
-        }
-    }
-
-    if (is_heading_written)
-    {
-        // Write length.
-        p_encoded_data[start_pos] = (*p_len) - (start_pos + 1);
-    }
-
-    return NRF_SUCCESS;
-}
-
-
-static uint32_t uuid_list_encode(const ble_advdata_uuid_list_t * p_uuid_list,
-                                 uint8_t                         adv_type_16,
-                                 uint8_t                         adv_type_128,
-                                 uint8_t                       * p_encoded_data,
-                                 uint8_t                       * p_len)
-{
-    uint32_t err_code;
-
-    // Encode 16 bit UUIDs.
-    err_code = uuid_list_sized_encode(p_uuid_list,
-                                      adv_type_16,
-                                      sizeof(uint16_le_t),
-                                      p_encoded_data,
-                                      p_len);
-    if (err_code != NRF_SUCCESS)
-    {
-        return err_code;
-    }
-
-    // Encode 128 bit UUIDs.
-    err_code = uuid_list_sized_encode(p_uuid_list,
-                                      adv_type_128,
-                                      sizeof(ble_uuid128_t),
-                                      p_encoded_data,
-                                      p_len);
-    if (err_code != NRF_SUCCESS)
-    {
-        return err_code;
-    }
-
-    return NRF_SUCCESS;
-}
-
-
-static uint32_t conn_int_check(const ble_advdata_conn_int_t *p_conn_int)
-{
-    // Check Minimum Connection Interval.
-    if ((p_conn_int->min_conn_interval < 0x0006) ||
-        (
-            (p_conn_int->min_conn_interval > 0x0c80) &&
-            (p_conn_int->min_conn_interval != 0xffff)
-        )
-       )
-    {
-        return NRF_ERROR_INVALID_PARAM;
-    }
-
-    // Check Maximum Connection Interval.
-    if ((p_conn_int->max_conn_interval < 0x0006) || 
-        (
-            (p_conn_int->max_conn_interval > 0x0c80) && 
-            (p_conn_int->max_conn_interval != 0xffff)
-        )
-       )
-    {
-        return NRF_ERROR_INVALID_PARAM;
-    }
-
-    // Make sure Minimum Connection Interval is not bigger than Maximum Connection Interval.
-    if ((p_conn_int->min_conn_interval != 0xffff) &&
-        (p_conn_int->max_conn_interval != 0xffff) &&
-        (p_conn_int->min_conn_interval > p_conn_int->max_conn_interval)
-        )
-    {
-        return NRF_ERROR_INVALID_PARAM;
-    }
-
-    return NRF_SUCCESS;
-}
-
-
-static uint32_t conn_int_encode(const ble_advdata_conn_int_t * p_conn_int,
-                                uint8_t                      * p_encoded_data,
-                                uint8_t                      * p_len)
-{
-    uint32_t err_code;
-
-    // Check for buffer overflow.
-    if ((*p_len) + ADV_DATA_OFFSET + 2 * sizeof(uint16_le_t) > BLE_GAP_ADV_MAX_SIZE)
-    {
-        return NRF_ERROR_DATA_SIZE;
-    }
-
-    // Check parameters.
-    err_code = conn_int_check(p_conn_int);
-    if (err_code != NRF_SUCCESS)
-    {
-        return err_code;
-    }
-
-    // Encode Length and AD Type.
-    p_encoded_data[(*p_len)++] = 1 + 2 * sizeof(uint16_le_t);
-    p_encoded_data[(*p_len)++] = BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE;
-
-    // Encode Minimum and Maximum Connection Intervals.
-    (*p_len) += uint16_encode(p_conn_int->min_conn_interval, &p_encoded_data[*p_len]);
-    (*p_len) += uint16_encode(p_conn_int->max_conn_interval, &p_encoded_data[*p_len]);
-
-    return NRF_SUCCESS;
-}
-
-
-static uint32_t manuf_specific_data_encode(const ble_advdata_manuf_data_t * p_manuf_sp_data,
-                                           uint8_t                        * p_encoded_data,
-                                           uint8_t                        * p_len)
-{
-    uint8_t data_size = sizeof(uint16_le_t) + p_manuf_sp_data->data.size;
-
-    // Check for buffer overflow.
-    if ((*p_len) + ADV_DATA_OFFSET + data_size > BLE_GAP_ADV_MAX_SIZE)
-    {
-        return NRF_ERROR_DATA_SIZE;
-    }
-
-    // Encode Length and AD Type.
-    p_encoded_data[(*p_len)++] = 1 + data_size;
-    p_encoded_data[(*p_len)++] = BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA;
-    
-    // Encode Company Identifier.
-    (*p_len) += uint16_encode(p_manuf_sp_data->company_identifier, &p_encoded_data[*p_len]);
-    
-    // Encode additional manufacturer specific data.
-    if (p_manuf_sp_data->data.size > 0)
-    {
-        if (p_manuf_sp_data->data.p_data == NULL)
-        {
-            return NRF_ERROR_INVALID_PARAM;
-        }
-        memcpy(&p_encoded_data[*p_len], p_manuf_sp_data->data.p_data, p_manuf_sp_data->data.size);
-        (*p_len) += p_manuf_sp_data->data.size;
-    }
-
-    return NRF_SUCCESS;
-}
-
-
-static uint32_t service_data_encode(const ble_advdata_t * p_advdata,
-                                    uint8_t             * p_encoded_data,
-                                    uint8_t             * p_len)
-{
-    uint8_t i;
-
-    // Check parameter consistency.
-    if (p_advdata->p_service_data_array == NULL)
-    {
-        return NRF_ERROR_INVALID_PARAM;
-    }
-
-    for (i = 0; i < p_advdata->service_data_count; i++)
-    {
-        ble_advdata_service_data_t * p_service_data;
-        uint8_t                      data_size;
-
-        p_service_data = &p_advdata->p_service_data_array[i];
-        data_size      = sizeof(uint16_le_t) + p_service_data->data.size;
-
-        // Encode Length and AD Type.
-        p_encoded_data[(*p_len)++] = 1 + data_size;
-        p_encoded_data[(*p_len)++] = BLE_GAP_AD_TYPE_SERVICE_DATA;
-
-        // Encode service UUID.
-        (*p_len) += uint16_encode(p_service_data->service_uuid, &p_encoded_data[*p_len]);
-
-        // Encode additional service data.
-        if (p_service_data->data.size > 0)
-        {
-            if (p_service_data->data.p_data == NULL)
-            {
-                return NRF_ERROR_INVALID_PARAM;
-            }
-            memcpy(&p_encoded_data[*p_len], p_service_data->data.p_data, p_service_data->data.size);
-            (*p_len) += p_service_data->data.size;
-        }
-    }
-
-    return NRF_SUCCESS;
-}
-
-
-static uint32_t adv_data_encode(const ble_advdata_t * p_advdata,
-                                uint8_t             * p_encoded_data,
-                                uint8_t             * p_len)
-{
-    uint32_t err_code = NRF_SUCCESS;
-
-    *p_len = 0;
-
-    // Encode name.
-    if (p_advdata->name_type != BLE_ADVDATA_NO_NAME)
-    {
-        err_code = name_encode(p_advdata, p_encoded_data, p_len);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-    }
-
-    // Encode appearance.
-    if (p_advdata->include_appearance)
-    {
-        err_code = appearance_encode(p_encoded_data, p_len);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-    }
-
-    // Encode flags.
-    if (p_advdata->flags.size > 0)
-    {
-        err_code = uint8_array_encode(&p_advdata->flags,
-                                      BLE_GAP_AD_TYPE_FLAGS,
-                                      p_encoded_data,
-                                      p_len);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-    }
-
-    // Encode TX power level.
-    if (p_advdata->p_tx_power_level != NULL)
-    {
-        err_code = tx_power_level_encode(*p_advdata->p_tx_power_level, p_encoded_data, p_len);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-    }
-    
-    // Encode 'more available' uuid list.
-    if (p_advdata->uuids_more_available.uuid_cnt > 0)
-    {
-        err_code = uuid_list_encode(&p_advdata->uuids_more_available,
-                                    BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE,
-                                    BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE,
-                                    p_encoded_data,
-                                    p_len);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-    }
-
-    // Encode 'complete' uuid list.
-    if (p_advdata->uuids_complete.uuid_cnt > 0)
-    {
-        err_code = uuid_list_encode(&p_advdata->uuids_complete,
-                                    BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE,
-                                    BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE,
-                                    p_encoded_data,
-                                    p_len);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-    }
-
-    // Encode 'solicited service' uuid list.
-    if (p_advdata->uuids_solicited.uuid_cnt > 0)
-    {
-        err_code = uuid_list_encode(&p_advdata->uuids_solicited,
-                                    BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT,
-                                    BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT,
-                                    p_encoded_data,
-                                    p_len);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-    }
-
-    // Encode Slave Connection Interval Range.
-    if (p_advdata->p_slave_conn_int != NULL)
-    {
-        err_code = conn_int_encode(p_advdata->p_slave_conn_int, p_encoded_data, p_len);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-    }
-
-    // Encode Manufacturer Specific Data.
-    if (p_advdata->p_manuf_specific_data != NULL)
-    {
-        err_code = manuf_specific_data_encode(p_advdata->p_manuf_specific_data,
-                                              p_encoded_data,
-                                              p_len);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-    }
-
-    // Encode Service Data.
-    if (p_advdata->service_data_count > 0)
-    {
-        err_code = service_data_encode(p_advdata, p_encoded_data, p_len);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-    }
-
-    return err_code;
-}
-
-
-static uint32_t advdata_check(const ble_advdata_t * p_advdata)
-{
-    // Flags must be included in advertising data, and the BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED flag must be set.
-    if ((p_advdata->flags.size == 0)      ||
-        (p_advdata->flags.p_data == NULL) ||
-        ((p_advdata->flags.p_data[0] & BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) == 0)
-       )
-    {
-        return NRF_ERROR_INVALID_PARAM;
-    }
-
-    return NRF_SUCCESS;
-}
-
-
-static uint32_t srdata_check(const ble_advdata_t * p_srdata)
-{
-    // Flags shall not be included in the scan response data.
-    if (p_srdata->flags.size > 0)
-    {
-        return NRF_ERROR_INVALID_PARAM;
-    }
-
-    return NRF_SUCCESS;
-}
-
-
-uint32_t ble_advdata_set(const ble_advdata_t * p_advdata, const ble_advdata_t * p_srdata)
-{
-    uint32_t  err_code;
-    uint8_t   len_advdata = 0;
-    uint8_t   len_srdata  = 0;
-    uint8_t   encoded_advdata[BLE_GAP_ADV_MAX_SIZE];
-    uint8_t   encoded_srdata[BLE_GAP_ADV_MAX_SIZE];
-    uint8_t * p_encoded_advdata;
-    uint8_t * p_encoded_srdata;
-
-    // Encode advertising data (if supplied).
-    if (p_advdata != NULL)
-    {
-        err_code = advdata_check(p_advdata);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-
-        err_code = adv_data_encode(p_advdata, encoded_advdata, &len_advdata);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-        p_encoded_advdata = encoded_advdata;
-    }
-    else
-    {
-        p_encoded_advdata = NULL;
-    }
-
-    // Encode scan response data (if supplied).
-    if (p_srdata != NULL)
-    {
-        err_code = srdata_check(p_srdata);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-
-        err_code = adv_data_encode(p_srdata, encoded_srdata, &len_srdata);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-        p_encoded_srdata = encoded_srdata;
-    }
-    else
-    {
-        p_encoded_srdata = NULL;
-    }
-
-    // Pass encoded advertising data and/or scan response data to the stack.
-    return sd_ble_gap_adv_data_set(p_encoded_advdata, len_advdata, p_encoded_srdata, len_srdata);
-}
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/common/ble_advdata.h
--- a/nRF51822/nordic-sdk/components/ble/common/ble_advdata.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_lib_advdata Advertising Data Encoder
- * @{
- * @ingroup ble_sdk_lib
- * @brief Function for encoding the advertising data and/or scan response data, and passing them to
- *        the stack.
- */
-
-#ifndef BLE_ADVDATA_H__
-#define BLE_ADVDATA_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <string.h>
-#include "ble.h"
-#include "app_util.h"
-
-/**@brief Advertising data name type. This contains the options available for the device name inside
- *        the advertising data. */
-typedef enum
-{
-    BLE_ADVDATA_NO_NAME,                                              /**< Include no device name in advertising data. */
-    BLE_ADVDATA_SHORT_NAME,                                           /**< Include short device name in advertising data. */
-    BLE_ADVDATA_FULL_NAME                                             /**< Include full device name in advertising data. */
-} ble_advdata_name_type_t;
-
-/**@brief UUID list type. */
-typedef struct
-{
-    uint16_t                     uuid_cnt;                            /**< Number of UUID entries. */
-    ble_uuid_t *                 p_uuids;                             /**< Pointer to UUID array entries. */
-} ble_advdata_uuid_list_t;
-
-/**@brief Connection interval range structure. */
-typedef struct
-{
-    uint16_t                     min_conn_interval;                   /**< Minimum Connection Interval, in units of 1.25ms, range 6 to 3200 (i.e. 7.5ms to 4s). */
-    uint16_t                     max_conn_interval;                   /**< Maximum Connection Interval, in units of 1.25ms, range 6 to 3200 (i.e. 7.5ms to 4s). Value of 0xFFFF indicates no specific maximum. */
-} ble_advdata_conn_int_t;
-
-/**@brief Manufacturer specific data structure. */
-typedef struct
-{
-    uint16_t                     company_identifier;                  /**< Company Identifier Code. */
-    uint8_array_t                data;                                /**< Additional manufacturer specific data. */
-} ble_advdata_manuf_data_t;
-
-/**@brief Service data structure. */
-typedef struct
-{
-    uint16_t                     service_uuid;                        /**< Service UUID. */
-    uint8_array_t                data;                                /**< Additional service data. */
-} ble_advdata_service_data_t;
-
-/**@brief Advertising data structure. This contains all options and data needed for encoding and
- *        setting the advertising data. */
-typedef struct
-{
-    ble_advdata_name_type_t      name_type;                           /**< Type of device name. */
-    uint8_t                      short_name_len;                      /**< Length of short device name (if short type is specified). */
-    bool                         include_appearance;                  /**< Determines if Appearance shall be included. */
-    uint8_array_t                flags;                               /**< Advertising data Flags field. */
-    int8_t *                     p_tx_power_level;                    /**< TX Power Level field. */
-    ble_advdata_uuid_list_t      uuids_more_available;                /**< List of UUIDs in the 'More Available' list. */
-    ble_advdata_uuid_list_t      uuids_complete;                      /**< List of UUIDs in the 'Complete' list. */
-    ble_advdata_uuid_list_t      uuids_solicited;                     /**< List of solcited UUIDs. */
-    ble_advdata_conn_int_t *     p_slave_conn_int;                    /**< Slave Connection Interval Range. */
-    ble_advdata_manuf_data_t *   p_manuf_specific_data;               /**< Manufacturer specific data. */
-    ble_advdata_service_data_t * p_service_data_array;                /**< Array of Service data structures. */
-    uint8_t                      service_data_count;                  /**< Number of Service data structures. */
-} ble_advdata_t;
-
-/**@brief Function for encoding and setting the advertising data and/or scan response data.
- *
- * @details This function encodes advertising data and/or scan response data based on the selections
- *          in the supplied structures, and passes the encoded data to the stack.
- *
- * @param[in]   p_advdata   Structure for specifying the content of the advertising data.
- *                          Set to NULL if advertising data is not to be set.
- * @param[in]   p_srdata    Structure for specifying the content of the scan response data.
- *                          Set to NULL if scan response data is not to be set.
- *
- * @return      NRF_SUCCESS on success, NRF_ERROR_DATA_SIZE if not all the requested data could fit
- *              into the advertising packet. The maximum size of the advertisement packet is @ref
- *              BLE_GAP_ADV_MAX_SIZE.
- *
- * @warning This API may override application's request to use the long name and use a short name
- * instead. This truncation will occur in case the long name does not fit advertisement data size.
- * Application is permitted to specify a preferred short name length in case truncation is required.
- * For example, if the complete device name is ABCD_HRMonitor, application can specify short name 
- * length to 8 such that short device name appears as ABCD_HRM instead of ABCD_HRMo or ABCD_HRMoni
- * etc if available size for short name is 9 or 12 respectively to have more apporpriate short name.
- * However, it should be noted that this is just a preference that application can specify and
- * if the preference too large to fit in Advertisement Data, this can be further truncated. 
- */
-uint32_t ble_advdata_set(const ble_advdata_t * p_advdata, const ble_advdata_t * p_srdata);
-
-#endif // BLE_ADVDATA_H__
-
-/** @} */
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/common/ble_advdata_parser.c
--- a/nRF51822/nordic-sdk/components/ble/common/ble_advdata_parser.c	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,24 +0,0 @@
-#include "ble_advdata_parser.h"
-
-uint32_t ble_advdata_parser_field_find(uint8_t    type,
-                                       uint8_t  * p_advdata,
-                                       uint8_t  * len,
-                                       uint8_t ** pp_field_data)
-{
-    uint32_t index = 0;
-
-    while (index < *len)
-    {
-        uint8_t field_length = p_advdata[index];
-        uint8_t field_type   = p_advdata[index + 1];
-
-        if (field_type == type)
-        {
-            *pp_field_data = &p_advdata[index + 2];
-            *len           = field_length - 1;
-            return NRF_SUCCESS;
-        }
-        index += field_length + 1;
-    }
-    return NRF_ERROR_NOT_FOUND;
-}
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/common/ble_advdata_parser.h
--- a/nRF51822/nordic-sdk/components/ble/common/ble_advdata_parser.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,9 +0,0 @@
-#ifndef BLE_ADVDATA_PARSER_H_
-#define BLE_ADVDATA_PARSER_H_
-
-#include "ble_advdata.h"
-
-uint32_t ble_advdata_parse(uint8_t * p_data, uint8_t len, ble_advdata_t * advdata);
-uint32_t ble_advdata_parser_field_find(uint8_t type, uint8_t * p_advdata, uint8_t * len, uint8_t ** pp_field_data);
-
-#endif
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/common/ble_conn_params.cpp
--- a/nRF51822/nordic-sdk/components/ble/common/ble_conn_params.cpp	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,361 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#include "ble_conn_params.h"
-#include <stdlib.h>
-#include "nordic_common.h"
-#include "ble_hci.h"
-#include "ble_srv_common.h"
-#include "app_util.h"
-
-#ifdef USE_APP_TIMER
-#include "app_timer.h"
-#else
-#include "mbed.h"
-#endif
-
-static ble_conn_params_init_t m_conn_params_config;     /**< Configuration as specified by the application. */
-static ble_gap_conn_params_t  m_preferred_conn_params;  /**< Connection parameters preferred by the application. */
-static uint8_t                m_update_count;           /**< Number of Connection Parameter Update messages that has currently been sent. */
-static uint16_t               m_conn_handle;            /**< Current connection handle. */
-static ble_gap_conn_params_t  m_current_conn_params;    /**< Connection parameters received in the most recent Connect event. */
-#ifdef USE_APP_TIMER
-static app_timer_id_t         m_conn_params_timer_id;   /**< Connection parameters timer. */
-#else
-static Ticker                 m_conn_params_timer;
-#endif
-
-static bool m_change_param = false;
-
-static bool is_conn_params_ok(ble_gap_conn_params_t * p_conn_params)
-{
-    // Check if interval is within the acceptable range.
-    // NOTE: Using max_conn_interval in the received event data because this contains
-    //       the client's connection interval.
-    if (
-        (p_conn_params->max_conn_interval >= m_preferred_conn_params.min_conn_interval)
-        && 
-        (p_conn_params->max_conn_interval <= m_preferred_conn_params.max_conn_interval)
-       )
-    {
-        return true;
-    }
-    else
-    {
-        return false;
-    }
-}
-
-
-#ifdef USE_APP_TIMER
-static void update_timeout_handler(void * p_context)
-{
-    UNUSED_PARAMETER(p_context);
-
-#else /* #if !USE_APP_TIMER */
-static void update_timeout_handler(void)
-{
-    m_conn_params_timer.detach(); /* this is supposed to be a single-shot timer callback */
-#endif /* #if !USE_APP_TIMER */
-    if (m_conn_handle != BLE_CONN_HANDLE_INVALID)
-    {
-        // Check if we have reached the maximum number of attempts
-        m_update_count++;
-        if (m_update_count <= m_conn_params_config.max_conn_params_update_count)
-        {
-            uint32_t err_code;
-
-            // Parameters are not ok, send connection parameters update request.
-            err_code = sd_ble_gap_conn_param_update(m_conn_handle, &m_preferred_conn_params);
-            if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL))
-            {
-                m_conn_params_config.error_handler(err_code);
-            }
-        }
-        else
-        {
-            m_update_count = 0;
-
-            // Negotiation failed, disconnect automatically if this has been configured
-            if (m_conn_params_config.disconnect_on_fail)
-            {
-                uint32_t err_code;
-
-                err_code = sd_ble_gap_disconnect(m_conn_handle, BLE_HCI_CONN_INTERVAL_UNACCEPTABLE);
-                if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL))
-                {
-                    m_conn_params_config.error_handler(err_code);
-                }
-            }
-
-            // Notify the application that the procedure has failed
-            if (m_conn_params_config.evt_handler != NULL)
-            {
-                ble_conn_params_evt_t evt;
-
-                evt.evt_type = BLE_CONN_PARAMS_EVT_FAILED;
-                m_conn_params_config.evt_handler(&evt);
-            }
-        }
-    }
-}
-
-
-uint32_t ble_conn_params_init(const ble_conn_params_init_t * p_init)
-{
-    uint32_t err_code;
-
-    m_conn_params_config = *p_init;
-    m_change_param = false;
-    if (p_init->p_conn_params != NULL)
-    {
-        m_preferred_conn_params = *p_init->p_conn_params;
-
-        // Set the connection params in stack
-        err_code = sd_ble_gap_ppcp_set(&m_preferred_conn_params);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-    }
-    else
-    {
-        // Fetch the connection params from stack
-        err_code = sd_ble_gap_ppcp_get(&m_preferred_conn_params);
-        if (err_code != NRF_SUCCESS)
-        {
-            return err_code;
-        }
-    }
-
-    m_conn_handle  = BLE_CONN_HANDLE_INVALID;
-    m_update_count = 0;
-
-#ifdef USE_APP_TIMER
-    return app_timer_create(&m_conn_params_timer_id,
-                            APP_TIMER_MODE_SINGLE_SHOT,
-                            update_timeout_handler);
-#else
-    return NRF_SUCCESS;
-#endif
-}
-
-
-uint32_t ble_conn_params_stop(void)
-{
-#ifdef USE_APP_TIMER
-    return app_timer_stop(m_conn_params_timer_id);
-#else /* #if !USE_APP_TIMER */
-    m_conn_params_timer.detach();
-    return NRF_SUCCESS;
-#endif /* #if !USE_APP_TIMER */
-}
-
-
-static void conn_params_negotiation(void)
-{
-    // Start negotiation if the received connection parameters are not acceptable
-    if (!is_conn_params_ok(&m_current_conn_params))
-    {
-#ifdef USE_APP_TIMER
-        uint32_t err_code;
-#endif
-        uint32_t timeout_ticks;
-
-        if (m_change_param)
-        {
-            // Notify the application that the procedure has failed
-            if (m_conn_params_config.evt_handler != NULL)
-            {
-                ble_conn_params_evt_t evt;
-
-                evt.evt_type = BLE_CONN_PARAMS_EVT_FAILED;
-                m_conn_params_config.evt_handler(&evt);
-            }
-        }
-        else
-        {
-            if (m_update_count == 0)
-            {
-                // First connection parameter update
-                timeout_ticks = m_conn_params_config.first_conn_params_update_delay;
-            }
-            else
-            {
-                timeout_ticks = m_conn_params_config.next_conn_params_update_delay;
-            }
-
-#ifdef USE_APP_TIMER
-            err_code = app_timer_start(m_conn_params_timer_id, timeout_ticks, NULL);
-            if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL))
-            {
-                m_conn_params_config.error_handler(err_code);
-            }
-#else
-            m_conn_params_timer.attach(update_timeout_handler, timeout_ticks / 32768);
-#endif
-        }
-    }
-    else
-    {
-        // Notify the application that the procedure has succeded
-        if (m_conn_params_config.evt_handler != NULL)
-        {
-            ble_conn_params_evt_t evt;
-
-            evt.evt_type = BLE_CONN_PARAMS_EVT_SUCCEEDED;
-            m_conn_params_config.evt_handler(&evt);
-        }
-    }
-    m_change_param = false;
-}
-
-
-static void on_connect(ble_evt_t * p_ble_evt)
-{
-    // Save connection parameters
-    m_conn_handle         = p_ble_evt->evt.gap_evt.conn_handle;
-    m_current_conn_params = p_ble_evt->evt.gap_evt.params.connected.conn_params;
-    m_update_count        = 0;  // Connection parameter negotiation should re-start every connection
-
-    // Check if we shall handle negotiation on connect
-    if (m_conn_params_config.start_on_notify_cccd_handle == BLE_GATT_HANDLE_INVALID)
-    {
-        conn_params_negotiation();
-    }
-}
-
-
-static void on_disconnect(ble_evt_t * p_ble_evt)
-{
-#ifdef USE_APP_TIMER
-    uint32_t err_code;
-#endif
-
-    m_conn_handle = BLE_CONN_HANDLE_INVALID;
-
-    // Stop timer if running
-    m_update_count = 0; // Connection parameters updates should happen during every connection
-
-#ifdef USE_APP_TIMER
-    err_code = app_timer_stop(m_conn_params_timer_id);
-    if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL))
-    {
-        m_conn_params_config.error_handler(err_code);
-    }
-#else
-    m_conn_params_timer.detach();
-#endif
-}
-
-
-static void on_write(ble_evt_t * p_ble_evt)
-{
-    ble_gatts_evt_write_t * p_evt_write = &p_ble_evt->evt.gatts_evt.params.write;
-
-    // Check if this the correct CCCD
-    if (
-        (p_evt_write->handle == m_conn_params_config.start_on_notify_cccd_handle)
-        &&
-        (p_evt_write->len == 2)
-       )
-    {
-        // Check if this is a 'start notification'
-        if (ble_srv_is_notification_enabled(p_evt_write->data))
-        {
-            // Do connection parameter negotiation if necessary
-            conn_params_negotiation();
-        }
-        else
-        {
-#ifdef USE_APP_TIMER
-            uint32_t err_code;
-
-            // Stop timer if running
-            err_code = app_timer_stop(m_conn_params_timer_id);
-            if ((err_code != NRF_SUCCESS) && (m_conn_params_config.error_handler != NULL))
-            {
-                m_conn_params_config.error_handler(err_code);
-            }
-#else /* #if !USE_APP_TIMER */
-            m_conn_params_timer.detach();
-#endif /* #if !USE_APP_TIMER */
-        }
-    }
-}
-
-
-static void on_conn_params_update(ble_evt_t * p_ble_evt)
-{
-    // Copy the parameters
-    m_current_conn_params = p_ble_evt->evt.gap_evt.params.conn_param_update.conn_params;
-
-    conn_params_negotiation();
-}
-
-
-void ble_conn_params_on_ble_evt(ble_evt_t * p_ble_evt)
-{
-    switch (p_ble_evt->header.evt_id)
-    {
-        case BLE_GAP_EVT_CONNECTED:
-            on_connect(p_ble_evt);
-            break;
-
-        case BLE_GAP_EVT_DISCONNECTED:
-            on_disconnect(p_ble_evt);
-            break;
-
-        case BLE_GATTS_EVT_WRITE:
-            on_write(p_ble_evt);
-            break;
-
-        case BLE_GAP_EVT_CONN_PARAM_UPDATE:
-            on_conn_params_update(p_ble_evt);
-            break;
-
-        default:
-            // No implementation needed.
-            break;
-    }
-}
-
-uint32_t ble_conn_params_change_conn_params(ble_gap_conn_params_t *new_params)
-{
-    uint32_t err_code;
-
-    m_preferred_conn_params = *new_params;
-    // Set the connection params in stack
-    err_code = sd_ble_gap_ppcp_set(&m_preferred_conn_params);
-    if (err_code == NRF_SUCCESS)
-    {
-        if (!is_conn_params_ok(&m_current_conn_params))
-        {
-            m_change_param = true;
-            err_code = sd_ble_gap_conn_param_update(m_conn_handle, &m_preferred_conn_params);
-            m_update_count = 1;
-        }
-        else
-        {
-            // Notify the application that the procedure has succeded
-            if (m_conn_params_config.evt_handler != NULL)
-            {
-                ble_conn_params_evt_t evt;
-
-                evt.evt_type = BLE_CONN_PARAMS_EVT_SUCCEEDED;
-                m_conn_params_config.evt_handler(&evt);
-            }
-            err_code = NRF_SUCCESS;
-        }
-    }
-    return err_code;
-}
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/common/ble_conn_params.h
--- a/nRF51822/nordic-sdk/components/ble/common/ble_conn_params.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,119 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_lib_conn_params Connection Parameters Negotiation
- * @{
- * @ingroup ble_sdk_lib
- * @brief Module for initiating and executing a connection parameters negotiation procedure.
- */
-
-#ifndef BLE_CONN_PARAMS_H__
-#define BLE_CONN_PARAMS_H__
-
-#include <stdint.h>
-#include "ble.h"
-#include "ble_srv_common.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**@brief Connection Parameters Module event type. */
-typedef enum
-{
-    BLE_CONN_PARAMS_EVT_FAILED   ,                                  /**< Negotiation procedure failed. */
-    BLE_CONN_PARAMS_EVT_SUCCEEDED                                   /**< Negotiation procedure succeeded. */
-} ble_conn_params_evt_type_t;
-
-/**@brief Connection Parameters Module event. */
-typedef struct
-{
-    ble_conn_params_evt_type_t evt_type;                            /**< Type of event. */
-} ble_conn_params_evt_t;
-
-/**@brief Connection Parameters Module event handler type. */
-typedef void (*ble_conn_params_evt_handler_t) (ble_conn_params_evt_t * p_evt);
-
-/**@brief Connection Parameters Module init structure. This contains all options and data needed for
- *        initialization of the connection parameters negotiation module. */
-typedef struct
-{
-    ble_gap_conn_params_t *       p_conn_params;                    /**< Pointer to the connection parameters desired by the application. When calling ble_conn_params_init, if this parameter is set to NULL, the connection parameters will be fetched from host. */
-    uint32_t                      first_conn_params_update_delay;   /**< Time from initiating event (connect or start of notification) to first time sd_ble_gap_conn_param_update is called (in number of timer ticks). */
-    uint32_t                      next_conn_params_update_delay;    /**< Time between each call to sd_ble_gap_conn_param_update after the first (in number of timer ticks). Recommended value 30 seconds as per BLUETOOTH SPECIFICATION Version 4.0. */
-    uint8_t                       max_conn_params_update_count;     /**< Number of attempts before giving up the negotiation. */
-    uint16_t                      start_on_notify_cccd_handle;      /**< If procedure is to be started when notification is started, set this to the handle of the corresponding CCCD. Set to BLE_GATT_HANDLE_INVALID if procedure is to be started on connect event. */
-    bool                          disconnect_on_fail;               /**< Set to TRUE if a failed connection parameters update shall cause an automatic disconnection, set to FALSE otherwise. */
-    ble_conn_params_evt_handler_t evt_handler;                      /**< Event handler to be called for handling events in the Connection Parameters. */
-    ble_srv_error_handler_t       error_handler;                    /**< Function to be called in case of an error. */
-} ble_conn_params_init_t;
-
-
-/**@brief Function for initializing the Connection Parameters module.
- *
- * @note If the negotiation procedure should be triggered when notification/indication of
- *       any characteristic is enabled by the peer, then this function must be called after
- *       having initialized the services.
- *
- * @param[in]   p_init  This contains information needed to initialize this module.
- *
- * @return      NRF_SUCCESS on successful initialization, otherwise an error code.
- */
-uint32_t ble_conn_params_init(const ble_conn_params_init_t * p_init);
-
-/**@brief Function for stopping the Connection Parameters module.
- *
- * @details This function is intended to be used by the application to clean up the connection
- *          parameters update module. This will stop the connection parameters update timer if
- *          running, thereby preventing any impending connection parameters update procedure. This
- *          function must be called by the application when it needs to clean itself up (for
- *          example, before disabling the bluetooth SoftDevice) so that an unwanted timer expiry
- *          event can be avoided.
- *
- * @return      NRF_SUCCESS on successful initialization, otherwise an error code.
- */
-uint32_t ble_conn_params_stop(void);
-
-/**@brief Function for changing the current connection parameters to a new set.
- *
- *  @details Use this function to change the connection parameters to a new set of parameter
- *       (ie different from the ones given at init of the module).
- *       This function is usefull for scenario where most of the time the application
- *       needs a relatively big connection interval, and just sometimes, for a temporary
- *       period requires shorter connection interval, for example to transfer a higher
- *       amount of data.
- *       If the given parameters does not match the current connection's parameters
- *       this function initiates a new negotiation.
- *
- * @param[in]   new_params  This contains the new connections parameters to setup.
- *
- * @return      NRF_SUCCESS on successful initialization, otherwise an error code.
- */
-uint32_t ble_conn_params_change_conn_params(ble_gap_conn_params_t *new_params);
-
-/**@brief Function for handling the Application's BLE Stack events.
- *
- * @details Handles all events from the BLE stack that are of interest to this module.
- *
- * @param[in]   p_ble_evt  The event received from the BLE stack.
- */
-void ble_conn_params_on_ble_evt(ble_evt_t * p_ble_evt);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // BLE_CONN_PARAMS_H__
-
-/** @} */
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/common/ble_date_time.h
--- a/nRF51822/nordic-sdk/components/ble/common/ble_date_time.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,76 +0,0 @@
-/* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved.
-*
-* The information contained herein is property of Nordic Semiconductor ASA.
-* Terms and conditions of usage are described in detail in NORDIC
-* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
-*
-* Licensees are granted free, non-transferable use of the information. NO
-* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
-* the file.
-*/
-
-/* Attention! 
-*  To maintain compliance with Nordic Semiconductor ASA’s Bluetooth profile 
-*  qualification listings, this section of source code must not be modified.
-*/
-
-/** @file
- * @brief Contains definition of ble_date_time structure.
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_date_time BLE Date Time characteristic type
- * @{
- * @ingroup ble_sdk_lib
- * @brief Definition of ble_date_time_t type.
- */
-
-#ifndef BLE_DATE_TIME_H__
-#define BLE_DATE_TIME_H__
-
-#include <stdint.h>
-
-/**@brief Date and Time structure. */
-typedef struct
-{
-    uint16_t year;
-    uint8_t  month;
-    uint8_t  day;
-    uint8_t  hours;
-    uint8_t  minutes;
-    uint8_t  seconds;
-} ble_date_time_t;
-
-static __INLINE uint8_t ble_date_time_encode(const ble_date_time_t * p_date_time,
-                                             uint8_t *               p_encoded_data)
-{
-    uint8_t len = uint16_encode(p_date_time->year, p_encoded_data);
-    
-    p_encoded_data[len++] = p_date_time->month;
-    p_encoded_data[len++] = p_date_time->day;
-    p_encoded_data[len++] = p_date_time->hours;
-    p_encoded_data[len++] = p_date_time->minutes;
-    p_encoded_data[len++] = p_date_time->seconds;
-    
-    return len;
-}
-
-static __INLINE uint8_t ble_date_time_decode(ble_date_time_t * p_date_time,
-                                             const uint8_t *   p_encoded_data)
-{
-    uint8_t len = sizeof(uint16_t);
-    
-    p_date_time->year    = uint16_decode(p_encoded_data);
-    p_date_time->month   = p_encoded_data[len++];
-    p_date_time->day     = p_encoded_data[len++]; 
-    p_date_time->hours   = p_encoded_data[len++];
-    p_date_time->minutes = p_encoded_data[len++];
-    p_date_time->seconds = p_encoded_data[len++];
-    
-    return len;
-}
-
-#endif // BLE_DATE_TIME_H__
-
-/** @} */
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/common/ble_sensor_location.h
--- a/nRF51822/nordic-sdk/components/ble/common/ble_sensor_location.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
- /* Attention!
-*  To maintain compliance with Nordic Semiconductor ASA’s Bluetooth profile
-*  qualification listings, this section of source code must not be modified.
-*/
- 
-#ifndef BLE_SENSOR_LOCATION_H__
-#define BLE_SENSOR_LOCATION_H__
-
-typedef enum {
-    BLE_SENSOR_LOCATION_OTHER        = 0 ,  /**<-- Other        */
-    BLE_SENSOR_LOCATION_TOP_OF_SHOE  = 1 ,  /**<-- Top of shoe  */
-    BLE_SENSOR_LOCATION_IN_SHOE      = 2 ,  /**<-- In shoe      */
-    BLE_SENSOR_LOCATION_HIP          = 3 ,  /**<-- Hip          */
-    BLE_SENSOR_LOCATION_FRONT_WHEEL  = 4 ,  /**<-- Front Wheel  */
-    BLE_SENSOR_LOCATION_LEFT_CRANK   = 5 ,  /**<-- Left Crank   */
-    BLE_SENSOR_LOCATION_RIGHT_CRANK  = 6 ,  /**<-- Right Crank  */
-    BLE_SENSOR_LOCATION_LEFT_PEDAL   = 7 ,  /**<-- Left Pedal   */
-    BLE_SENSOR_LOCATION_RIGHT_PEDAL  = 8 ,  /**<-- Right Pedal  */
-    BLE_SENSOR_LOCATION_FRONT_HUB    = 9 ,  /**<-- Front Hub    */
-    BLE_SENSOR_LOCATION_REAR_DROPOUT = 10,  /**<-- Rear Dropout */
-    BLE_SENSOR_LOCATION_CHAINSTAY    = 11,  /**<-- Chainstay    */
-    BLE_SENSOR_LOCATION_REAR_WHEEL   = 12,  /**<-- Rear Wheel   */
-    BLE_SENSOR_LOCATION_REAR_HUB     = 13,  /**<-- Rear Hub     */
-}ble_sensor_location_t;
-
-#define BLE_NB_MAX_SENSOR_LOCATIONS 14
-
-#endif // BLE_SENSOR_LOCATION_H__
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/common/ble_srv_common.c
--- a/nRF51822/nordic-sdk/components/ble/common/ble_srv_common.c	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/* Attention! 
-*  To maintain compliance with Nordic Semiconductor ASA’s Bluetooth profile 
-*  qualification listings, this section of source code must not be modified.
-*/
-
-#include "ble_srv_common.h"
-#include <string.h>
-#include "nordic_common.h"
-#include "app_error.h"
-
-
-uint8_t ble_srv_report_ref_encode(uint8_t                    * p_encoded_buffer,
-                                  const ble_srv_report_ref_t * p_report_ref)
-{
-    uint8_t len = 0;
-
-    p_encoded_buffer[len++] = p_report_ref->report_id;
-    p_encoded_buffer[len++] = p_report_ref->report_type;
-
-    APP_ERROR_CHECK_BOOL(len == BLE_SRV_ENCODED_REPORT_REF_LEN);
-    return len;
-}
-
-
-void ble_srv_ascii_to_utf8(ble_srv_utf8_str_t * p_utf8, char * p_ascii)
-{
-    p_utf8->length = (uint16_t)strlen(p_ascii);
-    p_utf8->p_str  = (uint8_t *)p_ascii;
-}
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/common/ble_srv_common.h
--- a/nRF51822/nordic-sdk/components/ble/common/ble_srv_common.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,230 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_sdk_srv_common Common service definitions
- * @{
- * @ingroup ble_sdk_srv
- * @brief Constants, type definitions and functions that are common to all services.
- */
-
-#ifndef BLE_SRV_COMMON_H__
-#define BLE_SRV_COMMON_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "ble_types.h"
-#include "app_util.h"
-#include "ble_gap.h"
-#include "ble_gatt.h"
-
-/** @defgroup UUID_SERVICES Service UUID definitions
- * @{ */
-#define BLE_UUID_ALERT_NOTIFICATION_SERVICE                      0x1811     /**< Alert Notification service UUID. */
-#define BLE_UUID_BATTERY_SERVICE                                 0x180F     /**< Battery service UUID. */
-#define BLE_UUID_BLOOD_PRESSURE_SERVICE                          0x1810     /**< Blood Pressure service UUID. */
-#define BLE_UUID_CURRENT_TIME_SERVICE                            0x1805     /**< Current Time service UUID. */
-#define BLE_UUID_CYCLING_SPEED_AND_CADENCE                       0x1816     /**< Cycling Speed and Cadence service UUID. */
-#define BLE_UUID_DEVICE_INFORMATION_SERVICE                      0x180A     /**< Device Information service UUID. */
-#define BLE_UUID_GLUCOSE_SERVICE                                 0x1808     /**< Glucose service UUID. */
-#define BLE_UUID_HEALTH_THERMOMETER_SERVICE                      0x1809     /**< Health Thermometer service UUID. */
-#define BLE_UUID_HEART_RATE_SERVICE                              0x180D     /**< Heart Rate service UUID. */
-#define BLE_UUID_HUMAN_INTERFACE_DEVICE_SERVICE                  0x1812     /**< Human Interface Device service UUID. */
-#define BLE_UUID_IMMEDIATE_ALERT_SERVICE                         0x1802     /**< Immediate Alert service UUID. */
-#define BLE_UUID_LINK_LOSS_SERVICE                               0x1803     /**< Link Loss service UUID. */
-#define BLE_UUID_NEXT_DST_CHANGE_SERVICE                         0x1807     /**< Next Dst Change service UUID. */
-#define BLE_UUID_PHONE_ALERT_STATUS_SERVICE                      0x180E     /**< Phone Alert Status service UUID. */
-#define BLE_UUID_REFERENCE_TIME_UPDATE_SERVICE                   0x1806     /**< Reference Time Update service UUID. */
-#define BLE_UUID_RUNNING_SPEED_AND_CADENCE                       0x1814     /**< Running Speed and Cadence service UUID. */
-#define BLE_UUID_SCAN_PARAMETERS_SERVICE                         0x1813     /**< Scan Parameters service UUID. */
-#define BLE_UUID_TX_POWER_SERVICE                                0x1804     /**< TX Power service UUID. */
-/** @} */
-
-/** @defgroup UUID_CHARACTERISTICS Characteristic UUID definitions
- * @{ */
-#define BLE_UUID_BATTERY_LEVEL_STATE_CHAR                        0x2A1B     /**< Battery Level State characteristic UUID. */
-#define BLE_UUID_BATTERY_POWER_STATE_CHAR                        0x2A1A     /**< Battery Power State characteristic UUID. */
-#define BLE_UUID_REMOVABLE_CHAR                                  0x2A3A     /**< Removable characteristic UUID. */
-#define BLE_UUID_SERVICE_REQUIRED_CHAR                           0x2A3B     /**< Service Required characteristic UUID. */
-#define BLE_UUID_ALERT_CATEGORY_ID_CHAR                          0x2A43     /**< Alert Category Id characteristic UUID. */
-#define BLE_UUID_ALERT_CATEGORY_ID_BIT_MASK_CHAR                 0x2A42     /**< Alert Category Id Bit Mask characteristic UUID. */
-#define BLE_UUID_ALERT_LEVEL_CHAR                                0x2A06     /**< Alert Level characteristic UUID. */
-#define BLE_UUID_ALERT_NOTIFICATION_CONTROL_POINT_CHAR           0x2A44     /**< Alert Notification Control Point characteristic UUID. */
-#define BLE_UUID_ALERT_STATUS_CHAR                               0x2A3F     /**< Alert Status characteristic UUID. */
-#define BLE_UUID_BATTERY_LEVEL_CHAR                              0x2A19     /**< Battery Level characteristic UUID. */
-#define BLE_UUID_BLOOD_PRESSURE_FEATURE_CHAR                     0x2A49     /**< Blood Pressure Feature characteristic UUID. */
-#define BLE_UUID_BLOOD_PRESSURE_MEASUREMENT_CHAR                 0x2A35     /**< Blood Pressure Measurement characteristic UUID. */
-#define BLE_UUID_BODY_SENSOR_LOCATION_CHAR                       0x2A38     /**< Body Sensor Location characteristic UUID. */
-#define BLE_UUID_BOOT_KEYBOARD_INPUT_REPORT_CHAR                 0x2A22     /**< Boot Keyboard Input Report characteristic UUID. */
-#define BLE_UUID_BOOT_KEYBOARD_OUTPUT_REPORT_CHAR                0x2A32     /**< Boot Keyboard Output Report characteristic UUID. */
-#define BLE_UUID_BOOT_MOUSE_INPUT_REPORT_CHAR                    0x2A33     /**< Boot Mouse Input Report characteristic UUID. */
-#define BLE_UUID_CURRENT_TIME_CHAR                               0x2A2B     /**< Current Time characteristic UUID. */
-#define BLE_UUID_DATE_TIME_CHAR                                  0x2A08     /**< Date Time characteristic UUID. */
-#define BLE_UUID_DAY_DATE_TIME_CHAR                              0x2A0A     /**< Day Date Time characteristic UUID. */
-#define BLE_UUID_DAY_OF_WEEK_CHAR                                0x2A09     /**< Day Of Week characteristic UUID. */
-#define BLE_UUID_DST_OFFSET_CHAR                                 0x2A0D     /**< Dst Offset characteristic UUID. */
-#define BLE_UUID_EXACT_TIME_256_CHAR                             0x2A0C     /**< Exact Time 256 characteristic UUID. */
-#define BLE_UUID_FIRMWARE_REVISION_STRING_CHAR                   0x2A26     /**< Firmware Revision String characteristic UUID. */
-#define BLE_UUID_GLUCOSE_FEATURE_CHAR                            0x2A51     /**< Glucose Feature characteristic UUID. */
-#define BLE_UUID_GLUCOSE_MEASUREMENT_CHAR                        0x2A18     /**< Glucose Measurement characteristic UUID. */
-#define BLE_UUID_GLUCOSE_MEASUREMENT_CONTEXT_CHAR                0x2A34     /**< Glucose Measurement Context characteristic UUID. */
-#define BLE_UUID_HARDWARE_REVISION_STRING_CHAR                   0x2A27     /**< Hardware Revision String characteristic UUID. */
-#define BLE_UUID_HEART_RATE_CONTROL_POINT_CHAR                   0x2A39     /**< Heart Rate Control Point characteristic UUID. */
-#define BLE_UUID_HEART_RATE_MEASUREMENT_CHAR                     0x2A37     /**< Heart Rate Measurement characteristic UUID. */
-#define BLE_UUID_HID_CONTROL_POINT_CHAR                          0x2A4C     /**< Hid Control Point characteristic UUID. */
-#define BLE_UUID_HID_INFORMATION_CHAR                            0x2A4A     /**< Hid Information characteristic UUID. */
-#define BLE_UUID_IEEE_REGULATORY_CERTIFICATION_DATA_LIST_CHAR    0x2A2A     /**< IEEE Regulatory Certification Data List characteristic UUID. */
-#define BLE_UUID_INTERMEDIATE_CUFF_PRESSURE_CHAR                 0x2A36     /**< Intermediate Cuff Pressure characteristic UUID. */
-#define BLE_UUID_INTERMEDIATE_TEMPERATURE_CHAR                   0x2A1E     /**< Intermediate Temperature characteristic UUID. */
-#define BLE_UUID_LOCAL_TIME_INFORMATION_CHAR                     0x2A0F     /**< Local Time Information characteristic UUID. */
-#define BLE_UUID_MANUFACTURER_NAME_STRING_CHAR                   0x2A29     /**< Manufacturer Name String characteristic UUID. */
-#define BLE_UUID_MEASUREMENT_INTERVAL_CHAR                       0x2A21     /**< Measurement Interval characteristic UUID. */
-#define BLE_UUID_MODEL_NUMBER_STRING_CHAR                        0x2A24     /**< Model Number String characteristic UUID. */
-#define BLE_UUID_UNREAD_ALERT_CHAR                               0x2A45     /**< Unread Alert characteristic UUID. */
-#define BLE_UUID_NEW_ALERT_CHAR                                  0x2A46     /**< New Alert characteristic UUID. */
-#define BLE_UUID_PNP_ID_CHAR                                     0x2A50     /**< PNP Id characteristic UUID. */
-#define BLE_UUID_PROTOCOL_MODE_CHAR                              0x2A4E     /**< Protocol Mode characteristic UUID. */
-#define BLE_UUID_RECORD_ACCESS_CONTROL_POINT_CHAR                0x2A52     /**< Record Access Control Point characteristic UUID. */
-#define BLE_UUID_REFERENCE_TIME_INFORMATION_CHAR                 0x2A14     /**< Reference Time Information characteristic UUID. */
-#define BLE_UUID_REPORT_CHAR                                     0x2A4D     /**< Report characteristic UUID. */
-#define BLE_UUID_REPORT_MAP_CHAR                                 0x2A4B     /**< Report Map characteristic UUID. */
-#define BLE_UUID_RINGER_CONTROL_POINT_CHAR                       0x2A40     /**< Ringer Control Point characteristic UUID. */
-#define BLE_UUID_RINGER_SETTING_CHAR                             0x2A41     /**< Ringer Setting characteristic UUID. */
-#define BLE_UUID_SCAN_INTERVAL_WINDOW_CHAR                       0x2A4F     /**< Scan Interval Window characteristic UUID. */
-#define BLE_UUID_SCAN_REFRESH_CHAR                               0x2A31     /**< Scan Refresh characteristic UUID. */
-#define BLE_UUID_SERIAL_NUMBER_STRING_CHAR                       0x2A25     /**< Serial Number String characteristic UUID. */
-#define BLE_UUID_SOFTWARE_REVISION_STRING_CHAR                   0x2A28     /**< Software Revision String characteristic UUID. */
-#define BLE_UUID_SUPPORTED_NEW_ALERT_CATEGORY_CHAR               0x2A47     /**< Supported New Alert Category characteristic UUID. */
-#define BLE_UUID_SUPPORTED_UNREAD_ALERT_CATEGORY_CHAR            0x2A48     /**< Supported Unread Alert Category characteristic UUID. */
-#define BLE_UUID_SYSTEM_ID_CHAR                                  0x2A23     /**< System Id characteristic UUID. */
-#define BLE_UUID_TEMPERATURE_MEASUREMENT_CHAR                    0x2A1C     /**< Temperature Measurement characteristic UUID. */
-#define BLE_UUID_TEMPERATURE_TYPE_CHAR                           0x2A1D     /**< Temperature Type characteristic UUID. */
-#define BLE_UUID_TIME_ACCURACY_CHAR                              0x2A12     /**< Time Accuracy characteristic UUID. */
-#define BLE_UUID_TIME_SOURCE_CHAR                                0x2A13     /**< Time Source characteristic UUID. */
-#define BLE_UUID_TIME_UPDATE_CONTROL_POINT_CHAR                  0x2A16     /**< Time Update Control Point characteristic UUID. */
-#define BLE_UUID_TIME_UPDATE_STATE_CHAR                          0x2A17     /**< Time Update State characteristic UUID. */
-#define BLE_UUID_TIME_WITH_DST_CHAR                              0x2A11     /**< Time With Dst characteristic UUID. */
-#define BLE_UUID_TIME_ZONE_CHAR                                  0x2A0E     /**< Time Zone characteristic UUID. */
-#define BLE_UUID_TX_POWER_LEVEL_CHAR                             0x2A07     /**< TX Power Level characteristic UUID. */
-#define BLE_UUID_CSC_FEATURE_CHAR                                0x2A5C     /**< Cycling Speed and Cadence Feature characteristic UUID. */
-#define BLE_UUID_CSC_MEASUREMENT_CHAR                            0x2A5B     /**< Cycling Speed and Cadence Measurement characteristic UUID. */
-#define BLE_UUID_RSC_FEATURE_CHAR                                0x2A54     /**< Running Speed and Cadence Feature characteristic UUID. */
-#define BLE_UUID_SC_CTRLPT_CHAR                                  0x2A55     /**< Speed and Cadence Control Point UUID. */
-#define BLE_UUID_RSC_MEASUREMENT_CHAR                            0x2A53     /**< Running Speed and Cadence Measurement characteristic UUID. */
-#define BLE_UUID_SENSOR_LOCATION_CHAR                            0x2A5D     /**< Sensor Location characteristic UUID. */
-#define BLE_UUID_EXTERNAL_REPORT_REF_DESCR                       0x2907     /**< External Report Reference descriptor UUID. */
-#define BLE_UUID_REPORT_REF_DESCR                                0x2908     /**< Report Reference descriptor UUID. */
-/** @} */
-
-/** @defgroup ALERT_LEVEL_VALUES Definitions for the Alert Level characteristic values
- * @{ */
-#define BLE_CHAR_ALERT_LEVEL_NO_ALERT                            0x00       /**< No Alert. */
-#define BLE_CHAR_ALERT_LEVEL_MILD_ALERT                          0x01       /**< Mild Alert. */
-#define BLE_CHAR_ALERT_LEVEL_HIGH_ALERT                          0x02       /**< High Alert. */
-/** @} */
-
-#define BLE_SRV_ENCODED_REPORT_REF_LEN                           2          /**< The length of an encoded Report Reference Descriptor. */
-#define BLE_CCCD_VALUE_LEN                                       2          /**< The length of a CCCD value. */
-
-/**@brief Type definition for error handler function which will be called in case of an error in
- *        a service or a service library module. */
-typedef void (*ble_srv_error_handler_t) (uint32_t nrf_error);
-
-/**@brief Value of a Report Reference descriptor. 
- *
- * @details This is mapping information which maps the parent characteristic to the Report ID(s) and
- *          Report Type(s) defined within a Report Map characteristic.
- */
-typedef struct
-{
-    uint8_t report_id;                                  /**< Non-zero value if these is more than one instance of the same Report Type */
-    uint8_t report_type;                                /**< Type of Report characteristic @if (SD_S110) (see @ref BLE_HIDS_REPORT_TYPE) @endif */
-} ble_srv_report_ref_t;
-
-/**@brief UTF-8 string data type.
- *
- * @note The type can only hold a pointer to the string data (i.e. not the actual data).
- */
-typedef struct
-{
-    uint16_t  length;                                   /**< String length. */
-    uint8_t * p_str;                                    /**< String data. */
-} ble_srv_utf8_str_t;
-
-/**@brief Security settings structure.
- * @details This structure contains the security options needed during initialization of the
- *          service.
- */
-typedef struct
-{
-    ble_gap_conn_sec_mode_t read_perm;                  /**< Read permissions. */
-    ble_gap_conn_sec_mode_t write_perm;                 /**< Write permissions. */
-} ble_srv_security_mode_t;
-
-/**@brief Security settings structure.
- * @details This structure contains the security options needed during initialization of the
- *          service. It can be used when the charecteristics contains cccd.
- */
-typedef struct
-{
-    ble_gap_conn_sec_mode_t cccd_write_perm;
-    ble_gap_conn_sec_mode_t read_perm;                  /**< Read permissions. */
-    ble_gap_conn_sec_mode_t write_perm;                 /**< Write permissions. */
-} ble_srv_cccd_security_mode_t;
-
-/**@brief Function for decoding a CCCD value, and then testing if notification is
- *        enabled.
- *
- * @param[in]   p_encoded_data   Buffer where the encoded CCCD is stored.
- *
- * @return      TRUE if notification is enabled, FALSE otherwise.
- */
-static __INLINE bool ble_srv_is_notification_enabled(uint8_t * p_encoded_data)
-{
-    uint16_t cccd_value = uint16_decode(p_encoded_data);
-    return ((cccd_value & BLE_GATT_HVX_NOTIFICATION) != 0);
-}
-    
-/**@brief Function for decoding a CCCD value, and then testing if indication is
- *        enabled.
- *
- * @param[in]   p_encoded_data   Buffer where the encoded CCCD is stored.
- *
- * @return      TRUE if indication is enabled, FALSE otherwise.
- */
-static __INLINE bool ble_srv_is_indication_enabled(uint8_t * p_encoded_data)
-{
-    uint16_t cccd_value = uint16_decode(p_encoded_data);
-    return ((cccd_value & BLE_GATT_HVX_INDICATION) != 0);
-}
-
-/**@brief Function for encoding a Report Reference Descriptor.
- *
- * @param[in]   p_encoded_buffer  The buffer of the encoded data.
- * @param[in]   p_report_ref      Report Reference value to be encoded.
- *
- * @return      Length of the encoded data.
- */
-uint8_t ble_srv_report_ref_encode(uint8_t *                    p_encoded_buffer,
-                                  const ble_srv_report_ref_t * p_report_ref);
-
-/**@brief Function for making UTF-8 structure refer to an ASCII string.
- *
- * @param[out]  p_utf8   UTF-8 structure to be set.
- * @param[in]   p_ascii  ASCII string to be referred to.
- */
-void ble_srv_ascii_to_utf8(ble_srv_utf8_str_t * p_utf8, char * p_ascii);
-
-#endif // BLE_SRV_COMMON_H__
-
-/** @} */
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/device_manager/config/device_manager_cnfg.h
--- a/nRF51822/nordic-sdk/components/ble/device_manager/config/device_manager_cnfg.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,98 +0,0 @@
-/* Copyright (C) 2013 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
- /**
- * @file device_manager_cnfg.h
- *
- * @cond
- * @defgroup device_manager_cnfg Device Manager Configuration 
- * @ingroup device_manager
- * @{
- *
- * @brief Defines application specific configuration for Device Manager.
- *
- * @details All configurations that are specific to application have been defined
- *          here. Application should configuration that best suits its requirements.
- */
- 
-#ifndef DEVICE_MANAGER_CNFG_H__
-#define DEVICE_MANAGER_CNFG_H__
-
-/**
- * @defgroup device_manager_inst Device Manager Instances
- * @{
- */
-/**
- * @brief Maximum applications that Device Manager can support.
- *
- * @details Maximum application that the Device Manager can support.
- *          Currently only one application can be supported.
- *          Minimum value : 1
- *          Maximum value : 1
- *          Dependencies  : None.
- */
-#define DEVICE_MANAGER_MAX_APPLICATIONS  1
-
-/**
- * @brief Maximum connections that Device Manager should simultaneously manage.
- *
- * @details Maximum connections that Device Manager should simultaneously manage.
- *          Minimum value : 1
- *          Maximum value : Maximum links supported by SoftDevice.
- *          Dependencies  : None.
- */
-#define DEVICE_MANAGER_MAX_CONNECTIONS   1
-
-
-/**
- * @brief Maximum bonds that Device Manager should manage.
- *
- * @details Maximum bonds that Device Manager should manage.
- *          Minimum value : 1
- *          Maximum value : 254.
- *          Dependencies  : None.
- * @note In case of GAP Peripheral role, the Device Manager will accept bonding procedure 
- *       requests from peers even if this limit is reached, but bonding information will not 
- *       be stored. In such cases, application will be notified with DM_DEVICE_CONTEXT_FULL 
- *       as event result at the completion of the security procedure.
- */
-#define DEVICE_MANAGER_MAX_BONDS         7
-
-
-/**
- * @brief Maximum Characteristic Client Descriptors used for GATT Server.
- *
- * @details Maximum Characteristic Client Descriptors used for GATT Server.
- *          Minimum value : 1
- *          Maximum value : 254.
- *          Dependencies  : None.
- */
-#define DM_GATT_CCCD_COUNT               2
-
-
-/**
- * @brief Size of application context.
- *
- * @details Size of application context that Device Manager should manage for each bonded device.
- *          Size had to be a multiple of word size.
- *          Minimum value : 4.
- *          Maximum value : 256. 
- *          Dependencies  : Needed only if Application Context saving is used by the application.
- * @note If set to zero, its an indication that application context is not required to be managed
- *       by the module.
- */
-#define DEVICE_MANAGER_APP_CONTEXT_SIZE    0
-
-/* @} */
-/* @} */
-/** @endcond */
-#endif // DEVICE_MANAGER_CNFG_H__
-
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/ble/device_manager/device_manager.h
--- a/nRF51822/nordic-sdk/components/ble/device_manager/device_manager.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,878 +0,0 @@
-/* Copyright (C) 2013 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/**
- * @file device_manager.h
- *
- * @defgroup device_manager Device Manager
- * @ingroup ble_sdk_lib
- * @{
- * @brief Device Manager Application Interface Abstraction.
- *
- * @details The Device Manager module manages Active and Bonded Peers. Management of peer includes
- *          book keeping of contextual information like the Security Keys, GATT
- *          configuration and any application specific information.
- *
- *          Active Peers are devices which are connected, and may or may not be bonded.
- *          Bonded Peers are devices which are bonded, and may or may not be Active (Connected).
- *          Active Bonded Peer refers to a device which is connected and bonded.
- *
- *          Paired Devices refers to peer devices that are connected and have necessary context
- *          establishment/exchange for the current connection session. On disconnect,
- *          all contextual information is flushed. For example, SMP Information Exchanged during
- *          pairing and GATT Configuration is not retained on disconnection.
- *
- *          Note that this module allows management of contextual information but
- *          does not provide an interface for connection management. Therefore, entering connectible
- *          mode, connection establishment, or disconnection of a link with peer is not in scope
- *          of this module.
- *
- *          For bonded peers, the contextual information is required to be retained on disconnection
- *          and power cycling. Persistent storage of contextual information is handled by the
- *          module. This module categorizes the contextual information into 3 categories:
- *             - <b>Bonding Information</b>
- *               Bond information is the information exchanged between local and peer device to
- *               establish a bond. It also includes peer identification information,
- *               like the peer address or the IRK or both. From here on this category of information
- *               is referred to as Device Context.
- *             - <b>Service/Protocol Information</b>
- *               Service/Protocol information is the information retained for the peer to save on one-time
- *               procedures like the GATT Service Discovery procedures and Service Configurations.
- *               It allows devices to resume data exchange on subsequent reconnection without having
- *               to perform initial set-up procedures each time. From here on this category is
- *               referred to as Service Context.
- *             - <b>Application Information</b>
- *               Application information is the context that the application would like to associate with
- *               each of the bonded device. For example, if the application chooses to rank its peers
- *               in order to manage them better, the rank information could be treated as
- *               Application Information. This storage space is provided to save the application from
- *               maintaining a mapping table with each Device Instance and Application Information.
- *               However, if the application have no use for this, it is possible to not
- *               use or employ this at compile time. From here on this category of information is
- *               referred to as Application Context.
- */
-
-
-#ifndef DEVICE_MANAGER_H__
-#define DEVICE_MANAGER_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "sdk_common.h"
-#include "ble.h"
-#include "ble_gap.h"
-#include "device_manager_cnfg.h"
-
-/**
- * @defgroup dm_service_cntext_types Service/Protocol Types
- *
- * @brief Describes the possible types of Service/Protocol Contexts for a bonded/peer device.
- *
- * @details Possible Service/Protocol context per peer device. The Device Manager provides the
- *          functionality of persistently storing the Service/Protocol context and can automatically
- *          load them when needed.
- *          For example system attributes for a GATT Server. Based on the nature of the application,
- *          not all service types may be needed. The application can specify
- *          only the service/protocol context it wants to use at the time of registration.
- * @{
- */
-#define DM_PROTOCOL_CNTXT_NONE         0x00  /**< No Service Context, this implies the application does not want to associate any service/protocol context with the peer device */
-#define DM_PROTOCOL_CNTXT_GATT_SRVR_ID 0x01  /**< GATT Server Service Context, this implies the application does associate GATT Server with the peer device and this information will be loaded when needed for a bonded device */
-#define DM_PROTOCOL_CNTXT_GATT_CLI_ID  0x02  /**< GATT Client Service Context, this implies the application does associate GATT Client with the peer device and this information will be loaded when needed for a bonded device */
-#define DM_PROTOCOL_CNTXT_ALL                                                                     \
-        (DM_PROTOCOL_CNTXT_GATT_SRVR_ID | DM_PROTOCOL_CNTXT_GATT_CLI_ID) /**< All Service/Protocol Context, this implies that the application wants to associate all Service/Protocol Information with the bonded device. This is configurable based on system requirements. If the application has only one type of service, this define could be altered to reflect the same.  */
-/** @} */
-
-
-/**
- * @defgroup dm_events Device Manager Events
- *
- * @brief This section describes the device manager events that are notified to the application.
- *
- * @details The Device Manager notifies the application of various asynchronous events using the
- *          asynchronous event notification callback. All events has been categorized into:
- *          a. General.
- *          b. Link Status.
- *          c. Context Management.
- *
- *          In the callback, these events are notified along with handle that uniquely identifies:
- *          application instance, active instance (if applicable), device instance
- *          bonding instance, (if applicable) and service instance.
- *          Not all events are pertaining to an active connection, for example a context deletion event could occur even if the peer
- *          is not connected. Also, general category of events may not be pertaining to any specific peer.
- *          See also \ref dm_event_cb_t and \ref dm_register.
- * @{
- */
-/**
- * @defgroup general_events General Events
- *
- * @brief General or miscellaneous events.
- *
- * @details This category of events are general events not pertaining to a peer or context.
- *
- * @{
- */
-#define DM_EVT_RFU   0x00 /**< Reserved for future use, is never notified. */
-#define DM_EVT_ERROR 0x01 /**< Device Manager Event Error. */
-/** @} */
-
-/**
- * @defgroup link_status_events Link Status Events
- *
- * @brief Link Status Events.
- *
- * @details This category of events notify the application of the link status. Event result associated
- *          with the event is provided along with the event in the callback to provide more details of
- *          whether a procedure succeeded or failed and assist the application in decision making of
- *          how to proceed. For example if a DM_DEVICE_CONNECT_IND is indicated with NRF_SUCCESS
- *          result, the application may want to proceed with discovering and association with
- *          service of the peer. However, if indicated with a failure result, the application may
- *          want to take an alternate action such as reattempting to connect or go into a
- *          sleep mode.
- *
- * @{
- */
-#define DM_EVT_CONNECTION              0x11 /**< Indicates that link with the peer is established. */
-#define DM_EVT_DISCONNECTION           0x12 /**< Indicates that link with peer is torn down. */
-#define DM_EVT_SECURITY_SETUP          0x13 /**< Security procedure for link started indication */
-#define DM_EVT_SECURITY_SETUP_COMPLETE 0x14 /**< Security procedure for link completion indication. */
-#define DM_EVT_LINK_SECURED            0x15 /**< Indicates that link with the peer is secured. For bonded devices, subsequent reconnections with bonded peer will result only in this event when the link is secured and setup procedures will not occur unless the bonding information is either lost or deleted on either or both sides.  */
-#define DM_EVT_SECURITY_SETUP_REFRESH  0x16 /**< Indicates that the security on the link was re-established. */
-/** @} */
-
-/**
- * @defgroup context_mgmt_events Context Management Events
- *
- * @brief Context Management Events.
- *
- * @details These events notify the application of the status of context loading and storing.
- *
- * @{
- */
-#define DM_EVT_DEVICE_CONTEXT_LOADED   0x21 /**< Indicates that device context for a peer is loaded. */
-#define DM_EVT_DEVICE_CONTEXT_STORED   0x22 /**< Indicates that device context is stored persistently. */
-#define DM_EVT_DEVICE_CONTEXT_DELETED  0x23 /**< Indicates that device context is deleted. */
-#define DM_EVT_SERVICE_CONTEXT_LOADED  0x31 /**< Indicates that service context for a peer is loaded. */
-#define DM_EVT_SERVICE_CONTEXT_STORED  0x32 /**< Indicates that service context is stored persistently. */
-#define DM_EVT_SERVICE_CONTEXT_DELETED 0x33 /**< Indicates that service context is deleted. */
-#define DM_EVT_APPL_CONTEXT_LOADED     0x41 /**< Indicates that application context for a peer is loaded. */
-#define DM_EVT_APPL_CONTEXT_STORED     0x42 /**< Indicates that application context is stored persistently. */
-#define DM_EVT_APPL_CONTEXT_DELETED    0x43 /**< Indicates that application context is deleted. */
-/** @} */
-/** @} */
-
-#define DM_INVALID_ID 0xFF /**< Invalid instance idenitifer. */
-
-/**
- * @defgroup dm_data_structure Device Manager Data Types
- *
- * @brief This section describes all the data types exposed by the module to the application.
- * @{
- */
-
-/**
- * @brief Application Instance.
- *
- * @details Application instance uniquely identifies an application. The identifier is allocated by
- *          the device manager when application registers with the module. The application is
- *          expected to identify itself with this instance identifier when initiating subsequent
- *          requests. Application should use the utility API \ref dm_application_instance_set in
- *          order to set its application instance in dm_handle_t needed for all subsequent APIs.
- *          See also \ref dm_register.
- */
-typedef uint8_t dm_application_instance_t;
-
-/**
- * @brief Connection Instance.
- *
- * @details Identifies connection instance for an active device. This instance is allocated by the
- *          device manager when a connection is established and is notified with DM_EVT_CONNECTION
- *          with the event result NRF_SUCCESS.
- */
-typedef uint8_t dm_connection_instance_t;
-
-/**
- * @brief Device Instance.
- *
- * @details Uniquely identifies a bonded peer device. The peer device may or may not be connected.
- *          In case of the central: The bonded device instance to identify the peer is allocated when bonding procedure is initiated by the central using dm_security_setup_req.
- *          In case of the peripheral: When the bonding procedure is successful, the DM_EVT_SECURITY_SETUP_COMPLETE event with success event result, is received.
- *          In case the module cannot add more bonded devices, no instance is allocated, this is indicated by an appropriate error code for the API/event as the case may be. Application can choose to disconnect the link.
- */
-typedef uint8_t dm_device_instance_t;
-
-/**
- * @brief Service Instance.
- *
- * @details Uniquely identifies a peer device. The peer device may or may not be connected. This
- *          instance is allocated by the device manager when a device is bonded and is notified
- *          when security procedures have been initiated.
- *          Security Procedures initiation is notified with DM_SECURITY_SETUP_IND with
- *          success event result. In case the event result indicates that the module cannot add more
- *          bonded devices, no instance is allocated. Application can chose to disconnect the link.
- */
-typedef uint8_t dm_service_instance_t;
-
-/**
- * @brief Service/Protocol Type Identifier.
- *
- * @details Uniquely identifies a service or a protocol type. Service/Protocol Type identification
- *          is needed as each service/protocol can have its own contextual data.
- *          This allows the peer to access more than one service at a time. \ref dm_service_cntext_types describes the
- *          list of services/protocols supported.
- */
-typedef uint8_t service_type_t;
-
-/**@brief Device Manager Master identification and encryption information. */
-typedef struct dm_enc_key
-{
-    ble_gap_enc_info_t  enc_info;  /**< GAP encryption information. */
-    ble_gap_master_id_t master_id; /**< Master identification. */
-} dm_enc_key_t;
-
-/** @brief Device Manager identity and address information. */
-typedef struct dm_id_key
-{
-  ble_gap_irk_t  id_info;      /**< Identity information. */
-  ble_gap_addr_t id_addr_info; /**< Identity address information. */
-} dm_id_key_t;
-
-/** @brief Device Manager signing information. */
-typedef struct dm_sign_key
-{
-    ble_gap_sign_info_t sign_key; /**< GAP signing information. */
-} dm_sign_key_t;
-
-/** @brief Security keys. */
-typedef struct dm_sec_keyset
-{
-    union
-    {
-        dm_enc_key_t       * p_enc_key;  /**< Pointer to Device Manager encryption information structure. */
-        ble_gap_enc_info_t * p_enc_info; /**< Pointer to GAP encryption information. */
-    } enc_key;
-    dm_id_key_t   * p_id_key;            /**< Identity key, or NULL. */
-    dm_sign_key_t * p_sign_key;          /**< Signing key, or NULL. */
-} dm_sec_keys_t;
-
-/** @brief Device Manager security key set. */
-typedef struct
-{
-  dm_sec_keys_t keys_periph;  /**< Keys distributed by the device in the Peripheral role. */
-  dm_sec_keys_t keys_central; /**< Keys distributed by the device in the Central role. */
-} dm_sec_keyset_t;
-
-/**
- * @brief Device Handle used for unique identification of each peer.
- *
- * @details This data type is used to uniquely identify each peer device. A peer device could be
- *          active and/or bonded. Therefore an instance for active and bonded is provided.
- *          However, the application is expected to treat this is an opaque structure and use this for
- *          all API interactions once stored on appropriate events.
- *          See \ref dm_events.
- */
-typedef struct device_handle
-{
-    dm_application_instance_t    appl_id;       /**< Identifies the application instances for the device that is being managed. */
-    dm_connection_instance_t     connection_id; /**< Identifies the active connection instance. */
-    dm_device_instance_t         device_id;     /**< Identifies peer instance in the data base. */
-    dm_service_instance_t        service_id;    /**< Service instance identifier. */
-} dm_handle_t;
-
-/**
- * @brief Definition of Data Context.
- *
- * @details Defines contextual data format, it consists of context data length and pointer to data.
- */
-typedef struct
-{
-    uint32_t  len;    /**< Length of data . */
-    uint8_t * p_data; /**< Pointer to contextual data, a copy is made of the data. */
-} dm_context_t;
-
-
-/**
- * @brief Device Context.
- *
- * @details Defines "device context" type for a device managed by device manager.
- */
-typedef dm_context_t dm_device_context_t;
-
-/**
- * @brief Service Context.
- *
- * @details Service context data for a service identified by the 'service_type' field.
- */
-typedef struct
-{
-    service_type_t service_type; /**< Identifies the service/protocol to which the context data is related. */
-    dm_context_t   context_data; /**< Contains length and pointer to context data */
-} dm_service_context_t;
-
-/**
- * @brief Application context.
- *
- * @details The application context can be used by the application to map any application level
- *          information that is to be mapped with a particular peer.
- *          For bonded peers, this information will be stored by the bond manager persistently.
- *          Note that the device manager treats this information as an
- *          opaque block of bytes.
- *          Necessary APIs to get and set this context for a peer have been provided.
- */
-typedef dm_context_t dm_application_context_t;
-
-/**
- * @brief Event parameters.
- *
- * @details Defines event parameters for each of the events notified by the module.
- */
-typedef union
-{
-    ble_gap_evt_t            * p_gap_param;       /**< All events that are triggered in device manager as a result of GAP events, like connection, disconnection and security procedures are accompanied with GAP parameters. */
-    dm_application_context_t * p_app_context;     /**< All events that are associated with application context procedures of store, load, and deletion have this as event parameter. */
-    dm_service_context_t     * p_service_context; /**< All events that are associated with service context procedures of store, load and deletion have this as event parameter. */
-    dm_device_context_t      * p_device_context;  /**< All events that are associated with device context procedures of store, load and deletion have this as event parameter. */
-} dm_event_param_t;
-
-/**
- * @brief Asynchronous events details notified to the application by the module.
- *
- * @details Defines event type along with event parameters notified to the application by the
- *          module.
- */
-typedef struct
-{
-    uint8_t          event_id;       /**< Identifies the event. See \ref dm_events for details on event types and their significance. */
-    dm_event_param_t event_param;    /**< Event parameters. Can be NULL if the event does not have any parameters. */
-    uint16_t         event_paramlen; /**< Length of the event parameters, is zero if the event does not have any parameters. */
-} dm_event_t;
-
-/**
- * @brief Event notification callback registered by application with the module.
- *
- * @details Event notification callback registered by application with the module when registering
- *          the module using \ref dm_register API.
- *
- * @param[in] p_handle   Identifies the peer for which the event is being notified.
- * @param[in] p_event    Identifies the event, any associated parameters and parameter length.
- *                       See \ref dm_events for details on event types and their significance.
- * @param[in,out] event_result   Provide additional information on the event.
- *                      In addition to SDK error codes there is also a return value
- *                      indicating if maximum number of connections has been reached when connecting or bonding.
- *
- * @retval NRF_SUCCESS on success, or a failure to indicate if it could handle the event
- *         successfully. There is no action taken in case application returns a failure.
- */
-typedef api_result_t (*dm_event_cb_t)(dm_handle_t const * p_handle,
-                                      dm_event_t const  * p_event,
-                                      api_result_t        event_result);
-
-/**
- * @brief Initialization Parameters.
- *
- * @details Indicates the application parameters. Currently this only encompasses clearing
- *          all persistent data.
- */
-typedef struct
-{
-    bool clear_persistent_data; /**< Set to true in case the module should clear all persistent data. */
-} dm_init_param_t;
-
-/**
- * @brief Application Registration Parameters.
- *
- * @details Parameters needed by the module when registering with it.
- */
-typedef struct
-{
-    dm_event_cb_t        evt_handler;  /**< Event Handler to be registered. It will receive asynchronous notification from the module, see \ref dm_events for asynchronous events. */
-    uint8_t              service_type; /**< Bit mask identifying services that the application intends to support for all peers. */
-    ble_gap_sec_params_t sec_param;    /**< Security parameters to be used for the application. */
-} dm_application_param_t;
-
-/**
- * @brief Defines possible security status/states.
- *
- * @details Defines possible security status/states of a link when requested by application using
- *          the \ref dm_security_status_req.
- */
-typedef enum
-{
-    NOT_ENCRYPTED,                  /**< The link does not security. */
-    ENCRYPTION_IN_PROGRESS, /**< Security is in progress of being established.*/
-    ENCRYPTED              /**< The link is secure.*/
-} dm_security_status_t;
-/** @} */
-
-/**
- * @defgroup dm_api Device Module APIs
- *
- * @brief This section describes APIs exposed by the module.
- *
- * @details This section describes APIs exposed by the module. The APIs have been categorized to provide
- *          better and specific look up for developers. Categories are:
- *          - Set up APIs.
- *          - Context Management APIs.
- *          - Utility APIs.
- *
- *          MSCs describe usage of these APIs.
- *          See @ref dm_msc.
- * @{
- */
-/**
- * @defgroup dm_setup_api Device Module Set-up APIs
- *
- * @brief Initialization & registration APIs that are pre-requisite for all other module procedures.
- * @details This section describes the Module Initialization and Registration APIs needed to be set up by
- *          the application before device manager can start managing devices and device contexts
- *          for the application.
- *
- * @{
- */
-
-/**
- * @brief Module Initialization Routine.
- *
- * @details Function for initializing the module. Must called before any other APIs of the module are used.
- *
- * @param[in] p_init_param Initialization parameters.
- *
- * @retval NRF_SUCCESS On success, else an error code indicating reason for failure.
- *
- * @note It is mandatory that pstorage is initialized before initializing this module.
- */
-api_result_t dm_init(dm_init_param_t const * p_init_param);
-
-/**
- * @brief Function for registering the application.
- *
- * @details This routine is used by the application to register for asynchronous events with the
- *          device manager. During registration the application also indicates the services that it
- *          intends to support on this instance. It is possible to register multiple times with the
- *          device manager. At least one instance shall be registered with the device manager after
- *          the module has been initialized.
- *          Maximum number of application instances device manager can support is determined
- *          by DM_MAX_APPLICATIONS.
- *
- *          All applications must be registered before initiating or accepting connections from the peer.
- *
- * @param[in]  p_appl_param    Application parameters.
- * @param[out] p_appl_instance Application Instance Identifier in case registration is successful.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization.
- * @retval NRF_ERROR_NO_MEM        If module cannot support more applications.
- *
- * @note Currently only one application instance is supported by the module.
- */
-api_result_t dm_register(dm_application_instance_t    * p_appl_instance,
-                         dm_application_param_t const * p_appl_param);
-
-/**
- * @brief Function for handling BLE events.
- *
- * @details BLE Event Handler for the module. This routine should be called from BLE stack event
- *          dispatcher for the module to work as expected.
- *
- * @param[in] p_ble_evt BLE stack event being dispatched to the function.
- *
- */
-void dm_ble_evt_handler(ble_evt_t * p_ble_evt);
-
-/** @} */
-
-
-/**
- * @defgroup dm_security_api APIs to set up or read status of security on a link.
- *
- * @brief This section describes APIs to set up Security. These APIs require that the peer is
- *        connected before the procedures can be requested.
- *
- * @details This group allows application to request security procedures
- *          or get the status of the security on a link.
- * @{
- */
-/**
- * @brief Function for requesting setting up security on a link.
- *
- * @details This API initiates security procedures with a peer device.
- *          @note For the GAP Central role, in case peer is not bonded, request to bond/pair is
- *          initiated. If it is bonded, the link is re-encrypted using the existing bond information.
- *          For the GAP peripheral role, a Slave security request is sent.
- * @details If a pairing procedure is initiated successfully, application is notified of
- *          @ref DM_EVT_SECURITY_SETUP_COMPLETE. A result indicating success or failure is notified along with the event.
- *          In case the link is re-encrypted using existing bond information, @ref DM_EVT_LINK_SECURED is
- *          notified to the application.
- *
- * @param[in] p_handle Identifies the link on which security is desired.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If p_handle is NULL.
- * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application
- *                                 or if the peer is not connected when this procedure is requested.
- */
-api_result_t dm_security_setup_req(dm_handle_t * p_handle);
-
-/**
- * @brief Function for reading the status of the security on a link.
- *
- * @details This API allows application to query status of security on a link.
- *
- * @param[in]  p_handle  Identifies the link on which security is desired.
- * @param[out] p_status  Pointer where security status is provided to the application.
- *                       See \ref dm_security_status_t for possible statuses that can be expected.
- *
- * @retval NRF_SUCCESS             Or appropriate error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If p_handle or p_status is NULL.
- * @retval NRF_ERROR_INVALID_ADDR  If peer is not identified by the handle provided by the application
- *                                 or if peer is not connected when this procedure is requested.
- */
-api_result_t dm_security_status_req(dm_handle_t const * p_handle, dm_security_status_t * p_status);
-
-/**
- * @brief Function for creating the whitelist.
- *
- * @details This API allows application to create whitelist based on bonded peer devices in module
- *          data base.
- *
- * @param[in]  p_handle       Identifies the application requesting whitelist creation.
- * @param[in,out] p_whitelist Pointer where created whitelist is provided to the application.
- *
- * @note 'addr_count' and 'irk_count' fields of the structure should be populated with the maximum
- *       number of devices that the application wishes to request in the whitelist.
- *       If the number of bonded devices is less than requested, the fields are updated with that number of devices.
- *       If the number of devices are more than requested, the module will populate the list
- *       with devices in the order the bond was established with the peer devices. Also, if this routine is
- *       called when a connection exists with one or more peer devices,
- *       those connected devices are not added to the whitelist.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If p_handle or p_whitelist is NULL.
- */
-api_result_t dm_whitelist_create(dm_application_instance_t const * p_handle,
-                                 ble_gap_whitelist_t             * p_whitelist);
-
-/** @} */
-
-
-/**
- * @defgroup dm_cntxt_mgmt_api Context Management APIs
- *
- * @brief Utility APIs offered by the device manager to get information about the peer if and
- *        when needed.
- *
- * @details This group of API allow the application to access information that is not required to be
- *          maintained by the application but may be needed. Hence it is possible to get the
- *          information from the module instead of mapping all the information with a device
- *          context.
- * @{
- */
-
-api_result_t dm_device_add(dm_handle_t               * p_handle,
-                           dm_device_context_t const * p_context);
-
-/**
- * @brief Function for deleting a peer device context and all related information from the database.
- *
- * @details Delete peer device context and all related information from database. If
- *          this API returns NRF_SUCCESS, DM_EVT_DEVICE_CONTEXT_DELETED event is notified to the
- *          application. Event result notified along with the event indicates success or failure
- *          of this procedure.
- *
- * @param[in] p_handle Identifies the peer device to be deleted.
- *
- * @retval NRF_SUCCESS             on success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE In the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If p_handle is NULL.
- * @retval NRF_ERROR_INVALID_ADDR  If peer is not identified the handle provided by the application.
- *
- * @note Deleting device context results in deleting service and application context for the
- *       bonded device. The respective events DM_EVT_SERVICE_CONTEXT_DELETED and
- *       DM_EVT_APPL_CONTEXT_DELETED are not notified to the application.
- */
-api_result_t dm_device_delete(dm_handle_t const * p_handle);
-
-/**
- * @brief Function for deleting all peer device context and all related information from the database.
- *
- * @details Delete peer device context and all related information from database. If
- *          this API returns NRF_SUCCESS, DM_EVT_DEVICE_CONTEXT_DELETED event is notified to the
- *          application for each device that is deleted from the data base. Event result
- *          notified along with the event indicates success or failure of this procedure.
- *
- * @param[in] p_handle Identifies application instance that is requesting
- *                     the deletion of all bonded devices.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If p_handle is NULL.
- * @retval NRF_ERROR_INVALID_ADDR  If peer is not identified the handle provided by the application.
- *
- * @note Deleting device context results in deleting both service and application context for the
- *       bonded device. The respective events DM_EVT_SERVICE_CONTEXT_DELETED and
- *       DM_EVT_APPL_CONTEXT_DELETED are not notified to the application.
- */
-api_result_t dm_device_delete_all(dm_application_instance_t const * p_handle);
-
-/**
- * @brief Function for setting Service Context for a peer device identified by 'p_handle' parameter.
- *
- * @details This API allows application to Set Service Context for a peer device identified by the
- *          'p_handle' parameter. This API is useful when the Service Context cannot be requested
- *          from the SoftDevice, but needs to be assembled by the application or an another module.
- *          (or when service context is exchanged in an out of band way.)
- *          This API could also be used to trigger a storing of service context into persistent
- *          memory. If this is desired, a NULL pointer could be passed to the p_context.
- *
- * @param[in] p_handle  Identifies peer device for which the procedure is requested.
- * @param[in] p_context Service context being set. The context information includes length of
- *                      data and pointer to the contextual data being set. The memory pointed to by
- *                      the pointer to data is assumed to be resident when API is being called and
- *                      can be freed or reused once the set procedure is complete. Set procedure
- *                      completion is indicated by the event \ref DM_EVT_SERVICE_CONTEXT_STORED.
- *                      The Event result is notified along with the event and indicates success or failure of
- *                      this procedure.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If p_handle is NULL.
- * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application.
- */
-api_result_t dm_service_context_set(dm_handle_t const          * p_handle,
-                                    dm_service_context_t const * p_context);
-
-/**
- * @brief Function for getting Service Context for a peer device identified by 'p_handle' parameter.
- *
- * @details Get Service Context for a peer device identified by the 'p_handle' parameter. If
- *          this API returns NRF_SUCCESS, DM_EVT_SERVICE_CONTEXT_LOADED event is notified to the
- *          application. The event result is notified along with the event indicates success or failure
- *          of this procedure.
- *
- * @param[in] p_handle  Identifies peer device for which procedure is requested.
- * @param[in] p_context Application context being requested. The context information includes length
- *                      of the data and a pointer to the data. Note that requesting a 'get'
- *                      of application does not need to provide memory, the pointer to data will be
- *                      pointing to service data and hence no data movement is involved.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE In case API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If p_handle is NULL.
- * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application.
- */
-api_result_t dm_service_context_get(dm_handle_t const    * p_handle,
-                                    dm_service_context_t * p_context);
-
-/**
- * @brief Function for deleting a Service Context for a peer device identified by the 'p_handle' parameter.
- *
- * @details This API allows application to delete a Service Context identified for a peer device
- *          identified by the 'p_handle' parameter. If this API returns NRF_SUCCESS,
- *          DM_EVT_SERVICE_CONTEXT_DELETED event is notified to the application.
- *          Event result is notified along with the event and indicates success or failure of this
- *          procedure.
- *
- * @param[in] p_handle Identifies peer device for which procedure is requested.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If p_handle is NULL.
- * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application.
- */
-api_result_t dm_service_context_delete(dm_handle_t const * p_handle);
-
-/**
- * @brief Function for setting Application Context for a peer device identified by the 'p_handle' parameter.
- *
- * @details This application allows the setting of the application context for the peer device identified by
- *          the 'p_handle'. Application context is stored persistently by the module and can be
- *          requested by the application at any time using the \ref dm_application_context_get
- *          API. Note that this procedure is permitted only for bonded devices. If the
- *          device is not bonded, application context cannot be set. However, it is not mandatory
- *          that the bonded device is connected when requesting this procedure.
- *
- * @param[in] p_handle  Identifies peer device for which procedure is requested.
- *
- * @param[in] p_context Application context being set. The context information includes length of the
- *                      data and pointer to the contextual data being set. The memory pointed to by
- *                      the data pointer is assumed to be resident when API is being called and
- *                      can be freed or reused once the set procedure is complete. Set procedure
- *                      completion is notified by the event \ref DM_EVT_APPL_CONTEXT_STORED.
- *                      The event result is notified along with the event and indicates success or
- *                      failure of this procedure.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If p_handle and/or p_context is NULL.
- * @retval NRF_ERROR_INVALID_ADDR  If peer is not identified the handle provided by the application.
- *
- * @note The API returns FEATURE_NOT_ENABLED in case DEVICE_MANAGER_APP_CONTEXT_SIZE is set to zero.
- */
-api_result_t dm_application_context_set(dm_handle_t const              * p_handle,
-                                        dm_application_context_t const * p_context);
-
-/**
- * @brief Function for getting Application Context for a peer device identified by the 'p_handle' parameter.
- *
- * @details Get Application Context for a peer device identified by the 'p_handle' parameter. If
- *          this API returns NRF_SUCCESS, DM_EVT_APPL_CONTEXT_LOADED event is notified to the
- *          application. Event result notified along with the event indicates success or failure
- *          of this procedure.
- *
- * @param[in] p_handle  Identifies peer device for which procedure is requested.
- * @param[in] p_context Application context being requested. The context information includes
- *                      length of data and pointer to the contextual data is provided.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If p_handle and/or p_context is NULL.
- * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application.
- * @retval DM_NO_APP_CONTEXT       If no application context was set that can be fetched.
- *
- * @note The API returns FEATURE_NOT_ENABLED in case DEVICE_MANAGER_APP_CONTEXT_SIZE is set to
- *       zero.
- */
-api_result_t dm_application_context_get(dm_handle_t const        * p_handle,
-                                        dm_application_context_t * p_context);
-
-/**
- * @brief Function for deleting Application Context for a peer device identified by the 'p_handle' parameter.
- *
- * @details Delete Application Context for a peer device identified by the 'p_handle' parameter. If
- *          this API returns NRF_SUCCESS, DM_EVT_APPL_CONTEXT_DELETED event is notified to the
- *          application. The event result notified along with the event and indicates success or failure
- *          of this procedure.
- *
- * @param[in] p_handle Identifies peer device for which procedure is requested.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If the p_handle is NULL.
- * @retval NRF_ERROR_INVALID_ADDR  If peer is not identified the handle provided by the application.
- * @retval DM_NO_APP_CONTEXT       If no application context was set that can be deleted.
- *
- * @note The API returns FEATURE_NOT_ENABLED if the DEVICE_MANAGER_APP_CONTEXT_SIZE is set to zero.
- */
-api_result_t dm_application_context_delete(dm_handle_t const * p_handle);
-
-/** @} */
-
-
-/**
- * @defgroup utility_api Utility APIs
- * @{
- * @brief This section describes the utility APIs offered by the module.
- *
- * @details APIs defined in this section are utility or assisting/helper APIs.
- */
-/**
- * @brief Function for Setting/Copying Application instance to Device Manager handle.
- *
- * @param[in]  p_appl_instance Application instance to be set.
- * @param[out] p_handle        Device Manager handle for which the instance is to be copied.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If p_handle and/or p_addr is NULL.
- */
-api_result_t dm_application_instance_set(dm_application_instance_t const * p_appl_instance,
-                                         dm_handle_t                     * p_handle);
-
-/**
- * @brief Function for getting a peer's device address.
- *
- * @param[in]  p_handle Identifies the peer device whose address is requested. Can not be NULL.
- * @param[out] p_addr   Pointer where address is to be copied. Can not be NULL.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If p_handle and/or p_addr is NULL.
- * @retval NRF_ERROR_NOT_FOUND     If the peer could not be identified.
- */
-api_result_t dm_peer_addr_get(dm_handle_t const * p_handle,
-                              ble_gap_addr_t    * p_addr);
-
-/**
- * @brief Function for setting/updating a peer's device address.
- *
- * @param[in]  p_handle Identifies the peer device whose address is requested to be set/updated.
- * @param[out] p_addr   Address to be set/updated.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If p_handle and/or p_addr is NULL.
- * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application.
- * @retval NRF_ERROR_INVALID_PARAM If this procedure is requested while connected to the peer or if the address
- *                                 type was set to BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE.
- *
- * @note Setting or updating a peer's device address is permitted
- *       only for a peer that is bonded and disconnected.
- * @note Updated address is reflected only after DM_EVT_DEVICE_CONTEXT_STORED is notified to the
- *       application for this bonded device instance. In order to avoid abnormal behaviour, it is
- *       recommended to not invite/initiate connections on the updated address unless this event
- *       has been notified.
- */
-api_result_t dm_peer_addr_set(dm_handle_t const    * p_handle,
-                              ble_gap_addr_t const * p_addr);
-
-/**
- * @brief Function for initializing Device Manager handle.
- *
- * @param[in] p_handle Device Manager handle to be initialized.
- *
- * @retval NRF_SUCCESS    On success.
- * @retval NRF_ERROR_NULL If p_handle is NULL.
- *
- * @note This routine is permitted before initialization of the module.
- */
-api_result_t dm_handle_initialize(dm_handle_t * p_handle);
-
-/**
- * @brief Function for getting distributed keys for a device.
- *
- * @details This routine is used to get distributed keys with a bonded device. This API is currently
- *          only available on S120 (GAP Central role).
- *
- * @param[in] p_handle Device Manager handle identifying the peer.
- *
- * @param[out] p_key_dist Pointer to distributed keys.
- *
- * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
- * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
- *                                 application registration.
- * @retval NRF_ERROR_NULL          If the p_handle and/or p_key_dist pointer is NULL.
- * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application.
- */
-api_result_t dm_distributed_keys_get(dm_handle_t const * p_handle,
-                                     dm_sec_keyset_t   * p_key_dist);
-
-/** @} */
-/** @} */
-/** @} */
-#endif // DEVICE_MANAGER_H__
-
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/ble_flash/ble_flash.c
--- a/nRF51822/nordic-sdk/components/drivers_nrf/ble_flash/ble_flash.c	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,287 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#include "ble_flash.h"
-#include <stdlib.h>
-#include <stdint.h>
-#include <string.h>
-#include "nrf_soc.h"
-#include "nordic_common.h"
-#include "nrf_error.h"
-#include "nrf.h"
-#include "nrf51_bitfields.h"
-#include "app_util.h"
-
-
-static volatile bool m_radio_active = false;  /**< TRUE if radio is active (or about to become active), FALSE otherwise. */
-
-
-uint16_t ble_flash_crc16_compute(uint8_t * p_data, uint16_t size, uint16_t * p_crc)
-{
-    uint16_t i;
-    uint16_t crc = (p_crc == NULL) ? 0xffff : *p_crc;
-
-    for (i = 0; i < size; i++)
-    {
-        crc  = (unsigned char)(crc >> 8) | (crc << 8);
-        crc ^= p_data[i];
-        crc ^= (unsigned char)(crc & 0xff) >> 4;
-        crc ^= (crc << 8) << 4;
-        crc ^= ((crc & 0xff) << 4) << 1;
-    }
-    return crc;
-}
-
-
-/**@brief Function for erasing a page in flash.
- * 
- * @param[in]  p_page  Pointer to first word in page to be erased.
- */
-static void flash_page_erase(uint32_t * p_page)
-{
-    // Turn on flash erase enable and wait until the NVMC is ready.
-    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Een << NVMC_CONFIG_WEN_Pos);
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-    {
-        // Do nothing.
-    }
-
-    // Erase page.
-    NRF_NVMC->ERASEPAGE = (uint32_t)p_page;
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-    {
-        // Do nothing.
-    }
-
-    // Turn off flash erase enable and wait until the NVMC is ready.
-    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-    {
-        // Do nothing
-    }
-}
-
-
-/**@brief Function for writing one word to flash. Unprotected write, which can interfere with radio communication.
- *
- * @details This function DOES NOT use the m_radio_active variable, but will force the write even
- *          when the radio is active. To be used only from @ref ble_flash_page_write.
- *
- * @note Flash location to be written must have been erased previously.
- *
- * @param[in]  p_address   Pointer to flash location to be written.
- * @param[in]  value       Value to write to flash.
- */
-static void flash_word_unprotected_write(uint32_t * p_address, uint32_t value)
-{
-    // Turn on flash write enable and wait until the NVMC is ready.
-    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos);
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-    {
-        // Do nothing.
-    }
-    *p_address = value;
-    
-    // Wait flash write to finish
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-    {
-        // Do nothing.
-    }
-
-    // Turn off flash write enable and wait until the NVMC is ready.
-    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-    {
-        // Do nothing.
-    }
-}
-
-
-/**@brief Function for writing one word to flash.
- *
- * @note Flash location to be written must have been erased previously.
- *
- * @param[in]  p_address   Pointer to flash location to be written.
- * @param[in]  value       Value to write to flash.
- */
-static void flash_word_write(uint32_t * p_address, uint32_t value)
-{
-    // If radio is active, wait for it to become inactive.
-    while (m_radio_active)
-    {
-        // Do nothing (just wait for radio to become inactive).
-        (void) sd_app_evt_wait();
-    }
-
-    // Turn on flash write enable and wait until the NVMC is ready.
-    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos);
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-    {
-        // Do nothing.
-    }
-
-    *p_address = value;
-    // Wait flash write to finish
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-    {
-        // Do nothing.
-    }
-    // Turn off flash write enable and wait until the NVMC is ready.
-    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-    {
-        // Do nothing
-    }
-}
-
-
-uint32_t ble_flash_word_write(uint32_t * p_address, uint32_t value)
-{
-    flash_word_write(p_address, value);
-    return NRF_SUCCESS;
-}
-
-
-uint32_t ble_flash_block_write(uint32_t * p_address, uint32_t * p_in_array, uint16_t word_count)
-{
-    uint16_t i;
-
-    for (i = 0; i < word_count; i++)
-    {
-        flash_word_write(p_address, p_in_array[i]);
-        p_address++;
-    }
-
-    return NRF_SUCCESS;
-}
-
-
-uint32_t ble_flash_page_erase(uint8_t page_num)
-{
-    uint32_t * p_page = (uint32_t *)(BLE_FLASH_PAGE_SIZE * page_num);
-    flash_page_erase(p_page);
-
-    return NRF_SUCCESS;
-}
-
-
-uint32_t ble_flash_page_write(uint8_t page_num, uint32_t * p_in_array, uint8_t word_count)
-{
-    int        i;
-    uint32_t * p_page;
-    uint32_t * p_curr_addr;
-    uint16_t   in_data_crc;
-    uint16_t   flash_crc;
-    uint32_t   flash_header;
-
-    p_page      = (uint32_t *)(BLE_FLASH_PAGE_SIZE * page_num);
-    p_curr_addr = p_page;
-
-    // Calculate CRC of the data to write.
-    in_data_crc = ble_flash_crc16_compute((uint8_t *)p_in_array,
-                                          word_count * sizeof(uint32_t),
-                                          NULL);
-
-    // Compare the calculated to the one in flash.
-    flash_header = *p_curr_addr;
-    flash_crc    = (uint16_t)flash_header;
-
-    if (flash_crc == in_data_crc)
-    {
-        // Data is the same as the data already stored in flash, return without modifying flash.
-        return NRF_SUCCESS;
-    }
-
-    // Erase flash page
-    flash_page_erase(p_page);
-
-    // Reserve space for magic number (for detecting if flash content is valid).
-    p_curr_addr++;
-
-    // Reserve space for saving word_count.
-    p_curr_addr++;
-
-    // Write data
-    for (i = 0; i < word_count; i++)
-    {
-        flash_word_unprotected_write(p_curr_addr, p_in_array[i]);
-        p_curr_addr++;
-    }
-
-    // Write number of elements.
-    flash_word_write(p_page + 1, (uint32_t)(word_count));
-
-    // Write magic number and CRC to indicate that flash content is valid.
-    flash_header = BLE_FLASH_MAGIC_NUMBER | (uint32_t)in_data_crc;
-    flash_word_write(p_page, flash_header);
-
-    return NRF_SUCCESS;
-}
-
-
-uint32_t ble_flash_page_read(uint8_t page_num, uint32_t * p_out_array, uint8_t * p_word_count)
-{
-    int        byte_count;
-    uint32_t * p_page;
-    uint32_t * p_curr_addr;
-    uint32_t   flash_header;
-    uint32_t   calc_header;
-    uint16_t   calc_crc;
-    uint32_t   tmp;
-
-    p_page      = (uint32_t *)(BLE_FLASH_PAGE_SIZE * page_num);    
-    p_curr_addr = p_page;
-
-    // Check if block is valid
-    flash_header = *p_curr_addr;
-    tmp = flash_header & 0xFFFF0000;
-    if (tmp != BLE_FLASH_MAGIC_NUMBER)
-    {
-        *p_word_count = 0;
-        return NRF_ERROR_NOT_FOUND;
-    }
-    p_curr_addr++;
-
-    // Read number of elements
-    *p_word_count = (uint8_t)(*(p_curr_addr));
-    p_curr_addr++;
-
-    // Read data
-    byte_count = (*p_word_count) * sizeof(uint32_t);
-    memcpy(p_out_array, p_curr_addr, byte_count);
-
-    // Check CRC
-    calc_crc = ble_flash_crc16_compute((uint8_t *)p_out_array,
-                                       (*p_word_count) * sizeof(uint32_t),
-                                       NULL);
-    calc_header = BLE_FLASH_MAGIC_NUMBER | (uint32_t)calc_crc;
-
-    if (calc_header != flash_header)
-    {
-        return NRF_ERROR_NOT_FOUND;
-    }
-
-    return NRF_SUCCESS;
-}
-
-
-uint32_t ble_flash_page_addr(uint8_t page_num, uint32_t ** pp_page_addr)
-{
-    *pp_page_addr = (uint32_t *)(BLE_FLASH_PAGE_SIZE * page_num);
-    return NRF_SUCCESS;
-}
-
-
-void ble_flash_on_radio_active_evt(bool radio_active)
-{
-    m_radio_active = radio_active;
-}
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/ble_flash/ble_flash.h
--- a/nRF51822/nordic-sdk/components/drivers_nrf/ble_flash/ble_flash.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,142 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-/** @file
- *
- * @defgroup ble_flash_module Flash Manager
- * @{
- * @ingroup ble_sdk_lib
- * @brief Module for accessing flash memory.
- *
- * @details It contains functions for reading, writing and erasing one page in flash.
- *
- *          The module uses the first 32 bits of the flash page to write a magic number in order to
- *          determine if the page has been written or not.
- *
- * @note Be careful not to use a page number in the SoftDevice area (which currently occupies the
- *       range 0 to 127), or in your application space! In both cases, this would end up
- *       with a hard fault.
- */
-
-#ifndef BLE_FLASH_H__
-#define BLE_FLASH_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <nrf51.h>
-
-#define BLE_FLASH_PAGE_SIZE     ((uint16_t)NRF_FICR->CODEPAGESIZE)  /**< Size of one flash page. */
-#define BLE_FLASH_MAGIC_NUMBER  0x45DE0000                          /**< Magic value to identify if flash contains valid data. */
-#define BLE_FLASH_EMPTY_MASK    0xFFFFFFFF                          /**< Bit mask that defines an empty address in flash. */
-
-
-/**@brief Macro for getting the end of the flash available for application.
- * 
- * @details    The result flash page number indicates the end boundary of the flash available 
- *             to the application. If a bootloader is used, the end will be the start of the 
- *             bootloader region. Otherwise, the end will be the size of the flash. 
- */
-#define BLE_FLASH_PAGE_END \
-    ((NRF_UICR->BOOTLOADERADDR != BLE_FLASH_EMPTY_MASK) \
-        ? (NRF_UICR->BOOTLOADERADDR / BLE_FLASH_PAGE_SIZE) \
-        : NRF_FICR->CODESIZE)
-
-/**@brief Function for erasing the specified flash page, and then writes the given data to this page.
- *
- * @warning This operation blocks the CPU. DO NOT use while in a connection!
- *
- * @param[in]  page_num     Page number to update.
- * @param[in]  p_in_array   Pointer to a RAM area containing the elements to write in flash.
- *                          This area has to be 32 bits aligned.
- * @param[in]  word_count   Number of 32 bits words to write in flash.
- *
- * @return     NRF_SUCCESS on successful flash write, otherwise an error code.
- */
-uint32_t ble_flash_page_write(uint8_t page_num, uint32_t * p_in_array, uint8_t word_count);
-
-/**@brief Function for reading data from flash to RAM.
- *
- * @param[in]  page_num       Page number to read.
- * @param[out] p_out_array    Pointer to a RAM area where the found data will be written. 
- *                            This area has to be 32 bits aligned.
- * @param[out] p_word_count   Number of 32 bits words read.
- *
- * @return     NRF_SUCCESS on successful upload, NRF_ERROR_NOT_FOUND if no valid data has been found
- *             in flash (first 32 bits not equal to the MAGIC_NUMBER+CRC).
- */
-uint32_t ble_flash_page_read(uint8_t page_num, uint32_t * p_out_array, uint8_t * p_word_count);
-
-/**@brief Function for erasing a flash page.
- *
- * @note This operation blocks the CPU, so it should not be done while the radio is running!
- *
- * @param[in]  page_num   Page number to erase.
- *
- * @return     NRF_SUCCESS on success, an error_code otherwise.
- */
-uint32_t ble_flash_page_erase(uint8_t page_num);
-
-/**@brief Function for writing one word to flash.
- *
- * @note Flash location to be written must have been erased previously.
- *
- * @param[in]  p_address   Pointer to flash location to be written.
- * @param[in]  value       Value to write to flash.
- *
- * @return     NRF_SUCCESS.
- */
-uint32_t ble_flash_word_write(uint32_t * p_address, uint32_t value);
-
-/**@brief Function for writing a data block to flash.
- *
- * @note Flash locations to be written must have been erased previously.
- *
- * @param[in]  p_address    Pointer to start of flash location to be written.
- * @param[in]  p_in_array   Pointer to start of flash block to be written.
- * @param[in]  word_count   Number of words to be written.
- *
- * @return     NRF_SUCCESS.
- */
-uint32_t ble_flash_block_write(uint32_t * p_address, uint32_t * p_in_array, uint16_t word_count);
-
-/**@brief Function for computing pointer to start of specified flash page.
- *
- * @param[in]  page_num       Page number.
- * @param[out] pp_page_addr   Pointer to start of flash page.
- *
- * @return     NRF_SUCCESS.
- */
-uint32_t ble_flash_page_addr(uint8_t page_num, uint32_t ** pp_page_addr);
-
-/**@brief Function for calculating a 16 bit CRC using the CRC-16-CCITT scheme.
- * 
- * @param[in]  p_data   Pointer to data on which the CRC is to be calulated.
- * @param[in]  size     Number of bytes on which the CRC is to be calulated.
- * @param[in]  p_crc    Initial CRC value (if NULL, a preset value is used as the initial value).
- *
- * @return     Calculated CRC.
- */
-uint16_t ble_flash_crc16_compute(uint8_t * p_data, uint16_t size, uint16_t * p_crc);
-
-/**@brief Function for handling flashing module Radio Notification event.
- *
- * @note For flash writing to work safely while in a connection or while advertising, this function
- *       MUST be called from the Radio Notification module's event handler (see
- *       @ref ble_radio_notification for details).
- *
- * @param[in]  radio_active   TRUE if radio is active (or about to become active), FALSE otherwise.
- */
-void ble_flash_on_radio_active_evt(bool radio_active);
-
-#endif // BLE_FLASH_H__
-
-/** @} */
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/hal/compiler_abstraction.h
--- a/nRF51822/nordic-sdk/components/drivers_nrf/hal/compiler_abstraction.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,109 +0,0 @@
-/* Copyright (c) 2013, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright notice, this
- *     list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright notice,
- *     this list of conditions and the following disclaimer in the documentation
- *     and/or other materials provided with the distribution.
- *
- *   * Neither the name of Nordic Semiconductor ASA nor the names of its
- *     contributors may be used to endorse or promote products derived from
- *     this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-#ifndef _COMPILER_ABSTRACTION_H
-#define _COMPILER_ABSTRACTION_H
-
-/*lint ++flb "Enter library region" */
-
-#if defined ( __CC_ARM )
-    
-    #ifndef __ASM
-        #define __ASM               __asm                       /*!< asm keyword for ARM Compiler */
-    #endif
-    
-    #ifndef __INLINE
-        #define __INLINE            __inline                    /*!< inline keyword for ARM Compiler */
-    #endif
-    
-    #ifndef __WEAK
-        #define __WEAK              __weak                      /*!< weak keyword for ARM Compiler */
-    #endif
-    
-    #define GET_SP()                __current_sp()              /*!> read current SP function for ARM Compiler */
-  
-#elif defined ( __ICCARM__ )
-    
-    #ifndef __ASM
-        #define __ASM               __asm                       /*!< asm keyword for IAR Compiler */
-    #endif
-    
-    #ifndef __INLINE
-        #define __INLINE            inline                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-    #endif
-    
-    #ifndef __WEAK
-        #define __WEAK              __weak                      /*!> define weak function for IAR Compiler */
-    #endif
-    
-    #define GET_SP()                __get_SP()                  /*!> read current SP function for IAR Compiler */
-    
-#elif defined   ( __GNUC__ )
-    
-    #ifndef __ASM
-        #define __ASM               __asm                       /*!< asm keyword for GNU Compiler */
-    #endif
-    
-    #ifndef __INLINE
-        #define __INLINE            inline                      /*!< inline keyword for GNU Compiler */
-    #endif
-    
-    #ifndef __WEAK
-        #define __WEAK              __attribute__((weak))       /*!< weak keyword for GNU Compiler */
-    #endif
-    
-    #define GET_SP()                gcc_current_sp()            /*!> read current SP function for GNU Compiler */
-
-    static inline unsigned int gcc_current_sp(void)
-    {
-        register unsigned sp asm("sp");
-        return sp;
-    }
-    
-#elif defined   ( __TASKING__ )
-        
-    #ifndef __ASM        
-        #define __ASM               __asm                       /*!< asm keyword for TASKING Compiler */
-    #endif
-    
-    #ifndef __INLINE
-        #define __INLINE            inline                      /*!< inline keyword for TASKING Compiler */
-    #endif
-    
-    #ifndef __WEAK
-        #define __WEAK              __attribute__((weak))       /*!< weak keyword for TASKING Compiler */
-    #endif
-    
-    #define GET_SP()                __get_MSP()                 /*!> read current SP function for TASKING Compiler */
-    
-#endif
-
-/*lint --flb "Leave library region" */
-
-#endif
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf.h
--- a/nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* Copyright (c) 2013, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright notice, this
- *     list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright notice,
- *     this list of conditions and the following disclaimer in the documentation
- *     and/or other materials provided with the distribution.
- *
- *   * Neither the name of Nordic Semiconductor ASA nor the names of its
- *     contributors may be used to endorse or promote products derived from
- *     this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-#ifndef NRF_H
-#define NRF_H
-
-#ifndef _WIN32
-
-/* Family selection for main includes. NRF51 must be selected. */
-#ifdef NRF51
-    #include "nrf51.h"
-    #include "nrf51_bitfields.h"
-    #include "nrf51_deprecated.h"
-#else
-    #error "Device family must be defined. See nrf.h."
-#endif /* NRF51 */
-
-#include "compiler_abstraction.h"
-
-#endif /* _WIN32 */
-
-#endif /* NRF_H */
-
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf51.h
--- a/nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf51.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1313 +0,0 @@
-
-/****************************************************************************************************//**
- * @file     nRF51.h
- *
- * @brief    CMSIS Cortex-M0 Peripheral Access Layer Header File for
- *           nRF51 from Nordic Semiconductor.
- *
- * @version  V522
- * @date     31. October 2014
- *
- * @note     Generated with SVDConv V2.81d 
- *           from CMSIS SVD File 'nRF51.xml' Version 522,
- *
- * @par      Copyright (c) 2013, Nordic Semiconductor ASA
- *           All rights reserved.
- *           
- *           Redistribution and use in source and binary forms, with or without
- *           modification, are permitted provided that the following conditions are met:
- *           
- *           * Redistributions of source code must retain the above copyright notice, this
- *           list of conditions and the following disclaimer.
- *           
- *           * Redistributions in binary form must reproduce the above copyright notice,
- *           this list of conditions and the following disclaimer in the documentation
- *           and/or other materials provided with the distribution.
- *           
- *           * Neither the name of Nordic Semiconductor ASA nor the names of its
- *           contributors may be used to endorse or promote products derived from
- *           this software without specific prior written permission.
- *           
- *           THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *           AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *           IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- *           DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- *           FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *           DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- *           SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- *           CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- *           OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *           OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *           
- *
- *******************************************************************************************************/
-
-
-
-/** @addtogroup Nordic Semiconductor
-  * @{
-  */
-
-/** @addtogroup nRF51
-  * @{
-  */
-
-#ifndef NRF51_H
-#define NRF51_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* -------------------------  Interrupt Number Definition  ------------------------ */
-
-typedef enum {
-/* -------------------  Cortex-M0 Processor Exceptions Numbers  ------------------- */
-  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
-  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
-  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
-  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
-  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
-  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
-  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
-/* ----------------------  nRF51 Specific Interrupt Numbers  ---------------------- */
-  POWER_CLOCK_IRQn              =   0,              /*!<   0  POWER_CLOCK                                                      */
-  RADIO_IRQn                    =   1,              /*!<   1  RADIO                                                            */
-  UART0_IRQn                    =   2,              /*!<   2  UART0                                                            */
-  SPI0_TWI0_IRQn                =   3,              /*!<   3  SPI0_TWI0                                                        */
-  SPI1_TWI1_IRQn                =   4,              /*!<   4  SPI1_TWI1                                                        */
-  GPIOTE_IRQn                   =   6,              /*!<   6  GPIOTE                                                           */
-  ADC_IRQn                      =   7,              /*!<   7  ADC                                                              */
-  TIMER0_IRQn                   =   8,              /*!<   8  TIMER0                                                           */
-  TIMER1_IRQn                   =   9,              /*!<   9  TIMER1                                                           */
-  TIMER2_IRQn                   =  10,              /*!<  10  TIMER2                                                           */
-  RTC0_IRQn                     =  11,              /*!<  11  RTC0                                                             */
-  TEMP_IRQn                     =  12,              /*!<  12  TEMP                                                             */
-  RNG_IRQn                      =  13,              /*!<  13  RNG                                                              */
-  ECB_IRQn                      =  14,              /*!<  14  ECB                                                              */
-  CCM_AAR_IRQn                  =  15,              /*!<  15  CCM_AAR                                                          */
-  WDT_IRQn                      =  16,              /*!<  16  WDT                                                              */
-  RTC1_IRQn                     =  17,              /*!<  17  RTC1                                                             */
-  QDEC_IRQn                     =  18,              /*!<  18  QDEC                                                             */
-  LPCOMP_IRQn                   =  19,              /*!<  19  LPCOMP                                                           */
-  SWI0_IRQn                     =  20,              /*!<  20  SWI0                                                             */
-  SWI1_IRQn                     =  21,              /*!<  21  SWI1                                                             */
-  SWI2_IRQn                     =  22,              /*!<  22  SWI2                                                             */
-  SWI3_IRQn                     =  23,              /*!<  23  SWI3                                                             */
-  SWI4_IRQn                     =  24,              /*!<  24  SWI4                                                             */
-  SWI5_IRQn                     =  25               /*!<  25  SWI5                                                             */
-} IRQn_Type;
-
-
-/** @addtogroup Configuration_of_CMSIS
-  * @{
-  */
-
-
-/* ================================================================================ */
-/* ================      Processor and Core Peripheral Section     ================ */
-/* ================================================================================ */
-
-/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
-#define __CM0_REV                 0x0301            /*!< Cortex-M0 Core Revision                                               */
-#define __MPU_PRESENT                  0            /*!< MPU present or not                                                    */
-#define __NVIC_PRIO_BITS               2            /*!< Number of Bits used for Priority Levels                               */
-#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include "core_cm0.h"                               /*!< Cortex-M0 processor and core peripherals                              */
-#include "system_nrf51.h"                           /*!< nRF51 System                                                          */
-
-
-/* ================================================================================ */
-/* ================       Device Specific Peripheral Section       ================ */
-/* ================================================================================ */
-
-
-/** @addtogroup Device_Peripheral_Registers
-  * @{
-  */
-
-
-/* -------------------  Start of section using anonymous unions  ------------------ */
-#if defined(__CC_ARM)
-  #pragma push
-  #pragma anon_unions
-#elif defined(__ICCARM__)
-  #pragma language=extended
-#elif defined(__GNUC__)
-  /* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
-/* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
-  #pragma warning 586
-#else
-  #warning Not supported compiler type
-#endif
-
-
-typedef struct {
-  __IO uint32_t  CPU0;                              /*!< Configurable priority configuration register for CPU0.                */
-  __IO uint32_t  SPIS1;                             /*!< Configurable priority configuration register for SPIS1.               */
-  __IO uint32_t  RADIO;                             /*!< Configurable priority configuration register for RADIO.               */
-  __IO uint32_t  ECB;                               /*!< Configurable priority configuration register for ECB.                 */
-  __IO uint32_t  CCM;                               /*!< Configurable priority configuration register for CCM.                 */
-  __IO uint32_t  AAR;                               /*!< Configurable priority configuration register for AAR.                 */
-} AMLI_RAMPRI_Type;
-
-typedef struct {
-  __IO uint32_t  SCK;                               /*!< Pin select for SCK.                                                   */
-  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI.                                                  */
-  __IO uint32_t  MISO;                              /*!< Pin select for MISO.                                                  */
-} SPIM_PSEL_Type;
-
-typedef struct {
-  __IO uint32_t  PTR;                               /*!< Data pointer.                                                         */
-  __IO uint32_t  MAXCNT;                            /*!< Maximum number of buffer bytes to receive.                            */
-  __I  uint32_t  AMOUNT;                            /*!< Number of bytes received in the last transaction.                     */
-} SPIM_RXD_Type;
-
-typedef struct {
-  __IO uint32_t  PTR;                               /*!< Data pointer.                                                         */
-  __IO uint32_t  MAXCNT;                            /*!< Maximum number of buffer bytes to send.                               */
-  __I  uint32_t  AMOUNT;                            /*!< Number of bytes sent in the last transaction.                         */
-} SPIM_TXD_Type;
-
-typedef struct {
-  __O  uint32_t  EN;                                /*!< Enable channel group.                                                 */
-  __O  uint32_t  DIS;                               /*!< Disable channel group.                                                */
-} PPI_TASKS_CHG_Type;
-
-typedef struct {
-  __IO uint32_t  EEP;                               /*!< Channel event end-point.                                              */
-  __IO uint32_t  TEP;                               /*!< Channel task end-point.                                               */
-} PPI_CH_Type;
-
-typedef struct {
-  __I  uint32_t  PART;                              /*!< Part code                                                             */
-  __I  uint32_t  VARIANT;                           /*!< Part variant                                                          */
-  __I  uint32_t  PACKAGE;                           /*!< Package option                                                        */
-  __I  uint32_t  RAM;                               /*!< RAM variant                                                           */
-  __I  uint32_t  FLASH;                             /*!< Flash variant                                                         */
-  __I  uint32_t  RESERVED[3];                       /*!< Reserved                                                              */
-} FICR_INFO_Type;
-
-
-/* ================================================================================ */
-/* ================                      POWER                     ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Power Control. (POWER)
-  */
-
-typedef struct {                                    /*!< POWER Structure                                                       */
-  __I  uint32_t  RESERVED0[30];
-  __O  uint32_t  TASKS_CONSTLAT;                    /*!< Enable constant latency mode.                                         */
-  __O  uint32_t  TASKS_LOWPWR;                      /*!< Enable low power mode (variable latency).                             */
-  __I  uint32_t  RESERVED1[34];
-  __IO uint32_t  EVENTS_POFWARN;                    /*!< Power failure warning.                                                */
-  __I  uint32_t  RESERVED2[126];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[61];
-  __IO uint32_t  RESETREAS;                         /*!< Reset reason.                                                         */
-  __I  uint32_t  RESERVED4[9];
-  __I  uint32_t  RAMSTATUS;                         /*!< Ram status register.                                                  */
-  __I  uint32_t  RESERVED5[53];
-  __O  uint32_t  SYSTEMOFF;                         /*!< System off register.                                                  */
-  __I  uint32_t  RESERVED6[3];
-  __IO uint32_t  POFCON;                            /*!< Power failure configuration.                                          */
-  __I  uint32_t  RESERVED7[2];
-  __IO uint32_t  GPREGRET;                          /*!< General purpose retention register. This register is a retained
-                                                         register.                                                             */
-  __I  uint32_t  RESERVED8;
-  __IO uint32_t  RAMON;                             /*!< Ram on/off.                                                           */
-  __I  uint32_t  RESERVED9[7];
-  __IO uint32_t  RESET;                             /*!< Pin reset functionality configuration register. This register
-                                                         is a retained register.                                               */
-  __I  uint32_t  RESERVED10[3];
-  __IO uint32_t  RAMONB;                            /*!< Ram on/off.                                                           */
-  __I  uint32_t  RESERVED11[8];
-  __IO uint32_t  DCDCEN;                            /*!< DCDC converter enable configuration register.                         */
-  __I  uint32_t  RESERVED12[291];
-  __IO uint32_t  DCDCFORCE;                         /*!< DCDC power-up force register.                                         */
-} NRF_POWER_Type;
-
-
-/* ================================================================================ */
-/* ================                      CLOCK                     ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Clock control. (CLOCK)
-  */
-
-typedef struct {                                    /*!< CLOCK Structure                                                       */
-  __O  uint32_t  TASKS_HFCLKSTART;                  /*!< Start HFCLK clock source.                                             */
-  __O  uint32_t  TASKS_HFCLKSTOP;                   /*!< Stop HFCLK clock source.                                              */
-  __O  uint32_t  TASKS_LFCLKSTART;                  /*!< Start LFCLK clock source.                                             */
-  __O  uint32_t  TASKS_LFCLKSTOP;                   /*!< Stop LFCLK clock source.                                              */
-  __O  uint32_t  TASKS_CAL;                         /*!< Start calibration of LFCLK RC oscillator.                             */
-  __O  uint32_t  TASKS_CTSTART;                     /*!< Start calibration timer.                                              */
-  __O  uint32_t  TASKS_CTSTOP;                      /*!< Stop calibration timer.                                               */
-  __I  uint32_t  RESERVED0[57];
-  __IO uint32_t  EVENTS_HFCLKSTARTED;               /*!< HFCLK oscillator started.                                             */
-  __IO uint32_t  EVENTS_LFCLKSTARTED;               /*!< LFCLK oscillator started.                                             */
-  __I  uint32_t  RESERVED1;
-  __IO uint32_t  EVENTS_DONE;                       /*!< Calibration of LFCLK RC oscillator completed.                         */
-  __IO uint32_t  EVENTS_CTTO;                       /*!< Calibration timer timeout.                                            */
-  __I  uint32_t  RESERVED2[124];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[63];
-  __I  uint32_t  HFCLKRUN;                          /*!< Task HFCLKSTART trigger status.                                       */
-  __I  uint32_t  HFCLKSTAT;                         /*!< High frequency clock status.                                          */
-  __I  uint32_t  RESERVED4;
-  __I  uint32_t  LFCLKRUN;                          /*!< Task LFCLKSTART triggered status.                                     */
-  __I  uint32_t  LFCLKSTAT;                         /*!< Low frequency clock status.                                           */
-  __I  uint32_t  LFCLKSRCCOPY;                      /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
-                                                         triggered.                                                            */
-  __I  uint32_t  RESERVED5[62];
-  __IO uint32_t  LFCLKSRC;                          /*!< Clock source for the LFCLK clock.                                     */
-  __I  uint32_t  RESERVED6[7];
-  __IO uint32_t  CTIV;                              /*!< Calibration timer interval.                                           */
-  __I  uint32_t  RESERVED7[5];
-  __IO uint32_t  XTALFREQ;                          /*!< Crystal frequency.                                                    */
-} NRF_CLOCK_Type;
-
-
-/* ================================================================================ */
-/* ================                       MPU                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Memory Protection Unit. (MPU)
-  */
-
-typedef struct {                                    /*!< MPU Structure                                                         */
-  __I  uint32_t  RESERVED0[330];
-  __IO uint32_t  PERR0;                             /*!< Configuration of peripherals in mpu regions.                          */
-  __IO uint32_t  RLENR0;                            /*!< Length of RAM region 0.                                               */
-  __I  uint32_t  RESERVED1[52];
-  __IO uint32_t  PROTENSET0;                        /*!< Erase and write protection bit enable set register.                   */
-  __IO uint32_t  PROTENSET1;                        /*!< Erase and write protection bit enable set register.                   */
-  __IO uint32_t  DISABLEINDEBUG;                    /*!< Disable erase and write protection mechanism in debug mode.           */
-  __IO uint32_t  PROTBLOCKSIZE;                     /*!< Erase and write protection block size.                                */
-} NRF_MPU_Type;
-
-
-/* ================================================================================ */
-/* ================                       PU                       ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Patch unit. (PU)
-  */
-
-typedef struct {                                    /*!< PU Structure                                                          */
-  __I  uint32_t  RESERVED0[448];
-  __IO uint32_t  REPLACEADDR[8];                    /*!< Address of first instruction to replace.                              */
-  __I  uint32_t  RESERVED1[24];
-  __IO uint32_t  PATCHADDR[8];                      /*!< Relative address of patch instructions.                               */
-  __I  uint32_t  RESERVED2[24];
-  __IO uint32_t  PATCHEN;                           /*!< Patch enable register.                                                */
-  __IO uint32_t  PATCHENSET;                        /*!< Patch enable register.                                                */
-  __IO uint32_t  PATCHENCLR;                        /*!< Patch disable register.                                               */
-} NRF_PU_Type;
-
-
-/* ================================================================================ */
-/* ================                      AMLI                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief AHB Multi-Layer Interface. (AMLI)
-  */
-
-typedef struct {                                    /*!< AMLI Structure                                                        */
-  __I  uint32_t  RESERVED0[896];
-  AMLI_RAMPRI_Type RAMPRI;                          /*!< RAM configurable priority configuration structure.                    */
-} NRF_AMLI_Type;
-
-
-/* ================================================================================ */
-/* ================                      RADIO                     ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief The radio. (RADIO)
-  */
-
-typedef struct {                                    /*!< RADIO Structure                                                       */
-  __O  uint32_t  TASKS_TXEN;                        /*!< Enable radio in TX mode.                                              */
-  __O  uint32_t  TASKS_RXEN;                        /*!< Enable radio in RX mode.                                              */
-  __O  uint32_t  TASKS_START;                       /*!< Start radio.                                                          */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop radio.                                                           */
-  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable radio.                                                        */
-  __O  uint32_t  TASKS_RSSISTART;                   /*!< Start the RSSI and take one sample of the receive signal strength.    */
-  __O  uint32_t  TASKS_RSSISTOP;                    /*!< Stop the RSSI measurement.                                            */
-  __O  uint32_t  TASKS_BCSTART;                     /*!< Start the bit counter.                                                */
-  __O  uint32_t  TASKS_BCSTOP;                      /*!< Stop the bit counter.                                                 */
-  __I  uint32_t  RESERVED0[55];
-  __IO uint32_t  EVENTS_READY;                      /*!< Ready event.                                                          */
-  __IO uint32_t  EVENTS_ADDRESS;                    /*!< Address event.                                                        */
-  __IO uint32_t  EVENTS_PAYLOAD;                    /*!< Payload event.                                                        */
-  __IO uint32_t  EVENTS_END;                        /*!< End event.                                                            */
-  __IO uint32_t  EVENTS_DISABLED;                   /*!< Disable event.                                                        */
-  __IO uint32_t  EVENTS_DEVMATCH;                   /*!< A device address match occurred on the last received packet.          */
-  __IO uint32_t  EVENTS_DEVMISS;                    /*!< No device address match occurred on the last received packet.         */
-  __IO uint32_t  EVENTS_RSSIEND;                    /*!< Sampling of the receive signal strength complete. A new RSSI
-                                                         sample is ready for readout at the RSSISAMPLE register.               */
-  __I  uint32_t  RESERVED1[2];
-  __IO uint32_t  EVENTS_BCMATCH;                    /*!< Bit counter reached bit count value specified in BC register.         */
-  __I  uint32_t  RESERVED2[53];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the radio.                                              */
-  __I  uint32_t  RESERVED3[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED4[61];
-  __I  uint32_t  CRCSTATUS;                         /*!< CRC status of received packet.                                        */
-  __I  uint32_t  CD;                                /*!< Carrier detect.                                                       */
-  __I  uint32_t  RXMATCH;                           /*!< Received address.                                                     */
-  __I  uint32_t  RXCRC;                             /*!< Received CRC.                                                         */
-  __I  uint32_t  DAI;                               /*!< Device address match index.                                           */
-  __I  uint32_t  RESERVED5[60];
-  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer. Decision point: START task.                           */
-  __IO uint32_t  FREQUENCY;                         /*!< Frequency.                                                            */
-  __IO uint32_t  TXPOWER;                           /*!< Output power.                                                         */
-  __IO uint32_t  MODE;                              /*!< Data rate and modulation.                                             */
-  __IO uint32_t  PCNF0;                             /*!< Packet configuration 0.                                               */
-  __IO uint32_t  PCNF1;                             /*!< Packet configuration 1.                                               */
-  __IO uint32_t  BASE0;                             /*!< Radio base address 0. Decision point: START task.                     */
-  __IO uint32_t  BASE1;                             /*!< Radio base address 1. Decision point: START task.                     */
-  __IO uint32_t  PREFIX0;                           /*!< Prefixes bytes for logical addresses 0 to 3.                          */
-  __IO uint32_t  PREFIX1;                           /*!< Prefixes bytes for logical addresses 4 to 7.                          */
-  __IO uint32_t  TXADDRESS;                         /*!< Transmit address select.                                              */
-  __IO uint32_t  RXADDRESSES;                       /*!< Receive address select.                                               */
-  __IO uint32_t  CRCCNF;                            /*!< CRC configuration.                                                    */
-  __IO uint32_t  CRCPOLY;                           /*!< CRC polynomial.                                                       */
-  __IO uint32_t  CRCINIT;                           /*!< CRC initial value.                                                    */
-  __IO uint32_t  TEST;                              /*!< Test features enable register.                                        */
-  __IO uint32_t  TIFS;                              /*!< Inter Frame Spacing in microseconds.                                  */
-  __I  uint32_t  RSSISAMPLE;                        /*!< RSSI sample.                                                          */
-  __I  uint32_t  RESERVED6;
-  __I  uint32_t  STATE;                             /*!< Current radio state.                                                  */
-  __IO uint32_t  DATAWHITEIV;                       /*!< Data whitening initial value.                                         */
-  __I  uint32_t  RESERVED7[2];
-  __IO uint32_t  BCC;                               /*!< Bit counter compare.                                                  */
-  __I  uint32_t  RESERVED8[39];
-  __IO uint32_t  DAB[8];                            /*!< Device address base segment.                                          */
-  __IO uint32_t  DAP[8];                            /*!< Device address prefix.                                                */
-  __IO uint32_t  DACNF;                             /*!< Device address match configuration.                                   */
-  __I  uint32_t  RESERVED9[56];
-  __IO uint32_t  OVERRIDE0;                         /*!< Trim value override register 0.                                       */
-  __IO uint32_t  OVERRIDE1;                         /*!< Trim value override register 1.                                       */
-  __IO uint32_t  OVERRIDE2;                         /*!< Trim value override register 2.                                       */
-  __IO uint32_t  OVERRIDE3;                         /*!< Trim value override register 3.                                       */
-  __IO uint32_t  OVERRIDE4;                         /*!< Trim value override register 4.                                       */
-  __I  uint32_t  RESERVED10[561];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_RADIO_Type;
-
-
-/* ================================================================================ */
-/* ================                      UART                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Universal Asynchronous Receiver/Transmitter. (UART)
-  */
-
-typedef struct {                                    /*!< UART Structure                                                        */
-  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver.                                                  */
-  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver.                                                   */
-  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter.                                               */
-  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter.                                                */
-  __I  uint32_t  RESERVED0[3];
-  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend UART.                                                         */
-  __I  uint32_t  RESERVED1[56];
-  __IO uint32_t  EVENTS_CTS;                        /*!< CTS activated.                                                        */
-  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS deactivated.                                                      */
-  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD.                                                 */
-  __I  uint32_t  RESERVED2[4];
-  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD.                                                   */
-  __I  uint32_t  RESERVED3;
-  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected.                                                       */
-  __I  uint32_t  RESERVED4[7];
-  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout.                                                     */
-  __I  uint32_t  RESERVED5[46];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for UART.                                                   */
-  __I  uint32_t  RESERVED6[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED7[93];
-  __IO uint32_t  ERRORSRC;                          /*!< Error source. Write error field to 1 to clear error.                  */
-  __I  uint32_t  RESERVED8[31];
-  __IO uint32_t  ENABLE;                            /*!< Enable UART and acquire IOs.                                          */
-  __I  uint32_t  RESERVED9;
-  __IO uint32_t  PSELRTS;                           /*!< Pin select for RTS.                                                   */
-  __IO uint32_t  PSELTXD;                           /*!< Pin select for TXD.                                                   */
-  __IO uint32_t  PSELCTS;                           /*!< Pin select for CTS.                                                   */
-  __IO uint32_t  PSELRXD;                           /*!< Pin select for RXD.                                                   */
-  __I  uint32_t  RXD;                               /*!< RXD register. On read action the buffer pointer is displaced.
-                                                         Once read the character is consumed. If read when no character
-                                                          available, the UART will stop working.                               */
-  __O  uint32_t  TXD;                               /*!< TXD register.                                                         */
-  __I  uint32_t  RESERVED10;
-  __IO uint32_t  BAUDRATE;                          /*!< UART Baudrate.                                                        */
-  __I  uint32_t  RESERVED11[17];
-  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control register.           */
-  __I  uint32_t  RESERVED12[675];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_UART_Type;
-
-
-/* ================================================================================ */
-/* ================                       SPI                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief SPI master 0. (SPI)
-  */
-
-typedef struct {                                    /*!< SPI Structure                                                         */
-  __I  uint32_t  RESERVED0[66];
-  __IO uint32_t  EVENTS_READY;                      /*!< TXD byte sent and RXD byte received.                                  */
-  __I  uint32_t  RESERVED1[126];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED2[125];
-  __IO uint32_t  ENABLE;                            /*!< Enable SPI.                                                           */
-  __I  uint32_t  RESERVED3;
-  __IO uint32_t  PSELSCK;                           /*!< Pin select for SCK.                                                   */
-  __IO uint32_t  PSELMOSI;                          /*!< Pin select for MOSI.                                                  */
-  __IO uint32_t  PSELMISO;                          /*!< Pin select for MISO.                                                  */
-  __I  uint32_t  RESERVED4;
-  __I  uint32_t  RXD;                               /*!< RX data.                                                              */
-  __IO uint32_t  TXD;                               /*!< TX data.                                                              */
-  __I  uint32_t  RESERVED5;
-  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */
-  __I  uint32_t  RESERVED6[11];
-  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
-  __I  uint32_t  RESERVED7[681];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_SPI_Type;
-
-
-/* ================================================================================ */
-/* ================                       TWI                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Two-wire interface master 0. (TWI)
-  */
-
-typedef struct {                                    /*!< TWI Structure                                                         */
-  __O  uint32_t  TASKS_STARTRX;                     /*!< Start 2-Wire master receive sequence.                                 */
-  __I  uint32_t  RESERVED0;
-  __O  uint32_t  TASKS_STARTTX;                     /*!< Start 2-Wire master transmit sequence.                                */
-  __I  uint32_t  RESERVED1[2];
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop 2-Wire transaction.                                              */
-  __I  uint32_t  RESERVED2;
-  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend 2-Wire transaction.                                           */
-  __O  uint32_t  TASKS_RESUME;                      /*!< Resume 2-Wire transaction.                                            */
-  __I  uint32_t  RESERVED3[56];
-  __IO uint32_t  EVENTS_STOPPED;                    /*!< Two-wire stopped.                                                     */
-  __IO uint32_t  EVENTS_RXDREADY;                   /*!< Two-wire ready to deliver new RXD byte received.                      */
-  __I  uint32_t  RESERVED4[4];
-  __IO uint32_t  EVENTS_TXDSENT;                    /*!< Two-wire finished sending last TXD byte.                              */
-  __I  uint32_t  RESERVED5;
-  __IO uint32_t  EVENTS_ERROR;                      /*!< Two-wire error detected.                                              */
-  __I  uint32_t  RESERVED6[4];
-  __IO uint32_t  EVENTS_BB;                         /*!< Two-wire byte boundary.                                               */
-  __I  uint32_t  RESERVED7[3];
-  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< Two-wire suspended.                                                   */
-  __I  uint32_t  RESERVED8[45];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for TWI.                                                    */
-  __I  uint32_t  RESERVED9[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED10[110];
-  __IO uint32_t  ERRORSRC;                          /*!< Two-wire error source. Write error field to 1 to clear error.         */
-  __I  uint32_t  RESERVED11[14];
-  __IO uint32_t  ENABLE;                            /*!< Enable two-wire master.                                               */
-  __I  uint32_t  RESERVED12;
-  __IO uint32_t  PSELSCL;                           /*!< Pin select for SCL.                                                   */
-  __IO uint32_t  PSELSDA;                           /*!< Pin select for SDA.                                                   */
-  __I  uint32_t  RESERVED13[2];
-  __I  uint32_t  RXD;                               /*!< RX data register.                                                     */
-  __IO uint32_t  TXD;                               /*!< TX data register.                                                     */
-  __I  uint32_t  RESERVED14;
-  __IO uint32_t  FREQUENCY;                         /*!< Two-wire frequency.                                                   */
-  __I  uint32_t  RESERVED15[24];
-  __IO uint32_t  ADDRESS;                           /*!< Address used in the two-wire transfer.                                */
-  __I  uint32_t  RESERVED16[668];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_TWI_Type;
-
-
-/* ================================================================================ */
-/* ================                      SPIS                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief SPI slave 1. (SPIS)
-  */
-
-typedef struct {                                    /*!< SPIS Structure                                                        */
-  __I  uint32_t  RESERVED0[9];
-  __O  uint32_t  TASKS_ACQUIRE;                     /*!< Acquire SPI semaphore.                                                */
-  __O  uint32_t  TASKS_RELEASE;                     /*!< Release SPI semaphore.                                                */
-  __I  uint32_t  RESERVED1[54];
-  __IO uint32_t  EVENTS_END;                        /*!< Granted transaction completed.                                        */
-  __I  uint32_t  RESERVED2[8];
-  __IO uint32_t  EVENTS_ACQUIRED;                   /*!< Semaphore acquired.                                                   */
-  __I  uint32_t  RESERVED3[53];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for SPIS.                                                   */
-  __I  uint32_t  RESERVED4[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED5[61];
-  __I  uint32_t  SEMSTAT;                           /*!< Semaphore status.                                                     */
-  __I  uint32_t  RESERVED6[15];
-  __IO uint32_t  STATUS;                            /*!< Status from last transaction.                                         */
-  __I  uint32_t  RESERVED7[47];
-  __IO uint32_t  ENABLE;                            /*!< Enable SPIS.                                                          */
-  __I  uint32_t  RESERVED8;
-  __IO uint32_t  PSELSCK;                           /*!< Pin select for SCK.                                                   */
-  __IO uint32_t  PSELMISO;                          /*!< Pin select for MISO.                                                  */
-  __IO uint32_t  PSELMOSI;                          /*!< Pin select for MOSI.                                                  */
-  __IO uint32_t  PSELCSN;                           /*!< Pin select for CSN.                                                   */
-  __I  uint32_t  RESERVED9[7];
-  __IO uint32_t  RXDPTR;                            /*!< RX data pointer.                                                      */
-  __IO uint32_t  MAXRX;                             /*!< Maximum number of bytes in the receive buffer.                        */
-  __I  uint32_t  AMOUNTRX;                          /*!< Number of bytes received in last granted transaction.                 */
-  __I  uint32_t  RESERVED10;
-  __IO uint32_t  TXDPTR;                            /*!< TX data pointer.                                                      */
-  __IO uint32_t  MAXTX;                             /*!< Maximum number of bytes in the transmit buffer.                       */
-  __I  uint32_t  AMOUNTTX;                          /*!< Number of bytes transmitted in last granted transaction.              */
-  __I  uint32_t  RESERVED11;
-  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
-  __I  uint32_t  RESERVED12;
-  __IO uint32_t  DEF;                               /*!< Default character.                                                    */
-  __I  uint32_t  RESERVED13[24];
-  __IO uint32_t  ORC;                               /*!< Over-read character.                                                  */
-  __I  uint32_t  RESERVED14[654];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_SPIS_Type;
-
-
-/* ================================================================================ */
-/* ================                      SPIM                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief SPI master with easyDMA 1. (SPIM)
-  */
-
-typedef struct {                                    /*!< SPIM Structure                                                        */
-  __I  uint32_t  RESERVED0[4];
-  __O  uint32_t  TASKS_START;                       /*!< Start SPI transaction.                                                */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop SPI transaction.                                                 */
-  __I  uint32_t  RESERVED1;
-  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend SPI transaction.                                              */
-  __O  uint32_t  TASKS_RESUME;                      /*!< Resume SPI transaction.                                               */
-  __I  uint32_t  RESERVED2[56];
-  __IO uint32_t  EVENTS_STOPPED;                    /*!< SPI transaction has stopped.                                          */
-  __I  uint32_t  RESERVED3[2];
-  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached.                                            */
-  __I  uint32_t  RESERVED4;
-  __IO uint32_t  EVENTS_END;                        /*!< End of RXD buffer and TXD buffer reached.                             */
-  __I  uint32_t  RESERVED5;
-  __IO uint32_t  EVENTS_ENDTX;                      /*!< End of TXD buffer reached.                                            */
-  __I  uint32_t  RESERVED6[10];
-  __IO uint32_t  EVENTS_STARTED;                    /*!< Transaction started.                                                  */
-  __I  uint32_t  RESERVED7[44];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for SPIM.                                                   */
-  __I  uint32_t  RESERVED8[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED9[125];
-  __IO uint32_t  ENABLE;                            /*!< Enable SPIM.                                                          */
-  __I  uint32_t  RESERVED10;
-  SPIM_PSEL_Type PSEL;                              /*!< Pin select configuration.                                             */
-  __I  uint32_t  RESERVED11;
-  __I  uint32_t  RXDDATA;                           /*!< RXD register.                                                         */
-  __IO uint32_t  TXDDATA;                           /*!< TXD register.                                                         */
-  __I  uint32_t  RESERVED12;
-  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency.                                                        */
-  __I  uint32_t  RESERVED13[3];
-  SPIM_RXD_Type RXD;                                /*!< RXD EasyDMA configuration and status.                                 */
-  __I  uint32_t  RESERVED14;
-  SPIM_TXD_Type TXD;                                /*!< TXD EasyDMA configuration and status.                                 */
-  __I  uint32_t  RESERVED15;
-  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
-  __I  uint32_t  RESERVED16[26];
-  __IO uint32_t  ORC;                               /*!< Over-read character.                                                  */
-  __I  uint32_t  RESERVED17[654];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_SPIM_Type;
-
-
-/* ================================================================================ */
-/* ================                     GPIOTE                     ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief GPIO tasks and events. (GPIOTE)
-  */
-
-typedef struct {                                    /*!< GPIOTE Structure                                                      */
-  __O  uint32_t  TASKS_OUT[4];                      /*!< Tasks asssociated with GPIOTE channels.                               */
-  __I  uint32_t  RESERVED0[60];
-  __IO uint32_t  EVENTS_IN[4];                      /*!< Tasks asssociated with GPIOTE channels.                               */
-  __I  uint32_t  RESERVED1[27];
-  __IO uint32_t  EVENTS_PORT;                       /*!< Event generated from multiple pins.                                   */
-  __I  uint32_t  RESERVED2[97];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[129];
-  __IO uint32_t  CONFIG[4];                         /*!< Channel configuration registers.                                      */
-  __I  uint32_t  RESERVED4[695];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_GPIOTE_Type;
-
-
-/* ================================================================================ */
-/* ================                       ADC                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Analog to digital converter. (ADC)
-  */
-
-typedef struct {                                    /*!< ADC Structure                                                         */
-  __O  uint32_t  TASKS_START;                       /*!< Start an ADC conversion.                                              */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop ADC.                                                             */
-  __I  uint32_t  RESERVED0[62];
-  __IO uint32_t  EVENTS_END;                        /*!< ADC conversion complete.                                              */
-  __I  uint32_t  RESERVED1[128];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED2[61];
-  __I  uint32_t  BUSY;                              /*!< ADC busy register.                                                    */
-  __I  uint32_t  RESERVED3[63];
-  __IO uint32_t  ENABLE;                            /*!< ADC enable.                                                           */
-  __IO uint32_t  CONFIG;                            /*!< ADC configuration register.                                           */
-  __I  uint32_t  RESULT;                            /*!< Result of ADC conversion.                                             */
-  __I  uint32_t  RESERVED4[700];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_ADC_Type;
-
-
-/* ================================================================================ */
-/* ================                      TIMER                     ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Timer 0. (TIMER)
-  */
-
-typedef struct {                                    /*!< TIMER Structure                                                       */
-  __O  uint32_t  TASKS_START;                       /*!< Start Timer.                                                          */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop Timer.                                                           */
-  __O  uint32_t  TASKS_COUNT;                       /*!< Increment Timer (In counter mode).                                    */
-  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear timer.                                                          */
-  __O  uint32_t  TASKS_SHUTDOWN;                    /*!< Shutdown timer.                                                       */
-  __I  uint32_t  RESERVED0[11];
-  __O  uint32_t  TASKS_CAPTURE[4];                  /*!< Capture Timer value to CC[n] registers.                               */
-  __I  uint32_t  RESERVED1[60];
-  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Compare event on CC[n] match.                                         */
-  __I  uint32_t  RESERVED2[44];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for Timer.                                                  */
-  __I  uint32_t  RESERVED3[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED4[126];
-  __IO uint32_t  MODE;                              /*!< Timer Mode selection.                                                 */
-  __IO uint32_t  BITMODE;                           /*!< Sets timer behaviour.                                                 */
-  __I  uint32_t  RESERVED5;
-  __IO uint32_t  PRESCALER;                         /*!< 4-bit prescaler to source clock frequency (max value 9). Source
-                                                         clock frequency is divided by 2^SCALE.                                */
-  __I  uint32_t  RESERVED6[11];
-  __IO uint32_t  CC[4];                             /*!< Capture/compare registers.                                            */
-  __I  uint32_t  RESERVED7[683];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_TIMER_Type;
-
-
-/* ================================================================================ */
-/* ================                       RTC                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Real time counter 0. (RTC)
-  */
-
-typedef struct {                                    /*!< RTC Structure                                                         */
-  __O  uint32_t  TASKS_START;                       /*!< Start RTC Counter.                                                    */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop RTC Counter.                                                     */
-  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear RTC Counter.                                                    */
-  __O  uint32_t  TASKS_TRIGOVRFLW;                  /*!< Set COUNTER to 0xFFFFFFF0.                                            */
-  __I  uint32_t  RESERVED0[60];
-  __IO uint32_t  EVENTS_TICK;                       /*!< Event on COUNTER increment.                                           */
-  __IO uint32_t  EVENTS_OVRFLW;                     /*!< Event on COUNTER overflow.                                            */
-  __I  uint32_t  RESERVED1[14];
-  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Compare event on CC[n] match.                                         */
-  __I  uint32_t  RESERVED2[109];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[13];
-  __IO uint32_t  EVTEN;                             /*!< Configures event enable routing to PPI for each RTC event.            */
-  __IO uint32_t  EVTENSET;                          /*!< Enable events routing to PPI. The reading of this register gives
-                                                         the value of EVTEN.                                                   */
-  __IO uint32_t  EVTENCLR;                          /*!< Disable events routing to PPI. The reading of this register
-                                                         gives the value of EVTEN.                                             */
-  __I  uint32_t  RESERVED4[110];
-  __I  uint32_t  COUNTER;                           /*!< Current COUNTER value.                                                */
-  __IO uint32_t  PRESCALER;                         /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
-                                                         Must be written when RTC is STOPed.                                   */
-  __I  uint32_t  RESERVED5[13];
-  __IO uint32_t  CC[4];                             /*!< Capture/compare registers.                                            */
-  __I  uint32_t  RESERVED6[683];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_RTC_Type;
-
-
-/* ================================================================================ */
-/* ================                      TEMP                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Temperature Sensor. (TEMP)
-  */
-
-typedef struct {                                    /*!< TEMP Structure                                                        */
-  __O  uint32_t  TASKS_START;                       /*!< Start temperature measurement.                                        */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop temperature measurement.                                         */
-  __I  uint32_t  RESERVED0[62];
-  __IO uint32_t  EVENTS_DATARDY;                    /*!< Temperature measurement complete, data ready event.                   */
-  __I  uint32_t  RESERVED1[128];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED2[127];
-  __I  int32_t   TEMP;                              /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision.   */
-  __I  uint32_t  RESERVED3[700];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_TEMP_Type;
-
-
-/* ================================================================================ */
-/* ================                       RNG                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Random Number Generator. (RNG)
-  */
-
-typedef struct {                                    /*!< RNG Structure                                                         */
-  __O  uint32_t  TASKS_START;                       /*!< Start the random number generator.                                    */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop the random number generator.                                     */
-  __I  uint32_t  RESERVED0[62];
-  __IO uint32_t  EVENTS_VALRDY;                     /*!< New random number generated and written to VALUE register.            */
-  __I  uint32_t  RESERVED1[63];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the RNG.                                                */
-  __I  uint32_t  RESERVED2[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register                                         */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register                                       */
-  __I  uint32_t  RESERVED3[126];
-  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
-  __I  uint32_t  VALUE;                             /*!< RNG random number.                                                    */
-  __I  uint32_t  RESERVED4[700];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_RNG_Type;
-
-
-/* ================================================================================ */
-/* ================                       ECB                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief AES ECB Mode Encryption. (ECB)
-  */
-
-typedef struct {                                    /*!< ECB Structure                                                         */
-  __O  uint32_t  TASKS_STARTECB;                    /*!< Start ECB block encrypt. If a crypto operation is running, this
-                                                         will not initiate a new encryption and the ERRORECB event will
-                                                          be triggered.                                                        */
-  __O  uint32_t  TASKS_STOPECB;                     /*!< Stop current ECB encryption. If a crypto operation is running,
-                                                         this will will trigger the ERRORECB event.                            */
-  __I  uint32_t  RESERVED0[62];
-  __IO uint32_t  EVENTS_ENDECB;                     /*!< ECB block encrypt complete.                                           */
-  __IO uint32_t  EVENTS_ERRORECB;                   /*!< ECB block encrypt aborted due to a STOPECB task or due to an
-                                                         error.                                                                */
-  __I  uint32_t  RESERVED1[127];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED2[126];
-  __IO uint32_t  ECBDATAPTR;                        /*!< ECB block encrypt memory pointer.                                     */
-  __I  uint32_t  RESERVED3[701];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_ECB_Type;
-
-
-/* ================================================================================ */
-/* ================                       AAR                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Accelerated Address Resolver. (AAR)
-  */
-
-typedef struct {                                    /*!< AAR Structure                                                         */
-  __O  uint32_t  TASKS_START;                       /*!< Start resolving addresses based on IRKs specified in the IRK
-                                                         data structure.                                                       */
-  __I  uint32_t  RESERVED0;
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop resolving addresses.                                             */
-  __I  uint32_t  RESERVED1[61];
-  __IO uint32_t  EVENTS_END;                        /*!< Address resolution procedure completed.                               */
-  __IO uint32_t  EVENTS_RESOLVED;                   /*!< Address resolved.                                                     */
-  __IO uint32_t  EVENTS_NOTRESOLVED;                /*!< Address not resolved.                                                 */
-  __I  uint32_t  RESERVED2[126];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[61];
-  __I  uint32_t  STATUS;                            /*!< Resolution status.                                                    */
-  __I  uint32_t  RESERVED4[63];
-  __IO uint32_t  ENABLE;                            /*!< Enable AAR.                                                           */
-  __IO uint32_t  NIRK;                              /*!< Number of Identity root Keys in the IRK data structure.               */
-  __IO uint32_t  IRKPTR;                            /*!< Pointer to the IRK data structure.                                    */
-  __I  uint32_t  RESERVED5;
-  __IO uint32_t  ADDRPTR;                           /*!< Pointer to the resolvable address (6 bytes).                          */
-  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a "scratch" data area used for temporary storage
-                                                         during resolution. A minimum of 3 bytes must be reserved.             */
-  __I  uint32_t  RESERVED6[697];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_AAR_Type;
-
-
-/* ================================================================================ */
-/* ================                       CCM                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief AES CCM Mode Encryption. (CCM)
-  */
-
-typedef struct {                                    /*!< CCM Structure                                                         */
-  __O  uint32_t  TASKS_KSGEN;                       /*!< Start generation of key-stream. This operation will stop by
-                                                         itself when completed.                                                */
-  __O  uint32_t  TASKS_CRYPT;                       /*!< Start encrypt/decrypt. This operation will stop by itself when
-                                                         completed.                                                            */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop encrypt/decrypt.                                                 */
-  __I  uint32_t  RESERVED0[61];
-  __IO uint32_t  EVENTS_ENDKSGEN;                   /*!< Keystream generation completed.                                       */
-  __IO uint32_t  EVENTS_ENDCRYPT;                   /*!< Encrypt/decrypt completed.                                            */
-  __IO uint32_t  EVENTS_ERROR;                      /*!< Error happened.                                                       */
-  __I  uint32_t  RESERVED1[61];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the CCM.                                                */
-  __I  uint32_t  RESERVED2[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[61];
-  __I  uint32_t  MICSTATUS;                         /*!< CCM RX MIC check result.                                              */
-  __I  uint32_t  RESERVED4[63];
-  __IO uint32_t  ENABLE;                            /*!< CCM enable.                                                           */
-  __IO uint32_t  MODE;                              /*!< Operation mode.                                                       */
-  __IO uint32_t  CNFPTR;                            /*!< Pointer to a data structure holding AES key and NONCE vector.         */
-  __IO uint32_t  INPTR;                             /*!< Pointer to the input packet.                                          */
-  __IO uint32_t  OUTPTR;                            /*!< Pointer to the output packet.                                         */
-  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a "scratch" data area used for temporary storage
-                                                         during resolution. A minimum of 43 bytes must be reserved.            */
-  __I  uint32_t  RESERVED5[697];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_CCM_Type;
-
-
-/* ================================================================================ */
-/* ================                       WDT                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Watchdog Timer. (WDT)
-  */
-
-typedef struct {                                    /*!< WDT Structure                                                         */
-  __O  uint32_t  TASKS_START;                       /*!< Start the watchdog.                                                   */
-  __I  uint32_t  RESERVED0[63];
-  __IO uint32_t  EVENTS_TIMEOUT;                    /*!< Watchdog timeout.                                                     */
-  __I  uint32_t  RESERVED1[128];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED2[61];
-  __I  uint32_t  RUNSTATUS;                         /*!< Watchdog running status.                                              */
-  __I  uint32_t  REQSTATUS;                         /*!< Request status.                                                       */
-  __I  uint32_t  RESERVED3[63];
-  __IO uint32_t  CRV;                               /*!< Counter reload value in number of 32kiHz clock cycles.                */
-  __IO uint32_t  RREN;                              /*!< Reload request enable.                                                */
-  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
-  __I  uint32_t  RESERVED4[60];
-  __O  uint32_t  RR[8];                             /*!< Reload requests registers.                                            */
-  __I  uint32_t  RESERVED5[631];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_WDT_Type;
-
-
-/* ================================================================================ */
-/* ================                      QDEC                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Rotary decoder. (QDEC)
-  */
-
-typedef struct {                                    /*!< QDEC Structure                                                        */
-  __O  uint32_t  TASKS_START;                       /*!< Start the quadrature decoder.                                         */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop the quadrature decoder.                                          */
-  __O  uint32_t  TASKS_READCLRACC;                  /*!< Transfers the content from ACC registers to ACCREAD registers,
-                                                         and clears the ACC registers.                                         */
-  __I  uint32_t  RESERVED0[61];
-  __IO uint32_t  EVENTS_SAMPLERDY;                  /*!< A new sample is written to the sample register.                       */
-  __IO uint32_t  EVENTS_REPORTRDY;                  /*!< REPORTPER number of samples accumulated in ACC register, and
-                                                         ACC register different than zero.                                     */
-  __IO uint32_t  EVENTS_ACCOF;                      /*!< ACC or ACCDBL register overflow.                                      */
-  __I  uint32_t  RESERVED1[61];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the QDEC.                                               */
-  __I  uint32_t  RESERVED2[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[125];
-  __IO uint32_t  ENABLE;                            /*!< Enable the QDEC.                                                      */
-  __IO uint32_t  LEDPOL;                            /*!< LED output pin polarity.                                              */
-  __IO uint32_t  SAMPLEPER;                         /*!< Sample period.                                                        */
-  __I  int32_t   SAMPLE;                            /*!< Motion sample value.                                                  */
-  __IO uint32_t  REPORTPER;                         /*!< Number of samples to generate an EVENT_REPORTRDY.                     */
-  __I  int32_t   ACC;                               /*!< Accumulated valid transitions register.                               */
-  __I  int32_t   ACCREAD;                           /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
-                                                         task.                                                                 */
-  __IO uint32_t  PSELLED;                           /*!< Pin select for LED output.                                            */
-  __IO uint32_t  PSELA;                             /*!< Pin select for phase A input.                                         */
-  __IO uint32_t  PSELB;                             /*!< Pin select for phase B input.                                         */
-  __IO uint32_t  DBFEN;                             /*!< Enable debouncer input filters.                                       */
-  __I  uint32_t  RESERVED4[5];
-  __IO uint32_t  LEDPRE;                            /*!< Time LED is switched ON before the sample.                            */
-  __I  uint32_t  ACCDBL;                            /*!< Accumulated double (error) transitions register.                      */
-  __I  uint32_t  ACCDBLREAD;                        /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
-                                                         task.                                                                 */
-  __I  uint32_t  RESERVED5[684];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_QDEC_Type;
-
-
-/* ================================================================================ */
-/* ================                     LPCOMP                     ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Low power comparator. (LPCOMP)
-  */
-
-typedef struct {                                    /*!< LPCOMP Structure                                                      */
-  __O  uint32_t  TASKS_START;                       /*!< Start the comparator.                                                 */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop the comparator.                                                  */
-  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value.                                              */
-  __I  uint32_t  RESERVED0[61];
-  __IO uint32_t  EVENTS_READY;                      /*!< LPCOMP is ready and output is valid.                                  */
-  __IO uint32_t  EVENTS_DOWN;                       /*!< Input voltage crossed the threshold going down.                       */
-  __IO uint32_t  EVENTS_UP;                         /*!< Input voltage crossed the threshold going up.                         */
-  __IO uint32_t  EVENTS_CROSS;                      /*!< Input voltage crossed the threshold in any direction.                 */
-  __I  uint32_t  RESERVED1[60];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the LPCOMP.                                             */
-  __I  uint32_t  RESERVED2[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[61];
-  __I  uint32_t  RESULT;                            /*!< Result of last compare.                                               */
-  __I  uint32_t  RESERVED4[63];
-  __IO uint32_t  ENABLE;                            /*!< Enable the LPCOMP.                                                    */
-  __IO uint32_t  PSEL;                              /*!< Input pin select.                                                     */
-  __IO uint32_t  REFSEL;                            /*!< Reference select.                                                     */
-  __IO uint32_t  EXTREFSEL;                         /*!< External reference select.                                            */
-  __I  uint32_t  RESERVED5[4];
-  __IO uint32_t  ANADETECT;                         /*!< Analog detect configuration.                                          */
-  __I  uint32_t  RESERVED6[694];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_LPCOMP_Type;
-
-
-/* ================================================================================ */
-/* ================                       SWI                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief SW Interrupts. (SWI)
-  */
-
-typedef struct {                                    /*!< SWI Structure                                                         */
-  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
-} NRF_SWI_Type;
-
-
-/* ================================================================================ */
-/* ================                      NVMC                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Non Volatile Memory Controller. (NVMC)
-  */
-
-typedef struct {                                    /*!< NVMC Structure                                                        */
-  __I  uint32_t  RESERVED0[256];
-  __I  uint32_t  READY;                             /*!< Ready flag.                                                           */
-  __I  uint32_t  RESERVED1[64];
-  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
-  __IO uint32_t  ERASEPAGE;                         /*!< Register for erasing a non-protected non-volatile memory page.        */
-  __IO uint32_t  ERASEALL;                          /*!< Register for erasing all non-volatile user memory.                    */
-  __IO uint32_t  ERASEPROTECTEDPAGE;                /*!< Register for erasing a protected non-volatile memory page.            */
-  __IO uint32_t  ERASEUICR;                         /*!< Register for start erasing User Information Congfiguration Registers. */
-} NRF_NVMC_Type;
-
-
-/* ================================================================================ */
-/* ================                       PPI                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief PPI controller. (PPI)
-  */
-
-typedef struct {                                    /*!< PPI Structure                                                         */
-  PPI_TASKS_CHG_Type TASKS_CHG[4];                  /*!< Channel group tasks.                                                  */
-  __I  uint32_t  RESERVED0[312];
-  __IO uint32_t  CHEN;                              /*!< Channel enable.                                                       */
-  __IO uint32_t  CHENSET;                           /*!< Channel enable set.                                                   */
-  __IO uint32_t  CHENCLR;                           /*!< Channel enable clear.                                                 */
-  __I  uint32_t  RESERVED1;
-  PPI_CH_Type CH[16];                               /*!< PPI Channel.                                                          */
-  __I  uint32_t  RESERVED2[156];
-  __IO uint32_t  CHG[4];                            /*!< Channel group configuration.                                          */
-} NRF_PPI_Type;
-
-
-/* ================================================================================ */
-/* ================                      FICR                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Factory Information Configuration. (FICR)
-  */
-
-typedef struct {                                    /*!< FICR Structure                                                        */
-  __I  uint32_t  RESERVED0[4];
-  __I  uint32_t  CODEPAGESIZE;                      /*!< Code memory page size in bytes.                                       */
-  __I  uint32_t  CODESIZE;                          /*!< Code memory size in pages.                                            */
-  __I  uint32_t  RESERVED1[4];
-  __I  uint32_t  CLENR0;                            /*!< Length of code region 0 in bytes.                                     */
-  __I  uint32_t  PPFC;                              /*!< Pre-programmed factory code present.                                  */
-  __I  uint32_t  RESERVED2;
-  __I  uint32_t  NUMRAMBLOCK;                       /*!< Number of individualy controllable RAM blocks.                        */
-  
-  union {
-    __I  uint32_t  SIZERAMBLOCK[4];                 /*!< Deprecated array of size of RAM block in bytes. This name is
-                                                         kept for backward compatinility purposes. Use SIZERAMBLOCKS
-                                                          instead.                                                             */
-    __I  uint32_t  SIZERAMBLOCKS;                   /*!< Size of RAM blocks in bytes.                                          */
-  };
-  __I  uint32_t  RESERVED3[5];
-  __I  uint32_t  CONFIGID;                          /*!< Configuration identifier.                                             */
-  __I  uint32_t  DEVICEID[2];                       /*!< Device identifier.                                                    */
-  __I  uint32_t  RESERVED4[6];
-  __I  uint32_t  ER[4];                             /*!< Encryption root.                                                      */
-  __I  uint32_t  IR[4];                             /*!< Identity root.                                                        */
-  __I  uint32_t  DEVICEADDRTYPE;                    /*!< Device address type.                                                  */
-  __I  uint32_t  DEVICEADDR[2];                     /*!< Device address.                                                       */
-  __I  uint32_t  OVERRIDEEN;                        /*!< Radio calibration override enable.                                    */
-  __I  uint32_t  NRF_1MBIT[5];                      /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
-                                                         mode.                                                                 */
-  __I  uint32_t  RESERVED5[10];
-  __I  uint32_t  BLE_1MBIT[5];                      /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
-                                                         mode.                                                                 */
-  FICR_INFO_Type INFO;                              /*!< Device info                                                           */
-} NRF_FICR_Type;
-
-
-/* ================================================================================ */
-/* ================                      UICR                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief User Information Configuration. (UICR)
-  */
-
-typedef struct {                                    /*!< UICR Structure                                                        */
-  __IO uint32_t  CLENR0;                            /*!< Length of code region 0.                                              */
-  __IO uint32_t  RBPCONF;                           /*!< Readback protection configuration.                                    */
-  __IO uint32_t  XTALFREQ;                          /*!< Reset value for CLOCK XTALFREQ register.                              */
-  __I  uint32_t  RESERVED0;
-  __I  uint32_t  FWID;                              /*!< Firmware ID.                                                          */
-  __IO uint32_t  BOOTLOADERADDR;                    /*!< Bootloader start address.                                             */
-} NRF_UICR_Type;
-
-
-/* ================================================================================ */
-/* ================                      GPIO                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief General purpose input and output. (GPIO)
-  */
-
-typedef struct {                                    /*!< GPIO Structure                                                        */
-  __I  uint32_t  RESERVED0[321];
-  __IO uint32_t  OUT;                               /*!< Write GPIO port.                                                      */
-  __IO uint32_t  OUTSET;                            /*!< Set individual bits in GPIO port.                                     */
-  __IO uint32_t  OUTCLR;                            /*!< Clear individual bits in GPIO port.                                   */
-  __I  uint32_t  IN;                                /*!< Read GPIO port.                                                       */
-  __IO uint32_t  DIR;                               /*!< Direction of GPIO pins.                                               */
-  __IO uint32_t  DIRSET;                            /*!< DIR set register.                                                     */
-  __IO uint32_t  DIRCLR;                            /*!< DIR clear register.                                                   */
-  __I  uint32_t  RESERVED1[120];
-  __IO uint32_t  PIN_CNF[32];                       /*!< Configuration of GPIO pins.                                           */
-} NRF_GPIO_Type;
-
-
-/* --------------------  End of section using anonymous unions  ------------------- */
-#if defined(__CC_ARM)
-  #pragma pop
-#elif defined(__ICCARM__)
-  /* leave anonymous unions enabled */
-#elif defined(__GNUC__)
-  /* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
-  /* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
-  #pragma warning restore
-#else
-  #warning Not supported compiler type
-#endif
-
-
-
-
-/* ================================================================================ */
-/* ================              Peripheral memory map             ================ */
-/* ================================================================================ */
-
-#define NRF_POWER_BASE                  0x40000000UL
-#define NRF_CLOCK_BASE                  0x40000000UL
-#define NRF_MPU_BASE                    0x40000000UL
-#define NRF_PU_BASE                     0x40000000UL
-#define NRF_AMLI_BASE                   0x40000000UL
-#define NRF_RADIO_BASE                  0x40001000UL
-#define NRF_UART0_BASE                  0x40002000UL
-#define NRF_SPI0_BASE                   0x40003000UL
-#define NRF_TWI0_BASE                   0x40003000UL
-#define NRF_SPI1_BASE                   0x40004000UL
-#define NRF_TWI1_BASE                   0x40004000UL
-#define NRF_SPIS1_BASE                  0x40004000UL
-#define NRF_SPIM1_BASE                  0x40004000UL
-#define NRF_GPIOTE_BASE                 0x40006000UL
-#define NRF_ADC_BASE                    0x40007000UL
-#define NRF_TIMER0_BASE                 0x40008000UL
-#define NRF_TIMER1_BASE                 0x40009000UL
-#define NRF_TIMER2_BASE                 0x4000A000UL
-#define NRF_RTC0_BASE                   0x4000B000UL
-#define NRF_TEMP_BASE                   0x4000C000UL
-#define NRF_RNG_BASE                    0x4000D000UL
-#define NRF_ECB_BASE                    0x4000E000UL
-#define NRF_AAR_BASE                    0x4000F000UL
-#define NRF_CCM_BASE                    0x4000F000UL
-#define NRF_WDT_BASE                    0x40010000UL
-#define NRF_RTC1_BASE                   0x40011000UL
-#define NRF_QDEC_BASE                   0x40012000UL
-#define NRF_LPCOMP_BASE                 0x40013000UL
-#define NRF_SWI_BASE                    0x40014000UL
-#define NRF_NVMC_BASE                   0x4001E000UL
-#define NRF_PPI_BASE                    0x4001F000UL
-#define NRF_FICR_BASE                   0x10000000UL
-#define NRF_UICR_BASE                   0x10001000UL
-#define NRF_GPIO_BASE                   0x50000000UL
-
-
-/* ================================================================================ */
-/* ================             Peripheral declaration             ================ */
-/* ================================================================================ */
-
-#define NRF_POWER                       ((NRF_POWER_Type          *) NRF_POWER_BASE)
-#define NRF_CLOCK                       ((NRF_CLOCK_Type          *) NRF_CLOCK_BASE)
-#define NRF_MPU                         ((NRF_MPU_Type            *) NRF_MPU_BASE)
-#define NRF_PU                          ((NRF_PU_Type             *) NRF_PU_BASE)
-#define NRF_AMLI                        ((NRF_AMLI_Type           *) NRF_AMLI_BASE)
-#define NRF_RADIO                       ((NRF_RADIO_Type          *) NRF_RADIO_BASE)
-#define NRF_UART0                       ((NRF_UART_Type           *) NRF_UART0_BASE)
-#define NRF_SPI0                        ((NRF_SPI_Type            *) NRF_SPI0_BASE)
-#define NRF_TWI0                        ((NRF_TWI_Type            *) NRF_TWI0_BASE)
-#define NRF_SPI1                        ((NRF_SPI_Type            *) NRF_SPI1_BASE)
-#define NRF_TWI1                        ((NRF_TWI_Type            *) NRF_TWI1_BASE)
-#define NRF_SPIS1                       ((NRF_SPIS_Type           *) NRF_SPIS1_BASE)
-#define NRF_SPIM1                       ((NRF_SPIM_Type           *) NRF_SPIM1_BASE)
-#define NRF_GPIOTE                      ((NRF_GPIOTE_Type         *) NRF_GPIOTE_BASE)
-#define NRF_ADC                         ((NRF_ADC_Type            *) NRF_ADC_BASE)
-#define NRF_TIMER0                      ((NRF_TIMER_Type          *) NRF_TIMER0_BASE)
-#define NRF_TIMER1                      ((NRF_TIMER_Type          *) NRF_TIMER1_BASE)
-#define NRF_TIMER2                      ((NRF_TIMER_Type          *) NRF_TIMER2_BASE)
-#define NRF_RTC0                        ((NRF_RTC_Type            *) NRF_RTC0_BASE)
-#define NRF_TEMP                        ((NRF_TEMP_Type           *) NRF_TEMP_BASE)
-#define NRF_RNG                         ((NRF_RNG_Type            *) NRF_RNG_BASE)
-#define NRF_ECB                         ((NRF_ECB_Type            *) NRF_ECB_BASE)
-#define NRF_AAR                         ((NRF_AAR_Type            *) NRF_AAR_BASE)
-#define NRF_CCM                         ((NRF_CCM_Type            *) NRF_CCM_BASE)
-#define NRF_WDT                         ((NRF_WDT_Type            *) NRF_WDT_BASE)
-#define NRF_RTC1                        ((NRF_RTC_Type            *) NRF_RTC1_BASE)
-#define NRF_QDEC                        ((NRF_QDEC_Type           *) NRF_QDEC_BASE)
-#define NRF_LPCOMP                      ((NRF_LPCOMP_Type         *) NRF_LPCOMP_BASE)
-#define NRF_SWI                         ((NRF_SWI_Type            *) NRF_SWI_BASE)
-#define NRF_NVMC                        ((NRF_NVMC_Type           *) NRF_NVMC_BASE)
-#define NRF_PPI                         ((NRF_PPI_Type            *) NRF_PPI_BASE)
-#define NRF_FICR                        ((NRF_FICR_Type           *) NRF_FICR_BASE)
-#define NRF_UICR                        ((NRF_UICR_Type           *) NRF_UICR_BASE)
-#define NRF_GPIO                        ((NRF_GPIO_Type           *) NRF_GPIO_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group nRF51 */
-/** @} */ /* End of group Nordic Semiconductor */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif  /* nRF51_H */
-
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf51_bitfields.h
--- a/nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf51_bitfields.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,7135 +0,0 @@
-/* Copyright (c) 2013, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright notice, this
- *     list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright notice,
- *     this list of conditions and the following disclaimer in the documentation
- *     and/or other materials provided with the distribution.
- *
- *   * Neither the name of Nordic Semiconductor ASA nor the names of its
- *     contributors may be used to endorse or promote products derived from
- *     this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-#ifndef __NRF51_BITS_H
-#define __NRF51_BITS_H
-
-/*lint ++flb "Enter library region */
-
-#include <core_cm0.h>
-
-/* Peripheral: AAR */
-/* Description: Accelerated Address Resolver. */
-
-/* Register: AAR_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
-#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
-#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
-#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on RESOLVED event. */
-#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
-#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
-#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on END event. */
-#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
-#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: AAR_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
-#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
-#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
-#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on RESOLVED event. */
-#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
-#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
-#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on ENDKSGEN event. */
-#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
-#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: AAR_STATUS */
-/* Description: Resolution status. */
-
-/* Bits 3..0 : The IRK used last time an address was resolved. */
-#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
-#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
-
-/* Register: AAR_ENABLE */
-/* Description: Enable AAR. */
-
-/* Bits 1..0 : Enable AAR. */
-#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
-#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
-
-/* Register: AAR_NIRK */
-/* Description: Number of Identity root Keys in the IRK data structure. */
-
-/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
-#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
-#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
-
-/* Register: AAR_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: ADC */
-/* Description: Analog to digital converter. */
-
-/* Register: ADC_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 0 : Enable interrupt on END event. */
-#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
-#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: ADC_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 0 : Disable interrupt on END event. */
-#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
-#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: ADC_BUSY */
-/* Description: ADC busy register. */
-
-/* Bit 0 : ADC busy register. */
-#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
-#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
-#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
-#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
-
-/* Register: ADC_ENABLE */
-/* Description: ADC enable. */
-
-/* Bits 1..0 : ADC enable. */
-#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
-#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
-
-/* Register: ADC_CONFIG */
-/* Description: ADC configuration register. */
-
-/* Bits 17..16 : ADC external reference pin selection. */
-#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
-#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
-#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
-#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
-#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
-
-/* Bits 15..8 : ADC analog pin selection. */
-#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
-#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
-#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
-#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
-
-/* Bits 6..5 : ADC reference selection. */
-#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
-#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
-#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
-#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
-#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
-#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
-
-/* Bits 4..2 : ADC input selection. */
-#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
-#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
-#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
-#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
-#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
-#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
-#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
-
-/* Bits 1..0 : ADC resolution. */
-#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
-#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
-#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
-#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
-#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
-
-/* Register: ADC_RESULT */
-/* Description: Result of ADC conversion. */
-
-/* Bits 9..0 : Result of ADC conversion. */
-#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
-#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
-
-/* Register: ADC_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: AMLI */
-/* Description: AHB Multi-Layer Interface. */
-
-/* Register: AMLI_RAMPRI_CPU0 */
-/* Description: Configurable priority configuration register for CPU0. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_SPIS1 */
-/* Description: Configurable priority configuration register for SPIS1. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_RADIO */
-/* Description: Configurable priority configuration register for RADIO. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_ECB */
-/* Description: Configurable priority configuration register for ECB. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_CCM */
-/* Description: Configurable priority configuration register for CCM. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_AAR */
-/* Description: Configurable priority configuration register for AAR. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Peripheral: CCM */
-/* Description: AES CCM Mode Encryption. */
-
-/* Register: CCM_SHORTS */
-/* Description: Shortcuts for the CCM. */
-
-/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: CCM_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on ERROR event. */
-#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
-#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on ENDCRYPT event. */
-#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
-#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
-#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on ENDKSGEN event. */
-#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
-#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
-#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: CCM_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on ERROR event. */
-#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
-#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on ENDCRYPT event. */
-#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
-#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
-#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on ENDKSGEN event. */
-#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
-#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
-#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: CCM_MICSTATUS */
-/* Description: CCM RX MIC check result. */
-
-/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
-#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
-#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
-#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
-#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
-
-/* Register: CCM_ENABLE */
-/* Description: CCM enable. */
-
-/* Bits 1..0 : CCM enable. */
-#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
-#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
-
-/* Register: CCM_MODE */
-/* Description: Operation mode. */
-
-/* Bit 0 : CCM mode operation. */
-#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
-#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
-#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
-#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
-
-/* Register: CCM_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: CLOCK */
-/* Description: Clock control. */
-
-/* Register: CLOCK_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 4 : Enable interrupt on CTTO event. */
-#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
-#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
-#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 3 : Enable interrupt on DONE event. */
-#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
-#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
-#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: CLOCK_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 4 : Disable interrupt on CTTO event. */
-#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
-#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
-#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 3 : Disable interrupt on DONE event. */
-#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
-#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
-#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: CLOCK_HFCLKRUN */
-/* Description: Task HFCLKSTART trigger status. */
-
-/* Bit 0 : Task HFCLKSTART trigger status. */
-#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
-#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
-#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
-#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
-
-/* Register: CLOCK_HFCLKSTAT */
-/* Description: High frequency clock status. */
-
-/* Bit 16 : State for the HFCLK. */
-#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
-#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
-#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
-#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
-
-/* Bit 0 : Active clock source for the HF clock. */
-#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
-#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
-
-/* Register: CLOCK_LFCLKRUN */
-/* Description: Task LFCLKSTART triggered status. */
-
-/* Bit 0 : Task LFCLKSTART triggered status. */
-#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
-#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
-#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
-#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
-
-/* Register: CLOCK_LFCLKSTAT */
-/* Description: Low frequency clock status. */
-
-/* Bit 16 : State for the LF clock. */
-#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
-#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
-#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
-#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
-
-/* Bits 1..0 : Active clock source for the LF clock. */
-#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
-#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
-#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
-
-/* Register: CLOCK_LFCLKSRCCOPY */
-/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
-
-/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
-#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
-#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
-#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
-
-/* Register: CLOCK_LFCLKSRC */
-/* Description: Clock source for the LFCLK clock. */
-
-/* Bits 1..0 : Clock source. */
-#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
-#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
-#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
-
-/* Register: CLOCK_CTIV */
-/* Description: Calibration timer interval. */
-
-/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
-#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
-#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
-
-/* Register: CLOCK_XTALFREQ */
-/* Description: Crystal frequency. */
-
-/* Bits 7..0 : External Xtal frequency selection. */
-#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
-#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
-#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
-#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
-
-
-/* Peripheral: ECB */
-/* Description: AES ECB Mode Encryption. */
-
-/* Register: ECB_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 1 : Enable interrupt on ERRORECB event. */
-#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
-#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
-#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
-#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
-#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on ENDECB event. */
-#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
-#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
-#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
-#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
-#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: ECB_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 1 : Disable interrupt on ERRORECB event. */
-#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
-#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
-#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
-#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
-#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on ENDECB event. */
-#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
-#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
-#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
-#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
-#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: ECB_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: FICR */
-/* Description: Factory Information Configuration. */
-
-/* Register: FICR_PPFC */
-/* Description: Pre-programmed factory code present. */
-
-/* Bits 7..0 : Pre-programmed factory code present. */
-#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
-#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
-#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
-#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
-
-/* Register: FICR_CONFIGID */
-/* Description: Configuration identifier. */
-
-/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
-#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
-#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
-
-/* Bits 15..0 : Hardware Identification Number. */
-#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
-#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
-
-/* Register: FICR_DEVICEADDRTYPE */
-/* Description: Device address type. */
-
-/* Bit 0 : Device address type. */
-#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
-#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
-#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
-#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
-
-/* Register: FICR_OVERRIDEEN */
-/* Description: Radio calibration override enable. */
-
-/* Bit 3 : Override default values for BLE_1Mbit mode. */
-#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
-#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
-#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
-#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
-
-/* Bit 0 : Override default values for NRF_1Mbit mode. */
-#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
-#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
-#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
-#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
-
-/* Register: FICR_INFO_PART */
-/* Description: Part code */
-
-/* Bits 31..0 : Part code */
-#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
-#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
-#define FICR_INFO_PART_PART_N51822 (0x51822UL) /*!< nRF51822 */
-#define FICR_INFO_PART_PART_N51422 (0x51422UL) /*!< nRF51422 */
-#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
-
-/* Register: FICR_INFO_VARIANT */
-/* Description: Part variant */
-
-/* Bits 31..0 : Part variant */
-#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
-#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
-#define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /*!< nRF51-C (XLR3) */
-#define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /*!< nRF51-D (L3) */
-#define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /*!< nRF51-E (XLR3P) */
-#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
-
-/* Register: FICR_INFO_PACKAGE */
-/* Description: Package option */
-
-/* Bits 31..0 : Package option */
-#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
-#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
-#define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /*!< 48-pin QFN with 31 GPIO */
-#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /*!< nRF51x22 CDxx - WLCSP 56 balls */
-#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /*!< nRF51x22 CExx - WLCSP 62 balls */
-#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /*!< nRF51x22 CFxx - WLCSP 62 balls */
-#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /*!< nRF51x22 CTxx - WLCSP 62 balls */
-#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
-
-/* Register: FICR_INFO_RAM */
-/* Description: RAM variant */
-
-/* Bits 31..0 : RAM variant */
-#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
-#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
-#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
-#define FICR_INFO_RAM_RAM_K16 (16UL) /*!< 16 kByte RAM. */
-#define FICR_INFO_RAM_RAM_K32 (32UL) /*!< 32 kByte RAM. */
-
-/* Register: FICR_INFO_FLASH */
-/* Description: Flash variant */
-
-/* Bits 31..0 : Flash variant */
-#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
-#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
-#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
-#define FICR_INFO_FLASH_FLASH_K128 (128UL) /*!< 128 kByte FLASH. */
-#define FICR_INFO_FLASH_FLASH_K256 (256UL) /*!< 256 kByte FLASH. */
-
-
-/* Peripheral: GPIO */
-/* Description: General purpose input and output. */
-
-/* Register: GPIO_OUT */
-/* Description: Write GPIO port. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
-
-/* Register: GPIO_OUTSET */
-/* Description: Set individual bits in GPIO port. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
-
-/* Register: GPIO_OUTCLR */
-/* Description: Clear individual bits in GPIO port. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
-
-/* Register: GPIO_IN */
-/* Description: Read GPIO port. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
-
-/* Register: GPIO_DIR */
-/* Description: Direction of GPIO pins. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
-
-/* Register: GPIO_DIRSET */
-/* Description: DIR set register. */
-
-/* Bit 31 : Set as output pin 31. */
-#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 30 : Set as output pin 30. */
-#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 29 : Set as output pin 29. */
-#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 28 : Set as output pin 28. */
-#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 27 : Set as output pin 27. */
-#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 26 : Set as output pin 26. */
-#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 25 : Set as output pin 25. */
-#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 24 : Set as output pin 24. */
-#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 23 : Set as output pin 23. */
-#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 22 : Set as output pin 22. */
-#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 21 : Set as output pin 21. */
-#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 20 : Set as output pin 20. */
-#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 19 : Set as output pin 19. */
-#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 18 : Set as output pin 18. */
-#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 17 : Set as output pin 17. */
-#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 16 : Set as output pin 16. */
-#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 15 : Set as output pin 15. */
-#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 14 : Set as output pin 14. */
-#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 13 : Set as output pin 13. */
-#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 12 : Set as output pin 12. */
-#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 11 : Set as output pin 11. */
-#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 10 : Set as output pin 10. */
-#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 9 : Set as output pin 9. */
-#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 8 : Set as output pin 8. */
-#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 7 : Set as output pin 7. */
-#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 6 : Set as output pin 6. */
-#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 5 : Set as output pin 5. */
-#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 4 : Set as output pin 4. */
-#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 3 : Set as output pin 3. */
-#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 2 : Set as output pin 2. */
-#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 1 : Set as output pin 1. */
-#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 0 : Set as output pin 0. */
-#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
-
-/* Register: GPIO_DIRCLR */
-/* Description: DIR clear register. */
-
-/* Bit 31 : Set as input pin 31. */
-#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 30 : Set as input pin 30. */
-#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 29 : Set as input pin 29. */
-#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 28 : Set as input pin 28. */
-#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 27 : Set as input pin 27. */
-#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 26 : Set as input pin 26. */
-#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 25 : Set as input pin 25. */
-#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 24 : Set as input pin 24. */
-#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 23 : Set as input pin 23. */
-#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 22 : Set as input pin 22. */
-#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 21 : Set as input pin 21. */
-#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 20 : Set as input pin 20. */
-#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 19 : Set as input pin 19. */
-#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 18 : Set as input pin 18. */
-#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 17 : Set as input pin 17. */
-#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 16 : Set as input pin 16. */
-#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 15 : Set as input pin 15. */
-#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 14 : Set as input pin 14. */
-#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 13 : Set as input pin 13. */
-#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 12 : Set as input pin 12. */
-#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 11 : Set as input pin 11. */
-#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 10 : Set as input pin 10. */
-#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 9 : Set as input pin 9. */
-#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 8 : Set as input pin 8. */
-#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 7 : Set as input pin 7. */
-#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 6 : Set as input pin 6. */
-#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 5 : Set as input pin 5. */
-#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 4 : Set as input pin 4. */
-#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 3 : Set as input pin 3. */
-#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 2 : Set as input pin 2. */
-#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 1 : Set as input pin 1. */
-#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 0 : Set as input pin 0. */
-#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
-
-/* Register: GPIO_PIN_CNF */
-/* Description: Configuration of GPIO pins. */
-
-/* Bits 17..16 : Pin sensing mechanism. */
-#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
-#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
-#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
-#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
-#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
-
-/* Bits 10..8 : Drive configuration. */
-#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
-#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
-#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
-#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
-#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
-#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
-#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
-#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
-#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
-#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
-
-/* Bits 3..2 : Pull-up or -down configuration. */
-#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
-#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
-#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
-#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
-#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
-
-/* Bit 1 : Connect or disconnect input path. */
-#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
-#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
-#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
-#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
-
-/* Bit 0 : Pin direction. */
-#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
-#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
-#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
-#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
-
-
-/* Peripheral: GPIOTE */
-/* Description: GPIO tasks and events. */
-
-/* Register: GPIOTE_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 31 : Enable interrupt on PORT event. */
-#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
-#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
-#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 3 : Enable interrupt on IN[3] event. */
-#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
-#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
-#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on IN[2] event. */
-#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
-#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
-#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on IN[1] event. */
-#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
-#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
-#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on IN[0] event. */
-#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
-#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
-#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: GPIOTE_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 31 : Disable interrupt on PORT event. */
-#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
-#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
-#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 3 : Disable interrupt on IN[3] event. */
-#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
-#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
-#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on IN[2] event. */
-#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
-#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
-#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on IN[1] event. */
-#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
-#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
-#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on IN[0] event. */
-#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
-#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
-#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: GPIOTE_CONFIG */
-/* Description: Channel configuration registers. */
-
-/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
-#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
-#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
-#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
-#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
-
-/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
-#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
-#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
-#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
-#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
-#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
-
-/* Bits 12..8 : Pin select. */
-#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
-#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
-
-/* Bits 1..0 : Mode */
-#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
-#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
-#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
-#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
-#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
-
-/* Register: GPIOTE_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: LPCOMP */
-/* Description: Low power comparator. */
-
-/* Register: LPCOMP_SHORTS */
-/* Description: Shortcuts for the LPCOMP. */
-
-/* Bit 4 : Shortcut between CROSS event and STOP task. */
-#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
-#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
-#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 3 : Shortcut between UP event and STOP task. */
-#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
-#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
-#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 2 : Shortcut between DOWN event and STOP task. */
-#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
-#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
-#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 1 : Shortcut between RADY event and STOP task. */
-#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
-#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
-#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between READY event and SAMPLE task. */
-#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
-#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
-#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: LPCOMP_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 3 : Enable interrupt on CROSS event. */
-#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
-#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
-#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on UP event. */
-#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
-#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
-#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on DOWN event. */
-#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
-#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
-#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on READY event. */
-#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
-#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
-#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: LPCOMP_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 3 : Disable interrupt on CROSS event. */
-#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
-#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
-#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on UP event. */
-#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
-#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
-#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on DOWN event. */
-#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
-#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
-#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on READY event. */
-#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
-#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
-#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: LPCOMP_RESULT */
-/* Description: Result of last compare. */
-
-/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
-#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
-#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
-#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
-#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
-
-/* Register: LPCOMP_ENABLE */
-/* Description: Enable the LPCOMP. */
-
-/* Bits 1..0 : Enable or disable LPCOMP. */
-#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
-#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
-
-/* Register: LPCOMP_PSEL */
-/* Description: Input pin select. */
-
-/* Bits 2..0 : Analog input pin select. */
-#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
-#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
-#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
-
-/* Register: LPCOMP_REFSEL */
-/* Description: Reference select. */
-
-/* Bits 2..0 : Reference select. */
-#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
-#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
-#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
-
-/* Register: LPCOMP_EXTREFSEL */
-/* Description: External reference select. */
-
-/* Bit 0 : External analog reference pin selection. */
-#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
-#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
-#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
-#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
-
-/* Register: LPCOMP_ANADETECT */
-/* Description: Analog detect configuration. */
-
-/* Bits 1..0 : Analog detect configuration. */
-#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
-#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
-#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
-#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
-#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
-
-/* Register: LPCOMP_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: MPU */
-/* Description: Memory Protection Unit. */
-
-/* Register: MPU_PERR0 */
-/* Description: Configuration of peripherals in mpu regions. */
-
-/* Bit 31 : PPI region configuration. */
-#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
-#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
-#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 30 : NVMC region configuration. */
-#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
-#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
-#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 19 : LPCOMP region configuration. */
-#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
-#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
-#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 18 : QDEC region configuration. */
-#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
-#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
-#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 17 : RTC1 region configuration. */
-#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
-#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
-#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 16 : WDT region configuration. */
-#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
-#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
-#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 15 : CCM and AAR region configuration. */
-#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
-#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
-#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 14 : ECB region configuration. */
-#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
-#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
-#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 13 : RNG region configuration. */
-#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
-#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
-#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 12 : TEMP region configuration. */
-#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
-#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
-#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 11 : RTC0 region configuration. */
-#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
-#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
-#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 10 : TIMER2 region configuration. */
-#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
-#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
-#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 9 : TIMER1 region configuration. */
-#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
-#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
-#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 8 : TIMER0 region configuration. */
-#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
-#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
-#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 7 : ADC region configuration. */
-#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
-#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
-#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 6 : GPIOTE region configuration. */
-#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
-#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
-#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 4 : SPI1 and TWI1 region configuration. */
-#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
-#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
-#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 3 : SPI0 and TWI0 region configuration. */
-#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
-#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
-#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 2 : UART0 region configuration. */
-#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
-#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
-#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 1 : RADIO region configuration. */
-#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
-#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
-#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 0 : POWER_CLOCK region configuration. */
-#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
-#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
-#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Register: MPU_PROTENSET0 */
-/* Description: Erase and write protection bit enable set register. */
-
-/* Bit 31 : Protection enable for region 31. */
-#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
-#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
-#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 30 : Protection enable for region 30. */
-#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
-#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
-#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 29 : Protection enable for region 29. */
-#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
-#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
-#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 28 : Protection enable for region 28. */
-#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
-#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
-#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 27 : Protection enable for region 27. */
-#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
-#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
-#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 26 : Protection enable for region 26. */
-#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
-#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
-#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 25 : Protection enable for region 25. */
-#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
-#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
-#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 24 : Protection enable for region 24. */
-#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
-#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
-#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 23 : Protection enable for region 23. */
-#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
-#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
-#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 22 : Protection enable for region 22. */
-#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
-#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
-#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 21 : Protection enable for region 21. */
-#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
-#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
-#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 20 : Protection enable for region 20. */
-#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
-#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
-#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 19 : Protection enable for region 19. */
-#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
-#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
-#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 18 : Protection enable for region 18. */
-#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
-#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
-#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 17 : Protection enable for region 17. */
-#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
-#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
-#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 16 : Protection enable for region 16. */
-#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
-#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
-#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 15 : Protection enable for region 15. */
-#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
-#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
-#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 14 : Protection enable for region 14. */
-#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
-#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
-#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 13 : Protection enable for region 13. */
-#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
-#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
-#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 12 : Protection enable for region 12. */
-#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
-#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
-#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 11 : Protection enable for region 11. */
-#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
-#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
-#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 10 : Protection enable for region 10. */
-#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
-#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
-#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 9 : Protection enable for region 9. */
-#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
-#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
-#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 8 : Protection enable for region 8. */
-#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
-#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
-#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 7 : Protection enable for region 7. */
-#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
-#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
-#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 6 : Protection enable for region 6. */
-#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
-#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
-#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 5 : Protection enable for region 5. */
-#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
-#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
-#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 4 : Protection enable for region 4. */
-#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
-#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
-#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 3 : Protection enable for region 3. */
-#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
-#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
-#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 2 : Protection enable for region 2. */
-#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
-#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
-#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 1 : Protection enable for region 1. */
-#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
-#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
-#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 0 : Protection enable for region 0. */
-#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
-#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
-#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
-
-/* Register: MPU_PROTENSET1 */
-/* Description: Erase and write protection bit enable set register. */
-
-/* Bit 31 : Protection enable for region 63. */
-#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
-#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
-#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 30 : Protection enable for region 62. */
-#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
-#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
-#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 29 : Protection enable for region 61. */
-#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
-#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
-#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 28 : Protection enable for region 60. */
-#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
-#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
-#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 27 : Protection enable for region 59. */
-#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
-#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
-#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 26 : Protection enable for region 58. */
-#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
-#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
-#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 25 : Protection enable for region 57. */
-#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
-#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
-#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 24 : Protection enable for region 56. */
-#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
-#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
-#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 23 : Protection enable for region 55. */
-#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
-#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
-#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 22 : Protection enable for region 54. */
-#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
-#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
-#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 21 : Protection enable for region 53. */
-#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
-#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
-#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 20 : Protection enable for region 52. */
-#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
-#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
-#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 19 : Protection enable for region 51. */
-#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
-#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
-#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 18 : Protection enable for region 50. */
-#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
-#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
-#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 17 : Protection enable for region 49. */
-#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
-#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
-#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 16 : Protection enable for region 48. */
-#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
-#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
-#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 15 : Protection enable for region 47. */
-#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
-#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
-#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 14 : Protection enable for region 46. */
-#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
-#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
-#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 13 : Protection enable for region 45. */
-#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
-#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
-#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 12 : Protection enable for region 44. */
-#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
-#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
-#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 11 : Protection enable for region 43. */
-#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
-#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
-#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 10 : Protection enable for region 42. */
-#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
-#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
-#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 9 : Protection enable for region 41. */
-#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
-#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
-#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 8 : Protection enable for region 40. */
-#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
-#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
-#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 7 : Protection enable for region 39. */
-#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
-#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
-#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 6 : Protection enable for region 38. */
-#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
-#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
-#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 5 : Protection enable for region 37. */
-#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
-#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
-#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 4 : Protection enable for region 36. */
-#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
-#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
-#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 3 : Protection enable for region 35. */
-#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
-#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
-#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 2 : Protection enable for region 34. */
-#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
-#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
-#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 1 : Protection enable for region 33. */
-#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
-#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
-#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 0 : Protection enable for region 32. */
-#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
-#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
-#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
-
-/* Register: MPU_DISABLEINDEBUG */
-/* Description: Disable erase and write protection mechanism in debug mode. */
-
-/* Bit 0 : Disable protection mechanism in debug mode. */
-#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
-#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
-#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
-#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
-
-/* Register: MPU_PROTBLOCKSIZE */
-/* Description: Erase and write protection block size. */
-
-/* Bits 1..0 : Erase and write protection block size. */
-#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */
-#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */
-#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */
-
-
-/* Peripheral: NVMC */
-/* Description: Non Volatile Memory Controller. */
-
-/* Register: NVMC_READY */
-/* Description: Ready flag. */
-
-/* Bit 0 : NVMC ready. */
-#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
-#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
-#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
-#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
-
-/* Register: NVMC_CONFIG */
-/* Description: Configuration register. */
-
-/* Bits 1..0 : Program write enable. */
-#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
-#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
-#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
-#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
-#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
-
-/* Register: NVMC_ERASEALL */
-/* Description: Register for erasing all non-volatile user memory. */
-
-/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
-#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
-#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
-#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
-#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
-
-/* Register: NVMC_ERASEUICR */
-/* Description: Register for start erasing User Information Congfiguration Registers. */
-
-/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
-#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
-#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
-#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
-#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
-
-
-/* Peripheral: POWER */
-/* Description: Power Control. */
-
-/* Register: POWER_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on POFWARN event. */
-#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
-#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
-#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
-#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
-#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: POWER_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on POFWARN event. */
-#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
-#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
-#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
-#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
-#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: POWER_RESETREAS */
-/* Description: Reset reason. */
-
-/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
-#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
-#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
-
-/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
-#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
-#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
-
-/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
-#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
-#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
-
-/* Bit 3 : Reset from CPU lock-up detected. */
-#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
-#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
-
-/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
-#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
-#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
-
-/* Bit 1 : Reset from watchdog detected. */
-#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
-#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
-
-/* Bit 0 : Reset from pin-reset detected. */
-#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
-#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
-
-/* Register: POWER_RAMSTATUS */
-/* Description: Ram status register. */
-
-/* Bit 3 : RAM block 3 status. */
-#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
-#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
-#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */
-#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
-
-/* Bit 2 : RAM block 2 status. */
-#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
-#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
-#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
-#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
-
-/* Bit 1 : RAM block 1 status. */
-#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
-#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
-#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */
-#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
-
-/* Bit 0 : RAM block 0 status. */
-#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
-#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
-#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */
-#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
-
-/* Register: POWER_SYSTEMOFF */
-/* Description: System off register. */
-
-/* Bit 0 : Enter system off mode. */
-#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
-#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
-#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
-
-/* Register: POWER_POFCON */
-/* Description: Power failure configuration. */
-
-/* Bits 2..1 : Set threshold level. */
-#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
-#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
-#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
-#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
-#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
-#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
-
-/* Bit 0 : Power failure comparator enable. */
-#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
-#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
-#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
-#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
-
-/* Register: POWER_GPREGRET */
-/* Description: General purpose retention register. This register is a retained register. */
-
-/* Bits 7..0 : General purpose retention register. */
-#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
-#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
-
-/* Register: POWER_RAMON */
-/* Description: Ram on/off. */
-
-/* Bit 17 : RAM block 1 behaviour in OFF mode. */
-#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
-#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
-#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
-#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
-
-/* Bit 16 : RAM block 0 behaviour in OFF mode. */
-#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
-#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
-#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
-#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
-
-/* Bit 1 : RAM block 1 behaviour in ON mode. */
-#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
-#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
-#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
-#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
-
-/* Bit 0 : RAM block 0 behaviour in ON mode. */
-#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
-#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
-#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
-#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
-
-/* Register: POWER_RESET */
-/* Description: Pin reset functionality configuration register. This register is a retained register. */
-
-/* Bit 0 : Enable or disable pin reset in debug interface mode. */
-#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
-#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
-#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
-#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
-
-/* Register: POWER_RAMONB */
-/* Description: Ram on/off. */
-
-/* Bit 17 : RAM block 3 behaviour in OFF mode. */
-#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
-#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
-#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
-#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
-
-/* Bit 16 : RAM block 2 behaviour in OFF mode. */
-#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
-#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
-#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
-#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
-
-/* Bit 1 : RAM block 3 behaviour in ON mode. */
-#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
-#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
-#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
-#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
-
-/* Bit 0 : RAM block 2 behaviour in ON mode. */
-#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
-#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
-#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
-#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
-
-/* Register: POWER_DCDCEN */
-/* Description: DCDC converter enable configuration register. */
-
-/* Bit 0 : Enable DCDC converter. */
-#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
-#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
-#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
-#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
-
-/* Register: POWER_DCDCFORCE */
-/* Description: DCDC power-up force register. */
-
-/* Bit 1 : DCDC power-up force on. */
-#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */
-#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */
-#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */
-#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */
-
-/* Bit 0 : DCDC power-up force off. */
-#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
-#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
-#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */
-#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */
-
-
-/* Peripheral: PPI */
-/* Description: PPI controller. */
-
-/* Register: PPI_CHEN */
-/* Description: Channel enable. */
-
-/* Bit 31 : Enable PPI channel 31. */
-#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
-#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
-#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 30 : Enable PPI channel 30. */
-#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
-#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
-#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 29 : Enable PPI channel 29. */
-#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
-#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
-#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 28 : Enable PPI channel 28. */
-#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
-#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
-#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 27 : Enable PPI channel 27. */
-#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
-#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
-#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 26 : Enable PPI channel 26. */
-#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
-#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
-#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 25 : Enable PPI channel 25. */
-#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
-#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
-#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 24 : Enable PPI channel 24. */
-#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
-#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
-#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 23 : Enable PPI channel 23. */
-#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
-#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
-#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 22 : Enable PPI channel 22. */
-#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
-#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
-#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 21 : Enable PPI channel 21. */
-#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
-#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
-#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 20 : Enable PPI channel 20. */
-#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
-#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
-#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 15 : Enable PPI channel 15. */
-#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
-#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 14 : Enable PPI channel 14. */
-#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
-#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 13 : Enable PPI channel 13. */
-#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
-#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 12 : Enable PPI channel 12. */
-#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
-#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 11 : Enable PPI channel 11. */
-#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
-#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 10 : Enable PPI channel 10. */
-#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
-#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 9 : Enable PPI channel 9. */
-#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
-#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 8 : Enable PPI channel 8. */
-#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
-#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 7 : Enable PPI channel 7. */
-#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
-#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 6 : Enable PPI channel 6. */
-#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
-#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 5 : Enable PPI channel 5. */
-#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
-#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 4 : Enable PPI channel 4. */
-#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
-#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 3 : Enable PPI channel 3. */
-#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
-#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
-#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
-
-/* Bit 2 : Enable PPI channel 2. */
-#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
-#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 1 : Enable PPI channel 1. */
-#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
-#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 0 : Enable PPI channel 0. */
-#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
-#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
-
-/* Register: PPI_CHENSET */
-/* Description: Channel enable set. */
-
-/* Bit 31 : Enable PPI channel 31. */
-#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
-#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
-#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 30 : Enable PPI channel 30. */
-#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
-#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
-#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 29 : Enable PPI channel 29. */
-#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
-#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
-#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 28 : Enable PPI channel 28. */
-#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
-#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
-#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 27 : Enable PPI channel 27. */
-#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
-#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
-#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 26 : Enable PPI channel 26. */
-#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
-#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
-#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 25 : Enable PPI channel 25. */
-#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
-#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
-#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 24 : Enable PPI channel 24. */
-#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
-#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
-#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 23 : Enable PPI channel 23. */
-#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
-#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
-#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 22 : Enable PPI channel 22. */
-#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
-#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
-#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 21 : Enable PPI channel 21. */
-#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
-#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
-#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 20 : Enable PPI channel 20. */
-#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
-#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
-#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 15 : Enable PPI channel 15. */
-#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
-#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 14 : Enable PPI channel 14. */
-#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
-#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 13 : Enable PPI channel 13. */
-#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
-#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 12 : Enable PPI channel 12. */
-#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
-#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 11 : Enable PPI channel 11. */
-#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
-#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 10 : Enable PPI channel 10. */
-#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
-#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 9 : Enable PPI channel 9. */
-#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
-#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 8 : Enable PPI channel 8. */
-#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
-#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 7 : Enable PPI channel 7. */
-#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
-#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 6 : Enable PPI channel 6. */
-#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
-#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 5 : Enable PPI channel 5. */
-#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
-#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 4 : Enable PPI channel 4. */
-#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
-#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 3 : Enable PPI channel 3. */
-#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
-#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 2 : Enable PPI channel 2. */
-#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
-#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 1 : Enable PPI channel 1. */
-#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
-#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 0 : Enable PPI channel 0. */
-#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
-#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
-
-/* Register: PPI_CHENCLR */
-/* Description: Channel enable clear. */
-
-/* Bit 31 : Disable PPI channel 31. */
-#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
-#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
-#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 30 : Disable PPI channel 30. */
-#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
-#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
-#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 29 : Disable PPI channel 29. */
-#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
-#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
-#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 28 : Disable PPI channel 28. */
-#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
-#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
-#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 27 : Disable PPI channel 27. */
-#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
-#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
-#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 26 : Disable PPI channel 26. */
-#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
-#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
-#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 25 : Disable PPI channel 25. */
-#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
-#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
-#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 24 : Disable PPI channel 24. */
-#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
-#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
-#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 23 : Disable PPI channel 23. */
-#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
-#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
-#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 22 : Disable PPI channel 22. */
-#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
-#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
-#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 21 : Disable PPI channel 21. */
-#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
-#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
-#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 20 : Disable PPI channel 20. */
-#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
-#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
-#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 15 : Disable PPI channel 15. */
-#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
-#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 14 : Disable PPI channel 14. */
-#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
-#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 13 : Disable PPI channel 13. */
-#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
-#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 12 : Disable PPI channel 12. */
-#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
-#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 11 : Disable PPI channel 11. */
-#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
-#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 10 : Disable PPI channel 10. */
-#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
-#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 9 : Disable PPI channel 9. */
-#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
-#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 8 : Disable PPI channel 8. */
-#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
-#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 7 : Disable PPI channel 7. */
-#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
-#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 6 : Disable PPI channel 6. */
-#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
-#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 5 : Disable PPI channel 5. */
-#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
-#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 4 : Disable PPI channel 4. */
-#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
-#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 3 : Disable PPI channel 3. */
-#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
-#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 2 : Disable PPI channel 2. */
-#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
-#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 1 : Disable PPI channel 1. */
-#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
-#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 0 : Disable PPI channel 0. */
-#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
-#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
-
-/* Register: PPI_CHG */
-/* Description: Channel group configuration. */
-
-/* Bit 31 : Include CH31 in channel group. */
-#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
-#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
-#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
-
-/* Bit 30 : Include CH30 in channel group. */
-#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
-#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
-#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
-
-/* Bit 29 : Include CH29 in channel group. */
-#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
-#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
-#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
-
-/* Bit 28 : Include CH28 in channel group. */
-#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
-#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
-#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
-
-/* Bit 27 : Include CH27 in channel group. */
-#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
-#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
-#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
-
-/* Bit 26 : Include CH26 in channel group. */
-#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
-#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
-#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
-
-/* Bit 25 : Include CH25 in channel group. */
-#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
-#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
-#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
-
-/* Bit 24 : Include CH24 in channel group. */
-#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
-#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
-#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
-
-/* Bit 23 : Include CH23 in channel group. */
-#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
-#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
-#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
-
-/* Bit 22 : Include CH22 in channel group. */
-#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
-#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
-#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
-
-/* Bit 21 : Include CH21 in channel group. */
-#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
-#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
-#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
-
-/* Bit 20 : Include CH20 in channel group. */
-#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
-#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
-#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
-
-/* Bit 15 : Include CH15 in channel group. */
-#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
-#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
-
-/* Bit 14 : Include CH14 in channel group. */
-#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
-#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
-
-/* Bit 13 : Include CH13 in channel group. */
-#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
-#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
-
-/* Bit 12 : Include CH12 in channel group. */
-#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
-#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
-
-/* Bit 11 : Include CH11 in channel group. */
-#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
-#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
-
-/* Bit 10 : Include CH10 in channel group. */
-#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
-#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
-
-/* Bit 9 : Include CH9 in channel group. */
-#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
-#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
-
-/* Bit 8 : Include CH8 in channel group. */
-#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
-#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
-
-/* Bit 7 : Include CH7 in channel group. */
-#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
-#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
-
-/* Bit 6 : Include CH6 in channel group. */
-#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
-#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
-
-/* Bit 5 : Include CH5 in channel group. */
-#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
-#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
-
-/* Bit 4 : Include CH4 in channel group. */
-#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
-#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
-
-/* Bit 3 : Include CH3 in channel group. */
-#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
-#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
-
-/* Bit 2 : Include CH2 in channel group. */
-#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
-#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
-
-/* Bit 1 : Include CH1 in channel group. */
-#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
-#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
-
-/* Bit 0 : Include CH0 in channel group. */
-#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
-#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
-
-
-/* Peripheral: PU */
-/* Description: Patch unit. */
-
-/* Register: PU_PATCHADDR */
-/* Description: Relative address of patch instructions. */
-
-/* Bits 24..0 : Relative address of patch instructions. */
-#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
-#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
-
-/* Register: PU_PATCHEN */
-/* Description: Patch enable register. */
-
-/* Bit 7 : Patch 7 enabled. */
-#define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
-#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
-#define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 6 : Patch 6 enabled. */
-#define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
-#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
-#define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 5 : Patch 5 enabled. */
-#define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
-#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
-#define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 4 : Patch 4 enabled. */
-#define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
-#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
-#define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 3 : Patch 3 enabled. */
-#define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
-#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
-#define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 2 : Patch 2 enabled. */
-#define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
-#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
-#define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 1 : Patch 1 enabled. */
-#define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
-#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
-#define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 0 : Patch 0 enabled. */
-#define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
-#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
-#define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
-
-/* Register: PU_PATCHENSET */
-/* Description: Patch enable register. */
-
-/* Bit 7 : Patch 7 enabled. */
-#define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
-#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
-#define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 6 : Patch 6 enabled. */
-#define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
-#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
-#define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 5 : Patch 5 enabled. */
-#define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
-#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
-#define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 4 : Patch 4 enabled. */
-#define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
-#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
-#define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 3 : Patch 3 enabled. */
-#define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
-#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
-#define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 2 : Patch 2 enabled. */
-#define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
-#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
-#define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 1 : Patch 1 enabled. */
-#define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
-#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
-#define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 0 : Patch 0 enabled. */
-#define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
-#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
-#define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
-
-/* Register: PU_PATCHENCLR */
-/* Description: Patch disable register. */
-
-/* Bit 7 : Patch 7 enabled. */
-#define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
-#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
-#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 6 : Patch 6 enabled. */
-#define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
-#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
-#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 5 : Patch 5 enabled. */
-#define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
-#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
-#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 4 : Patch 4 enabled. */
-#define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
-#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
-#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 3 : Patch 3 enabled. */
-#define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
-#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
-#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 2 : Patch 2 enabled. */
-#define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
-#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
-#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 1 : Patch 1 enabled. */
-#define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
-#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
-#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 0 : Patch 0 enabled. */
-#define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
-#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
-#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
-
-
-/* Peripheral: QDEC */
-/* Description: Rotary decoder. */
-
-/* Register: QDEC_SHORTS */
-/* Description: Shortcuts for the QDEC. */
-
-/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
-#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
-#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
-#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
-#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
-#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
-#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
-#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: QDEC_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on ACCOF event. */
-#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
-#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
-#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on REPORTRDY event. */
-#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
-#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
-#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on SAMPLERDY event. */
-#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
-#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
-#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: QDEC_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on ACCOF event. */
-#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
-#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
-#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on REPORTRDY event. */
-#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
-#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
-#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on SAMPLERDY event. */
-#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
-#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
-#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: QDEC_ENABLE */
-/* Description: Enable the QDEC. */
-
-/* Bit 0 : Enable or disable QDEC. */
-#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
-#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
-
-/* Register: QDEC_LEDPOL */
-/* Description: LED output pin polarity. */
-
-/* Bit 0 : LED output pin polarity. */
-#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
-#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
-#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
-#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
-
-/* Register: QDEC_SAMPLEPER */
-/* Description: Sample period. */
-
-/* Bits 2..0 : Sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
-#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
-#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
-
-/* Register: QDEC_SAMPLE */
-/* Description: Motion sample value. */
-
-/* Bits 31..0 : Last sample taken in compliment to 2. */
-#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
-#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
-
-/* Register: QDEC_REPORTPER */
-/* Description: Number of samples to generate an EVENT_REPORTRDY. */
-
-/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
-#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
-#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
-#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
-
-/* Register: QDEC_DBFEN */
-/* Description: Enable debouncer input filters. */
-
-/* Bit 0 : Enable debounce input filters. */
-#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
-#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
-#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
-#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
-
-/* Register: QDEC_LEDPRE */
-/* Description: Time LED is switched ON before the sample. */
-
-/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
-#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
-#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
-
-/* Register: QDEC_ACCDBL */
-/* Description: Accumulated double (error) transitions register. */
-
-/* Bits 3..0 : Accumulated double (error) transitions. */
-#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
-#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
-
-/* Register: QDEC_ACCDBLREAD */
-/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
-
-/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
-#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
-#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
-
-/* Register: QDEC_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: RADIO */
-/* Description: The radio. */
-
-/* Register: RADIO_SHORTS */
-/* Description: Shortcuts for the radio. */
-
-/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
-#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
-#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
-#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
-#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
-#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
-#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 5 : Shortcut between END event and START task. */
-#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
-#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
-#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
-#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
-#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
-#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
-#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
-#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
-#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 2 : Shortcut between DISABLED event and TXEN task.  */
-#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
-#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
-#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 1 : Shortcut between END event and DISABLE task. */
-#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
-#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
-#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between READY event and START task. */
-#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
-#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
-#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: RADIO_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 10 : Enable interrupt on BCMATCH event. */
-#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
-#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
-#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 7 : Enable interrupt on RSSIEND event. */
-#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
-#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
-#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 6 : Enable interrupt on DEVMISS event. */
-#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
-#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
-#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 5 : Enable interrupt on DEVMATCH event. */
-#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
-#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
-#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 4 : Enable interrupt on DISABLED event. */
-#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
-#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
-#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 3 : Enable interrupt on END event. */
-#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
-#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on PAYLOAD event. */
-#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
-#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
-#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on ADDRESS event. */
-#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
-#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
-#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on READY event. */
-#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
-#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
-#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: RADIO_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 10 : Disable interrupt on BCMATCH event. */
-#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
-#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
-#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 7 : Disable interrupt on RSSIEND event. */
-#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
-#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
-#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 6 : Disable interrupt on DEVMISS event. */
-#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
-#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
-#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 5 : Disable interrupt on DEVMATCH event. */
-#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
-#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
-#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 4 : Disable interrupt on DISABLED event. */
-#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
-#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
-#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 3 : Disable interrupt on END event. */
-#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
-#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on PAYLOAD event. */
-#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
-#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
-#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on ADDRESS event. */
-#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
-#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
-#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on READY event. */
-#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
-#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
-#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: RADIO_CRCSTATUS */
-/* Description: CRC status of received packet. */
-
-/* Bit 0 : CRC status of received packet. */
-#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
-#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
-#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
-#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
-
-/* Register: RADIO_CD */
-/* Description: Carrier detect. */
-
-/* Bit 0 : Carrier detect. */
-#define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */
-#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */
-
-/* Register: RADIO_RXMATCH */
-/* Description: Received address. */
-
-/* Bits 2..0 : Logical address in which previous packet was received. */
-#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
-#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
-
-/* Register: RADIO_RXCRC */
-/* Description: Received CRC. */
-
-/* Bits 23..0 : CRC field of previously received packet. */
-#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
-#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
-
-/* Register: RADIO_DAI */
-/* Description: Device address match index. */
-
-/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
-#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
-#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
-
-/* Register: RADIO_FREQUENCY */
-/* Description: Frequency. */
-
-/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task.  */
-#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
-#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
-
-/* Register: RADIO_TXPOWER */
-/* Description: Output power. */
-
-/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
-#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
-#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
-#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
-#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
-
-/* Register: RADIO_MODE */
-/* Description: Data rate and modulation. */
-
-/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
-#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
-#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
-#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
-#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
-#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
-#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
-
-/* Register: RADIO_PCNF0 */
-/* Description: Packet configuration 0. */
-
-/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
-#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
-#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
-
-/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
-#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
-#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
-
-/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
-#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
-#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
-
-/* Register: RADIO_PCNF1 */
-/* Description: Packet configuration 1. */
-
-/* Bit 25 : Packet whitening enable. */
-#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
-#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
-#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
-#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
-
-/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
-#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
-#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
-#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
-#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
-
-/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
-#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
-#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
-
-/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
-#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
-#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
-
-/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
-#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
-#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
-
-/* Register: RADIO_PREFIX0 */
-/* Description: Prefixes bytes for logical addresses 0 to 3. */
-
-/* Bits 31..24 : Address prefix 3. Decision point: START task. */
-#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
-#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
-
-/* Bits 23..16 : Address prefix 2. Decision point: START task. */
-#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
-#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
-
-/* Bits 15..8 : Address prefix 1. Decision point: START task. */
-#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
-#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
-
-/* Bits 7..0 : Address prefix 0. Decision point: START task. */
-#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
-#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
-
-/* Register: RADIO_PREFIX1 */
-/* Description: Prefixes bytes for logical addresses 4 to 7. */
-
-/* Bits 31..24 : Address prefix 7. Decision point: START task. */
-#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
-#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
-
-/* Bits 23..16 : Address prefix 6. Decision point: START task. */
-#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
-#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
-
-/* Bits 15..8 : Address prefix 5. Decision point: START task. */
-#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
-#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
-
-/* Bits 7..0 : Address prefix 4. Decision point: START task. */
-#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
-#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
-
-/* Register: RADIO_TXADDRESS */
-/* Description: Transmit address select. */
-
-/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
-#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
-#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
-
-/* Register: RADIO_RXADDRESSES */
-/* Description: Receive address select. */
-
-/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
-#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
-#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
-#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
-#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
-#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
-#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
-#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
-#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
-#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
-#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
-#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
-#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
-#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
-#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
-#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
-#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
-
-/* Register: RADIO_CRCCNF */
-/* Description: CRC configuration. */
-
-/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
-#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
-#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
-#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
-#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
-
-/* Bits 1..0 : CRC length. Decision point: START task. */
-#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
-#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
-#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
-#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
-#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
-#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
-
-/* Register: RADIO_CRCPOLY */
-/* Description: CRC polynomial. */
-
-/* Bits 23..0 : CRC polynomial. Decision point: START task. */
-#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
-#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
-
-/* Register: RADIO_CRCINIT */
-/* Description: CRC initial value. */
-
-/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
-#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
-#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
-
-/* Register: RADIO_TEST */
-/* Description: Test features enable register. */
-
-/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
-#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */
-#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */
-#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
-#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
-
-/* Bit 0 : Constant carrier. Decision point: TXEN task. */
-#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */
-#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */
-#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
-#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
-
-/* Register: RADIO_TIFS */
-/* Description: Inter Frame Spacing in microseconds. */
-
-/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
-#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
-#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
-
-/* Register: RADIO_RSSISAMPLE */
-/* Description: RSSI sample. */
-
-/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
-#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
-#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
-
-/* Register: RADIO_STATE */
-/* Description: Current radio state. */
-
-/* Bits 3..0 : Current radio state. */
-#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
-#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
-#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
-#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
-#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
-#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
-#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
-#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
-#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
-#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
-#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
-
-/* Register: RADIO_DATAWHITEIV */
-/* Description: Data whitening initial value. */
-
-/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
-#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
-#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
-
-/* Register: RADIO_DAP */
-/* Description: Device address prefix. */
-
-/* Bits 15..0 : Device address prefix. */
-#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
-#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
-
-/* Register: RADIO_DACNF */
-/* Description: Device address match configuration. */
-
-/* Bit 15 : TxAdd for device address 7. */
-#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
-#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
-
-/* Bit 14 : TxAdd for device address 6. */
-#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
-#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
-
-/* Bit 13 : TxAdd for device address 5. */
-#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
-#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
-
-/* Bit 12 : TxAdd for device address 4. */
-#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
-#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
-
-/* Bit 11 : TxAdd for device address 3. */
-#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
-#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
-
-/* Bit 10 : TxAdd for device address 2. */
-#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
-#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
-
-/* Bit 9 : TxAdd for device address 1. */
-#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
-#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
-
-/* Bit 8 : TxAdd for device address 0. */
-#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
-#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
-
-/* Bit 7 : Enable or disable device address matching using device address 7. */
-#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
-#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
-#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 6 : Enable or disable device address matching using device address 6. */
-#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
-#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
-#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 5 : Enable or disable device address matching using device address 5. */
-#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
-#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
-#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 4 : Enable or disable device address matching using device address 4. */
-#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
-#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
-#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 3 : Enable or disable device address matching using device address 3. */
-#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
-#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
-#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 2 : Enable or disable device address matching using device address 2. */
-#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
-#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
-#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 1 : Enable or disable device address matching using device address 1. */
-#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
-#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
-#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 0 : Enable or disable device address matching using device address 0. */
-#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
-#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
-#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
-
-/* Register: RADIO_OVERRIDE0 */
-/* Description: Trim value override register 0. */
-
-/* Bits 31..0 : Trim value override 0. */
-#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
-#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
-
-/* Register: RADIO_OVERRIDE1 */
-/* Description: Trim value override register 1. */
-
-/* Bits 31..0 : Trim value override 1. */
-#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
-#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
-
-/* Register: RADIO_OVERRIDE2 */
-/* Description: Trim value override register 2. */
-
-/* Bits 31..0 : Trim value override 2. */
-#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
-#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
-
-/* Register: RADIO_OVERRIDE3 */
-/* Description: Trim value override register 3. */
-
-/* Bits 31..0 : Trim value override 3. */
-#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
-#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
-
-/* Register: RADIO_OVERRIDE4 */
-/* Description: Trim value override register 4. */
-
-/* Bit 31 : Enable or disable override of default trim values. */
-#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
-#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
-#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
-
-/* Bits 27..0 : Trim value override 4. */
-#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
-#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
-
-/* Register: RADIO_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: RNG */
-/* Description: Random Number Generator. */
-
-/* Register: RNG_SHORTS */
-/* Description: Shortcuts for the RNG. */
-
-/* Bit 0 : Shortcut between VALRDY event and STOP task. */
-#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
-#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
-#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: RNG_INTENSET */
-/* Description: Interrupt enable set register */
-
-/* Bit 0 : Enable interrupt on VALRDY event. */
-#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
-#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
-#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: RNG_INTENCLR */
-/* Description: Interrupt enable clear register */
-
-/* Bit 0 : Disable interrupt on VALRDY event. */
-#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
-#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
-#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: RNG_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 0 : Digital error correction enable. */
-#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
-#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
-#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
-#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
-
-/* Register: RNG_VALUE */
-/* Description: RNG random number. */
-
-/* Bits 7..0 : Generated random number. */
-#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
-#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
-
-/* Register: RNG_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: RTC */
-/* Description: Real time counter 0. */
-
-/* Register: RTC_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 19 : Enable interrupt on COMPARE[3] event. */
-#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 18 : Enable interrupt on COMPARE[2] event. */
-#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 17 : Enable interrupt on COMPARE[1] event. */
-#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 16 : Enable interrupt on COMPARE[0] event. */
-#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on OVRFLW event. */
-#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on TICK event. */
-#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: RTC_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 19 : Disable interrupt on COMPARE[3] event. */
-#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 18 : Disable interrupt on COMPARE[2] event. */
-#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 17 : Disable interrupt on COMPARE[1] event. */
-#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 16 : Disable interrupt on COMPARE[0] event. */
-#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on OVRFLW event. */
-#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on TICK event. */
-#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: RTC_EVTEN */
-/* Description: Configures event enable routing to PPI for each RTC event. */
-
-/* Bit 19 : COMPARE[3] event enable. */
-#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 18 : COMPARE[2] event enable. */
-#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 17 : COMPARE[1] event enable. */
-#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 16 : COMPARE[0] event enable. */
-#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 1 : OVRFLW event enable. */
-#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 0 : TICK event enable. */
-#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
-
-/* Register: RTC_EVTENSET */
-/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
-
-/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
-#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
-#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
-#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
-#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 1 : Enable routing to PPI of OVRFLW event. */
-#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 0 : Enable routing to PPI of TICK event. */
-#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
-
-/* Register: RTC_EVTENCLR */
-/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
-
-/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
-#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
-#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
-#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
-#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 1 : Disable routing to PPI of OVRFLW event. */
-#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 0 : Disable routing to PPI of TICK event. */
-#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
-
-/* Register: RTC_COUNTER */
-/* Description: Current COUNTER value. */
-
-/* Bits 23..0 : Counter value. */
-#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
-#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
-
-/* Register: RTC_PRESCALER */
-/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
-
-/* Bits 11..0 : RTC PRESCALER value. */
-#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
-#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
-
-/* Register: RTC_CC */
-/* Description: Capture/compare registers. */
-
-/* Bits 23..0 : Compare value. */
-#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
-#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
-
-/* Register: RTC_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: SPI */
-/* Description: SPI master 0. */
-
-/* Register: SPI_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on READY event. */
-#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
-#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
-#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: SPI_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on READY event. */
-#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
-#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
-#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: SPI_ENABLE */
-/* Description: Enable SPI. */
-
-/* Bits 2..0 : Enable or disable SPI. */
-#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
-#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
-
-/* Register: SPI_RXD */
-/* Description: RX data. */
-
-/* Bits 7..0 : RX data from last transfer. */
-#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
-#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
-
-/* Register: SPI_TXD */
-/* Description: TX data. */
-
-/* Bits 7..0 : TX data for next transfer. */
-#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
-#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
-
-/* Register: SPI_FREQUENCY */
-/* Description: SPI frequency */
-
-/* Bits 31..0 : SPI data rate. */
-#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
-#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
-#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
-#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
-#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
-#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
-#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
-#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
-#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
-
-/* Register: SPI_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 2 : Serial clock (SCK) polarity. */
-#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
-#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
-#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
-#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
-
-/* Bit 1 : Serial clock (SCK) phase. */
-#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
-#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
-#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
-#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
-
-/* Bit 0 : Bit order. */
-#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
-#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
-#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
-#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
-
-/* Register: SPI_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: SPIM */
-/* Description: SPI master with easyDMA 1. */
-
-/* Register: SPIM_SHORTS */
-/* Description: Shortcuts for SPIM. */
-
-/* Bit 17 : Shortcut between END event and START task. */
-#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
-#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
-#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
-#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: SPIM_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 19 : Enable interrupt on STARTED event. */
-#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
-#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
-#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 8 : Enable interrupt on ENDTX event. */
-#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
-#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
-#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 6 : Enable interrupt on END event. */
-#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
-#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 4 : Enable interrupt on ENDRX event. */
-#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
-#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
-#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on STOPPED event. */
-#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
-#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
-#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: SPIM_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 19 : Disable interrupt on STARTED event. */
-#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
-#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
-#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 8 : Disable interrupt on ENDTX event. */
-#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
-#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
-#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 6 : Disable interrupt on END event. */
-#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
-#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 4 : Disable interrupt on ENDRX event. */
-#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
-#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
-#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on STOPPED event. */
-#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
-#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
-#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: SPIM_ENABLE */
-/* Description: Enable SPIM. */
-
-/* Bits 3..0 : Enable or disable SPIM. */
-#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */
-#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */
-
-/* Register: SPIM_RXDDATA */
-/* Description: RXD register. */
-
-/* Bits 7..0 : RX data received. Double buffered. */
-#define SPIM_RXDDATA_RXD_Pos (0UL) /*!< Position of RXD field. */
-#define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /*!< Bit mask of RXD field. */
-
-/* Register: SPIM_TXDDATA */
-/* Description: TXD register. */
-
-/* Bits 7..0 : TX data to send. Double buffered. */
-#define SPIM_TXDDATA_TXD_Pos (0UL) /*!< Position of TXD field. */
-#define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /*!< Bit mask of TXD field. */
-
-/* Register: SPIM_FREQUENCY */
-/* Description: SPI frequency. */
-
-/* Bits 31..0 : SPI master data rate. */
-#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
-#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
-#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */
-#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
-#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */
-#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */
-#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */
-#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */
-#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */
-
-/* Register: SPIM_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 2 : Serial clock (SCK) polarity. */
-#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
-#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
-#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
-#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
-
-/* Bit 1 : Serial clock (SCK) phase. */
-#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
-#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
-#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
-#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
-
-/* Bit 0 : Bit order. */
-#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
-#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
-#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
-#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
-
-/* Register: SPIM_ORC */
-/* Description: Over-read character. */
-
-/* Bits 7..0 : Over-read character. */
-#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
-#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
-
-/* Register: SPIM_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-/* Register: SPIM_RXD_PTR */
-/* Description: Data pointer. */
-
-/* Bits 31..0 : Data pointer. */
-#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
-#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
-
-/* Register: SPIM_RXD_MAXCNT */
-/* Description: Maximum number of buffer bytes to receive. */
-
-/* Bits 7..0 : Maximum number of buffer bytes to receive. */
-#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
-#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
-
-/* Register: SPIM_RXD_AMOUNT */
-/* Description: Number of bytes received in the last transaction. */
-
-/* Bits 7..0 : Number of bytes received in the last transaction. */
-#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
-#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
-
-/* Register: SPIM_TXD_PTR */
-/* Description: Data pointer. */
-
-/* Bits 31..0 : Data pointer. */
-#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
-#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
-
-/* Register: SPIM_TXD_MAXCNT */
-/* Description: Maximum number of buffer bytes to send. */
-
-/* Bits 7..0 : Maximum number of buffer bytes to send. */
-#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
-#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
-
-/* Register: SPIM_TXD_AMOUNT */
-/* Description: Number of bytes sent in the last transaction. */
-
-/* Bits 7..0 : Number of bytes sent in the last transaction. */
-#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
-#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
-
-
-/* Peripheral: SPIS */
-/* Description: SPI slave 1. */
-
-/* Register: SPIS_SHORTS */
-/* Description: Shortcuts for SPIS. */
-
-/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
-#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
-#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
-#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
-#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: SPIS_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 10 : Enable interrupt on ACQUIRED event. */
-#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
-#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
-#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on END event. */
-#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
-#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: SPIS_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 10 : Disable interrupt on ACQUIRED event. */
-#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
-#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
-#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on END event. */
-#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
-#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: SPIS_SEMSTAT */
-/* Description: Semaphore status. */
-
-/* Bits 1..0 : Semaphore status. */
-#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
-#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
-#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
-#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
-#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
-#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
-
-/* Register: SPIS_STATUS */
-/* Description: Status from last transaction. */
-
-/* Bit 1 : RX buffer overflow detected, and prevented. */
-#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
-#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
-#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
-#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
-#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
-
-/* Bit 0 : TX buffer overread detected, and prevented. */
-#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
-#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
-#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
-#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
-#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
-
-/* Register: SPIS_ENABLE */
-/* Description: Enable SPIS. */
-
-/* Bits 2..0 : Enable or disable SPIS. */
-#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
-#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
-
-/* Register: SPIS_MAXRX */
-/* Description: Maximum number of bytes in the receive buffer. */
-
-/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
-#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
-#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
-
-/* Register: SPIS_AMOUNTRX */
-/* Description: Number of bytes received in last granted transaction. */
-
-/* Bits 7..0 : Number of bytes received in last granted transaction. */
-#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
-#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
-
-/* Register: SPIS_MAXTX */
-/* Description: Maximum number of bytes in the transmit buffer. */
-
-/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
-#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
-#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
-
-/* Register: SPIS_AMOUNTTX */
-/* Description: Number of bytes transmitted in last granted transaction. */
-
-/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
-#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
-#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
-
-/* Register: SPIS_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 2 : Serial clock (SCK) polarity. */
-#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
-#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
-#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
-#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
-
-/* Bit 1 : Serial clock (SCK) phase. */
-#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
-#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
-#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
-#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
-
-/* Bit 0 : Bit order. */
-#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
-#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
-#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
-#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
-
-/* Register: SPIS_DEF */
-/* Description: Default character. */
-
-/* Bits 7..0 : Default character. */
-#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
-#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
-
-/* Register: SPIS_ORC */
-/* Description: Over-read character. */
-
-/* Bits 7..0 : Over-read character. */
-#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
-#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
-
-/* Register: SPIS_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: TEMP */
-/* Description: Temperature Sensor. */
-
-/* Register: TEMP_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 0 : Enable interrupt on DATARDY event. */
-#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
-#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
-#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: TEMP_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 0 : Disable interrupt on DATARDY event. */
-#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
-#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
-#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: TEMP_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: TIMER */
-/* Description: Timer 0. */
-
-/* Register: TIMER_SHORTS */
-/* Description: Shortcuts for Timer. */
-
-/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
-#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
-#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
-#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
-#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
-#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
-#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
-#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
-#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
-#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
-#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
-#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
-#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
-#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
-#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
-#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
-#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
-#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
-#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
-#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
-#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
-#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
-#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
-#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
-#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: TIMER_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 19 : Enable interrupt on COMPARE[3] */
-#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 18 : Enable interrupt on COMPARE[2] */
-#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 17 : Enable interrupt on COMPARE[1] */
-#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 16 : Enable interrupt on COMPARE[0] */
-#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: TIMER_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 19 : Disable interrupt on COMPARE[3] */
-#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 18 : Disable interrupt on COMPARE[2] */
-#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 17 : Disable interrupt on COMPARE[1] */
-#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 16 : Disable interrupt on COMPARE[0] */
-#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: TIMER_MODE */
-/* Description: Timer Mode selection. */
-
-/* Bit 0 : Select Normal or Counter mode. */
-#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
-#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
-#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
-#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
-
-/* Register: TIMER_BITMODE */
-/* Description: Sets timer behaviour. */
-
-/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
-#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
-#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
-#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
-#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
-#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
-#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
-
-/* Register: TIMER_PRESCALER */
-/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
-
-/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
-#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
-#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
-
-/* Register: TIMER_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: TWI */
-/* Description: Two-wire interface master 0. */
-
-/* Register: TWI_SHORTS */
-/* Description: Shortcuts for TWI. */
-
-/* Bit 1 : Shortcut between BB event and the STOP task. */
-#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
-#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
-#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
-#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
-#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
-#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
-#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: TWI_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 18 : Enable interrupt on SUSPENDED event. */
-#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
-#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
-#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 14 : Enable interrupt on BB event. */
-#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
-#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
-#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 9 : Enable interrupt on ERROR event. */
-#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
-#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 7 : Enable interrupt on TXDSENT event. */
-#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
-#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
-#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on READY event. */
-#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
-#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
-#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on STOPPED event. */
-#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
-#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
-#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: TWI_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 18 : Disable interrupt on SUSPENDED event. */
-#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
-#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
-#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 14 : Disable interrupt on BB event. */
-#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
-#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
-#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 9 : Disable interrupt on ERROR event. */
-#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
-#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 7 : Disable interrupt on TXDSENT event. */
-#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
-#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
-#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on RXDREADY event. */
-#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
-#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
-#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on STOPPED event. */
-#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
-#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
-#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: TWI_ERRORSRC */
-/* Description: Two-wire error source. Write error field to 1 to clear error. */
-
-/* Bit 2 : NACK received after sending a data byte. */
-#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
-#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
-#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
-#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
-#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
-
-/* Bit 1 : NACK received after sending the address. */
-#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
-#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
-#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
-#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
-#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
-
-/* Register: TWI_ENABLE */
-/* Description: Enable two-wire master. */
-
-/* Bits 2..0 : Enable or disable W2M */
-#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
-#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
-
-/* Register: TWI_RXD */
-/* Description: RX data register. */
-
-/* Bits 7..0 : RX data from last transfer. */
-#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
-#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
-
-/* Register: TWI_TXD */
-/* Description: TX data register. */
-
-/* Bits 7..0 : TX data for next transfer. */
-#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
-#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
-
-/* Register: TWI_FREQUENCY */
-/* Description: Two-wire frequency. */
-
-/* Bits 31..0 : Two-wire master clock frequency. */
-#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
-#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
-#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
-#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
-#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
-
-/* Register: TWI_ADDRESS */
-/* Description: Address used in the two-wire transfer. */
-
-/* Bits 6..0 : Two-wire address. */
-#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
-#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
-
-/* Register: TWI_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: UART */
-/* Description: Universal Asynchronous Receiver/Transmitter. */
-
-/* Register: UART_SHORTS */
-/* Description: Shortcuts for UART. */
-
-/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
-#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
-#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
-#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
-#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
-#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
-#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
-#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
-#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: UART_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 17 : Enable interrupt on RXTO event. */
-#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
-#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
-#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 9 : Enable interrupt on ERROR event. */
-#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
-#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 7 : Enable interrupt on TXRDY event. */
-#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
-#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
-#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on RXRDY event. */
-#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
-#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
-#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on NCTS event. */
-#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
-#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
-#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on CTS event. */
-#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
-#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
-#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: UART_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 17 : Disable interrupt on RXTO event. */
-#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
-#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
-#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 9 : Disable interrupt on ERROR event. */
-#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
-#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 7 : Disable interrupt on TXRDY event. */
-#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
-#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
-#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on RXRDY event. */
-#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
-#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
-#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on NCTS event. */
-#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
-#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
-#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on CTS event. */
-#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
-#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
-#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: UART_ERRORSRC */
-/* Description: Error source. Write error field to 1 to clear error. */
-
-/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
-#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
-#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
-#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
-#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
-#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
-
-/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
-#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
-#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
-#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
-#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
-#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
-
-/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
-#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
-#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
-#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
-#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
-#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
-
-/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
-#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
-#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
-#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
-#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
-#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
-
-/* Register: UART_ENABLE */
-/* Description: Enable UART and acquire IOs. */
-
-/* Bits 2..0 : Enable or disable UART and acquire IOs. */
-#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
-#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
-
-/* Register: UART_RXD */
-/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
-
-/* Bits 7..0 : RX data from previous transfer. Double buffered. */
-#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
-#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
-
-/* Register: UART_TXD */
-/* Description: TXD register. */
-
-/* Bits 7..0 : TX data for transfer. */
-#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
-#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
-
-/* Register: UART_BAUDRATE */
-/* Description: UART Baudrate. */
-
-/* Bits 31..0 : UART baudrate. */
-#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
-#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
-#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
-
-/* Register: UART_CONFIG */
-/* Description: Configuration of parity and hardware flow control register. */
-
-/* Bits 3..1 : Include parity bit. */
-#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
-#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
-#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
-#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
-
-/* Bit 0 : Hardware flow control. */
-#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
-#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
-#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
-#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
-
-/* Register: UART_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: UICR */
-/* Description: User Information Configuration. */
-
-/* Register: UICR_RBPCONF */
-/* Description: Readback protection configuration. */
-
-/* Bits 15..8 : Readback protect all code in the device. */
-#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
-#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
-#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
-#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
-
-/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
-#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
-#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
-#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
-#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
-
-/* Register: UICR_XTALFREQ */
-/* Description: Reset value for CLOCK XTALFREQ register. */
-
-/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
-#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
-#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
-#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
-#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
-
-/* Register: UICR_FWID */
-/* Description: Firmware ID. */
-
-/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
-#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
-#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
-
-
-/* Peripheral: WDT */
-/* Description: Watchdog Timer. */
-
-/* Register: WDT_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 0 : Enable interrupt on TIMEOUT event. */
-#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
-#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
-#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
-#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
-#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: WDT_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 0 : Disable interrupt on TIMEOUT event. */
-#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
-#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
-#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
-#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
-#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: WDT_RUNSTATUS */
-/* Description: Watchdog running status. */
-
-/* Bit 0 : Watchdog running status. */
-#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
-#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
-#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
-#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
-
-/* Register: WDT_REQSTATUS */
-/* Description: Request status. */
-
-/* Bit 7 : Request status for RR[7]. */
-#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
-#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
-#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
-
-/* Bit 6 : Request status for RR[6]. */
-#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
-#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
-#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
-
-/* Bit 5 : Request status for RR[5]. */
-#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
-#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
-#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
-
-/* Bit 4 : Request status for RR[4]. */
-#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
-#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
-#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
-
-/* Bit 3 : Request status for RR[3]. */
-#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
-#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
-#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
-
-/* Bit 2 : Request status for RR[2]. */
-#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
-#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
-#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
-
-/* Bit 1 : Request status for RR[1]. */
-#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
-#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
-#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
-
-/* Bit 0 : Request status for RR[0]. */
-#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
-#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
-#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
-
-/* Register: WDT_RREN */
-/* Description: Reload request enable. */
-
-/* Bit 7 : Enable or disable RR[7] register. */
-#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
-#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
-#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
-#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
-
-/* Bit 6 : Enable or disable RR[6] register. */
-#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
-#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
-#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
-#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
-
-/* Bit 5 : Enable or disable RR[5] register. */
-#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
-#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
-#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
-#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
-
-/* Bit 4 : Enable or disable RR[4] register. */
-#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
-#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
-#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
-#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
-
-/* Bit 3 : Enable or disable RR[3] register. */
-#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
-#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
-#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
-#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
-
-/* Bit 2 : Enable or disable RR[2] register. */
-#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
-#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
-#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
-#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
-
-/* Bit 1 : Enable or disable RR[1] register. */
-#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
-#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
-#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
-#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
-
-/* Bit 0 : Enable or disable RR[0] register. */
-#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
-#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
-#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
-#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
-
-/* Register: WDT_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
-#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
-#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
-#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
-#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
-
-/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
-#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
-#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
-#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
-#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
-
-/* Register: WDT_RR */
-/* Description: Reload requests registers. */
-
-/* Bits 31..0 : Reload register. */
-#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
-#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
-#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
-
-/* Register: WDT_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/*lint --flb "Leave library region" */
-#endif
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf51_deprecated.h
--- a/nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf51_deprecated.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,437 +0,0 @@
-/* Copyright (c) 2013, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright notice, this
- *     list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright notice,
- *     this list of conditions and the following disclaimer in the documentation
- *     and/or other materials provided with the distribution.
- *
- *   * Neither the name of Nordic Semiconductor ASA nor the names of its
- *     contributors may be used to endorse or promote products derived from
- *     this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-#ifndef NRF51_DEPRECATED_H
-#define NRF51_DEPRECATED_H
-
-/*lint ++flb "Enter library region */
-
-/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and 
- * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
- * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
- */
-
-/* NVMC */
-/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
-#define ERASEPCR0   ERASEPROTECTEDPAGE
-/* The register ERASEPAGE is also called ERASEPCR1 in the documentation. */
-#define ERASEPCR1   ERASEPAGE
- 
-/* LPCOMP */
-/* The interrupt ISR was renamed. Adding old name to the macros. */
-#define LPCOMP_COMP_IRQHandler      LPCOMP_IRQHandler
- 
- 
-/* MPU */
-/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
-#define MPU_PERR0_LPCOMP_COMP_Pos           MPU_PERR0_LPCOMP_Pos
-#define MPU_PERR0_LPCOMP_COMP_Msk           MPU_PERR0_LPCOMP_Msk
-#define MPU_PERR0_LPCOMP_COMP_InRegion1     MPU_PERR0_LPCOMP_InRegion1
-#define MPU_PERR0_LPCOMP_COMP_InRegion0     MPU_PERR0_LPCOMP_InRegion0
- 
- 
-/* POWER */
-/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
-#define POWER_RAMON_OFFRAM3_Pos         (19UL)                                  
-#define POWER_RAMON_OFFRAM3_Msk         (0x1UL << POWER_RAMON_OFFRAM3_Pos)      
-#define POWER_RAMON_OFFRAM3_RAM3Off     (0UL)                                   
-#define POWER_RAMON_OFFRAM3_RAM3On      (1UL)                                   
-/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
-#define POWER_RAMON_OFFRAM2_Pos         (18UL)                                  
-#define POWER_RAMON_OFFRAM2_Msk         (0x1UL << POWER_RAMON_OFFRAM2_Pos)      
-#define POWER_RAMON_OFFRAM2_RAM2Off     (0UL)                                   
-#define POWER_RAMON_OFFRAM2_RAM2On      (1UL)                                  
-/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
-#define POWER_RAMON_ONRAM3_Pos          (3UL)                                  
-#define POWER_RAMON_ONRAM3_Msk          (0x1UL << POWER_RAMON_ONRAM3_Pos)      
-#define POWER_RAMON_ONRAM3_RAM3Off      (0UL)                                  
-#define POWER_RAMON_ONRAM3_RAM3On       (1UL)                                  
-/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
-#define POWER_RAMON_ONRAM2_Pos          (2UL)                                  
-#define POWER_RAMON_ONRAM2_Msk          (0x1UL << POWER_RAMON_ONRAM2_Pos)       
-#define POWER_RAMON_ONRAM2_RAM2Off      (0UL)                                  
-#define POWER_RAMON_ONRAM2_RAM2On       (1UL)                                 
-
- 
-/* RADIO */
-/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
-#define RADIO_TXPOWER_TXPOWER_Neg40dBm  RADIO_TXPOWER_TXPOWER_Neg30dBm      
-/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
-#define RADIO_CRCCNF_SKIP_ADDR_Pos      RADIO_CRCCNF_SKIPADDR_Pos 
-#define RADIO_CRCCNF_SKIP_ADDR_Msk      RADIO_CRCCNF_SKIPADDR_Msk 
-#define RADIO_CRCCNF_SKIP_ADDR_Include  RADIO_CRCCNF_SKIPADDR_Include 
-#define RADIO_CRCCNF_SKIP_ADDR_Skip     RADIO_CRCCNF_SKIPADDR_Skip 
-/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
-#define RADIO_TEST_PLL_LOCK_Pos         RADIO_TEST_PLLLOCK_Pos 
-#define RADIO_TEST_PLL_LOCK_Msk         RADIO_TEST_PLLLOCK_Msk 
-#define RADIO_TEST_PLL_LOCK_Disabled    RADIO_TEST_PLLLOCK_Disabled 
-#define RADIO_TEST_PLL_LOCK_Enabled     RADIO_TEST_PLLLOCK_Enabled 
-/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
-#define RADIO_TEST_CONST_CARRIER_Pos        RADIO_TEST_CONSTCARRIER_Pos 
-#define RADIO_TEST_CONST_CARRIER_Msk        RADIO_TEST_CONSTCARRIER_Msk 
-#define RADIO_TEST_CONST_CARRIER_Disabled   RADIO_TEST_CONSTCARRIER_Disabled 
-#define RADIO_TEST_CONST_CARRIER_Enabled    RADIO_TEST_CONSTCARRIER_Enabled 
-
-
-/* FICR */
-/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
-#define SIZERAMBLOCK0   SIZERAMBLOCKS                   
-#define SIZERAMBLOCK1   SIZERAMBLOCKS                   
-#define SIZERAMBLOCK2   SIZERAMBLOCK[2]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
-#define SIZERAMBLOCK3   SIZERAMBLOCK[3]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
-/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
-#define DEVICEID0       DEVICEID[0]                     
-#define DEVICEID1       DEVICEID[1]                     
-/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
-#define ER0             ER[0]                           
-#define ER1             ER[1]                          
-#define ER2             ER[2]                       
-#define ER3             ER[3]                      
-/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
-#define IR0             IR[0]                         
-#define IR1             IR[1]                         
-#define IR2             IR[2]                         
-#define IR3             IR[3]                          
-/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
-#define DEVICEADDR0     DEVICEADDR[0]                  
-#define DEVICEADDR1     DEVICEADDR[1]                  
-
-
-/* PPI */
-/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
-#define TASKS_CHG0EN     TASKS_CHG[0].EN                    
-#define TASKS_CHG0DIS    TASKS_CHG[0].DIS                  
-#define TASKS_CHG1EN     TASKS_CHG[1].EN                    
-#define TASKS_CHG1DIS    TASKS_CHG[1].DIS                  
-#define TASKS_CHG2EN     TASKS_CHG[2].EN                   
-#define TASKS_CHG2DIS    TASKS_CHG[2].DIS                  
-#define TASKS_CHG3EN     TASKS_CHG[3].EN                    
-#define TASKS_CHG3DIS    TASKS_CHG[3].DIS                  
-/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
-#define CH0_EEP          CH[0].EEP                          
-#define CH0_TEP          CH[0].TEP                          
-#define CH1_EEP          CH[1].EEP                         
-#define CH1_TEP          CH[1].TEP                         
-#define CH2_EEP          CH[2].EEP                          
-#define CH2_TEP          CH[2].TEP                         
-#define CH3_EEP          CH[3].EEP                          
-#define CH3_TEP          CH[3].TEP                         
-#define CH4_EEP          CH[4].EEP                         
-#define CH4_TEP          CH[4].TEP                         
-#define CH5_EEP          CH[5].EEP                          
-#define CH5_TEP          CH[5].TEP                          
-#define CH6_EEP          CH[6].EEP                          
-#define CH6_TEP          CH[6].TEP                         
-#define CH7_EEP          CH[7].EEP                          
-#define CH7_TEP          CH[7].TEP                          
-#define CH8_EEP          CH[8].EEP                         
-#define CH8_TEP          CH[8].TEP                          
-#define CH9_EEP          CH[9].EEP                          
-#define CH9_TEP          CH[9].TEP                          
-#define CH10_EEP         CH[10].EEP                         
-#define CH10_TEP         CH[10].TEP                         
-#define CH11_EEP         CH[11].EEP                         
-#define CH11_TEP         CH[11].TEP                         
-#define CH12_EEP         CH[12].EEP                         
-#define CH12_TEP         CH[12].TEP                         
-#define CH13_EEP         CH[13].EEP                         
-#define CH13_TEP         CH[13].TEP                         
-#define CH14_EEP         CH[14].EEP                         
-#define CH14_TEP         CH[14].TEP                         
-#define CH15_EEP         CH[15].EEP                         
-#define CH15_TEP         CH[15].TEP                        
-/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
-#define CHG0             CHG[0]                            
-#define CHG1             CHG[1]                            
-#define CHG2             CHG[2]                             
-#define CHG3             CHG[3]                           
-/* All bitfield macros for the CHGx registers therefore changed name. */
-#define PPI_CHG0_CH15_Pos       PPI_CHG_CH15_Pos            
-#define PPI_CHG0_CH15_Msk       PPI_CHG_CH15_Msk            
-#define PPI_CHG0_CH15_Excluded  PPI_CHG_CH15_Excluded       
-#define PPI_CHG0_CH15_Included  PPI_CHG_CH15_Included       
-#define PPI_CHG0_CH14_Pos       PPI_CHG_CH14_Pos            
-#define PPI_CHG0_CH14_Msk       PPI_CHG_CH14_Msk           
-#define PPI_CHG0_CH14_Excluded  PPI_CHG_CH14_Excluded       
-#define PPI_CHG0_CH14_Included  PPI_CHG_CH14_Included       
-#define PPI_CHG0_CH13_Pos       PPI_CHG_CH13_Pos            
-#define PPI_CHG0_CH13_Msk       PPI_CHG_CH13_Msk            
-#define PPI_CHG0_CH13_Excluded  PPI_CHG_CH13_Excluded      
-#define PPI_CHG0_CH13_Included  PPI_CHG_CH13_Included       
-#define PPI_CHG0_CH12_Pos       PPI_CHG_CH12_Pos            
-#define PPI_CHG0_CH12_Msk       PPI_CHG_CH12_Msk            
-#define PPI_CHG0_CH12_Excluded  PPI_CHG_CH12_Excluded       
-#define PPI_CHG0_CH12_Included  PPI_CHG_CH12_Included       
-#define PPI_CHG0_CH11_Pos       PPI_CHG_CH11_Pos            
-#define PPI_CHG0_CH11_Msk       PPI_CHG_CH11_Msk            
-#define PPI_CHG0_CH11_Excluded  PPI_CHG_CH11_Excluded       
-#define PPI_CHG0_CH11_Included  PPI_CHG_CH11_Included       
-#define PPI_CHG0_CH10_Pos       PPI_CHG_CH10_Pos            
-#define PPI_CHG0_CH10_Msk       PPI_CHG_CH10_Msk            
-#define PPI_CHG0_CH10_Excluded  PPI_CHG_CH10_Excluded       
-#define PPI_CHG0_CH10_Included  PPI_CHG_CH10_Included       
-#define PPI_CHG0_CH9_Pos        PPI_CHG_CH9_Pos             
-#define PPI_CHG0_CH9_Msk        PPI_CHG_CH9_Msk             
-#define PPI_CHG0_CH9_Excluded   PPI_CHG_CH9_Excluded        
-#define PPI_CHG0_CH9_Included   PPI_CHG_CH9_Included        
-#define PPI_CHG0_CH8_Pos        PPI_CHG_CH8_Pos             
-#define PPI_CHG0_CH8_Msk        PPI_CHG_CH8_Msk             
-#define PPI_CHG0_CH8_Excluded   PPI_CHG_CH8_Excluded        
-#define PPI_CHG0_CH8_Included   PPI_CHG_CH8_Included        
-#define PPI_CHG0_CH7_Pos        PPI_CHG_CH7_Pos             
-#define PPI_CHG0_CH7_Msk        PPI_CHG_CH7_Msk             
-#define PPI_CHG0_CH7_Excluded   PPI_CHG_CH7_Excluded        
-#define PPI_CHG0_CH7_Included   PPI_CHG_CH7_Included        
-#define PPI_CHG0_CH6_Pos        PPI_CHG_CH6_Pos             
-#define PPI_CHG0_CH6_Msk        PPI_CHG_CH6_Msk             
-#define PPI_CHG0_CH6_Excluded   PPI_CHG_CH6_Excluded        
-#define PPI_CHG0_CH6_Included   PPI_CHG_CH6_Included        
-#define PPI_CHG0_CH5_Pos        PPI_CHG_CH5_Pos             
-#define PPI_CHG0_CH5_Msk        PPI_CHG_CH5_Msk             
-#define PPI_CHG0_CH5_Excluded   PPI_CHG_CH5_Excluded       
-#define PPI_CHG0_CH5_Included   PPI_CHG_CH5_Included        
-#define PPI_CHG0_CH4_Pos        PPI_CHG_CH4_Pos             
-#define PPI_CHG0_CH4_Msk        PPI_CHG_CH4_Msk             
-#define PPI_CHG0_CH4_Excluded   PPI_CHG_CH4_Excluded       
-#define PPI_CHG0_CH4_Included   PPI_CHG_CH4_Included       
-#define PPI_CHG0_CH3_Pos        PPI_CHG_CH3_Pos             
-#define PPI_CHG0_CH3_Msk        PPI_CHG_CH3_Msk            
-#define PPI_CHG0_CH3_Excluded   PPI_CHG_CH3_Excluded        
-#define PPI_CHG0_CH3_Included   PPI_CHG_CH3_Included       
-#define PPI_CHG0_CH2_Pos        PPI_CHG_CH2_Pos            
-#define PPI_CHG0_CH2_Msk        PPI_CHG_CH2_Msk             
-#define PPI_CHG0_CH2_Excluded   PPI_CHG_CH2_Excluded       
-#define PPI_CHG0_CH2_Included   PPI_CHG_CH2_Included       
-#define PPI_CHG0_CH1_Pos        PPI_CHG_CH1_Pos            
-#define PPI_CHG0_CH1_Msk        PPI_CHG_CH1_Msk            
-#define PPI_CHG0_CH1_Excluded   PPI_CHG_CH1_Excluded        
-#define PPI_CHG0_CH1_Included   PPI_CHG_CH1_Included       
-#define PPI_CHG0_CH0_Pos        PPI_CHG_CH0_Pos            
-#define PPI_CHG0_CH0_Msk        PPI_CHG_CH0_Msk            
-#define PPI_CHG0_CH0_Excluded   PPI_CHG_CH0_Excluded        
-#define PPI_CHG0_CH0_Included   PPI_CHG_CH0_Included       
-#define PPI_CHG1_CH15_Pos       PPI_CHG_CH15_Pos           
-#define PPI_CHG1_CH15_Msk       PPI_CHG_CH15_Msk           
-#define PPI_CHG1_CH15_Excluded  PPI_CHG_CH15_Excluded       
-#define PPI_CHG1_CH15_Included  PPI_CHG_CH15_Included      
-#define PPI_CHG1_CH14_Pos       PPI_CHG_CH14_Pos           
-#define PPI_CHG1_CH14_Msk       PPI_CHG_CH14_Msk            
-#define PPI_CHG1_CH14_Excluded  PPI_CHG_CH14_Excluded      
-#define PPI_CHG1_CH14_Included  PPI_CHG_CH14_Included       
-#define PPI_CHG1_CH13_Pos       PPI_CHG_CH13_Pos           
-#define PPI_CHG1_CH13_Msk       PPI_CHG_CH13_Msk            
-#define PPI_CHG1_CH13_Excluded  PPI_CHG_CH13_Excluded      
-#define PPI_CHG1_CH13_Included  PPI_CHG_CH13_Included      
-#define PPI_CHG1_CH12_Pos       PPI_CHG_CH12_Pos            
-#define PPI_CHG1_CH12_Msk       PPI_CHG_CH12_Msk           
-#define PPI_CHG1_CH12_Excluded  PPI_CHG_CH12_Excluded      
-#define PPI_CHG1_CH12_Included  PPI_CHG_CH12_Included      
-#define PPI_CHG1_CH11_Pos       PPI_CHG_CH11_Pos            
-#define PPI_CHG1_CH11_Msk       PPI_CHG_CH11_Msk           
-#define PPI_CHG1_CH11_Excluded  PPI_CHG_CH11_Excluded      
-#define PPI_CHG1_CH11_Included  PPI_CHG_CH11_Included      
-#define PPI_CHG1_CH10_Pos       PPI_CHG_CH10_Pos           
-#define PPI_CHG1_CH10_Msk       PPI_CHG_CH10_Msk            
-#define PPI_CHG1_CH10_Excluded  PPI_CHG_CH10_Excluded      
-#define PPI_CHG1_CH10_Included  PPI_CHG_CH10_Included      
-#define PPI_CHG1_CH9_Pos        PPI_CHG_CH9_Pos            
-#define PPI_CHG1_CH9_Msk        PPI_CHG_CH9_Msk            
-#define PPI_CHG1_CH9_Excluded   PPI_CHG_CH9_Excluded       
-#define PPI_CHG1_CH9_Included   PPI_CHG_CH9_Included       
-#define PPI_CHG1_CH8_Pos        PPI_CHG_CH8_Pos            
-#define PPI_CHG1_CH8_Msk        PPI_CHG_CH8_Msk            
-#define PPI_CHG1_CH8_Excluded   PPI_CHG_CH8_Excluded       
-#define PPI_CHG1_CH8_Included   PPI_CHG_CH8_Included       
-#define PPI_CHG1_CH7_Pos        PPI_CHG_CH7_Pos             
-#define PPI_CHG1_CH7_Msk        PPI_CHG_CH7_Msk            
-#define PPI_CHG1_CH7_Excluded   PPI_CHG_CH7_Excluded        
-#define PPI_CHG1_CH7_Included   PPI_CHG_CH7_Included       
-#define PPI_CHG1_CH6_Pos        PPI_CHG_CH6_Pos             
-#define PPI_CHG1_CH6_Msk        PPI_CHG_CH6_Msk            
-#define PPI_CHG1_CH6_Excluded   PPI_CHG_CH6_Excluded       
-#define PPI_CHG1_CH6_Included   PPI_CHG_CH6_Included       
-#define PPI_CHG1_CH5_Pos        PPI_CHG_CH5_Pos             
-#define PPI_CHG1_CH5_Msk        PPI_CHG_CH5_Msk             
-#define PPI_CHG1_CH5_Excluded   PPI_CHG_CH5_Excluded       
-#define PPI_CHG1_CH5_Included   PPI_CHG_CH5_Included        
-#define PPI_CHG1_CH4_Pos        PPI_CHG_CH4_Pos             
-#define PPI_CHG1_CH4_Msk        PPI_CHG_CH4_Msk             
-#define PPI_CHG1_CH4_Excluded   PPI_CHG_CH4_Excluded        
-#define PPI_CHG1_CH4_Included   PPI_CHG_CH4_Included        
-#define PPI_CHG1_CH3_Pos        PPI_CHG_CH3_Pos            
-#define PPI_CHG1_CH3_Msk        PPI_CHG_CH3_Msk             
-#define PPI_CHG1_CH3_Excluded   PPI_CHG_CH3_Excluded        
-#define PPI_CHG1_CH3_Included   PPI_CHG_CH3_Included       
-#define PPI_CHG1_CH2_Pos        PPI_CHG_CH2_Pos            
-#define PPI_CHG1_CH2_Msk        PPI_CHG_CH2_Msk             
-#define PPI_CHG1_CH2_Excluded   PPI_CHG_CH2_Excluded        
-#define PPI_CHG1_CH2_Included   PPI_CHG_CH2_Included        
-#define PPI_CHG1_CH1_Pos        PPI_CHG_CH1_Pos             
-#define PPI_CHG1_CH1_Msk        PPI_CHG_CH1_Msk            
-#define PPI_CHG1_CH1_Excluded   PPI_CHG_CH1_Excluded        
-#define PPI_CHG1_CH1_Included   PPI_CHG_CH1_Included       
-#define PPI_CHG1_CH0_Pos        PPI_CHG_CH0_Pos             
-#define PPI_CHG1_CH0_Msk        PPI_CHG_CH0_Msk            
-#define PPI_CHG1_CH0_Excluded   PPI_CHG_CH0_Excluded       
-#define PPI_CHG1_CH0_Included   PPI_CHG_CH0_Included       
-#define PPI_CHG2_CH15_Pos       PPI_CHG_CH15_Pos           
-#define PPI_CHG2_CH15_Msk       PPI_CHG_CH15_Msk            
-#define PPI_CHG2_CH15_Excluded  PPI_CHG_CH15_Excluded      
-#define PPI_CHG2_CH15_Included  PPI_CHG_CH15_Included      
-#define PPI_CHG2_CH14_Pos       PPI_CHG_CH14_Pos           
-#define PPI_CHG2_CH14_Msk       PPI_CHG_CH14_Msk           
-#define PPI_CHG2_CH14_Excluded  PPI_CHG_CH14_Excluded       
-#define PPI_CHG2_CH14_Included  PPI_CHG_CH14_Included      
-#define PPI_CHG2_CH13_Pos       PPI_CHG_CH13_Pos           
-#define PPI_CHG2_CH13_Msk       PPI_CHG_CH13_Msk            
-#define PPI_CHG2_CH13_Excluded  PPI_CHG_CH13_Excluded       
-#define PPI_CHG2_CH13_Included  PPI_CHG_CH13_Included      
-#define PPI_CHG2_CH12_Pos       PPI_CHG_CH12_Pos            
-#define PPI_CHG2_CH12_Msk       PPI_CHG_CH12_Msk            
-#define PPI_CHG2_CH12_Excluded  PPI_CHG_CH12_Excluded      
-#define PPI_CHG2_CH12_Included  PPI_CHG_CH12_Included       
-#define PPI_CHG2_CH11_Pos       PPI_CHG_CH11_Pos           
-#define PPI_CHG2_CH11_Msk       PPI_CHG_CH11_Msk           
-#define PPI_CHG2_CH11_Excluded  PPI_CHG_CH11_Excluded       
-#define PPI_CHG2_CH11_Included  PPI_CHG_CH11_Included       
-#define PPI_CHG2_CH10_Pos       PPI_CHG_CH10_Pos            
-#define PPI_CHG2_CH10_Msk       PPI_CHG_CH10_Msk            
-#define PPI_CHG2_CH10_Excluded  PPI_CHG_CH10_Excluded      
-#define PPI_CHG2_CH10_Included  PPI_CHG_CH10_Included      
-#define PPI_CHG2_CH9_Pos        PPI_CHG_CH9_Pos            
-#define PPI_CHG2_CH9_Msk        PPI_CHG_CH9_Msk            
-#define PPI_CHG2_CH9_Excluded   PPI_CHG_CH9_Excluded        
-#define PPI_CHG2_CH9_Included   PPI_CHG_CH9_Included       
-#define PPI_CHG2_CH8_Pos        PPI_CHG_CH8_Pos            
-#define PPI_CHG2_CH8_Msk        PPI_CHG_CH8_Msk            
-#define PPI_CHG2_CH8_Excluded   PPI_CHG_CH8_Excluded       
-#define PPI_CHG2_CH8_Included   PPI_CHG_CH8_Included        
-#define PPI_CHG2_CH7_Pos        PPI_CHG_CH7_Pos            
-#define PPI_CHG2_CH7_Msk        PPI_CHG_CH7_Msk            
-#define PPI_CHG2_CH7_Excluded   PPI_CHG_CH7_Excluded       
-#define PPI_CHG2_CH7_Included   PPI_CHG_CH7_Included       
-#define PPI_CHG2_CH6_Pos        PPI_CHG_CH6_Pos            
-#define PPI_CHG2_CH6_Msk        PPI_CHG_CH6_Msk            
-#define PPI_CHG2_CH6_Excluded   PPI_CHG_CH6_Excluded       
-#define PPI_CHG2_CH6_Included   PPI_CHG_CH6_Included       
-#define PPI_CHG2_CH5_Pos        PPI_CHG_CH5_Pos            
-#define PPI_CHG2_CH5_Msk        PPI_CHG_CH5_Msk            
-#define PPI_CHG2_CH5_Excluded   PPI_CHG_CH5_Excluded       
-#define PPI_CHG2_CH5_Included   PPI_CHG_CH5_Included        
-#define PPI_CHG2_CH4_Pos        PPI_CHG_CH4_Pos             
-#define PPI_CHG2_CH4_Msk        PPI_CHG_CH4_Msk             
-#define PPI_CHG2_CH4_Excluded   PPI_CHG_CH4_Excluded        
-#define PPI_CHG2_CH4_Included   PPI_CHG_CH4_Included       
-#define PPI_CHG2_CH3_Pos        PPI_CHG_CH3_Pos            
-#define PPI_CHG2_CH3_Msk        PPI_CHG_CH3_Msk            
-#define PPI_CHG2_CH3_Excluded   PPI_CHG_CH3_Excluded       
-#define PPI_CHG2_CH3_Included   PPI_CHG_CH3_Included       
-#define PPI_CHG2_CH2_Pos        PPI_CHG_CH2_Pos            
-#define PPI_CHG2_CH2_Msk        PPI_CHG_CH2_Msk           
-#define PPI_CHG2_CH2_Excluded   PPI_CHG_CH2_Excluded       
-#define PPI_CHG2_CH2_Included   PPI_CHG_CH2_Included       
-#define PPI_CHG2_CH1_Pos        PPI_CHG_CH1_Pos             
-#define PPI_CHG2_CH1_Msk        PPI_CHG_CH1_Msk             
-#define PPI_CHG2_CH1_Excluded   PPI_CHG_CH1_Excluded       
-#define PPI_CHG2_CH1_Included   PPI_CHG_CH1_Included       
-#define PPI_CHG2_CH0_Pos        PPI_CHG_CH0_Pos            
-#define PPI_CHG2_CH0_Msk        PPI_CHG_CH0_Msk            
-#define PPI_CHG2_CH0_Excluded   PPI_CHG_CH0_Excluded       
-#define PPI_CHG2_CH0_Included   PPI_CHG_CH0_Included        
-#define PPI_CHG3_CH15_Pos       PPI_CHG_CH15_Pos           
-#define PPI_CHG3_CH15_Msk       PPI_CHG_CH15_Msk           
-#define PPI_CHG3_CH15_Excluded  PPI_CHG_CH15_Excluded     
-#define PPI_CHG3_CH15_Included  PPI_CHG_CH15_Included      
-#define PPI_CHG3_CH14_Pos       PPI_CHG_CH14_Pos          
-#define PPI_CHG3_CH14_Msk       PPI_CHG_CH14_Msk           
-#define PPI_CHG3_CH14_Excluded  PPI_CHG_CH14_Excluded      
-#define PPI_CHG3_CH14_Included  PPI_CHG_CH14_Included       
-#define PPI_CHG3_CH13_Pos       PPI_CHG_CH13_Pos           
-#define PPI_CHG3_CH13_Msk       PPI_CHG_CH13_Msk            
-#define PPI_CHG3_CH13_Excluded  PPI_CHG_CH13_Excluded      
-#define PPI_CHG3_CH13_Included  PPI_CHG_CH13_Included      
-#define PPI_CHG3_CH12_Pos       PPI_CHG_CH12_Pos            
-#define PPI_CHG3_CH12_Msk       PPI_CHG_CH12_Msk            
-#define PPI_CHG3_CH12_Excluded  PPI_CHG_CH12_Excluded       
-#define PPI_CHG3_CH12_Included  PPI_CHG_CH12_Included       
-#define PPI_CHG3_CH11_Pos       PPI_CHG_CH11_Pos            
-#define PPI_CHG3_CH11_Msk       PPI_CHG_CH11_Msk            
-#define PPI_CHG3_CH11_Excluded  PPI_CHG_CH11_Excluded      
-#define PPI_CHG3_CH11_Included  PPI_CHG_CH11_Included       
-#define PPI_CHG3_CH10_Pos       PPI_CHG_CH10_Pos            
-#define PPI_CHG3_CH10_Msk       PPI_CHG_CH10_Msk            
-#define PPI_CHG3_CH10_Excluded  PPI_CHG_CH10_Excluded      
-#define PPI_CHG3_CH10_Included  PPI_CHG_CH10_Included      
-#define PPI_CHG3_CH9_Pos        PPI_CHG_CH9_Pos            
-#define PPI_CHG3_CH9_Msk        PPI_CHG_CH9_Msk            
-#define PPI_CHG3_CH9_Excluded   PPI_CHG_CH9_Excluded       
-#define PPI_CHG3_CH9_Included   PPI_CHG_CH9_Included       
-#define PPI_CHG3_CH8_Pos        PPI_CHG_CH8_Pos            
-#define PPI_CHG3_CH8_Msk        PPI_CHG_CH8_Msk             
-#define PPI_CHG3_CH8_Excluded   PPI_CHG_CH8_Excluded       
-#define PPI_CHG3_CH8_Included   PPI_CHG_CH8_Included       
-#define PPI_CHG3_CH7_Pos        PPI_CHG_CH7_Pos             
-#define PPI_CHG3_CH7_Msk        PPI_CHG_CH7_Msk            
-#define PPI_CHG3_CH7_Excluded   PPI_CHG_CH7_Excluded        
-#define PPI_CHG3_CH7_Included   PPI_CHG_CH7_Included       
-#define PPI_CHG3_CH6_Pos        PPI_CHG_CH6_Pos             
-#define PPI_CHG3_CH6_Msk        PPI_CHG_CH6_Msk             
-#define PPI_CHG3_CH6_Excluded   PPI_CHG_CH6_Excluded       
-#define PPI_CHG3_CH6_Included   PPI_CHG_CH6_Included        
-#define PPI_CHG3_CH5_Pos        PPI_CHG_CH5_Pos             
-#define PPI_CHG3_CH5_Msk        PPI_CHG_CH5_Msk             
-#define PPI_CHG3_CH5_Excluded   PPI_CHG_CH5_Excluded        
-#define PPI_CHG3_CH5_Included   PPI_CHG_CH5_Included       
-#define PPI_CHG3_CH4_Pos        PPI_CHG_CH4_Pos             
-#define PPI_CHG3_CH4_Msk        PPI_CHG_CH4_Msk            
-#define PPI_CHG3_CH4_Excluded   PPI_CHG_CH4_Excluded        
-#define PPI_CHG3_CH4_Included   PPI_CHG_CH4_Included        
-#define PPI_CHG3_CH3_Pos        PPI_CHG_CH3_Pos             
-#define PPI_CHG3_CH3_Msk        PPI_CHG_CH3_Msk            
-#define PPI_CHG3_CH3_Excluded   PPI_CHG_CH3_Excluded        
-#define PPI_CHG3_CH3_Included   PPI_CHG_CH3_Included        
-#define PPI_CHG3_CH2_Pos        PPI_CHG_CH2_Pos             
-#define PPI_CHG3_CH2_Msk        PPI_CHG_CH2_Msk             
-#define PPI_CHG3_CH2_Excluded   PPI_CHG_CH2_Excluded        
-#define PPI_CHG3_CH2_Included   PPI_CHG_CH2_Included       
-#define PPI_CHG3_CH1_Pos        PPI_CHG_CH1_Pos             
-#define PPI_CHG3_CH1_Msk        PPI_CHG_CH1_Msk             
-#define PPI_CHG3_CH1_Excluded   PPI_CHG_CH1_Excluded        
-#define PPI_CHG3_CH1_Included   PPI_CHG_CH1_Included        
-#define PPI_CHG3_CH0_Pos        PPI_CHG_CH0_Pos             
-#define PPI_CHG3_CH0_Msk        PPI_CHG_CH0_Msk             
-#define PPI_CHG3_CH0_Excluded   PPI_CHG_CH0_Excluded        
-#define PPI_CHG3_CH0_Included   PPI_CHG_CH0_Included        
-
-
-
-/*lint --flb "Leave library region" */
-
-#endif /* NRF51_DEPRECATED_H */
-
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_delay.c
--- a/nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_delay.c	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,26 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
- 
-#include <stdio.h> 
-#include "compiler_abstraction.h"
-#include "nrf.h"
-#include "nrf_delay.h"
-
-/*lint --e{438} "Variable not used" */
-void nrf_delay_ms(uint32_t volatile number_of_ms)
-{
-    while(number_of_ms != 0)
-    {
-        number_of_ms--;
-        nrf_delay_us(999);
-    }
-}
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_ecb.c
--- a/nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_ecb.c	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,74 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
-*
-* The information contained herein is property of Nordic Semiconductor ASA.
-* Terms and conditions of usage are described in detail in NORDIC
-* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. 
-*
-* Licensees are granted free, non-transferable use of the information. NO
-* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
-* the file.
-*
-* $LastChangedRevision: 25419 $
-*/ 
-
-/** 
- * @file
- * @brief Implementation of AES ECB driver
- */
-
-
-//lint -e438
-
-#include <stdlib.h>
-#include <stdbool.h>
-#include <string.h>
-#include "nrf.h" 
-#include "nrf_ecb.h"
-
-static uint8_t  ecb_data[48];   ///< ECB data structure for RNG peripheral to access.
-static uint8_t* ecb_key;        ///< Key:        Starts at ecb_data 
-static uint8_t* ecb_cleartext;  ///< Cleartext:  Starts at ecb_data + 16 bytes.
-static uint8_t* ecb_ciphertext; ///< Ciphertext: Starts at ecb_data + 32 bytes.
-
-bool nrf_ecb_init(void)
-{
-  ecb_key = ecb_data;
-  ecb_cleartext  = ecb_data + 16;
-  ecb_ciphertext = ecb_data + 32;
-
-  NRF_ECB->ECBDATAPTR = (uint32_t)ecb_data;
-  return true;
-}
-
-
-bool nrf_ecb_crypt(uint8_t * dest_buf, const uint8_t * src_buf)
-{
-   uint32_t counter = 0x1000000;
-   if(src_buf != ecb_cleartext)
-   {
-     memcpy(ecb_cleartext,src_buf,16);
-   }
-   NRF_ECB->EVENTS_ENDECB = 0;
-   NRF_ECB->TASKS_STARTECB = 1;
-   while(NRF_ECB->EVENTS_ENDECB == 0)
-   {
-    counter--;
-    if(counter == 0)
-    {
-      return false;
-    }
-   }
-   NRF_ECB->EVENTS_ENDECB = 0;
-   if(dest_buf != ecb_ciphertext)
-   {
-     memcpy(dest_buf,ecb_ciphertext,16);
-   }
-   return true;
-}
-
-void nrf_ecb_set_key(const uint8_t * key)
-{
-  memcpy(ecb_key,key,16);
-}
-
-
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_ecb.h
--- a/nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_ecb.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic 
- * Semiconductor ASA.Terms and conditions of usage are described in detail 
- * in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. 
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *              
- * $LastChangedRevision: 13999 $
- */
-
-/**
- * @file
- * @brief ECB driver API.
- */
-
-#ifndef NRF_ECB_H__
-#define NRF_ECB_H__
-
-/**
- * @defgroup nrf_ecb AES ECB encryption
- * @{
- * @ingroup nrf_drivers
- * @brief Driver for the nRF51 AES Electronic Code Book (ECB) peripheral.
- *
- * In order to encrypt and decrypt data the peripheral must be powered on
- * using nrf_ecb_init() and then the key set using nrf_ecb_set_key.
- */
-
-#include <stdint.h>
-
-/**
- * Initialize and power on the ECB peripheral.
- *
- * Allocates memory for the ECBDATAPTR.
- * @retval true Initialization was successful.
- * @retval false Powering up failed.
- */
-bool nrf_ecb_init(void);
-
-/**
- * Encrypt/decrypt 16-byte data using current key.
- *
- * The function avoids unnecessary copying of data if the point to the 
- * correct locations in the ECB data structure.
- *
- * @param dst Result of encryption/decryption. 16 bytes will be written. 
- * @param src Source with 16-byte data to be encrypted/decrypted.
- *
- * @retval true  If the encryption operation completed.
- * @retval false If the encryption operation did not complete.
- */
-bool nrf_ecb_crypt(uint8_t * dst, const uint8_t * src);
-
-/**
- * Set the key to be used for encryption/decryption.
- *
- * @param key Pointer to key. 16 bytes will be read.
- */
-void nrf_ecb_set_key(const uint8_t * key);
-
-#endif  // NRF_ECB_H__
-
-/** @} */
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_gpio.h
--- a/nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_gpio.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,422 +0,0 @@
-#ifndef NRF_GPIO_H__
-#define NRF_GPIO_H__
-
-#include "nrf51.h"
-#include "nrf51_bitfields.h"
-
-/**
- * @defgroup nrf_gpio GPIO abstraction
- * @{
- * @ingroup nrf_drivers
- * @brief GPIO pin abstraction and port abstraction for reading and writing byte-wise to GPIO ports.
- *
- * Here, the GPIO ports are defined as follows:
- * - Port 0 -> pin 0-7
- * - Port 1 -> pin 8-15
- * - Port 2 -> pin 16-23
- * - Port 3 -> pin 24-31
- */
-
-/**
- * @enum nrf_gpio_port_dir_t
- * @brief Enumerator used for setting the direction of a GPIO port.
- */
-typedef enum
-{
-    NRF_GPIO_PORT_DIR_OUTPUT,       ///<  Output
-    NRF_GPIO_PORT_DIR_INPUT         ///<  Input
-} nrf_gpio_port_dir_t;
-
-/**
- * @enum nrf_gpio_pin_dir_t
- * Pin direction definitions.
- */
-typedef enum
-{
-    NRF_GPIO_PIN_DIR_INPUT,   ///< Input
-    NRF_GPIO_PIN_DIR_OUTPUT   ///< Output
-} nrf_gpio_pin_dir_t;
-
-/**
- * @enum nrf_gpio_port_select_t
- * @brief Enumerator used for selecting between port 0 - 3.
- */
-typedef enum
-{
-    NRF_GPIO_PORT_SELECT_PORT0 = 0,           ///<  Port 0 (GPIO pin 0-7)
-    NRF_GPIO_PORT_SELECT_PORT1,               ///<  Port 1 (GPIO pin 8-15)
-    NRF_GPIO_PORT_SELECT_PORT2,               ///<  Port 2 (GPIO pin 16-23)
-    NRF_GPIO_PORT_SELECT_PORT3,               ///<  Port 3 (GPIO pin 24-31)
-} nrf_gpio_port_select_t;
-
-/**
- * @enum nrf_gpio_pin_pull_t
- * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration
- */
-typedef enum
-{
-    NRF_GPIO_PIN_NOPULL   = GPIO_PIN_CNF_PULL_Disabled,                 ///<  Pin pullup resistor disabled
-    NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown,                 ///<  Pin pulldown resistor enabled
-    NRF_GPIO_PIN_PULLUP   = GPIO_PIN_CNF_PULL_Pullup,                   ///<  Pin pullup resistor enabled
-} nrf_gpio_pin_pull_t;
-
-/**
- * @enum nrf_gpio_pin_sense_t
- * @brief Enumerator used for selecting the pin to sense high or low level on the pin input.
- */
-typedef enum
-{
-    NRF_GPIO_PIN_NOSENSE    = GPIO_PIN_CNF_SENSE_Disabled,              ///<  Pin sense level disabled.
-    NRF_GPIO_PIN_SENSE_LOW  = GPIO_PIN_CNF_SENSE_Low,                   ///<  Pin sense low level.
-    NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High,                  ///<  Pin sense high level.
-} nrf_gpio_pin_sense_t;
-
-/**
- * @brief Function for configuring the GPIO pin range as outputs with normal drive strength.
- *        This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
- *
- * @param pin_range_start specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
- *
- * @param pin_range_end specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
- *
- * @note For configuring only one pin as output use @ref nrf_gpio_cfg_output
- *       Sense capability on the pin is disabled, and input is disconnected from the buffer as the pins are configured as output.
- */
-static __INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
-{
-    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
-    for (; pin_range_start <= pin_range_end; pin_range_start++)
-    {
-        NRF_GPIO->PIN_CNF[pin_range_start] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
-                                        | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
-                                        | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
-                                        | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
-                                        | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
-    }
-}
-
-/**
- * @brief Function for configuring the GPIO pin range as inputs with given initial value set, hiding inner details.
- *        This function can be used to configure pin range as simple input.
- *
- * @param pin_range_start specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
- *
- * @param pin_range_end specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
- *
- * @param pull_config State of the pin range pull resistor (no pull, pulled down or pulled high)
- *
- * @note  For configuring only one pin as input use @ref nrf_gpio_cfg_input
- *        Sense capability on the pin is disabled, and input is connected to buffer so that the GPIO->IN register is readable
- */
-static __INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config)
-{
-    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
-    for (; pin_range_start <= pin_range_end; pin_range_start++)
-    {
-        NRF_GPIO->PIN_CNF[pin_range_start] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
-                                        | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
-                                        | (pull_config << GPIO_PIN_CNF_PULL_Pos)
-                                        | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
-                                        | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
-    }
-}
-
-/**
- * @brief Function for configuring the given GPIO pin number as output with given initial value set, hiding inner details.
- *        This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
- *
- * @param pin_number specifies the pin number of gpio pin numbers to be configured (allowed values 0-30)
- *
- * @note  Sense capability on the pin is disabled, and input is disconnected from the buffer as the pins are configured as output.
- */
-static __INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
-{
-    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
-    NRF_GPIO->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
-                                            | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
-                                            | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
-                                            | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
-                                            | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
-}
-
-/**
- * @brief Function for configuring the given GPIO pin number as input with given initial value set, hiding inner details.
- *        This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
- *
- * @param pin_number specifies the pin number of gpio pin numbers to be configured (allowed values 0-30)
- *
- * @param pull_config State of the pin range pull resistor (no pull, pulled down or pulled high)
- *
- * @note  Sense capability on the pin is disabled, and input is connected to buffer so that the GPIO->IN register is readable
- */
-static __INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config)
-{
-    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
-    NRF_GPIO->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
-                                        | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
-                                        | (pull_config << GPIO_PIN_CNF_PULL_Pos)
-                                        | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
-                                        | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
-}
-
-/**
- * @brief Function for configuring the given GPIO pin number as input with given initial value set, hiding inner details.
- *        This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
- *        Sense capability on the pin is configurable, and input is connected to buffer so that the GPIO->IN register is readable.
- *
- * @param pin_number specifies the pin number of gpio pin numbers to be configured (allowed values 0-30).
- *
- * @param pull_config state of the pin pull resistor (no pull, pulled down or pulled high).
- *
- * @param sense_config sense level of the pin (no sense, sense low or sense high).
- */
-static __INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config, nrf_gpio_pin_sense_t sense_config)
-{
-    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
-    NRF_GPIO->PIN_CNF[pin_number] = (sense_config << GPIO_PIN_CNF_SENSE_Pos)
-                                        | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
-                                        | (pull_config << GPIO_PIN_CNF_PULL_Pos)
-                                        | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
-                                        | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
-}
-
-/**
- * @brief Function for setting the direction for a GPIO pin.
- *
- * @param pin_number specifies the pin number [0:31] for which to
- * set the direction.
- *
- * @param direction specifies the direction
- */
-static __INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
-{
-    if(direction == NRF_GPIO_PIN_DIR_INPUT)
-    {
-        NRF_GPIO->PIN_CNF[pin_number] =
-          (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
-        | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
-        | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
-        | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
-        | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
-    }
-    else
-    {
-        NRF_GPIO->DIRSET = (1UL << pin_number);
-    }
-}
-
-/**
- * @brief Function for setting a GPIO pin.
- *
- * Note that the pin must be configured as an output for this
- * function to have any effect.
- *
- * @param pin_number specifies the pin number [0:31] to
- * set.
- */
-static __INLINE void nrf_gpio_pin_set(uint32_t pin_number)
-{
-    NRF_GPIO->OUTSET = (1UL << pin_number);
-}
-
-/**
- * @brief Function for clearing a GPIO pin.
- *
- * Note that the pin must be configured as an output for this
- * function to have any effect.
- *
- * @param pin_number specifies the pin number [0:31] to
- * clear.
- */
-static __INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
-{
-    NRF_GPIO->OUTCLR = (1UL << pin_number);
-}
-
-/**
- * @brief Function for toggling a GPIO pin.
- *
- * Note that the pin must be configured as an output for this
- * function to have any effect.
- *
- * @param pin_number specifies the pin number [0:31] to
- * toggle.
- */
-static __INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
-{
-    const uint32_t pin_bit   = 1UL << pin_number;
-    const uint32_t pin_state = ((NRF_GPIO->OUT >> pin_number) & 1UL);
-    
-    if (pin_state == 0)
-    {
-        // Current state low, set high.
-        NRF_GPIO->OUTSET = pin_bit;        
-    }
-    else
-    {
-        // Current state high, set low.    
-        NRF_GPIO->OUTCLR = pin_bit;       
-    }
-}
-
-/**
- * @brief Function for writing a value to a GPIO pin.
- *
- * Note that the pin must be configured as an output for this
- * function to have any effect.
- *
- * @param pin_number specifies the pin number [0:31] to
- * write.
- *
- * @param value specifies the value to be written to the pin.
- * @arg 0 clears the pin
- * @arg >=1 sets the pin.
- */
-static __INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
-{
-    if (value == 0)
-    {
-        nrf_gpio_pin_clear(pin_number);
-    }
-    else
-    {
-        nrf_gpio_pin_set(pin_number);
-    }
-}
-
-/**
- * @brief Function for reading the input level of a GPIO pin.
- *
- * Note that the pin must have input connected for the value
- * returned from this function to be valid.
- *
- * @param pin_number specifies the pin number [0:31] to
- * read.
- *
- * @return
- * @retval 0 if the pin input level is low.
- * @retval 1 if the pin input level is high.
- * @retval > 1 should never occur.
- */
-static __INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number)
-{
-    return  ((NRF_GPIO->IN >> pin_number) & 1UL);
-}
-
-/**
- * @brief Generic function for writing a single byte of a 32 bit word at a given
- * address.
- *
- * This function should not be called from outside the nrf_gpio
- * abstraction layer.
- *
- * @param word_address is the address of the word to be written.
- *
- * @param byte_no is the the word byte number (0-3) to be written.
- *
- * @param value is the value to be written to byte "byte_no" of word
- * at address "word_address"
- */
-static __INLINE void nrf_gpio_word_byte_write(volatile uint32_t * word_address, uint8_t byte_no, uint8_t value)
-{
-    *((volatile uint8_t*)(word_address) + byte_no) = value;
-}
-
-/**
- * @brief Generic function for reading a single byte of a 32 bit word at a given
- * address.
- *
- * This function should not be called from outside the nrf_gpio
- * abstraction layer.
- *
- * @param word_address is the address of the word to be read.
- *
- * @param byte_no is the the byte number (0-3) of the word to be read.
- *
- * @return byte "byte_no" of word at address "word_address".
- */
-static __INLINE uint8_t nrf_gpio_word_byte_read(const volatile uint32_t* word_address, uint8_t byte_no)
-{
-    return (*((const volatile uint8_t*)(word_address) + byte_no));
-}
-
-/**
- * @brief Function for setting the direction of a port.
- *
- * @param port is the port for which to set the direction.
- *
- * @param dir direction to be set for this port.
- */
-static __INLINE void nrf_gpio_port_dir_set(nrf_gpio_port_select_t port, nrf_gpio_port_dir_t dir)
-{
-    if (dir == NRF_GPIO_PORT_DIR_OUTPUT)
-    {
-        nrf_gpio_word_byte_write(&NRF_GPIO->DIRSET, port, 0xFF);
-    }
-    else
-    {
-        nrf_gpio_range_cfg_input(port*8, (port+1)*8-1, NRF_GPIO_PIN_NOPULL);
-    }
-}
-
-/**
- * @brief Function for reading a GPIO port.
- *
- * @param port is the port to read.
- *
- * @return the input value on this port.
- */
-static __INLINE uint8_t nrf_gpio_port_read(nrf_gpio_port_select_t port)
-{
-    return nrf_gpio_word_byte_read(&NRF_GPIO->IN, port);
-}
-
-/**
- * @brief Function for writing to a GPIO port.
- *
- * @param port is the port to write.
- *
- * @param value is the value to write to this port.
- *
- * @sa nrf_gpio_port_dir_set()
- */
-static __INLINE void nrf_gpio_port_write(nrf_gpio_port_select_t port, uint8_t value)
-{
-    nrf_gpio_word_byte_write(&NRF_GPIO->OUT, port, value);
-}
-
-/**
- * @brief Function for setting individual pins on GPIO port.
- *
- * @param port is the port for which to set the pins.
- *
- * @param set_mask is a mask specifying which pins to set. A bit
- * set to 1 indicates that the corresponding port pin shall be
- * set.
- *
- * @sa nrf_gpio_port_dir_set()
- */
-static __INLINE void nrf_gpio_port_set(nrf_gpio_port_select_t port, uint8_t set_mask)
-{
-    nrf_gpio_word_byte_write(&NRF_GPIO->OUTSET, port, set_mask);
-}
-
-/**
- * @brief Function for clearing individual pins on GPIO port.
- *
- * @param port is the port for which to clear the pins.
- *
- * @param clr_mask is a mask specifying which pins to clear. A bit
- * set to 1 indicates that the corresponding port pin shall be
- * cleared.
- *
- * @sa nrf_gpio_port_dir_set()
- */
-static __INLINE void nrf_gpio_port_clear(nrf_gpio_port_select_t port, uint8_t clr_mask)
-{
-    nrf_gpio_word_byte_write(&NRF_GPIO->OUTCLR, port, clr_mask);
-}
-
-/** @} */
-
-#endif
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_gpiote.h
--- a/nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_gpiote.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,153 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-#ifndef NRF_GPIOTE_H__
-#define NRF_GPIOTE_H__
-
-#include "nrf.h"
-
-/**
-* @defgroup nrf_gpiote GPIOTE abstraction
-* @{
-* @ingroup nrf_drivers
-* @brief GPIOTE abstraction for configuration of channels.
-*/
-
-
- /**
- * @enum nrf_gpiote_polarity_t
- * @brief Polarity for GPIOTE channel enumerator.
- */
-typedef enum
-{
-  NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi,       ///<  Low to high
-  NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo,       ///<  High to low
-  NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle        ///<  Toggle
-} nrf_gpiote_polarity_t;
-
-
- /**
- * @enum nrf_gpiote_outinit_t
- * @brief Initial output value for GPIOTE channel enumerator.
- */
-typedef enum
-{
-  NRF_GPIOTE_INITIAL_VALUE_LOW  = GPIOTE_CONFIG_OUTINIT_Low,       ///<  Low to high
-  NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High       ///<  High to low
-} nrf_gpiote_outinit_t;
-
-
-/**
- * @brief Function for configuring GPIOTE channel as output, setting the properly desired output level.
- *
- *
- * @param channel_number specifies the GPIOTE channel [0:3] to configure as an output channel.
- * @param pin_number specifies the pin number [0:30] to use in the GPIOTE channel.
- * @param polarity specifies the desired polarity in the output GPIOTE channel.
- * @param initial_value specifies the initial value of the GPIOTE channel input after the channel configuration.
- */
-static __INLINE void nrf_gpiote_task_config(uint32_t channel_number, uint32_t pin_number, nrf_gpiote_polarity_t polarity, nrf_gpiote_outinit_t initial_value)
-{
-    /* Check if the output desired is high or low */
-    if (initial_value == NRF_GPIOTE_INITIAL_VALUE_LOW)
-    {
-        /* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens
-        on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the 
-        correct state in GPIOTE but not in the OUT register. */
-        NRF_GPIO->OUTCLR = (1 << pin_number);
-        
-        /* Configure channel to Pin31, not connected to the pin, and configure as a tasks that will set it to proper level */
-        NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task       << GPIOTE_CONFIG_MODE_Pos)     |
-                                             (31UL                          << GPIOTE_CONFIG_PSEL_Pos)     |
-                                             (GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos);                                    
-    } 
-    else 
-    {
-        /* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens
-        on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the 
-        correct state in GPIOTE but not in the OUT register. */
-        NRF_GPIO->OUTSET = (1 << pin_number);
-        
-        /* Configure channel to Pin31, not connected to the pin, and configure as a tasks that will set it to proper level */
-        NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task       << GPIOTE_CONFIG_MODE_Pos)     |
-                                             (31UL                          << GPIOTE_CONFIG_PSEL_Pos)     |
-                                             (GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos);
-    }
-
-    /* Three NOPs are required to make sure configuration is written before setting tasks or getting events */
-    __NOP();
-    __NOP();
-    __NOP(); 
-
-    /* Launch the task to take the GPIOTE channel output to the desired level */
-    NRF_GPIOTE->TASKS_OUT[channel_number] = 1;
-    
-
-    /* Finally configure the channel as the caller expects. If OUTINIT works, the channel is configured properly. 
-       If it does not, the channel output inheritance sets the proper level. */
-    NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos)     |
-                                         ((uint32_t)pin_number    << GPIOTE_CONFIG_PSEL_Pos)     |
-                                         ((uint32_t)polarity      << GPIOTE_CONFIG_POLARITY_Pos) |
-                                         ((uint32_t)initial_value << GPIOTE_CONFIG_OUTINIT_Pos);
-
-    /* Three NOPs are required to make sure configuration is written before setting tasks or getting events */
-    __NOP();
-    __NOP();
-    __NOP(); 
-}
-
-/**
- * @brief Function for configuring GPIOTE channel as input, automatically clearing an event that appears in some cases under configuration.
- *
- * Note that when configuring the channel as input an event might be triggered. Care of disabling interrupts
- * for that channel is left to the user.
- *
- * @param channel_number specifies the GPIOTE channel [0:3] to configure as an input channel.
- * @param pin_number specifies the pin number [0:30] to use in the GPIOTE channel.
- * @param polarity specifies the desired polarity in the output GPIOTE channel.
- */
-static __INLINE void nrf_gpiote_event_config(uint32_t channel_number, uint32_t pin_number, nrf_gpiote_polarity_t polarity)
-{   
-    /* Configure the channel as the caller expects */
-    NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos)     |
-                                         ((uint32_t)pin_number     << GPIOTE_CONFIG_PSEL_Pos)     |
-                                         ((uint32_t)polarity       << GPIOTE_CONFIG_POLARITY_Pos);
-
-    /* Three NOPs are required to make sure configuration is written before setting tasks or getting events */
-    __NOP();
-    __NOP();
-    __NOP();
-    
-    /* Clear the event that appears in some cases */
-    NRF_GPIOTE->EVENTS_IN[channel_number] = 0; 
-}
-
-
-/**
- * @brief Function for unconfiguring GPIOTE channel.
- *
- *
- * Note that when unconfiguring the channel, the pin is configured as GPIO PIN_CNF configuration.
- *
- * @param channel_number specifies the GPIOTE channel [0:3] to unconfigure.
- */
-static __INLINE void nrf_gpiote_unconfig(uint32_t channel_number)
-{   
-    /* Unonfigure the channel as the caller expects */
-    NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Disabled   << GPIOTE_CONFIG_MODE_Pos) |
-                                         (31UL                          << GPIOTE_CONFIG_PSEL_Pos) |
-                                         (GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
-}
-
-
-/** @} */
-
-#endif
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_nvmc.c
--- a/nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_nvmc.c	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,117 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
-*
-* The information contained herein is property of Nordic Semiconductor ASA.
-* Terms and conditions of usage are described in detail in NORDIC
-* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. 
-*
-* Licensees are granted free, non-transferable use of the information. NO
-* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
-* the file.
-*
-* $LastChangedRevision: 17685 $
-*/ 
-
-/** 
- *@file
- *@brief NMVC driver implementation 
- */
-
-#include "stdbool.h"
-#include "nrf.h"
-#include "nrf_nvmc.h"
-
-
-void nrf_nvmc_page_erase(uint32_t address)
-{ 
-  // Enable erase.
-  NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een;
-  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-  {
-  }
-
-  // Erase the page
-  NRF_NVMC->ERASEPAGE = address;
-  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-  {
-  }
-  
-  NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
-  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-  {
-  }
-}
-
-
-void nrf_nvmc_write_byte(uint32_t address, uint8_t value)
-{
-  uint32_t byte_shift = address & (uint32_t)0x03;
-  uint32_t address32 = address & ~byte_shift; // Address to the word this byte is in.
-  uint32_t value32 = (*(uint32_t*)address32 & ~((uint32_t)0xFF << (byte_shift << (uint32_t)3)));
-  value32 = value32 + ((uint32_t)value << (byte_shift << 3));
-
-  // Enable write.
-  NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos);
-  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-  {
-  }
-
-  *(uint32_t*)address32 = value32;
-  while(NRF_NVMC->READY == NVMC_READY_READY_Busy)
-  {
-  }
-
-  NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
-  {
-  }
-}
-
-void nrf_nvmc_write_word(uint32_t address, uint32_t value)
-{
-  // Enable write.
-  NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
-  while (NRF_NVMC->READY == NVMC_READY_READY_Busy){
-  }
-
-  *(uint32_t*)address = value;
-  while (NRF_NVMC->READY == NVMC_READY_READY_Busy){
-  }
-
-  NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
-  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-  {
-  }
-}
-
-void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes)
-{
-  uint32_t i;
-  for(i=0;i<num_bytes;i++)
-  {
-     nrf_nvmc_write_byte(address+i,src[i]);
-  }
-}
-
-void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words)
-{
-  uint32_t i;
-
-  // Enable write.
-  NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
-  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-  {
-  }
-
-  for(i=0;i<num_words;i++)
-  {
-    ((uint32_t*)address)[i] = src[i];
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-    {
-    }
-  }
-
-  NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
-  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
-  {
-  }
-}
-
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_nvmc.h
--- a/nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_nvmc.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,90 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is confidential property of Nordic 
- * Semiconductor ASA.Terms and conditions of usage are described in detail 
- * in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. 
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *              
- * $LastChangedRevision: 17685 $
- */
-
-/**
- * @file
- * @brief NMVC driver API.
- */
-
-#ifndef NRF_NVMC_H__
-#define NRF_NVMC_H__
-
-#include <stdint.h>
-
-
-/**
- * @defgroup nrf_nvmc Non-volatile memory controller
- * @{
- * @ingroup nrf_drivers
- * @brief Driver for the nRF51 NVMC peripheral.
- *
- * This driver allows writing to the non-volatile memory (NVM) regions
- * of the nRF51. In order to write to NVM the controller must be powered
- * on and the relevant page must be erased.
- *
- */
-
-
-/**
- * @brief Erase a page in flash. This is required before writing to any
- * address in the page.
- *
- * @param address Start address of the page. 
- */
-void nrf_nvmc_page_erase(uint32_t address);
-
-
-/**
- * @brief Write a single byte to flash.
- *
- * The function reads the word containing the byte, and then
- * rewrites the entire word.
- *
- * @param address Address to write to.
- * @param value   Value to write.
- */
-void nrf_nvmc_write_byte(uint32_t address , uint8_t value);
-
-
-/**
- * @brief Write a 32-bit word to flash. 
- * @param address Address to write to.
- * @param value   Value to write.
- */
-void nrf_nvmc_write_word(uint32_t address, uint32_t value);
-
-
-/**
- * @brief Write consecutive bytes to flash.
- *
- * @param address   Address to write to.
- * @param src       Pointer to data to copy from.
- * @param num_bytes Number of bytes in src to write.
- */
-void nrf_nvmc_write_bytes(uint32_t  address, const uint8_t * src, uint32_t num_bytes);
-
-
-/**
- * @brief Write consecutive words to flash.
- * 
- * @param address   Address to write to.
- * @param src       Pointer to data to copy from.
- * @param num_words Number of bytes in src to write.
- */
-void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words);
-
-
-#endif // NRF_NVMC_H__
-/** @} */
-
-
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_temp.h
--- a/nRF51822/nordic-sdk/components/drivers_nrf/hal/nrf_temp.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,61 +0,0 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#ifndef NRF_TEMP_H__
-#define NRF_TEMP_H__
-
-#include "nrf51.h"
-
-/**
-* @defgroup nrf_temperature TEMP (temperature) abstraction
-* @{
-* @ingroup nrf_drivers temperature_example
-* @brief Temperature module init and read functions.
-*
-*/
-
-
-
-/**
- * @brief Function for preparing the temp module for temperature measurement.
- *
- * This function initializes the TEMP module and writes to the hidden configuration register.
- * 
- * @param none
- */
-static __INLINE void nrf_temp_init(void)
-{
-    /**@note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module */
-    *(uint32_t *) 0x4000C504 = 0;
-}
-
-
-
-#define MASK_SIGN           (0x00000200UL)
-#define MASK_SIGN_EXTENSION (0xFFFFFC00UL)
-
-/**
- * @brief Function for reading temperature measurement.
- *
- * The function reads the 10 bit 2's complement value and transforms it to a 32 bit 2's complement value.
- * 
- * @param none
- */
-static __INLINE int32_t nrf_temp_read(void)
-{    
-    /**@note Workaround for PAN_028 rev2.0A anomaly 28 - TEMP: Negative measured values are not represented correctly */
-    return ((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP);    
-}
-
-/** @} */
-
-#endif
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/pstorage/config/pstorage_platform.h
--- a/nRF51822/nordic-sdk/components/drivers_nrf/pstorage/config/pstorage_platform.h	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,70 +0,0 @@
-/* Copyright (c)  2013 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
- /** @cond To make doxygen skip this file */
-
-/** @file
- *  This header contains defines with respect persistent storage that are specific to
- *  persistent storage implementation and application use case.
- */
-#ifndef PSTORAGE_PL_H__
-#define PSTORAGE_PL_H__
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif // #ifdef __cplusplus
-
-#define PSTORAGE_FLASH_PAGE_SIZE    ((uint16_t)NRF_FICR->CODEPAGESIZE)   /**< Size of one flash page. */
-#define PSTORAGE_FLASH_EMPTY_MASK    0xFFFFFFFF                          /**< Bit mask that defines an empty address in flash. */
-
-#define PSTORAGE_FLASH_PAGE_END                                     \
-        ((NRF_UICR->BOOTLOADERADDR != PSTORAGE_FLASH_EMPTY_MASK)    \
-        ? (NRF_UICR->BOOTLOADERADDR / PSTORAGE_FLASH_PAGE_SIZE)     \
-        : NRF_FICR->CODESIZE)
-
-
-#define PSTORAGE_MAX_APPLICATIONS   1                                                           /**< Maximum number of applications that can be registered with the module, configurable based on system requirements. */
-#define PSTORAGE_MIN_BLOCK_SIZE     0x0010                                                      /**< Minimum size of block that can be registered with the module. Should be configured based on system requirements, recommendation is not have this value to be at least size of word. */
-
-#define PSTORAGE_DATA_START_ADDR    ((PSTORAGE_FLASH_PAGE_END - PSTORAGE_MAX_APPLICATIONS - 1) \
-                                    * PSTORAGE_FLASH_PAGE_SIZE)                                 /**< Start address for persistent data, configurable according to system requirements. */
-#define PSTORAGE_DATA_END_ADDR      ((PSTORAGE_FLASH_PAGE_END - 1) * PSTORAGE_FLASH_PAGE_SIZE)  /**< End address for persistent data, configurable according to system requirements. */
-#define PSTORAGE_SWAP_ADDR          PSTORAGE_DATA_END_ADDR                                      /**< Top-most page is used as swap area for clear and update. */
-
-#define PSTORAGE_MAX_BLOCK_SIZE     PSTORAGE_FLASH_PAGE_SIZE                                    /**< Maximum size of block that can be registered with the module. Should be configured based on system requirements. And should be greater than or equal to the minimum size. */
-#define PSTORAGE_CMD_QUEUE_SIZE     10                                                          /**< Maximum number of flash access commands that can be maintained by the module for all applications. Configurable. */
-
-
-/** Abstracts persistently memory block identifier. */
-typedef uint32_t pstorage_block_t;
-
-typedef struct
-{
-    uint32_t            module_id;      /**< Module ID.*/
-    pstorage_block_t    block_id;       /**< Block ID.*/
-} pstorage_handle_t;
-
-typedef uint16_t pstorage_size_t;      /** Size of length and offset fields. */
-
-/**@brief Handles Flash Access Result Events. To be called in the system event dispatcher of the application. */
-void pstorage_sys_event_handler (uint32_t sys_evt);
-
-#ifdef __cplusplus
-}
-#endif // #ifdef __cplusplus
-
-#endif // PSTORAGE_PL_H__
-
-/** @} */
-/** @endcond */
\ No newline at end of file
diff -r b61ddbb8528e -r 24e365bd1b97 nRF51822/nordic-sdk/components/drivers_nrf/pstorage/pstorage.c
--- a/nRF51822/nordic-sdk/components/drivers_nrf/pstorage/pstorage.c	Thu Nov 05 02:46:37 2015 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1121 +0,0 @@
-/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
- *
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
- *
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
- *
- */
-
-#include "pstorage.h"
-#include <stdlib.h>
-#include <stdint.h>
-#include <string.h>
-#include "nordic_common.h"
-#include "nrf_error.h"
-#include "nrf_assert.h"
-// #include "nrf.h"
-#include "nrf_soc.h"
-#include "app_util.h"
-
-#define INVALID_OPCODE     0x00                            /**< Invalid op code identifier. */
-#define SOC_MAX_WRITE_SIZE 1024                            /**< Maximum write size allowed for a single call to \ref sd_flash_write as specified in the SoC API. */
-#define RAW_MODE_APP_ID    (PSTORAGE_MAX_APPLICATIONS + 1) /**< Application id for raw mode. */
-
-/**
- * @defgroup api_param_check API Parameters check macros.
- *
- * @details Macros that verify parameters passed to the module in the APIs. These macros
- *          could be mapped to