stm-spirit1-rf-driver - Prototype RF driver for STM Sub-1 GHz RF expansio…

ST » Code » stm-spirit1-rf-driver

Prototype RF driver for STM Sub-1 GHz RF expansion board based on the SPSGRF-868 module for STM32 Nucleo.

Prototype RF Driver for STM Sub-1 GHz RF Expansion Boards based on the SPSGRF-868 and SPSGRF-915 Modules for STM32 Nucleo

Currently supported boards:

X-NUCLEO-IDS01A4

Note, in order to use expansion board X-NUCLEO-IDS01A4 in mbed you need to perform the following HW modifications on the board:

Unmount resistor R4
Mount resistor R7

Furthermore, on some Nucleo development boards (e.g. the NUCLEO_F429ZI), in order to be able to use Ethernet together with these Sub-1 GHz RF expansion boards, you need to compile this driver with macro SPIRIT1_SPI_MOSI=PB_5 defined, while the development board typically requires some HW modification as e.g. described here!

This driver can be used together with the 6LoWPAN stack (a.k.a. Nanostack).

source/libs/spirit1/SPIRIT1_Library/Inc/SPIRIT_Regs.h@67:93bec0baf1de, 2017-07-06 (annotated)

Committer:: Wolfgang Betz
Date:: Thu Jul 06 11:13:31 2017 +0200
Revision:: 67:93bec0baf1de
Parent:: 34:edda6a7238ec

Clarify some comments

Who changed what in which revision?

User	Revision	Line number	New contents of line
Wolfgang Betz	67:93bec0baf1de	1	/**
Wolfgang Betz	67:93bec0baf1de	2	******************************************************************************
Wolfgang Betz	67:93bec0baf1de	3	* @file SPIRIT_Regs.h
Wolfgang Betz	67:93bec0baf1de	4	* @author VMA division - AMS
Wolfgang Betz	67:93bec0baf1de	5	* @version 3.2.2
Wolfgang Betz	67:93bec0baf1de	6	* @date 08-July-2015
Wolfgang Betz	67:93bec0baf1de	7	* @brief This file contains all the SPIRIT registers address and masks.
Wolfgang Betz	67:93bec0baf1de	8	* @details
Wolfgang Betz	67:93bec0baf1de	9	*
Wolfgang Betz	67:93bec0baf1de	10	* @attention
Wolfgang Betz	67:93bec0baf1de	11	*
Wolfgang Betz	67:93bec0baf1de	12	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Wolfgang Betz	67:93bec0baf1de	13	*
Wolfgang Betz	67:93bec0baf1de	14	* Redistribution and use in source and binary forms, with or without modification,
Wolfgang Betz	67:93bec0baf1de	15	* are permitted provided that the following conditions are met:
Wolfgang Betz	67:93bec0baf1de	16	* 1. Redistributions of source code must retain the above copyright notice,
Wolfgang Betz	67:93bec0baf1de	17	* this list of conditions and the following disclaimer.
Wolfgang Betz	67:93bec0baf1de	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
Wolfgang Betz	67:93bec0baf1de	19	* this list of conditions and the following disclaimer in the documentation
Wolfgang Betz	67:93bec0baf1de	20	* and/or other materials provided with the distribution.
Wolfgang Betz	67:93bec0baf1de	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Wolfgang Betz	67:93bec0baf1de	22	* may be used to endorse or promote products derived from this software
Wolfgang Betz	67:93bec0baf1de	23	* without specific prior written permission.
Wolfgang Betz	67:93bec0baf1de	24	*
Wolfgang Betz	67:93bec0baf1de	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Wolfgang Betz	67:93bec0baf1de	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Wolfgang Betz	67:93bec0baf1de	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Wolfgang Betz	67:93bec0baf1de	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Wolfgang Betz	67:93bec0baf1de	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Wolfgang Betz	67:93bec0baf1de	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Wolfgang Betz	67:93bec0baf1de	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Wolfgang Betz	67:93bec0baf1de	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Wolfgang Betz	67:93bec0baf1de	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Wolfgang Betz	67:93bec0baf1de	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Wolfgang Betz	67:93bec0baf1de	35	*
Wolfgang Betz	67:93bec0baf1de	36	******************************************************************************
Wolfgang Betz	67:93bec0baf1de	37	*/
Wolfgang Betz	67:93bec0baf1de	38
Wolfgang Betz	67:93bec0baf1de	39	/* Define to prevent recursive inclusion -------------------------------------*/
Wolfgang Betz	67:93bec0baf1de	40	#ifndef __SPIRIT1_REGS_H
Wolfgang Betz	67:93bec0baf1de	41	#define __SPIRIT1_REGS_H
Wolfgang Betz	67:93bec0baf1de	42
Wolfgang Betz	67:93bec0baf1de	43	#ifdef __cplusplus
Wolfgang Betz	67:93bec0baf1de	44	extern "C" {
Wolfgang Betz	67:93bec0baf1de	45	#endif
Wolfgang Betz	67:93bec0baf1de	46
Wolfgang Betz	67:93bec0baf1de	47	/**
Wolfgang Betz	67:93bec0baf1de	48	* @addtogroup SPIRIT_Registers SPIRIT Registers
Wolfgang Betz	67:93bec0baf1de	49	* @brief Header file containing all the SPIRIT registers address and masks.
Wolfgang Betz	67:93bec0baf1de	50	* @details See the file <i>@ref SPIRIT_Regs.h</i> for more details.
Wolfgang Betz	67:93bec0baf1de	51	* @{
Wolfgang Betz	67:93bec0baf1de	52	*/
Wolfgang Betz	67:93bec0baf1de	53
Wolfgang Betz	67:93bec0baf1de	54	/** @defgroup General_Configuration_Registers
Wolfgang Betz	67:93bec0baf1de	55	* @{
Wolfgang Betz	67:93bec0baf1de	56	*/
Wolfgang Betz	67:93bec0baf1de	57
Wolfgang Betz	67:93bec0baf1de	58	/** @defgroup ANA_FUNC_CONF_1_Register
Wolfgang Betz	67:93bec0baf1de	59	* @{
Wolfgang Betz	67:93bec0baf1de	60	*/
Wolfgang Betz	67:93bec0baf1de	61
Wolfgang Betz	67:93bec0baf1de	62	/**
Wolfgang Betz	67:93bec0baf1de	63	* \brief ANA_FUNC_CONF register 1
Wolfgang Betz	67:93bec0baf1de	64	* \code
Wolfgang Betz	67:93bec0baf1de	65	* Read Write
Wolfgang Betz	67:93bec0baf1de	66	* Default value: 0x0C
Wolfgang Betz	67:93bec0baf1de	67	* 7:5 NUM_EN_PIPES: Number of enabled pipes (starting from Data Pipe 0).
Wolfgang Betz	67:93bec0baf1de	68	* 4:2 GM_CONF[2:0]: Sets the driver gm of the XO at start-up:
Wolfgang Betz	67:93bec0baf1de	69	* GM_CONF2 \| GM_CONF1 \| GM_CONF0 \| GM [mS]
Wolfgang Betz	67:93bec0baf1de	70	* ------------------------------------------
Wolfgang Betz	67:93bec0baf1de	71	* 0 \| 0 \| 0 \| 13.2
Wolfgang Betz	67:93bec0baf1de	72	* 0 \| 0 \| 1 \| 18.2
Wolfgang Betz	67:93bec0baf1de	73	* 0 \| 1 \| 0 \| 21.5
Wolfgang Betz	67:93bec0baf1de	74	* 0 \| 1 \| 1 \| 25.6
Wolfgang Betz	67:93bec0baf1de	75	* 1 \| 0 \| 0 \| 28.8
Wolfgang Betz	67:93bec0baf1de	76	* 1 \| 0 \| 1 \| 33.9
Wolfgang Betz	67:93bec0baf1de	77	* 1 \| 1 \| 0 \| 38.5
Wolfgang Betz	67:93bec0baf1de	78	* 1 \| 1 \| 1 \| 43.0
Wolfgang Betz	67:93bec0baf1de	79	* 1:0 SET_BLD_LVL[1:0]: Sets the Battery Level Detector threshold:
Wolfgang Betz	67:93bec0baf1de	80	* SET_BLD_LVL1 \| SET_BLD_LVL0 \| Threshold [V]
Wolfgang Betz	67:93bec0baf1de	81	* ------------------------------------------
Wolfgang Betz	67:93bec0baf1de	82	* 0 \| 0 \| 2.7
Wolfgang Betz	67:93bec0baf1de	83	* 0 \| 1 \| 2.5
Wolfgang Betz	67:93bec0baf1de	84	* 1 \| 0 \| 2.3
Wolfgang Betz	67:93bec0baf1de	85	* 1 \| 1 \| 2.1
Wolfgang Betz	67:93bec0baf1de	86	* \endcode
Wolfgang Betz	67:93bec0baf1de	87	*/
Wolfgang Betz	67:93bec0baf1de	88
Wolfgang Betz	67:93bec0baf1de	89	#define ANA_FUNC_CONF1_BASE ((uint8_t)0x00) /!< ANA_FUNC_CONF1 Address (R/W) /
Wolfgang Betz	67:93bec0baf1de	90
Wolfgang Betz	67:93bec0baf1de	91	#define ANA_FUNC_CONF1_NUM_PIPES_MASK ((uint8_t)0xE0) /!< Mask for number of enabled pipes/
Wolfgang Betz	67:93bec0baf1de	92
Wolfgang Betz	67:93bec0baf1de	93	#define ANA_FUNC_CONF1_GMCONF_MASK ((uint8_t)0x1C) /!< Mask of the GmConf field of ANA_FUNC_CONF1 register (R/W) /
Wolfgang Betz	67:93bec0baf1de	94
Wolfgang Betz	67:93bec0baf1de	95	#define GM_13_2 ((uint8_t)0x00) /!< Transconducatance Gm at start-up 13.2 mS /
Wolfgang Betz	67:93bec0baf1de	96	#define GM_18_2 ((uint8_t)0x04) /!< Transconducatance Gm at start-up 18.2 mS /
Wolfgang Betz	67:93bec0baf1de	97	#define GM_21_5 ((uint8_t)0x08) /!< Transconducatance Gm at start-up 21.5 mS /
Wolfgang Betz	67:93bec0baf1de	98	#define GM_25_6 ((uint8_t)0x0C) /!< Transconducatance Gm at start-up 25.6 mS /
Wolfgang Betz	67:93bec0baf1de	99	#define GM_28_8 ((uint8_t)0x10) /!< Transconducatance Gm at start-up 28.8 mS /
Wolfgang Betz	67:93bec0baf1de	100	#define GM_33_9 ((uint8_t)0x14) /!< Transconducatance Gm at start-up 33.9 mS /
Wolfgang Betz	67:93bec0baf1de	101	#define GM_38_5 ((uint8_t)0x18) /!< Transconducatance Gm at start-up 38.5 mS /
Wolfgang Betz	67:93bec0baf1de	102	#define GM_43_0 ((uint8_t)0x1C) /!< Transconducatance Gm at start-up 43.0 mS /
Wolfgang Betz	67:93bec0baf1de	103
Wolfgang Betz	67:93bec0baf1de	104	#define ANA_FUNC_CONF1_SET_BLD_LVL_MASK ((uint8_t)0x03) /!< Mask of the SET_BLD_LV field of ANA_FUNC_CONF1 register (R/W) /
Wolfgang Betz	67:93bec0baf1de	105
Wolfgang Betz	67:93bec0baf1de	106	#define BLD_LVL_2_7 ((uint8_t)0x00) /!< Sets the Battery Level Detector threshold to 2.7V /
Wolfgang Betz	67:93bec0baf1de	107	#define BLD_LVL_2_5 ((uint8_t)0x01) /!< Sets the Battery Level Detector threshold to 2.5V /
Wolfgang Betz	67:93bec0baf1de	108	#define BLD_LVL_2_3 ((uint8_t)0x02) /!< Sets the Battery Level Detector threshold to 2.3V /
Wolfgang Betz	67:93bec0baf1de	109	#define BLD_LVL_2_1 ((uint8_t)0x03) /!< Sets the Battery Level Detector threshold to 2.1V /
Wolfgang Betz	67:93bec0baf1de	110
Wolfgang Betz	67:93bec0baf1de	111	/**
Wolfgang Betz	67:93bec0baf1de	112	* @}
Wolfgang Betz	67:93bec0baf1de	113	*/
Wolfgang Betz	67:93bec0baf1de	114
Wolfgang Betz	67:93bec0baf1de	115
Wolfgang Betz	67:93bec0baf1de	116	/** @defgroup ANA_FUNC_CONF_0_Register
Wolfgang Betz	67:93bec0baf1de	117	* @{
Wolfgang Betz	67:93bec0baf1de	118	*/
Wolfgang Betz	67:93bec0baf1de	119
Wolfgang Betz	67:93bec0baf1de	120	/**
Wolfgang Betz	67:93bec0baf1de	121	* \brief ANA_FUNC_CONF register 0
Wolfgang Betz	67:93bec0baf1de	122	* \code
Wolfgang Betz	67:93bec0baf1de	123	* Read Write
Wolfgang Betz	67:93bec0baf1de	124	* Default value: 0xC0
Wolfgang Betz	67:93bec0baf1de	125	* 7 Reserved.
Wolfgang Betz	67:93bec0baf1de	126	* 6 24_26_MHz_SELECT: 1 - 26 MHz configuration
Wolfgang Betz	67:93bec0baf1de	127	* 0 - 24 MHz configuration
Wolfgang Betz	67:93bec0baf1de	128	* 5 AES_ON: 1 - AES engine enabled
Wolfgang Betz	67:93bec0baf1de	129	* 0 - AES engine disabled
Wolfgang Betz	67:93bec0baf1de	130	* 4 EXT_REF: 1 - Reference signal from XIN pin
Wolfgang Betz	67:93bec0baf1de	131	* 0 - Reference signal from XO circuit
Wolfgang Betz	67:93bec0baf1de	132	* 3 HIGH_POWER_MODE: 1 - SET_SMPS_LEVEL word will be set to the value to
Wolfgang Betz	67:93bec0baf1de	133	* PM_TEST register in RX state, while in TX state it
Wolfgang Betz	67:93bec0baf1de	134	* will be fixed to 111 (which programs the SMPS output
Wolfgang Betz	67:93bec0baf1de	135	* at max value 1.8V)
Wolfgang Betz	67:93bec0baf1de	136	* 0 - SET_SMPS_LEVEL word will hold the value written in the
Wolfgang Betz	67:93bec0baf1de	137	* PM_TEST register both in RX and TX state
Wolfgang Betz	67:93bec0baf1de	138	* 2 BROWN_OUT: 1 - Brown_Out Detection enabled
Wolfgang Betz	67:93bec0baf1de	139	* 0 - Brown_Out Detection disabled
Wolfgang Betz	67:93bec0baf1de	140	* 1 BATTERY_LEVEL: 1 - Battery level detector enabled
Wolfgang Betz	67:93bec0baf1de	141	* 0 - Battery level detector disabled
Wolfgang Betz	67:93bec0baf1de	142	* 0 TS: 1 - Enable the "Temperature Sensor" function
Wolfgang Betz	67:93bec0baf1de	143	* 0 - Disable the "Temperature Sensor" function
Wolfgang Betz	67:93bec0baf1de	144	* \endcode
Wolfgang Betz	67:93bec0baf1de	145	*/
Wolfgang Betz	67:93bec0baf1de	146
Wolfgang Betz	67:93bec0baf1de	147
Wolfgang Betz	67:93bec0baf1de	148	#define ANA_FUNC_CONF0_BASE ((uint8_t)0x01) /!< ANA_FUNC_CONF0 Address (R/W) /
Wolfgang Betz	67:93bec0baf1de	149
Wolfgang Betz	67:93bec0baf1de	150	#define SELECT_24_26_MHZ_MASK ((uint8_t)0x40) /!< Configure the RCO if using 26 MHz or 24 MHz master clock/reference signal /
Wolfgang Betz	67:93bec0baf1de	151	#define AES_MASK ((uint8_t)0x20) /!< AES engine on/off /
Wolfgang Betz	67:93bec0baf1de	152	#define EXT_REF_MASK ((uint8_t)0x10) /!< Reference signal from XIN pin (oscillator external) or from XO circuit (oscillator internal)/
Wolfgang Betz	67:93bec0baf1de	153	#define HIGH_POWER_MODE_MASK ((uint8_t)0x08) /*!< SET_SMPS_LEVEL word will be set to the value to PM_TEST register
Wolfgang Betz	67:93bec0baf1de	154	in RX state, while in TX state it will be fixed to 111
Wolfgang Betz	67:93bec0baf1de	155	(which programs the SMPS output at max value, 1.8V) */
Wolfgang Betz	67:93bec0baf1de	156	#define BROWN_OUT_MASK ((uint8_t)0x04) /!< Accurate Brown-Out detection on/off /
Wolfgang Betz	67:93bec0baf1de	157	#define BATTERY_LEVEL_MASK ((uint8_t)0x02) /!< Battery level detector circuit on/off /
Wolfgang Betz	67:93bec0baf1de	158	#define TEMPERATURE_SENSOR_MASK ((uint8_t)0x01) /!< The Temperature Sensor (available on GPIO0) on/off /
Wolfgang Betz	67:93bec0baf1de	159
Wolfgang Betz	67:93bec0baf1de	160	/**
Wolfgang Betz	67:93bec0baf1de	161	* @}
Wolfgang Betz	67:93bec0baf1de	162	*/
Wolfgang Betz	67:93bec0baf1de	163
Wolfgang Betz	67:93bec0baf1de	164	/** @defgroup ANT_SELECT_CONF_Register
Wolfgang Betz	67:93bec0baf1de	165	* @{
Wolfgang Betz	67:93bec0baf1de	166	*/
Wolfgang Betz	67:93bec0baf1de	167
Wolfgang Betz	67:93bec0baf1de	168	/**
Wolfgang Betz	67:93bec0baf1de	169	* \brief ANT_SELECT_CONF register
Wolfgang Betz	67:93bec0baf1de	170	* \code
Wolfgang Betz	67:93bec0baf1de	171	* Read Write
Wolfgang Betz	67:93bec0baf1de	172	* Default value: 0x05
Wolfgang Betz	67:93bec0baf1de	173	*
Wolfgang Betz	67:93bec0baf1de	174	* 7:5 Reserved.
Wolfgang Betz	67:93bec0baf1de	175	*
Wolfgang Betz	67:93bec0baf1de	176	* 4 CS_BLANKING: Blank received data if signal is below the CS threshold
Wolfgang Betz	67:93bec0baf1de	177	*
Wolfgang Betz	67:93bec0baf1de	178	* 3 AS_ENABLE: Enable antenna switching
Wolfgang Betz	67:93bec0baf1de	179	* 1 - Enable
Wolfgang Betz	67:93bec0baf1de	180	* 0 - Disable
Wolfgang Betz	67:93bec0baf1de	181	*
Wolfgang Betz	67:93bec0baf1de	182	* 2:0 AS_MEAS_TIME[2:0]: Measurement time according to the formula Tmeas = 242^(EchFlt)2^AS_MEAS_TIME/fxo
Wolfgang Betz	67:93bec0baf1de	183	* \endcode
Wolfgang Betz	67:93bec0baf1de	184	*/
Wolfgang Betz	67:93bec0baf1de	185	#define ANT_SELECT_CONF_BASE ((uint8_t)0x27) /!< Antenna diversity (works only in static carrier sense mode) /
Wolfgang Betz	67:93bec0baf1de	186	#define ANT_SELECT_CS_BLANKING_MASK ((uint8_t)0x10) /!< CS data blanking on/off /
Wolfgang Betz	67:93bec0baf1de	187	#define ANT_SELECT_CONF_AS_MASK ((uint8_t)0x08) /!< Antenna diversity on/off /
Wolfgang Betz	67:93bec0baf1de	188
Wolfgang Betz	67:93bec0baf1de	189	/**
Wolfgang Betz	67:93bec0baf1de	190	* @}
Wolfgang Betz	67:93bec0baf1de	191	*/
Wolfgang Betz	67:93bec0baf1de	192
Wolfgang Betz	67:93bec0baf1de	193	/** @defgroup DEVICE_INFO1_Register
Wolfgang Betz	67:93bec0baf1de	194	* @{
Wolfgang Betz	67:93bec0baf1de	195	*/
Wolfgang Betz	67:93bec0baf1de	196
Wolfgang Betz	67:93bec0baf1de	197	/**
Wolfgang Betz	67:93bec0baf1de	198	* \brief DEVICE_INFO1[7:0] registers
Wolfgang Betz	67:93bec0baf1de	199	* \code
Wolfgang Betz	67:93bec0baf1de	200	* Default value: 0x01
Wolfgang Betz	67:93bec0baf1de	201	* Read
Wolfgang Betz	67:93bec0baf1de	202	*
Wolfgang Betz	67:93bec0baf1de	203	* 7:0 PARTNUM[7:0]: Device part number
Wolfgang Betz	67:93bec0baf1de	204	* \endcode
Wolfgang Betz	67:93bec0baf1de	205	*/
Wolfgang Betz	67:93bec0baf1de	206	#define DEVICE_INFO1_PARTNUM ((uint8_t)(0xF0)) /!< Device part number [7:0] /
Wolfgang Betz	67:93bec0baf1de	207
Wolfgang Betz	67:93bec0baf1de	208	/**
Wolfgang Betz	67:93bec0baf1de	209	* @}
Wolfgang Betz	67:93bec0baf1de	210	*/
Wolfgang Betz	67:93bec0baf1de	211
Wolfgang Betz	67:93bec0baf1de	212	/** @defgroup DEVICE_INFO0_Register
Wolfgang Betz	67:93bec0baf1de	213	* @{
Wolfgang Betz	67:93bec0baf1de	214	*/
Wolfgang Betz	67:93bec0baf1de	215
Wolfgang Betz	67:93bec0baf1de	216	/**
Wolfgang Betz	67:93bec0baf1de	217	* \brief DEVICE_INFO0[7:0] registers
Wolfgang Betz	67:93bec0baf1de	218	* \code
Wolfgang Betz	67:93bec0baf1de	219	* Read
Wolfgang Betz	67:93bec0baf1de	220	*
Wolfgang Betz	67:93bec0baf1de	221	* 7:0 VERSION[7:0]: Device version number
Wolfgang Betz	67:93bec0baf1de	222	* \endcode
Wolfgang Betz	67:93bec0baf1de	223	*/
Wolfgang Betz	67:93bec0baf1de	224	#define DEVICE_INFO0_VERSION ((uint8_t)(0xF1)) /!< Device version [7:0]; (0x55 in CUT1.0) /
Wolfgang Betz	67:93bec0baf1de	225
Wolfgang Betz	67:93bec0baf1de	226	/**
Wolfgang Betz	67:93bec0baf1de	227	* @}
Wolfgang Betz	67:93bec0baf1de	228	*/
Wolfgang Betz	67:93bec0baf1de	229
Wolfgang Betz	67:93bec0baf1de	230
Wolfgang Betz	67:93bec0baf1de	231	/**
Wolfgang Betz	67:93bec0baf1de	232	* @}
Wolfgang Betz	67:93bec0baf1de	233	*/
Wolfgang Betz	67:93bec0baf1de	234
Wolfgang Betz	67:93bec0baf1de	235
Wolfgang Betz	67:93bec0baf1de	236	/** @defgroup GPIO_Registers
Wolfgang Betz	67:93bec0baf1de	237	* @{
Wolfgang Betz	67:93bec0baf1de	238	*/
Wolfgang Betz	67:93bec0baf1de	239
Wolfgang Betz	67:93bec0baf1de	240	/** @defgroup GPIOx_CONF_Registers
Wolfgang Betz	67:93bec0baf1de	241	* @{
Wolfgang Betz	67:93bec0baf1de	242	*/
Wolfgang Betz	67:93bec0baf1de	243
Wolfgang Betz	67:93bec0baf1de	244	/**
Wolfgang Betz	67:93bec0baf1de	245	* \brief GPIOx registers
Wolfgang Betz	67:93bec0baf1de	246	* \code
Wolfgang Betz	67:93bec0baf1de	247	* Read Write
Wolfgang Betz	67:93bec0baf1de	248	* Default value: 0x03
Wolfgang Betz	67:93bec0baf1de	249	* 7:3 GPIO_SELECT[4:0]: Specify the I/O signal.
Wolfgang Betz	67:93bec0baf1de	250	* GPIO_SELECT[4:0] \| I/O \| Signal
Wolfgang Betz	67:93bec0baf1de	251	* ------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	252	* 0 \| Output \| nIRQ
Wolfgang Betz	67:93bec0baf1de	253	* 0 \| Input \| TX command
Wolfgang Betz	67:93bec0baf1de	254	* 1 \| Output \| POR inverted
Wolfgang Betz	67:93bec0baf1de	255	* 1 \| Input \| RX command
Wolfgang Betz	67:93bec0baf1de	256	* 2 \| Output \| Wake-Up timer expiration
Wolfgang Betz	67:93bec0baf1de	257	* 2 \| Input \| TX data for direct modulation
Wolfgang Betz	67:93bec0baf1de	258	* 3 \| Output \| Low Battery Detection
Wolfgang Betz	67:93bec0baf1de	259	* 3 \| Input \| Wake-up from external input
Wolfgang Betz	67:93bec0baf1de	260	* 4 \| Output \| TX clock output
Wolfgang Betz	67:93bec0baf1de	261	* 5 \| Output \| TX state
Wolfgang Betz	67:93bec0baf1de	262	* 6 \| Output \| TX FIFO Almost Empty Flag
Wolfgang Betz	67:93bec0baf1de	263	* 7 \| Output \| TX FIFO ALmost Full Flag
Wolfgang Betz	67:93bec0baf1de	264	* 8 \| Output \| RX data output
Wolfgang Betz	67:93bec0baf1de	265	* 9 \| Output \| RX clock output
Wolfgang Betz	67:93bec0baf1de	266	* 10 \| Output \| RX state
Wolfgang Betz	67:93bec0baf1de	267	* 11 \| Output \| RX FIFO Almost Full Flag
Wolfgang Betz	67:93bec0baf1de	268	* 12 \| Output \| RX FIFO Almost Empty Flag
Wolfgang Betz	67:93bec0baf1de	269	* 13 \| Output \| Antenna switch
Wolfgang Betz	67:93bec0baf1de	270	* 14 \| Output \| Valid preamble detected
Wolfgang Betz	67:93bec0baf1de	271	* 15 \| Output \| Sync word detected
Wolfgang Betz	67:93bec0baf1de	272	* 16 \| Output \| RSSI above threshold
Wolfgang Betz	67:93bec0baf1de	273	* 17 \| Output \| MCU clock
Wolfgang Betz	67:93bec0baf1de	274	* 18 \| Output \| TX or RX mode indicator
Wolfgang Betz	67:93bec0baf1de	275	* 19 \| Output \| VDD
Wolfgang Betz	67:93bec0baf1de	276	* 20 \| Output \| GND
Wolfgang Betz	67:93bec0baf1de	277	* 21 \| Output \| External SMPS enable signal
Wolfgang Betz	67:93bec0baf1de	278	* 22-31 \| Not Used \| Not Used
Wolfgang Betz	67:93bec0baf1de	279	* 2 Reserved
Wolfgang Betz	67:93bec0baf1de	280	* 1:0 GpioMode[1:0]: Specify the mode:
Wolfgang Betz	67:93bec0baf1de	281	* GPIO_MODE1 \| GPIO_MODE0 \| MODE
Wolfgang Betz	67:93bec0baf1de	282	* ------------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	283	* 0 \| 0 \| Analog (valid only for GPIO_0)
Wolfgang Betz	67:93bec0baf1de	284	* 0 \| 1 \| Digital Input
Wolfgang Betz	67:93bec0baf1de	285	* 1 \| 0 \| Digital Output Low Power
Wolfgang Betz	67:93bec0baf1de	286	* 1 \| 1 \| Digital Output High Power
Wolfgang Betz	67:93bec0baf1de	287	*
Wolfgang Betz	67:93bec0baf1de	288	* Note: The Analog mode is used only for temperature sensor indication. This is available only
Wolfgang Betz	67:93bec0baf1de	289	* on GPIO_0 by setting the TS bit in the ANA_FUNC_CONF_0_Register.
Wolfgang Betz	67:93bec0baf1de	290	* \endcode
Wolfgang Betz	67:93bec0baf1de	291	*/
Wolfgang Betz	67:93bec0baf1de	292
Wolfgang Betz	67:93bec0baf1de	293
Wolfgang Betz	67:93bec0baf1de	294	#define GPIO3_CONF_BASE ((uint8_t)0x02) /!< GPIO_3 register address /
Wolfgang Betz	67:93bec0baf1de	295	#define GPIO2_CONF_BASE ((uint8_t)0x03) /!< GPIO_3 register address /
Wolfgang Betz	67:93bec0baf1de	296	#define GPIO1_CONF_BASE ((uint8_t)0x04) /!< GPIO_3 register address /
Wolfgang Betz	67:93bec0baf1de	297	#define GPIO0_CONF_BASE ((uint8_t)0x05) /!< GPIO_3 register address /
Wolfgang Betz	67:93bec0baf1de	298
Wolfgang Betz	67:93bec0baf1de	299	#define CONF_GPIO_IN_TX_Command ((uint8_t)0x00) /!< TX command direct from PIN (rising edge, width min=50ns) /
Wolfgang Betz	67:93bec0baf1de	300	#define CONF_GPIO_IN_RX_Command ((uint8_t)0x08) /!< RX command direct from PIN (rising edge, width min=50ns)/
Wolfgang Betz	67:93bec0baf1de	301	#define CONF_GPIO_IN_TX_Data ((uint8_t)0x10) /!< TX data input for direct modulation /
Wolfgang Betz	67:93bec0baf1de	302	#define CONF_GPIO_IN_WKUP_Ext ((uint8_t)0x18) /!< Wake up from external input /
Wolfgang Betz	67:93bec0baf1de	303
Wolfgang Betz	67:93bec0baf1de	304	#define CONF_GPIO_OUT_nIRQ ((uint8_t)0x00) /!< nIRQ (Interrupt Request, active low) , default configuration after POR /
Wolfgang Betz	67:93bec0baf1de	305	#define CONF_GPIO_OUT_POR_Inv ((uint8_t)0x08) /!< POR inverted (active low) /
Wolfgang Betz	67:93bec0baf1de	306	#define CONF_GPIO_OUT_WUT_Exp ((uint8_t)0x10) /!< Wake-Up Timer expiration: 1 when WUT has expired /
Wolfgang Betz	67:93bec0baf1de	307	#define CONF_GPIO_OUT_LBD ((uint8_t)0x18) /!< Low battery detection: 1 when battery is below threshold setting /
Wolfgang Betz	67:93bec0baf1de	308	#define CONF_GPIO_OUT_TX_Data ((uint8_t)0x20) /!< TX data internal clock output (TX data are sampled on the rising edge of it) /
Wolfgang Betz	67:93bec0baf1de	309	#define CONF_GPIO_OUT_TX_State ((uint8_t)0x28) /!< TX state indication: 1 when Spirit1 is transiting in the TX state /
Wolfgang Betz	67:93bec0baf1de	310	#define CONF_GPIO_OUT_TX_FIFO_Almost_Empty ((uint8_t)0x30) /!< TX FIFO Almost Empty Flag /
Wolfgang Betz	67:93bec0baf1de	311	#define CONF_GPIO_OUT_TX_FIFO_Amost_Full ((uint8_t)0x38) /!< TX FIFO Almost Full Flag /
Wolfgang Betz	67:93bec0baf1de	312	#define CONF_GPIO_OUT_RX_Data ((uint8_t)0x40) /!< RX data output /
Wolfgang Betz	67:93bec0baf1de	313	#define CONF_GPIO_OUT_RX_Clock ((uint8_t)0x48) /!< RX clock output (recovered from received data) /
Wolfgang Betz	67:93bec0baf1de	314	#define CONF_GPIO_OUT_RX_State ((uint8_t)0x50) /!< RX state indication: 1 when Spirit1 is transiting in the RX state /
Wolfgang Betz	67:93bec0baf1de	315	#define CONF_GPIO_OUT_RX_FIFO_Almost_Full ((uint8_t)0x58) /!< RX FIFO Almost Full Flag /
Wolfgang Betz	67:93bec0baf1de	316	#define CONF_GPIO_OUT_RX_FIFO_Almost_Empty ((uint8_t)0x60) /!< RX FIFO Almost Empty Flag /
Wolfgang Betz	67:93bec0baf1de	317	#define CONF_GPIO_OUT_Antenna_Switch ((uint8_t)0x68) /!< Antenna switch used for antenna diversity /
Wolfgang Betz	67:93bec0baf1de	318	#define CONF_GPIO_OUT_Valid_Preamble ((uint8_t)0x70) /!< Valid Preamble Detected Flag /
Wolfgang Betz	67:93bec0baf1de	319	#define CONF_GPIO_OUT_Sync_Detected ((uint8_t)0x78) /!< Sync WordSync Word Detected Flag /
Wolfgang Betz	67:93bec0baf1de	320	#define CONF_GPIO_OUT_RSSI_Threshold ((uint8_t)0x80) /!< CCA Assessment Flag /
Wolfgang Betz	67:93bec0baf1de	321	#define CONF_GPIO_OUT_MCU_Clock ((uint8_t)0x88) /!< MCU Clock /
Wolfgang Betz	67:93bec0baf1de	322	#define CONF_GPIO_OUT_TX_RX_Mode ((uint8_t)0x90) /!< TX or RX mode indicator (to enable an external range extender) /
Wolfgang Betz	67:93bec0baf1de	323	#define CONF_GPIO_OUT_VDD ((uint8_t)0x98) /!< VDD (to emulate an additional GPIO of the MCU, programmable by SPI) /
Wolfgang Betz	67:93bec0baf1de	324	#define CONF_GPIO_OUT_GND ((uint8_t)0xA0) /!< GND (to emulate an additional GPIO of the MCU, programmable by SPI) /
Wolfgang Betz	67:93bec0baf1de	325	#define CONF_GPIO_OUT_SMPS_Ext ((uint8_t)0xA8) /!< External SMPS enable signal (active high) /
Wolfgang Betz	67:93bec0baf1de	326
Wolfgang Betz	67:93bec0baf1de	327	#define CONF_GPIO_MODE_ANALOG ((uint8_t)0x00) /!< Analog test BUS on GPIO; used only in test mode (except for temperature sensor) /
Wolfgang Betz	67:93bec0baf1de	328	#define CONF_GPIO_MODE_DIG_IN ((uint8_t)0x01) /!< Digital Input on GPIO /
Wolfgang Betz	67:93bec0baf1de	329	#define CONF_GPIO_MODE_DIG_OUTL ((uint8_t)0x02) /!< Digital Output on GPIO (low current) /
Wolfgang Betz	67:93bec0baf1de	330	#define CONF_GPIO_MODE_DIG_OUTH ((uint8_t)0x03) /!< Digital Output on GPIO (high current) /
Wolfgang Betz	67:93bec0baf1de	331
Wolfgang Betz	67:93bec0baf1de	332	/**
Wolfgang Betz	67:93bec0baf1de	333	* @}
Wolfgang Betz	67:93bec0baf1de	334	*/
Wolfgang Betz	67:93bec0baf1de	335
Wolfgang Betz	67:93bec0baf1de	336
Wolfgang Betz	67:93bec0baf1de	337	/** @defgroup MCU_CK_CONF_Register
Wolfgang Betz	67:93bec0baf1de	338	* @{
Wolfgang Betz	67:93bec0baf1de	339	*/
Wolfgang Betz	67:93bec0baf1de	340
Wolfgang Betz	67:93bec0baf1de	341	/**
Wolfgang Betz	67:93bec0baf1de	342	* \brief MCU_CK_CONF register
Wolfgang Betz	67:93bec0baf1de	343	* \code
Wolfgang Betz	67:93bec0baf1de	344	* Read Write
Wolfgang Betz	67:93bec0baf1de	345	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	346	* 7 Reserved.
Wolfgang Betz	67:93bec0baf1de	347	* 6:5 CLOCK_TAIL[1:0]: Specifies the number of extra cylces provided before entering in STANDBY state.
Wolfgang Betz	67:93bec0baf1de	348	* CLOCK_TAIL1 \| CLOCK_TAIL0 \| Number of Extra Cycles
Wolfgang Betz	67:93bec0baf1de	349	* ------------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	350	* 0 \| 0 \| 0
Wolfgang Betz	67:93bec0baf1de	351	* 0 \| 1 \| 64
Wolfgang Betz	67:93bec0baf1de	352	* 1 \| 0 \| 256
Wolfgang Betz	67:93bec0baf1de	353	* 1 \| 1 \| 512
Wolfgang Betz	67:93bec0baf1de	354	* 4:1 XO_RATIO[3:0]: Specifies the division ratio when XO oscillator is the clock source
Wolfgang Betz	67:93bec0baf1de	355	* XO_RATIO[3:0] \| Division Ratio
Wolfgang Betz	67:93bec0baf1de	356	* -----------------------------------
Wolfgang Betz	67:93bec0baf1de	357	* 0 \| 1
Wolfgang Betz	67:93bec0baf1de	358	* 1 \| 2/3
Wolfgang Betz	67:93bec0baf1de	359	* 2 \| 1/2
Wolfgang Betz	67:93bec0baf1de	360	* 3 \| 1/3
Wolfgang Betz	67:93bec0baf1de	361	* 4 \| 1/4
Wolfgang Betz	67:93bec0baf1de	362	* 5 \| 1/6
Wolfgang Betz	67:93bec0baf1de	363	* 6 \| 1/8
Wolfgang Betz	67:93bec0baf1de	364	* 7 \| 1/12
Wolfgang Betz	67:93bec0baf1de	365	* 8 \| 1/16
Wolfgang Betz	67:93bec0baf1de	366	* 9 \| 1/24
Wolfgang Betz	67:93bec0baf1de	367	* 10 \| 1/36
Wolfgang Betz	67:93bec0baf1de	368	* 11 \| 1/48
Wolfgang Betz	67:93bec0baf1de	369	* 12 \| 1/64
Wolfgang Betz	67:93bec0baf1de	370	* 13 \| 1/96
Wolfgang Betz	67:93bec0baf1de	371	* 14 \| 1/128
Wolfgang Betz	67:93bec0baf1de	372	* 15 \| 1/256
Wolfgang Betz	67:93bec0baf1de	373	* 0 RCO_RATIO: Specifies the divsion ratio when RC oscillator is the clock source
Wolfgang Betz	67:93bec0baf1de	374	* 0 - Division Ratio equal to 0
Wolfgang Betz	67:93bec0baf1de	375	* 1 - Division Ratio equal to 1/128
Wolfgang Betz	67:93bec0baf1de	376	* \endcode
Wolfgang Betz	67:93bec0baf1de	377	*/
Wolfgang Betz	67:93bec0baf1de	378
Wolfgang Betz	67:93bec0baf1de	379
Wolfgang Betz	67:93bec0baf1de	380	#define MCU_CK_CONF_BASE ((uint8_t)0x06) /!< MCU Clock Config register address /
Wolfgang Betz	67:93bec0baf1de	381
Wolfgang Betz	67:93bec0baf1de	382	#define MCU_CK_ENABLE ((uint8_t)0x80) /!< MCU clock enable bit /
Wolfgang Betz	67:93bec0baf1de	383
Wolfgang Betz	67:93bec0baf1de	384	#define MCU_CK_CONF_CLOCK_TAIL_0 ((uint8_t)0x00) /!< 0 extra clock cycles provided to the MCU before switching to STANDBY state /
Wolfgang Betz	67:93bec0baf1de	385	#define MCU_CK_CONF_CLOCK_TAIL_64 ((uint8_t)0x20) /!< 64 extra clock cycles provided to the MCU before switching to STANDBY state /
Wolfgang Betz	67:93bec0baf1de	386	#define MCU_CK_CONF_CLOCK_TAIL_256 ((uint8_t)0x40) /!< 256 extra clock cycles provided to the MCU before switching to STANDBY state /
Wolfgang Betz	67:93bec0baf1de	387	#define MCU_CK_CONF_CLOCK_TAIL_512 ((uint8_t)0x60) /!< 512 extra clock cycles provided to the MCU before switching to STANDBY state /
Wolfgang Betz	67:93bec0baf1de	388	#define MCU_CK_CONF_XO_RATIO_1 ((uint8_t)0x00) /!< XO Clock signal available on the GPIO divided by 1 /
Wolfgang Betz	67:93bec0baf1de	389	#define MCU_CK_CONF_XO_RATIO_2_3 ((uint8_t)0x02) /!< XO Clock signal available on the GPIO divided by 2/3 /
Wolfgang Betz	67:93bec0baf1de	390	#define MCU_CK_CONF_XO_RATIO_1_2 ((uint8_t)0x04) /!< XO Clock signal available on the GPIO divided by 1/2 /
Wolfgang Betz	67:93bec0baf1de	391	#define MCU_CK_CONF_XO_RATIO_1_3 ((uint8_t)0x06) /!< XO Clock signal available on the GPIO divided by 1/3 /
Wolfgang Betz	67:93bec0baf1de	392	#define MCU_CK_CONF_XO_RATIO_1_4 ((uint8_t)0x08) /!< XO Clock signal available on the GPIO divided by 1/4 /
Wolfgang Betz	67:93bec0baf1de	393	#define MCU_CK_CONF_XO_RATIO_1_6 ((uint8_t)0x0A) /!< XO Clock signal available on the GPIO divided by 1/6 /
Wolfgang Betz	67:93bec0baf1de	394	#define MCU_CK_CONF_XO_RATIO_1_8 ((uint8_t)0x0C) /!< XO Clock signal available on the GPIO divided by 1/8 /
Wolfgang Betz	67:93bec0baf1de	395	#define MCU_CK_CONF_XO_RATIO_1_12 ((uint8_t)0x0E) /!< XO Clock signal available on the GPIO divided by 1/12 /
Wolfgang Betz	67:93bec0baf1de	396	#define MCU_CK_CONF_XO_RATIO_1_16 ((uint8_t)0x10) /!< XO Clock signal available on the GPIO divided by 1/16 /
Wolfgang Betz	67:93bec0baf1de	397	#define MCU_CK_CONF_XO_RATIO_1_24 ((uint8_t)0x12) /!< XO Clock signal available on the GPIO divided by 1/24 /
Wolfgang Betz	67:93bec0baf1de	398	#define MCU_CK_CONF_XO_RATIO_1_36 ((uint8_t)0x14) /!< XO Clock signal available on the GPIO divided by 1/36 /
Wolfgang Betz	67:93bec0baf1de	399	#define MCU_CK_CONF_XO_RATIO_1_48 ((uint8_t)0x16) /!< XO Clock signal available on the GPIO divided by 1/48 /
Wolfgang Betz	67:93bec0baf1de	400	#define MCU_CK_CONF_XO_RATIO_1_64 ((uint8_t)0x18) /!< XO Clock signal available on the GPIO divided by 1/64 /
Wolfgang Betz	67:93bec0baf1de	401	#define MCU_CK_CONF_XO_RATIO_1_96 ((uint8_t)0x1A) /!< XO Clock signal available on the GPIO divided by 1/96 /
Wolfgang Betz	67:93bec0baf1de	402	#define MCU_CK_CONF_XO_RATIO_1_128 ((uint8_t)0x1C) /!< XO Clock signal available on the GPIO divided by 1/128 /
Wolfgang Betz	67:93bec0baf1de	403	#define MCU_CK_CONF_XO_RATIO_1_192 ((uint8_t)0x1E) /!< XO Clock signal available on the GPIO divided by 1/196 /
Wolfgang Betz	67:93bec0baf1de	404	#define MCU_CK_CONF_RCO_RATIO_1 ((uint8_t)0x00) /!< RCO Clock signal available on the GPIO divided by 1 /
Wolfgang Betz	67:93bec0baf1de	405	#define MCU_CK_CONF_RCO_RATIO_1_128 ((uint8_t)0x01) /!< RCO Clock signal available on the GPIO divided by 1/128/
Wolfgang Betz	67:93bec0baf1de	406
Wolfgang Betz	67:93bec0baf1de	407	/**
Wolfgang Betz	67:93bec0baf1de	408	* @}
Wolfgang Betz	67:93bec0baf1de	409	*/
Wolfgang Betz	67:93bec0baf1de	410
Wolfgang Betz	67:93bec0baf1de	411	/**
Wolfgang Betz	67:93bec0baf1de	412	* @}
Wolfgang Betz	67:93bec0baf1de	413	*/
Wolfgang Betz	67:93bec0baf1de	414
Wolfgang Betz	67:93bec0baf1de	415
Wolfgang Betz	67:93bec0baf1de	416	/** @defgroup Radio_Configuration_Registers
Wolfgang Betz	67:93bec0baf1de	417	* @{
Wolfgang Betz	67:93bec0baf1de	418	*/
Wolfgang Betz	67:93bec0baf1de	419
Wolfgang Betz	67:93bec0baf1de	420
Wolfgang Betz	67:93bec0baf1de	421
Wolfgang Betz	67:93bec0baf1de	422	/** @defgroup SYNT3_Register
Wolfgang Betz	67:93bec0baf1de	423	* @{
Wolfgang Betz	67:93bec0baf1de	424	*/
Wolfgang Betz	67:93bec0baf1de	425
Wolfgang Betz	67:93bec0baf1de	426	/**
Wolfgang Betz	67:93bec0baf1de	427	* \brief SYNT3 register
Wolfgang Betz	67:93bec0baf1de	428	* \code
Wolfgang Betz	67:93bec0baf1de	429	* Read Write
Wolfgang Betz	67:93bec0baf1de	430	* Default value: 0x0C
Wolfgang Betz	67:93bec0baf1de	431	*
Wolfgang Betz	67:93bec0baf1de	432	* 7:5 WCP[2:0]: Set the charge pump current according to the VCO frequency in RX mode.
Wolfgang Betz	67:93bec0baf1de	433	*
Wolfgang Betz	67:93bec0baf1de	434	* VCO Frequency \| WCP2 \| WCP1 \| WCP0 \| Charge Pump Current (uA)
Wolfgang Betz	67:93bec0baf1de	435	* ------------------------------------------------------------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	436	* 4644-4678 \| 0 \| 0 \| 0 \| 378.4
Wolfgang Betz	67:93bec0baf1de	437	* 4708-4772 \| 0 \| 0 \| 1 \| 368.9
Wolfgang Betz	67:93bec0baf1de	438	* 4772-4836 \| 0 \| 1 \| 0 \| 359.5
Wolfgang Betz	67:93bec0baf1de	439	* 4836-4902 \| 0 \| 1 \| 1 \| 350
Wolfgang Betz	67:93bec0baf1de	440	* 4902-4966 \| 1 \| 0 \| 0 \| 340.5
Wolfgang Betz	67:93bec0baf1de	441	* 4966-5030 \| 1 \| 0 \| 1 \| 331.1
Wolfgang Betz	67:93bec0baf1de	442	* 5030-5095 \| 1 \| 1 \| 0 \| 321.6
Wolfgang Betz	67:93bec0baf1de	443	* 5095-5161 \| 1 \| 1 \| 1 \| 312.2
Wolfgang Betz	67:93bec0baf1de	444	* 5161-5232 \| 0 \| 0 \| 0 \| 378.4
Wolfgang Betz	67:93bec0baf1de	445	* 5232-5303 \| 0 \| 0 \| 1 \| 368.9
Wolfgang Betz	67:93bec0baf1de	446	* 5303-5375 \| 0 \| 1 \| 0 \| 359.5
Wolfgang Betz	67:93bec0baf1de	447	* 5375-5448 \| 0 \| 1 \| 1 \| 350
Wolfgang Betz	67:93bec0baf1de	448	* 5448-5519 \| 1 \| 0 \| 0 \| 340.5
Wolfgang Betz	67:93bec0baf1de	449	* 5519-5592 \| 1 \| 0 \| 1 \| 331.1
Wolfgang Betz	67:93bec0baf1de	450	* 5592-5663 \| 1 \| 1 \| 0 \| 321.6
Wolfgang Betz	67:93bec0baf1de	451	* 5663-5736 \| 1 \| 1 \| 1 \| 312.2
Wolfgang Betz	67:93bec0baf1de	452	*
Wolfgang Betz	67:93bec0baf1de	453	*
Wolfgang Betz	67:93bec0baf1de	454	* 4:0 SYNT[25:21]: highest 5 bits of the PLL programmable divider
Wolfgang Betz	67:93bec0baf1de	455	* The valid range depends on fXO and REFDIV settings; for
Wolfgang Betz	67:93bec0baf1de	456	* fXO=26MHz
Wolfgang Betz	67:93bec0baf1de	457	* REFDIV = 0 - SYNT[25:21] = 11...13
Wolfgang Betz	67:93bec0baf1de	458	* REFDIV = 1 - SYNT[25:21] = 2227
Wolfgang Betz	67:93bec0baf1de	459	*
Wolfgang Betz	67:93bec0baf1de	460	*
Wolfgang Betz	67:93bec0baf1de	461	* \endcode
Wolfgang Betz	67:93bec0baf1de	462	*/
Wolfgang Betz	67:93bec0baf1de	463	#define SYNT3_BASE ((uint8_t)0x08) /!< [4:0] -> SYNT[25:21], highest 5 bits of the PLL programmable divider /
Wolfgang Betz	67:93bec0baf1de	464
Wolfgang Betz	67:93bec0baf1de	465	#define WCP_CONF_WCP_378UA ((uint8_t)0x00) /!< Charge pump current nominal value = 378uA [VCO 4644-4708]&[VCO 5161-5232] /
Wolfgang Betz	67:93bec0baf1de	466	#define WCP_CONF_WCP_369UA ((uint8_t)0x01) /!< Charge pump current nominal value = 369uA [VCO 4708-4772]&[VCO 5232-5303] /
Wolfgang Betz	67:93bec0baf1de	467	#define WCP_CONF_WCP_359UA ((uint8_t)0x02) /!< Charge pump current nominal value = 359uA [VCO 4772-4836]&[VCO 5303-5375] /
Wolfgang Betz	67:93bec0baf1de	468	#define WCP_CONF_WCP_350UA ((uint8_t)0x03) /!< Charge pump current nominal value = 350uA [VCO 4836-4902]&[VCO 5375-5448] /
Wolfgang Betz	67:93bec0baf1de	469	#define WCP_CONF_WCP_340UA ((uint8_t)0x04) /!< Charge pump current nominal value = 340uA [VCO 4902-4966]&[VCO 5448-5519] /
Wolfgang Betz	67:93bec0baf1de	470	#define WCP_CONF_WCP_331UA ((uint8_t)0x05) /!< Charge pump current nominal value = 331uA [VCO 4966-5030]&[VCO 5519-5592] /
Wolfgang Betz	67:93bec0baf1de	471	#define WCP_CONF_WCP_321UA ((uint8_t)0x06) /!< Charge pump current nominal value = 321uA [VCO 5030-5095]&[VCO 5592-5563] /
Wolfgang Betz	67:93bec0baf1de	472	#define WCP_CONF_WCP_312UA ((uint8_t)0x07) /!< Charge pump current nominal value = 312uA [VCO 5095-5160]&[VCO 5563-5736] /
Wolfgang Betz	67:93bec0baf1de	473
Wolfgang Betz	67:93bec0baf1de	474
Wolfgang Betz	67:93bec0baf1de	475	/**
Wolfgang Betz	67:93bec0baf1de	476	* @}
Wolfgang Betz	67:93bec0baf1de	477	*/
Wolfgang Betz	67:93bec0baf1de	478
Wolfgang Betz	67:93bec0baf1de	479
Wolfgang Betz	67:93bec0baf1de	480	/** @defgroup SYNT2_Register
Wolfgang Betz	67:93bec0baf1de	481	* @{
Wolfgang Betz	67:93bec0baf1de	482	*/
Wolfgang Betz	67:93bec0baf1de	483
Wolfgang Betz	67:93bec0baf1de	484	/**
Wolfgang Betz	67:93bec0baf1de	485	* \brief SYNT2 register
Wolfgang Betz	67:93bec0baf1de	486	* \code
Wolfgang Betz	67:93bec0baf1de	487	* Read Write
Wolfgang Betz	67:93bec0baf1de	488	* Default value: 0x84
Wolfgang Betz	67:93bec0baf1de	489	* 7:0 SYNT[20:13]: intermediate bits of the PLL programmable divider.
Wolfgang Betz	67:93bec0baf1de	490	*
Wolfgang Betz	67:93bec0baf1de	491	* \endcode
Wolfgang Betz	67:93bec0baf1de	492	*/
Wolfgang Betz	67:93bec0baf1de	493
Wolfgang Betz	67:93bec0baf1de	494	#define SYNT2_BASE ((uint8_t)0x09) /!< SYNT[20:13], intermediate bits of the PLL programmable divider /
Wolfgang Betz	67:93bec0baf1de	495
Wolfgang Betz	67:93bec0baf1de	496	/**
Wolfgang Betz	67:93bec0baf1de	497	* @}
Wolfgang Betz	67:93bec0baf1de	498	*/
Wolfgang Betz	67:93bec0baf1de	499
Wolfgang Betz	67:93bec0baf1de	500	/** @defgroup SYNT1_Register
Wolfgang Betz	67:93bec0baf1de	501	* @{
Wolfgang Betz	67:93bec0baf1de	502	*/
Wolfgang Betz	67:93bec0baf1de	503
Wolfgang Betz	67:93bec0baf1de	504	/**
Wolfgang Betz	67:93bec0baf1de	505	* \brief SYNT1 register
Wolfgang Betz	67:93bec0baf1de	506	* \code
Wolfgang Betz	67:93bec0baf1de	507	* Read Write
Wolfgang Betz	67:93bec0baf1de	508	* Default value: 0xEC
Wolfgang Betz	67:93bec0baf1de	509	* 7:0 SYNT[12:5]: intermediate bits of the PLL programmable divider.
Wolfgang Betz	67:93bec0baf1de	510	*
Wolfgang Betz	67:93bec0baf1de	511	* \endcode
Wolfgang Betz	67:93bec0baf1de	512	*/
Wolfgang Betz	67:93bec0baf1de	513
Wolfgang Betz	67:93bec0baf1de	514	#define SYNT1_BASE ((uint8_t)0x0A) /!< SYNT[12:5], intermediate bits of the PLL programmable divider /
Wolfgang Betz	67:93bec0baf1de	515
Wolfgang Betz	67:93bec0baf1de	516	/**
Wolfgang Betz	67:93bec0baf1de	517	* @}
Wolfgang Betz	67:93bec0baf1de	518	*/
Wolfgang Betz	67:93bec0baf1de	519
Wolfgang Betz	67:93bec0baf1de	520	/** @defgroup SYNT0_Register
Wolfgang Betz	67:93bec0baf1de	521	* @{
Wolfgang Betz	67:93bec0baf1de	522	*/
Wolfgang Betz	67:93bec0baf1de	523
Wolfgang Betz	67:93bec0baf1de	524	/**
Wolfgang Betz	67:93bec0baf1de	525	* \brief SYNT0 register
Wolfgang Betz	67:93bec0baf1de	526	* \code
Wolfgang Betz	67:93bec0baf1de	527	* Read Write
Wolfgang Betz	67:93bec0baf1de	528	* Default value: 0x51
Wolfgang Betz	67:93bec0baf1de	529	* 7:3 SYNT[4:0]: lowest bits of the PLL programmable divider.
Wolfgang Betz	67:93bec0baf1de	530	* 2:0 BS[2:0]: Synthesizer band select. This parameter selects the out-of-loop divide factor of the synthesizer
Wolfgang Betz	67:93bec0baf1de	531	* according to the formula fxo/(B/2)/D*SYNT/2^18
Wolfgang Betz	67:93bec0baf1de	532	*
Wolfgang Betz	67:93bec0baf1de	533	* BS2 \| BS1 \| BS0 \| value of B
Wolfgang Betz	67:93bec0baf1de	534	* ---------------------------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	535	* 0 \| 0 \| 1 \| 6
Wolfgang Betz	67:93bec0baf1de	536	* 0 \| 1 \| 0 \| 8
Wolfgang Betz	67:93bec0baf1de	537	* 0 \| 1 \| 1 \| 12
Wolfgang Betz	67:93bec0baf1de	538	* 1 \| 0 \| 0 \| 16
Wolfgang Betz	67:93bec0baf1de	539	* 1 \| 0 \| 1 \| 32
Wolfgang Betz	67:93bec0baf1de	540	*
Wolfgang Betz	67:93bec0baf1de	541	* \endcode
Wolfgang Betz	67:93bec0baf1de	542	*/
Wolfgang Betz	67:93bec0baf1de	543	#define SYNT0_BASE ((uint8_t)0x0B) /!< [7:3] -> SYNT[4:0], lowest bits of the PLL programmable divider /
Wolfgang Betz	67:93bec0baf1de	544
Wolfgang Betz	67:93bec0baf1de	545	#define SYNT0_BS_6 ((uint8_t)0x01) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=6 (779-956MHz) /
Wolfgang Betz	67:93bec0baf1de	546	#define SYNT0_BS_8 ((uint8_t)0x02) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=8 (387-470MHz)/
Wolfgang Betz	67:93bec0baf1de	547	#define SYNT0_BS_12 ((uint8_t)0x03) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=12 (387-470MHz)/
Wolfgang Betz	67:93bec0baf1de	548	#define SYNT0_BS_16 ((uint8_t)0x04) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=16 (300-348MHz)/
Wolfgang Betz	67:93bec0baf1de	549	#define SYNT0_BS_32 ((uint8_t)0x05) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=32 (150-174MHz)/
Wolfgang Betz	67:93bec0baf1de	550
Wolfgang Betz	67:93bec0baf1de	551	/**
Wolfgang Betz	67:93bec0baf1de	552	* @}
Wolfgang Betz	67:93bec0baf1de	553	*/
Wolfgang Betz	67:93bec0baf1de	554
Wolfgang Betz	67:93bec0baf1de	555	/** @defgroup CHSPACE_Register
Wolfgang Betz	67:93bec0baf1de	556	* @{
Wolfgang Betz	67:93bec0baf1de	557	*/
Wolfgang Betz	67:93bec0baf1de	558
Wolfgang Betz	67:93bec0baf1de	559	/**
Wolfgang Betz	67:93bec0baf1de	560	* \brief CHSPACE register
Wolfgang Betz	67:93bec0baf1de	561	* \code
Wolfgang Betz	67:93bec0baf1de	562	* Read Write
Wolfgang Betz	67:93bec0baf1de	563	* Default value: 0xFC
Wolfgang Betz	67:93bec0baf1de	564	* 7:0 CH_SPACING[7:0]: Channel spacing. From ~793Hz to ~200KHz in 793Hz steps
Wolfgang Betz	67:93bec0baf1de	565	* (in general, frequency step is fXO/215=26MHz/215~793Hz).
Wolfgang Betz	67:93bec0baf1de	566	*
Wolfgang Betz	67:93bec0baf1de	567	* \endcode
Wolfgang Betz	67:93bec0baf1de	568	*/
Wolfgang Betz	67:93bec0baf1de	569
Wolfgang Betz	67:93bec0baf1de	570	#define CHSPACE_BASE ((uint8_t)0x0C) /!< Channel spacing. From ~0.8KHz to ~200KHz in (fXO/2^15)Hz (793Hz for 26MHz XO) steps /
Wolfgang Betz	67:93bec0baf1de	571
Wolfgang Betz	67:93bec0baf1de	572	/**
Wolfgang Betz	67:93bec0baf1de	573	* @}
Wolfgang Betz	67:93bec0baf1de	574	*/
Wolfgang Betz	67:93bec0baf1de	575
Wolfgang Betz	67:93bec0baf1de	576
Wolfgang Betz	67:93bec0baf1de	577
Wolfgang Betz	67:93bec0baf1de	578	/** @defgroup IF_OFFSET_DIG_Register
Wolfgang Betz	67:93bec0baf1de	579	* @{
Wolfgang Betz	67:93bec0baf1de	580	*/
Wolfgang Betz	67:93bec0baf1de	581
Wolfgang Betz	67:93bec0baf1de	582	/**
Wolfgang Betz	67:93bec0baf1de	583	* \brief IF_OFFSET_DIG register
Wolfgang Betz	67:93bec0baf1de	584	* \code
Wolfgang Betz	67:93bec0baf1de	585	* Read Write
Wolfgang Betz	67:93bec0baf1de	586	* Default value: 0xA3
Wolfgang Betz	67:93bec0baf1de	587	* 7:0 IF_OFFSET_DIG[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz.
Wolfgang Betz	67:93bec0baf1de	588	*
Wolfgang Betz	67:93bec0baf1de	589	* \endcode
Wolfgang Betz	67:93bec0baf1de	590	*/
Wolfgang Betz	67:93bec0baf1de	591	#define IF_OFFSET_DIG_BASE ((uint8_t)0x0D) /!< Intermediate frequency fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz /
Wolfgang Betz	67:93bec0baf1de	592
Wolfgang Betz	67:93bec0baf1de	593	/**
Wolfgang Betz	67:93bec0baf1de	594	* @}
Wolfgang Betz	67:93bec0baf1de	595	*/
Wolfgang Betz	67:93bec0baf1de	596
Wolfgang Betz	67:93bec0baf1de	597	/** @defgroup IF_OFFSET_ANA_Register
Wolfgang Betz	67:93bec0baf1de	598	* @{
Wolfgang Betz	67:93bec0baf1de	599	*/
Wolfgang Betz	67:93bec0baf1de	600
Wolfgang Betz	67:93bec0baf1de	601	/**
Wolfgang Betz	67:93bec0baf1de	602	* \brief IF_OFFSET_ANA register
Wolfgang Betz	67:93bec0baf1de	603	* \code
Wolfgang Betz	67:93bec0baf1de	604	* Read Write
Wolfgang Betz	67:93bec0baf1de	605	* Default value: 0xA3
Wolfgang Betz	67:93bec0baf1de	606	* 7:0 IF_OFFSET_ANA[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz.
Wolfgang Betz	67:93bec0baf1de	607	*
Wolfgang Betz	67:93bec0baf1de	608	* \endcode
Wolfgang Betz	67:93bec0baf1de	609	*/
Wolfgang Betz	67:93bec0baf1de	610	#define IF_OFFSET_ANA_BASE ((uint8_t)0x07) /!< Intermediate frequency fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz /
Wolfgang Betz	67:93bec0baf1de	611
Wolfgang Betz	67:93bec0baf1de	612
Wolfgang Betz	67:93bec0baf1de	613	/**
Wolfgang Betz	67:93bec0baf1de	614	* @}
Wolfgang Betz	67:93bec0baf1de	615	*/
Wolfgang Betz	67:93bec0baf1de	616
Wolfgang Betz	67:93bec0baf1de	617	/** @defgroup FC_OFFSET1_Register
Wolfgang Betz	67:93bec0baf1de	618	* @{
Wolfgang Betz	67:93bec0baf1de	619	*/
Wolfgang Betz	67:93bec0baf1de	620
Wolfgang Betz	67:93bec0baf1de	621	/**
Wolfgang Betz	67:93bec0baf1de	622	* \brief FC_OFFSET1 registers
Wolfgang Betz	67:93bec0baf1de	623	* \code
Wolfgang Betz	67:93bec0baf1de	624	* Read Write
Wolfgang Betz	67:93bec0baf1de	625	* Default value: 0xA3
Wolfgang Betz	67:93bec0baf1de	626	* 7:4 Reserved.
Wolfgang Betz	67:93bec0baf1de	627	* 3:0 FC_OFFSET[11:8]: Carrier offset. This value is the higher part of a 12-bit 2s complement integer
Wolfgang Betz	67:93bec0baf1de	628	* representing an offset in 99Hz(2) units added/subtracted to the
Wolfgang Betz	67:93bec0baf1de	629	* carrier frequency set by registers SYNT3SYNT0.
Wolfgang Betz	67:93bec0baf1de	630	* This register can be used to set a fixed correction value
Wolfgang Betz	67:93bec0baf1de	631	* obtained e.g. from crystal measurements.
Wolfgang Betz	67:93bec0baf1de	632	*
Wolfgang Betz	67:93bec0baf1de	633	* \endcode
Wolfgang Betz	67:93bec0baf1de	634	*/
Wolfgang Betz	67:93bec0baf1de	635	#define FC_OFFSET1_BASE ((uint8_t)0x0E) /!< [3:0] -> [11:8] Carrier offset (upper part) /
Wolfgang Betz	67:93bec0baf1de	636
Wolfgang Betz	67:93bec0baf1de	637	/**
Wolfgang Betz	67:93bec0baf1de	638	* @}
Wolfgang Betz	67:93bec0baf1de	639	*/
Wolfgang Betz	67:93bec0baf1de	640
Wolfgang Betz	67:93bec0baf1de	641
Wolfgang Betz	67:93bec0baf1de	642	/** @defgroup FC_OFFSET0_Register
Wolfgang Betz	67:93bec0baf1de	643	* @{
Wolfgang Betz	67:93bec0baf1de	644	*/
Wolfgang Betz	67:93bec0baf1de	645
Wolfgang Betz	67:93bec0baf1de	646	/**
Wolfgang Betz	67:93bec0baf1de	647	* \brief FC_OFFSET0 registers
Wolfgang Betz	67:93bec0baf1de	648	* \code
Wolfgang Betz	67:93bec0baf1de	649	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	650	* Read Write
Wolfgang Betz	67:93bec0baf1de	651	* 7:0 FC_OFFSET[7:0]: Carrier offset. This value is the lower part of a 12-bit 2s complement integer
Wolfgang Betz	67:93bec0baf1de	652	* representing an offset in 99Hz(2) units added/subtracted to the
Wolfgang Betz	67:93bec0baf1de	653	* carrier frequency set by registers SYNT3SYNT0.
Wolfgang Betz	67:93bec0baf1de	654	* This register can be used to set a fixed correction value
Wolfgang Betz	67:93bec0baf1de	655	* obtained e.g. from crystal measurements.
Wolfgang Betz	67:93bec0baf1de	656	*
Wolfgang Betz	67:93bec0baf1de	657	* \endcode
Wolfgang Betz	67:93bec0baf1de	658	*/
Wolfgang Betz	67:93bec0baf1de	659	#define FC_OFFSET0_BASE ((uint8_t)0x0F) /*!< [7:0] -> [7:0] Carrier offset (lower part). This value is a 12-bit 2s complement integer
Wolfgang Betz	67:93bec0baf1de	660	representing an offset in fXO/2^18 (99Hz for 26 MHz XO) units added/subtracted to the carrier frequency
Wolfgang Betz	67:93bec0baf1de	661	set by registers SYNT3SYNT0. Range is +/-200kHz with 26 MHz XO */
Wolfgang Betz	67:93bec0baf1de	662	/**
Wolfgang Betz	67:93bec0baf1de	663	* @}
Wolfgang Betz	67:93bec0baf1de	664	*/
Wolfgang Betz	67:93bec0baf1de	665
Wolfgang Betz	67:93bec0baf1de	666
Wolfgang Betz	67:93bec0baf1de	667	/** @defgroup PA_LEVEL_x_Registers
Wolfgang Betz	67:93bec0baf1de	668	* @{
Wolfgang Betz	67:93bec0baf1de	669	*/
Wolfgang Betz	67:93bec0baf1de	670
Wolfgang Betz	67:93bec0baf1de	671	/**
Wolfgang Betz	67:93bec0baf1de	672	* \brief PA_POWER_x[8:1] registers
Wolfgang Betz	67:93bec0baf1de	673	* \code
Wolfgang Betz	67:93bec0baf1de	674	* Default values from 8 to 1: [0x03, 0x0E, 0x1A, 0x25, 0x35, 0x40, 0x4E, 0x00]
Wolfgang Betz	67:93bec0baf1de	675	* Read Write
Wolfgang Betz	67:93bec0baf1de	676	*
Wolfgang Betz	67:93bec0baf1de	677	* 7 Reserved.
Wolfgang Betz	67:93bec0baf1de	678	* 6:0 PA_LEVEL_(x-1)[6:0]: Output power level for x-th slot.
Wolfgang Betz	67:93bec0baf1de	679	* \endcode
Wolfgang Betz	67:93bec0baf1de	680	*/
Wolfgang Betz	67:93bec0baf1de	681
Wolfgang Betz	67:93bec0baf1de	682	#define PA_POWER8_BASE ((uint8_t)0x10) /!< PA Power level for 8th slot of PA ramping or ASK modulation /
Wolfgang Betz	67:93bec0baf1de	683	#define PA_POWER7_BASE ((uint8_t)0x11) /!< PA Power level for 7th slot of PA ramping or ASK modulation /
Wolfgang Betz	67:93bec0baf1de	684	#define PA_POWER6_BASE ((uint8_t)0x12) /!< PA Power level for 6th slot of PA ramping or ASK modulation /
Wolfgang Betz	67:93bec0baf1de	685	#define PA_POWER5_BASE ((uint8_t)0x13) /!< PA Power level for 5th slot of PA ramping or ASK modulation /
Wolfgang Betz	67:93bec0baf1de	686	#define PA_POWER4_BASE ((uint8_t)0x14) /!< PA Power level for 4th slot of PA ramping or ASK modulation /
Wolfgang Betz	67:93bec0baf1de	687	#define PA_POWER3_BASE ((uint8_t)0x15) /!< PA Power level for 3rd slot of PA ramping or ASK modulation /
Wolfgang Betz	67:93bec0baf1de	688	#define PA_POWER2_BASE ((uint8_t)0x16) /!< PA Power level for 2nd slot of PA ramping or ASK modulation /
Wolfgang Betz	67:93bec0baf1de	689	#define PA_POWER1_BASE ((uint8_t)0x17) /!< PA Power level for 1st slot of PA ramping or ASK modulation /
Wolfgang Betz	67:93bec0baf1de	690
Wolfgang Betz	67:93bec0baf1de	691	/**
Wolfgang Betz	67:93bec0baf1de	692	* @}
Wolfgang Betz	67:93bec0baf1de	693	*/
Wolfgang Betz	67:93bec0baf1de	694
Wolfgang Betz	67:93bec0baf1de	695	/** @defgroup PA_POWER_CONF_Registers
Wolfgang Betz	67:93bec0baf1de	696	* @{
Wolfgang Betz	67:93bec0baf1de	697	*/
Wolfgang Betz	67:93bec0baf1de	698
Wolfgang Betz	67:93bec0baf1de	699	/**
Wolfgang Betz	67:93bec0baf1de	700	* \brief PA_POWER_CONF_Registers
Wolfgang Betz	67:93bec0baf1de	701	* \code
Wolfgang Betz	67:93bec0baf1de	702	* Default value:0x07
Wolfgang Betz	67:93bec0baf1de	703	* Read Write
Wolfgang Betz	67:93bec0baf1de	704	*
Wolfgang Betz	67:93bec0baf1de	705	* 7:6 CWC[1:0]: Output stage additional load capacitors bank (to be used to
Wolfgang Betz	67:93bec0baf1de	706	* optimize the PA for different sub-bands).
Wolfgang Betz	67:93bec0baf1de	707	*
Wolfgang Betz	67:93bec0baf1de	708	* CWC1 \| CWC0 \| Total capacity in pF
Wolfgang Betz	67:93bec0baf1de	709	* ---------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	710	* 0 \| 0 \| 0
Wolfgang Betz	67:93bec0baf1de	711	* 0 \| 1 \| 1.2
Wolfgang Betz	67:93bec0baf1de	712	* 1 \| 0 \| 2.4
Wolfgang Betz	67:93bec0baf1de	713	* 1 \| 1 \| 3.6
Wolfgang Betz	67:93bec0baf1de	714	*
Wolfgang Betz	67:93bec0baf1de	715	* 5 PA_RAMP_ENABLE:
Wolfgang Betz	67:93bec0baf1de	716	* 1 - Enable the power ramping
Wolfgang Betz	67:93bec0baf1de	717	* 0 - Disable the power ramping
Wolfgang Betz	67:93bec0baf1de	718	* 4:3 PA_RAMP_STEP_WIDTH[1:0]: Step width in bit period
Wolfgang Betz	67:93bec0baf1de	719	*
Wolfgang Betz	67:93bec0baf1de	720	* PA_RAMP_STEP_WIDTH1 \| PA_RAMP_STEP_WIDTH0 \| PA ramping time step
Wolfgang Betz	67:93bec0baf1de	721	* -------------------------------------------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	722	* 0 \| 0 \| 1/8 Bit period
Wolfgang Betz	67:93bec0baf1de	723	* 0 \| 1 \| 2/8 Bit period
Wolfgang Betz	67:93bec0baf1de	724	* 1 \| 0 \| 3/8 Bit period
Wolfgang Betz	67:93bec0baf1de	725	* 1 \| 1 \| 4/8 Bit period
Wolfgang Betz	67:93bec0baf1de	726	*
Wolfgang Betz	67:93bec0baf1de	727	* 2:0 PA_LEVEL_MAX_INDEX[2:0]: Fixes the MAX PA LEVEL in PA ramping or ASK modulation
Wolfgang Betz	67:93bec0baf1de	728	*
Wolfgang Betz	67:93bec0baf1de	729	* \endcode
Wolfgang Betz	67:93bec0baf1de	730	*/
Wolfgang Betz	67:93bec0baf1de	731	#define PA_POWER0_BASE ((uint8_t)0x18) /*!< PA ramping settings and additional load capacitor banks used
Wolfgang Betz	67:93bec0baf1de	732	for PA optimization in different sub bands*/
Wolfgang Betz	67:93bec0baf1de	733	#define PA_POWER0_CWC_MASK ((uint8_t)0x20) /!< Output stage additional load capacitors bank /
Wolfgang Betz	67:93bec0baf1de	734	#define PA_POWER0_CWC_0 ((uint8_t)0x00) /!< No additional PA load capacitor /
Wolfgang Betz	67:93bec0baf1de	735	#define PA_POWER0_CWC_1_2P ((uint8_t)0x40) /!< 1.2pF additional PA load capacitor /
Wolfgang Betz	67:93bec0baf1de	736	#define PA_POWER0_CWC_2_4P ((uint8_t)0x80) /!< 2.4pF additional PA load capacitor /
Wolfgang Betz	67:93bec0baf1de	737	#define PA_POWER0_CWC_3_6P ((uint8_t)0xC0) /!< 3.6pF additional PA load capacitor /
Wolfgang Betz	67:93bec0baf1de	738	#define PA_POWER0_PA_RAMP_MASK ((uint8_t)0x20) /!< The PA power ramping /
Wolfgang Betz	67:93bec0baf1de	739	#define PA_POWER0_PA_RAMP_STEP_WIDTH_MASK ((uint8_t)0x20) /!< The step width /
Wolfgang Betz	67:93bec0baf1de	740	#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_8 ((uint8_t)0x00) /!< PA ramping time step = 1/8 Bit period/
Wolfgang Betz	67:93bec0baf1de	741	#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_4 ((uint8_t)0x08) /!< PA ramping time step = 2/8 Bit period/
Wolfgang Betz	67:93bec0baf1de	742	#define PA_POWER0_PA_RAMP_STEP_WIDTH_3TB_8 ((uint8_t)0x10) /!< PA ramping time step = 3/8 Bit period/
Wolfgang Betz	67:93bec0baf1de	743	#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_2 ((uint8_t)0x18) /!< PA ramping time step = 4/8 Bit period/
Wolfgang Betz	67:93bec0baf1de	744	#define PA_POWER0_PA_LEVEL_MAX_INDEX ((uint8_t)0x20) /!< Final level for power ramping /
Wolfgang Betz	67:93bec0baf1de	745	#define PA_POWER0_PA_LEVEL_MAX_INDEX_0 ((uint8_t)0x00) /!< /
Wolfgang Betz	67:93bec0baf1de	746	#define PA_POWER0_PA_LEVEL_MAX_INDEX_1 ((uint8_t)0x01) /!< Fixes the MAX PA LEVEL in PA ramping or ASK modulation /
Wolfgang Betz	67:93bec0baf1de	747	#define PA_POWER0_PA_LEVEL_MAX_INDEX_2 ((uint8_t)0x02) /!< /
Wolfgang Betz	67:93bec0baf1de	748	#define PA_POWER0_PA_LEVEL_MAX_INDEX_3 ((uint8_t)0x03) /!< _________ /
Wolfgang Betz	67:93bec0baf1de	749	#define PA_POWER0_PA_LEVEL_MAX_INDEX_4 ((uint8_t)0x04) /!< PA_LVL2 _\| <--\| /
Wolfgang Betz	67:93bec0baf1de	750	#define PA_POWER0_PA_LEVEL_MAX_INDEX_5 ((uint8_t)0x05) /!< _\| \| /
Wolfgang Betz	67:93bec0baf1de	751	#define PA_POWER0_PA_LEVEL_MAX_INDEX_6 ((uint8_t)0x06) /!< PA_LVL1 _\| \| /
Wolfgang Betz	67:93bec0baf1de	752	#define PA_POWER0_PA_LEVEL_MAX_INDEX_7 ((uint8_t)0x07) /!< PA_LVL0 _\| MAX_INDEX- /
Wolfgang Betz	67:93bec0baf1de	753
Wolfgang Betz	67:93bec0baf1de	754
Wolfgang Betz	67:93bec0baf1de	755
Wolfgang Betz	67:93bec0baf1de	756	/**
Wolfgang Betz	67:93bec0baf1de	757	* @}
Wolfgang Betz	67:93bec0baf1de	758	*/
Wolfgang Betz	67:93bec0baf1de	759
Wolfgang Betz	67:93bec0baf1de	760
Wolfgang Betz	67:93bec0baf1de	761	/** @defgroup MOD1_Register
Wolfgang Betz	67:93bec0baf1de	762	* @{
Wolfgang Betz	67:93bec0baf1de	763	*/
Wolfgang Betz	67:93bec0baf1de	764
Wolfgang Betz	67:93bec0baf1de	765	/**
Wolfgang Betz	67:93bec0baf1de	766	* \brief MOD1 register
Wolfgang Betz	67:93bec0baf1de	767	* \code
Wolfgang Betz	67:93bec0baf1de	768	* Read Write
Wolfgang Betz	67:93bec0baf1de	769	* Default value: 0x83
Wolfgang Betz	67:93bec0baf1de	770	* 7:0 DATARATE_M[7:0]: The Mantissa of the specified data rate
Wolfgang Betz	67:93bec0baf1de	771	*
Wolfgang Betz	67:93bec0baf1de	772	* \endcode
Wolfgang Betz	67:93bec0baf1de	773	*/
Wolfgang Betz	67:93bec0baf1de	774	#define MOD1_BASE ((uint8_t)0x1A) /!< The Mantissa of the specified data rate /
Wolfgang Betz	67:93bec0baf1de	775
Wolfgang Betz	67:93bec0baf1de	776	/**
Wolfgang Betz	67:93bec0baf1de	777	* @}
Wolfgang Betz	67:93bec0baf1de	778	*/
Wolfgang Betz	67:93bec0baf1de	779
Wolfgang Betz	67:93bec0baf1de	780	/** @defgroup MOD0_Register
Wolfgang Betz	67:93bec0baf1de	781	* @{
Wolfgang Betz	67:93bec0baf1de	782	*/
Wolfgang Betz	67:93bec0baf1de	783
Wolfgang Betz	67:93bec0baf1de	784	/**
Wolfgang Betz	67:93bec0baf1de	785	* \brief MOD0 register
Wolfgang Betz	67:93bec0baf1de	786	* \code
Wolfgang Betz	67:93bec0baf1de	787	* Read Write
Wolfgang Betz	67:93bec0baf1de	788	* Default value: 0x1A
Wolfgang Betz	67:93bec0baf1de	789	* 7 CW: 1 - CW Mode enabled - enables the generation of a continous wave carrier without any modulation
Wolfgang Betz	67:93bec0baf1de	790	* 0 - CW Mode disabled
Wolfgang Betz	67:93bec0baf1de	791	*
Wolfgang Betz	67:93bec0baf1de	792	* 6 BT_SEL: Select BT value for GFSK
Wolfgang Betz	67:93bec0baf1de	793	* 1 - BT=0.5
Wolfgang Betz	67:93bec0baf1de	794	* 0 - BT=1
Wolfgang Betz	67:93bec0baf1de	795	*
Wolfgang Betz	67:93bec0baf1de	796	* 5:4 MOD_TYPE[1:0]: Modulation type
Wolfgang Betz	67:93bec0baf1de	797	*
Wolfgang Betz	67:93bec0baf1de	798	*
Wolfgang Betz	67:93bec0baf1de	799	* MOD_TYPE1 \| MOD_TYPE0 \| Modulation
Wolfgang Betz	67:93bec0baf1de	800	* ---------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	801	* 0 \| 0 \| 2-FSK,MSK
Wolfgang Betz	67:93bec0baf1de	802	* 0 \| 1 \| GFSK,GMSK
Wolfgang Betz	67:93bec0baf1de	803	* 1 \| 0 \| ASK/OOK
Wolfgang Betz	67:93bec0baf1de	804	*
Wolfgang Betz	67:93bec0baf1de	805	* 3:0 DATARATE_E[3:0]: The Exponent of the specified data rate
Wolfgang Betz	67:93bec0baf1de	806	*
Wolfgang Betz	67:93bec0baf1de	807	* \endcode
Wolfgang Betz	67:93bec0baf1de	808	*/
Wolfgang Betz	67:93bec0baf1de	809	#define MOD0_BASE ((uint8_t)0x1B) /!< Modulation Settings, Exponent of the specified data rate, CW mode/
Wolfgang Betz	67:93bec0baf1de	810
Wolfgang Betz	67:93bec0baf1de	811	#define MOD0_MOD_TYPE_2_FSK ((uint8_t)0x00) /!< Modulation type 2-FSK (MSK if the frequency deviation is identical to a quarter of the data rate) /
Wolfgang Betz	67:93bec0baf1de	812	#define MOD0_MOD_TYPE_GFSK ((uint8_t)0x10) /!< Modulation type GFSK (GMSK if the frequency deviation is identical to a quarter of the data rate) /
Wolfgang Betz	67:93bec0baf1de	813	#define MOD0_MOD_TYPE_ASK ((uint8_t)0x20) /!< Modulation type ASK (OOK the PA is switched off for symbol "0") /
Wolfgang Betz	67:93bec0baf1de	814	#define MOD0_MOD_TYPE_MSK ((uint8_t)0x00) /!< Modulation type MSK (the frequency deviation must be identical to a quarter of the data rate) /
Wolfgang Betz	67:93bec0baf1de	815	#define MOD0_MOD_TYPE_GMSK ((uint8_t)0x10) /!< Modulation type GMSK (the frequency deviation must be identical to a quarter of the data rate) /
Wolfgang Betz	67:93bec0baf1de	816	#define MOD0_BT_SEL_BT_MASK ((uint8_t)0x00) /!< Select the BT = 1 or BT = 0.5 valid only for GFSK or GMSK modulation/
Wolfgang Betz	67:93bec0baf1de	817	#define MOD0_CW ((uint8_t)0x80) /!< Set the Continous Wave (no modulation) transmit mode /
Wolfgang Betz	67:93bec0baf1de	818
Wolfgang Betz	67:93bec0baf1de	819	/**
Wolfgang Betz	67:93bec0baf1de	820	* @}
Wolfgang Betz	67:93bec0baf1de	821	*/
Wolfgang Betz	67:93bec0baf1de	822
Wolfgang Betz	67:93bec0baf1de	823
Wolfgang Betz	67:93bec0baf1de	824	/** @defgroup FDEV0_Register
Wolfgang Betz	67:93bec0baf1de	825	* @{
Wolfgang Betz	67:93bec0baf1de	826	*/
Wolfgang Betz	67:93bec0baf1de	827
Wolfgang Betz	67:93bec0baf1de	828	/**
Wolfgang Betz	67:93bec0baf1de	829	* \brief FDEV0 register
Wolfgang Betz	67:93bec0baf1de	830	* \code
Wolfgang Betz	67:93bec0baf1de	831	* Read Write
Wolfgang Betz	67:93bec0baf1de	832	* Default value: 0x45
Wolfgang Betz	67:93bec0baf1de	833	* 7:4 FDEV_E[3:0]: Exponent of the frequency deviation (allowed values from 0 to 9)
Wolfgang Betz	67:93bec0baf1de	834	*
Wolfgang Betz	67:93bec0baf1de	835	* 3 CLOCK_REC_ALGO_SEL: Select PLL or DLL mode for clock recovery
Wolfgang Betz	67:93bec0baf1de	836	* 1 - DLL mode
Wolfgang Betz	67:93bec0baf1de	837	* 0 - PLL mode
Wolfgang Betz	67:93bec0baf1de	838	*
Wolfgang Betz	67:93bec0baf1de	839	* 2:0 FDEV_M[1:0]: Mantissa of the frequency deviation (allowed values from 0 to 7)
Wolfgang Betz	67:93bec0baf1de	840	*
Wolfgang Betz	67:93bec0baf1de	841	*
Wolfgang Betz	67:93bec0baf1de	842	* \endcode
Wolfgang Betz	67:93bec0baf1de	843	*/
Wolfgang Betz	67:93bec0baf1de	844	#define FDEV0_BASE ((uint8_t)0x1C) /*!< Sets the Mantissa and exponent of frequency deviation (frequency separation/2)
Wolfgang Betz	67:93bec0baf1de	845	and PLL or DLL alogrithm from clock recovery in RX digital demod*/
Wolfgang Betz	67:93bec0baf1de	846	#define FDEV0_CLOCK_REG_ALGO_SEL_MASK ((uint8_t)0x08) /!< Can be DLL or PLL algorithm for clock recovery in RX digital demod (see CLOCKREC reg) /
Wolfgang Betz	67:93bec0baf1de	847	#define FDEV0_CLOCK_REG_ALGO_SEL_PLL ((uint8_t)0x00) /!< Sets PLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) /
Wolfgang Betz	67:93bec0baf1de	848	#define FDEV0_CLOCK_REG_ALGO_SEL_DLL ((uint8_t)0x08) /!< Sets DLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) /
Wolfgang Betz	67:93bec0baf1de	849
Wolfgang Betz	67:93bec0baf1de	850	/**
Wolfgang Betz	67:93bec0baf1de	851	* @}
Wolfgang Betz	67:93bec0baf1de	852	*/
Wolfgang Betz	67:93bec0baf1de	853
Wolfgang Betz	67:93bec0baf1de	854	/** @defgroup CHFLT_Register
Wolfgang Betz	67:93bec0baf1de	855	* @{
Wolfgang Betz	67:93bec0baf1de	856	*/
Wolfgang Betz	67:93bec0baf1de	857
Wolfgang Betz	67:93bec0baf1de	858	/**
Wolfgang Betz	67:93bec0baf1de	859	* \brief CHFLT register
Wolfgang Betz	67:93bec0baf1de	860	* \code
Wolfgang Betz	67:93bec0baf1de	861	* Read Write
Wolfgang Betz	67:93bec0baf1de	862	* Default value: 0x23
Wolfgang Betz	67:93bec0baf1de	863	* 7:4 CHFLT_M[3:0]: Mantissa of the channel filter BW (allowed values from 0 to 8)
Wolfgang Betz	67:93bec0baf1de	864	*
Wolfgang Betz	67:93bec0baf1de	865	* 3:0 CHFLT_E[3:0]: Exponent of the channel filter BW (allowed values from 0 to 9)
Wolfgang Betz	67:93bec0baf1de	866	*
Wolfgang Betz	67:93bec0baf1de	867	* M\E \| 0 \| 1 \| 2 \| 3 \| 4 \| 5 \| 6 \| 7 \| 8 \| 9 \|
Wolfgang Betz	67:93bec0baf1de	868	* -----+-------+-------+-------+-------+------+------+------+-----+-----+-----+
Wolfgang Betz	67:93bec0baf1de	869	* 0 \| 800.1 \| 450.9 \| 224.7 \| 112.3 \| 56.1 \| 28.0 \| 14.0 \| 7.0 \| 3.5 \| 1.8 \|
Wolfgang Betz	67:93bec0baf1de	870	* 1 \| 795.1 \| 425.9 \| 212.4 \| 106.2 \| 53.0 \| 26.5 \| 13.3 \| 6.6 \| 3.3 \| 1.7 \|
Wolfgang Betz	67:93bec0baf1de	871	* 2 \| 768.4 \| 403.2 \| 201.1 \| 100.5 \| 50.2 \| 25.1 \| 12.6 \| 6.3 \| 3.1 \| 1.6 \|
Wolfgang Betz	67:93bec0baf1de	872	* 3 \| 736.8 \| 380.8 \| 190.0 \| 95.0 \| 47.4 \| 23.7 \| 11.9 \| 5.9 \| 3.0 \| 1.5 \|
Wolfgang Betz	67:93bec0baf1de	873	* 4 \| 705.1 \| 362.1 \| 180.7 \| 90.3 \| 45.1 \| 22.6 \| 11.3 \| 5.6 \| 2.8 \| 1.4 \|
Wolfgang Betz	67:93bec0baf1de	874	* 5 \| 670.9 \| 341.7 \| 170.6 \| 85.3 \| 42.6 \| 21.3 \| 10.6 \| 5.3 \| 2.7 \| 1.3 \|
Wolfgang Betz	67:93bec0baf1de	875	* 6 \| 642.3 \| 325.4 \| 162.4 \| 81.2 \| 40.6 \| 20.3 \| 10.1 \| 5.1 \| 2.5 \| 1.3 \|
Wolfgang Betz	67:93bec0baf1de	876	* 7 \| 586.7 \| 294.5 \| 147.1 \| 73.5 \| 36.7 \| 18.4 \| 9.2 \| 4.6 \| 2.3 \| 1.2 \|
Wolfgang Betz	67:93bec0baf1de	877	* 8 \| 541.4 \| 270.3 \| 135.0 \| 67.5 \| 33.7 \| 16.9 \| 8.4 \| 4.2 \| 2.1 \| 1.1 \|
Wolfgang Betz	67:93bec0baf1de	878	*
Wolfgang Betz	67:93bec0baf1de	879	* \endcode
Wolfgang Betz	67:93bec0baf1de	880	*/
Wolfgang Betz	67:93bec0baf1de	881	#define CHFLT_BASE ((uint8_t)0x1D) /!< RX Channel Filter Bandwidth /
Wolfgang Betz	67:93bec0baf1de	882
Wolfgang Betz	67:93bec0baf1de	883	#define CHFLT_800_1 ((uint8_t)0x00) /!< RX Channel Filter Bandwidth = 800.1 kHz /
Wolfgang Betz	67:93bec0baf1de	884	#define CHFLT_795_1 ((uint8_t)0x10) /!< RX Channel Filter Bandwidth = 795.1 kHz /
Wolfgang Betz	67:93bec0baf1de	885	#define CHFLT_768_4 ((uint8_t)0x20) /!< RX Channel Filter Bandwidth = 768.4 kHz /
Wolfgang Betz	67:93bec0baf1de	886	#define CHFLT_736_8 ((uint8_t)0x30) /!< RX Channel Filter Bandwidth = 736.8 kHz /
Wolfgang Betz	67:93bec0baf1de	887	#define CHFLT_705_1 ((uint8_t)0x40) /!< RX Channel Filter Bandwidth = 705.1 kHz /
Wolfgang Betz	67:93bec0baf1de	888	#define CHFLT_670_9 ((uint8_t)0x50) /!< RX Channel Filter Bandwidth = 670.9 kHz /
Wolfgang Betz	67:93bec0baf1de	889	#define CHFLT_642_3 ((uint8_t)0x60) /!< RX Channel Filter Bandwidth = 642.3 kHz /
Wolfgang Betz	67:93bec0baf1de	890	#define CHFLT_586_7 ((uint8_t)0x70) /!< RX Channel Filter Bandwidth = 586.7 kHz /
Wolfgang Betz	67:93bec0baf1de	891	#define CHFLT_541_4 ((uint8_t)0x80) /!< RX Channel Filter Bandwidth = 541.4 kHz /
Wolfgang Betz	67:93bec0baf1de	892	#define CHFLT_450_9 ((uint8_t)0x01) /!< RX Channel Filter Bandwidth = 450.9 kHz /
Wolfgang Betz	67:93bec0baf1de	893	#define CHFLT_425_9 ((uint8_t)0x11) /!< RX Channel Filter Bandwidth = 425.9 kHz /
Wolfgang Betz	67:93bec0baf1de	894	#define CHFLT_403_2 ((uint8_t)0x21) /!< RX Channel Filter Bandwidth = 403.2 kHz /
Wolfgang Betz	67:93bec0baf1de	895	#define CHFLT_380_8 ((uint8_t)0x31) /!< RX Channel Filter Bandwidth = 380.8 kHz /
Wolfgang Betz	67:93bec0baf1de	896	#define CHFLT_362_1 ((uint8_t)0x41) /!< RX Channel Filter Bandwidth = 362.1 kHz /
Wolfgang Betz	67:93bec0baf1de	897	#define CHFLT_341_7 ((uint8_t)0x51) /!< RX Channel Filter Bandwidth = 341.7 kHz /
Wolfgang Betz	67:93bec0baf1de	898	#define CHFLT_325_4 ((uint8_t)0x61) /!< RX Channel Filter Bandwidth = 325.4 kHz /
Wolfgang Betz	67:93bec0baf1de	899	#define CHFLT_294_5 ((uint8_t)0x71) /!< RX Channel Filter Bandwidth = 294.5 kHz /
Wolfgang Betz	67:93bec0baf1de	900	#define CHFLT_270_3 ((uint8_t)0x81) /!< RX Channel Filter Bandwidth = 270.3 kHz /
Wolfgang Betz	67:93bec0baf1de	901	#define CHFLT_224_7 ((uint8_t)0x02) /!< RX Channel Filter Bandwidth = 224.7 kHz /
Wolfgang Betz	67:93bec0baf1de	902	#define CHFLT_212_4 ((uint8_t)0x12) /!< RX Channel Filter Bandwidth = 212.4 kHz /
Wolfgang Betz	67:93bec0baf1de	903	#define CHFLT_201_1 ((uint8_t)0x22) /!< RX Channel Filter Bandwidth = 201.1 kHz /
Wolfgang Betz	67:93bec0baf1de	904	#define CHFLT_190 ((uint8_t)0x32) /!< RX Channel Filter Bandwidth = 190.0 kHz /
Wolfgang Betz	67:93bec0baf1de	905	#define CHFLT_180_7 ((uint8_t)0x42) /!< RX Channel Filter Bandwidth = 180.7 kHz /
Wolfgang Betz	67:93bec0baf1de	906	#define CHFLT_170_6 ((uint8_t)0x52) /!< RX Channel Filter Bandwidth = 170.6 kHz /
Wolfgang Betz	67:93bec0baf1de	907	#define CHFLT_162_4 ((uint8_t)0x62) /!< RX Channel Filter Bandwidth = 162.4 kHz /
Wolfgang Betz	67:93bec0baf1de	908	#define CHFLT_147_1 ((uint8_t)0x72) /!< RX Channel Filter Bandwidth = 147.1 kHz /
Wolfgang Betz	67:93bec0baf1de	909	#define CHFLT_135 ((uint8_t)0x82) /!< RX Channel Filter Bandwidth = 135.0 kHz /
Wolfgang Betz	67:93bec0baf1de	910	#define CHFLT_112_3 ((uint8_t)0x03) /!< RX Channel Filter Bandwidth = 112.3 kHz /
Wolfgang Betz	67:93bec0baf1de	911	#define CHFLT_106_2 ((uint8_t)0x13) /!< RX Channel Filter Bandwidth = 106.2 kHz /
Wolfgang Betz	67:93bec0baf1de	912	#define CHFLT_100_5 ((uint8_t)0x23) /!< RX Channel Filter Bandwidth = 100.5 kHz /
Wolfgang Betz	67:93bec0baf1de	913	#define CHFLT_95 ((uint8_t)0x33) /!< RX Channel Filter Bandwidth = 95.0 kHz /
Wolfgang Betz	67:93bec0baf1de	914	#define CHFLT_90_3 ((uint8_t)0x43) /!< RX Channel Filter Bandwidth = 90.3 kHz /
Wolfgang Betz	67:93bec0baf1de	915	#define CHFLT_85_3 ((uint8_t)0x53) /!< RX Channel Filter Bandwidth = 85.3 kHz /
Wolfgang Betz	67:93bec0baf1de	916	#define CHFLT_81_2 ((uint8_t)0x63) /!< RX Channel Filter Bandwidth = 81.2 kHz /
Wolfgang Betz	67:93bec0baf1de	917	#define CHFLT_73_5 ((uint8_t)0x73) /!< RX Channel Filter Bandwidth = 73.5 kHz /
Wolfgang Betz	67:93bec0baf1de	918	#define CHFLT_67_5 ((uint8_t)0x83) /!< RX Channel Filter Bandwidth = 67.5 kHz /
Wolfgang Betz	67:93bec0baf1de	919	#define CHFLT_56_1 ((uint8_t)0x04) /!< RX Channel Filter Bandwidth = 56.1 kHz /
Wolfgang Betz	67:93bec0baf1de	920	#define CHFLT_53 ((uint8_t)0x14) /!< RX Channel Filter Bandwidth = 53.0 kHz /
Wolfgang Betz	67:93bec0baf1de	921	#define CHFLT_50_2 ((uint8_t)0x24) /!< RX Channel Filter Bandwidth = 50.2 kHz /
Wolfgang Betz	67:93bec0baf1de	922	#define CHFLT_47_4 ((uint8_t)0x34) /!< RX Channel Filter Bandwidth = 47.4 kHz /
Wolfgang Betz	67:93bec0baf1de	923	#define CHFLT_45_1 ((uint8_t)0x44) /!< RX Channel Filter Bandwidth = 45.1 kHz /
Wolfgang Betz	67:93bec0baf1de	924	#define CHFLT_42_6 ((uint8_t)0x54) /!< RX Channel Filter Bandwidth = 42.6 kHz /
Wolfgang Betz	67:93bec0baf1de	925	#define CHFLT_40_6 ((uint8_t)0x64) /!< RX Channel Filter Bandwidth = 40.6 kHz /
Wolfgang Betz	67:93bec0baf1de	926	#define CHFLT_36_7 ((uint8_t)0x74) /!< RX Channel Filter Bandwidth = 36.7 kHz /
Wolfgang Betz	67:93bec0baf1de	927	#define CHFLT_33_7 ((uint8_t)0x84) /!< RX Channel Filter Bandwidth = 33.7 kHz /
Wolfgang Betz	67:93bec0baf1de	928	#define CHFLT_28 ((uint8_t)0x05) /!< RX Channel Filter Bandwidth = 28.0 kHz /
Wolfgang Betz	67:93bec0baf1de	929	#define CHFLT_26_5 ((uint8_t)0x15) /!< RX Channel Filter Bandwidth = 26.5 kHz /
Wolfgang Betz	67:93bec0baf1de	930	#define CHFLT_25_1 ((uint8_t)0x25) /!< RX Channel Filter Bandwidth = 25.1 kHz /
Wolfgang Betz	67:93bec0baf1de	931	#define CHFLT_23_7 ((uint8_t)0x35) /!< RX Channel Filter Bandwidth = 23.7 kHz /
Wolfgang Betz	67:93bec0baf1de	932	#define CHFLT_22_6 ((uint8_t)0x45) /!< RX Channel Filter Bandwidth = 22.6 kHz /
Wolfgang Betz	67:93bec0baf1de	933	#define CHFLT_21_3 ((uint8_t)0x55) /!< RX Channel Filter Bandwidth = 21.3 kHz /
Wolfgang Betz	67:93bec0baf1de	934	#define CHFLT_20_3 ((uint8_t)0x65) /!< RX Channel Filter Bandwidth = 20.3 kHz /
Wolfgang Betz	67:93bec0baf1de	935	#define CHFLT_18_4 ((uint8_t)0x75) /!< RX Channel Filter Bandwidth = 18.4 kHz /
Wolfgang Betz	67:93bec0baf1de	936	#define CHFLT_16_9 ((uint8_t)0x85) /!< RX Channel Filter Bandwidth = 16.9 kHz /
Wolfgang Betz	67:93bec0baf1de	937	#define CHFLT_14 ((uint8_t)0x06) /!< RX Channel Filter Bandwidth = 14.0 kHz /
Wolfgang Betz	67:93bec0baf1de	938	#define CHFLT_13_3 ((uint8_t)0x16) /!< RX Channel Filter Bandwidth = 13.3 kHz /
Wolfgang Betz	67:93bec0baf1de	939	#define CHFLT_12_6 ((uint8_t)0x26) /!< RX Channel Filter Bandwidth = 12.6 kHz /
Wolfgang Betz	67:93bec0baf1de	940	#define CHFLT_11_9 ((uint8_t)0x36) /!< RX Channel Filter Bandwidth = 11.9 kHz /
Wolfgang Betz	67:93bec0baf1de	941	#define CHFLT_11_3 ((uint8_t)0x46) /!< RX Channel Filter Bandwidth = 11.3 kHz /
Wolfgang Betz	67:93bec0baf1de	942	#define CHFLT_10_6 ((uint8_t)0x56) /!< RX Channel Filter Bandwidth = 10.6 kHz /
Wolfgang Betz	67:93bec0baf1de	943	#define CHFLT_10_1 ((uint8_t)0x66) /!< RX Channel Filter Bandwidth = 10.1 kHz /
Wolfgang Betz	67:93bec0baf1de	944	#define CHFLT_9_2 ((uint8_t)0x76) /!< RX Channel Filter Bandwidth = 9.2 kHz /
Wolfgang Betz	67:93bec0baf1de	945	#define CHFLT_8_4 ((uint8_t)0x86) /!< RX Channel Filter Bandwidth = 8.4 kHz /
Wolfgang Betz	67:93bec0baf1de	946	#define CHFLT_7 ((uint8_t)0x07) /!< RX Channel Filter Bandwidth = 7.0 kHz /
Wolfgang Betz	67:93bec0baf1de	947	#define CHFLT_6_6 ((uint8_t)0x17) /!< RX Channel Filter Bandwidth = 6.6 kHz /
Wolfgang Betz	67:93bec0baf1de	948	#define CHFLT_6_3 ((uint8_t)0x27) /!< RX Channel Filter Bandwidth = 6.3 kHz /
Wolfgang Betz	67:93bec0baf1de	949	#define CHFLT_5_9 ((uint8_t)0x37) /!< RX Channel Filter Bandwidth = 5.9 kHz /
Wolfgang Betz	67:93bec0baf1de	950	#define CHFLT_5_6 ((uint8_t)0x47) /!< RX Channel Filter Bandwidth = 5.6 kHz /
Wolfgang Betz	67:93bec0baf1de	951	#define CHFLT_5_3 ((uint8_t)0x57) /!< RX Channel Filter Bandwidth = 5.3 kHz /
Wolfgang Betz	67:93bec0baf1de	952	#define CHFLT_5_1 ((uint8_t)0x67) /!< RX Channel Filter Bandwidth = 5.1 kHz /
Wolfgang Betz	67:93bec0baf1de	953	#define CHFLT_4_6 ((uint8_t)0x77) /!< RX Channel Filter Bandwidth = 4.6 kHz /
Wolfgang Betz	67:93bec0baf1de	954	#define CHFLT_4_2 ((uint8_t)0x87) /!< RX Channel Filter Bandwidth = 4.2 kHz /
Wolfgang Betz	67:93bec0baf1de	955	#define CHFLT_3_5 ((uint8_t)0x08) /!< RX Channel Filter Bandwidth = 3.5 kHz /
Wolfgang Betz	67:93bec0baf1de	956	#define CHFLT_3_3 ((uint8_t)0x18) /!< RX Channel Filter Bandwidth = 3.3 kHz /
Wolfgang Betz	67:93bec0baf1de	957	#define CHFLT_3_1 ((uint8_t)0x28) /!< RX Channel Filter Bandwidth = 3.1 kHz /
Wolfgang Betz	67:93bec0baf1de	958	#define CHFLT_3 ((uint8_t)0x38) /!< RX Channel Filter Bandwidth = 3.0 kHz /
Wolfgang Betz	67:93bec0baf1de	959	#define CHFLT_2_8 ((uint8_t)0x48) /!< RX Channel Filter Bandwidth = 2.8 kHz /
Wolfgang Betz	67:93bec0baf1de	960	#define CHFLT_2_7 ((uint8_t)0x58) /!< RX Channel Filter Bandwidth = 2.7 kHz /
Wolfgang Betz	67:93bec0baf1de	961	#define CHFLT_2_5 ((uint8_t)0x68) /!< RX Channel Filter Bandwidth = 2.5 kHz /
Wolfgang Betz	67:93bec0baf1de	962	#define CHFLT_2_3 ((uint8_t)0x78) /!< RX Channel Filter Bandwidth = 2.3 kHz /
Wolfgang Betz	67:93bec0baf1de	963	#define CHFLT_2_1 ((uint8_t)0x88) /!< RX Channel Filter Bandwidth = 2.1 kHz /
Wolfgang Betz	67:93bec0baf1de	964	#define CHFLT_1_8 ((uint8_t)0x09) /!< RX Channel Filter Bandwidth = 1.8 kHz /
Wolfgang Betz	67:93bec0baf1de	965	#define CHFLT_1_7 ((uint8_t)0x19) /!< RX Channel Filter Bandwidth = 1.7 kHz /
Wolfgang Betz	67:93bec0baf1de	966	#define CHFLT_1_6 ((uint8_t)0x29) /!< RX Channel Filter Bandwidth = 1.6 kHz /
Wolfgang Betz	67:93bec0baf1de	967	#define CHFLT_1_5 ((uint8_t)0x39) /!< RX Channel Filter Bandwidth = 1.5 kHz /
Wolfgang Betz	67:93bec0baf1de	968	#define CHFLT_1_4 ((uint8_t)0x49) /!< RX Channel Filter Bandwidth = 1.4 kHz /
Wolfgang Betz	67:93bec0baf1de	969	#define CHFLT_1_3a ((uint8_t)0x59) /!< RX Channel Filter Bandwidth = 1.3 kHz /
Wolfgang Betz	67:93bec0baf1de	970	#define CHFLT_1_3 ((uint8_t)0x69) /!< RX Channel Filter Bandwidth = 1.3 kHz /
Wolfgang Betz	67:93bec0baf1de	971	#define CHFLT_1_2 ((uint8_t)0x79) /!< RX Channel Filter Bandwidth = 1.2 kHz /
Wolfgang Betz	67:93bec0baf1de	972	#define CHFLT_1_1 ((uint8_t)0x89) /!< RX Channel Filter Bandwidth = 1.1 kHz /
Wolfgang Betz	67:93bec0baf1de	973
Wolfgang Betz	67:93bec0baf1de	974	/**
Wolfgang Betz	67:93bec0baf1de	975	* @}
Wolfgang Betz	67:93bec0baf1de	976	*/
Wolfgang Betz	67:93bec0baf1de	977
Wolfgang Betz	67:93bec0baf1de	978	/** @defgroup AFC2_Register
Wolfgang Betz	67:93bec0baf1de	979	* @{
Wolfgang Betz	67:93bec0baf1de	980	*/
Wolfgang Betz	67:93bec0baf1de	981
Wolfgang Betz	67:93bec0baf1de	982	/**
Wolfgang Betz	67:93bec0baf1de	983	* \brief AFC2 register
Wolfgang Betz	67:93bec0baf1de	984	* \code
Wolfgang Betz	67:93bec0baf1de	985	* Read Write
Wolfgang Betz	67:93bec0baf1de	986	* Default value: 0x48
Wolfgang Betz	67:93bec0baf1de	987	* 7 AFC Freeze on Sync: Freeze AFC correction upon sync word detection.
Wolfgang Betz	67:93bec0baf1de	988	* 1 - AFC Freeze enabled
Wolfgang Betz	67:93bec0baf1de	989	* 0 - AFC Freeze disabled
Wolfgang Betz	67:93bec0baf1de	990	*
Wolfgang Betz	67:93bec0baf1de	991	* 6 AFC Enabled: Enable AFC
Wolfgang Betz	67:93bec0baf1de	992	* 1 - AFC enabled
Wolfgang Betz	67:93bec0baf1de	993	* 0 - AFC disabled
Wolfgang Betz	67:93bec0baf1de	994	*
Wolfgang Betz	67:93bec0baf1de	995	* 5 AFC Mode: Select AFC mode
Wolfgang Betz	67:93bec0baf1de	996	* 1 - AFC Loop closed on 2nd conversion stage.
Wolfgang Betz	67:93bec0baf1de	997	* 0 - AFC Loop closed on slicer
Wolfgang Betz	67:93bec0baf1de	998	*
Wolfgang Betz	67:93bec0baf1de	999	* 4:0 AFC PD leakage[4:0]: Peak detector leakage. This parameter sets the decay speed of the min/max frequency peak detector (AFC2 register),
Wolfgang Betz	67:93bec0baf1de	1000	* the range allowed is 0..31 (0 - no leakage, 31 - high leakage). The recommended value for this parameter is 4.
Wolfgang Betz	67:93bec0baf1de	1001	*
Wolfgang Betz	67:93bec0baf1de	1002	* \endcode
Wolfgang Betz	67:93bec0baf1de	1003	*/
Wolfgang Betz	67:93bec0baf1de	1004	#define AFC2_BASE ((uint8_t)0x1E) /!< Automatic frequency compensation algorithm parameters (FSK/GFSK/MSK)/
Wolfgang Betz	67:93bec0baf1de	1005
Wolfgang Betz	67:93bec0baf1de	1006	#define AFC2_AFC_FREEZE_ON_SYNC_MASK ((uint8_t)0x80) /!< The frequency correction value is frozen when SYNC word is detected /
Wolfgang Betz	67:93bec0baf1de	1007	#define AFC2_AFC_MASK ((uint8_t)0x40) /!< Mask of Automatic Frequency Correction /
Wolfgang Betz	67:93bec0baf1de	1008	#define AFC2_AFC_MODE_MASK ((uint8_t)0x20) /!< Automatic Frequency Correction can be in Main MODE or Auxiliary MODE/
Wolfgang Betz	67:93bec0baf1de	1009	#define AFC2_AFC_MODE_SLICER ((uint8_t)0x00) /!< Automatic Frequency Correction Main MODE /
Wolfgang Betz	67:93bec0baf1de	1010	#define AFC2_AFC_MODE_MIXER ((uint8_t)0x20) /!< Automatic Frequency Correction Auxiliary MODE /
Wolfgang Betz	67:93bec0baf1de	1011
Wolfgang Betz	67:93bec0baf1de	1012	/**
Wolfgang Betz	67:93bec0baf1de	1013	* @}
Wolfgang Betz	67:93bec0baf1de	1014	*/
Wolfgang Betz	67:93bec0baf1de	1015
Wolfgang Betz	67:93bec0baf1de	1016	/** @defgroup AFC1_Register
Wolfgang Betz	67:93bec0baf1de	1017	* @{
Wolfgang Betz	67:93bec0baf1de	1018	*/
Wolfgang Betz	67:93bec0baf1de	1019
Wolfgang Betz	67:93bec0baf1de	1020	/**
Wolfgang Betz	67:93bec0baf1de	1021	* \brief AFC1 register
Wolfgang Betz	67:93bec0baf1de	1022	* \code
Wolfgang Betz	67:93bec0baf1de	1023	* Read Write
Wolfgang Betz	67:93bec0baf1de	1024	* Default value: 0x18
Wolfgang Betz	67:93bec0baf1de	1025	* 7:0 AFC_FAST_PERIOD: Length of the AFC fast period. this parameter sets the length of the fast period in number of samples (AFC1 register), the range allowed
Wolfgang Betz	67:93bec0baf1de	1026	* is 0..255. The recommended setting for this parameter is such that the fast period equals the preamble length. Since the
Wolfgang Betz	67:93bec0baf1de	1027	* algorithm operates typically on 2 samples per symbol, the programmed value should be twice the number of preamble
Wolfgang Betz	67:93bec0baf1de	1028	* symbols.
Wolfgang Betz	67:93bec0baf1de	1029	*
Wolfgang Betz	67:93bec0baf1de	1030	* \endcode
Wolfgang Betz	67:93bec0baf1de	1031	*/
Wolfgang Betz	67:93bec0baf1de	1032	#define AFC1_BASE ((uint8_t)0x1F) /!< Length of the AFC fast period /
Wolfgang Betz	67:93bec0baf1de	1033
Wolfgang Betz	67:93bec0baf1de	1034	/**
Wolfgang Betz	67:93bec0baf1de	1035	* @}
Wolfgang Betz	67:93bec0baf1de	1036	*/
Wolfgang Betz	67:93bec0baf1de	1037
Wolfgang Betz	67:93bec0baf1de	1038	/** @defgroup AFC0_Register
Wolfgang Betz	67:93bec0baf1de	1039	* @{
Wolfgang Betz	67:93bec0baf1de	1040	*/
Wolfgang Betz	67:93bec0baf1de	1041
Wolfgang Betz	67:93bec0baf1de	1042	/**
Wolfgang Betz	67:93bec0baf1de	1043	* \brief AFC0 register
Wolfgang Betz	67:93bec0baf1de	1044	* \code
Wolfgang Betz	67:93bec0baf1de	1045	* Read Write
Wolfgang Betz	67:93bec0baf1de	1046	* Default value: 0x25
Wolfgang Betz	67:93bec0baf1de	1047	* 7:4 AFC_FAST_GAIN_LOG2[3:0]: AFC loop gain in fast mode (2's log)
Wolfgang Betz	67:93bec0baf1de	1048	*
Wolfgang Betz	67:93bec0baf1de	1049	* 3:0 AFC_SLOW_GAIN_LOG2[3:0]: AFC loop gain in slow mode (2's log)
Wolfgang Betz	67:93bec0baf1de	1050	*
Wolfgang Betz	67:93bec0baf1de	1051	* \endcode
Wolfgang Betz	67:93bec0baf1de	1052	*/
Wolfgang Betz	67:93bec0baf1de	1053	#define AFC0_BASE ((uint8_t)0x20) /!< AFC loop gain in fast and slow modes (2's log) /
Wolfgang Betz	67:93bec0baf1de	1054
Wolfgang Betz	67:93bec0baf1de	1055	/**
Wolfgang Betz	67:93bec0baf1de	1056	* @}
Wolfgang Betz	67:93bec0baf1de	1057	*/
Wolfgang Betz	67:93bec0baf1de	1058
Wolfgang Betz	67:93bec0baf1de	1059	/** @defgroup CLOCKREC_Register
Wolfgang Betz	67:93bec0baf1de	1060	* @{
Wolfgang Betz	67:93bec0baf1de	1061	*/
Wolfgang Betz	67:93bec0baf1de	1062
Wolfgang Betz	67:93bec0baf1de	1063	/**
Wolfgang Betz	67:93bec0baf1de	1064	* \brief CLOCKREC register
Wolfgang Betz	67:93bec0baf1de	1065	* \code
Wolfgang Betz	67:93bec0baf1de	1066	* Read Write
Wolfgang Betz	67:93bec0baf1de	1067	* Default value: 0x58
Wolfgang Betz	67:93bec0baf1de	1068	*
Wolfgang Betz	67:93bec0baf1de	1069	* 7:5 CLK_REC_P_GAIN [2:0]: Clock recovery loop gain (log2)
Wolfgang Betz	67:93bec0baf1de	1070	*
Wolfgang Betz	67:93bec0baf1de	1071	* 4 PSTFLT_LEN: Set Postfilter length
Wolfgang Betz	67:93bec0baf1de	1072	* 1 - 16 symbols
Wolfgang Betz	67:93bec0baf1de	1073	* 0 - 8 symbols
Wolfgang Betz	67:93bec0baf1de	1074	*
Wolfgang Betz	67:93bec0baf1de	1075	* 3:0 CLK_REC_I_GAIN[3:0]: Integral gain for the clock recovery loop
Wolfgang Betz	67:93bec0baf1de	1076	* \endcode
Wolfgang Betz	67:93bec0baf1de	1077	*/
Wolfgang Betz	67:93bec0baf1de	1078
Wolfgang Betz	67:93bec0baf1de	1079	#define CLOCKREC_BASE ((uint8_t)0x23) /!< Gain of clock recovery loop - Postfilter length 0-8 symbols, 1-16 symbols /
Wolfgang Betz	67:93bec0baf1de	1080
Wolfgang Betz	67:93bec0baf1de	1081	/**
Wolfgang Betz	67:93bec0baf1de	1082	* @}
Wolfgang Betz	67:93bec0baf1de	1083	*/
Wolfgang Betz	67:93bec0baf1de	1084
Wolfgang Betz	67:93bec0baf1de	1085	/** @defgroup AGCCTRL2_Register
Wolfgang Betz	67:93bec0baf1de	1086	* @{
Wolfgang Betz	67:93bec0baf1de	1087	*/
Wolfgang Betz	67:93bec0baf1de	1088
Wolfgang Betz	67:93bec0baf1de	1089	/**
Wolfgang Betz	67:93bec0baf1de	1090	* \brief AGCCTRL2 register
Wolfgang Betz	67:93bec0baf1de	1091	* \code
Wolfgang Betz	67:93bec0baf1de	1092	* Read Write
Wolfgang Betz	67:93bec0baf1de	1093	* Default value: 0x22
Wolfgang Betz	67:93bec0baf1de	1094	*
Wolfgang Betz	67:93bec0baf1de	1095	* 7 Reserved
Wolfgang Betz	67:93bec0baf1de	1096	*
Wolfgang Betz	67:93bec0baf1de	1097	* 6 FREEZE_ON_STEADY: Enable freezing on steady state
Wolfgang Betz	67:93bec0baf1de	1098	* 1 - Enable
Wolfgang Betz	67:93bec0baf1de	1099	* 0 - Disable
Wolfgang Betz	67:93bec0baf1de	1100	*
Wolfgang Betz	67:93bec0baf1de	1101	* 5 FREEZE_ON_SYNC: Enable freezing on sync detection
Wolfgang Betz	67:93bec0baf1de	1102	* 1 - Enable
Wolfgang Betz	67:93bec0baf1de	1103	* 0 - Disable
Wolfgang Betz	67:93bec0baf1de	1104	*
Wolfgang Betz	67:93bec0baf1de	1105	* 4 START_MAX_ATTENUATION: Start with max attenuation
Wolfgang Betz	67:93bec0baf1de	1106	* 1 - Enable
Wolfgang Betz	67:93bec0baf1de	1107	* 0 - Disable
Wolfgang Betz	67:93bec0baf1de	1108	*
Wolfgang Betz	67:93bec0baf1de	1109	* 3:0 MEAS_TIME[3:0]: Measure time during which the signal peak is detected (according to the formula 12/fxo*2^MEAS_TIME)
Wolfgang Betz	67:93bec0baf1de	1110	* \endcode
Wolfgang Betz	67:93bec0baf1de	1111	*/
Wolfgang Betz	67:93bec0baf1de	1112	#define AGCCTRL2_BASE ((uint8_t)0x24) /!< AGC freeze strategy, AGC attenuation strategy, AGC measure time /
Wolfgang Betz	67:93bec0baf1de	1113
Wolfgang Betz	67:93bec0baf1de	1114	#define AGCCTRL2_FREEZE_ON_STEADY_MASK ((uint8_t)0x40) /*!< The attenuation settings will be frozen as soon as signal level
Wolfgang Betz	67:93bec0baf1de	1115	is betweeen min and max treshold (see AGCCTRL1) */
Wolfgang Betz	67:93bec0baf1de	1116	#define AGCCTRL2_FREEZE_ON_SYNC_MASK ((uint8_t)0x20) /!< The attenuation settings will be frozen as soon sync word is detected /
Wolfgang Betz	67:93bec0baf1de	1117	#define AGCCTRL2_START_MAX_ATTENUATION_MASK ((uint8_t)0x10) /!< The AGC algorithm can start with MAX attenuation or MIN attenuation /
Wolfgang Betz	67:93bec0baf1de	1118
Wolfgang Betz	67:93bec0baf1de	1119	/**
Wolfgang Betz	67:93bec0baf1de	1120	* @}
Wolfgang Betz	67:93bec0baf1de	1121	*/
Wolfgang Betz	67:93bec0baf1de	1122
Wolfgang Betz	67:93bec0baf1de	1123	/** @defgroup AGCCTRL1_Register
Wolfgang Betz	67:93bec0baf1de	1124	* @{
Wolfgang Betz	67:93bec0baf1de	1125	*/
Wolfgang Betz	67:93bec0baf1de	1126
Wolfgang Betz	67:93bec0baf1de	1127	/**
Wolfgang Betz	67:93bec0baf1de	1128	* \brief AGCCTRL1 register
Wolfgang Betz	67:93bec0baf1de	1129	* \code
Wolfgang Betz	67:93bec0baf1de	1130	* Read Write
Wolfgang Betz	67:93bec0baf1de	1131	* Default value: 0x65
Wolfgang Betz	67:93bec0baf1de	1132	*
Wolfgang Betz	67:93bec0baf1de	1133	* 7:4 THRESHOLD_HIGH[3:0]: High threshold for the AGC
Wolfgang Betz	67:93bec0baf1de	1134	*
Wolfgang Betz	67:93bec0baf1de	1135	* 3:0 THRESHOLD_LOW[3:0]: Low threshold for the AGC
Wolfgang Betz	67:93bec0baf1de	1136	* \endcode
Wolfgang Betz	67:93bec0baf1de	1137	*/
Wolfgang Betz	67:93bec0baf1de	1138	#define AGCCTRL1_BASE ((uint8_t)0x25) /!< Sets low and high threshold for AGC /
Wolfgang Betz	67:93bec0baf1de	1139
Wolfgang Betz	67:93bec0baf1de	1140	/**
Wolfgang Betz	67:93bec0baf1de	1141	* @}
Wolfgang Betz	67:93bec0baf1de	1142	*/
Wolfgang Betz	67:93bec0baf1de	1143
Wolfgang Betz	67:93bec0baf1de	1144	/** @defgroup AGCCTRL0_Register
Wolfgang Betz	67:93bec0baf1de	1145	* @{
Wolfgang Betz	67:93bec0baf1de	1146	*/
Wolfgang Betz	67:93bec0baf1de	1147
Wolfgang Betz	67:93bec0baf1de	1148	/**
Wolfgang Betz	67:93bec0baf1de	1149	* \brief AGCCTRL0 register
Wolfgang Betz	67:93bec0baf1de	1150	* \code
Wolfgang Betz	67:93bec0baf1de	1151	* Read Write
Wolfgang Betz	67:93bec0baf1de	1152	* Default value: 0x8A
Wolfgang Betz	67:93bec0baf1de	1153	*
Wolfgang Betz	67:93bec0baf1de	1154	* 7 AGC S_ENABLE: Enable AGC
Wolfgang Betz	67:93bec0baf1de	1155	* 1 - Enable
Wolfgang Betz	67:93bec0baf1de	1156	* 0 - Disable
Wolfgang Betz	67:93bec0baf1de	1157	*
Wolfgang Betz	67:93bec0baf1de	1158	* 6 AGC_MODE: Set linear-Binary AGC mode
Wolfgang Betz	67:93bec0baf1de	1159	* 1 - Enable
Wolfgang Betz	67:93bec0baf1de	1160	* 0 - Disable
Wolfgang Betz	67:93bec0baf1de	1161	*
Wolfgang Betz	67:93bec0baf1de	1162	* 5:0 HOLD_TIME[5:0]: Hold time after gain adjustment according to formula 12/fxo*HOLD_TIME
Wolfgang Betz	67:93bec0baf1de	1163	* \endcode
Wolfgang Betz	67:93bec0baf1de	1164	*/
Wolfgang Betz	67:93bec0baf1de	1165	#define AGCCTRL0_BASE ((uint8_t)0x26) /*!< Enables AGC, set AGC algo between linear/binary mode, set hold time
Wolfgang Betz	67:93bec0baf1de	1166	to account signal propagation through RX chain */
Wolfgang Betz	67:93bec0baf1de	1167	#define AGCCTRL0_AGC_MASK ((uint8_t)0x80) /!< AGC on/off /
Wolfgang Betz	67:93bec0baf1de	1168	#define AGCCTRL0_AGC_MODE_MASK ((uint8_t)0x40) /!< AGC search correct attenuation in binary mode or sequential mode /
Wolfgang Betz	67:93bec0baf1de	1169	#define AGCCTRL0_AGC_MODE_LINEAR ((uint8_t)0x00) /!< AGC search correct attenuation in sequential mode (recommended) /
Wolfgang Betz	67:93bec0baf1de	1170	#define AGCCTRL0_AGC_MODE_BINARY ((uint8_t)0x40) /!< AGC search correct attenuation in binary mode /
Wolfgang Betz	67:93bec0baf1de	1171
Wolfgang Betz	67:93bec0baf1de	1172	/**
Wolfgang Betz	67:93bec0baf1de	1173	* @}
Wolfgang Betz	67:93bec0baf1de	1174	*/
Wolfgang Betz	67:93bec0baf1de	1175
Wolfgang Betz	67:93bec0baf1de	1176	/** @defgroup CHNUM_Register
Wolfgang Betz	67:93bec0baf1de	1177	* @{
Wolfgang Betz	67:93bec0baf1de	1178	*/
Wolfgang Betz	67:93bec0baf1de	1179
Wolfgang Betz	67:93bec0baf1de	1180	/**
Wolfgang Betz	67:93bec0baf1de	1181	* \brief CHNUM registers
Wolfgang Betz	67:93bec0baf1de	1182	* \code
Wolfgang Betz	67:93bec0baf1de	1183	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1184	* Read Write
Wolfgang Betz	67:93bec0baf1de	1185	* 7:0 CH_NUM[7:0]: Channel number. This value is multiplied by the channel spacing and added to the
Wolfgang Betz	67:93bec0baf1de	1186	* synthesizer base frequency to generate the actual RF carrier frequency.
Wolfgang Betz	67:93bec0baf1de	1187	* \endcode
Wolfgang Betz	67:93bec0baf1de	1188	*/
Wolfgang Betz	67:93bec0baf1de	1189	#define CHNUM_BASE ((uint8_t)0x6C) /*!< Channel number. This value is multiplied by the channel
Wolfgang Betz	67:93bec0baf1de	1190	spacing and added to the synthesizer base frequency to generate the actual RF carrier frequency */
Wolfgang Betz	67:93bec0baf1de	1191	/**
Wolfgang Betz	67:93bec0baf1de	1192	* @}
Wolfgang Betz	67:93bec0baf1de	1193	*/
Wolfgang Betz	67:93bec0baf1de	1194
Wolfgang Betz	67:93bec0baf1de	1195	/** @defgroup AFC_CORR_Register
Wolfgang Betz	67:93bec0baf1de	1196	* @{
Wolfgang Betz	67:93bec0baf1de	1197	*/
Wolfgang Betz	67:93bec0baf1de	1198
Wolfgang Betz	67:93bec0baf1de	1199	/**
Wolfgang Betz	67:93bec0baf1de	1200	* \brief AFC_CORR registers
Wolfgang Betz	67:93bec0baf1de	1201	* \code
Wolfgang Betz	67:93bec0baf1de	1202	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1203	* Read
Wolfgang Betz	67:93bec0baf1de	1204	*
Wolfgang Betz	67:93bec0baf1de	1205	* 7:0 AFC_CORR[7:0]: AFC word of the received packet
Wolfgang Betz	67:93bec0baf1de	1206	* \endcode
Wolfgang Betz	67:93bec0baf1de	1207	*/
Wolfgang Betz	67:93bec0baf1de	1208	#define AFC_CORR_BASE ((uint8_t)(0xC4)) /!< AFC word of the received packet /
Wolfgang Betz	67:93bec0baf1de	1209
Wolfgang Betz	67:93bec0baf1de	1210	/**
Wolfgang Betz	67:93bec0baf1de	1211	* @}
Wolfgang Betz	67:93bec0baf1de	1212	*/
Wolfgang Betz	67:93bec0baf1de	1213
Wolfgang Betz	67:93bec0baf1de	1214	/**
Wolfgang Betz	67:93bec0baf1de	1215	* @}
Wolfgang Betz	67:93bec0baf1de	1216	*/
Wolfgang Betz	67:93bec0baf1de	1217
Wolfgang Betz	67:93bec0baf1de	1218
Wolfgang Betz	67:93bec0baf1de	1219	/** @defgroup Packet_Configuration_Registers
Wolfgang Betz	67:93bec0baf1de	1220	* @{
Wolfgang Betz	67:93bec0baf1de	1221	*/
Wolfgang Betz	67:93bec0baf1de	1222
Wolfgang Betz	67:93bec0baf1de	1223	/** @defgroup PCKTCTRL4_Register
Wolfgang Betz	67:93bec0baf1de	1224	* @{
Wolfgang Betz	67:93bec0baf1de	1225	*/
Wolfgang Betz	67:93bec0baf1de	1226
Wolfgang Betz	67:93bec0baf1de	1227	/**
Wolfgang Betz	67:93bec0baf1de	1228	* \brief PCKTCTRL4 register
Wolfgang Betz	67:93bec0baf1de	1229	* \code
Wolfgang Betz	67:93bec0baf1de	1230	* Read Write
Wolfgang Betz	67:93bec0baf1de	1231	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1232	*
Wolfgang Betz	67:93bec0baf1de	1233	* 7:5 NOT_USED.
Wolfgang Betz	67:93bec0baf1de	1234	*
Wolfgang Betz	67:93bec0baf1de	1235	* 4:3 ADDRESS_LEN[1:0]: length of address field in bytes
Wolfgang Betz	67:93bec0baf1de	1236	*
Wolfgang Betz	67:93bec0baf1de	1237	* 2:0 control_len[2:0]: length of control field in bytes
Wolfgang Betz	67:93bec0baf1de	1238	* \endcode
Wolfgang Betz	67:93bec0baf1de	1239	*/
Wolfgang Betz	67:93bec0baf1de	1240	#define PCKTCTRL4_BASE ((uint8_t)0x30) /!< lenghts of address and control field /
Wolfgang Betz	67:93bec0baf1de	1241
Wolfgang Betz	67:93bec0baf1de	1242	#define PCKTCTRL4_ADDRESS_LEN_MASK ((uint8_t)0x18)
Wolfgang Betz	67:93bec0baf1de	1243	#define PCKTCTRL4_CONTROL_LEN_MASK ((uint8_t)0x07)
Wolfgang Betz	67:93bec0baf1de	1244
Wolfgang Betz	67:93bec0baf1de	1245	/**
Wolfgang Betz	67:93bec0baf1de	1246	* @}
Wolfgang Betz	67:93bec0baf1de	1247	*/
Wolfgang Betz	67:93bec0baf1de	1248
Wolfgang Betz	67:93bec0baf1de	1249	/** @defgroup PCKTCTRL3_Register
Wolfgang Betz	67:93bec0baf1de	1250	* @{
Wolfgang Betz	67:93bec0baf1de	1251	*/
Wolfgang Betz	67:93bec0baf1de	1252
Wolfgang Betz	67:93bec0baf1de	1253	/**
Wolfgang Betz	67:93bec0baf1de	1254	* \brief PCKTCTRL3 register
Wolfgang Betz	67:93bec0baf1de	1255	* \code
Wolfgang Betz	67:93bec0baf1de	1256	* Read Write
Wolfgang Betz	67:93bec0baf1de	1257	* Default value: 0x07
Wolfgang Betz	67:93bec0baf1de	1258	*
Wolfgang Betz	67:93bec0baf1de	1259	* 7:6 PCKT_FRMT[1:0]: format of packet
Wolfgang Betz	67:93bec0baf1de	1260	*
Wolfgang Betz	67:93bec0baf1de	1261	* PCKT_FRMT1 \| PCKT_FRMT0 \| Format
Wolfgang Betz	67:93bec0baf1de	1262	* ----------------------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	1263	* 0 \| 0 \| BASIC
Wolfgang Betz	67:93bec0baf1de	1264	* 1 \| 0 \| MBUS
Wolfgang Betz	67:93bec0baf1de	1265	* 1 \| 1 \| STACK
Wolfgang Betz	67:93bec0baf1de	1266	*
Wolfgang Betz	67:93bec0baf1de	1267	* 5:4 RX_MODE[1:0]: length of address 0x30 field in bytes
Wolfgang Betz	67:93bec0baf1de	1268	*
Wolfgang Betz	67:93bec0baf1de	1269	* RX_MODE1 \| RX_MODE0 \| Rx Mode
Wolfgang Betz	67:93bec0baf1de	1270	* --------------------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	1271	* 0 \| 0 \| normal
Wolfgang Betz	67:93bec0baf1de	1272	* 0 \| 1 \| direct through FIFO
Wolfgang Betz	67:93bec0baf1de	1273	* 1 \| 0 \| direct through GPIO
Wolfgang Betz	67:93bec0baf1de	1274	*
Wolfgang Betz	67:93bec0baf1de	1275	* 3:0 LEN_WID[3:0]: length of length field in bits
Wolfgang Betz	67:93bec0baf1de	1276	* \endcode
Wolfgang Betz	67:93bec0baf1de	1277	*/
Wolfgang Betz	67:93bec0baf1de	1278	#define PCKTCTRL3_BASE ((uint8_t)0x31) /!< packet format, RX mode, lenght of length field /
Wolfgang Betz	67:93bec0baf1de	1279
Wolfgang Betz	67:93bec0baf1de	1280	#define PCKTCTRL3_PCKT_FRMT_BASIC ((uint8_t)0x00) /!< Basic Packet Format /
Wolfgang Betz	67:93bec0baf1de	1281	#define PCKTCTRL3_PCKT_FRMT_MBUS ((uint8_t)0x80) /!< Wireless M-BUS Packet Format /
Wolfgang Betz	67:93bec0baf1de	1282	#define PCKTCTRL3_PCKT_FRMT_STACK ((uint8_t)0xC0) /!< STack Packet Format /
Wolfgang Betz	67:93bec0baf1de	1283
Wolfgang Betz	67:93bec0baf1de	1284	#define PCKTCTRL3_RX_MODE_NORMAL ((uint8_t)0x00) /!< Normal RX Mode /
Wolfgang Betz	67:93bec0baf1de	1285	#define PCKTCTRL3_RX_MODE_DIRECT_FIFO ((uint8_t)0x10) /!< RX Direct Mode; data available through FIFO /
Wolfgang Betz	67:93bec0baf1de	1286	#define PCKTCTRL3_RX_MODE_DIRECT_GPIO ((uint8_t)0x20) /!< RX Direct Mode; data available through selected GPIO /
Wolfgang Betz	67:93bec0baf1de	1287
Wolfgang Betz	67:93bec0baf1de	1288	#define PCKTCTRL3_PKT_FRMT_MASK ((uint8_t)0xC0)
Wolfgang Betz	67:93bec0baf1de	1289	#define PCKTCTRL3_RX_MODE_MASK ((uint8_t)0x30)
Wolfgang Betz	67:93bec0baf1de	1290	#define PCKTCTRL3_LEN_WID_MASK ((uint8_t)0x0F)
Wolfgang Betz	67:93bec0baf1de	1291
Wolfgang Betz	67:93bec0baf1de	1292	/**
Wolfgang Betz	67:93bec0baf1de	1293	* @}
Wolfgang Betz	67:93bec0baf1de	1294	*/
Wolfgang Betz	67:93bec0baf1de	1295
Wolfgang Betz	67:93bec0baf1de	1296	/** @defgroup PCKTCTRL2_Register
Wolfgang Betz	67:93bec0baf1de	1297	* @{
Wolfgang Betz	67:93bec0baf1de	1298	*/
Wolfgang Betz	67:93bec0baf1de	1299
Wolfgang Betz	67:93bec0baf1de	1300	/**
Wolfgang Betz	67:93bec0baf1de	1301	* \brief PCKTCTRL2 register
Wolfgang Betz	67:93bec0baf1de	1302	* \code
Wolfgang Betz	67:93bec0baf1de	1303	* Read Write
Wolfgang Betz	67:93bec0baf1de	1304	* Default value: 0x1E
Wolfgang Betz	67:93bec0baf1de	1305	*
Wolfgang Betz	67:93bec0baf1de	1306	* 7:3 PREAMBLE_LENGTH[4:0]: length of preamble field in bytes (0..31)
Wolfgang Betz	67:93bec0baf1de	1307	*
Wolfgang Betz	67:93bec0baf1de	1308	*
Wolfgang Betz	67:93bec0baf1de	1309	* 2:1 SYNC_LENGTH[1:0]: length of sync field in bytes
Wolfgang Betz	67:93bec0baf1de	1310	*
Wolfgang Betz	67:93bec0baf1de	1311	*
Wolfgang Betz	67:93bec0baf1de	1312	* 0 FIX_VAR_LEN: fixed/variable packet length
Wolfgang Betz	67:93bec0baf1de	1313	* 1 - Variable
Wolfgang Betz	67:93bec0baf1de	1314	* 0 - Fixed
Wolfgang Betz	67:93bec0baf1de	1315	* \endcode
Wolfgang Betz	67:93bec0baf1de	1316	*/
Wolfgang Betz	67:93bec0baf1de	1317	#define PCKTCTRL2_BASE ((uint8_t)0x32) /!< length of preamble and sync fields (in bytes), fix or variable packet length /
Wolfgang Betz	67:93bec0baf1de	1318
Wolfgang Betz	67:93bec0baf1de	1319	#define PCKTCTRL2_FIX_VAR_LEN_MASK ((uint8_t)0x01) /!< Enable/disable the length mode /
Wolfgang Betz	67:93bec0baf1de	1320	#define PCKTCTRL2_PREAMBLE_LENGTH_MASK ((uint8_t)0xF8)
Wolfgang Betz	67:93bec0baf1de	1321	#define PCKTCTRL2_SYNC_LENGTH_MASK ((uint8_t)0x06)
Wolfgang Betz	67:93bec0baf1de	1322
Wolfgang Betz	67:93bec0baf1de	1323	/**
Wolfgang Betz	67:93bec0baf1de	1324	* @}
Wolfgang Betz	67:93bec0baf1de	1325	*/
Wolfgang Betz	67:93bec0baf1de	1326
Wolfgang Betz	67:93bec0baf1de	1327	/** @defgroup PCKTCTRL1_Register
Wolfgang Betz	67:93bec0baf1de	1328	* @{
Wolfgang Betz	67:93bec0baf1de	1329	*/
Wolfgang Betz	67:93bec0baf1de	1330
Wolfgang Betz	67:93bec0baf1de	1331	/**
Wolfgang Betz	67:93bec0baf1de	1332	* \brief PCKTCTRL1 register
Wolfgang Betz	67:93bec0baf1de	1333	* \code
Wolfgang Betz	67:93bec0baf1de	1334	* Read Write
Wolfgang Betz	67:93bec0baf1de	1335	* Default value: 0x20
Wolfgang Betz	67:93bec0baf1de	1336	*
Wolfgang Betz	67:93bec0baf1de	1337	* 7:5 CRC_MODE[2:0]: CRC type (0, 8, 16, 24 bits)
Wolfgang Betz	67:93bec0baf1de	1338	*
Wolfgang Betz	67:93bec0baf1de	1339	* CRC_MODE2 \| CRC_MODE1 \| CRC_MODE0 \| CRC Mode (n. bits - poly)
Wolfgang Betz	67:93bec0baf1de	1340	* -------------------------------------------------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	1341	* 0 \| 0 \| 1 \| 8 - 0x07
Wolfgang Betz	67:93bec0baf1de	1342	* 0 \| 1 \| 0 \| 16 - 0x8005
Wolfgang Betz	67:93bec0baf1de	1343	* 0 \| 1 \| 1 \| 16 - 0x1021
Wolfgang Betz	67:93bec0baf1de	1344	* 1 \| 0 \| 0 \| 24 - 0x864CBF
Wolfgang Betz	67:93bec0baf1de	1345	*
Wolfgang Betz	67:93bec0baf1de	1346	* 4 WHIT_EN[0]: Enable Whitening
Wolfgang Betz	67:93bec0baf1de	1347	* 1 - Enable
Wolfgang Betz	67:93bec0baf1de	1348	* 0 - Disable
Wolfgang Betz	67:93bec0baf1de	1349	*
Wolfgang Betz	67:93bec0baf1de	1350	* 3:2 TX_SOURCE[1:0]: length of sync field in bytes
Wolfgang Betz	67:93bec0baf1de	1351	*
Wolfgang Betz	67:93bec0baf1de	1352	* TX_SOURCE1 \| TX_SOURCE0 \| Tx Mode
Wolfgang Betz	67:93bec0baf1de	1353	* --------------------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	1354	* 0 \| 0 \| normal
Wolfgang Betz	67:93bec0baf1de	1355	* 0 \| 1 \| direct through FIFO
Wolfgang Betz	67:93bec0baf1de	1356	* 1 \| 0 \| direct through GPIO
Wolfgang Betz	67:93bec0baf1de	1357	* 1 \| 1 \| pn9
Wolfgang Betz	67:93bec0baf1de	1358	*
Wolfgang Betz	67:93bec0baf1de	1359	* 1 NOT_USED
Wolfgang Betz	67:93bec0baf1de	1360	*
Wolfgang Betz	67:93bec0baf1de	1361	* 0 FEC_EN: enable FEC
Wolfgang Betz	67:93bec0baf1de	1362	* 1 - FEC in TX , Viterbi decoding in RX
Wolfgang Betz	67:93bec0baf1de	1363	* 0 - Disabled
Wolfgang Betz	67:93bec0baf1de	1364	* \endcode
Wolfgang Betz	67:93bec0baf1de	1365	*/
Wolfgang Betz	67:93bec0baf1de	1366	#define PCKTCTRL1_BASE ((uint8_t)0x33) /!< CRC type, whitening enable, TX mode /
Wolfgang Betz	67:93bec0baf1de	1367
Wolfgang Betz	67:93bec0baf1de	1368	#define PCKTCTRL1_FEC_MASK ((uint8_t)0x01) /!< Enable/disable the Forward Error Correction /
Wolfgang Betz	67:93bec0baf1de	1369	#define PCKTCTRL1_TX_SOURCE_MASK ((uint8_t)0x0C) /!< TX source mode /
Wolfgang Betz	67:93bec0baf1de	1370	#define PCKTCTRL1_CRC_MODE_MASK ((uint8_t)0xE0) /!< CRC type /
Wolfgang Betz	67:93bec0baf1de	1371	#define PCKTCTRL1_WHIT_MASK ((uint8_t)0x10) /!< Enable/disable the Whitening /
Wolfgang Betz	67:93bec0baf1de	1372
Wolfgang Betz	67:93bec0baf1de	1373	/**
Wolfgang Betz	67:93bec0baf1de	1374	* @}
Wolfgang Betz	67:93bec0baf1de	1375	*/
Wolfgang Betz	67:93bec0baf1de	1376
Wolfgang Betz	67:93bec0baf1de	1377
Wolfgang Betz	67:93bec0baf1de	1378
Wolfgang Betz	67:93bec0baf1de	1379	/** @defgroup PCKTLEN1_Register
Wolfgang Betz	67:93bec0baf1de	1380	* @{
Wolfgang Betz	67:93bec0baf1de	1381	*/
Wolfgang Betz	67:93bec0baf1de	1382
Wolfgang Betz	67:93bec0baf1de	1383	/**
Wolfgang Betz	67:93bec0baf1de	1384	* \brief PCKTLEN1 register
Wolfgang Betz	67:93bec0baf1de	1385	* \code
Wolfgang Betz	67:93bec0baf1de	1386	* Read Write
Wolfgang Betz	67:93bec0baf1de	1387	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1388	*
Wolfgang Betz	67:93bec0baf1de	1389	* 7:0 pktlen1[7:0]: lenght of packet in bytes (upper field) LENGHT/256
Wolfgang Betz	67:93bec0baf1de	1390	* \endcode
Wolfgang Betz	67:93bec0baf1de	1391	*/
Wolfgang Betz	67:93bec0baf1de	1392	#define PCKTLEN1_BASE ((uint8_t)0x34) /!< lenght of packet in bytes (upper field) /
Wolfgang Betz	67:93bec0baf1de	1393
Wolfgang Betz	67:93bec0baf1de	1394	/**
Wolfgang Betz	67:93bec0baf1de	1395	* @}
Wolfgang Betz	67:93bec0baf1de	1396	*/
Wolfgang Betz	67:93bec0baf1de	1397
Wolfgang Betz	67:93bec0baf1de	1398	/** @defgroup PCKTLEN0_Register
Wolfgang Betz	67:93bec0baf1de	1399	* @{
Wolfgang Betz	67:93bec0baf1de	1400	*/
Wolfgang Betz	67:93bec0baf1de	1401
Wolfgang Betz	67:93bec0baf1de	1402	/**
Wolfgang Betz	67:93bec0baf1de	1403	* \brief PCKTLEN0 register
Wolfgang Betz	67:93bec0baf1de	1404	* \code
Wolfgang Betz	67:93bec0baf1de	1405	* Read Write
Wolfgang Betz	67:93bec0baf1de	1406	* Default value: 0x14
Wolfgang Betz	67:93bec0baf1de	1407	*
Wolfgang Betz	67:93bec0baf1de	1408	* 7:0 pktlen0[7:0]: lenght of packet in bytes (lower field) LENGHT%256
Wolfgang Betz	67:93bec0baf1de	1409	* \endcode
Wolfgang Betz	67:93bec0baf1de	1410	*/
Wolfgang Betz	67:93bec0baf1de	1411	#define PCKTLEN0_BASE ((uint8_t)0x35) /!< lenght of packet in bytes (lower field) [PCKTLEN=PCKTLEN1x256+PCKTLEN0]/
Wolfgang Betz	67:93bec0baf1de	1412
Wolfgang Betz	67:93bec0baf1de	1413	/**
Wolfgang Betz	67:93bec0baf1de	1414	* @}
Wolfgang Betz	67:93bec0baf1de	1415	*/
Wolfgang Betz	67:93bec0baf1de	1416
Wolfgang Betz	67:93bec0baf1de	1417	/** @defgroup SYNCx_Registers
Wolfgang Betz	67:93bec0baf1de	1418	* @{
Wolfgang Betz	67:93bec0baf1de	1419	*/
Wolfgang Betz	67:93bec0baf1de	1420	/**
Wolfgang Betz	67:93bec0baf1de	1421	* \brief SYNCx[4:1] Registers
Wolfgang Betz	67:93bec0baf1de	1422	* \code
Wolfgang Betz	67:93bec0baf1de	1423	* Read Write
Wolfgang Betz	67:93bec0baf1de	1424	* Default value: 0x88
Wolfgang Betz	67:93bec0baf1de	1425	*
Wolfgang Betz	67:93bec0baf1de	1426	* 7:0 SYNCx[7:0]: xth sync word
Wolfgang Betz	67:93bec0baf1de	1427	* \endcode
Wolfgang Betz	67:93bec0baf1de	1428	*/
Wolfgang Betz	67:93bec0baf1de	1429	#define SYNC4_BASE ((uint8_t)0x36) /!< Sync word 4 /
Wolfgang Betz	67:93bec0baf1de	1430	#define SYNC3_BASE ((uint8_t)0x37) /!< Sync word 3 /
Wolfgang Betz	67:93bec0baf1de	1431	#define SYNC2_BASE ((uint8_t)0x38) /!< Sync word 2 /
Wolfgang Betz	67:93bec0baf1de	1432	#define SYNC1_BASE ((uint8_t)0x39) /!< Sync word 1 /
Wolfgang Betz	67:93bec0baf1de	1433
Wolfgang Betz	67:93bec0baf1de	1434	/**
Wolfgang Betz	67:93bec0baf1de	1435	* @}
Wolfgang Betz	67:93bec0baf1de	1436	*/
Wolfgang Betz	67:93bec0baf1de	1437
Wolfgang Betz	67:93bec0baf1de	1438
Wolfgang Betz	67:93bec0baf1de	1439	/** @defgroup MBUS_PRMBL_Register
Wolfgang Betz	67:93bec0baf1de	1440	* @{
Wolfgang Betz	67:93bec0baf1de	1441	*/
Wolfgang Betz	67:93bec0baf1de	1442
Wolfgang Betz	67:93bec0baf1de	1443	/**
Wolfgang Betz	67:93bec0baf1de	1444	* \brief MBUS_PRMBL register
Wolfgang Betz	67:93bec0baf1de	1445	* \code
Wolfgang Betz	67:93bec0baf1de	1446	* Read Write
Wolfgang Betz	67:93bec0baf1de	1447	* Default value: 0x20
Wolfgang Betz	67:93bec0baf1de	1448	*
Wolfgang Betz	67:93bec0baf1de	1449	* 7:0 MBUS_PRMBL[7:0]: MBUS preamble control
Wolfgang Betz	67:93bec0baf1de	1450	* \endcode
Wolfgang Betz	67:93bec0baf1de	1451	*/
Wolfgang Betz	67:93bec0baf1de	1452	#define MBUS_PRMBL_BASE ((uint8_t)0x3B) /!< MBUS preamble lenght (in 01 bit pairs) /
Wolfgang Betz	67:93bec0baf1de	1453
Wolfgang Betz	67:93bec0baf1de	1454	/**
Wolfgang Betz	67:93bec0baf1de	1455	* @}
Wolfgang Betz	67:93bec0baf1de	1456	*/
Wolfgang Betz	67:93bec0baf1de	1457
Wolfgang Betz	67:93bec0baf1de	1458
Wolfgang Betz	67:93bec0baf1de	1459	/** @defgroup MBUS_PSTMBL_Register
Wolfgang Betz	67:93bec0baf1de	1460	* @{
Wolfgang Betz	67:93bec0baf1de	1461	*/
Wolfgang Betz	67:93bec0baf1de	1462
Wolfgang Betz	67:93bec0baf1de	1463	/**
Wolfgang Betz	67:93bec0baf1de	1464	* \brief MBUS_PSTMBL register
Wolfgang Betz	67:93bec0baf1de	1465	* \code
Wolfgang Betz	67:93bec0baf1de	1466	* Read Write
Wolfgang Betz	67:93bec0baf1de	1467	* Default value: 0x20
Wolfgang Betz	67:93bec0baf1de	1468	*
Wolfgang Betz	67:93bec0baf1de	1469	* 7:0 MBUS_PSTMBL[7:0]: MBUS postamble control
Wolfgang Betz	67:93bec0baf1de	1470	* \endcode
Wolfgang Betz	67:93bec0baf1de	1471	*/
Wolfgang Betz	67:93bec0baf1de	1472	#define MBUS_PSTMBL_BASE ((uint8_t)0x3C) /!< MBUS postamble length (in 01 bit pairs) /
Wolfgang Betz	67:93bec0baf1de	1473
Wolfgang Betz	67:93bec0baf1de	1474	/**
Wolfgang Betz	67:93bec0baf1de	1475	* @}
Wolfgang Betz	67:93bec0baf1de	1476	*/
Wolfgang Betz	67:93bec0baf1de	1477
Wolfgang Betz	67:93bec0baf1de	1478	/** @defgroup MBUS_CTRL_Register
Wolfgang Betz	67:93bec0baf1de	1479	* @{
Wolfgang Betz	67:93bec0baf1de	1480	*/
Wolfgang Betz	67:93bec0baf1de	1481
Wolfgang Betz	67:93bec0baf1de	1482	/**
Wolfgang Betz	67:93bec0baf1de	1483	* \brief MBUS_CTRL register
Wolfgang Betz	67:93bec0baf1de	1484	* \code
Wolfgang Betz	67:93bec0baf1de	1485	* Read Write
Wolfgang Betz	67:93bec0baf1de	1486	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1487	*
Wolfgang Betz	67:93bec0baf1de	1488	* 7:4 NOT_USED
Wolfgang Betz	67:93bec0baf1de	1489	*
Wolfgang Betz	67:93bec0baf1de	1490	* 3:1 MBUS_SUBMODE[2:0]: MBUS submode (allowed values are 0,1,3,5)
Wolfgang Betz	67:93bec0baf1de	1491	*
Wolfgang Betz	67:93bec0baf1de	1492	* 0 NOT_USED
Wolfgang Betz	67:93bec0baf1de	1493	* \endcode
Wolfgang Betz	67:93bec0baf1de	1494	*/
Wolfgang Betz	67:93bec0baf1de	1495	#define MBUS_CTRL_BASE ((uint8_t)0x3D) /!< MBUS sub-modes (S1, S2 short/long header, T1, T2, R2) /
Wolfgang Betz	67:93bec0baf1de	1496
Wolfgang Betz	67:93bec0baf1de	1497	#define MBUS_CTRL_MBUS_SUBMODE_S1_S2L ((uint8_t)0x00) /!< MBUS sub-modes S1 & S2L, header lenght min 279, sync 0x7696, Manchester /
Wolfgang Betz	67:93bec0baf1de	1498	#define MBUS_CTRL_MBUS_SUBMODE_S2_S1M_T2_OTHER ((uint8_t)0x02) /!< MBUS sub-modes S2, S1-m, T2 (only other to meter) short header, header lenght min 15, sync 0x7696, Manchester /
Wolfgang Betz	67:93bec0baf1de	1499	#define MBUS_CTRL_MBUS_SUBMODE_T1_T2_METER ((uint8_t)0x06) /!< MBUS sub-modes T1, T2 (only meter to other), header lenght min 19, sync 0x3D, 3 out of 6 /
Wolfgang Betz	67:93bec0baf1de	1500	#define MBUS_CTRL_MBUS_SUBMODE_R2 ((uint8_t)0x0A) /!< MBUS sub-mode R2, header lenght min 39, sync 0x7696, Manchester /
Wolfgang Betz	67:93bec0baf1de	1501
Wolfgang Betz	67:93bec0baf1de	1502	/**
Wolfgang Betz	67:93bec0baf1de	1503	* @}
Wolfgang Betz	67:93bec0baf1de	1504	*/
Wolfgang Betz	67:93bec0baf1de	1505
Wolfgang Betz	67:93bec0baf1de	1506
Wolfgang Betz	67:93bec0baf1de	1507
Wolfgang Betz	67:93bec0baf1de	1508	/** @defgroup PCKT_FLT_GOALS_CONTROLx_MASK_Registers
Wolfgang Betz	67:93bec0baf1de	1509	* @{
Wolfgang Betz	67:93bec0baf1de	1510	*/
Wolfgang Betz	67:93bec0baf1de	1511
Wolfgang Betz	67:93bec0baf1de	1512	/**
Wolfgang Betz	67:93bec0baf1de	1513	* \brief PCKT_FLT_GOALS_CONTROLx_MASK registers
Wolfgang Betz	67:93bec0baf1de	1514	* \code
Wolfgang Betz	67:93bec0baf1de	1515	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1516	* Read Write
Wolfgang Betz	67:93bec0baf1de	1517	* 7:0 CONTROLx_MASK[7:0]: All 0s - no filtering
Wolfgang Betz	67:93bec0baf1de	1518	*
Wolfgang Betz	67:93bec0baf1de	1519	* \endcode
Wolfgang Betz	67:93bec0baf1de	1520	*/
Wolfgang Betz	67:93bec0baf1de	1521	#define PCKT_FLT_GOALS_CONTROL0_MASK_BASE ((uint8_t)0x42) /!< Packet control field #3 mask, all 0s -> no filtering /
Wolfgang Betz	67:93bec0baf1de	1522
Wolfgang Betz	67:93bec0baf1de	1523	#define PCKT_FLT_GOALS_CONTROL1_MASK_BASE ((uint8_t)0x43) /!< Packet control field #2 mask, all 0s -> no filtering /
Wolfgang Betz	67:93bec0baf1de	1524
Wolfgang Betz	67:93bec0baf1de	1525	#define PCKT_FLT_GOALS_CONTROL2_MASK_BASE ((uint8_t)0x44) /!< Packet control field #1 mask, all 0s -> no filtering /
Wolfgang Betz	67:93bec0baf1de	1526
Wolfgang Betz	67:93bec0baf1de	1527	#define PCKT_FLT_GOALS_CONTROL3_MASK_BASE ((uint8_t)0x45) /!< Packet control field #0 mask, all 0s -> no filtering /
Wolfgang Betz	67:93bec0baf1de	1528
Wolfgang Betz	67:93bec0baf1de	1529	/**
Wolfgang Betz	67:93bec0baf1de	1530	* @}
Wolfgang Betz	67:93bec0baf1de	1531	*/
Wolfgang Betz	67:93bec0baf1de	1532
Wolfgang Betz	67:93bec0baf1de	1533	/** @defgroup PCKT_FLT_GOALS_CONTROLx_FIELD_Registers
Wolfgang Betz	67:93bec0baf1de	1534	* @{
Wolfgang Betz	67:93bec0baf1de	1535	*/
Wolfgang Betz	67:93bec0baf1de	1536
Wolfgang Betz	67:93bec0baf1de	1537	/**
Wolfgang Betz	67:93bec0baf1de	1538	* \brief PCKT_FLT_GOALS_CONTROLx_FIELD registers
Wolfgang Betz	67:93bec0baf1de	1539	* \code
Wolfgang Betz	67:93bec0baf1de	1540	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1541	* Read Write
Wolfgang Betz	67:93bec0baf1de	1542	* 7:0 CONTROLx_FIELD[7:0]: Control field (byte x) to be used as reference
Wolfgang Betz	67:93bec0baf1de	1543	*
Wolfgang Betz	67:93bec0baf1de	1544	* \endcode
Wolfgang Betz	67:93bec0baf1de	1545	*/
Wolfgang Betz	67:93bec0baf1de	1546	#define PCKT_FLT_GOALS_CONTROL0_FIELD_BASE ((uint8_t)0x46) /!< Control field (byte #3) /
Wolfgang Betz	67:93bec0baf1de	1547
Wolfgang Betz	67:93bec0baf1de	1548	#define PCKT_FLT_GOALS_CONTROL1_FIELD_BASE ((uint8_t)0x47) /!< Control field (byte #2) /
Wolfgang Betz	67:93bec0baf1de	1549
Wolfgang Betz	67:93bec0baf1de	1550	#define PCKT_FLT_GOALS_CONTROL2_FIELD_BASE ((uint8_t)0x48) /!< Control field (byte #1) /
Wolfgang Betz	67:93bec0baf1de	1551
Wolfgang Betz	67:93bec0baf1de	1552	#define PCKT_FLT_GOALS_CONTROL3_FIELD_BASE ((uint8_t)0x49) /!< Control field (byte #0) /
Wolfgang Betz	67:93bec0baf1de	1553
Wolfgang Betz	67:93bec0baf1de	1554	/**
Wolfgang Betz	67:93bec0baf1de	1555	* @}
Wolfgang Betz	67:93bec0baf1de	1556	*/
Wolfgang Betz	67:93bec0baf1de	1557
Wolfgang Betz	67:93bec0baf1de	1558	/** @defgroup PCKT_FLT_GOALS_SOURCE_MASK_Register
Wolfgang Betz	67:93bec0baf1de	1559	* @{
Wolfgang Betz	67:93bec0baf1de	1560	*/
Wolfgang Betz	67:93bec0baf1de	1561
Wolfgang Betz	67:93bec0baf1de	1562	/**
Wolfgang Betz	67:93bec0baf1de	1563	* \brief PCKT_FLT_GOALS_SOURCE_MASK register
Wolfgang Betz	67:93bec0baf1de	1564	* \code
Wolfgang Betz	67:93bec0baf1de	1565	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1566	* Read Write
Wolfgang Betz	67:93bec0baf1de	1567	* 7:0 RX_SOURCE_MASK[7:0]: For received packet only: all 0s - no filtering
Wolfgang Betz	67:93bec0baf1de	1568	*
Wolfgang Betz	67:93bec0baf1de	1569	* \endcode
Wolfgang Betz	67:93bec0baf1de	1570	*/
Wolfgang Betz	67:93bec0baf1de	1571	#define PCKT_FLT_GOALS_SOURCE_MASK_BASE ((uint8_t)0x4A) /!< Source address mask, valid in RX mode /
Wolfgang Betz	67:93bec0baf1de	1572
Wolfgang Betz	67:93bec0baf1de	1573	/**
Wolfgang Betz	67:93bec0baf1de	1574	* @}
Wolfgang Betz	67:93bec0baf1de	1575	*/
Wolfgang Betz	67:93bec0baf1de	1576
Wolfgang Betz	67:93bec0baf1de	1577	/** @defgroup PCKT_FLT_GOALS_SOURCE_ADDR_Register
Wolfgang Betz	67:93bec0baf1de	1578	* @{
Wolfgang Betz	67:93bec0baf1de	1579	*/
Wolfgang Betz	67:93bec0baf1de	1580	/**
Wolfgang Betz	67:93bec0baf1de	1581	* \brief PCKT_FLT_GOALS_SOURCE_ADDR register
Wolfgang Betz	67:93bec0baf1de	1582	* \code
Wolfgang Betz	67:93bec0baf1de	1583	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1584	* Read Write
Wolfgang Betz	67:93bec0baf1de	1585	* 7:0 RX_SOURCE_ADDR[7:0]: RX packet source / TX packet destination fields
Wolfgang Betz	67:93bec0baf1de	1586	*
Wolfgang Betz	67:93bec0baf1de	1587	* \endcode
Wolfgang Betz	67:93bec0baf1de	1588	*/
Wolfgang Betz	67:93bec0baf1de	1589	#define PCKT_FLT_GOALS_SOURCE_ADDR_BASE ((uint8_t)0x4B) /!< Source address /
Wolfgang Betz	67:93bec0baf1de	1590
Wolfgang Betz	67:93bec0baf1de	1591	/**
Wolfgang Betz	67:93bec0baf1de	1592	* @}
Wolfgang Betz	67:93bec0baf1de	1593	*/
Wolfgang Betz	67:93bec0baf1de	1594
Wolfgang Betz	67:93bec0baf1de	1595	/** @defgroup PCKT_FLT_GOALS_BROADCAST_Register
Wolfgang Betz	67:93bec0baf1de	1596	* @{
Wolfgang Betz	67:93bec0baf1de	1597	*/
Wolfgang Betz	67:93bec0baf1de	1598
Wolfgang Betz	67:93bec0baf1de	1599	/**
Wolfgang Betz	67:93bec0baf1de	1600	* \brief PCKT_FLT_GOALS_BROADCAST register
Wolfgang Betz	67:93bec0baf1de	1601	* \code
Wolfgang Betz	67:93bec0baf1de	1602	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1603	* Read Write
Wolfgang Betz	67:93bec0baf1de	1604	* 7:0 BROADCAST[7:0]: Address shared for broadcast communication link
Wolfgang Betz	67:93bec0baf1de	1605	*
Wolfgang Betz	67:93bec0baf1de	1606	* \endcode
Wolfgang Betz	67:93bec0baf1de	1607	*/
Wolfgang Betz	67:93bec0baf1de	1608	#define PCKT_FLT_GOALS_BROADCAST_BASE ((uint8_t)0x4C) /!< Address shared for broadcast communication links /
Wolfgang Betz	67:93bec0baf1de	1609
Wolfgang Betz	67:93bec0baf1de	1610	/**
Wolfgang Betz	67:93bec0baf1de	1611	* @}
Wolfgang Betz	67:93bec0baf1de	1612	*/
Wolfgang Betz	67:93bec0baf1de	1613
Wolfgang Betz	67:93bec0baf1de	1614	/** @defgroup PCKT_FLT_GOALS_MULTICAST_Register
Wolfgang Betz	67:93bec0baf1de	1615	* @{
Wolfgang Betz	67:93bec0baf1de	1616	*/
Wolfgang Betz	67:93bec0baf1de	1617
Wolfgang Betz	67:93bec0baf1de	1618	/**
Wolfgang Betz	67:93bec0baf1de	1619	* \brief PCKT_FLT_GOALS_MULTICAST register
Wolfgang Betz	67:93bec0baf1de	1620	* \code
Wolfgang Betz	67:93bec0baf1de	1621	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1622	* Read Write
Wolfgang Betz	67:93bec0baf1de	1623	* 7:0 MULTICAST[7:0]: Address shared for multicast communication links
Wolfgang Betz	67:93bec0baf1de	1624	*
Wolfgang Betz	67:93bec0baf1de	1625	* \endcode
Wolfgang Betz	67:93bec0baf1de	1626	*/
Wolfgang Betz	67:93bec0baf1de	1627	#define PCKT_FLT_GOALS_MULTICAST_BASE ((uint8_t)0x4D) /!< Address shared for multicast communication links /
Wolfgang Betz	67:93bec0baf1de	1628
Wolfgang Betz	67:93bec0baf1de	1629	/**
Wolfgang Betz	67:93bec0baf1de	1630	* @}
Wolfgang Betz	67:93bec0baf1de	1631	*/
Wolfgang Betz	67:93bec0baf1de	1632
Wolfgang Betz	67:93bec0baf1de	1633	/** @defgroup PCKT_FLT_GOALS_TX_SOURCE_ADDR_Register
Wolfgang Betz	67:93bec0baf1de	1634	* @{
Wolfgang Betz	67:93bec0baf1de	1635	*/
Wolfgang Betz	67:93bec0baf1de	1636
Wolfgang Betz	67:93bec0baf1de	1637	/**
Wolfgang Betz	67:93bec0baf1de	1638	* \brief PCKT_FLT_GOALS_TX_SOURCE_ADDR register
Wolfgang Betz	67:93bec0baf1de	1639	* \code
Wolfgang Betz	67:93bec0baf1de	1640	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1641	* Read Write
Wolfgang Betz	67:93bec0baf1de	1642	* 7:0 TX_SOURCE_ADDR[7:0]: TX packet source / RX packet destination fields
Wolfgang Betz	67:93bec0baf1de	1643	*
Wolfgang Betz	67:93bec0baf1de	1644	* \endcode
Wolfgang Betz	67:93bec0baf1de	1645	*/
Wolfgang Betz	67:93bec0baf1de	1646	#define PCKT_FLT_GOALS_TX_ADDR_BASE ((uint8_t)0x4E) /!< Address of the destination (also device own address) /
Wolfgang Betz	67:93bec0baf1de	1647
Wolfgang Betz	67:93bec0baf1de	1648	/**
Wolfgang Betz	67:93bec0baf1de	1649	* @}
Wolfgang Betz	67:93bec0baf1de	1650	*/
Wolfgang Betz	67:93bec0baf1de	1651
Wolfgang Betz	67:93bec0baf1de	1652	/** @defgroup PCKT_FLT_OPTIONS_Register
Wolfgang Betz	67:93bec0baf1de	1653	* @{
Wolfgang Betz	67:93bec0baf1de	1654	*/
Wolfgang Betz	67:93bec0baf1de	1655
Wolfgang Betz	67:93bec0baf1de	1656	/**
Wolfgang Betz	67:93bec0baf1de	1657	* \brief PCKT_FLT_OPTIONS register
Wolfgang Betz	67:93bec0baf1de	1658	* \code
Wolfgang Betz	67:93bec0baf1de	1659	* Default value: 0x70
Wolfgang Betz	67:93bec0baf1de	1660	* Read Write
Wolfgang Betz	67:93bec0baf1de	1661	* 7 Reserved.
Wolfgang Betz	67:93bec0baf1de	1662	*
Wolfgang Betz	67:93bec0baf1de	1663	* 6 RX_TIMEOUT_AND_OR_SELECT[0]: 1 - OR logical function applied to CS/SQI/PQI
Wolfgang Betz	67:93bec0baf1de	1664	* values (masked by 7:5 bits in PROTOCOL register)
Wolfgang Betz	67:93bec0baf1de	1665	* 5 CONTROL_FILTERING[0]: 1 - RX packet accepted if its control fields matches
Wolfgang Betz	67:93bec0baf1de	1666	* with masked CONTROLx_FIELD registers.
Wolfgang Betz	67:93bec0baf1de	1667	* 4 SOURCE_FILTERING[0]: 1 - RX packet accepted if its source field
Wolfgang Betz	67:93bec0baf1de	1668	* matches w/ masked RX_SOURCE_ADDR register.
Wolfgang Betz	67:93bec0baf1de	1669	* 3 DEST_VS_ SOURCE _ADDR[0]: 1 - RX packet accepted if its destination
Wolfgang Betz	67:93bec0baf1de	1670	* address matches with TX_SOURCE_ADDR reg.
Wolfgang Betz	67:93bec0baf1de	1671	* 2 DEST_VS_MULTICAST_ADDR[0]: 1 - RX packet accepted if its destination
Wolfgang Betz	67:93bec0baf1de	1672	* address matches with MULTICAST register
Wolfgang Betz	67:93bec0baf1de	1673	* 1 DEST_VS_BROADCAST_ADDR[0]: 1 - RX packet accepted if its destination
Wolfgang Betz	67:93bec0baf1de	1674	* address matches with BROADCAST register.
Wolfgang Betz	67:93bec0baf1de	1675	* 0 CRC_CHECK[0]: 1 - packet discarded if CRC not valid.
Wolfgang Betz	67:93bec0baf1de	1676	*
Wolfgang Betz	67:93bec0baf1de	1677	* \endcode
Wolfgang Betz	67:93bec0baf1de	1678	*/
Wolfgang Betz	67:93bec0baf1de	1679	#define PCKT_FLT_OPTIONS_BASE ((uint8_t)0x4F) /!< Options relative to packet filtering /
Wolfgang Betz	67:93bec0baf1de	1680
Wolfgang Betz	67:93bec0baf1de	1681	#define PCKT_FLT_OPTIONS_CRC_CHECK_MASK ((uint8_t)0x01) /!< Enable/disable of CRC check: packet is discarded if CRC is not valid [RX] /
Wolfgang Betz	67:93bec0baf1de	1682	#define PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK ((uint8_t)0x02) /!< Packet discarded if destination address differs from BROADCAST register [RX] /
Wolfgang Betz	67:93bec0baf1de	1683	#define PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK ((uint8_t)0x04) /!< Packet discarded if destination address differs from MULTICAST register [RX] /
Wolfgang Betz	67:93bec0baf1de	1684	#define PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK ((uint8_t)0x08) /!< Packet discarded if destination address differs from TX_ADDR register [RX] /
Wolfgang Betz	67:93bec0baf1de	1685	#define PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK ((uint8_t)0x10) /*!< Packet discarded if source address (masked by the SOURCE_MASK register)
Wolfgang Betz	67:93bec0baf1de	1686	differs from SOURCE_ADDR register [RX] */
Wolfgang Betz	67:93bec0baf1de	1687	#define PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK ((uint8_t)0x20) /*!< Packet discarded if the x-byte (x=1¸4) control field (masked by the CONTROLx_MASK register)
Wolfgang Betz	67:93bec0baf1de	1688	differs from CONTROLx_FIELD register [RX] */
Wolfgang Betz	67:93bec0baf1de	1689	#define PCKT_FLT_OPTIONS_RX_TIMEOUT_AND_OR_SELECT ((uint8_t)0x40) /*!< Logical function applied to CS/SQI/PQI values (masked by [7:5] bits in PROTOCOL[2]
Wolfgang Betz	67:93bec0baf1de	1690	register) */
Wolfgang Betz	67:93bec0baf1de	1691
Wolfgang Betz	67:93bec0baf1de	1692	/**
Wolfgang Betz	67:93bec0baf1de	1693	* @}
Wolfgang Betz	67:93bec0baf1de	1694	*/
Wolfgang Betz	67:93bec0baf1de	1695
Wolfgang Betz	67:93bec0baf1de	1696	/** @defgroup TX_CTRL_FIELD_Registers
Wolfgang Betz	67:93bec0baf1de	1697	* @{
Wolfgang Betz	67:93bec0baf1de	1698	*/
Wolfgang Betz	67:93bec0baf1de	1699
Wolfgang Betz	67:93bec0baf1de	1700	/**
Wolfgang Betz	67:93bec0baf1de	1701	* \brief TX_CTRL_FIELDx registers
Wolfgang Betz	67:93bec0baf1de	1702	* \code
Wolfgang Betz	67:93bec0baf1de	1703	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1704	* Read Write
Wolfgang Betz	67:93bec0baf1de	1705	* 7:0 TX_CTRLx[7:0]: Control field value to be used in TX packet as byte n.x
Wolfgang Betz	67:93bec0baf1de	1706	* \endcode
Wolfgang Betz	67:93bec0baf1de	1707	*/
Wolfgang Betz	67:93bec0baf1de	1708	#define TX_CTRL_FIELD3_BASE ((uint8_t)0x68) /!< Control field value to be used in TX packet as byte n.3 /
Wolfgang Betz	67:93bec0baf1de	1709
Wolfgang Betz	67:93bec0baf1de	1710	#define TX_CTRL_FIELD2_BASE ((uint8_t)0x69) /!< Control field value to be used in TX packet as byte n.2 /
Wolfgang Betz	67:93bec0baf1de	1711
Wolfgang Betz	67:93bec0baf1de	1712	#define TX_CTRL_FIELD1_BASE ((uint8_t)0x6A) /!< Control field value to be used in TX packet as byte n.1 /
Wolfgang Betz	67:93bec0baf1de	1713
Wolfgang Betz	67:93bec0baf1de	1714	#define TX_CTRL_FIELD0_BASE ((uint8_t)0x6B) /!< Control field value to be used in TX packet as byte n.0 /
Wolfgang Betz	67:93bec0baf1de	1715
Wolfgang Betz	67:93bec0baf1de	1716	/**
Wolfgang Betz	67:93bec0baf1de	1717	* @}
Wolfgang Betz	67:93bec0baf1de	1718	*/
Wolfgang Betz	67:93bec0baf1de	1719
Wolfgang Betz	67:93bec0baf1de	1720
Wolfgang Betz	67:93bec0baf1de	1721	/** @defgroup TX_PCKT_INFO_Register
Wolfgang Betz	67:93bec0baf1de	1722	* @{
Wolfgang Betz	67:93bec0baf1de	1723	*/
Wolfgang Betz	67:93bec0baf1de	1724
Wolfgang Betz	67:93bec0baf1de	1725	/**
Wolfgang Betz	67:93bec0baf1de	1726	* \brief TX_PCKT_INFO registers
Wolfgang Betz	67:93bec0baf1de	1727	* \code
Wolfgang Betz	67:93bec0baf1de	1728	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1729	* Read
Wolfgang Betz	67:93bec0baf1de	1730	*
Wolfgang Betz	67:93bec0baf1de	1731	* 7:6 Not used.
Wolfgang Betz	67:93bec0baf1de	1732	*
Wolfgang Betz	67:93bec0baf1de	1733	* 5:4 TX_SEQ_NUM: Current TX packet sequence number
Wolfgang Betz	67:93bec0baf1de	1734	*
Wolfgang Betz	67:93bec0baf1de	1735	* 0 N_RETX[3:0]: Number of retransmissions done on the
Wolfgang Betz	67:93bec0baf1de	1736	* last TX packet
Wolfgang Betz	67:93bec0baf1de	1737	* \endcode
Wolfgang Betz	67:93bec0baf1de	1738	*/
Wolfgang Betz	67:93bec0baf1de	1739	#define TX_PCKT_INFO_BASE ((uint8_t)(0xC2)) /*!< Current TX packet sequence number [5:4];
Wolfgang Betz	67:93bec0baf1de	1740	Number of retransmissions done on the last TX packet [3:0]*/
Wolfgang Betz	67:93bec0baf1de	1741	/**
Wolfgang Betz	67:93bec0baf1de	1742	* @}
Wolfgang Betz	67:93bec0baf1de	1743	*/
Wolfgang Betz	67:93bec0baf1de	1744
Wolfgang Betz	67:93bec0baf1de	1745	/** @defgroup RX_PCKT_INFO_Register
Wolfgang Betz	67:93bec0baf1de	1746	* @{
Wolfgang Betz	67:93bec0baf1de	1747	*/
Wolfgang Betz	67:93bec0baf1de	1748
Wolfgang Betz	67:93bec0baf1de	1749	/**
Wolfgang Betz	67:93bec0baf1de	1750	* \brief RX_PCKT_INFO registers
Wolfgang Betz	67:93bec0baf1de	1751	* \code
Wolfgang Betz	67:93bec0baf1de	1752	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1753	* Read
Wolfgang Betz	67:93bec0baf1de	1754	*
Wolfgang Betz	67:93bec0baf1de	1755	* 7:3 Not used.
Wolfgang Betz	67:93bec0baf1de	1756	*
Wolfgang Betz	67:93bec0baf1de	1757	* 2 NACK_RX: NACK field of the received packet
Wolfgang Betz	67:93bec0baf1de	1758	*
Wolfgang Betz	67:93bec0baf1de	1759	* 1:0 RX_SEQ_NUM[1:0]: Sequence number of the received packet
Wolfgang Betz	67:93bec0baf1de	1760	* \endcode
Wolfgang Betz	67:93bec0baf1de	1761	*/
Wolfgang Betz	67:93bec0baf1de	1762	#define RX_PCKT_INFO_BASE ((uint8_t)(0xC3)) /*!< NO_ACK field of the received packet [2];
Wolfgang Betz	67:93bec0baf1de	1763	sequence number of the received packet [1:0]*/
Wolfgang Betz	67:93bec0baf1de	1764
Wolfgang Betz	67:93bec0baf1de	1765	#define TX_PCKT_INFO_NACK_RX ((uint8_t)(0x04)) /!< NACK field of the received packet /
Wolfgang Betz	67:93bec0baf1de	1766
Wolfgang Betz	67:93bec0baf1de	1767	/**
Wolfgang Betz	67:93bec0baf1de	1768	* @}
Wolfgang Betz	67:93bec0baf1de	1769	*/
Wolfgang Betz	67:93bec0baf1de	1770
Wolfgang Betz	67:93bec0baf1de	1771	/** @defgroup RX_PCKT_LEN1
Wolfgang Betz	67:93bec0baf1de	1772	* @{
Wolfgang Betz	67:93bec0baf1de	1773	*/
Wolfgang Betz	67:93bec0baf1de	1774
Wolfgang Betz	67:93bec0baf1de	1775	/**
Wolfgang Betz	67:93bec0baf1de	1776	* \brief RX_PCKT_LEN1 registers
Wolfgang Betz	67:93bec0baf1de	1777	* \code
Wolfgang Betz	67:93bec0baf1de	1778	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1779	* Read
Wolfgang Betz	67:93bec0baf1de	1780	*
Wolfgang Betz	67:93bec0baf1de	1781	* 7:0 RX_PCKT_LEN1[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0
Wolfgang Betz	67:93bec0baf1de	1782	* This value is packet_length/256
Wolfgang Betz	67:93bec0baf1de	1783	* \endcode
Wolfgang Betz	67:93bec0baf1de	1784	*/
Wolfgang Betz	67:93bec0baf1de	1785	#define RX_PCKT_LEN1_BASE ((uint8_t)(0xC9)) /!< Length (number of bytes) of the received packet: /
Wolfgang Betz	67:93bec0baf1de	1786
Wolfgang Betz	67:93bec0baf1de	1787	/**
Wolfgang Betz	67:93bec0baf1de	1788	* @}
Wolfgang Betz	67:93bec0baf1de	1789	*/
Wolfgang Betz	67:93bec0baf1de	1790
Wolfgang Betz	67:93bec0baf1de	1791	/** @defgroup RX_PCKT_LEN0
Wolfgang Betz	67:93bec0baf1de	1792	* @{
Wolfgang Betz	67:93bec0baf1de	1793	*/
Wolfgang Betz	67:93bec0baf1de	1794
Wolfgang Betz	67:93bec0baf1de	1795	/**
Wolfgang Betz	67:93bec0baf1de	1796	* \brief RX_PCKT_LEN0 registers
Wolfgang Betz	67:93bec0baf1de	1797	* \code
Wolfgang Betz	67:93bec0baf1de	1798	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1799	* Read
Wolfgang Betz	67:93bec0baf1de	1800	*
Wolfgang Betz	67:93bec0baf1de	1801	* 7:0 RX_PCKT_LEN0[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0
Wolfgang Betz	67:93bec0baf1de	1802	* This value is packet_length%256
Wolfgang Betz	67:93bec0baf1de	1803	* \endcode
Wolfgang Betz	67:93bec0baf1de	1804	*/
Wolfgang Betz	67:93bec0baf1de	1805	#define RX_PCKT_LEN0_BASE ((uint8_t)(0xCA)) /!< RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0 /
Wolfgang Betz	67:93bec0baf1de	1806
Wolfgang Betz	67:93bec0baf1de	1807	/**
Wolfgang Betz	67:93bec0baf1de	1808	* @}
Wolfgang Betz	67:93bec0baf1de	1809	*/
Wolfgang Betz	67:93bec0baf1de	1810
Wolfgang Betz	67:93bec0baf1de	1811
Wolfgang Betz	67:93bec0baf1de	1812	/** @defgroup CRC_FIELD_Register
Wolfgang Betz	67:93bec0baf1de	1813	* @{
Wolfgang Betz	67:93bec0baf1de	1814	*/
Wolfgang Betz	67:93bec0baf1de	1815
Wolfgang Betz	67:93bec0baf1de	1816	/**
Wolfgang Betz	67:93bec0baf1de	1817	* \brief CRC_FIELD[2:0] registers
Wolfgang Betz	67:93bec0baf1de	1818	* \code
Wolfgang Betz	67:93bec0baf1de	1819	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1820	* Read
Wolfgang Betz	67:93bec0baf1de	1821	*
Wolfgang Betz	67:93bec0baf1de	1822	* 7:0 CRC_FIELDx[7:0]: upper(x=2), middle(x=1) and lower(x=0) part of the crc field of the received packet
Wolfgang Betz	67:93bec0baf1de	1823	* \endcode
Wolfgang Betz	67:93bec0baf1de	1824	*/
Wolfgang Betz	67:93bec0baf1de	1825	#define CRC_FIELD2_BASE ((uint8_t)(0xCB)) /!< CRC2 field of the received packet /
Wolfgang Betz	67:93bec0baf1de	1826
Wolfgang Betz	67:93bec0baf1de	1827	#define CRC_FIELD1_BASE ((uint8_t)(0xCC)) /!< CRC1 field of the received packet /
Wolfgang Betz	67:93bec0baf1de	1828
Wolfgang Betz	67:93bec0baf1de	1829	#define CRC_FIELD0_BASE ((uint8_t)(0xCD)) /!< CRC0 field of the received packet /
Wolfgang Betz	67:93bec0baf1de	1830
Wolfgang Betz	67:93bec0baf1de	1831	/**
Wolfgang Betz	67:93bec0baf1de	1832	* @}
Wolfgang Betz	67:93bec0baf1de	1833	*/
Wolfgang Betz	67:93bec0baf1de	1834
Wolfgang Betz	67:93bec0baf1de	1835	/** @defgroup RX_CTRL_FIELD_Register
Wolfgang Betz	67:93bec0baf1de	1836	* @{
Wolfgang Betz	67:93bec0baf1de	1837	*/
Wolfgang Betz	67:93bec0baf1de	1838
Wolfgang Betz	67:93bec0baf1de	1839	/**
Wolfgang Betz	67:93bec0baf1de	1840	* \brief RX_CTRL_FIELD[3:0] registers
Wolfgang Betz	67:93bec0baf1de	1841	* \code
Wolfgang Betz	67:93bec0baf1de	1842	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1843	* Read
Wolfgang Betz	67:93bec0baf1de	1844	*
Wolfgang Betz	67:93bec0baf1de	1845	* 7:0 RX_CTRL_FIELDx[7:0]: upper(x=3), middle(x=2), middle(x=1) and lower(x=0) part of the control field of the received packet
Wolfgang Betz	67:93bec0baf1de	1846	* \endcode
Wolfgang Betz	67:93bec0baf1de	1847	*/
Wolfgang Betz	67:93bec0baf1de	1848	#define RX_CTRL_FIELD0_BASE ((uint8_t)(0xCE)) /!< CRTL3 Control field of the received packet /
Wolfgang Betz	67:93bec0baf1de	1849
Wolfgang Betz	67:93bec0baf1de	1850	#define RX_CTRL_FIELD1_BASE ((uint8_t)(0xCF)) /!< CRTL2 Control field of the received packet /
Wolfgang Betz	67:93bec0baf1de	1851
Wolfgang Betz	67:93bec0baf1de	1852	#define RX_CTRL_FIELD2_BASE ((uint8_t)(0xD0)) /!< CRTL1 Control field of the received packet /
Wolfgang Betz	67:93bec0baf1de	1853
Wolfgang Betz	67:93bec0baf1de	1854	#define RX_CTRL_FIELD3_BASE ((uint8_t)(0xD1)) /!< CRTL0 Control field of the received packet /
Wolfgang Betz	67:93bec0baf1de	1855
Wolfgang Betz	67:93bec0baf1de	1856	/**
Wolfgang Betz	67:93bec0baf1de	1857	* @}
Wolfgang Betz	67:93bec0baf1de	1858	*/
Wolfgang Betz	67:93bec0baf1de	1859
Wolfgang Betz	67:93bec0baf1de	1860	/** @defgroup RX_ADDR_FIELD_Register
Wolfgang Betz	67:93bec0baf1de	1861	* @{
Wolfgang Betz	67:93bec0baf1de	1862	*/
Wolfgang Betz	67:93bec0baf1de	1863
Wolfgang Betz	67:93bec0baf1de	1864	/**
Wolfgang Betz	67:93bec0baf1de	1865	* \brief RX_ADDR_FIELD[1:0] registers
Wolfgang Betz	67:93bec0baf1de	1866	* \code
Wolfgang Betz	67:93bec0baf1de	1867	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1868	* Read
Wolfgang Betz	67:93bec0baf1de	1869	*
Wolfgang Betz	67:93bec0baf1de	1870	* 7:0 RX_ADDR_FIELDx[7:0]: source(x=1) and destination(x=0) address field of the received packet
Wolfgang Betz	67:93bec0baf1de	1871	* \endcode
Wolfgang Betz	67:93bec0baf1de	1872	*/
Wolfgang Betz	67:93bec0baf1de	1873	#define RX_ADDR_FIELD1_BASE ((uint8_t)(0xD2)) /!< ADDR1 Address field of the received packet /
Wolfgang Betz	67:93bec0baf1de	1874
Wolfgang Betz	67:93bec0baf1de	1875	#define RX_ADDR_FIELD0_BASE ((uint8_t)(0xD3)) /!< ADDR0 Address field of the received packet /
Wolfgang Betz	67:93bec0baf1de	1876
Wolfgang Betz	67:93bec0baf1de	1877	/**
Wolfgang Betz	67:93bec0baf1de	1878	* @}
Wolfgang Betz	67:93bec0baf1de	1879	*/
Wolfgang Betz	67:93bec0baf1de	1880
Wolfgang Betz	67:93bec0baf1de	1881	/**
Wolfgang Betz	67:93bec0baf1de	1882	* @}
Wolfgang Betz	67:93bec0baf1de	1883	*/
Wolfgang Betz	67:93bec0baf1de	1884
Wolfgang Betz	67:93bec0baf1de	1885
Wolfgang Betz	67:93bec0baf1de	1886	/** @defgroup Protocol_Registers
Wolfgang Betz	67:93bec0baf1de	1887	* @{
Wolfgang Betz	67:93bec0baf1de	1888	*/
Wolfgang Betz	67:93bec0baf1de	1889
Wolfgang Betz	67:93bec0baf1de	1890	/** @defgroup PROTOCOL2_Register
Wolfgang Betz	67:93bec0baf1de	1891	* @{
Wolfgang Betz	67:93bec0baf1de	1892	*/
Wolfgang Betz	67:93bec0baf1de	1893
Wolfgang Betz	67:93bec0baf1de	1894	/**
Wolfgang Betz	67:93bec0baf1de	1895	* \brief PROTOCOL2 register
Wolfgang Betz	67:93bec0baf1de	1896	* \code
Wolfgang Betz	67:93bec0baf1de	1897	* Default value: 0x06
Wolfgang Betz	67:93bec0baf1de	1898	* Read Write
Wolfgang Betz	67:93bec0baf1de	1899	* 7 CS_TIMEOUT_MASK: 1 - CS value contributes to timeout disabling
Wolfgang Betz	67:93bec0baf1de	1900	*
Wolfgang Betz	67:93bec0baf1de	1901	* 6 SQI_TIMEOUT_MASK: 1 - SQI value contributes to timeout disabling
Wolfgang Betz	67:93bec0baf1de	1902	*
Wolfgang Betz	67:93bec0baf1de	1903	* 5 PQI_TIMEOUT_MASK: 1 - PQI value contributes to timeout disabling
Wolfgang Betz	67:93bec0baf1de	1904	*
Wolfgang Betz	67:93bec0baf1de	1905	* 4:3 TX_SEQ_NUM_RELOAD[1:0]: TX sequence number to be used when counting reset is required using the related command.
Wolfgang Betz	67:93bec0baf1de	1906	*
Wolfgang Betz	67:93bec0baf1de	1907	* 2 RCO_CALIBRATION[0]: 1 - Enables the automatic RCO calibration
Wolfgang Betz	67:93bec0baf1de	1908	*
Wolfgang Betz	67:93bec0baf1de	1909	* 1 VCO_CALIBRATION[0]: 1 - Enables the automatic VCO calibration
Wolfgang Betz	67:93bec0baf1de	1910	*
Wolfgang Betz	67:93bec0baf1de	1911	* 0 LDCR_MODE[0]: 1 - LDCR mode enabled
Wolfgang Betz	67:93bec0baf1de	1912	*
Wolfgang Betz	67:93bec0baf1de	1913	* \endcode
Wolfgang Betz	67:93bec0baf1de	1914	*/
Wolfgang Betz	67:93bec0baf1de	1915	#define PROTOCOL2_BASE ((uint8_t)0x50) /!< Protocol2 regisetr address /
Wolfgang Betz	67:93bec0baf1de	1916
Wolfgang Betz	67:93bec0baf1de	1917	#define PROTOCOL2_LDC_MODE_MASK ((uint8_t)0x01) /!< Enable/disable Low duty Cycle mode /
Wolfgang Betz	67:93bec0baf1de	1918	#define PROTOCOL2_VCO_CALIBRATION_MASK ((uint8_t)0x02) /!< Enable/disable VCO automatic calibration /
Wolfgang Betz	67:93bec0baf1de	1919	#define PROTOCOL2_RCO_CALIBRATION_MASK ((uint8_t)0x04) /!< Enable/disable RCO automatic calibration /
Wolfgang Betz	67:93bec0baf1de	1920	#define PROTOCOL2_PQI_TIMEOUT_MASK ((uint8_t)0x20) /!< PQI value contributes to timeout disabling /
Wolfgang Betz	67:93bec0baf1de	1921	#define PROTOCOL2_SQI_TIMEOUT_MASK ((uint8_t)0x40) /!< SQI value contributes to timeout disabling /
Wolfgang Betz	67:93bec0baf1de	1922	#define PROTOCOL2_CS_TIMEOUT_MASK ((uint8_t)0x80) /!< CS value contributes to timeout disabling /
Wolfgang Betz	67:93bec0baf1de	1923
Wolfgang Betz	67:93bec0baf1de	1924	/**
Wolfgang Betz	67:93bec0baf1de	1925	* @}
Wolfgang Betz	67:93bec0baf1de	1926	*/
Wolfgang Betz	67:93bec0baf1de	1927
Wolfgang Betz	67:93bec0baf1de	1928	/** @defgroup PROTOCOL1_Register
Wolfgang Betz	67:93bec0baf1de	1929	* @{
Wolfgang Betz	67:93bec0baf1de	1930	*/
Wolfgang Betz	67:93bec0baf1de	1931
Wolfgang Betz	67:93bec0baf1de	1932	/**
Wolfgang Betz	67:93bec0baf1de	1933	* \brief PROTOCOL1 register
Wolfgang Betz	67:93bec0baf1de	1934	* \code
Wolfgang Betz	67:93bec0baf1de	1935	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	1936	* Read Write
Wolfgang Betz	67:93bec0baf1de	1937	* 7 LDCR_RELOAD_ON_SYNC: 1 - LDCR timer will be reloaded with the value stored in the LDCR_RELOAD registers
Wolfgang Betz	67:93bec0baf1de	1938	*
Wolfgang Betz	67:93bec0baf1de	1939	* 6 PIGGYBACKING: 1 - PIGGYBACKING enabled
Wolfgang Betz	67:93bec0baf1de	1940	*
Wolfgang Betz	67:93bec0baf1de	1941	* 5:4 Reserved.
Wolfgang Betz	67:93bec0baf1de	1942	*
Wolfgang Betz	67:93bec0baf1de	1943	* 3 SEED_RELOAD[0]: 1 - Reload the back-off random generator
Wolfgang Betz	67:93bec0baf1de	1944	* seed using the value written in the
Wolfgang Betz	67:93bec0baf1de	1945	* BU_COUNTER_SEED_MSByte / LSByte registers
Wolfgang Betz	67:93bec0baf1de	1946	*
Wolfgang Betz	67:93bec0baf1de	1947	* 2 CSMA_ON [0]: 1 - CSMA channel access mode enabled
Wolfgang Betz	67:93bec0baf1de	1948	*
Wolfgang Betz	67:93bec0baf1de	1949	* 1 CSMA_PERS_ON[0]: 1 - CSMA persistent (no back-off) enabled
Wolfgang Betz	67:93bec0baf1de	1950	*
Wolfgang Betz	67:93bec0baf1de	1951	* 0 AUTO_PCKT_FLT[0]: 1 - automatic packet filtering mode enabled
Wolfgang Betz	67:93bec0baf1de	1952	*
Wolfgang Betz	67:93bec0baf1de	1953	* \endcode
Wolfgang Betz	67:93bec0baf1de	1954	*/
Wolfgang Betz	67:93bec0baf1de	1955	#define PROTOCOL1_BASE ((uint8_t)0x51) /!< Protocol1 regisetr address /
Wolfgang Betz	67:93bec0baf1de	1956
Wolfgang Betz	67:93bec0baf1de	1957	#define PROTOCOL1_AUTO_PCKT_FLT_MASK ((uint8_t)0x01) /!< Enable/disable automatic packet filtering mode /
Wolfgang Betz	67:93bec0baf1de	1958	#define PROTOCOL1_CSMA_PERS_ON_MASK ((uint8_t)0x02) /!< Enable/disable CSMA persistent (no back-off) /
Wolfgang Betz	67:93bec0baf1de	1959	#define PROTOCOL1_CSMA_ON_MASK ((uint8_t)0x04) /!< Enable/disable CSMA channel access mode /
Wolfgang Betz	67:93bec0baf1de	1960	#define PROTOCOL1_SEED_RELOAD_MASK ((uint8_t)0x08) /!< Reloads the seed of the PN generator for CSMA procedure /
Wolfgang Betz	67:93bec0baf1de	1961	#define PROTOCOL1_PIGGYBACKING_MASK ((uint8_t)0x40) /!< Enable/disable Piggybacking /
Wolfgang Betz	67:93bec0baf1de	1962	#define PROTOCOL1_LDC_RELOAD_ON_SYNC_MASK ((uint8_t)0x80) /!< LDC timer will be reloaded with the value stored in the LDC_RELOAD registers /
Wolfgang Betz	67:93bec0baf1de	1963
Wolfgang Betz	67:93bec0baf1de	1964	/**
Wolfgang Betz	67:93bec0baf1de	1965	* @}
Wolfgang Betz	67:93bec0baf1de	1966	*/
Wolfgang Betz	67:93bec0baf1de	1967
Wolfgang Betz	67:93bec0baf1de	1968	/** @defgroup PROTOCOL0_Register
Wolfgang Betz	67:93bec0baf1de	1969	* @{
Wolfgang Betz	67:93bec0baf1de	1970	*/
Wolfgang Betz	67:93bec0baf1de	1971
Wolfgang Betz	67:93bec0baf1de	1972	/**
Wolfgang Betz	67:93bec0baf1de	1973	* \brief PROTOCOL0 register
Wolfgang Betz	67:93bec0baf1de	1974	* \code
Wolfgang Betz	67:93bec0baf1de	1975	* Default value: 0x08
Wolfgang Betz	67:93bec0baf1de	1976	* Read Write
Wolfgang Betz	67:93bec0baf1de	1977	* 7:4 NMAX_RETX[3:0]: Max number of re-TX. 0 - re-transmission is not performed
Wolfgang Betz	67:93bec0baf1de	1978	*
Wolfgang Betz	67:93bec0baf1de	1979	* 3 NACK_TX[0]: 1 - field NO_ACK=1 on transmitted packet
Wolfgang Betz	67:93bec0baf1de	1980	*
Wolfgang Betz	67:93bec0baf1de	1981	* 2 AUTO_ACK[0]: 1 - automatic ack after RX
Wolfgang Betz	67:93bec0baf1de	1982	*
Wolfgang Betz	67:93bec0baf1de	1983	* 1 PERS_RX[0]: 1 - persistent reception enabled
Wolfgang Betz	67:93bec0baf1de	1984	*
Wolfgang Betz	67:93bec0baf1de	1985	* 0 PERS_TX[0]: 1 - persistent transmission enabled
Wolfgang Betz	67:93bec0baf1de	1986	*
Wolfgang Betz	67:93bec0baf1de	1987	* \endcode
Wolfgang Betz	67:93bec0baf1de	1988	*/
Wolfgang Betz	67:93bec0baf1de	1989	#define PROTOCOL0_BASE ((uint8_t)0x52) /!< Persistent RX/TX, autoack, Max number of retransmissions /
Wolfgang Betz	67:93bec0baf1de	1990
Wolfgang Betz	67:93bec0baf1de	1991	#define PROTOCOL0_PERS_TX_MASK ((uint8_t)0x01) /!< Enables persistent transmission /
Wolfgang Betz	67:93bec0baf1de	1992	#define PROTOCOL0_PERS_RX_MASK ((uint8_t)0x02) /!< Enables persistent reception /
Wolfgang Betz	67:93bec0baf1de	1993	#define PROTOCOL0_AUTO_ACK_MASK ((uint8_t)0x04) /!< Enables auto acknowlegment /
Wolfgang Betz	67:93bec0baf1de	1994	#define PROTOCOL0_NACK_TX_MASK ((uint8_t)0x08) /!< Writes field NO_ACK=1 on transmitted packet /
Wolfgang Betz	67:93bec0baf1de	1995	#define PROTOCOL0_NMAX_RETX_MASK ((uint8_t)0xF0) /!< Retransmission mask /
Wolfgang Betz	67:93bec0baf1de	1996
Wolfgang Betz	67:93bec0baf1de	1997	/**
Wolfgang Betz	67:93bec0baf1de	1998	* @}
Wolfgang Betz	67:93bec0baf1de	1999	*/
Wolfgang Betz	67:93bec0baf1de	2000
Wolfgang Betz	67:93bec0baf1de	2001	/** @defgroup TIMERS5_Register
Wolfgang Betz	67:93bec0baf1de	2002	* @{
Wolfgang Betz	67:93bec0baf1de	2003	*/
Wolfgang Betz	67:93bec0baf1de	2004
Wolfgang Betz	67:93bec0baf1de	2005	/**
Wolfgang Betz	67:93bec0baf1de	2006	* \brief TIMERS5 register
Wolfgang Betz	67:93bec0baf1de	2007	* \code
Wolfgang Betz	67:93bec0baf1de	2008	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2009	* Read Write
Wolfgang Betz	67:93bec0baf1de	2010	* 7:0 RX_TIMEOUT_PRESCALER[7:0] : RX operation timeout: prescaler value
Wolfgang Betz	67:93bec0baf1de	2011	* \endcode
Wolfgang Betz	67:93bec0baf1de	2012	*/
Wolfgang Betz	67:93bec0baf1de	2013	#define TIMERS5_RX_TIMEOUT_PRESCALER_BASE ((uint8_t)0x53) /!< RX operation timeout: prescaler value /
Wolfgang Betz	67:93bec0baf1de	2014
Wolfgang Betz	67:93bec0baf1de	2015	/**
Wolfgang Betz	67:93bec0baf1de	2016	* @}
Wolfgang Betz	67:93bec0baf1de	2017	*/
Wolfgang Betz	67:93bec0baf1de	2018
Wolfgang Betz	67:93bec0baf1de	2019	/** @defgroup TIMERS4_Register
Wolfgang Betz	67:93bec0baf1de	2020	* @{
Wolfgang Betz	67:93bec0baf1de	2021	*/
Wolfgang Betz	67:93bec0baf1de	2022
Wolfgang Betz	67:93bec0baf1de	2023	/**
Wolfgang Betz	67:93bec0baf1de	2024	* \brief TIMERS4 register
Wolfgang Betz	67:93bec0baf1de	2025	* \code
Wolfgang Betz	67:93bec0baf1de	2026	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2027	* Read Write
Wolfgang Betz	67:93bec0baf1de	2028	* 7:0 RX_TIMEOUT_COUNTER[7:0] : RX operation timeout: counter value
Wolfgang Betz	67:93bec0baf1de	2029	* \endcode
Wolfgang Betz	67:93bec0baf1de	2030	*/
Wolfgang Betz	67:93bec0baf1de	2031	#define TIMERS4_RX_TIMEOUT_COUNTER_BASE ((uint8_t)0x54) /!< RX operation timeout: counter value /
Wolfgang Betz	67:93bec0baf1de	2032
Wolfgang Betz	67:93bec0baf1de	2033	/**
Wolfgang Betz	67:93bec0baf1de	2034	* @}
Wolfgang Betz	67:93bec0baf1de	2035	*/
Wolfgang Betz	67:93bec0baf1de	2036
Wolfgang Betz	67:93bec0baf1de	2037	/** @defgroup TIMERS3_Register
Wolfgang Betz	67:93bec0baf1de	2038	* @{
Wolfgang Betz	67:93bec0baf1de	2039	*/
Wolfgang Betz	67:93bec0baf1de	2040
Wolfgang Betz	67:93bec0baf1de	2041	/**
Wolfgang Betz	67:93bec0baf1de	2042	* \brief TIMERS3 register
Wolfgang Betz	67:93bec0baf1de	2043	* \code
Wolfgang Betz	67:93bec0baf1de	2044	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2045	* Read Write
Wolfgang Betz	67:93bec0baf1de	2046	* 7:0 LDCR_PRESCALER[7:0] : LDC Mode: Prescaler part of the wake-up value
Wolfgang Betz	67:93bec0baf1de	2047	* \endcode
Wolfgang Betz	67:93bec0baf1de	2048	*/
Wolfgang Betz	67:93bec0baf1de	2049	#define TIMERS3_LDC_PRESCALER_BASE ((uint8_t)0x55) /!< LDC Mode: Prescaler of the wake-up timer /
Wolfgang Betz	67:93bec0baf1de	2050
Wolfgang Betz	67:93bec0baf1de	2051	/**
Wolfgang Betz	67:93bec0baf1de	2052	* @}
Wolfgang Betz	67:93bec0baf1de	2053	*/
Wolfgang Betz	67:93bec0baf1de	2054
Wolfgang Betz	67:93bec0baf1de	2055	/** @defgroup TIMERS2_Register
Wolfgang Betz	67:93bec0baf1de	2056	* @{
Wolfgang Betz	67:93bec0baf1de	2057	*/
Wolfgang Betz	67:93bec0baf1de	2058
Wolfgang Betz	67:93bec0baf1de	2059	/**
Wolfgang Betz	67:93bec0baf1de	2060	* \brief TIMERS2 register
Wolfgang Betz	67:93bec0baf1de	2061	* \code
Wolfgang Betz	67:93bec0baf1de	2062	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2063	* Read Write
Wolfgang Betz	67:93bec0baf1de	2064	* 7:0 LDCR_COUNTER[7:0] : LDC Mode: counter part of the wake-up value
Wolfgang Betz	67:93bec0baf1de	2065	* \endcode
Wolfgang Betz	67:93bec0baf1de	2066	*/
Wolfgang Betz	67:93bec0baf1de	2067	#define TIMERS2_LDC_COUNTER_BASE ((uint8_t)0x56) /!< LDC Mode: counter of the wake-up timer /
Wolfgang Betz	67:93bec0baf1de	2068
Wolfgang Betz	67:93bec0baf1de	2069	/**
Wolfgang Betz	67:93bec0baf1de	2070	* @}
Wolfgang Betz	67:93bec0baf1de	2071	*/
Wolfgang Betz	67:93bec0baf1de	2072
Wolfgang Betz	67:93bec0baf1de	2073	/** @defgroup TIMERS1_Register
Wolfgang Betz	67:93bec0baf1de	2074	* @{
Wolfgang Betz	67:93bec0baf1de	2075	*/
Wolfgang Betz	67:93bec0baf1de	2076
Wolfgang Betz	67:93bec0baf1de	2077	/**
Wolfgang Betz	67:93bec0baf1de	2078	* \brief TIMERS1 register
Wolfgang Betz	67:93bec0baf1de	2079	* \code
Wolfgang Betz	67:93bec0baf1de	2080	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2081	* Read Write
Wolfgang Betz	67:93bec0baf1de	2082	* 7:0 LDCR_RELOAD_PRESCALER[7:0] : LDC Mode: Prescaler part of the reload value
Wolfgang Betz	67:93bec0baf1de	2083	* \endcode
Wolfgang Betz	67:93bec0baf1de	2084	*/
Wolfgang Betz	67:93bec0baf1de	2085	#define TIMERS1_LDC_RELOAD_PRESCALER_BASE ((uint8_t)0x57) /!< LDC Mode: Prescaler part of the reload value /
Wolfgang Betz	67:93bec0baf1de	2086
Wolfgang Betz	67:93bec0baf1de	2087	/**
Wolfgang Betz	67:93bec0baf1de	2088	* @}
Wolfgang Betz	67:93bec0baf1de	2089	*/
Wolfgang Betz	67:93bec0baf1de	2090
Wolfgang Betz	67:93bec0baf1de	2091	/** @defgroup TIMERS0_Register
Wolfgang Betz	67:93bec0baf1de	2092	* @{
Wolfgang Betz	67:93bec0baf1de	2093	*/
Wolfgang Betz	67:93bec0baf1de	2094
Wolfgang Betz	67:93bec0baf1de	2095	/**
Wolfgang Betz	67:93bec0baf1de	2096	* \brief TIMERS0 register
Wolfgang Betz	67:93bec0baf1de	2097	* \code
Wolfgang Betz	67:93bec0baf1de	2098	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2099	* Read Write
Wolfgang Betz	67:93bec0baf1de	2100	* 7:0 LDCR_RELOAD_COUNTER[7:0] : LDC Mode: Counter part of the reload value
Wolfgang Betz	67:93bec0baf1de	2101	* \endcode
Wolfgang Betz	67:93bec0baf1de	2102	*/
Wolfgang Betz	67:93bec0baf1de	2103	#define TIMERS0_LDC_RELOAD_COUNTER_BASE ((uint8_t)0x58) /!< LDC Mode: Counter part of the reload value /
Wolfgang Betz	67:93bec0baf1de	2104
Wolfgang Betz	67:93bec0baf1de	2105	/**
Wolfgang Betz	67:93bec0baf1de	2106	* @}
Wolfgang Betz	67:93bec0baf1de	2107	*/
Wolfgang Betz	67:93bec0baf1de	2108
Wolfgang Betz	67:93bec0baf1de	2109
Wolfgang Betz	67:93bec0baf1de	2110	/** @defgroup CSMA_CONFIG3_Register
Wolfgang Betz	67:93bec0baf1de	2111	* @{
Wolfgang Betz	67:93bec0baf1de	2112	*/
Wolfgang Betz	67:93bec0baf1de	2113
Wolfgang Betz	67:93bec0baf1de	2114	/**
Wolfgang Betz	67:93bec0baf1de	2115	* \brief CSMA_CONFIG3 registers
Wolfgang Betz	67:93bec0baf1de	2116	* \code
Wolfgang Betz	67:93bec0baf1de	2117	* Default value: 0xFF
Wolfgang Betz	67:93bec0baf1de	2118	* Read Write
Wolfgang Betz	67:93bec0baf1de	2119	* 7:0 BU_COUNTER_SEED_MSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB)
Wolfgang Betz	67:93bec0baf1de	2120	* \endcode
Wolfgang Betz	67:93bec0baf1de	2121	*/
Wolfgang Betz	67:93bec0baf1de	2122	#define CSMA_CONFIG3_BASE ((uint8_t)0x64) /!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB) /
Wolfgang Betz	67:93bec0baf1de	2123
Wolfgang Betz	67:93bec0baf1de	2124	/**
Wolfgang Betz	67:93bec0baf1de	2125	* @}
Wolfgang Betz	67:93bec0baf1de	2126	*/
Wolfgang Betz	67:93bec0baf1de	2127
Wolfgang Betz	67:93bec0baf1de	2128	/** @defgroup CSMA_CONFIG2_Register
Wolfgang Betz	67:93bec0baf1de	2129	* @{
Wolfgang Betz	67:93bec0baf1de	2130	*/
Wolfgang Betz	67:93bec0baf1de	2131
Wolfgang Betz	67:93bec0baf1de	2132	/**
Wolfgang Betz	67:93bec0baf1de	2133	* \brief CSMA_CONFIG2 registers
Wolfgang Betz	67:93bec0baf1de	2134	* \code
Wolfgang Betz	67:93bec0baf1de	2135	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2136	* Read Write
Wolfgang Betz	67:93bec0baf1de	2137	* 7:0 BU_COUNTER_SEED_LSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB)
Wolfgang Betz	67:93bec0baf1de	2138	* \endcode
Wolfgang Betz	67:93bec0baf1de	2139	*/
Wolfgang Betz	67:93bec0baf1de	2140	#define CSMA_CONFIG2_BASE ((uint8_t)0x65) /!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB) /
Wolfgang Betz	67:93bec0baf1de	2141
Wolfgang Betz	67:93bec0baf1de	2142	/**
Wolfgang Betz	67:93bec0baf1de	2143	* @}
Wolfgang Betz	67:93bec0baf1de	2144	*/
Wolfgang Betz	67:93bec0baf1de	2145
Wolfgang Betz	67:93bec0baf1de	2146	/** @defgroup CSMA_CONFIG1_Register
Wolfgang Betz	67:93bec0baf1de	2147	* @{
Wolfgang Betz	67:93bec0baf1de	2148	*/
Wolfgang Betz	67:93bec0baf1de	2149
Wolfgang Betz	67:93bec0baf1de	2150	/**
Wolfgang Betz	67:93bec0baf1de	2151	* \brief CSMA_CONFIG1 registers
Wolfgang Betz	67:93bec0baf1de	2152	* \code
Wolfgang Betz	67:93bec0baf1de	2153	* Default value: 0x04
Wolfgang Betz	67:93bec0baf1de	2154	* Read Write
Wolfgang Betz	67:93bec0baf1de	2155	* 7:2 BU_PRESCALER[5:0]: Used to program the back-off unit BU
Wolfgang Betz	67:93bec0baf1de	2156	*
Wolfgang Betz	67:93bec0baf1de	2157	* 1:0 CCA_PERIOD[1:0]: Used to program the Tcca time (64 / 128 /256 / 512 × Tbit.
Wolfgang Betz	67:93bec0baf1de	2158	* \endcode
Wolfgang Betz	67:93bec0baf1de	2159	*/
Wolfgang Betz	67:93bec0baf1de	2160	#define CSMA_CONFIG1_BASE ((uint8_t)0x66) /!< CSMA/CA: Prescaler of the back-off time unit (BU); CCA period /
Wolfgang Betz	67:93bec0baf1de	2161
Wolfgang Betz	67:93bec0baf1de	2162	#define CSMA_CCA_PERIOD_64TBIT ((uint8_t)0x00) /!< CSMA/CA: Sets CCA period to 64TBIT */
Wolfgang Betz	67:93bec0baf1de	2163	#define CSMA_CCA_PERIOD_128TBIT ((uint8_t)0x01) /!< CSMA/CA: Sets CCA period to 128TBIT */
Wolfgang Betz	67:93bec0baf1de	2164	#define CSMA_CCA_PERIOD_256TBIT ((uint8_t)0x02) /!< CSMA/CA: Sets CCA period to 256TBIT */
Wolfgang Betz	67:93bec0baf1de	2165	#define CSMA_CCA_PERIOD_512TBIT ((uint8_t)0x03) /!< CSMA/CA: Sets CCA period to 512TBIT */
Wolfgang Betz	67:93bec0baf1de	2166
Wolfgang Betz	67:93bec0baf1de	2167	/**
Wolfgang Betz	67:93bec0baf1de	2168	* @}
Wolfgang Betz	67:93bec0baf1de	2169	*/
Wolfgang Betz	67:93bec0baf1de	2170
Wolfgang Betz	67:93bec0baf1de	2171	/** @defgroup CSMA_CONFIG0_Register
Wolfgang Betz	67:93bec0baf1de	2172	* @{
Wolfgang Betz	67:93bec0baf1de	2173	*/
Wolfgang Betz	67:93bec0baf1de	2174
Wolfgang Betz	67:93bec0baf1de	2175	/**
Wolfgang Betz	67:93bec0baf1de	2176	* \brief CSMA_CONFIG0 registers
Wolfgang Betz	67:93bec0baf1de	2177	* \code
Wolfgang Betz	67:93bec0baf1de	2178	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2179	* Read Write
Wolfgang Betz	67:93bec0baf1de	2180	* 7:4 CCA_LENGTH[3:0]: Used to program the Tlisten time
Wolfgang Betz	67:93bec0baf1de	2181	*
Wolfgang Betz	67:93bec0baf1de	2182	* 3 Reserved.
Wolfgang Betz	67:93bec0baf1de	2183	*
Wolfgang Betz	67:93bec0baf1de	2184	* 2:0 NBACKOFF_MAX[2:0]: Max number of back-off cycles.
Wolfgang Betz	67:93bec0baf1de	2185	* \endcode
Wolfgang Betz	67:93bec0baf1de	2186	*/
Wolfgang Betz	67:93bec0baf1de	2187	#define CSMA_CONFIG0_BASE ((uint8_t)0x67) /!< CSMA/CA: CCA lenght; Max number of backoff cycles /
Wolfgang Betz	67:93bec0baf1de	2188
Wolfgang Betz	67:93bec0baf1de	2189	/**
Wolfgang Betz	67:93bec0baf1de	2190	* @}
Wolfgang Betz	67:93bec0baf1de	2191	*/
Wolfgang Betz	67:93bec0baf1de	2192
Wolfgang Betz	67:93bec0baf1de	2193	/**
Wolfgang Betz	67:93bec0baf1de	2194	* @}
Wolfgang Betz	67:93bec0baf1de	2195	*/
Wolfgang Betz	67:93bec0baf1de	2196
Wolfgang Betz	67:93bec0baf1de	2197
Wolfgang Betz	67:93bec0baf1de	2198	/** @defgroup Link_Quality_Registers
Wolfgang Betz	67:93bec0baf1de	2199	* @{
Wolfgang Betz	67:93bec0baf1de	2200	*/
Wolfgang Betz	67:93bec0baf1de	2201
Wolfgang Betz	67:93bec0baf1de	2202	/** @defgroup QI_Register
Wolfgang Betz	67:93bec0baf1de	2203	* @{
Wolfgang Betz	67:93bec0baf1de	2204	*/
Wolfgang Betz	67:93bec0baf1de	2205
Wolfgang Betz	67:93bec0baf1de	2206	/**
Wolfgang Betz	67:93bec0baf1de	2207	* \brief QI register
Wolfgang Betz	67:93bec0baf1de	2208	* \code
Wolfgang Betz	67:93bec0baf1de	2209	* Read Write
Wolfgang Betz	67:93bec0baf1de	2210	* Default value: 0x02
Wolfgang Betz	67:93bec0baf1de	2211	*
Wolfgang Betz	67:93bec0baf1de	2212	* 7:6 SQI_TH[1:0]: SQI threshold according to the formula: 8SYNC_LEN - 2SQI_TH
Wolfgang Betz	67:93bec0baf1de	2213	*
Wolfgang Betz	67:93bec0baf1de	2214	* 5:2 PQI_TH[3:0]: PQI threshold according to the formula: 4*PQI_THR
Wolfgang Betz	67:93bec0baf1de	2215	*
Wolfgang Betz	67:93bec0baf1de	2216	*
Wolfgang Betz	67:93bec0baf1de	2217	* 1 SQI_EN[0]: SQI enable
Wolfgang Betz	67:93bec0baf1de	2218	* 1 - Enable
Wolfgang Betz	67:93bec0baf1de	2219	* 0 - Disable
Wolfgang Betz	67:93bec0baf1de	2220	*
Wolfgang Betz	67:93bec0baf1de	2221	* 0 PQI_EN[0]: PQI enable
Wolfgang Betz	67:93bec0baf1de	2222	* 1 - Enable
Wolfgang Betz	67:93bec0baf1de	2223	* 0 - Disable
Wolfgang Betz	67:93bec0baf1de	2224	* \endcode
Wolfgang Betz	67:93bec0baf1de	2225	*/
Wolfgang Betz	67:93bec0baf1de	2226	#define QI_BASE ((uint8_t)0x3A) /!< QI register /
Wolfgang Betz	67:93bec0baf1de	2227
Wolfgang Betz	67:93bec0baf1de	2228	#define QI_PQI_MASK ((uint8_t)0x01) /!< PQI enable/disable /
Wolfgang Betz	67:93bec0baf1de	2229	#define QI_SQI_MASK ((uint8_t)0x02) /!< SQI enable/disable /
Wolfgang Betz	67:93bec0baf1de	2230
Wolfgang Betz	67:93bec0baf1de	2231	/**
Wolfgang Betz	67:93bec0baf1de	2232	* @}
Wolfgang Betz	67:93bec0baf1de	2233	*/
Wolfgang Betz	67:93bec0baf1de	2234
Wolfgang Betz	67:93bec0baf1de	2235	/** @defgroup LINK_QUALIF2
Wolfgang Betz	67:93bec0baf1de	2236	* @{
Wolfgang Betz	67:93bec0baf1de	2237	*/
Wolfgang Betz	67:93bec0baf1de	2238
Wolfgang Betz	67:93bec0baf1de	2239	/**
Wolfgang Betz	67:93bec0baf1de	2240	* \brief LINK_QUALIF2 registers
Wolfgang Betz	67:93bec0baf1de	2241	* \code
Wolfgang Betz	67:93bec0baf1de	2242	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2243	* Read
Wolfgang Betz	67:93bec0baf1de	2244	*
Wolfgang Betz	67:93bec0baf1de	2245	* 7:0 PQI[7:0]: PQI value of the received packet
Wolfgang Betz	67:93bec0baf1de	2246	* \endcode
Wolfgang Betz	67:93bec0baf1de	2247	*/
Wolfgang Betz	67:93bec0baf1de	2248	#define LINK_QUALIF2_BASE ((uint8_t)(0xC5)) /!< PQI value of the received packet /
Wolfgang Betz	67:93bec0baf1de	2249
Wolfgang Betz	67:93bec0baf1de	2250	/**
Wolfgang Betz	67:93bec0baf1de	2251	* @}
Wolfgang Betz	67:93bec0baf1de	2252	*/
Wolfgang Betz	67:93bec0baf1de	2253
Wolfgang Betz	67:93bec0baf1de	2254	/** @defgroup LINK_QUALIF1
Wolfgang Betz	67:93bec0baf1de	2255	* @{
Wolfgang Betz	67:93bec0baf1de	2256	*/
Wolfgang Betz	67:93bec0baf1de	2257
Wolfgang Betz	67:93bec0baf1de	2258	/**
Wolfgang Betz	67:93bec0baf1de	2259	* \brief LINK_QUALIF1 registers
Wolfgang Betz	67:93bec0baf1de	2260	* \code
Wolfgang Betz	67:93bec0baf1de	2261	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2262	* Read
Wolfgang Betz	67:93bec0baf1de	2263	*
Wolfgang Betz	67:93bec0baf1de	2264	* 7 CS: Carrier Sense indication
Wolfgang Betz	67:93bec0baf1de	2265	*
Wolfgang Betz	67:93bec0baf1de	2266	* 6:0 SQI[6:0]: SQI value of the received packet
Wolfgang Betz	67:93bec0baf1de	2267	* \endcode
Wolfgang Betz	67:93bec0baf1de	2268	*/
Wolfgang Betz	67:93bec0baf1de	2269	#define LINK_QUALIF1_BASE ((uint8_t)(0xC6)) /!< Carrier sense indication [7]; SQI value of the received packet /
Wolfgang Betz	67:93bec0baf1de	2270
Wolfgang Betz	67:93bec0baf1de	2271	#define LINK_QUALIF1_CS ((uint8_t)(0x80)) /!< Carrier sense indication [7] /
Wolfgang Betz	67:93bec0baf1de	2272
Wolfgang Betz	67:93bec0baf1de	2273	/**
Wolfgang Betz	67:93bec0baf1de	2274	* @}
Wolfgang Betz	67:93bec0baf1de	2275	*/
Wolfgang Betz	67:93bec0baf1de	2276
Wolfgang Betz	67:93bec0baf1de	2277	/** @defgroup LINK_QUALIF0
Wolfgang Betz	67:93bec0baf1de	2278	* @{
Wolfgang Betz	67:93bec0baf1de	2279	*/
Wolfgang Betz	67:93bec0baf1de	2280
Wolfgang Betz	67:93bec0baf1de	2281	/**
Wolfgang Betz	67:93bec0baf1de	2282	* \brief LINK_QUALIF0 registers
Wolfgang Betz	67:93bec0baf1de	2283	* \code
Wolfgang Betz	67:93bec0baf1de	2284	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2285	* Read
Wolfgang Betz	67:93bec0baf1de	2286	*
Wolfgang Betz	67:93bec0baf1de	2287	* 7:4 LQI [3:0]: LQI value of the received packet
Wolfgang Betz	67:93bec0baf1de	2288	*
Wolfgang Betz	67:93bec0baf1de	2289	* 3:0 AGC_WORD[3:0]: AGC word of the received packet
Wolfgang Betz	67:93bec0baf1de	2290	* \endcode
Wolfgang Betz	67:93bec0baf1de	2291	*/
Wolfgang Betz	67:93bec0baf1de	2292	#define LINK_QUALIF0_BASE ((uint8_t)(0xC7)) /!< LQI value of the received packet [7:4]; AGC word of the received packet [3:0] /
Wolfgang Betz	67:93bec0baf1de	2293
Wolfgang Betz	67:93bec0baf1de	2294	/**
Wolfgang Betz	67:93bec0baf1de	2295	* @}
Wolfgang Betz	67:93bec0baf1de	2296	*/
Wolfgang Betz	67:93bec0baf1de	2297
Wolfgang Betz	67:93bec0baf1de	2298	/** @defgroup RSSI_LEVEL
Wolfgang Betz	67:93bec0baf1de	2299	* @{
Wolfgang Betz	67:93bec0baf1de	2300	*/
Wolfgang Betz	67:93bec0baf1de	2301
Wolfgang Betz	67:93bec0baf1de	2302	/**
Wolfgang Betz	67:93bec0baf1de	2303	* \brief RSSI_LEVEL registers
Wolfgang Betz	67:93bec0baf1de	2304	* \code
Wolfgang Betz	67:93bec0baf1de	2305	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2306	* Read
Wolfgang Betz	67:93bec0baf1de	2307	*
Wolfgang Betz	67:93bec0baf1de	2308	* 7:0 RSSI_LEVEL[7:0]: RSSI level of the received packet
Wolfgang Betz	67:93bec0baf1de	2309	* \endcode
Wolfgang Betz	67:93bec0baf1de	2310	*/
Wolfgang Betz	67:93bec0baf1de	2311	#define RSSI_LEVEL_BASE ((uint8_t)(0xC8)) /!< RSSI level of the received packet /
Wolfgang Betz	67:93bec0baf1de	2312
Wolfgang Betz	67:93bec0baf1de	2313	/**
Wolfgang Betz	67:93bec0baf1de	2314	* @}
Wolfgang Betz	67:93bec0baf1de	2315	*/
Wolfgang Betz	67:93bec0baf1de	2316
Wolfgang Betz	67:93bec0baf1de	2317	/** @defgroup RSSI_FLT_Register
Wolfgang Betz	67:93bec0baf1de	2318	* @{
Wolfgang Betz	67:93bec0baf1de	2319	*/
Wolfgang Betz	67:93bec0baf1de	2320
Wolfgang Betz	67:93bec0baf1de	2321	/**
Wolfgang Betz	67:93bec0baf1de	2322	* \brief RSSI register
Wolfgang Betz	67:93bec0baf1de	2323	* \code
Wolfgang Betz	67:93bec0baf1de	2324	* Read Write
Wolfgang Betz	67:93bec0baf1de	2325	* Default value: 0xF3
Wolfgang Betz	67:93bec0baf1de	2326	* 7:4 RSSI_FLT[3:0]: Gain of the RSSI filter
Wolfgang Betz	67:93bec0baf1de	2327	*
Wolfgang Betz	67:93bec0baf1de	2328	* 3:2 CS_MODE[1:0]: AFC loop gain in slow mode (2's log)
Wolfgang Betz	67:93bec0baf1de	2329	*
Wolfgang Betz	67:93bec0baf1de	2330	* CS_MODE1 \| CS_MODE0 \| CS Mode
Wolfgang Betz	67:93bec0baf1de	2331	* -----------------------------------------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	2332	* 0 \| 0 \| Static CS
Wolfgang Betz	67:93bec0baf1de	2333	* 0 \| 1 \| Dynamic CS with 6dB dynamic threshold
Wolfgang Betz	67:93bec0baf1de	2334	* 1 \| 0 \| Dynamic CS with 12dB dynamic threshold
Wolfgang Betz	67:93bec0baf1de	2335	* 1 \| 1 \| Dynamic CS with 18dB dynamic threshold
Wolfgang Betz	67:93bec0baf1de	2336	*
Wolfgang Betz	67:93bec0baf1de	2337	* 1:0 OOK_PEAK_DECAY[1:0]: Peak decay control for OOK: 3 slow decay; 0 fast decay
Wolfgang Betz	67:93bec0baf1de	2338	*
Wolfgang Betz	67:93bec0baf1de	2339	* \endcode
Wolfgang Betz	67:93bec0baf1de	2340	*/
Wolfgang Betz	67:93bec0baf1de	2341	#define RSSI_FLT_BASE ((uint8_t)0x21) /*!< Gain of the RSSI filter; lower value is fast but inaccurate,
Wolfgang Betz	67:93bec0baf1de	2342	higher value is slow and more accurate */
Wolfgang Betz	67:93bec0baf1de	2343	#define RSSI_FLT_CS_MODE_MASK ((uint8_t)0x0C) /!< Carrier sense mode mask /
Wolfgang Betz	67:93bec0baf1de	2344	#define RSSI_FLT_CS_MODE_STATIC ((uint8_t)0x00) /!< Carrier sense mode; static carrier sensing /
Wolfgang Betz	67:93bec0baf1de	2345	#define RSSI_FLT_CS_MODE_DYNAMIC_6 ((uint8_t)0x04) /!< Carrier sense mode; dynamic carrier sensing with 6dB threshold /
Wolfgang Betz	67:93bec0baf1de	2346	#define RSSI_FLT_CS_MODE_DYNAMIC_12 ((uint8_t)0x08) /!< Carrier sense mode; dynamic carrier sensing with 12dB threshold /
Wolfgang Betz	67:93bec0baf1de	2347	#define RSSI_FLT_CS_MODE_DYNAMIC_18 ((uint8_t)0x0C) /!< Carrier sense mode; dynamic carrier sensing with 18dB threshold /
Wolfgang Betz	67:93bec0baf1de	2348	#define RSSI_FLT_OOK_PEAK_DECAY_MASK ((uint8_t)0x03) /!< Peak decay control for OOK mask /
Wolfgang Betz	67:93bec0baf1de	2349	#define RSSI_FLT_OOK_PEAK_DECAY_FAST ((uint8_t)0x00) /!< Peak decay control for OOK: fast decay /
Wolfgang Betz	67:93bec0baf1de	2350	#define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_FAST ((uint8_t)0x01) /!< Peak decay control for OOK: medium_fast decay /
Wolfgang Betz	67:93bec0baf1de	2351	#define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_SLOW ((uint8_t)0x02) /!< Peak decay control for OOK: medium_fast decay /
Wolfgang Betz	67:93bec0baf1de	2352	#define RSSI_FLT_OOK_PEAK_DECAY_SLOW ((uint8_t)0x03) /!< Peak decay control for OOK: slow decay /
Wolfgang Betz	67:93bec0baf1de	2353
Wolfgang Betz	67:93bec0baf1de	2354	/**
Wolfgang Betz	67:93bec0baf1de	2355	* @}
Wolfgang Betz	67:93bec0baf1de	2356	*/
Wolfgang Betz	67:93bec0baf1de	2357
Wolfgang Betz	67:93bec0baf1de	2358	/** @defgroup RSSI_TH_Register
Wolfgang Betz	67:93bec0baf1de	2359	* @{
Wolfgang Betz	67:93bec0baf1de	2360	*/
Wolfgang Betz	67:93bec0baf1de	2361
Wolfgang Betz	67:93bec0baf1de	2362	/**
Wolfgang Betz	67:93bec0baf1de	2363	* \brief RSSI_TH register
Wolfgang Betz	67:93bec0baf1de	2364	* \code
Wolfgang Betz	67:93bec0baf1de	2365	* Read Write
Wolfgang Betz	67:93bec0baf1de	2366	* Default value: 0x24
Wolfgang Betz	67:93bec0baf1de	2367	*
Wolfgang Betz	67:93bec0baf1de	2368	* 7:0 RSSI_THRESHOLD [7:0]: Signal detect threshold in 0.5dB. -120dBm corresponds to 20
Wolfgang Betz	67:93bec0baf1de	2369	* \endcode
Wolfgang Betz	67:93bec0baf1de	2370	*/
Wolfgang Betz	67:93bec0baf1de	2371	#define RSSI_TH_BASE ((uint8_t)0x22) /!< Signal detect threshold in 0.5dB stp. 20 correspond to -120 dBm /
Wolfgang Betz	67:93bec0baf1de	2372
Wolfgang Betz	67:93bec0baf1de	2373	/**
Wolfgang Betz	67:93bec0baf1de	2374	* @}
Wolfgang Betz	67:93bec0baf1de	2375	*/
Wolfgang Betz	67:93bec0baf1de	2376
Wolfgang Betz	67:93bec0baf1de	2377	/**
Wolfgang Betz	67:93bec0baf1de	2378	* @}
Wolfgang Betz	67:93bec0baf1de	2379	*/
Wolfgang Betz	67:93bec0baf1de	2380
Wolfgang Betz	67:93bec0baf1de	2381
Wolfgang Betz	67:93bec0baf1de	2382	/** @defgroup FIFO_Registers
Wolfgang Betz	67:93bec0baf1de	2383	* @{
Wolfgang Betz	67:93bec0baf1de	2384	*/
Wolfgang Betz	67:93bec0baf1de	2385
Wolfgang Betz	67:93bec0baf1de	2386	/** @defgroup FIFO_CONFIG3_Register
Wolfgang Betz	67:93bec0baf1de	2387	* @{
Wolfgang Betz	67:93bec0baf1de	2388	*/
Wolfgang Betz	67:93bec0baf1de	2389
Wolfgang Betz	67:93bec0baf1de	2390	/**
Wolfgang Betz	67:93bec0baf1de	2391	* \brief FIFO_CONFIG3 registers
Wolfgang Betz	67:93bec0baf1de	2392	* \code
Wolfgang Betz	67:93bec0baf1de	2393	* Default value: 0x30
Wolfgang Betz	67:93bec0baf1de	2394	* Read Write
Wolfgang Betz	67:93bec0baf1de	2395	* 7 Reserved.
Wolfgang Betz	67:93bec0baf1de	2396	*
Wolfgang Betz	67:93bec0baf1de	2397	* 6:0 rxafthr [6:0]: FIFO Almost Full threshold for rx fifo.
Wolfgang Betz	67:93bec0baf1de	2398	*
Wolfgang Betz	67:93bec0baf1de	2399	* \endcode
Wolfgang Betz	67:93bec0baf1de	2400	*/
Wolfgang Betz	67:93bec0baf1de	2401	#define FIFO_CONFIG3_RXAFTHR_BASE ((uint8_t)0x3E) /!< FIFO Almost Full threshold for rx fifo [6:0] /
Wolfgang Betz	67:93bec0baf1de	2402
Wolfgang Betz	67:93bec0baf1de	2403	/**
Wolfgang Betz	67:93bec0baf1de	2404	* @}
Wolfgang Betz	67:93bec0baf1de	2405	*/
Wolfgang Betz	67:93bec0baf1de	2406
Wolfgang Betz	67:93bec0baf1de	2407	/** @defgroup FIFO_CONFIG2_Register
Wolfgang Betz	67:93bec0baf1de	2408	* @{
Wolfgang Betz	67:93bec0baf1de	2409	*/
Wolfgang Betz	67:93bec0baf1de	2410
Wolfgang Betz	67:93bec0baf1de	2411	/**
Wolfgang Betz	67:93bec0baf1de	2412	* \brief FIFO_CONFIG2 registers
Wolfgang Betz	67:93bec0baf1de	2413	* \code
Wolfgang Betz	67:93bec0baf1de	2414	* Default value: 0x30
Wolfgang Betz	67:93bec0baf1de	2415	* Read Write
Wolfgang Betz	67:93bec0baf1de	2416	* 7 Reserved.
Wolfgang Betz	67:93bec0baf1de	2417	*
Wolfgang Betz	67:93bec0baf1de	2418	* 6:0 rxaethr [6:0]: FIFO Almost Empty threshold for rx fifo.
Wolfgang Betz	67:93bec0baf1de	2419	*
Wolfgang Betz	67:93bec0baf1de	2420	* \endcode
Wolfgang Betz	67:93bec0baf1de	2421	*/
Wolfgang Betz	67:93bec0baf1de	2422	#define FIFO_CONFIG2_RXAETHR_BASE ((uint8_t)0x3F) /!< FIFO Almost Empty threshold for rx fifo [6:0] /
Wolfgang Betz	67:93bec0baf1de	2423
Wolfgang Betz	67:93bec0baf1de	2424	/**
Wolfgang Betz	67:93bec0baf1de	2425	* @}
Wolfgang Betz	67:93bec0baf1de	2426	*/
Wolfgang Betz	67:93bec0baf1de	2427
Wolfgang Betz	67:93bec0baf1de	2428	/** @defgroup FIFO_CONFIG1_Register
Wolfgang Betz	67:93bec0baf1de	2429	* @{
Wolfgang Betz	67:93bec0baf1de	2430	*/
Wolfgang Betz	67:93bec0baf1de	2431
Wolfgang Betz	67:93bec0baf1de	2432	/**
Wolfgang Betz	67:93bec0baf1de	2433	* \brief FIFO_CONFIG1 registers
Wolfgang Betz	67:93bec0baf1de	2434	* \code
Wolfgang Betz	67:93bec0baf1de	2435	* Default value: 0x30
Wolfgang Betz	67:93bec0baf1de	2436	* Read Write
Wolfgang Betz	67:93bec0baf1de	2437	* 7 Reserved.
Wolfgang Betz	67:93bec0baf1de	2438	*
Wolfgang Betz	67:93bec0baf1de	2439	* 6:0 txafthr [6:0]: FIFO Almost Full threshold for tx fifo.
Wolfgang Betz	67:93bec0baf1de	2440	*
Wolfgang Betz	67:93bec0baf1de	2441	* \endcode
Wolfgang Betz	67:93bec0baf1de	2442	*/
Wolfgang Betz	67:93bec0baf1de	2443	#define FIFO_CONFIG1_TXAFTHR_BASE ((uint8_t)0x40) /!< FIFO Almost Full threshold for tx fifo [6:0] /
Wolfgang Betz	67:93bec0baf1de	2444
Wolfgang Betz	67:93bec0baf1de	2445	/**
Wolfgang Betz	67:93bec0baf1de	2446	* @}
Wolfgang Betz	67:93bec0baf1de	2447	*/
Wolfgang Betz	67:93bec0baf1de	2448
Wolfgang Betz	67:93bec0baf1de	2449	/** @defgroup FIFO_CONFIG0_Register
Wolfgang Betz	67:93bec0baf1de	2450	* @{
Wolfgang Betz	67:93bec0baf1de	2451	*/
Wolfgang Betz	67:93bec0baf1de	2452
Wolfgang Betz	67:93bec0baf1de	2453	/**
Wolfgang Betz	67:93bec0baf1de	2454	* \brief FIFO_CONFIG0 registers
Wolfgang Betz	67:93bec0baf1de	2455	* \code
Wolfgang Betz	67:93bec0baf1de	2456	* Default value: 0x30
Wolfgang Betz	67:93bec0baf1de	2457	* Read Write
Wolfgang Betz	67:93bec0baf1de	2458	* 7 Reserved.
Wolfgang Betz	67:93bec0baf1de	2459	*
Wolfgang Betz	67:93bec0baf1de	2460	* 6:0 txaethr [6:0]: FIFO Almost Empty threshold for tx fifo.
Wolfgang Betz	67:93bec0baf1de	2461	*
Wolfgang Betz	67:93bec0baf1de	2462	* \endcode
Wolfgang Betz	67:93bec0baf1de	2463	*/
Wolfgang Betz	67:93bec0baf1de	2464	#define FIFO_CONFIG0_TXAETHR_BASE ((uint8_t)0x41) /!< FIFO Almost Empty threshold for tx fifo [6:0] /
Wolfgang Betz	67:93bec0baf1de	2465
Wolfgang Betz	67:93bec0baf1de	2466	/**
Wolfgang Betz	67:93bec0baf1de	2467	* @}
Wolfgang Betz	67:93bec0baf1de	2468	*/
Wolfgang Betz	67:93bec0baf1de	2469
Wolfgang Betz	67:93bec0baf1de	2470	/** @defgroup LINEAR_FIFO_STATUS1_Register
Wolfgang Betz	67:93bec0baf1de	2471	* @{
Wolfgang Betz	67:93bec0baf1de	2472	*/
Wolfgang Betz	67:93bec0baf1de	2473
Wolfgang Betz	67:93bec0baf1de	2474	/**
Wolfgang Betz	67:93bec0baf1de	2475	* \brief LINEAR_FIFO_STATUS1 registers
Wolfgang Betz	67:93bec0baf1de	2476	* \code
Wolfgang Betz	67:93bec0baf1de	2477	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2478	* Read
Wolfgang Betz	67:93bec0baf1de	2479	*
Wolfgang Betz	67:93bec0baf1de	2480	* 7 Reserved.
Wolfgang Betz	67:93bec0baf1de	2481	*
Wolfgang Betz	67:93bec0baf1de	2482	* 6:0 elem_txfifo[6:0]: Number of elements in the linear TXFIFO (<=96)
Wolfgang Betz	67:93bec0baf1de	2483	* \endcode
Wolfgang Betz	67:93bec0baf1de	2484	*/
Wolfgang Betz	67:93bec0baf1de	2485	#define LINEAR_FIFO_STATUS1_BASE ((uint8_t)(0xE6)) /!< Number of elements in the linear TX FIFO [6:0] (<=96) /
Wolfgang Betz	67:93bec0baf1de	2486
Wolfgang Betz	67:93bec0baf1de	2487	/**
Wolfgang Betz	67:93bec0baf1de	2488	* @}
Wolfgang Betz	67:93bec0baf1de	2489	*/
Wolfgang Betz	67:93bec0baf1de	2490
Wolfgang Betz	67:93bec0baf1de	2491	/** @defgroup LINEAR_FIFO_STATUS0_Register
Wolfgang Betz	67:93bec0baf1de	2492	* @{
Wolfgang Betz	67:93bec0baf1de	2493	*/
Wolfgang Betz	67:93bec0baf1de	2494
Wolfgang Betz	67:93bec0baf1de	2495	/**
Wolfgang Betz	67:93bec0baf1de	2496	* \brief LINEAR_FIFO_STATUS0 registers
Wolfgang Betz	67:93bec0baf1de	2497	* \code
Wolfgang Betz	67:93bec0baf1de	2498	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2499	* Read
Wolfgang Betz	67:93bec0baf1de	2500	*
Wolfgang Betz	67:93bec0baf1de	2501	* 7 Reserved.
Wolfgang Betz	67:93bec0baf1de	2502	*
Wolfgang Betz	67:93bec0baf1de	2503	* 6:0 elem_rxfifo[6:0]: Number of elements in the linear RXFIFO (<=96)
Wolfgang Betz	67:93bec0baf1de	2504	* \endcode
Wolfgang Betz	67:93bec0baf1de	2505	*/
Wolfgang Betz	67:93bec0baf1de	2506	#define LINEAR_FIFO_STATUS0_BASE ((uint8_t)(0xE7)) /!< Number of elements in the linear RX FIFO [6:0] (<=96) /
Wolfgang Betz	67:93bec0baf1de	2507
Wolfgang Betz	67:93bec0baf1de	2508	/**
Wolfgang Betz	67:93bec0baf1de	2509	* @}
Wolfgang Betz	67:93bec0baf1de	2510	*/
Wolfgang Betz	67:93bec0baf1de	2511
Wolfgang Betz	67:93bec0baf1de	2512
Wolfgang Betz	67:93bec0baf1de	2513	/**
Wolfgang Betz	67:93bec0baf1de	2514	* @}
Wolfgang Betz	67:93bec0baf1de	2515	*/
Wolfgang Betz	67:93bec0baf1de	2516
Wolfgang Betz	67:93bec0baf1de	2517
Wolfgang Betz	67:93bec0baf1de	2518	/** @defgroup Calibration_Registers
Wolfgang Betz	67:93bec0baf1de	2519	* @{
Wolfgang Betz	67:93bec0baf1de	2520	*/
Wolfgang Betz	67:93bec0baf1de	2521
Wolfgang Betz	67:93bec0baf1de	2522	/** @defgroup RCO_VCO_CALIBR_IN2_Register
Wolfgang Betz	67:93bec0baf1de	2523	* @{
Wolfgang Betz	67:93bec0baf1de	2524	*/
Wolfgang Betz	67:93bec0baf1de	2525
Wolfgang Betz	67:93bec0baf1de	2526	/**
Wolfgang Betz	67:93bec0baf1de	2527	* \brief RCO_VCO_CALIBR_IN2 registers
Wolfgang Betz	67:93bec0baf1de	2528	* \code
Wolfgang Betz	67:93bec0baf1de	2529	* Default value: 0x70
Wolfgang Betz	67:93bec0baf1de	2530	* Read Write
Wolfgang Betz	67:93bec0baf1de	2531	* 7:4 RWT_IN[3:0]: RaWThermometric word value for the RCO [7:4]
Wolfgang Betz	67:93bec0baf1de	2532	*
Wolfgang Betz	67:93bec0baf1de	2533	* 3:0 RFB_IN[4:1]: ResistorFineBit word value for the RCO (first 4 bits)
Wolfgang Betz	67:93bec0baf1de	2534	* \endcode
Wolfgang Betz	67:93bec0baf1de	2535	*/
Wolfgang Betz	67:93bec0baf1de	2536	#define RCO_VCO_CALIBR_IN2_BASE ((uint8_t)0x6D) /!< RaWThermometric word value for the RCO [7:4]; ResistorFineBit word value for the RCO [3:0] /
Wolfgang Betz	67:93bec0baf1de	2537
Wolfgang Betz	67:93bec0baf1de	2538	/**
Wolfgang Betz	67:93bec0baf1de	2539	* @}
Wolfgang Betz	67:93bec0baf1de	2540	*/
Wolfgang Betz	67:93bec0baf1de	2541
Wolfgang Betz	67:93bec0baf1de	2542	/** @defgroup RCO_VCO_CALIBR_IN1_Register
Wolfgang Betz	67:93bec0baf1de	2543	* @{
Wolfgang Betz	67:93bec0baf1de	2544	*/
Wolfgang Betz	67:93bec0baf1de	2545
Wolfgang Betz	67:93bec0baf1de	2546	/**
Wolfgang Betz	67:93bec0baf1de	2547	* \brief RCO_VCO_CALIBR_IN1 registers
Wolfgang Betz	67:93bec0baf1de	2548	* \code
Wolfgang Betz	67:93bec0baf1de	2549	* Default value: 0x48
Wolfgang Betz	67:93bec0baf1de	2550	* Read Write
Wolfgang Betz	67:93bec0baf1de	2551	*
Wolfgang Betz	67:93bec0baf1de	2552	* 7 RFB_IN[0]: ResistorFineBit word value for the RCO (LSb)
Wolfgang Betz	67:93bec0baf1de	2553	*
Wolfgang Betz	67:93bec0baf1de	2554	* 6:0 VCO_CALIBR_TX[6:0]: Word value for the VCO to be used in TX mode
Wolfgang Betz	67:93bec0baf1de	2555	* \endcode
Wolfgang Betz	67:93bec0baf1de	2556	*/
Wolfgang Betz	67:93bec0baf1de	2557	#define RCO_VCO_CALIBR_IN1_BASE ((uint8_t)0x6E) /!< ResistorFineBit word value for the RCO [7]; Word value for the VCO to be used in TX mode [6:0]/
Wolfgang Betz	67:93bec0baf1de	2558
Wolfgang Betz	67:93bec0baf1de	2559	/**
Wolfgang Betz	67:93bec0baf1de	2560	* @}
Wolfgang Betz	67:93bec0baf1de	2561	*/
Wolfgang Betz	67:93bec0baf1de	2562
Wolfgang Betz	67:93bec0baf1de	2563	/** @defgroup RCO_VCO_CALIBR_IN0_Register
Wolfgang Betz	67:93bec0baf1de	2564	* @{
Wolfgang Betz	67:93bec0baf1de	2565	*/
Wolfgang Betz	67:93bec0baf1de	2566
Wolfgang Betz	67:93bec0baf1de	2567	/**
Wolfgang Betz	67:93bec0baf1de	2568	* \brief RCO_VCO_CALIBR_IN0 registers
Wolfgang Betz	67:93bec0baf1de	2569	* \code
Wolfgang Betz	67:93bec0baf1de	2570	* Default value: 0x48
Wolfgang Betz	67:93bec0baf1de	2571	* Read Write
Wolfgang Betz	67:93bec0baf1de	2572	*
Wolfgang Betz	67:93bec0baf1de	2573	* 7 Reserved.
Wolfgang Betz	67:93bec0baf1de	2574	*
Wolfgang Betz	67:93bec0baf1de	2575	* 6:0 VCO_CALIBR_RX[6:0]: Word value for the VCO to be used in RX mode
Wolfgang Betz	67:93bec0baf1de	2576	* \endcode
Wolfgang Betz	67:93bec0baf1de	2577	*/
Wolfgang Betz	67:93bec0baf1de	2578	#define RCO_VCO_CALIBR_IN0_BASE ((uint8_t)0x6F) /!< Word value for the VCO to be used in RX mode [6:0] /
Wolfgang Betz	67:93bec0baf1de	2579
Wolfgang Betz	67:93bec0baf1de	2580	/**
Wolfgang Betz	67:93bec0baf1de	2581	* @}
Wolfgang Betz	67:93bec0baf1de	2582	*/
Wolfgang Betz	67:93bec0baf1de	2583
Wolfgang Betz	67:93bec0baf1de	2584	/** @defgroup RCO_VCO_CALIBR_OUT1_Register
Wolfgang Betz	67:93bec0baf1de	2585	* @{
Wolfgang Betz	67:93bec0baf1de	2586	*/
Wolfgang Betz	67:93bec0baf1de	2587
Wolfgang Betz	67:93bec0baf1de	2588	/**
Wolfgang Betz	67:93bec0baf1de	2589	* \brief RCO_VCO_CALIBR_OUT1 registers
Wolfgang Betz	67:93bec0baf1de	2590	* \code
Wolfgang Betz	67:93bec0baf1de	2591	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2592	* Read
Wolfgang Betz	67:93bec0baf1de	2593	*
Wolfgang Betz	67:93bec0baf1de	2594	* 7:4 RWT_OUT[3:0]: RWT word from internal RCO calibrator
Wolfgang Betz	67:93bec0baf1de	2595	*
Wolfgang Betz	67:93bec0baf1de	2596	* 3:0 RFB_OUT[4:1]: RFB word from internal RCO calibrator (upper part)
Wolfgang Betz	67:93bec0baf1de	2597	* \endcode
Wolfgang Betz	67:93bec0baf1de	2598	*/
Wolfgang Betz	67:93bec0baf1de	2599	#define RCO_VCO_CALIBR_OUT1_BASE ((uint8_t)(0xE4)) /*!< RaWThermometric RWT word from internal RCO calibrator [7];
Wolfgang Betz	67:93bec0baf1de	2600	ResistorFineBit RFB word from internal RCO oscillator [6:0] */
Wolfgang Betz	67:93bec0baf1de	2601	/**
Wolfgang Betz	67:93bec0baf1de	2602	* @}
Wolfgang Betz	67:93bec0baf1de	2603	*/
Wolfgang Betz	67:93bec0baf1de	2604
Wolfgang Betz	67:93bec0baf1de	2605	/** @defgroup RCO_VCO_CALIBR_OUT0_Register
Wolfgang Betz	67:93bec0baf1de	2606	* @{
Wolfgang Betz	67:93bec0baf1de	2607	*/
Wolfgang Betz	67:93bec0baf1de	2608
Wolfgang Betz	67:93bec0baf1de	2609	/**
Wolfgang Betz	67:93bec0baf1de	2610	* \brief RCO_VCO_CALIBR_OUT0 registers
Wolfgang Betz	67:93bec0baf1de	2611	* \code
Wolfgang Betz	67:93bec0baf1de	2612	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2613	* Read
Wolfgang Betz	67:93bec0baf1de	2614	*
Wolfgang Betz	67:93bec0baf1de	2615	* 7 RFB_OUT[0]: RFB word from internal RCO calibrator (last bit LSB)
Wolfgang Betz	67:93bec0baf1de	2616	*
Wolfgang Betz	67:93bec0baf1de	2617	* 6:0 VCO_CALIBR_DATA[6:0]: Output word from internal VCO calibrator
Wolfgang Betz	67:93bec0baf1de	2618	* \endcode
Wolfgang Betz	67:93bec0baf1de	2619	*/
Wolfgang Betz	67:93bec0baf1de	2620	#define RCO_VCO_CALIBR_OUT0_BASE ((uint8_t)(0xE5)) /*!< ResistorFineBit RFB word from internal RCO oscillator [0];
Wolfgang Betz	67:93bec0baf1de	2621	Output word from internal calibrator [6:0]; */
Wolfgang Betz	67:93bec0baf1de	2622	/**
Wolfgang Betz	67:93bec0baf1de	2623	* @}
Wolfgang Betz	67:93bec0baf1de	2624	*/
Wolfgang Betz	67:93bec0baf1de	2625
Wolfgang Betz	67:93bec0baf1de	2626	/**
Wolfgang Betz	67:93bec0baf1de	2627	* @}
Wolfgang Betz	67:93bec0baf1de	2628	*/
Wolfgang Betz	67:93bec0baf1de	2629
Wolfgang Betz	67:93bec0baf1de	2630
Wolfgang Betz	67:93bec0baf1de	2631	/** @defgroup AES_Registers
Wolfgang Betz	67:93bec0baf1de	2632	* @{
Wolfgang Betz	67:93bec0baf1de	2633	*/
Wolfgang Betz	67:93bec0baf1de	2634
Wolfgang Betz	67:93bec0baf1de	2635	/** @defgroup AES_KEY_IN_Register
Wolfgang Betz	67:93bec0baf1de	2636	* @{
Wolfgang Betz	67:93bec0baf1de	2637	*/
Wolfgang Betz	67:93bec0baf1de	2638
Wolfgang Betz	67:93bec0baf1de	2639	/**
Wolfgang Betz	67:93bec0baf1de	2640	* \brief AES_KEY_INx registers
Wolfgang Betz	67:93bec0baf1de	2641	* \code
Wolfgang Betz	67:93bec0baf1de	2642	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2643	* Read Write
Wolfgang Betz	67:93bec0baf1de	2644	*
Wolfgang Betz	67:93bec0baf1de	2645	* 7:0 AES_KEY_INx[7:0]: AES engine key input (total - 128 bits)
Wolfgang Betz	67:93bec0baf1de	2646	* \endcode
Wolfgang Betz	67:93bec0baf1de	2647	*/
Wolfgang Betz	67:93bec0baf1de	2648	#define AES_KEY_IN_15_BASE ((uint8_t)0x70) /!< AES engine key input 15 /
Wolfgang Betz	67:93bec0baf1de	2649
Wolfgang Betz	67:93bec0baf1de	2650	#define AES_KEY_IN_14_BASE ((uint8_t)0x71) /!< AES engine key input 14 /
Wolfgang Betz	67:93bec0baf1de	2651
Wolfgang Betz	67:93bec0baf1de	2652	#define AES_KEY_IN_13_BASE ((uint8_t)0x72) /!< AES engine key input 13 /
Wolfgang Betz	67:93bec0baf1de	2653
Wolfgang Betz	67:93bec0baf1de	2654	#define AES_KEY_IN_12_BASE ((uint8_t)0x73) /!< AES engine key input 12 /
Wolfgang Betz	67:93bec0baf1de	2655
Wolfgang Betz	67:93bec0baf1de	2656	#define AES_KEY_IN_11_BASE ((uint8_t)0x74) /!< AES engine key input 11 /
Wolfgang Betz	67:93bec0baf1de	2657
Wolfgang Betz	67:93bec0baf1de	2658	#define AES_KEY_IN_10_BASE ((uint8_t)0x75) /!< AES engine key input 10 /
Wolfgang Betz	67:93bec0baf1de	2659
Wolfgang Betz	67:93bec0baf1de	2660	#define AES_KEY_IN_9_BASE ((uint8_t)0x76) /!< AES engine key input 9 /
Wolfgang Betz	67:93bec0baf1de	2661
Wolfgang Betz	67:93bec0baf1de	2662	#define AES_KEY_IN_8_BASE ((uint8_t)0x77) /!< AES engine key input 8 /
Wolfgang Betz	67:93bec0baf1de	2663
Wolfgang Betz	67:93bec0baf1de	2664	#define AES_KEY_IN_7_BASE ((uint8_t)0x78) /!< AES engine key input 7 /
Wolfgang Betz	67:93bec0baf1de	2665
Wolfgang Betz	67:93bec0baf1de	2666	#define AES_KEY_IN_6_BASE ((uint8_t)0x79) /!< AES engine key input 6 /
Wolfgang Betz	67:93bec0baf1de	2667
Wolfgang Betz	67:93bec0baf1de	2668	#define AES_KEY_IN_5_BASE ((uint8_t)0x7A) /!< AES engine key input 5 /
Wolfgang Betz	67:93bec0baf1de	2669
Wolfgang Betz	67:93bec0baf1de	2670	#define AES_KEY_IN_4_BASE ((uint8_t)0x7B) /!< AES engine key input 4 /
Wolfgang Betz	67:93bec0baf1de	2671
Wolfgang Betz	67:93bec0baf1de	2672	#define AES_KEY_IN_3_BASE ((uint8_t)0x7C) /!< AES engine key input 3 /
Wolfgang Betz	67:93bec0baf1de	2673
Wolfgang Betz	67:93bec0baf1de	2674	#define AES_KEY_IN_2_BASE ((uint8_t)0x7D) /!< AES engine key input 2 /
Wolfgang Betz	67:93bec0baf1de	2675
Wolfgang Betz	67:93bec0baf1de	2676	#define AES_KEY_IN_1_BASE ((uint8_t)0x7E) /!< AES engine key input 1 /
Wolfgang Betz	67:93bec0baf1de	2677
Wolfgang Betz	67:93bec0baf1de	2678	#define AES_KEY_IN_0_BASE ((uint8_t)0x7F) /!< AES engine key input 0 /
Wolfgang Betz	67:93bec0baf1de	2679
Wolfgang Betz	67:93bec0baf1de	2680	/**
Wolfgang Betz	67:93bec0baf1de	2681	* @}
Wolfgang Betz	67:93bec0baf1de	2682	*/
Wolfgang Betz	67:93bec0baf1de	2683
Wolfgang Betz	67:93bec0baf1de	2684	/** @defgroup AES_DATA_IN_Register
Wolfgang Betz	67:93bec0baf1de	2685	* @{
Wolfgang Betz	67:93bec0baf1de	2686	*/
Wolfgang Betz	67:93bec0baf1de	2687
Wolfgang Betz	67:93bec0baf1de	2688	/**
Wolfgang Betz	67:93bec0baf1de	2689	* \brief AES_DATA_INx registers
Wolfgang Betz	67:93bec0baf1de	2690	* \code
Wolfgang Betz	67:93bec0baf1de	2691	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2692	* Read Write
Wolfgang Betz	67:93bec0baf1de	2693	*
Wolfgang Betz	67:93bec0baf1de	2694	* 7:0 AES_DATA_INx[7:0]: AES engine data input (total - 128 bits)
Wolfgang Betz	67:93bec0baf1de	2695	* \endcode
Wolfgang Betz	67:93bec0baf1de	2696	*/
Wolfgang Betz	67:93bec0baf1de	2697	#define AES_DATA_IN_15_BASE ((uint8_t)0x80) /*!< AES engine data input 15
Wolfgang Betz	67:93bec0baf1de	2698	Take care: Address is in reverse order respect data numbering; eg.: 0x81 -> AES_data14[7:0] */
Wolfgang Betz	67:93bec0baf1de	2699	#define AES_DATA_IN_14_BASE ((uint8_t)0x81) /!< AES engine data input 14 /
Wolfgang Betz	67:93bec0baf1de	2700
Wolfgang Betz	67:93bec0baf1de	2701	#define AES_DATA_IN_13_BASE ((uint8_t)0x82) /!< AES engine data input 13 /
Wolfgang Betz	67:93bec0baf1de	2702
Wolfgang Betz	67:93bec0baf1de	2703	#define AES_DATA_IN_12_BASE ((uint8_t)0x83) /!< AES engine data input 12 /
Wolfgang Betz	67:93bec0baf1de	2704
Wolfgang Betz	67:93bec0baf1de	2705	#define AES_DATA_IN_11_BASE ((uint8_t)0x84) /!< AES engine data input 11 /
Wolfgang Betz	67:93bec0baf1de	2706
Wolfgang Betz	67:93bec0baf1de	2707	#define AES_DATA_IN_10_BASE ((uint8_t)0x85) /!< AES engine data input 10 /
Wolfgang Betz	67:93bec0baf1de	2708
Wolfgang Betz	67:93bec0baf1de	2709	#define AES_DATA_IN_9_BASE ((uint8_t)0x86) /!< AES engine data input 9 /
Wolfgang Betz	67:93bec0baf1de	2710
Wolfgang Betz	67:93bec0baf1de	2711	#define AES_DATA_IN_8_BASE ((uint8_t)0x87) /!< AES engine data input 8 /
Wolfgang Betz	67:93bec0baf1de	2712
Wolfgang Betz	67:93bec0baf1de	2713	#define AES_DATA_IN_7_BASE ((uint8_t)0x88) /!< AES engine data input 7 /
Wolfgang Betz	67:93bec0baf1de	2714
Wolfgang Betz	67:93bec0baf1de	2715	#define AES_DATA_IN_6_BASE ((uint8_t)0x89) /!< AES engine data input 6 /
Wolfgang Betz	67:93bec0baf1de	2716
Wolfgang Betz	67:93bec0baf1de	2717	#define AES_DATA_IN_5_BASE ((uint8_t)0x8A) /!< AES engine data input 5 /
Wolfgang Betz	67:93bec0baf1de	2718
Wolfgang Betz	67:93bec0baf1de	2719	#define AES_DATA_IN_4_BASE ((uint8_t)0x8B) /!< AES engine data input 4 /
Wolfgang Betz	67:93bec0baf1de	2720
Wolfgang Betz	67:93bec0baf1de	2721	#define AES_DATA_IN_3_BASE ((uint8_t)0x8C) /!< AES engine data input 3 /
Wolfgang Betz	67:93bec0baf1de	2722
Wolfgang Betz	67:93bec0baf1de	2723	#define AES_DATA_IN_2_BASE ((uint8_t)0x8D) /!< AES engine data input 2 /
Wolfgang Betz	67:93bec0baf1de	2724
Wolfgang Betz	67:93bec0baf1de	2725	#define AES_DATA_IN_1_BASE ((uint8_t)0x8E) /!< AES engine data input 1 /
Wolfgang Betz	67:93bec0baf1de	2726
Wolfgang Betz	67:93bec0baf1de	2727	#define AES_DATA_IN_0_BASE ((uint8_t)0x8F) /!< AES engine data input 0 /
Wolfgang Betz	67:93bec0baf1de	2728
Wolfgang Betz	67:93bec0baf1de	2729	/**
Wolfgang Betz	67:93bec0baf1de	2730	* @}
Wolfgang Betz	67:93bec0baf1de	2731	*/
Wolfgang Betz	67:93bec0baf1de	2732
Wolfgang Betz	67:93bec0baf1de	2733	/** @defgroup AES_DATA_OUT_Register
Wolfgang Betz	67:93bec0baf1de	2734	* @{
Wolfgang Betz	67:93bec0baf1de	2735	*/
Wolfgang Betz	67:93bec0baf1de	2736
Wolfgang Betz	67:93bec0baf1de	2737	/**
Wolfgang Betz	67:93bec0baf1de	2738	* \brief AES_DATA_OUT[15:0] registers
Wolfgang Betz	67:93bec0baf1de	2739	* \code
Wolfgang Betz	67:93bec0baf1de	2740	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2741	* Read
Wolfgang Betz	67:93bec0baf1de	2742	*
Wolfgang Betz	67:93bec0baf1de	2743	* 7:0 AES_DATA_OUTx[7:0]: AES engine data output (128 bits)
Wolfgang Betz	67:93bec0baf1de	2744	* \endcode
Wolfgang Betz	67:93bec0baf1de	2745	*/
Wolfgang Betz	67:93bec0baf1de	2746	#define AES_DATA_OUT_15_BASE ((uint8_t)(0xD4)) /!< AES engine data output 15 /
Wolfgang Betz	67:93bec0baf1de	2747
Wolfgang Betz	67:93bec0baf1de	2748	#define AES_DATA_OUT_14_BASE ((uint8_t)(0xD5)) /!< AES engine data output 14 /
Wolfgang Betz	67:93bec0baf1de	2749
Wolfgang Betz	67:93bec0baf1de	2750	#define AES_DATA_OUT_13_BASE ((uint8_t)(0xD6)) /!< AES engine data output 13 /
Wolfgang Betz	67:93bec0baf1de	2751
Wolfgang Betz	67:93bec0baf1de	2752	#define AES_DATA_OUT_12_BASE ((uint8_t)(0xD7)) /!< AES engine data output 12 /
Wolfgang Betz	67:93bec0baf1de	2753
Wolfgang Betz	67:93bec0baf1de	2754	#define AES_DATA_OUT_11_BASE ((uint8_t)(0xD8)) /!< AES engine data output 11 /
Wolfgang Betz	67:93bec0baf1de	2755
Wolfgang Betz	67:93bec0baf1de	2756	#define AES_DATA_OUT_10_BASE ((uint8_t)(0xD9)) /!< AES engine data output 10 /
Wolfgang Betz	67:93bec0baf1de	2757
Wolfgang Betz	67:93bec0baf1de	2758	#define AES_DATA_OUT_9_BASE ((uint8_t)(0xDA)) /!< AES engine data output 9 /
Wolfgang Betz	67:93bec0baf1de	2759
Wolfgang Betz	67:93bec0baf1de	2760	#define AES_DATA_OUT_8_BASE ((uint8_t)(0xDB)) /!< AES engine data output 8 /
Wolfgang Betz	67:93bec0baf1de	2761
Wolfgang Betz	67:93bec0baf1de	2762	#define AES_DATA_OUT_7_BASE ((uint8_t)(0xDC)) /!< AES engine data output 7 /
Wolfgang Betz	67:93bec0baf1de	2763
Wolfgang Betz	67:93bec0baf1de	2764	#define AES_DATA_OUT_6_BASE ((uint8_t)(0xDD)) /!< AES engine data output 6 /
Wolfgang Betz	67:93bec0baf1de	2765
Wolfgang Betz	67:93bec0baf1de	2766	#define AES_DATA_OUT_5_BASE ((uint8_t)(0xDE)) /!< AES engine data output 5 /
Wolfgang Betz	67:93bec0baf1de	2767
Wolfgang Betz	67:93bec0baf1de	2768	#define AES_DATA_OUT_4_BASE ((uint8_t)(0xDF)) /!< AES engine data output 4 /
Wolfgang Betz	67:93bec0baf1de	2769
Wolfgang Betz	67:93bec0baf1de	2770	#define AES_DATA_OUT_3_BASE ((uint8_t)(0xE0)) /!< AES engine data output 3 /
Wolfgang Betz	67:93bec0baf1de	2771
Wolfgang Betz	67:93bec0baf1de	2772	#define AES_DATA_OUT_2_BASE ((uint8_t)(0xE1)) /!< AES engine data output 2 /
Wolfgang Betz	67:93bec0baf1de	2773
Wolfgang Betz	67:93bec0baf1de	2774	#define AES_DATA_OUT_1_BASE ((uint8_t)(0xE2)) /!< AES engine data output 1 /
Wolfgang Betz	67:93bec0baf1de	2775
Wolfgang Betz	67:93bec0baf1de	2776	#define AES_DATA_OUT_0_BASE ((uint8_t)(0xE3)) /!< AES engine data output 0 /
Wolfgang Betz	67:93bec0baf1de	2777
Wolfgang Betz	67:93bec0baf1de	2778	/**
Wolfgang Betz	67:93bec0baf1de	2779	* @}
Wolfgang Betz	67:93bec0baf1de	2780	*/
Wolfgang Betz	67:93bec0baf1de	2781
Wolfgang Betz	67:93bec0baf1de	2782	/**
Wolfgang Betz	67:93bec0baf1de	2783	* @}
Wolfgang Betz	67:93bec0baf1de	2784	*/
Wolfgang Betz	67:93bec0baf1de	2785
Wolfgang Betz	67:93bec0baf1de	2786	/** @defgroup IRQ_Registers
Wolfgang Betz	67:93bec0baf1de	2787	* @{
Wolfgang Betz	67:93bec0baf1de	2788	*/
Wolfgang Betz	67:93bec0baf1de	2789
Wolfgang Betz	67:93bec0baf1de	2790	/** @defgroup IRQ_MASK0_Register
Wolfgang Betz	67:93bec0baf1de	2791	* @{
Wolfgang Betz	67:93bec0baf1de	2792	*/
Wolfgang Betz	67:93bec0baf1de	2793
Wolfgang Betz	67:93bec0baf1de	2794	/**
Wolfgang Betz	67:93bec0baf1de	2795	* \brief IRQ_MASK0 registers
Wolfgang Betz	67:93bec0baf1de	2796	* \code
Wolfgang Betz	67:93bec0baf1de	2797	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2798	* Read Write
Wolfgang Betz	67:93bec0baf1de	2799	*
Wolfgang Betz	67:93bec0baf1de	2800	* 7:0 INT_MASK0: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
Wolfgang Betz	67:93bec0baf1de	2801	*
Wolfgang Betz	67:93bec0baf1de	2802	* Bit \| Events Group Interrupt Event
Wolfgang Betz	67:93bec0baf1de	2803	* -------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	2804	* 0 \| RX data ready
Wolfgang Betz	67:93bec0baf1de	2805	* 1 \| RX data discarded (upon filtering)
Wolfgang Betz	67:93bec0baf1de	2806	* 2 \| TX data sent
Wolfgang Betz	67:93bec0baf1de	2807	* 3 \| Max re-TX reached
Wolfgang Betz	67:93bec0baf1de	2808	* 4 \| CRC error
Wolfgang Betz	67:93bec0baf1de	2809	* 5 \| TX FIFO underflow/overflow error
Wolfgang Betz	67:93bec0baf1de	2810	* 6 \| RX FIFO underflow/overflow error
Wolfgang Betz	67:93bec0baf1de	2811	* 7 \| TX FIFO almost full
Wolfgang Betz	67:93bec0baf1de	2812	* \endcode
Wolfgang Betz	67:93bec0baf1de	2813	*/
Wolfgang Betz	67:93bec0baf1de	2814
Wolfgang Betz	67:93bec0baf1de	2815
Wolfgang Betz	67:93bec0baf1de	2816	#define IRQ_MASK0_BASE ((uint8_t)0x93) /!< IRQ_MASK is split into 4 registers/
Wolfgang Betz	67:93bec0baf1de	2817
Wolfgang Betz	67:93bec0baf1de	2818	#define IRQ_MASK0_RX_DATA_READY ((uint8_t)0x01) /!< IRQ: RX data ready /
Wolfgang Betz	67:93bec0baf1de	2819	#define IRQ_MASK0_RX_DATA_DISC ((uint8_t)0x02) /!< IRQ: RX data discarded (upon filtering) /
Wolfgang Betz	67:93bec0baf1de	2820	#define IRQ_MASK0_TX_DATA_SENT ((uint8_t)0x04) /!< IRQ: TX data sent /
Wolfgang Betz	67:93bec0baf1de	2821	#define IRQ_MASK0_MAX_RE_TX_REACH ((uint8_t)0x08) /!< IRQ: Max re-TX reached /
Wolfgang Betz	67:93bec0baf1de	2822	#define IRQ_MASK0_CRC_ERROR ((uint8_t)0x10) /!< IRQ: CRC error /
Wolfgang Betz	67:93bec0baf1de	2823	#define IRQ_MASK0_TX_FIFO_ERROR ((uint8_t)0x20) /!< IRQ: TX FIFO underflow/overflow error /
Wolfgang Betz	67:93bec0baf1de	2824	#define IRQ_MASK0_RX_FIFO_ERROR ((uint8_t)0x40) /!< IRQ: RX FIFO underflow/overflow error /
Wolfgang Betz	67:93bec0baf1de	2825	#define IRQ_MASK0_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /!< IRQ: TX FIFO almost full /
Wolfgang Betz	67:93bec0baf1de	2826
Wolfgang Betz	67:93bec0baf1de	2827	/**
Wolfgang Betz	67:93bec0baf1de	2828	* @}
Wolfgang Betz	67:93bec0baf1de	2829	*/
Wolfgang Betz	67:93bec0baf1de	2830
Wolfgang Betz	67:93bec0baf1de	2831	/** @defgroup IRQ_MASK1_Register
Wolfgang Betz	67:93bec0baf1de	2832	* @{
Wolfgang Betz	67:93bec0baf1de	2833	*/
Wolfgang Betz	67:93bec0baf1de	2834
Wolfgang Betz	67:93bec0baf1de	2835	/**
Wolfgang Betz	67:93bec0baf1de	2836	* \brief IRQ_MASK1 registers
Wolfgang Betz	67:93bec0baf1de	2837	* \code
Wolfgang Betz	67:93bec0baf1de	2838	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2839	* Read Write
Wolfgang Betz	67:93bec0baf1de	2840	*
Wolfgang Betz	67:93bec0baf1de	2841	* 7:0 INT_MASK1: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
Wolfgang Betz	67:93bec0baf1de	2842	*
Wolfgang Betz	67:93bec0baf1de	2843	* Bit \| Events Group Interrupt Event
Wolfgang Betz	67:93bec0baf1de	2844	* -------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	2845	* 8 \| TX FIFO almost empty
Wolfgang Betz	67:93bec0baf1de	2846	* 9 \| RX FIFO almost full
Wolfgang Betz	67:93bec0baf1de	2847	* 10 \| RX FIFO almost empty
Wolfgang Betz	67:93bec0baf1de	2848	* 11 \| Max number of back-off during CCA
Wolfgang Betz	67:93bec0baf1de	2849	* 12 \| Valid preamble detected
Wolfgang Betz	67:93bec0baf1de	2850	* 13 \| Sync word detected
Wolfgang Betz	67:93bec0baf1de	2851	* 14 \| RSSI above threshold (Carrier Sense)
Wolfgang Betz	67:93bec0baf1de	2852	* 15 \| Wake-up timeout in LDCR mode13
Wolfgang Betz	67:93bec0baf1de	2853	* \endcode
Wolfgang Betz	67:93bec0baf1de	2854	*/
Wolfgang Betz	67:93bec0baf1de	2855
Wolfgang Betz	67:93bec0baf1de	2856	#define IRQ_MASK1_BASE ((uint8_t)0x92) /!< IRQ_MASK is split into 4 registers/
Wolfgang Betz	67:93bec0baf1de	2857
Wolfgang Betz	67:93bec0baf1de	2858	#define IRQ_MASK1_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /!< IRQ: TX FIFO almost empty /
Wolfgang Betz	67:93bec0baf1de	2859	#define IRQ_MASK1_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /!< IRQ: RX FIFO almost full /
Wolfgang Betz	67:93bec0baf1de	2860	#define IRQ_MASK1_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /!< IRQ: RX FIFO almost empty /
Wolfgang Betz	67:93bec0baf1de	2861	#define IRQ_MASK1_MAX_BO_CCA_REACH ((uint8_t)0x08) /!< IRQ: Max number of back-off during CCA /
Wolfgang Betz	67:93bec0baf1de	2862	#define IRQ_MASK1_VALID_PREAMBLE ((uint8_t)0x10) /!< IRQ: Valid preamble detected /
Wolfgang Betz	67:93bec0baf1de	2863	#define IRQ_MASK1_VALID_SYNC ((uint8_t)0x20) /!< IRQ: Sync word detected /
Wolfgang Betz	67:93bec0baf1de	2864	#define IRQ_MASK1_RSSI_ABOVE_TH ((uint8_t)0x40) /!< IRQ: RSSI above threshold /
Wolfgang Betz	67:93bec0baf1de	2865	#define IRQ_MASK1_WKUP_TOUT_LDC ((uint8_t)0x80) /!< IRQ: Wake-up timeout in LDC mode /
Wolfgang Betz	67:93bec0baf1de	2866
Wolfgang Betz	67:93bec0baf1de	2867	/**
Wolfgang Betz	67:93bec0baf1de	2868	* @}
Wolfgang Betz	67:93bec0baf1de	2869	*/
Wolfgang Betz	67:93bec0baf1de	2870
Wolfgang Betz	67:93bec0baf1de	2871	/** @defgroup IRQ_MASK2_Register
Wolfgang Betz	67:93bec0baf1de	2872	* @{
Wolfgang Betz	67:93bec0baf1de	2873	*/
Wolfgang Betz	67:93bec0baf1de	2874
Wolfgang Betz	67:93bec0baf1de	2875	/**
Wolfgang Betz	67:93bec0baf1de	2876	* \brief IRQ_MASK2 registers
Wolfgang Betz	67:93bec0baf1de	2877	* \code
Wolfgang Betz	67:93bec0baf1de	2878	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2879	* Read Write
Wolfgang Betz	67:93bec0baf1de	2880	*
Wolfgang Betz	67:93bec0baf1de	2881	* 7:0 INT_MASK2: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
Wolfgang Betz	67:93bec0baf1de	2882	*
Wolfgang Betz	67:93bec0baf1de	2883	* Bit \| Events Group Interrupt Event
Wolfgang Betz	67:93bec0baf1de	2884	* -------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	2885	* 16 \| READY state in steady condition14
Wolfgang Betz	67:93bec0baf1de	2886	* 17 \| STANDBY state switching in progress
Wolfgang Betz	67:93bec0baf1de	2887	* 18 \| Low battery level
Wolfgang Betz	67:93bec0baf1de	2888	* 19 \| Power-On reset
Wolfgang Betz	67:93bec0baf1de	2889	* 20 \| Brown-Out event
Wolfgang Betz	67:93bec0baf1de	2890	* 21 \| LOCK state in steady condition
Wolfgang Betz	67:93bec0baf1de	2891	* 22 \| PM start-up timer expiration
Wolfgang Betz	67:93bec0baf1de	2892	* 23 \| XO settling timeout
Wolfgang Betz	67:93bec0baf1de	2893	* \endcode
Wolfgang Betz	67:93bec0baf1de	2894	*/
Wolfgang Betz	67:93bec0baf1de	2895	#define IRQ_MASK2_BASE ((uint8_t)0x91) /!< IRQ_MASK is split into 4 registers/
Wolfgang Betz	67:93bec0baf1de	2896
Wolfgang Betz	67:93bec0baf1de	2897	#define IRQ_MASK2_READY ((uint8_t)0x01) /!< IRQ: READY state /
Wolfgang Betz	67:93bec0baf1de	2898	#define IRQ_MASK2_STANDBY_DELAYED ((uint8_t)0x02) /!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles /
Wolfgang Betz	67:93bec0baf1de	2899	#define IRQ_MASK2_LOW_BATT_LVL ((uint8_t)0x04) /!< IRQ: Battery level below threshold/
Wolfgang Betz	67:93bec0baf1de	2900	#define IRQ_MASK2_POR ((uint8_t)0x08) /!< IRQ: Power On Reset /
Wolfgang Betz	67:93bec0baf1de	2901	#define IRQ_MASK2_BOR ((uint8_t)0x10) /!< IRQ: Brown out event (both accurate and inaccurate)/
Wolfgang Betz	67:93bec0baf1de	2902	#define IRQ_MASK2_LOCK ((uint8_t)0x20) /!< IRQ: LOCK state /
Wolfgang Betz	67:93bec0baf1de	2903	#define IRQ_MASK2_PM_COUNT_EXPIRED ((uint8_t)0x40) /!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) /
Wolfgang Betz	67:93bec0baf1de	2904	#define IRQ_MASK2_XO_COUNT_EXPIRED ((uint8_t)0x80) /!< IRQ: only for debug; Crystal oscillator settling time counter expired /
Wolfgang Betz	67:93bec0baf1de	2905
Wolfgang Betz	67:93bec0baf1de	2906	/**
Wolfgang Betz	67:93bec0baf1de	2907	* @}
Wolfgang Betz	67:93bec0baf1de	2908	*/
Wolfgang Betz	67:93bec0baf1de	2909
Wolfgang Betz	67:93bec0baf1de	2910	/** @defgroup IRQ_MASK3_Register
Wolfgang Betz	67:93bec0baf1de	2911	* @{
Wolfgang Betz	67:93bec0baf1de	2912	*/
Wolfgang Betz	67:93bec0baf1de	2913
Wolfgang Betz	67:93bec0baf1de	2914	/**
Wolfgang Betz	67:93bec0baf1de	2915	* \brief IRQ_MASK3 registers
Wolfgang Betz	67:93bec0baf1de	2916	* \code
Wolfgang Betz	67:93bec0baf1de	2917	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2918	* Read Write
Wolfgang Betz	67:93bec0baf1de	2919	*
Wolfgang Betz	67:93bec0baf1de	2920	* 7:0 INT_MASK3: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
Wolfgang Betz	67:93bec0baf1de	2921	*
Wolfgang Betz	67:93bec0baf1de	2922	* Bit \| Events Group Interrupt Event
Wolfgang Betz	67:93bec0baf1de	2923	* -------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	2924	* 24 \| SYNTH locking timeout
Wolfgang Betz	67:93bec0baf1de	2925	* 25 \| SYNTH calibration start-up time
Wolfgang Betz	67:93bec0baf1de	2926	* 26 \| SYNTH calibration timeout
Wolfgang Betz	67:93bec0baf1de	2927	* 27 \| TX circuitry start-up time
Wolfgang Betz	67:93bec0baf1de	2928	* 28 \| RX circuitry start-up time
Wolfgang Betz	67:93bec0baf1de	2929	* 29 \| RX operation timeout
Wolfgang Betz	67:93bec0baf1de	2930	* 30 \| Others AES Endof Operation
Wolfgang Betz	67:93bec0baf1de	2931	* 31 \| Reserved
Wolfgang Betz	67:93bec0baf1de	2932	* \endcode
Wolfgang Betz	67:93bec0baf1de	2933	*/
Wolfgang Betz	67:93bec0baf1de	2934	#define IRQ_MASK3_BASE ((uint8_t)0x90) /!< IRQ_MASK is split into 4 registers/
Wolfgang Betz	67:93bec0baf1de	2935
Wolfgang Betz	67:93bec0baf1de	2936	#define IRQ_MASK3_SYNTH_LOCK_TIMEOUT ((uint8_t)0x01) /!< IRQ: only for debug; LOCK state timeout /
Wolfgang Betz	67:93bec0baf1de	2937	#define IRQ_MASK3_SYNTH_LOCK_STARTUP ((uint8_t)0x02) /!< IRQ: only for debug; see CALIBR_START_COUNTER /
Wolfgang Betz	67:93bec0baf1de	2938	#define IRQ_MASK3_SYNTH_CAL_TIMEOUT ((uint8_t)0x04) /!< IRQ: only for debug; SYNTH calibration timeout /
Wolfgang Betz	67:93bec0baf1de	2939	#define IRQ_MASK3_TX_START_TIME ((uint8_t)0x08) /!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER /
Wolfgang Betz	67:93bec0baf1de	2940	#define IRQ_MASK3_RX_START_TIME ((uint8_t)0x10) /!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER /
Wolfgang Betz	67:93bec0baf1de	2941	#define IRQ_MASK3_RX_TIMEOUT ((uint8_t)0x20) /!< IRQ: RX operation timeout /
Wolfgang Betz	67:93bec0baf1de	2942	#define IRQ_MASK3_AES_END ((uint8_t)0x40) /!< IRQ: AES End of operation /
Wolfgang Betz	67:93bec0baf1de	2943
Wolfgang Betz	67:93bec0baf1de	2944	/**
Wolfgang Betz	67:93bec0baf1de	2945	* @}
Wolfgang Betz	67:93bec0baf1de	2946	*/
Wolfgang Betz	67:93bec0baf1de	2947
Wolfgang Betz	67:93bec0baf1de	2948
Wolfgang Betz	67:93bec0baf1de	2949	/** @defgroup IRQ_STATUS0_Register
Wolfgang Betz	67:93bec0baf1de	2950	* @{
Wolfgang Betz	67:93bec0baf1de	2951	*/
Wolfgang Betz	67:93bec0baf1de	2952
Wolfgang Betz	67:93bec0baf1de	2953	/**
Wolfgang Betz	67:93bec0baf1de	2954	* \brief IRQ_STATUS0 registers
Wolfgang Betz	67:93bec0baf1de	2955	* \code
Wolfgang Betz	67:93bec0baf1de	2956	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2957	* Read Write
Wolfgang Betz	67:93bec0baf1de	2958	*
Wolfgang Betz	67:93bec0baf1de	2959	* 7:0 INT_STATUS0: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
Wolfgang Betz	67:93bec0baf1de	2960	*
Wolfgang Betz	67:93bec0baf1de	2961	* Bit \| Events Group Interrupt Event
Wolfgang Betz	67:93bec0baf1de	2962	* -------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	2963	* 0 \| RX data ready
Wolfgang Betz	67:93bec0baf1de	2964	* 1 \| RX data discarded (upon filtering)
Wolfgang Betz	67:93bec0baf1de	2965	* 2 \| TX data sent
Wolfgang Betz	67:93bec0baf1de	2966	* 3 \| Max re-TX reached
Wolfgang Betz	67:93bec0baf1de	2967	* 4 \| CRC error
Wolfgang Betz	67:93bec0baf1de	2968	* 5 \| TX FIFO underflow/overflow error
Wolfgang Betz	67:93bec0baf1de	2969	* 6 \| RX FIFO underflow/overflow error
Wolfgang Betz	67:93bec0baf1de	2970	* 7 \| TX FIFO almost full
Wolfgang Betz	67:93bec0baf1de	2971	* \endcode
Wolfgang Betz	67:93bec0baf1de	2972	*/
Wolfgang Betz	67:93bec0baf1de	2973
Wolfgang Betz	67:93bec0baf1de	2974	#define IRQ_STATUS0_BASE ((uint8_t)(0xFD)) /!< IRQ Events(RR, split into 4 registers) /
Wolfgang Betz	67:93bec0baf1de	2975
Wolfgang Betz	67:93bec0baf1de	2976	#define IRQ_STATUS0_SYNTH_LOCK_TIMEOUT ((uint8_t)(0x01)) /!< IRQ: LOCK state timeout /
Wolfgang Betz	67:93bec0baf1de	2977	#define IRQ_STATUS0_SYNTH_LOCK_STARTUP ((uint8_t)(0x02)) /!< IRQ: only for debug; see CALIBR_START_COUNTER /
Wolfgang Betz	67:93bec0baf1de	2978	#define IRQ_STATUS0_SYNTH_CAL_TIMEOUT ((uint8_t)(0x04)) /!< IRQ: SYNTH locking timeout /
Wolfgang Betz	67:93bec0baf1de	2979	#define IRQ_STATUS0_TX_START_TIME ((uint8_t)(0x08)) /!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER /
Wolfgang Betz	67:93bec0baf1de	2980	#define IRQ_STATUS0_RX_START_TIME ((uint8_t)(0x10)) /!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER /
Wolfgang Betz	67:93bec0baf1de	2981	#define IRQ_STATUS0_RX_TIMEOUT ((uint8_t)(0x20)) /!< IRQ: RX operation timeout expiration /
Wolfgang Betz	67:93bec0baf1de	2982	#define IRQ_STATUS0_AES_END ((uint8_t)(0x40)) /!< IRQ: AES End of operation /
Wolfgang Betz	67:93bec0baf1de	2983
Wolfgang Betz	67:93bec0baf1de	2984	/**
Wolfgang Betz	67:93bec0baf1de	2985	* @}
Wolfgang Betz	67:93bec0baf1de	2986	*/
Wolfgang Betz	67:93bec0baf1de	2987
Wolfgang Betz	67:93bec0baf1de	2988	/** @defgroup IRQ_STATUS1_Register
Wolfgang Betz	67:93bec0baf1de	2989	* @{
Wolfgang Betz	67:93bec0baf1de	2990	*/
Wolfgang Betz	67:93bec0baf1de	2991
Wolfgang Betz	67:93bec0baf1de	2992	/**
Wolfgang Betz	67:93bec0baf1de	2993	* \brief IRQ_STATUS1 registers
Wolfgang Betz	67:93bec0baf1de	2994	* \code
Wolfgang Betz	67:93bec0baf1de	2995	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	2996	* Read Write
Wolfgang Betz	67:93bec0baf1de	2997	*
Wolfgang Betz	67:93bec0baf1de	2998	* 7:0 INT_STATUS1: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
Wolfgang Betz	67:93bec0baf1de	2999	*
Wolfgang Betz	67:93bec0baf1de	3000	* Bit \| Events Group Interrupt Event
Wolfgang Betz	67:93bec0baf1de	3001	* -------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	3002	* 8 \| TX FIFO almost empty
Wolfgang Betz	67:93bec0baf1de	3003	* 9 \| RX FIFO almost full
Wolfgang Betz	67:93bec0baf1de	3004	* 10 \| RX FIFO almost empty
Wolfgang Betz	67:93bec0baf1de	3005	* 11 \| Max number of back-off during CCA
Wolfgang Betz	67:93bec0baf1de	3006	* 12 \| Valid preamble detected
Wolfgang Betz	67:93bec0baf1de	3007	* 13 \| Sync word detected
Wolfgang Betz	67:93bec0baf1de	3008	* 14 \| RSSI above threshold (Carrier Sense)
Wolfgang Betz	67:93bec0baf1de	3009	* 15 \| Wake-up timeout in LDCR mode13
Wolfgang Betz	67:93bec0baf1de	3010	* \endcode
Wolfgang Betz	67:93bec0baf1de	3011	*/
Wolfgang Betz	67:93bec0baf1de	3012
Wolfgang Betz	67:93bec0baf1de	3013	#define IRQ_STATUS1_BASE ((uint8_t)(0xFC)) /!< IRQ Events(RR, split into 4 registers) /
Wolfgang Betz	67:93bec0baf1de	3014
Wolfgang Betz	67:93bec0baf1de	3015	#define IRQ_STATUS1_READY ((uint8_t)(0x01)) /!< IRQ: READY state in steady condition/
Wolfgang Betz	67:93bec0baf1de	3016	#define IRQ_STATUS1_STANDBY_DELAYED ((uint8_t)(0x02)) /!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles /
Wolfgang Betz	67:93bec0baf1de	3017	#define IRQ_STATUS1_LOW_BATT_LVL ((uint8_t)(0x04)) /!< IRQ: Battery level below threshold/
Wolfgang Betz	67:93bec0baf1de	3018	#define IRQ_STATUS1_POR ((uint8_t)(0x08)) /!< IRQ: Power On Reset /
Wolfgang Betz	67:93bec0baf1de	3019	#define IRQ_STATUS1_BOR ((uint8_t)(0x10)) /!< IRQ: Brown out event (both accurate and inaccurate)/
Wolfgang Betz	67:93bec0baf1de	3020	#define IRQ_STATUS1_LOCK ((uint8_t)(0x20)) /!< IRQ: LOCK state in steady condition /
Wolfgang Betz	67:93bec0baf1de	3021	#define IRQ_STATUS1_PM_COUNT_EXPIRED ((uint8_t)(0x40)) /!< IRQ: Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) /
Wolfgang Betz	67:93bec0baf1de	3022	#define IRQ_STATUS1_XO_COUNT_EXPIRED ((uint8_t)(0x80)) /!< IRQ: Crystal oscillator settling time counter expired /
Wolfgang Betz	67:93bec0baf1de	3023
Wolfgang Betz	67:93bec0baf1de	3024	/**
Wolfgang Betz	67:93bec0baf1de	3025	* @}
Wolfgang Betz	67:93bec0baf1de	3026	*/
Wolfgang Betz	67:93bec0baf1de	3027
Wolfgang Betz	67:93bec0baf1de	3028	/** @defgroup IRQ_STATUS2_Register
Wolfgang Betz	67:93bec0baf1de	3029	* @{
Wolfgang Betz	67:93bec0baf1de	3030	*/
Wolfgang Betz	67:93bec0baf1de	3031
Wolfgang Betz	67:93bec0baf1de	3032	/**
Wolfgang Betz	67:93bec0baf1de	3033	* \brief IRQ_STATUS2 registers
Wolfgang Betz	67:93bec0baf1de	3034	* \code
Wolfgang Betz	67:93bec0baf1de	3035	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	3036	* Read Write
Wolfgang Betz	67:93bec0baf1de	3037	*
Wolfgang Betz	67:93bec0baf1de	3038	* 7:0 INT_STATUS2: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
Wolfgang Betz	67:93bec0baf1de	3039	*
Wolfgang Betz	67:93bec0baf1de	3040	* Bit \| Events Group Interrupt Event
Wolfgang Betz	67:93bec0baf1de	3041	* -------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	3042	* 16 \| READY state in steady condition14
Wolfgang Betz	67:93bec0baf1de	3043	* 17 \| STANDBY state switching in progress
Wolfgang Betz	67:93bec0baf1de	3044	* 18 \| Low battery level
Wolfgang Betz	67:93bec0baf1de	3045	* 19 \| Power-On reset
Wolfgang Betz	67:93bec0baf1de	3046	* 20 \| Brown-Out event
Wolfgang Betz	67:93bec0baf1de	3047	* 21 \| LOCK state in steady condition
Wolfgang Betz	67:93bec0baf1de	3048	* 22 \| PM start-up timer expiration
Wolfgang Betz	67:93bec0baf1de	3049	* 23 \| XO settling timeout
Wolfgang Betz	67:93bec0baf1de	3050	* \endcode
Wolfgang Betz	67:93bec0baf1de	3051	*/
Wolfgang Betz	67:93bec0baf1de	3052
Wolfgang Betz	67:93bec0baf1de	3053	#define IRQ_STATUS2_BASE ((uint8_t)0xFB) /!< IRQ Events(RR, split into 4 registers) /
Wolfgang Betz	67:93bec0baf1de	3054
Wolfgang Betz	67:93bec0baf1de	3055	#define IRQ_STATUS2_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /!< IRQ: TX FIFO almost empty /
Wolfgang Betz	67:93bec0baf1de	3056	#define IRQ_STATUS2_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /!< IRQ: RX FIFO almost full /
Wolfgang Betz	67:93bec0baf1de	3057	#define IRQ_STATUS2_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /!< IRQ: RX FIFO almost empty /
Wolfgang Betz	67:93bec0baf1de	3058	#define IRQ_STATUS2_MAX_BO_CCA_REACH ((uint8_t)0x08) /!< IRQ: Max number of back-off during CCA /
Wolfgang Betz	67:93bec0baf1de	3059	#define IRQ_STATUS2_VALID_PREAMBLE ((uint8_t)0x10) /!< IRQ: Valid preamble detected /
Wolfgang Betz	67:93bec0baf1de	3060	#define IRQ_STATUS2_VALID_SYNC ((uint8_t)0x20) /!< IRQ: Sync word detected /
Wolfgang Betz	67:93bec0baf1de	3061	#define IRQ_STATUS2_RSSI_ABOVE_TH ((uint8_t)(0x40)) /!< IRQ: RSSI above threshold /
Wolfgang Betz	67:93bec0baf1de	3062	#define IRQ_STATUS2_WKUP_TOUT_LDC ((uint8_t)(0x80)) /!< IRQ: Wake-up timeout in LDC mode /
Wolfgang Betz	67:93bec0baf1de	3063
Wolfgang Betz	67:93bec0baf1de	3064	/**
Wolfgang Betz	67:93bec0baf1de	3065	* @}
Wolfgang Betz	67:93bec0baf1de	3066	*/
Wolfgang Betz	67:93bec0baf1de	3067
Wolfgang Betz	67:93bec0baf1de	3068	/** @defgroup IRQ_STATUS3_Register
Wolfgang Betz	67:93bec0baf1de	3069	* @{
Wolfgang Betz	67:93bec0baf1de	3070	*/
Wolfgang Betz	67:93bec0baf1de	3071
Wolfgang Betz	67:93bec0baf1de	3072	/**
Wolfgang Betz	67:93bec0baf1de	3073	* \brief IRQ_STATUS3 registers
Wolfgang Betz	67:93bec0baf1de	3074	* \code
Wolfgang Betz	67:93bec0baf1de	3075	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	3076	* Read Write
Wolfgang Betz	67:93bec0baf1de	3077	*
Wolfgang Betz	67:93bec0baf1de	3078	* 7:0 INT_STATUS3: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
Wolfgang Betz	67:93bec0baf1de	3079	*
Wolfgang Betz	67:93bec0baf1de	3080	* Bit \| Events Group Interrupt Event
Wolfgang Betz	67:93bec0baf1de	3081	* -------------------------------------------------------
Wolfgang Betz	67:93bec0baf1de	3082	* 24 \| SYNTH locking timeout
Wolfgang Betz	67:93bec0baf1de	3083	* 25 \| SYNTH calibration start-up time
Wolfgang Betz	67:93bec0baf1de	3084	* 26 \| SYNTH calibration timeout
Wolfgang Betz	67:93bec0baf1de	3085	* 27 \| TX circuitry start-up time
Wolfgang Betz	67:93bec0baf1de	3086	* 28 \| RX circuitry start-up time
Wolfgang Betz	67:93bec0baf1de	3087	* 29 \| RX operation timeout
Wolfgang Betz	67:93bec0baf1de	3088	* 30 \| Others AES Endof Operation
Wolfgang Betz	67:93bec0baf1de	3089	* 31 \| Reserved
Wolfgang Betz	67:93bec0baf1de	3090	* \endcode
Wolfgang Betz	67:93bec0baf1de	3091	*/
Wolfgang Betz	67:93bec0baf1de	3092	#define IRQ_STATUS3_BASE ((uint8_t)0xFA) /!< IRQ Events(RR, split into 4 registers) /
Wolfgang Betz	67:93bec0baf1de	3093
Wolfgang Betz	67:93bec0baf1de	3094	#define IRQ_STATUS3_RX_DATA_READY ((uint8_t)0x01) /!< IRQ: RX data ready /
Wolfgang Betz	67:93bec0baf1de	3095	#define IRQ_STATUS3_RX_DATA_DISC ((uint8_t)0x02) /!< IRQ: RX data discarded (upon filtering) /
Wolfgang Betz	67:93bec0baf1de	3096	#define IRQ_STATUS3_TX_DATA_SENT ((uint8_t)0x04) /!< IRQ: TX data sent /
Wolfgang Betz	67:93bec0baf1de	3097	#define IRQ_STATUS3_MAX_RE_TX_REACH ((uint8_t)0x08) /!< IRQ: Max re-TX reached /
Wolfgang Betz	67:93bec0baf1de	3098	#define IRQ_STATUS3_CRC_ERROR ((uint8_t)0x10) /!< IRQ: CRC error /
Wolfgang Betz	67:93bec0baf1de	3099	#define IRQ_STATUS3_TX_FIFO_ERROR ((uint8_t)0x20) /!< IRQ: TX FIFO underflow/overflow error /
Wolfgang Betz	67:93bec0baf1de	3100	#define IRQ_STATUS3_RX_FIFO_ERROR ((uint8_t)0x40) /!< IRQ: RX FIFO underflow/overflow error /
Wolfgang Betz	67:93bec0baf1de	3101	#define IRQ_STATUS3_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /!< IRQ: TX FIFO almost full /
Wolfgang Betz	67:93bec0baf1de	3102
Wolfgang Betz	67:93bec0baf1de	3103	/**
Wolfgang Betz	67:93bec0baf1de	3104	* @}
Wolfgang Betz	67:93bec0baf1de	3105	*/
Wolfgang Betz	67:93bec0baf1de	3106
Wolfgang Betz	67:93bec0baf1de	3107	/**
Wolfgang Betz	67:93bec0baf1de	3108	* @}
Wolfgang Betz	67:93bec0baf1de	3109	*/
Wolfgang Betz	67:93bec0baf1de	3110
Wolfgang Betz	67:93bec0baf1de	3111
Wolfgang Betz	67:93bec0baf1de	3112	/** @defgroup MC_STATE_Registers
Wolfgang Betz	67:93bec0baf1de	3113	* @{
Wolfgang Betz	67:93bec0baf1de	3114	*/
Wolfgang Betz	67:93bec0baf1de	3115
Wolfgang Betz	67:93bec0baf1de	3116	/** @defgroup MC_STATE1_Register
Wolfgang Betz	67:93bec0baf1de	3117	* @{
Wolfgang Betz	67:93bec0baf1de	3118	*/
Wolfgang Betz	67:93bec0baf1de	3119
Wolfgang Betz	67:93bec0baf1de	3120	/**
Wolfgang Betz	67:93bec0baf1de	3121	* \brief MC_STATE1 registers
Wolfgang Betz	67:93bec0baf1de	3122	* \code
Wolfgang Betz	67:93bec0baf1de	3123	* Default value: 0x50
Wolfgang Betz	67:93bec0baf1de	3124	* Read
Wolfgang Betz	67:93bec0baf1de	3125	*
Wolfgang Betz	67:93bec0baf1de	3126	* 7:4 Reserved.
Wolfgang Betz	67:93bec0baf1de	3127	*
Wolfgang Betz	67:93bec0baf1de	3128	* 3 ANT_SELECT: Currently selected antenna
Wolfgang Betz	67:93bec0baf1de	3129	*
Wolfgang Betz	67:93bec0baf1de	3130	* 2 TX_FIFO_Full: 1 - TX FIFO is full
Wolfgang Betz	67:93bec0baf1de	3131	*
Wolfgang Betz	67:93bec0baf1de	3132	* 1 RX_FIFO_Empty: 1 - RX FIFO is empty
Wolfgang Betz	67:93bec0baf1de	3133	*
Wolfgang Betz	67:93bec0baf1de	3134	* 0 ERROR_LOCK: 1 - RCO calibrator error
Wolfgang Betz	67:93bec0baf1de	3135	* \endcode
Wolfgang Betz	67:93bec0baf1de	3136	*/
Wolfgang Betz	67:93bec0baf1de	3137	#define MC_STATE1_BASE ((uint8_t)(0xC0)) /!< MC_STATE1 register address (see the SpiritStatus struct /
Wolfgang Betz	67:93bec0baf1de	3138
Wolfgang Betz	67:93bec0baf1de	3139
Wolfgang Betz	67:93bec0baf1de	3140	/**
Wolfgang Betz	67:93bec0baf1de	3141	* @}
Wolfgang Betz	67:93bec0baf1de	3142	*/
Wolfgang Betz	67:93bec0baf1de	3143
Wolfgang Betz	67:93bec0baf1de	3144
Wolfgang Betz	67:93bec0baf1de	3145	/** @defgroup MC_STATE0_Register
Wolfgang Betz	67:93bec0baf1de	3146	* @{
Wolfgang Betz	67:93bec0baf1de	3147	*/
Wolfgang Betz	67:93bec0baf1de	3148
Wolfgang Betz	67:93bec0baf1de	3149	/**
Wolfgang Betz	67:93bec0baf1de	3150	* \brief MC_STATE0 registers
Wolfgang Betz	67:93bec0baf1de	3151	* \code
Wolfgang Betz	67:93bec0baf1de	3152	* Default value: 0x00
Wolfgang Betz	67:93bec0baf1de	3153	* Read
Wolfgang Betz	67:93bec0baf1de	3154	*
Wolfgang Betz	67:93bec0baf1de	3155	* 7:1 STATE[6:0]: Current MC state.
Wolfgang Betz	67:93bec0baf1de	3156	*
Wolfgang Betz	67:93bec0baf1de	3157	* REGISTER VALUE \| STATE
Wolfgang Betz	67:93bec0baf1de	3158	* --------------------------------------------
Wolfgang Betz	67:93bec0baf1de	3159	* 0x40 \| STANDBY
Wolfgang Betz	67:93bec0baf1de	3160	* 0x36 \| SLEEP
Wolfgang Betz	67:93bec0baf1de	3161	* 0x03 \| READY
Wolfgang Betz	67:93bec0baf1de	3162	* 0x3B \| PM setup
Wolfgang Betz	67:93bec0baf1de	3163	* 0x23 \| XO settling
Wolfgang Betz	67:93bec0baf1de	3164	* 0x53 \| SYNTH setup
Wolfgang Betz	67:93bec0baf1de	3165	* 0x1F \| PROTOCOL
Wolfgang Betz	67:93bec0baf1de	3166	* 0x4F \| SYNTH calibration
Wolfgang Betz	67:93bec0baf1de	3167	* 0x0F \| LOCK
Wolfgang Betz	67:93bec0baf1de	3168	* 0x33 \| RX
Wolfgang Betz	67:93bec0baf1de	3169	* 0x5F \| TX
Wolfgang Betz	67:93bec0baf1de	3170	*
Wolfgang Betz	67:93bec0baf1de	3171	* 0 XO_ON: 1 - XO is operating
Wolfgang Betz	67:93bec0baf1de	3172	* \endcode
Wolfgang Betz	67:93bec0baf1de	3173	*/
Wolfgang Betz	67:93bec0baf1de	3174	#define MC_STATE0_BASE ((uint8_t)(0xC1)) /*!< MC_STATE0 register address. In this version ALL existing states have been inserted
Wolfgang Betz	67:93bec0baf1de	3175	and are still to be verified */
Wolfgang Betz	67:93bec0baf1de	3176	/**
Wolfgang Betz	67:93bec0baf1de	3177	* @}
Wolfgang Betz	67:93bec0baf1de	3178	*/
Wolfgang Betz	67:93bec0baf1de	3179
Wolfgang Betz	67:93bec0baf1de	3180	/**
Wolfgang Betz	67:93bec0baf1de	3181	* @}
Wolfgang Betz	67:93bec0baf1de	3182	*/
Wolfgang Betz	67:93bec0baf1de	3183
Wolfgang Betz	67:93bec0baf1de	3184	/** @defgroup Engineering-Test_Registers
Wolfgang Betz	67:93bec0baf1de	3185	* @{
Wolfgang Betz	67:93bec0baf1de	3186	*/
Wolfgang Betz	67:93bec0baf1de	3187
Wolfgang Betz	67:93bec0baf1de	3188	#define SYNTH_CONFIG1_BASE ((uint8_t)(0x9E)) /*!< Synthesizier registers: M, A, K data sync on positive/negative clock edges [4],
Wolfgang Betz	67:93bec0baf1de	3189	Enable Linearization of the charge pump [3], split time 1.75/3.45ns [2], VCO calibration window 16,32,64,128 clock cycles [1:0]*/
Wolfgang Betz	67:93bec0baf1de	3190	#define SYNTH_CONFIG0_BASE ((uint8_t)(0x9F)) /!< Enable DSM randomizer [7], Window width 1.2-7.5ns (Down-up) of lock detector/
Wolfgang Betz	67:93bec0baf1de	3191	#define VCOTH_BASE ((uint8_t)(0xA0)) /*!< Controls the threshold frequency between VCO low and VCO high [7:0]
Wolfgang Betz	67:93bec0baf1de	3192	VCOth frequency=2fXO(96+VCO_TH/16), fmin=4992 MHz, fmax=5820 MHz*/
Wolfgang Betz	67:93bec0baf1de	3193	#define PM_CONFIG2_BASE ((uint8_t)(0xA4)) /!< Enables high current buffer on Temperature sensor, sets SMPS options /
Wolfgang Betz	67:93bec0baf1de	3194	#define PM_CONFIG1_BASE ((uint8_t)(0xA5)) /!< Set SMPS options /
Wolfgang Betz	67:93bec0baf1de	3195	#define PM_CONFIG0_BASE ((uint8_t)(0xA6)) /!< Set SMPS options /
Wolfgang Betz	67:93bec0baf1de	3196	#define VCO_CONFIG_BASE ((uint8_t)(0xA1)) /!< Set VCO current [5:2]part and [1:0] part /
Wolfgang Betz	67:93bec0baf1de	3197	#define XO_CONFIG_BASE ((uint8_t)(0xA7)) /!< Clock management options from XO to digital part /
Wolfgang Betz	67:93bec0baf1de	3198
Wolfgang Betz	67:93bec0baf1de	3199	#define XO_RCO_TEST_BASE ((uint8_t)(0xB4)) /!< Test of XO and RCO /
Wolfgang Betz	67:93bec0baf1de	3200
Wolfgang Betz	67:93bec0baf1de	3201	/**
Wolfgang Betz	67:93bec0baf1de	3202	* @}
Wolfgang Betz	67:93bec0baf1de	3203	*/
Wolfgang Betz	67:93bec0baf1de	3204
Wolfgang Betz	67:93bec0baf1de	3205
Wolfgang Betz	67:93bec0baf1de	3206	/** @addtogroup Commands
Wolfgang Betz	67:93bec0baf1de	3207	* @{
Wolfgang Betz	67:93bec0baf1de	3208	*/
Wolfgang Betz	67:93bec0baf1de	3209
Wolfgang Betz	67:93bec0baf1de	3210	#define COMMAND_TX ((uint8_t)(0x60)) /!< Start to transmit; valid only from READY /
Wolfgang Betz	67:93bec0baf1de	3211	#define COMMAND_RX ((uint8_t)(0x61)) /!< Start to receive; valid only from READY /
Wolfgang Betz	67:93bec0baf1de	3212	#define COMMAND_READY ((uint8_t)(0x62)) /!< Go to READY; valid only from STANDBY or SLEEP or LOCK /
Wolfgang Betz	67:93bec0baf1de	3213	#define COMMAND_STANDBY ((uint8_t)(0x63)) /!< Go to STANDBY; valid only from READY /
Wolfgang Betz	67:93bec0baf1de	3214	#define COMMAND_SLEEP ((uint8_t)(0x64)) /!< Go to SLEEP; valid only from READY /
Wolfgang Betz	67:93bec0baf1de	3215	#define COMMAND_LOCKRX ((uint8_t)(0x65)) /!< Go to LOCK state by using the RX configuration of the synth; valid only from READY /
Wolfgang Betz	67:93bec0baf1de	3216	#define COMMAND_LOCKTX ((uint8_t)(0x66)) /!< Go to LOCK state by using the TX configuration of the synth; valid only from READY /
Wolfgang Betz	67:93bec0baf1de	3217	#define COMMAND_SABORT ((uint8_t)(0x67)) /!< Force exit form TX or RX states and go to READY state; valid only from TX or RX /
Wolfgang Betz	67:93bec0baf1de	3218	#define COMMAND_LDC_RELOAD ((uint8_t)(0x68)) /*!< LDC Mode: Reload the LDC timer with the value stored in the LDC_PRESCALER / COUNTER
Wolfgang Betz	67:93bec0baf1de	3219	registers; valid from all states */
Wolfgang Betz	67:93bec0baf1de	3220	#define COMMAND_SEQUENCE_UPDATE ((uint8_t)(0x69)) /*!< Autoretransmission: Reload the Packet sequence counter with the value stored in the PROTOCOL[2] register
Wolfgang Betz	67:93bec0baf1de	3221	valid from all states */
Wolfgang Betz	67:93bec0baf1de	3222	#define COMMAND_AES_ENC ((uint8_t)(0x6A)) /!< AES: Start the encryption routine; valid from all states; valid from all states /
Wolfgang Betz	67:93bec0baf1de	3223	#define COMMAND_AES_KEY ((uint8_t)(0x6B)) /!< AES: Start the procedure to compute the key for the decryption; valid from all states /
Wolfgang Betz	67:93bec0baf1de	3224	#define COMMAND_AES_DEC ((uint8_t)(0x6C)) /!< AES: Start the decryption routine using the current key; valid from all states /
Wolfgang Betz	67:93bec0baf1de	3225	#define COMMAND_AES_KEY_DEC ((uint8_t)(0x6D)) /!< AES: Compute the key and start the decryption; valid from all states /
Wolfgang Betz	67:93bec0baf1de	3226	#define COMMAND_SRES ((uint8_t)(0x70)) /!< Reset of all digital part, except SPI registers /
Wolfgang Betz	67:93bec0baf1de	3227	#define COMMAND_FLUSHRXFIFO ((uint8_t)(0x71)) /!< Clean the RX FIFO; valid from all states /
Wolfgang Betz	67:93bec0baf1de	3228	#define COMMAND_FLUSHTXFIFO ((uint8_t)(0x72)) /!< Clean the TX FIFO; valid from all states /
Wolfgang Betz	67:93bec0baf1de	3229
Wolfgang Betz	67:93bec0baf1de	3230	/**
Wolfgang Betz	67:93bec0baf1de	3231	* @}
Wolfgang Betz	67:93bec0baf1de	3232	*/
Wolfgang Betz	67:93bec0baf1de	3233
Wolfgang Betz	67:93bec0baf1de	3234	/**
Wolfgang Betz	67:93bec0baf1de	3235	* @}
Wolfgang Betz	67:93bec0baf1de	3236	*/
Wolfgang Betz	67:93bec0baf1de	3237
Wolfgang Betz	67:93bec0baf1de	3238	#ifdef __cplusplus
Wolfgang Betz	67:93bec0baf1de	3239	}
Wolfgang Betz	67:93bec0baf1de	3240	#endif
Wolfgang Betz	67:93bec0baf1de	3241
Wolfgang Betz	67:93bec0baf1de	3242	#endif
Wolfgang Betz	67:93bec0baf1de	3243
Wolfgang Betz	67:93bec0baf1de	3244	/***************** (C) COPYRIGHT 2015 STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	05 Jul 2017
Imports:	273
Forks:	2
Commits:	83
Dependents:	0
Dependencies:	0
Followers:	410

The code in this repository is Apache licensed.

Components

X-NUCLEO-IDS01A4 Sub-1GHz RF Expansion Board