ST
Expansion SW library to control high power stepper motor(s) using IHM03A1 expansion board(s) with Powerstep01 driver.
Dependencies: X_NUCLEO_COMMON ST_INTERFACES
Dependents: IHM03A1_ExampleFor1Motor HelloWorld_IHM03A1 IHM03A1_ExampleFor3Motors KYPHOS_Stepper_Motor_Control
Fork of
X_NUCLEO_IHM03A1
by 
ST Expansion SW Team
Motor Control Library
Library to handle the X-NUCLEO-IHM03A1 Motor Control Expansion Board based on the Powerstep01 component.
It features the:
- read and write of Powerstep01 registers
- Nucleo and expansion board configuration (GPIOs, PWMs, IRQs, etc.)
- Powerstep01 application commands handling
- FLAG and BUSY interrupt handling (alarm reporting)
- Daisy chain handling
The API allows to easily:
- perform various positioning, moves and stops
- get/set or monitor the motor positions
- set home position and mark another position
- get/set minimum and maximum speed
- get current speed
- get/set acceleration and deceleration
- get/set the step mode (up to 1/128)
- get/set the control method
- get/set parameters for voltage mode driving
- get/set parameters for current mode driving
- get/set parameters for gate driving
- configure various protections such as overcurrent detection
- enable/disable alarms
- handle step-clock
- get system status
Daisy-Chain Configuration
The IHM03A1 board can be stacked up to three times so that the Powerstep01 components will be connected in daisy-chain configuration. For this purpose, some resistors must be correctly connected on the boards as depicted here below:
Platform compatibility
Compatible platforms have been tested with the default configuration provided by the HelloWorld_IHM03A1 example.
Components/powerstep01/powerstep01_target_config.h@0:00a3c3f5a8f0, 2016-04-05 (annotated)
- Committer:
- nucleosam
- Date:
- Tue Apr 05 15:18:56 2016 +0000
- Revision:
- 0:00a3c3f5a8f0
Initial version
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| nucleosam | 0:00a3c3f5a8f0 | 1 | /** |
| nucleosam | 0:00a3c3f5a8f0 | 2 | ****************************************************************************** |
| nucleosam | 0:00a3c3f5a8f0 | 3 | * @file powerstep01_target_config.h |
| nucleosam | 0:00a3c3f5a8f0 | 4 | * @author IPC Rennes |
| nucleosam | 0:00a3c3f5a8f0 | 5 | * @version V1.2.0 |
| nucleosam | 0:00a3c3f5a8f0 | 6 | * @date March 18th, 2016 |
| nucleosam | 0:00a3c3f5a8f0 | 7 | * @brief Predefines values for the Powerstep01 registers |
| nucleosam | 0:00a3c3f5a8f0 | 8 | * and for the devices parameters |
| nucleosam | 0:00a3c3f5a8f0 | 9 | * @note (C) COPYRIGHT 2016 STMicroelectronics |
| nucleosam | 0:00a3c3f5a8f0 | 10 | ****************************************************************************** |
| nucleosam | 0:00a3c3f5a8f0 | 11 | * @attention |
| nucleosam | 0:00a3c3f5a8f0 | 12 | * |
| nucleosam | 0:00a3c3f5a8f0 | 13 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| nucleosam | 0:00a3c3f5a8f0 | 14 | * |
| nucleosam | 0:00a3c3f5a8f0 | 15 | * Redistribution and use in source and binary forms, with or without modification, |
| nucleosam | 0:00a3c3f5a8f0 | 16 | * are permitted provided that the following conditions are met: |
| nucleosam | 0:00a3c3f5a8f0 | 17 | * 1. Redistributions of source code must retain the above copyright notice, |
| nucleosam | 0:00a3c3f5a8f0 | 18 | * this list of conditions and the following disclaimer. |
| nucleosam | 0:00a3c3f5a8f0 | 19 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| nucleosam | 0:00a3c3f5a8f0 | 20 | * this list of conditions and the following disclaimer in the documentation |
| nucleosam | 0:00a3c3f5a8f0 | 21 | * and/or other materials provided with the distribution. |
| nucleosam | 0:00a3c3f5a8f0 | 22 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| nucleosam | 0:00a3c3f5a8f0 | 23 | * may be used to endorse or promote products derived from this software |
| nucleosam | 0:00a3c3f5a8f0 | 24 | * without specific prior written permission. |
| nucleosam | 0:00a3c3f5a8f0 | 25 | * |
| nucleosam | 0:00a3c3f5a8f0 | 26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| nucleosam | 0:00a3c3f5a8f0 | 27 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| nucleosam | 0:00a3c3f5a8f0 | 28 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| nucleosam | 0:00a3c3f5a8f0 | 29 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| nucleosam | 0:00a3c3f5a8f0 | 30 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| nucleosam | 0:00a3c3f5a8f0 | 31 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| nucleosam | 0:00a3c3f5a8f0 | 32 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| nucleosam | 0:00a3c3f5a8f0 | 33 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| nucleosam | 0:00a3c3f5a8f0 | 34 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| nucleosam | 0:00a3c3f5a8f0 | 35 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| nucleosam | 0:00a3c3f5a8f0 | 36 | * |
| nucleosam | 0:00a3c3f5a8f0 | 37 | ****************************************************************************** |
| nucleosam | 0:00a3c3f5a8f0 | 38 | */ |
| nucleosam | 0:00a3c3f5a8f0 | 39 | |
| nucleosam | 0:00a3c3f5a8f0 | 40 | |
| nucleosam | 0:00a3c3f5a8f0 | 41 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| nucleosam | 0:00a3c3f5a8f0 | 42 | |
| nucleosam | 0:00a3c3f5a8f0 | 43 | #ifndef __POWERSTEP01_TARGET_CONFIG_H |
| nucleosam | 0:00a3c3f5a8f0 | 44 | #define __POWERSTEP01_TARGET_CONFIG_H |
| nucleosam | 0:00a3c3f5a8f0 | 45 | |
| nucleosam | 0:00a3c3f5a8f0 | 46 | #ifdef __cplusplus |
| nucleosam | 0:00a3c3f5a8f0 | 47 | extern "C" { |
| nucleosam | 0:00a3c3f5a8f0 | 48 | #endif |
| nucleosam | 0:00a3c3f5a8f0 | 49 | |
| nucleosam | 0:00a3c3f5a8f0 | 50 | /* Definitions ---------------------------------------------------------------*/ |
| nucleosam | 0:00a3c3f5a8f0 | 51 | |
| nucleosam | 0:00a3c3f5a8f0 | 52 | /** @addtogroup POWERSTEP01 |
| nucleosam | 0:00a3c3f5a8f0 | 53 | * @{ |
| nucleosam | 0:00a3c3f5a8f0 | 54 | */ |
| nucleosam | 0:00a3c3f5a8f0 | 55 | |
| nucleosam | 0:00a3c3f5a8f0 | 56 | /** @addtogroup Powerstep01_Exported_Defines |
| nucleosam | 0:00a3c3f5a8f0 | 57 | * @{ |
| nucleosam | 0:00a3c3f5a8f0 | 58 | */ |
| nucleosam | 0:00a3c3f5a8f0 | 59 | |
| nucleosam | 0:00a3c3f5a8f0 | 60 | /** @defgroup Predefined_Powerstep01_Registers_Values Predefined Powerstep01 Registers Values |
| nucleosam | 0:00a3c3f5a8f0 | 61 | * @{ |
| nucleosam | 0:00a3c3f5a8f0 | 62 | */ |
| nucleosam | 0:00a3c3f5a8f0 | 63 | |
| nucleosam | 0:00a3c3f5a8f0 | 64 | /// The maximum number of devices in the daisy chain |
| nucleosam | 0:00a3c3f5a8f0 | 65 | #define MAX_NUMBER_OF_DEVICES (3) |
| nucleosam | 0:00a3c3f5a8f0 | 66 | |
| nucleosam | 0:00a3c3f5a8f0 | 67 | /****************************************************************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 68 | /* Device 0 */ |
| nucleosam | 0:00a3c3f5a8f0 | 69 | /****************************************************************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 70 | |
| nucleosam | 0:00a3c3f5a8f0 | 71 | /**************************** Speed Profile *********************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 72 | /// Register : ACC |
| nucleosam | 0:00a3c3f5a8f0 | 73 | /// Acceleration rate in step/s2, range 14.55 to 59590 steps/s^2 |
| nucleosam | 0:00a3c3f5a8f0 | 74 | #define POWERSTEP01_CONF_PARAM_ACC_DEVICE_0 (582) |
| nucleosam | 0:00a3c3f5a8f0 | 75 | |
| nucleosam | 0:00a3c3f5a8f0 | 76 | /// Register : DEC |
| nucleosam | 0:00a3c3f5a8f0 | 77 | /// Deceleration rate in step/s2, range 14.55 to 59590 steps/s^2 |
| nucleosam | 0:00a3c3f5a8f0 | 78 | #define POWERSTEP01_CONF_PARAM_DEC_DEVICE_0 (582) |
| nucleosam | 0:00a3c3f5a8f0 | 79 | |
| nucleosam | 0:00a3c3f5a8f0 | 80 | ///Register : MAX_SPEED |
| nucleosam | 0:00a3c3f5a8f0 | 81 | /// Maximum speed in step/s, range 15.25 to 15610 steps/s |
| nucleosam | 0:00a3c3f5a8f0 | 82 | #define POWERSTEP01_CONF_PARAM_MAX_SPEED_DEVICE_0 (488) |
| nucleosam | 0:00a3c3f5a8f0 | 83 | |
| nucleosam | 0:00a3c3f5a8f0 | 84 | /// Register : MIN_SPEED |
| nucleosam | 0:00a3c3f5a8f0 | 85 | /// Minimum speed in step/s, range 0 to 976.3 steps/s |
| nucleosam | 0:00a3c3f5a8f0 | 86 | #define POWERSTEP01_CONF_PARAM_MIN_SPEED_DEVICE_0 (0) |
| nucleosam | 0:00a3c3f5a8f0 | 87 | |
| nucleosam | 0:00a3c3f5a8f0 | 88 | /// Register : FS_SPD |
| nucleosam | 0:00a3c3f5a8f0 | 89 | /// Full step speed in step/s, range 7.63 to 15625 steps/s |
| nucleosam | 0:00a3c3f5a8f0 | 90 | #define POWERSTEP01_CONF_PARAM_FS_SPD_DEVICE_0 (244.16) |
| nucleosam | 0:00a3c3f5a8f0 | 91 | |
| nucleosam | 0:00a3c3f5a8f0 | 92 | /// Register : FS_SPD - field : BOOST_MODE |
| nucleosam | 0:00a3c3f5a8f0 | 93 | /// Boost of the amplitude square wave, enum powerstep01_BoostMode_t |
| nucleosam | 0:00a3c3f5a8f0 | 94 | #define POWERSTEP01_CONF_PARAM_BOOST_MODE_DEVICE_0 (POWERSTEP01_BOOST_MODE_OFF) |
| nucleosam | 0:00a3c3f5a8f0 | 95 | |
| nucleosam | 0:00a3c3f5a8f0 | 96 | |
| nucleosam | 0:00a3c3f5a8f0 | 97 | /************************ Voltage mode parameters **************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 98 | /// Register : KVAL_ACC |
| nucleosam | 0:00a3c3f5a8f0 | 99 | /// Acceleration duty cycle (torque) in %, range 0 to 99.6% |
| nucleosam | 0:00a3c3f5a8f0 | 100 | #define POWERSTEP01_CONF_PARAM_KVAL_ACC_DEVICE_0 (16.02) |
| nucleosam | 0:00a3c3f5a8f0 | 101 | |
| nucleosam | 0:00a3c3f5a8f0 | 102 | /// Register : KVAL_DEC |
| nucleosam | 0:00a3c3f5a8f0 | 103 | /// Deceleration duty cycle (torque) in %, range 0 to 99.6% |
| nucleosam | 0:00a3c3f5a8f0 | 104 | #define POWERSTEP01_CONF_PARAM_KVAL_DEC_DEVICE_0 (16.02) |
| nucleosam | 0:00a3c3f5a8f0 | 105 | |
| nucleosam | 0:00a3c3f5a8f0 | 106 | /// Register : KVAL_RUN |
| nucleosam | 0:00a3c3f5a8f0 | 107 | /// Run duty cycle (torque) in %, range 0 to 99.6% |
| nucleosam | 0:00a3c3f5a8f0 | 108 | #define POWERSTEP01_CONF_PARAM_KVAL_RUN_DEVICE_0 (16.02) |
| nucleosam | 0:00a3c3f5a8f0 | 109 | |
| nucleosam | 0:00a3c3f5a8f0 | 110 | /// Register : KVAL_HOLD |
| nucleosam | 0:00a3c3f5a8f0 | 111 | /// Hold duty cycle (torque) in %, range 0 to 99.6% |
| nucleosam | 0:00a3c3f5a8f0 | 112 | #define POWERSTEP01_CONF_PARAM_KVAL_HOLD_DEVICE_0 (16.02) |
| nucleosam | 0:00a3c3f5a8f0 | 113 | |
| nucleosam | 0:00a3c3f5a8f0 | 114 | /// Register : CONFIG - field : EN_VSCOMP |
| nucleosam | 0:00a3c3f5a8f0 | 115 | /// Motor Supply Voltage Compensation enabling , enum powerstep01_ConfigEnVscomp_t |
| nucleosam | 0:00a3c3f5a8f0 | 116 | #define POWERSTEP01_CONF_PARAM_VS_COMP_DEVICE_0 (POWERSTEP01_CONFIG_VS_COMP_DISABLE) |
| nucleosam | 0:00a3c3f5a8f0 | 117 | |
| nucleosam | 0:00a3c3f5a8f0 | 118 | /// Register : MIN_SPEED - field : LSPD_OPT |
| nucleosam | 0:00a3c3f5a8f0 | 119 | /// Low speed optimization bit, enum powerstep01_LspdOpt_t |
| nucleosam | 0:00a3c3f5a8f0 | 120 | #define POWERSTEP01_CONF_PARAM_LSPD_BIT_DEVICE_0 (POWERSTEP01_LSPD_OPT_OFF) |
| nucleosam | 0:00a3c3f5a8f0 | 121 | |
| nucleosam | 0:00a3c3f5a8f0 | 122 | /// Register : K_THERM |
| nucleosam | 0:00a3c3f5a8f0 | 123 | /// Thermal compensation param, range 1 to 1.46875 |
| nucleosam | 0:00a3c3f5a8f0 | 124 | #define POWERSTEP01_CONF_PARAM_K_THERM_DEVICE_0 (1) |
| nucleosam | 0:00a3c3f5a8f0 | 125 | |
| nucleosam | 0:00a3c3f5a8f0 | 126 | /// Register : INT_SPEED |
| nucleosam | 0:00a3c3f5a8f0 | 127 | /// Intersect speed settings for BEMF compensation in steps/s, range 0 to 3906 steps/s |
| nucleosam | 0:00a3c3f5a8f0 | 128 | #define POWERSTEP01_CONF_PARAM_INT_SPD_DEVICE_0 (61.512) |
| nucleosam | 0:00a3c3f5a8f0 | 129 | |
| nucleosam | 0:00a3c3f5a8f0 | 130 | /// Register : ST_SLP |
| nucleosam | 0:00a3c3f5a8f0 | 131 | /// BEMF start slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
| nucleosam | 0:00a3c3f5a8f0 | 132 | #define POWERSTEP01_CONF_PARAM_ST_SLP_DEVICE_0 (0.03815) |
| nucleosam | 0:00a3c3f5a8f0 | 133 | |
| nucleosam | 0:00a3c3f5a8f0 | 134 | /// Register : FN_SLP_ACC |
| nucleosam | 0:00a3c3f5a8f0 | 135 | /// BEMF final acc slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
| nucleosam | 0:00a3c3f5a8f0 | 136 | #define POWERSTEP01_CONF_PARAM_FN_SLP_ACC_DEVICE_0 (0.06256) |
| nucleosam | 0:00a3c3f5a8f0 | 137 | |
| nucleosam | 0:00a3c3f5a8f0 | 138 | /// Register : FN_SLP_DEC |
| nucleosam | 0:00a3c3f5a8f0 | 139 | /// BEMF final dec slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
| nucleosam | 0:00a3c3f5a8f0 | 140 | #define POWERSTEP01_CONF_PARAM_FN_SLP_DEC_DEVICE_0 (0.06256) |
| nucleosam | 0:00a3c3f5a8f0 | 141 | |
| nucleosam | 0:00a3c3f5a8f0 | 142 | /// Register : CONFIG - field : F_PWM_INT |
| nucleosam | 0:00a3c3f5a8f0 | 143 | /// PWM Frequency Integer division, enum powerstep01_ConfigFPwmInt_t |
| nucleosam | 0:00a3c3f5a8f0 | 144 | #define POWERSTEP01_CONF_PARAM_PWM_DIV_DEVICE_0 (POWERSTEP01_CONFIG_PWM_DIV_2) |
| nucleosam | 0:00a3c3f5a8f0 | 145 | |
| nucleosam | 0:00a3c3f5a8f0 | 146 | /// Register : CONFIG - field : F_PWM_DEC |
| nucleosam | 0:00a3c3f5a8f0 | 147 | /// PWM Frequency Integer Multiplier, enum powerstep01_ConfigFPwmDec_t |
| nucleosam | 0:00a3c3f5a8f0 | 148 | #define POWERSTEP01_CONF_PARAM_PWM_MUL_DEVICE_0 (POWERSTEP01_CONFIG_PWM_MUL_1) |
| nucleosam | 0:00a3c3f5a8f0 | 149 | |
| nucleosam | 0:00a3c3f5a8f0 | 150 | /******************** Advance current control parameters *********************/ |
| nucleosam | 0:00a3c3f5a8f0 | 151 | |
| nucleosam | 0:00a3c3f5a8f0 | 152 | /// Register : TVAL_ACC |
| nucleosam | 0:00a3c3f5a8f0 | 153 | /// Acceleration torque in mV, range from 7.8mV to 1000 mV |
| nucleosam | 0:00a3c3f5a8f0 | 154 | #define POWERSTEP01_CONF_PARAM_TVAL_ACC_DEVICE_0 (328.12) |
| nucleosam | 0:00a3c3f5a8f0 | 155 | |
| nucleosam | 0:00a3c3f5a8f0 | 156 | /// Register : TVAL_DEC |
| nucleosam | 0:00a3c3f5a8f0 | 157 | /// Deceleration torque in mV, range from 7.8mV to 1000 mV |
| nucleosam | 0:00a3c3f5a8f0 | 158 | #define POWERSTEP01_CONF_PARAM_TVAL_DEC_DEVICE_0 (328.12) |
| nucleosam | 0:00a3c3f5a8f0 | 159 | |
| nucleosam | 0:00a3c3f5a8f0 | 160 | /// Register : TVAL_RUN |
| nucleosam | 0:00a3c3f5a8f0 | 161 | /// Running torque in mV, range from 7.8mV to 1000 mV |
| nucleosam | 0:00a3c3f5a8f0 | 162 | #define POWERSTEP01_CONF_PARAM_TVAL_RUN_DEVICE_0 (328.12) |
| nucleosam | 0:00a3c3f5a8f0 | 163 | |
| nucleosam | 0:00a3c3f5a8f0 | 164 | /// Register : TVAL_HOLD |
| nucleosam | 0:00a3c3f5a8f0 | 165 | /// Holding torque in mV, range from 7.8mV to 1000 mV |
| nucleosam | 0:00a3c3f5a8f0 | 166 | #define POWERSTEP01_CONF_PARAM_TVAL_HOLD_DEVICE_0 (328.12) |
| nucleosam | 0:00a3c3f5a8f0 | 167 | |
| nucleosam | 0:00a3c3f5a8f0 | 168 | /// Register : CONFIG - field : EN_TQREG |
| nucleosam | 0:00a3c3f5a8f0 | 169 | /// External torque regulation enabling , enum powerstep01_ConfigEnTqReg_t |
| nucleosam | 0:00a3c3f5a8f0 | 170 | #define POWERSTEP01_CONF_PARAM_TQ_REG_DEVICE_0 (POWERSTEP01_CONFIG_TQ_REG_TVAL_USED) |
| nucleosam | 0:00a3c3f5a8f0 | 171 | |
| nucleosam | 0:00a3c3f5a8f0 | 172 | /// Register : CONFIG - field : PRED_EN |
| nucleosam | 0:00a3c3f5a8f0 | 173 | /// Predictive current enabling , enum powerstep01_ConfigPredEn_t |
| nucleosam | 0:00a3c3f5a8f0 | 174 | #define POWERSTEP01_CONF_PARAM_PRED_DEVICE_0 (POWERSTEP01_CONFIG_PRED_DISABLE) |
| nucleosam | 0:00a3c3f5a8f0 | 175 | |
| nucleosam | 0:00a3c3f5a8f0 | 176 | /// Register : TON_MIN |
| nucleosam | 0:00a3c3f5a8f0 | 177 | /// Minimum on-time in us, range 0.5us to 64us |
| nucleosam | 0:00a3c3f5a8f0 | 178 | #define POWERSTEP01_CONF_PARAM_TON_MIN_DEVICE_0 (3.0) |
| nucleosam | 0:00a3c3f5a8f0 | 179 | |
| nucleosam | 0:00a3c3f5a8f0 | 180 | /// Register : TOFF_MIN |
| nucleosam | 0:00a3c3f5a8f0 | 181 | /// Minimum off-time in us, range 0.5us to 64us |
| nucleosam | 0:00a3c3f5a8f0 | 182 | #define POWERSTEP01_CONF_PARAM_TOFF_MIN_DEVICE_0 (21.0) |
| nucleosam | 0:00a3c3f5a8f0 | 183 | |
| nucleosam | 0:00a3c3f5a8f0 | 184 | /// Register : T_FAST - field: TOFF_FAST |
| nucleosam | 0:00a3c3f5a8f0 | 185 | /// Maximum fast decay time , enum powerstep01_ToffFast_t |
| nucleosam | 0:00a3c3f5a8f0 | 186 | #define POWERSTEP01_CONF_PARAM_TOFF_FAST_DEVICE_0 (POWERSTEP01_TOFF_FAST_8us) |
| nucleosam | 0:00a3c3f5a8f0 | 187 | |
| nucleosam | 0:00a3c3f5a8f0 | 188 | /// Register : T_FAST - field: FAST_STEP |
| nucleosam | 0:00a3c3f5a8f0 | 189 | /// Maximum fall step time , enum powerstep01_FastStep_t |
| nucleosam | 0:00a3c3f5a8f0 | 190 | #define POWERSTEP01_CONF_PARAM_FAST_STEP_DEVICE_0 (POWERSTEP01_FAST_STEP_12us) |
| nucleosam | 0:00a3c3f5a8f0 | 191 | |
| nucleosam | 0:00a3c3f5a8f0 | 192 | /// Register : CONFIG - field : TSW |
| nucleosam | 0:00a3c3f5a8f0 | 193 | /// Switching period, enum powerstep01_ConfigTsw_t |
| nucleosam | 0:00a3c3f5a8f0 | 194 | #define POWERSTEP01_CONF_PARAM_TSW_DEVICE_0 (POWERSTEP01_CONFIG_TSW_048us) |
| nucleosam | 0:00a3c3f5a8f0 | 195 | |
| nucleosam | 0:00a3c3f5a8f0 | 196 | /****************************** Gate Driving **********************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 197 | |
| nucleosam | 0:00a3c3f5a8f0 | 198 | /// Register : GATECFG1 - field : IGATE |
| nucleosam | 0:00a3c3f5a8f0 | 199 | /// Gate sink/source current via enum powerstep01_Igate_t |
| nucleosam | 0:00a3c3f5a8f0 | 200 | #define POWERSTEP01_CONF_PARAM_IGATE_DEVICE_0 (POWERSTEP01_IGATE_64mA) |
| nucleosam | 0:00a3c3f5a8f0 | 201 | |
| nucleosam | 0:00a3c3f5a8f0 | 202 | /// Register : CONFIG - field : VCCVAL |
| nucleosam | 0:00a3c3f5a8f0 | 203 | /// VCC Val, enum powerstep01_ConfigVccVal_t |
| nucleosam | 0:00a3c3f5a8f0 | 204 | #define POWERSTEP01_CONF_PARAM_VCCVAL_DEVICE_0 (POWERSTEP01_CONFIG_VCCVAL_15V) |
| nucleosam | 0:00a3c3f5a8f0 | 205 | |
| nucleosam | 0:00a3c3f5a8f0 | 206 | /// Register : CONFIG - field : UVLOVAL |
| nucleosam | 0:00a3c3f5a8f0 | 207 | /// UVLO Threshold via powerstep01_ConfigUvLoVal_t |
| nucleosam | 0:00a3c3f5a8f0 | 208 | #define POWERSTEP01_CONF_PARAM_UVLOVAL_DEVICE_0 (POWERSTEP01_CONFIG_UVLOVAL_LOW) |
| nucleosam | 0:00a3c3f5a8f0 | 209 | |
| nucleosam | 0:00a3c3f5a8f0 | 210 | /// Register : GATECFG1 - field : TBOOST |
| nucleosam | 0:00a3c3f5a8f0 | 211 | /// Duration of the overboost phase during gate turn-off via enum powerstep01_Tboost_t |
| nucleosam | 0:00a3c3f5a8f0 | 212 | #define POWERSTEP01_CONF_PARAM_TBOOST_DEVICE_0 (POWERSTEP01_TBOOST_0ns) |
| nucleosam | 0:00a3c3f5a8f0 | 213 | |
| nucleosam | 0:00a3c3f5a8f0 | 214 | /// Register : GATECFG1 - field : TCC |
| nucleosam | 0:00a3c3f5a8f0 | 215 | /// Controlled current time via enum powerstep01_Tcc_t |
| nucleosam | 0:00a3c3f5a8f0 | 216 | #define POWERSTEP01_CONF_PARAM_TCC_DEVICE_0 (POWERSTEP01_TCC_500ns) |
| nucleosam | 0:00a3c3f5a8f0 | 217 | |
| nucleosam | 0:00a3c3f5a8f0 | 218 | /// Duration of the blanking time via enum powerstep01_TBlank_t |
| nucleosam | 0:00a3c3f5a8f0 | 219 | #define POWERSTEP01_CONF_PARAM_TBLANK_DEVICE_0 (POWERSTEP01_TBLANK_375ns) |
| nucleosam | 0:00a3c3f5a8f0 | 220 | |
| nucleosam | 0:00a3c3f5a8f0 | 221 | /// Register : GATECFG2 - field : TDT |
| nucleosam | 0:00a3c3f5a8f0 | 222 | /// Duration of the dead time via enum powerstep01_Tdt_t |
| nucleosam | 0:00a3c3f5a8f0 | 223 | #define POWERSTEP01_CONF_PARAM_TDT_DEVICE_0 (POWERSTEP01_TDT_125ns) |
| nucleosam | 0:00a3c3f5a8f0 | 224 | |
| nucleosam | 0:00a3c3f5a8f0 | 225 | /******************************* Others *************************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 226 | |
| nucleosam | 0:00a3c3f5a8f0 | 227 | /// Register : OCD_TH |
| nucleosam | 0:00a3c3f5a8f0 | 228 | /// Overcurrent threshold settings via enum powerstep01_OcdTh_t |
| nucleosam | 0:00a3c3f5a8f0 | 229 | #define POWERSTEP01_CONF_PARAM_OCD_TH_DEVICE_0 (POWERSTEP01_OCD_TH_281_25mV) |
| nucleosam | 0:00a3c3f5a8f0 | 230 | |
| nucleosam | 0:00a3c3f5a8f0 | 231 | /// Register : CONFIG - field : OC_SD |
| nucleosam | 0:00a3c3f5a8f0 | 232 | /// Over current shutwdown enabling, enum powerstep01_ConfigOcSd_t |
| nucleosam | 0:00a3c3f5a8f0 | 233 | #define POWERSTEP01_CONF_PARAM_OC_SD_DEVICE_0 (POWERSTEP01_CONFIG_OC_SD_DISABLE) |
| nucleosam | 0:00a3c3f5a8f0 | 234 | |
| nucleosam | 0:00a3c3f5a8f0 | 235 | /// Register : STALL_TH |
| nucleosam | 0:00a3c3f5a8f0 | 236 | /// Stall threshold settings in mV, range 31.25mV to 1000mV |
| nucleosam | 0:00a3c3f5a8f0 | 237 | #define POWERSTEP01_CONF_PARAM_STALL_TH_DEVICE_0 (531.25) |
| nucleosam | 0:00a3c3f5a8f0 | 238 | |
| nucleosam | 0:00a3c3f5a8f0 | 239 | /// Register : ALARM_EN |
| nucleosam | 0:00a3c3f5a8f0 | 240 | /// Alarm settings via bitmap enum powerstep01_AlarmEn_t |
| nucleosam | 0:00a3c3f5a8f0 | 241 | #define POWERSTEP01_CONF_PARAM_ALARM_EN_DEVICE_0 (POWERSTEP01_ALARM_EN_OVERCURRENT | \ |
| nucleosam | 0:00a3c3f5a8f0 | 242 | POWERSTEP01_ALARM_EN_THERMAL_SHUTDOWN | \ |
| nucleosam | 0:00a3c3f5a8f0 | 243 | POWERSTEP01_ALARM_EN_THERMAL_WARNING | \ |
| nucleosam | 0:00a3c3f5a8f0 | 244 | POWERSTEP01_ALARM_EN_UVLO | \ |
| nucleosam | 0:00a3c3f5a8f0 | 245 | POWERSTEP01_ALARM_EN_STALL_DETECTION | \ |
| nucleosam | 0:00a3c3f5a8f0 | 246 | POWERSTEP01_ALARM_EN_SW_TURN_ON | \ |
| nucleosam | 0:00a3c3f5a8f0 | 247 | POWERSTEP01_ALARM_EN_WRONG_NPERF_CMD) |
| nucleosam | 0:00a3c3f5a8f0 | 248 | |
| nucleosam | 0:00a3c3f5a8f0 | 249 | /// Register : CONFIG - field : SW_MODE |
| nucleosam | 0:00a3c3f5a8f0 | 250 | /// External switch hard stop interrupt mode, enum powerstep01_ConfigSwMode_t |
| nucleosam | 0:00a3c3f5a8f0 | 251 | #define POWERSTEP01_CONF_PARAM_SW_MODE_DEVICE_0 (POWERSTEP01_CONFIG_SW_HARD_STOP) |
| nucleosam | 0:00a3c3f5a8f0 | 252 | |
| nucleosam | 0:00a3c3f5a8f0 | 253 | /// Register : STEP_MODE - field : STEP_MODE |
| nucleosam | 0:00a3c3f5a8f0 | 254 | /// Step mode settings via enum motorStepMode_t |
| nucleosam | 0:00a3c3f5a8f0 | 255 | #define POWERSTEP01_CONF_PARAM_STEP_MODE_DEVICE_0 (STEP_MODE_1_16) |
| nucleosam | 0:00a3c3f5a8f0 | 256 | |
| nucleosam | 0:00a3c3f5a8f0 | 257 | /// Register : STEP_MODE - field : CM_VM |
| nucleosam | 0:00a3c3f5a8f0 | 258 | /// Current mode or Voltage mode via enum powerstep01_CmVm_t |
| nucleosam | 0:00a3c3f5a8f0 | 259 | #define POWERSTEP01_CONF_PARAM_CM_VM_DEVICE_0 (POWERSTEP01_CM_VM_CURRENT) |
| nucleosam | 0:00a3c3f5a8f0 | 260 | |
| nucleosam | 0:00a3c3f5a8f0 | 261 | /// Register : STEP_MODE - Field : SYNC_MODE and SYNC_EN |
| nucleosam | 0:00a3c3f5a8f0 | 262 | /// Synch. Mode settings via enum powerstep01_SyncSel_t |
| nucleosam | 0:00a3c3f5a8f0 | 263 | #define POWERSTEP01_CONF_PARAM_SYNC_MODE_DEVICE_0 (POWERSTEP01_SYNC_SEL_DISABLED) |
| nucleosam | 0:00a3c3f5a8f0 | 264 | |
| nucleosam | 0:00a3c3f5a8f0 | 265 | /// Register : CONFIG - field : OSC_CLK_SEL |
| nucleosam | 0:00a3c3f5a8f0 | 266 | /// Clock setting , enum powerstep01_ConfigOscMgmt_t |
| nucleosam | 0:00a3c3f5a8f0 | 267 | #define POWERSTEP01_CONF_PARAM_CLOCK_SETTING_DEVICE_0 (POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_2MHZ) |
| nucleosam | 0:00a3c3f5a8f0 | 268 | |
| nucleosam | 0:00a3c3f5a8f0 | 269 | /// Register : GATECFG1 - field : WD_EN |
| nucleosam | 0:00a3c3f5a8f0 | 270 | /// External clock watchdog, enum powerstep01_WdEn_t |
| nucleosam | 0:00a3c3f5a8f0 | 271 | #define POWERSTEP01_CONF_PARAM_WD_EN_DEVICE_0 (POWERSTEP01_WD_EN_DISABLE) |
| nucleosam | 0:00a3c3f5a8f0 | 272 | |
| nucleosam | 0:00a3c3f5a8f0 | 273 | /****************************************************************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 274 | /* Device 1 */ |
| nucleosam | 0:00a3c3f5a8f0 | 275 | /****************************************************************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 276 | |
| nucleosam | 0:00a3c3f5a8f0 | 277 | /**************************** Speed Profile *********************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 278 | /// Register : ACC |
| nucleosam | 0:00a3c3f5a8f0 | 279 | /// Acceleration rate in step/s2, range 14.55 to 59590 steps/s^2 |
| nucleosam | 0:00a3c3f5a8f0 | 280 | #define POWERSTEP01_CONF_PARAM_ACC_DEVICE_1 (2008.16) |
| nucleosam | 0:00a3c3f5a8f0 | 281 | |
| nucleosam | 0:00a3c3f5a8f0 | 282 | /// Register : DEC |
| nucleosam | 0:00a3c3f5a8f0 | 283 | /// Deceleration rate in step/s2, range 14.55 to 59590 steps/s^2 |
| nucleosam | 0:00a3c3f5a8f0 | 284 | #define POWERSTEP01_CONF_PARAM_DEC_DEVICE_1 (2008.16) |
| nucleosam | 0:00a3c3f5a8f0 | 285 | |
| nucleosam | 0:00a3c3f5a8f0 | 286 | ///Register : MAX_SPEED |
| nucleosam | 0:00a3c3f5a8f0 | 287 | /// Maximum speed in step/s, range 15.25 to 15610 steps/s |
| nucleosam | 0:00a3c3f5a8f0 | 288 | #define POWERSTEP01_CONF_PARAM_MAX_SPEED_DEVICE_1 (991.82) |
| nucleosam | 0:00a3c3f5a8f0 | 289 | |
| nucleosam | 0:00a3c3f5a8f0 | 290 | /// Register : MIN_SPEED |
| nucleosam | 0:00a3c3f5a8f0 | 291 | /// Minimum speed in step/s, range 0 to 976.3 steps/s |
| nucleosam | 0:00a3c3f5a8f0 | 292 | #define POWERSTEP01_CONF_PARAM_MIN_SPEED_DEVICE_1 (0) |
| nucleosam | 0:00a3c3f5a8f0 | 293 | |
| nucleosam | 0:00a3c3f5a8f0 | 294 | /// Register : FS_SPD |
| nucleosam | 0:00a3c3f5a8f0 | 295 | /// Full step speed in step/s, range 7.63 to 15625 steps/s |
| nucleosam | 0:00a3c3f5a8f0 | 296 | #define POWERSTEP01_CONF_PARAM_FS_SPD_DEVICE_1 (595.09) |
| nucleosam | 0:00a3c3f5a8f0 | 297 | |
| nucleosam | 0:00a3c3f5a8f0 | 298 | /// Register : FS_SPD - field : BOOST_MODE |
| nucleosam | 0:00a3c3f5a8f0 | 299 | /// Boost of the amplitude square wave, enum powerstep01_BoostMode_t |
| nucleosam | 0:00a3c3f5a8f0 | 300 | #define POWERSTEP01_CONF_PARAM_BOOST_MODE_DEVICE_1 (POWERSTEP01_BOOST_MODE_OFF) |
| nucleosam | 0:00a3c3f5a8f0 | 301 | |
| nucleosam | 0:00a3c3f5a8f0 | 302 | |
| nucleosam | 0:00a3c3f5a8f0 | 303 | /************************ Voltage mode parameters **************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 304 | /// Register : KVAL_ACC |
| nucleosam | 0:00a3c3f5a8f0 | 305 | /// Acceleration duty cycle (torque) in %, range 0 to 99.6% |
| nucleosam | 0:00a3c3f5a8f0 | 306 | #define POWERSTEP01_CONF_PARAM_KVAL_ACC_DEVICE_1 (16.02) |
| nucleosam | 0:00a3c3f5a8f0 | 307 | |
| nucleosam | 0:00a3c3f5a8f0 | 308 | /// Register : KVAL_DEC |
| nucleosam | 0:00a3c3f5a8f0 | 309 | /// Deceleration duty cycle (torque) in %, range 0 to 99.6% |
| nucleosam | 0:00a3c3f5a8f0 | 310 | #define POWERSTEP01_CONF_PARAM_KVAL_DEC_DEVICE_1 (16.02) |
| nucleosam | 0:00a3c3f5a8f0 | 311 | |
| nucleosam | 0:00a3c3f5a8f0 | 312 | /// Register : KVAL_RUN |
| nucleosam | 0:00a3c3f5a8f0 | 313 | /// Run duty cycle (torque) in %, range 0 to 99.6% |
| nucleosam | 0:00a3c3f5a8f0 | 314 | #define POWERSTEP01_CONF_PARAM_KVAL_RUN_DEVICE_1 (16.02) |
| nucleosam | 0:00a3c3f5a8f0 | 315 | |
| nucleosam | 0:00a3c3f5a8f0 | 316 | /// Register : KVAL_HOLD |
| nucleosam | 0:00a3c3f5a8f0 | 317 | /// Hold duty cycle (torque) in %, range 0 to 99.6% |
| nucleosam | 0:00a3c3f5a8f0 | 318 | #define POWERSTEP01_CONF_PARAM_KVAL_HOLD_DEVICE_1 (16.02) |
| nucleosam | 0:00a3c3f5a8f0 | 319 | |
| nucleosam | 0:00a3c3f5a8f0 | 320 | /// Register : CONFIG - field : EN_VSCOMP |
| nucleosam | 0:00a3c3f5a8f0 | 321 | /// Motor Supply Voltage Compensation enabling , enum powerstep01_ConfigEnVscomp_t |
| nucleosam | 0:00a3c3f5a8f0 | 322 | #define POWERSTEP01_CONF_PARAM_VS_COMP_DEVICE_1 (POWERSTEP01_CONFIG_VS_COMP_DISABLE) |
| nucleosam | 0:00a3c3f5a8f0 | 323 | |
| nucleosam | 0:00a3c3f5a8f0 | 324 | /// Register : MIN_SPEED - field : LSPD_OPT |
| nucleosam | 0:00a3c3f5a8f0 | 325 | /// Low speed optimization bit, enum powerstep01_LspdOpt_t |
| nucleosam | 0:00a3c3f5a8f0 | 326 | #define POWERSTEP01_CONF_PARAM_LSPD_BIT_DEVICE_1 (POWERSTEP01_LSPD_OPT_OFF) |
| nucleosam | 0:00a3c3f5a8f0 | 327 | |
| nucleosam | 0:00a3c3f5a8f0 | 328 | /// Register : K_THERM |
| nucleosam | 0:00a3c3f5a8f0 | 329 | /// Thermal compensation param, range 1 to 1.46875 |
| nucleosam | 0:00a3c3f5a8f0 | 330 | #define POWERSTEP01_CONF_PARAM_K_THERM_DEVICE_1 (1) |
| nucleosam | 0:00a3c3f5a8f0 | 331 | |
| nucleosam | 0:00a3c3f5a8f0 | 332 | /// Register : INT_SPEED |
| nucleosam | 0:00a3c3f5a8f0 | 333 | /// Intersect speed settings for BEMF compensation in steps/s, range 0 to 3906 steps/s |
| nucleosam | 0:00a3c3f5a8f0 | 334 | #define POWERSTEP01_CONF_PARAM_INT_SPD_DEVICE_1 (61.512) |
| nucleosam | 0:00a3c3f5a8f0 | 335 | |
| nucleosam | 0:00a3c3f5a8f0 | 336 | /// Register : ST_SLP |
| nucleosam | 0:00a3c3f5a8f0 | 337 | /// BEMF start slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
| nucleosam | 0:00a3c3f5a8f0 | 338 | #define POWERSTEP01_CONF_PARAM_ST_SLP_DEVICE_1 (0.03815) |
| nucleosam | 0:00a3c3f5a8f0 | 339 | |
| nucleosam | 0:00a3c3f5a8f0 | 340 | /// Register : FN_SLP_ACC |
| nucleosam | 0:00a3c3f5a8f0 | 341 | /// BEMF final acc slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
| nucleosam | 0:00a3c3f5a8f0 | 342 | #define POWERSTEP01_CONF_PARAM_FN_SLP_ACC_DEVICE_1 (0.06256) |
| nucleosam | 0:00a3c3f5a8f0 | 343 | |
| nucleosam | 0:00a3c3f5a8f0 | 344 | /// Register : FN_SLP_DEC |
| nucleosam | 0:00a3c3f5a8f0 | 345 | /// BEMF final dec slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
| nucleosam | 0:00a3c3f5a8f0 | 346 | #define POWERSTEP01_CONF_PARAM_FN_SLP_DEC_DEVICE_1 (0.06256) |
| nucleosam | 0:00a3c3f5a8f0 | 347 | |
| nucleosam | 0:00a3c3f5a8f0 | 348 | /// Register : CONFIG - field : F_PWM_INT |
| nucleosam | 0:00a3c3f5a8f0 | 349 | /// PWM Frequency Integer division, enum powerstep01_ConfigFPwmInt_t |
| nucleosam | 0:00a3c3f5a8f0 | 350 | #define POWERSTEP01_CONF_PARAM_PWM_DIV_DEVICE_1 (POWERSTEP01_CONFIG_PWM_DIV_2) |
| nucleosam | 0:00a3c3f5a8f0 | 351 | |
| nucleosam | 0:00a3c3f5a8f0 | 352 | /// Register : CONFIG - field : F_PWM_DEC |
| nucleosam | 0:00a3c3f5a8f0 | 353 | /// PWM Frequency Integer Multiplier, enum powerstep01_ConfigFPwmDec_t |
| nucleosam | 0:00a3c3f5a8f0 | 354 | #define POWERSTEP01_CONF_PARAM_PWM_MUL_DEVICE_1 (POWERSTEP01_CONFIG_PWM_MUL_1) |
| nucleosam | 0:00a3c3f5a8f0 | 355 | |
| nucleosam | 0:00a3c3f5a8f0 | 356 | /******************** Advance current control parameters *********************/ |
| nucleosam | 0:00a3c3f5a8f0 | 357 | |
| nucleosam | 0:00a3c3f5a8f0 | 358 | /// Register : TVAL_ACC |
| nucleosam | 0:00a3c3f5a8f0 | 359 | /// Acceleration torque in mV, range from 7.8mV to 1000 mV |
| nucleosam | 0:00a3c3f5a8f0 | 360 | #define POWERSTEP01_CONF_PARAM_TVAL_ACC_DEVICE_1 (328.12) |
| nucleosam | 0:00a3c3f5a8f0 | 361 | |
| nucleosam | 0:00a3c3f5a8f0 | 362 | /// Register : TVAL_DEC |
| nucleosam | 0:00a3c3f5a8f0 | 363 | /// Deceleration torque in mV, range from 7.8mV to 1000 mV |
| nucleosam | 0:00a3c3f5a8f0 | 364 | #define POWERSTEP01_CONF_PARAM_TVAL_DEC_DEVICE_1 (328.12) |
| nucleosam | 0:00a3c3f5a8f0 | 365 | |
| nucleosam | 0:00a3c3f5a8f0 | 366 | /// Register : TVAL_RUN |
| nucleosam | 0:00a3c3f5a8f0 | 367 | /// Running torque in mV, range from 7.8mV to 1000 mV |
| nucleosam | 0:00a3c3f5a8f0 | 368 | #define POWERSTEP01_CONF_PARAM_TVAL_RUN_DEVICE_1 (328.12) |
| nucleosam | 0:00a3c3f5a8f0 | 369 | |
| nucleosam | 0:00a3c3f5a8f0 | 370 | /// Register : TVAL_HOLD |
| nucleosam | 0:00a3c3f5a8f0 | 371 | /// Holding torque in mV, range from 7.8mV to 1000 mV |
| nucleosam | 0:00a3c3f5a8f0 | 372 | #define POWERSTEP01_CONF_PARAM_TVAL_HOLD_DEVICE_1 (328.12) |
| nucleosam | 0:00a3c3f5a8f0 | 373 | |
| nucleosam | 0:00a3c3f5a8f0 | 374 | /// Register : CONFIG - field : EN_TQREG |
| nucleosam | 0:00a3c3f5a8f0 | 375 | /// External torque regulation enabling , enum powerstep01_ConfigEnTqReg_t |
| nucleosam | 0:00a3c3f5a8f0 | 376 | #define POWERSTEP01_CONF_PARAM_TQ_REG_DEVICE_1 (POWERSTEP01_CONFIG_TQ_REG_TVAL_USED) |
| nucleosam | 0:00a3c3f5a8f0 | 377 | |
| nucleosam | 0:00a3c3f5a8f0 | 378 | /// Register : CONFIG - field : PRED_EN |
| nucleosam | 0:00a3c3f5a8f0 | 379 | /// Predictive current enabling , enum powerstep01_ConfigPredEn_t |
| nucleosam | 0:00a3c3f5a8f0 | 380 | #define POWERSTEP01_CONF_PARAM_PRED_DEVICE_1 (POWERSTEP01_CONFIG_PRED_DISABLE) |
| nucleosam | 0:00a3c3f5a8f0 | 381 | |
| nucleosam | 0:00a3c3f5a8f0 | 382 | /// Register : TON_MIN |
| nucleosam | 0:00a3c3f5a8f0 | 383 | /// Minimum on-time in us, range 0.5us to 64us |
| nucleosam | 0:00a3c3f5a8f0 | 384 | #define POWERSTEP01_CONF_PARAM_TON_MIN_DEVICE_1 (3.0) |
| nucleosam | 0:00a3c3f5a8f0 | 385 | |
| nucleosam | 0:00a3c3f5a8f0 | 386 | /// Register : TOFF_MIN |
| nucleosam | 0:00a3c3f5a8f0 | 387 | /// Minimum off-time in us, range 0.5us to 64us |
| nucleosam | 0:00a3c3f5a8f0 | 388 | #define POWERSTEP01_CONF_PARAM_TOFF_MIN_DEVICE_1 (21.0) |
| nucleosam | 0:00a3c3f5a8f0 | 389 | |
| nucleosam | 0:00a3c3f5a8f0 | 390 | /// Register : T_FAST - field: TOFF_FAST |
| nucleosam | 0:00a3c3f5a8f0 | 391 | /// Maximum fast decay time , enum powerstep01_ToffFast_t |
| nucleosam | 0:00a3c3f5a8f0 | 392 | #define POWERSTEP01_CONF_PARAM_TOFF_FAST_DEVICE_1 (POWERSTEP01_TOFF_FAST_8us) |
| nucleosam | 0:00a3c3f5a8f0 | 393 | |
| nucleosam | 0:00a3c3f5a8f0 | 394 | /// Register : T_FAST - field: FAST_STEP |
| nucleosam | 0:00a3c3f5a8f0 | 395 | /// Maximum fall step time , enum powerstep01_FastStep_t |
| nucleosam | 0:00a3c3f5a8f0 | 396 | #define POWERSTEP01_CONF_PARAM_FAST_STEP_DEVICE_1 (POWERSTEP01_FAST_STEP_12us) |
| nucleosam | 0:00a3c3f5a8f0 | 397 | |
| nucleosam | 0:00a3c3f5a8f0 | 398 | /// Register : CONFIG - field : TSW |
| nucleosam | 0:00a3c3f5a8f0 | 399 | /// Switching period, enum powerstep01_ConfigTsw_t |
| nucleosam | 0:00a3c3f5a8f0 | 400 | #define POWERSTEP01_CONF_PARAM_TSW_DEVICE_1 (POWERSTEP01_CONFIG_TSW_048us) |
| nucleosam | 0:00a3c3f5a8f0 | 401 | |
| nucleosam | 0:00a3c3f5a8f0 | 402 | /****************************** Gate Driving **********************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 403 | |
| nucleosam | 0:00a3c3f5a8f0 | 404 | /// Register : GATECFG1 - field : IGATE |
| nucleosam | 0:00a3c3f5a8f0 | 405 | /// Gate sink/source current via enum powerstep01_Igate_t |
| nucleosam | 0:00a3c3f5a8f0 | 406 | #define POWERSTEP01_CONF_PARAM_IGATE_DEVICE_1 (POWERSTEP01_IGATE_64mA) |
| nucleosam | 0:00a3c3f5a8f0 | 407 | |
| nucleosam | 0:00a3c3f5a8f0 | 408 | /// Register : CONFIG - field : VCCVAL |
| nucleosam | 0:00a3c3f5a8f0 | 409 | /// VCC Val, enum powerstep01_ConfigVccVal_t |
| nucleosam | 0:00a3c3f5a8f0 | 410 | #define POWERSTEP01_CONF_PARAM_VCCVAL_DEVICE_1 (POWERSTEP01_CONFIG_VCCVAL_15V) |
| nucleosam | 0:00a3c3f5a8f0 | 411 | |
| nucleosam | 0:00a3c3f5a8f0 | 412 | /// Register : CONFIG - field : UVLOVAL |
| nucleosam | 0:00a3c3f5a8f0 | 413 | /// UVLO Threshold via powerstep01_ConfigUvLoVal_t |
| nucleosam | 0:00a3c3f5a8f0 | 414 | #define POWERSTEP01_CONF_PARAM_UVLOVAL_DEVICE_1 (POWERSTEP01_CONFIG_UVLOVAL_LOW) |
| nucleosam | 0:00a3c3f5a8f0 | 415 | |
| nucleosam | 0:00a3c3f5a8f0 | 416 | /// Register : GATECFG1 - field : TBOOST |
| nucleosam | 0:00a3c3f5a8f0 | 417 | /// Duration of the overboost phase during gate turn-off via enum powerstep01_Tboost_t |
| nucleosam | 0:00a3c3f5a8f0 | 418 | #define POWERSTEP01_CONF_PARAM_TBOOST_DEVICE_1 (POWERSTEP01_TBOOST_0ns) |
| nucleosam | 0:00a3c3f5a8f0 | 419 | |
| nucleosam | 0:00a3c3f5a8f0 | 420 | /// Register : GATECFG1 - field : TCC |
| nucleosam | 0:00a3c3f5a8f0 | 421 | /// Controlled current time via enum powerstep01_Tcc_t |
| nucleosam | 0:00a3c3f5a8f0 | 422 | #define POWERSTEP01_CONF_PARAM_TCC_DEVICE_1 (POWERSTEP01_TCC_500ns) |
| nucleosam | 0:00a3c3f5a8f0 | 423 | |
| nucleosam | 0:00a3c3f5a8f0 | 424 | /// Duration of the blanking time via enum powerstep01_TBlank_t |
| nucleosam | 0:00a3c3f5a8f0 | 425 | #define POWERSTEP01_CONF_PARAM_TBLANK_DEVICE_1 (POWERSTEP01_TBLANK_375ns) |
| nucleosam | 0:00a3c3f5a8f0 | 426 | |
| nucleosam | 0:00a3c3f5a8f0 | 427 | /// Register : GATECFG2 - field : TDT |
| nucleosam | 0:00a3c3f5a8f0 | 428 | /// Duration of the dead time via enum powerstep01_Tdt_t |
| nucleosam | 0:00a3c3f5a8f0 | 429 | #define POWERSTEP01_CONF_PARAM_TDT_DEVICE_1 (POWERSTEP01_TDT_125ns) |
| nucleosam | 0:00a3c3f5a8f0 | 430 | |
| nucleosam | 0:00a3c3f5a8f0 | 431 | /******************************* Others *************************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 432 | |
| nucleosam | 0:00a3c3f5a8f0 | 433 | /// Register : OCD_TH |
| nucleosam | 0:00a3c3f5a8f0 | 434 | /// Overcurrent threshold settings via enum powerstep01_OcdTh_t |
| nucleosam | 0:00a3c3f5a8f0 | 435 | #define POWERSTEP01_CONF_PARAM_OCD_TH_DEVICE_1 (POWERSTEP01_OCD_TH_281_25mV) |
| nucleosam | 0:00a3c3f5a8f0 | 436 | |
| nucleosam | 0:00a3c3f5a8f0 | 437 | /// Register : CONFIG - field : OC_SD |
| nucleosam | 0:00a3c3f5a8f0 | 438 | /// Over current shutwdown enabling, enum powerstep01_ConfigOcSd_t |
| nucleosam | 0:00a3c3f5a8f0 | 439 | #define POWERSTEP01_CONF_PARAM_OC_SD_DEVICE_1 (POWERSTEP01_CONFIG_OC_SD_DISABLE) |
| nucleosam | 0:00a3c3f5a8f0 | 440 | |
| nucleosam | 0:00a3c3f5a8f0 | 441 | /// Register : STALL_TH |
| nucleosam | 0:00a3c3f5a8f0 | 442 | /// Stall threshold settings in mV, range 31.25mV to 1000mV |
| nucleosam | 0:00a3c3f5a8f0 | 443 | #define POWERSTEP01_CONF_PARAM_STALL_TH_DEVICE_1 (531.25) |
| nucleosam | 0:00a3c3f5a8f0 | 444 | |
| nucleosam | 0:00a3c3f5a8f0 | 445 | /// Register : ALARM_EN |
| nucleosam | 0:00a3c3f5a8f0 | 446 | /// Alarm settings via bitmap enum powerstep01_AlarmEn_t |
| nucleosam | 0:00a3c3f5a8f0 | 447 | #define POWERSTEP01_CONF_PARAM_ALARM_EN_DEVICE_1 (POWERSTEP01_ALARM_EN_OVERCURRENT | \ |
| nucleosam | 0:00a3c3f5a8f0 | 448 | POWERSTEP01_ALARM_EN_THERMAL_SHUTDOWN | \ |
| nucleosam | 0:00a3c3f5a8f0 | 449 | POWERSTEP01_ALARM_EN_THERMAL_WARNING | \ |
| nucleosam | 0:00a3c3f5a8f0 | 450 | POWERSTEP01_ALARM_EN_UVLO | \ |
| nucleosam | 0:00a3c3f5a8f0 | 451 | POWERSTEP01_ALARM_EN_STALL_DETECTION | \ |
| nucleosam | 0:00a3c3f5a8f0 | 452 | POWERSTEP01_ALARM_EN_SW_TURN_ON | \ |
| nucleosam | 0:00a3c3f5a8f0 | 453 | POWERSTEP01_ALARM_EN_WRONG_NPERF_CMD) |
| nucleosam | 0:00a3c3f5a8f0 | 454 | |
| nucleosam | 0:00a3c3f5a8f0 | 455 | /// Register : CONFIG - field : SW_MODE |
| nucleosam | 0:00a3c3f5a8f0 | 456 | /// External switch hard stop interrupt mode, enum powerstep01_ConfigSwMode_t |
| nucleosam | 0:00a3c3f5a8f0 | 457 | #define POWERSTEP01_CONF_PARAM_SW_MODE_DEVICE_1 (POWERSTEP01_CONFIG_SW_HARD_STOP) |
| nucleosam | 0:00a3c3f5a8f0 | 458 | |
| nucleosam | 0:00a3c3f5a8f0 | 459 | /// Register : STEP_MODE - field : STEP_MODE |
| nucleosam | 0:00a3c3f5a8f0 | 460 | /// Step mode settings via enum powerstep01_StepSel_t |
| nucleosam | 0:00a3c3f5a8f0 | 461 | #define POWERSTEP01_CONF_PARAM_STEP_MODE_DEVICE_1 (STEP_MODE_1_16) |
| nucleosam | 0:00a3c3f5a8f0 | 462 | |
| nucleosam | 0:00a3c3f5a8f0 | 463 | /// Register : STEP_MODE - field : CM_VM |
| nucleosam | 0:00a3c3f5a8f0 | 464 | /// Current mode or Voltage mode via enum powerstep01_CmVm_t |
| nucleosam | 0:00a3c3f5a8f0 | 465 | #define POWERSTEP01_CONF_PARAM_CM_VM_DEVICE_1 (POWERSTEP01_CM_VM_CURRENT) |
| nucleosam | 0:00a3c3f5a8f0 | 466 | |
| nucleosam | 0:00a3c3f5a8f0 | 467 | /// Register : STEP_MODE - Field : SYNC_MODE and SYNC_EN |
| nucleosam | 0:00a3c3f5a8f0 | 468 | /// Synch. Mode settings via enum powerstep01_SyncSel_t |
| nucleosam | 0:00a3c3f5a8f0 | 469 | #define POWERSTEP01_CONF_PARAM_SYNC_MODE_DEVICE_1 (POWERSTEP01_SYNC_SEL_DISABLED) |
| nucleosam | 0:00a3c3f5a8f0 | 470 | |
| nucleosam | 0:00a3c3f5a8f0 | 471 | /// Register : CONFIG - field : OSC_CLK_SEL |
| nucleosam | 0:00a3c3f5a8f0 | 472 | /// Clock setting , enum powerstep01_ConfigOscMgmt_t |
| nucleosam | 0:00a3c3f5a8f0 | 473 | #define POWERSTEP01_CONF_PARAM_CLOCK_SETTING_DEVICE_1 (POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_2MHZ) |
| nucleosam | 0:00a3c3f5a8f0 | 474 | |
| nucleosam | 0:00a3c3f5a8f0 | 475 | /// Register : GATECFG1 - field : WD_EN |
| nucleosam | 0:00a3c3f5a8f0 | 476 | /// External clock watchdog, enum powerstep01_WdEn_t |
| nucleosam | 0:00a3c3f5a8f0 | 477 | #define POWERSTEP01_CONF_PARAM_WD_EN_DEVICE_1 (POWERSTEP01_WD_EN_DISABLE) |
| nucleosam | 0:00a3c3f5a8f0 | 478 | |
| nucleosam | 0:00a3c3f5a8f0 | 479 | /****************************************************************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 480 | /* Device 2 */ |
| nucleosam | 0:00a3c3f5a8f0 | 481 | /****************************************************************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 482 | |
| nucleosam | 0:00a3c3f5a8f0 | 483 | /**************************** Speed Profile *********************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 484 | /// Register : ACC |
| nucleosam | 0:00a3c3f5a8f0 | 485 | /// Acceleration rate in step/s2, range 14.55 to 59590 steps/s^2 |
| nucleosam | 0:00a3c3f5a8f0 | 486 | #define POWERSTEP01_CONF_PARAM_ACC_DEVICE_2 (2008.16) |
| nucleosam | 0:00a3c3f5a8f0 | 487 | |
| nucleosam | 0:00a3c3f5a8f0 | 488 | /// Register : DEC |
| nucleosam | 0:00a3c3f5a8f0 | 489 | /// Deceleration rate in step/s2, range 14.55 to 59590 steps/s^2 |
| nucleosam | 0:00a3c3f5a8f0 | 490 | #define POWERSTEP01_CONF_PARAM_DEC_DEVICE_2 (2008.16) |
| nucleosam | 0:00a3c3f5a8f0 | 491 | |
| nucleosam | 0:00a3c3f5a8f0 | 492 | ///Register : MAX_SPEED |
| nucleosam | 0:00a3c3f5a8f0 | 493 | /// Maximum speed in step/s, range 15.25 to 15610 steps/s |
| nucleosam | 0:00a3c3f5a8f0 | 494 | #define POWERSTEP01_CONF_PARAM_MAX_SPEED_DEVICE_2 (991.82) |
| nucleosam | 0:00a3c3f5a8f0 | 495 | |
| nucleosam | 0:00a3c3f5a8f0 | 496 | /// Register : MIN_SPEED |
| nucleosam | 0:00a3c3f5a8f0 | 497 | /// Minimum speed in step/s, range 0 to 976.3 steps/s |
| nucleosam | 0:00a3c3f5a8f0 | 498 | #define POWERSTEP01_CONF_PARAM_MIN_SPEED_DEVICE_2 (0) |
| nucleosam | 0:00a3c3f5a8f0 | 499 | |
| nucleosam | 0:00a3c3f5a8f0 | 500 | /// Register : FS_SPD |
| nucleosam | 0:00a3c3f5a8f0 | 501 | /// Full step speed in step/s, range 7.63 to 15625 steps/s |
| nucleosam | 0:00a3c3f5a8f0 | 502 | #define POWERSTEP01_CONF_PARAM_FS_SPD_DEVICE_2 (595.09) |
| nucleosam | 0:00a3c3f5a8f0 | 503 | |
| nucleosam | 0:00a3c3f5a8f0 | 504 | /// Register : FS_SPD - field : BOOST_MODE |
| nucleosam | 0:00a3c3f5a8f0 | 505 | /// Boost of the amplitude square wave, enum powerstep01_BoostMode_t |
| nucleosam | 0:00a3c3f5a8f0 | 506 | #define POWERSTEP01_CONF_PARAM_BOOST_MODE_DEVICE_2 (POWERSTEP01_BOOST_MODE_OFF) |
| nucleosam | 0:00a3c3f5a8f0 | 507 | |
| nucleosam | 0:00a3c3f5a8f0 | 508 | |
| nucleosam | 0:00a3c3f5a8f0 | 509 | /************************ Voltage mode parameters **************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 510 | /// Register : KVAL_ACC |
| nucleosam | 0:00a3c3f5a8f0 | 511 | /// Acceleration duty cycle (torque) in %, range 0 to 99.6% |
| nucleosam | 0:00a3c3f5a8f0 | 512 | #define POWERSTEP01_CONF_PARAM_KVAL_ACC_DEVICE_2 (16.02) |
| nucleosam | 0:00a3c3f5a8f0 | 513 | |
| nucleosam | 0:00a3c3f5a8f0 | 514 | /// Register : KVAL_DEC |
| nucleosam | 0:00a3c3f5a8f0 | 515 | /// Deceleration duty cycle (torque) in %, range 0 to 99.6% |
| nucleosam | 0:00a3c3f5a8f0 | 516 | #define POWERSTEP01_CONF_PARAM_KVAL_DEC_DEVICE_2 (16.02) |
| nucleosam | 0:00a3c3f5a8f0 | 517 | |
| nucleosam | 0:00a3c3f5a8f0 | 518 | /// Register : KVAL_RUN |
| nucleosam | 0:00a3c3f5a8f0 | 519 | /// Run duty cycle (torque) in %, range 0 to 99.6% |
| nucleosam | 0:00a3c3f5a8f0 | 520 | #define POWERSTEP01_CONF_PARAM_KVAL_RUN_DEVICE_2 (16.02) |
| nucleosam | 0:00a3c3f5a8f0 | 521 | |
| nucleosam | 0:00a3c3f5a8f0 | 522 | /// Register : KVAL_HOLD |
| nucleosam | 0:00a3c3f5a8f0 | 523 | /// Hold duty cycle (torque) in %, range 0 to 99.6% |
| nucleosam | 0:00a3c3f5a8f0 | 524 | #define POWERSTEP01_CONF_PARAM_KVAL_HOLD_DEVICE_2 (16.02) |
| nucleosam | 0:00a3c3f5a8f0 | 525 | |
| nucleosam | 0:00a3c3f5a8f0 | 526 | /// Register : CONFIG - field : EN_VSCOMP |
| nucleosam | 0:00a3c3f5a8f0 | 527 | /// Motor Supply Voltage Compensation enabling , enum powerstep01_ConfigEnVscomp_t |
| nucleosam | 0:00a3c3f5a8f0 | 528 | #define POWERSTEP01_CONF_PARAM_VS_COMP_DEVICE_2 (POWERSTEP01_CONFIG_VS_COMP_DISABLE) |
| nucleosam | 0:00a3c3f5a8f0 | 529 | |
| nucleosam | 0:00a3c3f5a8f0 | 530 | /// Register : MIN_SPEED - field : LSPD_OPT |
| nucleosam | 0:00a3c3f5a8f0 | 531 | /// Low speed optimization bit, enum powerstep01_LspdOpt_t |
| nucleosam | 0:00a3c3f5a8f0 | 532 | #define POWERSTEP01_CONF_PARAM_LSPD_BIT_DEVICE_2 (POWERSTEP01_LSPD_OPT_OFF) |
| nucleosam | 0:00a3c3f5a8f0 | 533 | |
| nucleosam | 0:00a3c3f5a8f0 | 534 | /// Register : K_THERM |
| nucleosam | 0:00a3c3f5a8f0 | 535 | /// Thermal compensation param, range 1 to 1.46875 |
| nucleosam | 0:00a3c3f5a8f0 | 536 | #define POWERSTEP01_CONF_PARAM_K_THERM_DEVICE_2 (1) |
| nucleosam | 0:00a3c3f5a8f0 | 537 | |
| nucleosam | 0:00a3c3f5a8f0 | 538 | /// Register : INT_SPEED |
| nucleosam | 0:00a3c3f5a8f0 | 539 | /// Intersect speed settings for BEMF compensation in steps/s, range 0 to 3906 steps/s |
| nucleosam | 0:00a3c3f5a8f0 | 540 | #define POWERSTEP01_CONF_PARAM_INT_SPD_DEVICE_2 (61.512) |
| nucleosam | 0:00a3c3f5a8f0 | 541 | |
| nucleosam | 0:00a3c3f5a8f0 | 542 | /// Register : ST_SLP |
| nucleosam | 0:00a3c3f5a8f0 | 543 | /// BEMF start slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
| nucleosam | 0:00a3c3f5a8f0 | 544 | #define POWERSTEP01_CONF_PARAM_ST_SLP_DEVICE_2 (0.03815) |
| nucleosam | 0:00a3c3f5a8f0 | 545 | |
| nucleosam | 0:00a3c3f5a8f0 | 546 | /// Register : FN_SLP_ACC |
| nucleosam | 0:00a3c3f5a8f0 | 547 | /// BEMF final acc slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
| nucleosam | 0:00a3c3f5a8f0 | 548 | #define POWERSTEP01_CONF_PARAM_FN_SLP_ACC_DEVICE_2 (0.06256) |
| nucleosam | 0:00a3c3f5a8f0 | 549 | |
| nucleosam | 0:00a3c3f5a8f0 | 550 | /// Register : FN_SLP_DEC |
| nucleosam | 0:00a3c3f5a8f0 | 551 | /// BEMF final dec slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
| nucleosam | 0:00a3c3f5a8f0 | 552 | #define POWERSTEP01_CONF_PARAM_FN_SLP_DEC_DEVICE_2 (0.06256) |
| nucleosam | 0:00a3c3f5a8f0 | 553 | |
| nucleosam | 0:00a3c3f5a8f0 | 554 | /// Register : CONFIG - field : F_PWM_INT |
| nucleosam | 0:00a3c3f5a8f0 | 555 | /// PWM Frequency Integer division, enum powerstep01_ConfigFPwmInt_t |
| nucleosam | 0:00a3c3f5a8f0 | 556 | #define POWERSTEP01_CONF_PARAM_PWM_DIV_DEVICE_2 (POWERSTEP01_CONFIG_PWM_DIV_2) |
| nucleosam | 0:00a3c3f5a8f0 | 557 | |
| nucleosam | 0:00a3c3f5a8f0 | 558 | /// Register : CONFIG - field : F_PWM_DEC |
| nucleosam | 0:00a3c3f5a8f0 | 559 | /// PWM Frequency Integer Multiplier, enum powerstep01_ConfigFPwmDec_t |
| nucleosam | 0:00a3c3f5a8f0 | 560 | #define POWERSTEP01_CONF_PARAM_PWM_MUL_DEVICE_2 (POWERSTEP01_CONFIG_PWM_MUL_1) |
| nucleosam | 0:00a3c3f5a8f0 | 561 | |
| nucleosam | 0:00a3c3f5a8f0 | 562 | /******************** Advance current control parameters *********************/ |
| nucleosam | 0:00a3c3f5a8f0 | 563 | |
| nucleosam | 0:00a3c3f5a8f0 | 564 | /// Register : TVAL_ACC |
| nucleosam | 0:00a3c3f5a8f0 | 565 | /// Acceleration torque in mV, range from 7.8mV to 1000 mV |
| nucleosam | 0:00a3c3f5a8f0 | 566 | #define POWERSTEP01_CONF_PARAM_TVAL_ACC_DEVICE_2 (328.12) |
| nucleosam | 0:00a3c3f5a8f0 | 567 | |
| nucleosam | 0:00a3c3f5a8f0 | 568 | /// Register : TVAL_DEC |
| nucleosam | 0:00a3c3f5a8f0 | 569 | /// Deceleration torque in mV, range from 7.8mV to 1000 mV |
| nucleosam | 0:00a3c3f5a8f0 | 570 | #define POWERSTEP01_CONF_PARAM_TVAL_DEC_DEVICE_2 (328.12) |
| nucleosam | 0:00a3c3f5a8f0 | 571 | |
| nucleosam | 0:00a3c3f5a8f0 | 572 | /// Register : TVAL_RUN |
| nucleosam | 0:00a3c3f5a8f0 | 573 | /// Running torque in mV, range from 7.8mV to 1000 mV |
| nucleosam | 0:00a3c3f5a8f0 | 574 | #define POWERSTEP01_CONF_PARAM_TVAL_RUN_DEVICE_2 (328.12) |
| nucleosam | 0:00a3c3f5a8f0 | 575 | |
| nucleosam | 0:00a3c3f5a8f0 | 576 | /// Register : TVAL_HOLD |
| nucleosam | 0:00a3c3f5a8f0 | 577 | /// Holding torque in mV, range from 7.8mV to 1000 mV |
| nucleosam | 0:00a3c3f5a8f0 | 578 | #define POWERSTEP01_CONF_PARAM_TVAL_HOLD_DEVICE_2 (328.12) |
| nucleosam | 0:00a3c3f5a8f0 | 579 | |
| nucleosam | 0:00a3c3f5a8f0 | 580 | /// Register : CONFIG - field : EN_TQREG |
| nucleosam | 0:00a3c3f5a8f0 | 581 | /// External torque regulation enabling , enum powerstep01_ConfigEnTqReg_t |
| nucleosam | 0:00a3c3f5a8f0 | 582 | #define POWERSTEP01_CONF_PARAM_TQ_REG_DEVICE_2 (POWERSTEP01_CONFIG_TQ_REG_TVAL_USED) |
| nucleosam | 0:00a3c3f5a8f0 | 583 | |
| nucleosam | 0:00a3c3f5a8f0 | 584 | /// Register : CONFIG - field : PRED_EN |
| nucleosam | 0:00a3c3f5a8f0 | 585 | /// Predictive current enabling , enum powerstep01_ConfigPredEn_t |
| nucleosam | 0:00a3c3f5a8f0 | 586 | #define POWERSTEP01_CONF_PARAM_PRED_DEVICE_2 (POWERSTEP01_CONFIG_PRED_DISABLE) |
| nucleosam | 0:00a3c3f5a8f0 | 587 | |
| nucleosam | 0:00a3c3f5a8f0 | 588 | /// Register : TON_MIN |
| nucleosam | 0:00a3c3f5a8f0 | 589 | /// Minimum on-time in us, range 0.5us to 64us |
| nucleosam | 0:00a3c3f5a8f0 | 590 | #define POWERSTEP01_CONF_PARAM_TON_MIN_DEVICE_2 (3.0) |
| nucleosam | 0:00a3c3f5a8f0 | 591 | |
| nucleosam | 0:00a3c3f5a8f0 | 592 | /// Register : TOFF_MIN |
| nucleosam | 0:00a3c3f5a8f0 | 593 | /// Minimum off-time in us, range 0.5us to 64us |
| nucleosam | 0:00a3c3f5a8f0 | 594 | #define POWERSTEP01_CONF_PARAM_TOFF_MIN_DEVICE_2 (21.0) |
| nucleosam | 0:00a3c3f5a8f0 | 595 | |
| nucleosam | 0:00a3c3f5a8f0 | 596 | /// Register : T_FAST - field: TOFF_FAST |
| nucleosam | 0:00a3c3f5a8f0 | 597 | /// Maximum fast decay time , enum powerstep01_ToffFast_t |
| nucleosam | 0:00a3c3f5a8f0 | 598 | #define POWERSTEP01_CONF_PARAM_TOFF_FAST_DEVICE_2 (POWERSTEP01_TOFF_FAST_8us) |
| nucleosam | 0:00a3c3f5a8f0 | 599 | |
| nucleosam | 0:00a3c3f5a8f0 | 600 | /// Register : T_FAST - field: FAST_STEP |
| nucleosam | 0:00a3c3f5a8f0 | 601 | /// Maximum fall step time , enum powerstep01_FastStep_t |
| nucleosam | 0:00a3c3f5a8f0 | 602 | #define POWERSTEP01_CONF_PARAM_FAST_STEP_DEVICE_2 (POWERSTEP01_FAST_STEP_12us) |
| nucleosam | 0:00a3c3f5a8f0 | 603 | |
| nucleosam | 0:00a3c3f5a8f0 | 604 | /// Register : CONFIG - field : TSW |
| nucleosam | 0:00a3c3f5a8f0 | 605 | /// Switching period, enum powerstep01_ConfigTsw_t |
| nucleosam | 0:00a3c3f5a8f0 | 606 | #define POWERSTEP01_CONF_PARAM_TSW_DEVICE_2 (POWERSTEP01_CONFIG_TSW_048us) |
| nucleosam | 0:00a3c3f5a8f0 | 607 | |
| nucleosam | 0:00a3c3f5a8f0 | 608 | /****************************** Gate Driving **********************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 609 | |
| nucleosam | 0:00a3c3f5a8f0 | 610 | /// Register : GATECFG1 - field : IGATE |
| nucleosam | 0:00a3c3f5a8f0 | 611 | /// Gate sink/source current via enum powerstep01_Igate_t |
| nucleosam | 0:00a3c3f5a8f0 | 612 | #define POWERSTEP01_CONF_PARAM_IGATE_DEVICE_2 (POWERSTEP01_IGATE_64mA) |
| nucleosam | 0:00a3c3f5a8f0 | 613 | |
| nucleosam | 0:00a3c3f5a8f0 | 614 | /// Register : CONFIG - field : VCCVAL |
| nucleosam | 0:00a3c3f5a8f0 | 615 | /// VCC Val, enum powerstep01_ConfigVccVal_t |
| nucleosam | 0:00a3c3f5a8f0 | 616 | #define POWERSTEP01_CONF_PARAM_VCCVAL_DEVICE_2 (POWERSTEP01_CONFIG_VCCVAL_15V) |
| nucleosam | 0:00a3c3f5a8f0 | 617 | |
| nucleosam | 0:00a3c3f5a8f0 | 618 | /// Register : CONFIG - field : UVLOVAL |
| nucleosam | 0:00a3c3f5a8f0 | 619 | /// UVLO Threshold via powerstep01_ConfigUvLoVal_t |
| nucleosam | 0:00a3c3f5a8f0 | 620 | #define POWERSTEP01_CONF_PARAM_UVLOVAL_DEVICE_2 (POWERSTEP01_CONFIG_UVLOVAL_LOW) |
| nucleosam | 0:00a3c3f5a8f0 | 621 | |
| nucleosam | 0:00a3c3f5a8f0 | 622 | /// Register : GATECFG1 - field : TBOOST |
| nucleosam | 0:00a3c3f5a8f0 | 623 | /// Duration of the overboost phase during gate turn-off via enum powerstep01_Tboost_t |
| nucleosam | 0:00a3c3f5a8f0 | 624 | #define POWERSTEP01_CONF_PARAM_TBOOST_DEVICE_2 (POWERSTEP01_TBOOST_0ns) |
| nucleosam | 0:00a3c3f5a8f0 | 625 | |
| nucleosam | 0:00a3c3f5a8f0 | 626 | /// Register : GATECFG1 - field : TCC |
| nucleosam | 0:00a3c3f5a8f0 | 627 | /// Controlled current time via enum powerstep01_Tcc_t |
| nucleosam | 0:00a3c3f5a8f0 | 628 | #define POWERSTEP01_CONF_PARAM_TCC_DEVICE_2 (POWERSTEP01_TCC_500ns) |
| nucleosam | 0:00a3c3f5a8f0 | 629 | |
| nucleosam | 0:00a3c3f5a8f0 | 630 | /// Duration of the blanking time via enum powerstep01_TBlank_t |
| nucleosam | 0:00a3c3f5a8f0 | 631 | #define POWERSTEP01_CONF_PARAM_TBLANK_DEVICE_2 (POWERSTEP01_TBLANK_375ns) |
| nucleosam | 0:00a3c3f5a8f0 | 632 | |
| nucleosam | 0:00a3c3f5a8f0 | 633 | /// Register : GATECFG2 - field : TDT |
| nucleosam | 0:00a3c3f5a8f0 | 634 | /// Duration of the dead time via enum powerstep01_Tdt_t |
| nucleosam | 0:00a3c3f5a8f0 | 635 | #define POWERSTEP01_CONF_PARAM_TDT_DEVICE_2 (POWERSTEP01_TDT_125ns) |
| nucleosam | 0:00a3c3f5a8f0 | 636 | |
| nucleosam | 0:00a3c3f5a8f0 | 637 | /******************************* Others *************************************/ |
| nucleosam | 0:00a3c3f5a8f0 | 638 | |
| nucleosam | 0:00a3c3f5a8f0 | 639 | /// Register : OCD_TH |
| nucleosam | 0:00a3c3f5a8f0 | 640 | /// Overcurrent threshold settings via enum powerstep01_OcdTh_t |
| nucleosam | 0:00a3c3f5a8f0 | 641 | #define POWERSTEP01_CONF_PARAM_OCD_TH_DEVICE_2 (POWERSTEP01_OCD_TH_281_25mV) |
| nucleosam | 0:00a3c3f5a8f0 | 642 | |
| nucleosam | 0:00a3c3f5a8f0 | 643 | /// Register : CONFIG - field : OC_SD |
| nucleosam | 0:00a3c3f5a8f0 | 644 | /// Over current shutwdown enabling, enum powerstep01_ConfigOcSd_t |
| nucleosam | 0:00a3c3f5a8f0 | 645 | #define POWERSTEP01_CONF_PARAM_OC_SD_DEVICE_2 (POWERSTEP01_CONFIG_OC_SD_DISABLE) |
| nucleosam | 0:00a3c3f5a8f0 | 646 | |
| nucleosam | 0:00a3c3f5a8f0 | 647 | /// Register : STALL_TH |
| nucleosam | 0:00a3c3f5a8f0 | 648 | /// Stall threshold settings in mV, range 31.25mV to 1000mV |
| nucleosam | 0:00a3c3f5a8f0 | 649 | #define POWERSTEP01_CONF_PARAM_STALL_TH_DEVICE_2 (531.25) |
| nucleosam | 0:00a3c3f5a8f0 | 650 | |
| nucleosam | 0:00a3c3f5a8f0 | 651 | /// Register : ALARM_EN |
| nucleosam | 0:00a3c3f5a8f0 | 652 | /// Alarm settings via bitmap enum powerstep01_AlarmEn_t |
| nucleosam | 0:00a3c3f5a8f0 | 653 | #define POWERSTEP01_CONF_PARAM_ALARM_EN_DEVICE_2 (POWERSTEP01_ALARM_EN_OVERCURRENT | \ |
| nucleosam | 0:00a3c3f5a8f0 | 654 | POWERSTEP01_ALARM_EN_THERMAL_SHUTDOWN | \ |
| nucleosam | 0:00a3c3f5a8f0 | 655 | POWERSTEP01_ALARM_EN_THERMAL_WARNING | \ |
| nucleosam | 0:00a3c3f5a8f0 | 656 | POWERSTEP01_ALARM_EN_UVLO | \ |
| nucleosam | 0:00a3c3f5a8f0 | 657 | POWERSTEP01_ALARM_EN_STALL_DETECTION | \ |
| nucleosam | 0:00a3c3f5a8f0 | 658 | POWERSTEP01_ALARM_EN_SW_TURN_ON | \ |
| nucleosam | 0:00a3c3f5a8f0 | 659 | POWERSTEP01_ALARM_EN_WRONG_NPERF_CMD) |
| nucleosam | 0:00a3c3f5a8f0 | 660 | |
| nucleosam | 0:00a3c3f5a8f0 | 661 | /// Register : CONFIG - field : SW_MODE |
| nucleosam | 0:00a3c3f5a8f0 | 662 | /// External switch hard stop interrupt mode, enum powerstep01_ConfigSwMode_t |
| nucleosam | 0:00a3c3f5a8f0 | 663 | #define POWERSTEP01_CONF_PARAM_SW_MODE_DEVICE_2 (POWERSTEP01_CONFIG_SW_HARD_STOP) |
| nucleosam | 0:00a3c3f5a8f0 | 664 | |
| nucleosam | 0:00a3c3f5a8f0 | 665 | /// Register : STEP_MODE - field : STEP_MODE |
| nucleosam | 0:00a3c3f5a8f0 | 666 | /// Step mode settings via enum powerstep01_StepSel_t |
| nucleosam | 0:00a3c3f5a8f0 | 667 | #define POWERSTEP01_CONF_PARAM_STEP_MODE_DEVICE_2 (STEP_MODE_1_16) |
| nucleosam | 0:00a3c3f5a8f0 | 668 | |
| nucleosam | 0:00a3c3f5a8f0 | 669 | /// Register : STEP_MODE - field : CM_VM |
| nucleosam | 0:00a3c3f5a8f0 | 670 | /// Current mode or Voltage mode via enum powerstep01_CmVm_t |
| nucleosam | 0:00a3c3f5a8f0 | 671 | #define POWERSTEP01_CONF_PARAM_CM_VM_DEVICE_2 (POWERSTEP01_CM_VM_CURRENT) |
| nucleosam | 0:00a3c3f5a8f0 | 672 | |
| nucleosam | 0:00a3c3f5a8f0 | 673 | /// Register : STEP_MODE - Field : SYNC_MODE and SYNC_EN |
| nucleosam | 0:00a3c3f5a8f0 | 674 | /// Synch. Mode settings via enum powerstep01_SyncSel_t |
| nucleosam | 0:00a3c3f5a8f0 | 675 | #define POWERSTEP01_CONF_PARAM_SYNC_MODE_DEVICE_2 (POWERSTEP01_SYNC_SEL_DISABLED) |
| nucleosam | 0:00a3c3f5a8f0 | 676 | |
| nucleosam | 0:00a3c3f5a8f0 | 677 | /// Register : CONFIG - field : OSC_CLK_SEL |
| nucleosam | 0:00a3c3f5a8f0 | 678 | /// Clock setting , enum powerstep01_ConfigOscMgmt_t |
| nucleosam | 0:00a3c3f5a8f0 | 679 | #define POWERSTEP01_CONF_PARAM_CLOCK_SETTING_DEVICE_2 (POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_2MHZ) |
| nucleosam | 0:00a3c3f5a8f0 | 680 | |
| nucleosam | 0:00a3c3f5a8f0 | 681 | /// Register : GATECFG1 - field : WD_EN |
| nucleosam | 0:00a3c3f5a8f0 | 682 | /// External clock watchdog, enum powerstep01_WdEn_t |
| nucleosam | 0:00a3c3f5a8f0 | 683 | #define POWERSTEP01_CONF_PARAM_WD_EN_DEVICE_2 (POWERSTEP01_WD_EN_DISABLE) |
| nucleosam | 0:00a3c3f5a8f0 | 684 | |
| nucleosam | 0:00a3c3f5a8f0 | 685 | /** |
| nucleosam | 0:00a3c3f5a8f0 | 686 | * @} |
| nucleosam | 0:00a3c3f5a8f0 | 687 | */ |
| nucleosam | 0:00a3c3f5a8f0 | 688 | |
| nucleosam | 0:00a3c3f5a8f0 | 689 | /** |
| nucleosam | 0:00a3c3f5a8f0 | 690 | * @} |
| nucleosam | 0:00a3c3f5a8f0 | 691 | */ |
| nucleosam | 0:00a3c3f5a8f0 | 692 | |
| nucleosam | 0:00a3c3f5a8f0 | 693 | /** |
| nucleosam | 0:00a3c3f5a8f0 | 694 | * @} |
| nucleosam | 0:00a3c3f5a8f0 | 695 | */ |
| nucleosam | 0:00a3c3f5a8f0 | 696 | |
| nucleosam | 0:00a3c3f5a8f0 | 697 | #ifdef __cplusplus |
| nucleosam | 0:00a3c3f5a8f0 | 698 | } |
| nucleosam | 0:00a3c3f5a8f0 | 699 | #endif |
| nucleosam | 0:00a3c3f5a8f0 | 700 | |
| nucleosam | 0:00a3c3f5a8f0 | 701 | #endif /* __POWERSTEP01_TARGET_CONFIG_H */ |
| nucleosam | 0:00a3c3f5a8f0 | 702 | |
| nucleosam | 0:00a3c3f5a8f0 | 703 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
X-NUCLEO-IHM03A1 High Power Stepper Motor Driver