ST / USBDEVICE

USBDevice for STM support

Dependents:   Nucleo_Usb_JoyMouse Nucleo_usbmouse ELEC350_1-referral-2018-usb-hid USBJoystick_HelloWorld2_wip ... more

This library contains all mbed usb device library (mbed-os\features\unsupported\USBDevice).

USBDevice/USBRegs_STM32.h@4:50ec00aa4515, 2017-03-28 (annotated)

Committer:
frq08711@LMECWL0871.LME.ST.COM
Date:
Tue Mar 28 11:00:57 2017 +0200
Branch:
master
Revision:
4:50ec00aa4515
Parent:
1:2a3ae13b45ef 
update for 5.4.2

Who changed what in which revision?

UserRevisionLine numberNew contents of line
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 1 /**
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 2 ******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 3 * @file usb_regs.h
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 4 * @author MCD Application Team
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 5 * @version V2.1.0
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 6 * @date 19-March-2012
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 7 * @brief hardware registers
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 8 ******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 9 * @attention
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 10 *
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 11 * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 12 *
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 14 * You may not use this file except in compliance with the License.
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 15 * You may obtain a copy of the License at:
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 16 *
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 17 * http://www.st.com/software_license_agreement_liberty_v2
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 18 *
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 19 * Unless required by applicable law or agreed to in writing, software
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 20 * distributed under the License is distributed on an "AS IS" BASIS,
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 22 * See the License for the specific language governing permissions and
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 23 * limitations under the License.
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 24 *
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 25 ******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 26 */
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 27
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 28 #ifndef __USB_OTG_REGS_H__
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 29 #define __USB_OTG_REGS_H__
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 30
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 31 typedef struct //000h
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 32 {
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 33 __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 34 __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 35 __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 36 __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 37 __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 38 __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 39 __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 40 __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 41 __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 42 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 43 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 44 __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 45 uint32_t Reserved30[2]; /* Reserved 030h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 46 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 47 __IO uint32_t CID; /* User ID Register 03Ch*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 48 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 49 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 50 __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 51 }
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 52 USB_OTG_GREGS;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 53
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 54 typedef struct // 800h
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 55 {
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 56 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 57 __IO uint32_t DCTL; /* dev Control Register 804h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 58 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 59 uint32_t Reserved0C; /* Reserved 80Ch*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 60 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 61 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 62 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 63 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 64 uint32_t Reserved20; /* Reserved 820h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 65 uint32_t Reserved9; /* Reserved 824h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 66 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 67 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 68 __IO uint32_t DTHRCTL; /* dev thr 830h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 69 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 70 }
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 71 USB_OTG_DREGS;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 72
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 73 typedef struct
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 74 {
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 75 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 76 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 77 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 78 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 79 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 80 uint32_t Reserved14;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 81 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 82 uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 83 }
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 84 USB_OTG_INEPREGS;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 85
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 86 typedef struct
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 87 {
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 88 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 89 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 90 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 91 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 92 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 93 uint32_t Reserved14[3];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 94 }
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 95 USB_OTG_OUTEPREGS;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 96
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 97 typedef struct
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 98 {
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 99 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 100 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 101 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 102 uint32_t Reserved40C; /* Reserved 40Ch*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 103 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 104 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 105 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 106 }
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 107 USB_OTG_HREGS;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 108
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 109 typedef struct
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 110 {
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 111 __IO uint32_t HCCHAR;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 112 __IO uint32_t HCSPLT;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 113 __IO uint32_t HCINT;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 114 __IO uint32_t HCINTMSK;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 115 __IO uint32_t HCTSIZ;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 116 uint32_t Reserved[3];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 117 }
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 118 USB_OTG_HC_REGS;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 119
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 120 typedef struct
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 121 {
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 122 USB_OTG_GREGS GREGS;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 123 uint32_t RESERVED0[188];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 124 USB_OTG_HREGS HREGS;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 125 uint32_t RESERVED1[9];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 126 __IO uint32_t HPRT;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 127 uint32_t RESERVED2[47];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 128 USB_OTG_HC_REGS HC_REGS[8];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 129 uint32_t RESERVED3[128];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 130 USB_OTG_DREGS DREGS;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 131 uint32_t RESERVED4[50];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 132 USB_OTG_INEPREGS INEP_REGS[4];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 133 uint32_t RESERVED5[96];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 134 USB_OTG_OUTEPREGS OUTEP_REGS[4];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 135 uint32_t RESERVED6[160];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 136 __IO uint32_t PCGCCTL;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 137 uint32_t RESERVED7[127];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 138 __IO uint32_t FIFO[4][1024];
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 139 }
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 140 USB_OTG_CORE_REGS;
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 141
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 142
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 143 #define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 144 #define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 145
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 146 #endif //__USB_OTG_REGS_H__
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 147
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 148 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
frq08711@LMECWL0871.LME.ST.COM 1:2a3ae13b45ef 149