LSM6DSO - iNEMO inertial module: 3D accelerometer and 3D gy…

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iNEMO inertial module: 3D accelerometer and 3D gyroscope.

Dependencies: X_NUCLEO_COMMON ST_INTERFACES

Dependents: X_NUCLEO_IKS01A3 X_NUCLEO_IKS01A3

lsm6dso_reg.c@4:77faf76e3cd8, 2 months ago (annotated)

Committer:: cparata
Date:: Thu Oct 29 12:50:52 2020 +0000
Revision:: 4:77faf76e3cd8
Parent:: 3:4274d9103f1d

Update PID and add low power modes

Who changed what in which revision?

User	Revision	Line number	New contents of line
cparata	0:6d69e896ce38	1	/*
cparata	4:77faf76e3cd8	2	******************************************************************************
cparata	4:77faf76e3cd8	3	* @file lsm6dso_reg.c
cparata	4:77faf76e3cd8	4	* @author Sensors Software Solution Team
cparata	4:77faf76e3cd8	5	* @brief LSM6DSO driver file
cparata	4:77faf76e3cd8	6	******************************************************************************
cparata	4:77faf76e3cd8	7	* @attention
cparata	4:77faf76e3cd8	8	*
cparata	4:77faf76e3cd8	9	* <h2><center>© Copyright (c) 2019 STMicroelectronics.
cparata	4:77faf76e3cd8	10	* All rights reserved.</center></h2>
cparata	4:77faf76e3cd8	11	*
cparata	4:77faf76e3cd8	12	* This software component is licensed by ST under BSD 3-Clause license,
cparata	4:77faf76e3cd8	13	* the "License"; You may not use this file except in compliance with the
cparata	4:77faf76e3cd8	14	* License. You may obtain a copy of the License at:
cparata	4:77faf76e3cd8	15	* opensource.org/licenses/BSD-3-Clause
cparata	4:77faf76e3cd8	16	*
cparata	4:77faf76e3cd8	17	******************************************************************************
cparata	4:77faf76e3cd8	18	*/
cparata	0:6d69e896ce38	19
cparata	0:6d69e896ce38	20	#include "lsm6dso_reg.h"
cparata	0:6d69e896ce38	21
cparata	0:6d69e896ce38	22	/**
cparata	0:6d69e896ce38	23	* @defgroup LSM6DSO
cparata	0:6d69e896ce38	24	* @brief This file provides a set of functions needed to drive the
cparata	0:6d69e896ce38	25	* lsm6dso enhanced inertial module.
cparata	0:6d69e896ce38	26	* @{
cparata	0:6d69e896ce38	27	*
cparata	0:6d69e896ce38	28	*/
cparata	0:6d69e896ce38	29
cparata	0:6d69e896ce38	30	/**
cparata	0:6d69e896ce38	31	* @defgroup LSM6DSO_Interfaces_Functions
cparata	0:6d69e896ce38	32	* @brief This section provide a set of functions used to read and
cparata	0:6d69e896ce38	33	* write a generic register of the device.
cparata	0:6d69e896ce38	34	* MANDATORY: return 0 -> no Error.
cparata	0:6d69e896ce38	35	* @{
cparata	0:6d69e896ce38	36	*
cparata	0:6d69e896ce38	37	*/
cparata	0:6d69e896ce38	38
cparata	0:6d69e896ce38	39	/**
cparata	0:6d69e896ce38	40	* @brief Read generic device register
cparata	0:6d69e896ce38	41	*
cparata	0:6d69e896ce38	42	* @param ctx read / write interface definitions(ptr)
cparata	0:6d69e896ce38	43	* @param reg register to read
cparata	0:6d69e896ce38	44	* @param data pointer to buffer that store the data read(ptr)
cparata	0:6d69e896ce38	45	* @param len number of consecutive register to read
cparata	0:6d69e896ce38	46	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:6d69e896ce38	47	*
cparata	0:6d69e896ce38	48	*/
cparata	4:77faf76e3cd8	49	int32_t lsm6dso_read_reg(lsm6dso_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	0:6d69e896ce38	50	uint16_t len)
cparata	0:6d69e896ce38	51	{
cparata	4:77faf76e3cd8	52	int32_t ret;
cparata	4:77faf76e3cd8	53	ret = ctx->read_reg(ctx->handle, reg, data, len);
cparata	4:77faf76e3cd8	54	return ret;
cparata	0:6d69e896ce38	55	}
cparata	0:6d69e896ce38	56
cparata	0:6d69e896ce38	57	/**
cparata	0:6d69e896ce38	58	* @brief Write generic device register
cparata	0:6d69e896ce38	59	*
cparata	0:6d69e896ce38	60	* @param ctx read / write interface definitions(ptr)
cparata	0:6d69e896ce38	61	* @param reg register to write
cparata	0:6d69e896ce38	62	* @param data pointer to data to write in register reg(ptr)
cparata	0:6d69e896ce38	63	* @param len number of consecutive register to write
cparata	0:6d69e896ce38	64	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:6d69e896ce38	65	*
cparata	0:6d69e896ce38	66	*/
cparata	4:77faf76e3cd8	67	int32_t lsm6dso_write_reg(lsm6dso_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	0:6d69e896ce38	68	uint16_t len)
cparata	0:6d69e896ce38	69	{
cparata	4:77faf76e3cd8	70	int32_t ret;
cparata	4:77faf76e3cd8	71	ret = ctx->write_reg(ctx->handle, reg, data, len);
cparata	4:77faf76e3cd8	72	return ret;
cparata	0:6d69e896ce38	73	}
cparata	0:6d69e896ce38	74
cparata	0:6d69e896ce38	75	/**
cparata	0:6d69e896ce38	76	* @}
cparata	0:6d69e896ce38	77	*
cparata	0:6d69e896ce38	78	*/
cparata	0:6d69e896ce38	79
cparata	0:6d69e896ce38	80	/**
cparata	4:77faf76e3cd8	81	* @defgroup LSM6DSOX_Private_functions
cparata	4:77faf76e3cd8	82	* @brief Section collect all the utility functions needed by APIs.
cparata	4:77faf76e3cd8	83	* @{
cparata	4:77faf76e3cd8	84	*
cparata	4:77faf76e3cd8	85	*/
cparata	4:77faf76e3cd8	86
cparata	4:77faf76e3cd8	87	static void bytecpy(uint8_t target, uint8_t source)
cparata	4:77faf76e3cd8	88	{
cparata	4:77faf76e3cd8	89	if ( (target != NULL) && (source != NULL) ) {
cparata	4:77faf76e3cd8	90	target = source;
cparata	4:77faf76e3cd8	91	}
cparata	4:77faf76e3cd8	92	}
cparata	4:77faf76e3cd8	93
cparata	4:77faf76e3cd8	94	/**
cparata	0:6d69e896ce38	95	* @defgroup LSM6DSO_Sensitivity
cparata	0:6d69e896ce38	96	* @brief These functions convert raw-data into engineering units.
cparata	0:6d69e896ce38	97	* @{
cparata	0:6d69e896ce38	98	*
cparata	0:6d69e896ce38	99	*/
cparata	2:4d14e9edf37e	100	float_t lsm6dso_from_fs2_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	101	{
cparata	4:77faf76e3cd8	102	return ((float_t)lsb) * 0.061f;
cparata	2:4d14e9edf37e	103	}
cparata	2:4d14e9edf37e	104
cparata	2:4d14e9edf37e	105	float_t lsm6dso_from_fs4_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	106	{
cparata	4:77faf76e3cd8	107	return ((float_t)lsb) * 0.122f;
cparata	2:4d14e9edf37e	108	}
cparata	2:4d14e9edf37e	109
cparata	2:4d14e9edf37e	110	float_t lsm6dso_from_fs8_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	111	{
cparata	4:77faf76e3cd8	112	return ((float_t)lsb) * 0.244f;
cparata	2:4d14e9edf37e	113	}
cparata	2:4d14e9edf37e	114
cparata	2:4d14e9edf37e	115	float_t lsm6dso_from_fs16_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	116	{
cparata	4:77faf76e3cd8	117	return ((float_t)lsb) *0.488f;
cparata	2:4d14e9edf37e	118	}
cparata	2:4d14e9edf37e	119
cparata	2:4d14e9edf37e	120	float_t lsm6dso_from_fs125_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	121	{
cparata	4:77faf76e3cd8	122	return ((float_t)lsb) *4.375f;
cparata	2:4d14e9edf37e	123	}
cparata	2:4d14e9edf37e	124
cparata	2:4d14e9edf37e	125	float_t lsm6dso_from_fs500_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	126	{
cparata	4:77faf76e3cd8	127	return ((float_t)lsb) *17.50f;
cparata	2:4d14e9edf37e	128	}
cparata	2:4d14e9edf37e	129
cparata	2:4d14e9edf37e	130	float_t lsm6dso_from_fs250_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	131	{
cparata	4:77faf76e3cd8	132	return ((float_t)lsb) *8.750f;
cparata	2:4d14e9edf37e	133	}
cparata	2:4d14e9edf37e	134
cparata	2:4d14e9edf37e	135	float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	136	{
cparata	4:77faf76e3cd8	137	return ((float_t)lsb) *35.0f;
cparata	2:4d14e9edf37e	138	}
cparata	2:4d14e9edf37e	139
cparata	2:4d14e9edf37e	140	float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	141	{
cparata	4:77faf76e3cd8	142	return ((float_t)lsb) *70.0f;
cparata	2:4d14e9edf37e	143	}
cparata	2:4d14e9edf37e	144
cparata	2:4d14e9edf37e	145	float_t lsm6dso_from_lsb_to_celsius(int16_t lsb)
cparata	2:4d14e9edf37e	146	{
cparata	4:77faf76e3cd8	147	return (((float_t)lsb / 256.0f) + 25.0f);
cparata	2:4d14e9edf37e	148	}
cparata	2:4d14e9edf37e	149
cparata	2:4d14e9edf37e	150	float_t lsm6dso_from_lsb_to_nsec(int16_t lsb)
cparata	2:4d14e9edf37e	151	{
cparata	4:77faf76e3cd8	152	return ((float_t)lsb * 25000.0f);
cparata	0:6d69e896ce38	153	}
cparata	0:6d69e896ce38	154
cparata	0:6d69e896ce38	155	/**
cparata	0:6d69e896ce38	156	* @}
cparata	0:6d69e896ce38	157	*
cparata	0:6d69e896ce38	158	*/
cparata	0:6d69e896ce38	159
cparata	0:6d69e896ce38	160	/**
cparata	0:6d69e896ce38	161	* @defgroup LSM6DSO_Data_Generation
cparata	0:6d69e896ce38	162	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	163	* data generation.
cparata	0:6d69e896ce38	164	*
cparata	0:6d69e896ce38	165	*/
cparata	0:6d69e896ce38	166
cparata	0:6d69e896ce38	167	/**
cparata	0:6d69e896ce38	168	* @brief Accelerometer full-scale selection.[set]
cparata	0:6d69e896ce38	169	*
cparata	0:6d69e896ce38	170	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	171	* @param val change the values of fs_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	172	*
cparata	0:6d69e896ce38	173	*/
cparata	0:6d69e896ce38	174	int32_t lsm6dso_xl_full_scale_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	175	lsm6dso_fs_xl_t val)
cparata	0:6d69e896ce38	176	{
cparata	4:77faf76e3cd8	177	lsm6dso_ctrl1_xl_t reg;
cparata	4:77faf76e3cd8	178	int32_t ret;
cparata	4:77faf76e3cd8	179
cparata	4:77faf76e3cd8	180	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	181	if (ret == 0) {
cparata	4:77faf76e3cd8	182	reg.fs_xl = (uint8_t) val;
cparata	4:77faf76e3cd8	183	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	184	}
cparata	4:77faf76e3cd8	185	return ret;
cparata	0:6d69e896ce38	186	}
cparata	0:6d69e896ce38	187
cparata	0:6d69e896ce38	188	/**
cparata	0:6d69e896ce38	189	* @brief Accelerometer full-scale selection.[get]
cparata	0:6d69e896ce38	190	*
cparata	0:6d69e896ce38	191	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	192	* @param val Get the values of fs_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	193	*
cparata	0:6d69e896ce38	194	*/
cparata	0:6d69e896ce38	195	int32_t lsm6dso_xl_full_scale_get(lsm6dso_ctx_t ctx, lsm6dso_fs_xl_t val)
cparata	0:6d69e896ce38	196	{
cparata	4:77faf76e3cd8	197	lsm6dso_ctrl1_xl_t reg;
cparata	4:77faf76e3cd8	198	int32_t ret;
cparata	4:77faf76e3cd8	199
cparata	4:77faf76e3cd8	200	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	201	switch (reg.fs_xl) {
cparata	4:77faf76e3cd8	202	case LSM6DSO_2g:
cparata	4:77faf76e3cd8	203	*val = LSM6DSO_2g;
cparata	4:77faf76e3cd8	204	break;
cparata	4:77faf76e3cd8	205	case LSM6DSO_16g:
cparata	4:77faf76e3cd8	206	*val = LSM6DSO_16g;
cparata	4:77faf76e3cd8	207	break;
cparata	4:77faf76e3cd8	208	case LSM6DSO_4g:
cparata	4:77faf76e3cd8	209	*val = LSM6DSO_4g;
cparata	4:77faf76e3cd8	210	break;
cparata	4:77faf76e3cd8	211	case LSM6DSO_8g:
cparata	4:77faf76e3cd8	212	*val = LSM6DSO_8g;
cparata	4:77faf76e3cd8	213	break;
cparata	4:77faf76e3cd8	214	default:
cparata	4:77faf76e3cd8	215	*val = LSM6DSO_2g;
cparata	4:77faf76e3cd8	216	break;
cparata	4:77faf76e3cd8	217	}
cparata	4:77faf76e3cd8	218
cparata	4:77faf76e3cd8	219	return ret;
cparata	0:6d69e896ce38	220	}
cparata	0:6d69e896ce38	221
cparata	0:6d69e896ce38	222	/**
cparata	0:6d69e896ce38	223	* @brief Accelerometer UI data rate selection.[set]
cparata	0:6d69e896ce38	224	*
cparata	0:6d69e896ce38	225	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	226	* @param val change the values of odr_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	227	*
cparata	0:6d69e896ce38	228	*/
cparata	0:6d69e896ce38	229	int32_t lsm6dso_xl_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_xl_t val)
cparata	0:6d69e896ce38	230	{
cparata	4:77faf76e3cd8	231	lsm6dso_odr_xl_t odr_xl = val;
cparata	4:77faf76e3cd8	232	lsm6dso_emb_fsm_enable_t fsm_enable;
cparata	4:77faf76e3cd8	233	lsm6dso_fsm_odr_t fsm_odr;
cparata	4:77faf76e3cd8	234	lsm6dso_ctrl1_xl_t reg;
cparata	4:77faf76e3cd8	235	int32_t ret;
cparata	4:77faf76e3cd8	236
cparata	4:77faf76e3cd8	237	/* Check the Finite State Machine data rate constraints */
cparata	4:77faf76e3cd8	238	ret = lsm6dso_fsm_enable_get(ctx, &fsm_enable);
cparata	4:77faf76e3cd8	239	if (ret == 0) {
cparata	4:77faf76e3cd8	240	if ( (fsm_enable.fsm_enable_a.fsm1_en \|
cparata	4:77faf76e3cd8	241	fsm_enable.fsm_enable_a.fsm2_en \|
cparata	4:77faf76e3cd8	242	fsm_enable.fsm_enable_a.fsm3_en \|
cparata	4:77faf76e3cd8	243	fsm_enable.fsm_enable_a.fsm4_en \|
cparata	4:77faf76e3cd8	244	fsm_enable.fsm_enable_a.fsm5_en \|
cparata	4:77faf76e3cd8	245	fsm_enable.fsm_enable_a.fsm6_en \|
cparata	4:77faf76e3cd8	246	fsm_enable.fsm_enable_a.fsm7_en \|
cparata	4:77faf76e3cd8	247	fsm_enable.fsm_enable_a.fsm8_en \|
cparata	4:77faf76e3cd8	248	fsm_enable.fsm_enable_b.fsm9_en \|
cparata	4:77faf76e3cd8	249	fsm_enable.fsm_enable_b.fsm10_en \|
cparata	4:77faf76e3cd8	250	fsm_enable.fsm_enable_b.fsm11_en \|
cparata	4:77faf76e3cd8	251	fsm_enable.fsm_enable_b.fsm12_en \|
cparata	4:77faf76e3cd8	252	fsm_enable.fsm_enable_b.fsm13_en \|
cparata	4:77faf76e3cd8	253	fsm_enable.fsm_enable_b.fsm14_en \|
cparata	4:77faf76e3cd8	254	fsm_enable.fsm_enable_b.fsm15_en \|
cparata	4:77faf76e3cd8	255	fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
cparata	4:77faf76e3cd8	256
cparata	4:77faf76e3cd8	257	ret = lsm6dso_fsm_data_rate_get(ctx, &fsm_odr);
cparata	4:77faf76e3cd8	258	if (ret == 0) {
cparata	4:77faf76e3cd8	259	switch (fsm_odr) {
cparata	4:77faf76e3cd8	260	case LSM6DSO_ODR_FSM_12Hz5:
cparata	4:77faf76e3cd8	261
cparata	4:77faf76e3cd8	262	if (val == LSM6DSO_XL_ODR_OFF){
cparata	4:77faf76e3cd8	263	odr_xl = LSM6DSO_XL_ODR_12Hz5;
cparata	4:77faf76e3cd8	264
cparata	4:77faf76e3cd8	265	} else {
cparata	4:77faf76e3cd8	266	odr_xl = val;
cparata	4:77faf76e3cd8	267	}
cparata	4:77faf76e3cd8	268	break;
cparata	4:77faf76e3cd8	269	case LSM6DSO_ODR_FSM_26Hz:
cparata	4:77faf76e3cd8	270
cparata	4:77faf76e3cd8	271	if (val == LSM6DSO_XL_ODR_OFF){
cparata	4:77faf76e3cd8	272	odr_xl = LSM6DSO_XL_ODR_26Hz;
cparata	4:77faf76e3cd8	273
cparata	4:77faf76e3cd8	274	} else if (val == LSM6DSO_XL_ODR_12Hz5){
cparata	4:77faf76e3cd8	275	odr_xl = LSM6DSO_XL_ODR_26Hz;
cparata	4:77faf76e3cd8	276
cparata	4:77faf76e3cd8	277	} else {
cparata	4:77faf76e3cd8	278	odr_xl = val;
cparata	4:77faf76e3cd8	279	}
cparata	4:77faf76e3cd8	280	break;
cparata	4:77faf76e3cd8	281	case LSM6DSO_ODR_FSM_52Hz:
cparata	4:77faf76e3cd8	282
cparata	4:77faf76e3cd8	283	if (val == LSM6DSO_XL_ODR_OFF){
cparata	4:77faf76e3cd8	284	odr_xl = LSM6DSO_XL_ODR_52Hz;
cparata	4:77faf76e3cd8	285
cparata	4:77faf76e3cd8	286	} else if (val == LSM6DSO_XL_ODR_12Hz5){
cparata	4:77faf76e3cd8	287	odr_xl = LSM6DSO_XL_ODR_52Hz;
cparata	4:77faf76e3cd8	288
cparata	4:77faf76e3cd8	289	} else if (val == LSM6DSO_XL_ODR_26Hz){
cparata	4:77faf76e3cd8	290	odr_xl = LSM6DSO_XL_ODR_52Hz;
cparata	4:77faf76e3cd8	291
cparata	4:77faf76e3cd8	292	} else {
cparata	4:77faf76e3cd8	293	odr_xl = val;
cparata	4:77faf76e3cd8	294	}
cparata	4:77faf76e3cd8	295	break;
cparata	4:77faf76e3cd8	296	case LSM6DSO_ODR_FSM_104Hz:
cparata	4:77faf76e3cd8	297
cparata	4:77faf76e3cd8	298	if (val == LSM6DSO_XL_ODR_OFF){
cparata	4:77faf76e3cd8	299	odr_xl = LSM6DSO_XL_ODR_104Hz;
cparata	4:77faf76e3cd8	300
cparata	4:77faf76e3cd8	301	} else if (val == LSM6DSO_XL_ODR_12Hz5){
cparata	4:77faf76e3cd8	302	odr_xl = LSM6DSO_XL_ODR_104Hz;
cparata	4:77faf76e3cd8	303
cparata	4:77faf76e3cd8	304	} else if (val == LSM6DSO_XL_ODR_26Hz){
cparata	4:77faf76e3cd8	305	odr_xl = LSM6DSO_XL_ODR_104Hz;
cparata	4:77faf76e3cd8	306
cparata	4:77faf76e3cd8	307	} else if (val == LSM6DSO_XL_ODR_52Hz){
cparata	4:77faf76e3cd8	308	odr_xl = LSM6DSO_XL_ODR_104Hz;
cparata	4:77faf76e3cd8	309
cparata	4:77faf76e3cd8	310	} else {
cparata	4:77faf76e3cd8	311	odr_xl = val;
cparata	4:77faf76e3cd8	312	}
cparata	4:77faf76e3cd8	313	break;
cparata	4:77faf76e3cd8	314	default:
cparata	4:77faf76e3cd8	315	odr_xl = val;
cparata	4:77faf76e3cd8	316	break;
cparata	4:77faf76e3cd8	317	}
cparata	4:77faf76e3cd8	318	}
cparata	3:4274d9103f1d	319	}
cparata	4:77faf76e3cd8	320	}
cparata	4:77faf76e3cd8	321	if (ret == 0) {
cparata	4:77faf76e3cd8	322	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	323	}
cparata	4:77faf76e3cd8	324	if (ret == 0) {
cparata	4:77faf76e3cd8	325	reg.odr_xl = (uint8_t) odr_xl;
cparata	4:77faf76e3cd8	326	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	327	}
cparata	4:77faf76e3cd8	328	return ret;
cparata	0:6d69e896ce38	329	}
cparata	0:6d69e896ce38	330
cparata	0:6d69e896ce38	331	/**
cparata	0:6d69e896ce38	332	* @brief Accelerometer UI data rate selection.[get]
cparata	0:6d69e896ce38	333	*
cparata	0:6d69e896ce38	334	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	335	* @param val Get the values of odr_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	336	*
cparata	0:6d69e896ce38	337	*/
cparata	0:6d69e896ce38	338	int32_t lsm6dso_xl_data_rate_get(lsm6dso_ctx_t ctx, lsm6dso_odr_xl_t val)
cparata	0:6d69e896ce38	339	{
cparata	4:77faf76e3cd8	340	lsm6dso_ctrl1_xl_t reg;
cparata	4:77faf76e3cd8	341	int32_t ret;
cparata	4:77faf76e3cd8	342
cparata	4:77faf76e3cd8	343	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	344
cparata	4:77faf76e3cd8	345	switch (reg.odr_xl) {
cparata	4:77faf76e3cd8	346	case LSM6DSO_XL_ODR_OFF:
cparata	4:77faf76e3cd8	347	*val = LSM6DSO_XL_ODR_OFF;
cparata	4:77faf76e3cd8	348	break;
cparata	4:77faf76e3cd8	349	case LSM6DSO_XL_ODR_12Hz5:
cparata	4:77faf76e3cd8	350	*val = LSM6DSO_XL_ODR_12Hz5;
cparata	4:77faf76e3cd8	351	break;
cparata	4:77faf76e3cd8	352	case LSM6DSO_XL_ODR_26Hz:
cparata	4:77faf76e3cd8	353	*val = LSM6DSO_XL_ODR_26Hz;
cparata	4:77faf76e3cd8	354	break;
cparata	4:77faf76e3cd8	355	case LSM6DSO_XL_ODR_52Hz:
cparata	4:77faf76e3cd8	356	*val = LSM6DSO_XL_ODR_52Hz;
cparata	4:77faf76e3cd8	357	break;
cparata	4:77faf76e3cd8	358	case LSM6DSO_XL_ODR_104Hz:
cparata	4:77faf76e3cd8	359	*val = LSM6DSO_XL_ODR_104Hz;
cparata	4:77faf76e3cd8	360	break;
cparata	4:77faf76e3cd8	361	case LSM6DSO_XL_ODR_208Hz:
cparata	4:77faf76e3cd8	362	*val = LSM6DSO_XL_ODR_208Hz;
cparata	4:77faf76e3cd8	363	break;
cparata	4:77faf76e3cd8	364	case LSM6DSO_XL_ODR_417Hz:
cparata	4:77faf76e3cd8	365	*val = LSM6DSO_XL_ODR_417Hz;
cparata	4:77faf76e3cd8	366	break;
cparata	4:77faf76e3cd8	367	case LSM6DSO_XL_ODR_833Hz:
cparata	4:77faf76e3cd8	368	*val = LSM6DSO_XL_ODR_833Hz;
cparata	4:77faf76e3cd8	369	break;
cparata	4:77faf76e3cd8	370	case LSM6DSO_XL_ODR_1667Hz:
cparata	4:77faf76e3cd8	371	*val = LSM6DSO_XL_ODR_1667Hz;
cparata	4:77faf76e3cd8	372	break;
cparata	4:77faf76e3cd8	373	case LSM6DSO_XL_ODR_3333Hz:
cparata	4:77faf76e3cd8	374	*val = LSM6DSO_XL_ODR_3333Hz;
cparata	4:77faf76e3cd8	375	break;
cparata	4:77faf76e3cd8	376	case LSM6DSO_XL_ODR_6667Hz:
cparata	4:77faf76e3cd8	377	*val = LSM6DSO_XL_ODR_6667Hz;
cparata	4:77faf76e3cd8	378	break;
cparata	4:77faf76e3cd8	379	case LSM6DSO_XL_ODR_1Hz6:
cparata	4:77faf76e3cd8	380	*val = LSM6DSO_XL_ODR_1Hz6;
cparata	4:77faf76e3cd8	381	break;
cparata	4:77faf76e3cd8	382	default:
cparata	4:77faf76e3cd8	383	*val = LSM6DSO_XL_ODR_OFF;
cparata	4:77faf76e3cd8	384	break;
cparata	4:77faf76e3cd8	385	}
cparata	4:77faf76e3cd8	386	return ret;
cparata	0:6d69e896ce38	387	}
cparata	0:6d69e896ce38	388
cparata	0:6d69e896ce38	389	/**
cparata	0:6d69e896ce38	390	* @brief Gyroscope UI chain full-scale selection.[set]
cparata	0:6d69e896ce38	391	*
cparata	0:6d69e896ce38	392	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	393	* @param val change the values of fs_g in reg CTRL2_G
cparata	0:6d69e896ce38	394	*
cparata	0:6d69e896ce38	395	*/
cparata	0:6d69e896ce38	396	int32_t lsm6dso_gy_full_scale_set(lsm6dso_ctx_t *ctx, lsm6dso_fs_g_t val)
cparata	0:6d69e896ce38	397	{
cparata	4:77faf76e3cd8	398	lsm6dso_ctrl2_g_t reg;
cparata	4:77faf76e3cd8	399	int32_t ret;
cparata	4:77faf76e3cd8	400
cparata	4:77faf76e3cd8	401	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	402	if (ret == 0) {
cparata	4:77faf76e3cd8	403	reg.fs_g = (uint8_t) val;
cparata	4:77faf76e3cd8	404	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	405	}
cparata	4:77faf76e3cd8	406
cparata	4:77faf76e3cd8	407	return ret;
cparata	0:6d69e896ce38	408	}
cparata	0:6d69e896ce38	409
cparata	0:6d69e896ce38	410	/**
cparata	0:6d69e896ce38	411	* @brief Gyroscope UI chain full-scale selection.[get]
cparata	0:6d69e896ce38	412	*
cparata	0:6d69e896ce38	413	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	414	* @param val Get the values of fs_g in reg CTRL2_G
cparata	0:6d69e896ce38	415	*
cparata	0:6d69e896ce38	416	*/
cparata	0:6d69e896ce38	417	int32_t lsm6dso_gy_full_scale_get(lsm6dso_ctx_t ctx, lsm6dso_fs_g_t val)
cparata	0:6d69e896ce38	418	{
cparata	4:77faf76e3cd8	419	lsm6dso_ctrl2_g_t reg;
cparata	4:77faf76e3cd8	420	int32_t ret;
cparata	4:77faf76e3cd8	421
cparata	4:77faf76e3cd8	422	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	423	switch (reg.fs_g) {
cparata	4:77faf76e3cd8	424	case LSM6DSO_250dps:
cparata	4:77faf76e3cd8	425	*val = LSM6DSO_250dps;
cparata	4:77faf76e3cd8	426	break;
cparata	4:77faf76e3cd8	427	case LSM6DSO_125dps:
cparata	4:77faf76e3cd8	428	*val = LSM6DSO_125dps;
cparata	4:77faf76e3cd8	429	break;
cparata	4:77faf76e3cd8	430	case LSM6DSO_500dps:
cparata	4:77faf76e3cd8	431	*val = LSM6DSO_500dps;
cparata	4:77faf76e3cd8	432	break;
cparata	4:77faf76e3cd8	433	case LSM6DSO_1000dps:
cparata	4:77faf76e3cd8	434	*val = LSM6DSO_1000dps;
cparata	4:77faf76e3cd8	435	break;
cparata	4:77faf76e3cd8	436	case LSM6DSO_2000dps:
cparata	4:77faf76e3cd8	437	*val = LSM6DSO_2000dps;
cparata	4:77faf76e3cd8	438	break;
cparata	4:77faf76e3cd8	439	default:
cparata	4:77faf76e3cd8	440	*val = LSM6DSO_250dps;
cparata	4:77faf76e3cd8	441	break;
cparata	4:77faf76e3cd8	442	}
cparata	4:77faf76e3cd8	443
cparata	4:77faf76e3cd8	444	return ret;
cparata	0:6d69e896ce38	445	}
cparata	0:6d69e896ce38	446
cparata	0:6d69e896ce38	447	/**
cparata	0:6d69e896ce38	448	* @brief Gyroscope UI data rate selection.[set]
cparata	0:6d69e896ce38	449	*
cparata	0:6d69e896ce38	450	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	451	* @param val change the values of odr_g in reg CTRL2_G
cparata	0:6d69e896ce38	452	*
cparata	0:6d69e896ce38	453	*/
cparata	0:6d69e896ce38	454	int32_t lsm6dso_gy_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_g_t val)
cparata	0:6d69e896ce38	455	{
cparata	4:77faf76e3cd8	456	lsm6dso_odr_g_t odr_gy = val;
cparata	4:77faf76e3cd8	457	lsm6dso_emb_fsm_enable_t fsm_enable;
cparata	4:77faf76e3cd8	458	lsm6dso_fsm_odr_t fsm_odr;
cparata	4:77faf76e3cd8	459	lsm6dso_ctrl2_g_t reg;
cparata	4:77faf76e3cd8	460	int32_t ret;
cparata	4:77faf76e3cd8	461
cparata	4:77faf76e3cd8	462	/* Check the Finite State Machine data rate constraints */
cparata	4:77faf76e3cd8	463	ret = lsm6dso_fsm_enable_get(ctx, &fsm_enable);
cparata	4:77faf76e3cd8	464	if (ret == 0) {
cparata	4:77faf76e3cd8	465	if ( (fsm_enable.fsm_enable_a.fsm1_en \|
cparata	4:77faf76e3cd8	466	fsm_enable.fsm_enable_a.fsm2_en \|
cparata	4:77faf76e3cd8	467	fsm_enable.fsm_enable_a.fsm3_en \|
cparata	4:77faf76e3cd8	468	fsm_enable.fsm_enable_a.fsm4_en \|
cparata	4:77faf76e3cd8	469	fsm_enable.fsm_enable_a.fsm5_en \|
cparata	4:77faf76e3cd8	470	fsm_enable.fsm_enable_a.fsm6_en \|
cparata	4:77faf76e3cd8	471	fsm_enable.fsm_enable_a.fsm7_en \|
cparata	4:77faf76e3cd8	472	fsm_enable.fsm_enable_a.fsm8_en \|
cparata	4:77faf76e3cd8	473	fsm_enable.fsm_enable_b.fsm9_en \|
cparata	4:77faf76e3cd8	474	fsm_enable.fsm_enable_b.fsm10_en \|
cparata	4:77faf76e3cd8	475	fsm_enable.fsm_enable_b.fsm11_en \|
cparata	4:77faf76e3cd8	476	fsm_enable.fsm_enable_b.fsm12_en \|
cparata	4:77faf76e3cd8	477	fsm_enable.fsm_enable_b.fsm13_en \|
cparata	4:77faf76e3cd8	478	fsm_enable.fsm_enable_b.fsm14_en \|
cparata	4:77faf76e3cd8	479	fsm_enable.fsm_enable_b.fsm15_en \|
cparata	4:77faf76e3cd8	480	fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
cparata	4:77faf76e3cd8	481
cparata	4:77faf76e3cd8	482	ret = lsm6dso_fsm_data_rate_get(ctx, &fsm_odr);
cparata	4:77faf76e3cd8	483	if (ret == 0) {
cparata	4:77faf76e3cd8	484	switch (fsm_odr) {
cparata	4:77faf76e3cd8	485	case LSM6DSO_ODR_FSM_12Hz5:
cparata	4:77faf76e3cd8	486
cparata	4:77faf76e3cd8	487	if (val == LSM6DSO_GY_ODR_OFF){
cparata	4:77faf76e3cd8	488	odr_gy = LSM6DSO_GY_ODR_12Hz5;
cparata	4:77faf76e3cd8	489
cparata	4:77faf76e3cd8	490	} else {
cparata	4:77faf76e3cd8	491	odr_gy = val;
cparata	4:77faf76e3cd8	492	}
cparata	4:77faf76e3cd8	493	break;
cparata	4:77faf76e3cd8	494	case LSM6DSO_ODR_FSM_26Hz:
cparata	4:77faf76e3cd8	495
cparata	4:77faf76e3cd8	496	if (val == LSM6DSO_GY_ODR_OFF){
cparata	4:77faf76e3cd8	497	odr_gy = LSM6DSO_GY_ODR_26Hz;
cparata	4:77faf76e3cd8	498
cparata	4:77faf76e3cd8	499	} else if (val == LSM6DSO_GY_ODR_12Hz5){
cparata	4:77faf76e3cd8	500	odr_gy = LSM6DSO_GY_ODR_26Hz;
cparata	4:77faf76e3cd8	501
cparata	4:77faf76e3cd8	502	} else {
cparata	4:77faf76e3cd8	503	odr_gy = val;
cparata	4:77faf76e3cd8	504	}
cparata	4:77faf76e3cd8	505	break;
cparata	4:77faf76e3cd8	506	case LSM6DSO_ODR_FSM_52Hz:
cparata	4:77faf76e3cd8	507
cparata	4:77faf76e3cd8	508	if (val == LSM6DSO_GY_ODR_OFF){
cparata	4:77faf76e3cd8	509	odr_gy = LSM6DSO_GY_ODR_52Hz;
cparata	4:77faf76e3cd8	510
cparata	4:77faf76e3cd8	511	} else if (val == LSM6DSO_GY_ODR_12Hz5){
cparata	4:77faf76e3cd8	512	odr_gy = LSM6DSO_GY_ODR_52Hz;
cparata	4:77faf76e3cd8	513
cparata	4:77faf76e3cd8	514	} else if (val == LSM6DSO_GY_ODR_26Hz){
cparata	4:77faf76e3cd8	515	odr_gy = LSM6DSO_GY_ODR_52Hz;
cparata	4:77faf76e3cd8	516
cparata	4:77faf76e3cd8	517	} else {
cparata	4:77faf76e3cd8	518	odr_gy = val;
cparata	4:77faf76e3cd8	519	}
cparata	4:77faf76e3cd8	520	break;
cparata	4:77faf76e3cd8	521	case LSM6DSO_ODR_FSM_104Hz:
cparata	4:77faf76e3cd8	522
cparata	4:77faf76e3cd8	523	if (val == LSM6DSO_GY_ODR_OFF){
cparata	4:77faf76e3cd8	524	odr_gy = LSM6DSO_GY_ODR_104Hz;
cparata	4:77faf76e3cd8	525
cparata	4:77faf76e3cd8	526	} else if (val == LSM6DSO_GY_ODR_12Hz5){
cparata	4:77faf76e3cd8	527	odr_gy = LSM6DSO_GY_ODR_104Hz;
cparata	4:77faf76e3cd8	528
cparata	4:77faf76e3cd8	529	} else if (val == LSM6DSO_GY_ODR_26Hz){
cparata	4:77faf76e3cd8	530	odr_gy = LSM6DSO_GY_ODR_104Hz;
cparata	4:77faf76e3cd8	531
cparata	4:77faf76e3cd8	532	} else if (val == LSM6DSO_GY_ODR_52Hz){
cparata	4:77faf76e3cd8	533	odr_gy = LSM6DSO_GY_ODR_104Hz;
cparata	4:77faf76e3cd8	534
cparata	4:77faf76e3cd8	535	} else {
cparata	4:77faf76e3cd8	536	odr_gy = val;
cparata	4:77faf76e3cd8	537	}
cparata	4:77faf76e3cd8	538	break;
cparata	4:77faf76e3cd8	539	default:
cparata	4:77faf76e3cd8	540	odr_gy = val;
cparata	4:77faf76e3cd8	541	break;
cparata	4:77faf76e3cd8	542	}
cparata	4:77faf76e3cd8	543	}
cparata	3:4274d9103f1d	544	}
cparata	4:77faf76e3cd8	545	}
cparata	4:77faf76e3cd8	546
cparata	4:77faf76e3cd8	547	if (ret == 0) {
cparata	4:77faf76e3cd8	548	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	549	}
cparata	4:77faf76e3cd8	550	if (ret == 0) {
cparata	4:77faf76e3cd8	551	reg.odr_g = (uint8_t) odr_gy;
cparata	4:77faf76e3cd8	552	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	553	}
cparata	4:77faf76e3cd8	554
cparata	4:77faf76e3cd8	555	return ret;
cparata	0:6d69e896ce38	556	}
cparata	0:6d69e896ce38	557
cparata	0:6d69e896ce38	558	/**
cparata	0:6d69e896ce38	559	* @brief Gyroscope UI data rate selection.[get]
cparata	0:6d69e896ce38	560	*
cparata	0:6d69e896ce38	561	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	562	* @param val Get the values of odr_g in reg CTRL2_G
cparata	0:6d69e896ce38	563	*
cparata	0:6d69e896ce38	564	*/
cparata	0:6d69e896ce38	565	int32_t lsm6dso_gy_data_rate_get(lsm6dso_ctx_t ctx, lsm6dso_odr_g_t val)
cparata	0:6d69e896ce38	566	{
cparata	4:77faf76e3cd8	567	lsm6dso_ctrl2_g_t reg;
cparata	4:77faf76e3cd8	568	int32_t ret;
cparata	4:77faf76e3cd8	569
cparata	4:77faf76e3cd8	570	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	571	switch (reg.odr_g) {
cparata	4:77faf76e3cd8	572	case LSM6DSO_GY_ODR_OFF:
cparata	4:77faf76e3cd8	573	*val = LSM6DSO_GY_ODR_OFF;
cparata	4:77faf76e3cd8	574	break;
cparata	4:77faf76e3cd8	575	case LSM6DSO_GY_ODR_12Hz5:
cparata	4:77faf76e3cd8	576	*val = LSM6DSO_GY_ODR_12Hz5;
cparata	4:77faf76e3cd8	577	break;
cparata	4:77faf76e3cd8	578	case LSM6DSO_GY_ODR_26Hz:
cparata	4:77faf76e3cd8	579	*val = LSM6DSO_GY_ODR_26Hz;
cparata	4:77faf76e3cd8	580	break;
cparata	4:77faf76e3cd8	581	case LSM6DSO_GY_ODR_52Hz:
cparata	4:77faf76e3cd8	582	*val = LSM6DSO_GY_ODR_52Hz;
cparata	4:77faf76e3cd8	583	break;
cparata	4:77faf76e3cd8	584	case LSM6DSO_GY_ODR_104Hz:
cparata	4:77faf76e3cd8	585	*val = LSM6DSO_GY_ODR_104Hz;
cparata	4:77faf76e3cd8	586	break;
cparata	4:77faf76e3cd8	587	case LSM6DSO_GY_ODR_208Hz:
cparata	4:77faf76e3cd8	588	*val = LSM6DSO_GY_ODR_208Hz;
cparata	4:77faf76e3cd8	589	break;
cparata	4:77faf76e3cd8	590	case LSM6DSO_GY_ODR_417Hz:
cparata	4:77faf76e3cd8	591	*val = LSM6DSO_GY_ODR_417Hz;
cparata	4:77faf76e3cd8	592	break;
cparata	4:77faf76e3cd8	593	case LSM6DSO_GY_ODR_833Hz:
cparata	4:77faf76e3cd8	594	*val = LSM6DSO_GY_ODR_833Hz;
cparata	4:77faf76e3cd8	595	break;
cparata	4:77faf76e3cd8	596	case LSM6DSO_GY_ODR_1667Hz:
cparata	4:77faf76e3cd8	597	*val = LSM6DSO_GY_ODR_1667Hz;
cparata	4:77faf76e3cd8	598	break;
cparata	4:77faf76e3cd8	599	case LSM6DSO_GY_ODR_3333Hz:
cparata	4:77faf76e3cd8	600	*val = LSM6DSO_GY_ODR_3333Hz;
cparata	4:77faf76e3cd8	601	break;
cparata	4:77faf76e3cd8	602	case LSM6DSO_GY_ODR_6667Hz:
cparata	4:77faf76e3cd8	603	*val = LSM6DSO_GY_ODR_6667Hz;
cparata	4:77faf76e3cd8	604	break;
cparata	4:77faf76e3cd8	605	default:
cparata	4:77faf76e3cd8	606	*val = LSM6DSO_GY_ODR_OFF;
cparata	4:77faf76e3cd8	607	break;
cparata	4:77faf76e3cd8	608	}
cparata	4:77faf76e3cd8	609	return ret;
cparata	0:6d69e896ce38	610	}
cparata	0:6d69e896ce38	611
cparata	0:6d69e896ce38	612	/**
cparata	0:6d69e896ce38	613	* @brief Block data update.[set]
cparata	0:6d69e896ce38	614	*
cparata	0:6d69e896ce38	615	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	616	* @param val change the values of bdu in reg CTRL3_C
cparata	0:6d69e896ce38	617	*
cparata	0:6d69e896ce38	618	*/
cparata	0:6d69e896ce38	619	int32_t lsm6dso_block_data_update_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	620	{
cparata	4:77faf76e3cd8	621	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	622	int32_t ret;
cparata	4:77faf76e3cd8	623
cparata	4:77faf76e3cd8	624	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	625	if (ret == 0) {
cparata	4:77faf76e3cd8	626	reg.bdu = val;
cparata	4:77faf76e3cd8	627	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	628	}
cparata	4:77faf76e3cd8	629	return ret;
cparata	0:6d69e896ce38	630	}
cparata	0:6d69e896ce38	631
cparata	0:6d69e896ce38	632	/**
cparata	0:6d69e896ce38	633	* @brief Block data update.[get]
cparata	0:6d69e896ce38	634	*
cparata	0:6d69e896ce38	635	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	636	* @param val change the values of bdu in reg CTRL3_C
cparata	0:6d69e896ce38	637	*
cparata	0:6d69e896ce38	638	*/
cparata	0:6d69e896ce38	639	int32_t lsm6dso_block_data_update_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	640	{
cparata	4:77faf76e3cd8	641	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	642	int32_t ret;
cparata	4:77faf76e3cd8	643
cparata	4:77faf76e3cd8	644	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	645	*val = reg.bdu;
cparata	4:77faf76e3cd8	646
cparata	4:77faf76e3cd8	647	return ret;
cparata	0:6d69e896ce38	648	}
cparata	0:6d69e896ce38	649
cparata	0:6d69e896ce38	650	/**
cparata	0:6d69e896ce38	651	* @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
cparata	0:6d69e896ce38	652	* Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
cparata	0:6d69e896ce38	653	*
cparata	0:6d69e896ce38	654	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	655	* @param val change the values of usr_off_w in reg CTRL6_C
cparata	0:6d69e896ce38	656	*
cparata	0:6d69e896ce38	657	*/
cparata	0:6d69e896ce38	658	int32_t lsm6dso_xl_offset_weight_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	659	lsm6dso_usr_off_w_t val)
cparata	0:6d69e896ce38	660	{
cparata	4:77faf76e3cd8	661	lsm6dso_ctrl6_c_t reg;
cparata	4:77faf76e3cd8	662	int32_t ret;
cparata	4:77faf76e3cd8	663
cparata	4:77faf76e3cd8	664	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	665	if (ret == 0) {
cparata	4:77faf76e3cd8	666	reg.usr_off_w = (uint8_t)val;
cparata	4:77faf76e3cd8	667	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	668	}
cparata	4:77faf76e3cd8	669	return ret;
cparata	0:6d69e896ce38	670	}
cparata	0:6d69e896ce38	671
cparata	0:6d69e896ce38	672	/**
cparata	0:6d69e896ce38	673	* @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
cparata	0:6d69e896ce38	674	* Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
cparata	0:6d69e896ce38	675	*
cparata	0:6d69e896ce38	676	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	677	* @param val Get the values of usr_off_w in reg CTRL6_C
cparata	0:6d69e896ce38	678	*
cparata	0:6d69e896ce38	679	*/
cparata	0:6d69e896ce38	680	int32_t lsm6dso_xl_offset_weight_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	681	lsm6dso_usr_off_w_t *val)
cparata	0:6d69e896ce38	682	{
cparata	4:77faf76e3cd8	683	lsm6dso_ctrl6_c_t reg;
cparata	4:77faf76e3cd8	684	int32_t ret;
cparata	4:77faf76e3cd8	685
cparata	4:77faf76e3cd8	686	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	687
cparata	4:77faf76e3cd8	688	switch (reg.usr_off_w) {
cparata	4:77faf76e3cd8	689	case LSM6DSO_LSb_1mg:
cparata	4:77faf76e3cd8	690	*val = LSM6DSO_LSb_1mg;
cparata	4:77faf76e3cd8	691	break;
cparata	4:77faf76e3cd8	692	case LSM6DSO_LSb_16mg:
cparata	4:77faf76e3cd8	693	*val = LSM6DSO_LSb_16mg;
cparata	4:77faf76e3cd8	694	break;
cparata	4:77faf76e3cd8	695	default:
cparata	4:77faf76e3cd8	696	*val = LSM6DSO_LSb_1mg;
cparata	4:77faf76e3cd8	697	break;
cparata	4:77faf76e3cd8	698	}
cparata	4:77faf76e3cd8	699	return ret;
cparata	0:6d69e896ce38	700	}
cparata	0:6d69e896ce38	701
cparata	0:6d69e896ce38	702	/**
cparata	0:6d69e896ce38	703	* @brief Accelerometer power mode.[set]
cparata	0:6d69e896ce38	704	*
cparata	0:6d69e896ce38	705	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	706	* @param val change the values of xl_hm_mode in
cparata	0:6d69e896ce38	707	* reg CTRL6_C
cparata	0:6d69e896ce38	708	*
cparata	0:6d69e896ce38	709	*/
cparata	0:6d69e896ce38	710	int32_t lsm6dso_xl_power_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	711	lsm6dso_xl_hm_mode_t val)
cparata	0:6d69e896ce38	712	{
cparata	4:77faf76e3cd8	713	lsm6dso_ctrl5_c_t ctrl5_c;
cparata	4:77faf76e3cd8	714	lsm6dso_ctrl6_c_t ctrl6_c;
cparata	4:77faf76e3cd8	715	int32_t ret;
cparata	4:77faf76e3cd8	716
cparata	4:77faf76e3cd8	717	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata	4:77faf76e3cd8	718	if (ret == 0) {
cparata	4:77faf76e3cd8	719	ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
cparata	4:77faf76e3cd8	720	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata	4:77faf76e3cd8	721	}
cparata	4:77faf76e3cd8	722	if (ret == 0) {
cparata	4:77faf76e3cd8	723	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata	4:77faf76e3cd8	724	}
cparata	4:77faf76e3cd8	725	if (ret == 0) {
cparata	4:77faf76e3cd8	726	ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
cparata	4:77faf76e3cd8	727	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata	4:77faf76e3cd8	728	}
cparata	4:77faf76e3cd8	729	return ret;
cparata	0:6d69e896ce38	730	}
cparata	0:6d69e896ce38	731
cparata	0:6d69e896ce38	732	/**
cparata	0:6d69e896ce38	733	* @brief Accelerometer power mode.[get]
cparata	0:6d69e896ce38	734	*
cparata	0:6d69e896ce38	735	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	736	* @param val Get the values of xl_hm_mode in reg CTRL6_C
cparata	0:6d69e896ce38	737	*
cparata	0:6d69e896ce38	738	*/
cparata	0:6d69e896ce38	739	int32_t lsm6dso_xl_power_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	740	lsm6dso_xl_hm_mode_t *val)
cparata	0:6d69e896ce38	741	{
cparata	4:77faf76e3cd8	742	lsm6dso_ctrl5_c_t ctrl5_c;
cparata	4:77faf76e3cd8	743	lsm6dso_ctrl6_c_t ctrl6_c;
cparata	4:77faf76e3cd8	744	int32_t ret;
cparata	4:77faf76e3cd8	745
cparata	4:77faf76e3cd8	746	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata	4:77faf76e3cd8	747	if (ret == 0) {
cparata	4:77faf76e3cd8	748	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata	4:77faf76e3cd8	749	switch ( (ctrl5_c.xl_ulp_en << 1) \| ctrl6_c.xl_hm_mode) {
cparata	4:77faf76e3cd8	750	case LSM6DSO_HIGH_PERFORMANCE_MD:
cparata	4:77faf76e3cd8	751	*val = LSM6DSO_HIGH_PERFORMANCE_MD;
cparata	4:77faf76e3cd8	752	break;
cparata	4:77faf76e3cd8	753	case LSM6DSO_LOW_NORMAL_POWER_MD:
cparata	4:77faf76e3cd8	754	*val = LSM6DSO_LOW_NORMAL_POWER_MD;
cparata	4:77faf76e3cd8	755	break;
cparata	4:77faf76e3cd8	756	case LSM6DSO_ULTRA_LOW_POWER_MD:
cparata	4:77faf76e3cd8	757	*val = LSM6DSO_ULTRA_LOW_POWER_MD;
cparata	4:77faf76e3cd8	758	break;
cparata	4:77faf76e3cd8	759	default:
cparata	4:77faf76e3cd8	760	*val = LSM6DSO_HIGH_PERFORMANCE_MD;
cparata	4:77faf76e3cd8	761	break;
cparata	3:4274d9103f1d	762	}
cparata	4:77faf76e3cd8	763	}
cparata	4:77faf76e3cd8	764	return ret;
cparata	0:6d69e896ce38	765	}
cparata	0:6d69e896ce38	766
cparata	0:6d69e896ce38	767	/**
cparata	0:6d69e896ce38	768	* @brief Operating mode for gyroscope.[set]
cparata	0:6d69e896ce38	769	*
cparata	0:6d69e896ce38	770	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	771	* @param val change the values of g_hm_mode in reg CTRL7_G
cparata	0:6d69e896ce38	772	*
cparata	0:6d69e896ce38	773	*/
cparata	0:6d69e896ce38	774	int32_t lsm6dso_gy_power_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	775	lsm6dso_g_hm_mode_t val)
cparata	0:6d69e896ce38	776	{
cparata	4:77faf76e3cd8	777	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	778	int32_t ret;
cparata	4:77faf76e3cd8	779
cparata	4:77faf76e3cd8	780	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	781	if (ret == 0) {
cparata	4:77faf76e3cd8	782	reg.g_hm_mode = (uint8_t)val;
cparata	4:77faf76e3cd8	783	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	784	}
cparata	4:77faf76e3cd8	785	return ret;
cparata	0:6d69e896ce38	786	}
cparata	0:6d69e896ce38	787
cparata	0:6d69e896ce38	788	/**
cparata	0:6d69e896ce38	789	* @brief Operating mode for gyroscope.[get]
cparata	0:6d69e896ce38	790	*
cparata	0:6d69e896ce38	791	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	792	* @param val Get the values of g_hm_mode in reg CTRL7_G
cparata	0:6d69e896ce38	793	*
cparata	0:6d69e896ce38	794	*/
cparata	0:6d69e896ce38	795	int32_t lsm6dso_gy_power_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	796	lsm6dso_g_hm_mode_t *val)
cparata	0:6d69e896ce38	797	{
cparata	4:77faf76e3cd8	798	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	799	int32_t ret;
cparata	4:77faf76e3cd8	800
cparata	4:77faf76e3cd8	801	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	802	switch (reg.g_hm_mode) {
cparata	4:77faf76e3cd8	803	case LSM6DSO_GY_HIGH_PERFORMANCE:
cparata	4:77faf76e3cd8	804	*val = LSM6DSO_GY_HIGH_PERFORMANCE;
cparata	4:77faf76e3cd8	805	break;
cparata	4:77faf76e3cd8	806	case LSM6DSO_GY_NORMAL:
cparata	4:77faf76e3cd8	807	*val = LSM6DSO_GY_NORMAL;
cparata	4:77faf76e3cd8	808	break;
cparata	4:77faf76e3cd8	809	default:
cparata	4:77faf76e3cd8	810	*val = LSM6DSO_GY_HIGH_PERFORMANCE;
cparata	4:77faf76e3cd8	811	break;
cparata	4:77faf76e3cd8	812	}
cparata	4:77faf76e3cd8	813	return ret;
cparata	0:6d69e896ce38	814	}
cparata	0:6d69e896ce38	815
cparata	0:6d69e896ce38	816	/**
cparata	0:6d69e896ce38	817	* @brief The STATUS_REG register is read by the primary interface.[get]
cparata	0:6d69e896ce38	818	*
cparata	0:6d69e896ce38	819	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	820	* @param val register STATUS_REG
cparata	0:6d69e896ce38	821	*
cparata	0:6d69e896ce38	822	*/
cparata	0:6d69e896ce38	823	int32_t lsm6dso_status_reg_get(lsm6dso_ctx_t ctx, lsm6dso_status_reg_t val)
cparata	0:6d69e896ce38	824	{
cparata	4:77faf76e3cd8	825	int32_t ret;
cparata	4:77faf76e3cd8	826	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*) val, 1);
cparata	4:77faf76e3cd8	827	return ret;
cparata	0:6d69e896ce38	828	}
cparata	0:6d69e896ce38	829
cparata	0:6d69e896ce38	830	/**
cparata	0:6d69e896ce38	831	* @brief Accelerometer new data available.[get]
cparata	0:6d69e896ce38	832	*
cparata	0:6d69e896ce38	833	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	834	* @param val change the values of xlda in reg STATUS_REG
cparata	0:6d69e896ce38	835	*
cparata	0:6d69e896ce38	836	*/
cparata	0:6d69e896ce38	837	int32_t lsm6dso_xl_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	838	{
cparata	4:77faf76e3cd8	839	lsm6dso_status_reg_t reg;
cparata	4:77faf76e3cd8	840	int32_t ret;
cparata	4:77faf76e3cd8	841
cparata	4:77faf76e3cd8	842	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	843	*val = reg.xlda;
cparata	4:77faf76e3cd8	844
cparata	4:77faf76e3cd8	845	return ret;
cparata	0:6d69e896ce38	846	}
cparata	0:6d69e896ce38	847
cparata	0:6d69e896ce38	848	/**
cparata	0:6d69e896ce38	849	* @brief Gyroscope new data available.[get]
cparata	0:6d69e896ce38	850	*
cparata	0:6d69e896ce38	851	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	852	* @param val change the values of gda in reg STATUS_REG
cparata	0:6d69e896ce38	853	*
cparata	0:6d69e896ce38	854	*/
cparata	0:6d69e896ce38	855	int32_t lsm6dso_gy_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	856	{
cparata	4:77faf76e3cd8	857	lsm6dso_status_reg_t reg;
cparata	4:77faf76e3cd8	858	int32_t ret;
cparata	4:77faf76e3cd8	859
cparata	4:77faf76e3cd8	860	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	861	*val = reg.gda;
cparata	4:77faf76e3cd8	862
cparata	4:77faf76e3cd8	863	return ret;
cparata	0:6d69e896ce38	864	}
cparata	0:6d69e896ce38	865
cparata	0:6d69e896ce38	866	/**
cparata	0:6d69e896ce38	867	* @brief Temperature new data available.[get]
cparata	0:6d69e896ce38	868	*
cparata	0:6d69e896ce38	869	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	870	* @param val change the values of tda in reg STATUS_REG
cparata	0:6d69e896ce38	871	*
cparata	0:6d69e896ce38	872	*/
cparata	0:6d69e896ce38	873	int32_t lsm6dso_temp_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	874	{
cparata	4:77faf76e3cd8	875	lsm6dso_status_reg_t reg;
cparata	4:77faf76e3cd8	876	int32_t ret;
cparata	4:77faf76e3cd8	877
cparata	4:77faf76e3cd8	878	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	879	*val = reg.tda;
cparata	4:77faf76e3cd8	880
cparata	4:77faf76e3cd8	881	return ret;
cparata	0:6d69e896ce38	882	}
cparata	0:6d69e896ce38	883
cparata	0:6d69e896ce38	884	/**
cparata	0:6d69e896ce38	885	* @brief Accelerometer X-axis user offset correction expressed in
cparata	0:6d69e896ce38	886	* two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	887	* The value must be in the range [-127 127].[set]
cparata	0:6d69e896ce38	888	*
cparata	0:6d69e896ce38	889	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	890	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	891	*
cparata	0:6d69e896ce38	892	*/
cparata	0:6d69e896ce38	893	int32_t lsm6dso_xl_usr_offset_x_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	894	{
cparata	4:77faf76e3cd8	895	int32_t ret;
cparata	4:77faf76e3cd8	896	ret = lsm6dso_write_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
cparata	4:77faf76e3cd8	897	return ret;
cparata	0:6d69e896ce38	898	}
cparata	0:6d69e896ce38	899
cparata	0:6d69e896ce38	900	/**
cparata	0:6d69e896ce38	901	* @brief Accelerometer X-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	902	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	903	* The value must be in the range [-127 127].[get]
cparata	0:6d69e896ce38	904	*
cparata	0:6d69e896ce38	905	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	906	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	907	*
cparata	0:6d69e896ce38	908	*/
cparata	0:6d69e896ce38	909	int32_t lsm6dso_xl_usr_offset_x_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	910	{
cparata	4:77faf76e3cd8	911	int32_t ret;
cparata	4:77faf76e3cd8	912	ret = lsm6dso_read_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
cparata	4:77faf76e3cd8	913	return ret;
cparata	0:6d69e896ce38	914	}
cparata	0:6d69e896ce38	915
cparata	0:6d69e896ce38	916	/**
cparata	0:6d69e896ce38	917	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	918	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	919	* The value must be in the range [-127 127].[set]
cparata	0:6d69e896ce38	920	*
cparata	0:6d69e896ce38	921	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	922	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	923	*
cparata	0:6d69e896ce38	924	*/
cparata	0:6d69e896ce38	925	int32_t lsm6dso_xl_usr_offset_y_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	926	{
cparata	4:77faf76e3cd8	927	int32_t ret;
cparata	4:77faf76e3cd8	928	ret = lsm6dso_write_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
cparata	4:77faf76e3cd8	929	return ret;
cparata	0:6d69e896ce38	930	}
cparata	0:6d69e896ce38	931
cparata	0:6d69e896ce38	932	/**
cparata	0:6d69e896ce38	933	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	934	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	935	* The value must be in the range [-127 127].[get]
cparata	0:6d69e896ce38	936	*
cparata	0:6d69e896ce38	937	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	938	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	939	*
cparata	0:6d69e896ce38	940	*/
cparata	0:6d69e896ce38	941	int32_t lsm6dso_xl_usr_offset_y_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	942	{
cparata	4:77faf76e3cd8	943	int32_t ret;
cparata	4:77faf76e3cd8	944	ret = lsm6dso_read_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
cparata	4:77faf76e3cd8	945	return ret;
cparata	0:6d69e896ce38	946	}
cparata	0:6d69e896ce38	947
cparata	0:6d69e896ce38	948	/**
cparata	0:6d69e896ce38	949	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	950	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	951	* The value must be in the range [-127 127].[set]
cparata	0:6d69e896ce38	952	*
cparata	0:6d69e896ce38	953	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	954	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	955	*
cparata	0:6d69e896ce38	956	*/
cparata	0:6d69e896ce38	957	int32_t lsm6dso_xl_usr_offset_z_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	958	{
cparata	4:77faf76e3cd8	959	int32_t ret;
cparata	4:77faf76e3cd8	960	ret = lsm6dso_write_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
cparata	4:77faf76e3cd8	961	return ret;
cparata	0:6d69e896ce38	962	}
cparata	0:6d69e896ce38	963
cparata	0:6d69e896ce38	964	/**
cparata	0:6d69e896ce38	965	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	966	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	967	* The value must be in the range [-127 127].[get]
cparata	0:6d69e896ce38	968	*
cparata	0:6d69e896ce38	969	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	970	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	971	*
cparata	0:6d69e896ce38	972	*/
cparata	0:6d69e896ce38	973	int32_t lsm6dso_xl_usr_offset_z_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	974	{
cparata	4:77faf76e3cd8	975	int32_t ret;
cparata	4:77faf76e3cd8	976	ret = lsm6dso_read_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
cparata	4:77faf76e3cd8	977	return ret;
cparata	0:6d69e896ce38	978	}
cparata	0:6d69e896ce38	979
cparata	0:6d69e896ce38	980	/**
cparata	0:6d69e896ce38	981	* @brief Enables user offset on out.[set]
cparata	0:6d69e896ce38	982	*
cparata	0:6d69e896ce38	983	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	984	* @param val change the values of usr_off_on_out in reg CTRL7_G
cparata	0:6d69e896ce38	985	*
cparata	0:6d69e896ce38	986	*/
cparata	0:6d69e896ce38	987	int32_t lsm6dso_xl_usr_offset_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	988	{
cparata	4:77faf76e3cd8	989	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	990	int32_t ret;
cparata	4:77faf76e3cd8	991
cparata	4:77faf76e3cd8	992	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	993	if (ret == 0) {
cparata	4:77faf76e3cd8	994	reg.usr_off_on_out = val;
cparata	4:77faf76e3cd8	995	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	996	}
cparata	4:77faf76e3cd8	997	return ret;
cparata	0:6d69e896ce38	998	}
cparata	0:6d69e896ce38	999
cparata	0:6d69e896ce38	1000	/**
cparata	0:6d69e896ce38	1001	* @brief User offset on out flag.[get]
cparata	0:6d69e896ce38	1002	*
cparata	0:6d69e896ce38	1003	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1004	* @param val values of usr_off_on_out in reg CTRL7_G
cparata	0:6d69e896ce38	1005	*
cparata	0:6d69e896ce38	1006	*/
cparata	0:6d69e896ce38	1007	int32_t lsm6dso_xl_usr_offset_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1008	{
cparata	4:77faf76e3cd8	1009	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	1010	int32_t ret;
cparata	4:77faf76e3cd8	1011
cparata	4:77faf76e3cd8	1012	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1013	*val = reg.usr_off_on_out;
cparata	4:77faf76e3cd8	1014
cparata	4:77faf76e3cd8	1015	return ret;
cparata	0:6d69e896ce38	1016	}
cparata	0:6d69e896ce38	1017
cparata	0:6d69e896ce38	1018	/**
cparata	0:6d69e896ce38	1019	* @}
cparata	0:6d69e896ce38	1020	*
cparata	0:6d69e896ce38	1021	*/
cparata	0:6d69e896ce38	1022
cparata	0:6d69e896ce38	1023	/**
cparata	0:6d69e896ce38	1024	* @defgroup LSM6DSO_Timestamp
cparata	0:6d69e896ce38	1025	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	1026	* timestamp generation.
cparata	0:6d69e896ce38	1027	* @{
cparata	0:6d69e896ce38	1028	*
cparata	4:77faf76e3cd8	1029	*/
cparata	4:77faf76e3cd8	1030
cparata	4:77faf76e3cd8	1031	/**
cparata	4:77faf76e3cd8	1032	* @brief Reset timestamp counter.[set]
cparata	4:77faf76e3cd8	1033	*
cparata	4:77faf76e3cd8	1034	* @param ctx Read / write interface definitions.(ptr)
cparata	4:77faf76e3cd8	1035	* @retval Interface status (MANDATORY: return 0 -> no Error).
cparata	4:77faf76e3cd8	1036	*
cparata	4:77faf76e3cd8	1037	*/
cparata	4:77faf76e3cd8	1038	int32_t lsm6dso_timestamp_rst(lsm6dso_ctx_t *ctx)
cparata	4:77faf76e3cd8	1039	{
cparata	4:77faf76e3cd8	1040	uint8_t rst_val = 0xAA;
cparata	4:77faf76e3cd8	1041
cparata	4:77faf76e3cd8	1042	return lsm6dso_write_reg(ctx, LSM6DSO_TIMESTAMP2, &rst_val, 1);
cparata	4:77faf76e3cd8	1043	}
cparata	0:6d69e896ce38	1044
cparata	0:6d69e896ce38	1045	/**
cparata	0:6d69e896ce38	1046	* @brief Enables timestamp counter.[set]
cparata	0:6d69e896ce38	1047	*
cparata	0:6d69e896ce38	1048	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1049	* @param val change the values of timestamp_en in reg CTRL10_C
cparata	0:6d69e896ce38	1050	*
cparata	0:6d69e896ce38	1051	*/
cparata	0:6d69e896ce38	1052	int32_t lsm6dso_timestamp_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1053	{
cparata	4:77faf76e3cd8	1054	lsm6dso_ctrl10_c_t reg;
cparata	4:77faf76e3cd8	1055	int32_t ret;
cparata	4:77faf76e3cd8	1056
cparata	4:77faf76e3cd8	1057	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1058	if (ret == 0) {
cparata	4:77faf76e3cd8	1059	reg.timestamp_en = val;
cparata	4:77faf76e3cd8	1060	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1061	}
cparata	4:77faf76e3cd8	1062	return ret;
cparata	0:6d69e896ce38	1063	}
cparata	0:6d69e896ce38	1064
cparata	0:6d69e896ce38	1065	/**
cparata	0:6d69e896ce38	1066	* @brief Enables timestamp counter.[get]
cparata	0:6d69e896ce38	1067	*
cparata	0:6d69e896ce38	1068	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1069	* @param val change the values of timestamp_en in reg CTRL10_C
cparata	0:6d69e896ce38	1070	*
cparata	0:6d69e896ce38	1071	*/
cparata	0:6d69e896ce38	1072	int32_t lsm6dso_timestamp_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1073	{
cparata	4:77faf76e3cd8	1074	lsm6dso_ctrl10_c_t reg;
cparata	4:77faf76e3cd8	1075	int32_t ret;
cparata	4:77faf76e3cd8	1076
cparata	4:77faf76e3cd8	1077	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1078	*val = reg.timestamp_en;
cparata	4:77faf76e3cd8	1079
cparata	4:77faf76e3cd8	1080	return ret;
cparata	0:6d69e896ce38	1081	}
cparata	0:6d69e896ce38	1082
cparata	0:6d69e896ce38	1083	/**
cparata	0:6d69e896ce38	1084	* @brief Timestamp first data output register (r).
cparata	0:6d69e896ce38	1085	* The value is expressed as a 32-bit word and the bit
cparata	0:6d69e896ce38	1086	* resolution is 25 μs.[get]
cparata	0:6d69e896ce38	1087	*
cparata	0:6d69e896ce38	1088	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1089	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1090	*
cparata	0:6d69e896ce38	1091	*/
cparata	0:6d69e896ce38	1092	int32_t lsm6dso_timestamp_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1093	{
cparata	4:77faf76e3cd8	1094	int32_t ret;
cparata	4:77faf76e3cd8	1095	ret = lsm6dso_read_reg(ctx, LSM6DSO_TIMESTAMP0, buff, 4);
cparata	4:77faf76e3cd8	1096	return ret;
cparata	0:6d69e896ce38	1097	}
cparata	0:6d69e896ce38	1098
cparata	0:6d69e896ce38	1099	/**
cparata	0:6d69e896ce38	1100	* @}
cparata	0:6d69e896ce38	1101	*
cparata	0:6d69e896ce38	1102	*/
cparata	0:6d69e896ce38	1103
cparata	0:6d69e896ce38	1104	/**
cparata	0:6d69e896ce38	1105	* @defgroup LSM6DSO_Data output
cparata	0:6d69e896ce38	1106	* @brief This section groups all the data output functions.
cparata	0:6d69e896ce38	1107	* @{
cparata	0:6d69e896ce38	1108	*
cparata	0:6d69e896ce38	1109	*/
cparata	0:6d69e896ce38	1110
cparata	0:6d69e896ce38	1111	/**
cparata	0:6d69e896ce38	1112	* @brief Circular burst-mode (rounding) read of the output
cparata	0:6d69e896ce38	1113	* registers.[set]
cparata	0:6d69e896ce38	1114	*
cparata	0:6d69e896ce38	1115	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1116	* @param val change the values of rounding in reg CTRL5_C
cparata	0:6d69e896ce38	1117	*
cparata	0:6d69e896ce38	1118	*/
cparata	0:6d69e896ce38	1119	int32_t lsm6dso_rounding_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1120	lsm6dso_rounding_t val)
cparata	0:6d69e896ce38	1121	{
cparata	4:77faf76e3cd8	1122	lsm6dso_ctrl5_c_t reg;
cparata	4:77faf76e3cd8	1123	int32_t ret;
cparata	4:77faf76e3cd8	1124
cparata	4:77faf76e3cd8	1125	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1126	if (ret == 0) {
cparata	4:77faf76e3cd8	1127	reg.rounding = (uint8_t)val;
cparata	4:77faf76e3cd8	1128	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1129	}
cparata	4:77faf76e3cd8	1130	return ret;
cparata	0:6d69e896ce38	1131	}
cparata	0:6d69e896ce38	1132
cparata	0:6d69e896ce38	1133	/**
cparata	0:6d69e896ce38	1134	* @brief Gyroscope UI chain full-scale selection.[get]
cparata	0:6d69e896ce38	1135	*
cparata	0:6d69e896ce38	1136	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1137	* @param val Get the values of rounding in reg CTRL5_C
cparata	0:6d69e896ce38	1138	*
cparata	0:6d69e896ce38	1139	*/
cparata	0:6d69e896ce38	1140	int32_t lsm6dso_rounding_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1141	lsm6dso_rounding_t *val)
cparata	0:6d69e896ce38	1142	{
cparata	4:77faf76e3cd8	1143	lsm6dso_ctrl5_c_t reg;
cparata	4:77faf76e3cd8	1144	int32_t ret;
cparata	4:77faf76e3cd8	1145
cparata	4:77faf76e3cd8	1146	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1147	switch (reg.rounding) {
cparata	4:77faf76e3cd8	1148	case LSM6DSO_NO_ROUND:
cparata	4:77faf76e3cd8	1149	*val = LSM6DSO_NO_ROUND;
cparata	4:77faf76e3cd8	1150	break;
cparata	4:77faf76e3cd8	1151	case LSM6DSO_ROUND_XL:
cparata	4:77faf76e3cd8	1152	*val = LSM6DSO_ROUND_XL;
cparata	4:77faf76e3cd8	1153	break;
cparata	4:77faf76e3cd8	1154	case LSM6DSO_ROUND_GY:
cparata	4:77faf76e3cd8	1155	*val = LSM6DSO_ROUND_GY;
cparata	4:77faf76e3cd8	1156	break;
cparata	4:77faf76e3cd8	1157	case LSM6DSO_ROUND_GY_XL:
cparata	4:77faf76e3cd8	1158	*val = LSM6DSO_ROUND_GY_XL;
cparata	4:77faf76e3cd8	1159	break;
cparata	4:77faf76e3cd8	1160	default:
cparata	4:77faf76e3cd8	1161	*val = LSM6DSO_NO_ROUND;
cparata	4:77faf76e3cd8	1162	break;
cparata	4:77faf76e3cd8	1163	}
cparata	4:77faf76e3cd8	1164	return ret;
cparata	0:6d69e896ce38	1165	}
cparata	0:6d69e896ce38	1166
cparata	0:6d69e896ce38	1167	/**
cparata	0:6d69e896ce38	1168	* @brief Temperature data output register (r).
cparata	0:6d69e896ce38	1169	* L and H registers together express a 16-bit word in two’s
cparata	0:6d69e896ce38	1170	* complement.[get]
cparata	0:6d69e896ce38	1171	*
cparata	0:6d69e896ce38	1172	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1173	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1174	*
cparata	0:6d69e896ce38	1175	*/
cparata	0:6d69e896ce38	1176	int32_t lsm6dso_temperature_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1177	{
cparata	4:77faf76e3cd8	1178	int32_t ret;
cparata	4:77faf76e3cd8	1179	ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 2);
cparata	4:77faf76e3cd8	1180	return ret;
cparata	0:6d69e896ce38	1181	}
cparata	0:6d69e896ce38	1182
cparata	0:6d69e896ce38	1183	/**
cparata	0:6d69e896ce38	1184	* @brief Angular rate sensor. The value is expressed as a 16-bit
cparata	0:6d69e896ce38	1185	* word in two’s complement.[get]
cparata	0:6d69e896ce38	1186	*
cparata	0:6d69e896ce38	1187	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1188	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1189	*
cparata	0:6d69e896ce38	1190	*/
cparata	0:6d69e896ce38	1191	int32_t lsm6dso_angular_rate_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1192	{
cparata	4:77faf76e3cd8	1193	int32_t ret;
cparata	4:77faf76e3cd8	1194	ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_G, buff, 6);
cparata	4:77faf76e3cd8	1195	return ret;
cparata	0:6d69e896ce38	1196	}
cparata	0:6d69e896ce38	1197
cparata	0:6d69e896ce38	1198	/**
cparata	0:6d69e896ce38	1199	* @brief Linear acceleration output register.
cparata	0:6d69e896ce38	1200	* The value is expressed as a 16-bit word in two’s complement.[get]
cparata	0:6d69e896ce38	1201	*
cparata	0:6d69e896ce38	1202	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1203	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1204	*
cparata	0:6d69e896ce38	1205	*/
cparata	0:6d69e896ce38	1206	int32_t lsm6dso_acceleration_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1207	{
cparata	4:77faf76e3cd8	1208	int32_t ret;
cparata	4:77faf76e3cd8	1209	ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_A, buff, 6);
cparata	4:77faf76e3cd8	1210	return ret;
cparata	0:6d69e896ce38	1211	}
cparata	0:6d69e896ce38	1212
cparata	0:6d69e896ce38	1213	/**
cparata	0:6d69e896ce38	1214	* @brief FIFO data output [get]
cparata	0:6d69e896ce38	1215	*
cparata	0:6d69e896ce38	1216	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1217	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1218	*
cparata	0:6d69e896ce38	1219	*/
cparata	0:6d69e896ce38	1220	int32_t lsm6dso_fifo_out_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1221	{
cparata	4:77faf76e3cd8	1222	int32_t ret;
cparata	4:77faf76e3cd8	1223	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_X_L, buff, 6);
cparata	4:77faf76e3cd8	1224	return ret;
cparata	0:6d69e896ce38	1225	}
cparata	0:6d69e896ce38	1226
cparata	0:6d69e896ce38	1227	/**
cparata	0:6d69e896ce38	1228	* @brief Step counter output register.[get]
cparata	0:6d69e896ce38	1229	*
cparata	0:6d69e896ce38	1230	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1231	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1232	*
cparata	0:6d69e896ce38	1233	*/
cparata	0:6d69e896ce38	1234	int32_t lsm6dso_number_of_steps_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1235	{
cparata	4:77faf76e3cd8	1236	int32_t ret;
cparata	4:77faf76e3cd8	1237
cparata	4:77faf76e3cd8	1238	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	1239	if (ret == 0) {
cparata	4:77faf76e3cd8	1240	ret = lsm6dso_read_reg(ctx, LSM6DSO_STEP_COUNTER_L, buff, 2);
cparata	4:77faf76e3cd8	1241	}
cparata	4:77faf76e3cd8	1242	if (ret == 0) {
cparata	4:77faf76e3cd8	1243	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	1244	}
cparata	4:77faf76e3cd8	1245	return ret;
cparata	0:6d69e896ce38	1246	}
cparata	0:6d69e896ce38	1247
cparata	0:6d69e896ce38	1248	/**
cparata	0:6d69e896ce38	1249	* @brief Reset step counter register.[get]
cparata	0:6d69e896ce38	1250	*
cparata	0:6d69e896ce38	1251	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1252	*
cparata	0:6d69e896ce38	1253	*/
cparata	0:6d69e896ce38	1254	int32_t lsm6dso_steps_reset(lsm6dso_ctx_t *ctx)
cparata	0:6d69e896ce38	1255	{
cparata	4:77faf76e3cd8	1256	lsm6dso_emb_func_src_t reg;
cparata	4:77faf76e3cd8	1257	int32_t ret;
cparata	4:77faf76e3cd8	1258
cparata	4:77faf76e3cd8	1259	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	1260	if (ret == 0) {
cparata	4:77faf76e3cd8	1261	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1262	}
cparata	4:77faf76e3cd8	1263	if (ret == 0) {
cparata	4:77faf76e3cd8	1264	reg.pedo_rst_step = PROPERTY_ENABLE;
cparata	4:77faf76e3cd8	1265	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1266	}
cparata	4:77faf76e3cd8	1267	if (ret == 0) {
cparata	4:77faf76e3cd8	1268	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	1269	}
cparata	4:77faf76e3cd8	1270	return ret;
cparata	0:6d69e896ce38	1271	}
cparata	0:6d69e896ce38	1272
cparata	0:6d69e896ce38	1273	/**
cparata	0:6d69e896ce38	1274	* @}
cparata	0:6d69e896ce38	1275	*
cparata	0:6d69e896ce38	1276	*/
cparata	0:6d69e896ce38	1277
cparata	0:6d69e896ce38	1278	/**
cparata	0:6d69e896ce38	1279	* @defgroup LSM6DSO_common
cparata	0:6d69e896ce38	1280	* @brief This section groups common usefull functions.
cparata	0:6d69e896ce38	1281	* @{
cparata	0:6d69e896ce38	1282	*
cparata	0:6d69e896ce38	1283	*/
cparata	0:6d69e896ce38	1284
cparata	0:6d69e896ce38	1285	/**
cparata	0:6d69e896ce38	1286	* @brief Difference in percentage of the effective ODR(and timestamp rate)
cparata	0:6d69e896ce38	1287	* with respect to the typical.
cparata	0:6d69e896ce38	1288	* Step: 0.15%. 8-bit format, 2's complement.[set]
cparata	0:6d69e896ce38	1289	*
cparata	0:6d69e896ce38	1290	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1291	* @param val change the values of freq_fine in reg
cparata	0:6d69e896ce38	1292	* INTERNAL_FREQ_FINE
cparata	0:6d69e896ce38	1293	*
cparata	0:6d69e896ce38	1294	*/
cparata	0:6d69e896ce38	1295	int32_t lsm6dso_odr_cal_reg_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1296	{
cparata	4:77faf76e3cd8	1297	lsm6dso_internal_freq_fine_t reg;
cparata	4:77faf76e3cd8	1298	int32_t ret;
cparata	4:77faf76e3cd8	1299
cparata	4:77faf76e3cd8	1300	ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1301	if (ret == 0) {
cparata	4:77faf76e3cd8	1302	reg.freq_fine = val;
cparata	4:77faf76e3cd8	1303	ret = lsm6dso_write_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
cparata	4:77faf76e3cd8	1304	(uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1305	}
cparata	4:77faf76e3cd8	1306	return ret;
cparata	0:6d69e896ce38	1307	}
cparata	0:6d69e896ce38	1308
cparata	0:6d69e896ce38	1309	/**
cparata	0:6d69e896ce38	1310	* @brief Difference in percentage of the effective ODR(and timestamp rate)
cparata	0:6d69e896ce38	1311	* with respect to the typical.
cparata	0:6d69e896ce38	1312	* Step: 0.15%. 8-bit format, 2's complement.[get]
cparata	0:6d69e896ce38	1313	*
cparata	0:6d69e896ce38	1314	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1315	* @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
cparata	0:6d69e896ce38	1316	*
cparata	0:6d69e896ce38	1317	*/
cparata	0:6d69e896ce38	1318	int32_t lsm6dso_odr_cal_reg_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1319	{
cparata	4:77faf76e3cd8	1320	lsm6dso_internal_freq_fine_t reg;
cparata	4:77faf76e3cd8	1321	int32_t ret;
cparata	4:77faf76e3cd8	1322
cparata	4:77faf76e3cd8	1323	ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1324	*val = reg.freq_fine;
cparata	4:77faf76e3cd8	1325
cparata	4:77faf76e3cd8	1326	return ret;
cparata	0:6d69e896ce38	1327	}
cparata	0:6d69e896ce38	1328
cparata	0:6d69e896ce38	1329
cparata	0:6d69e896ce38	1330	/**
cparata	0:6d69e896ce38	1331	* @brief Enable access to the embedded functions/sensor
cparata	0:6d69e896ce38	1332	* hub configuration registers.[set]
cparata	0:6d69e896ce38	1333	*
cparata	0:6d69e896ce38	1334	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1335	* @param val change the values of reg_access in
cparata	0:6d69e896ce38	1336	* reg FUNC_CFG_ACCESS
cparata	0:6d69e896ce38	1337	*
cparata	0:6d69e896ce38	1338	*/
cparata	0:6d69e896ce38	1339	int32_t lsm6dso_mem_bank_set(lsm6dso_ctx_t *ctx, lsm6dso_reg_access_t val)
cparata	0:6d69e896ce38	1340	{
cparata	4:77faf76e3cd8	1341	lsm6dso_func_cfg_access_t reg;
cparata	4:77faf76e3cd8	1342	int32_t ret;
cparata	4:77faf76e3cd8	1343
cparata	4:77faf76e3cd8	1344	ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1345	if (ret == 0) {
cparata	4:77faf76e3cd8	1346	reg.reg_access = (uint8_t)val;
cparata	4:77faf76e3cd8	1347	ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1348	}
cparata	4:77faf76e3cd8	1349	return ret;
cparata	0:6d69e896ce38	1350	}
cparata	0:6d69e896ce38	1351
cparata	0:6d69e896ce38	1352	/**
cparata	0:6d69e896ce38	1353	* @brief Enable access to the embedded functions/sensor
cparata	0:6d69e896ce38	1354	* hub configuration registers.[get]
cparata	0:6d69e896ce38	1355	*
cparata	0:6d69e896ce38	1356	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1357	* @param val Get the values of reg_access in
cparata	0:6d69e896ce38	1358	* reg FUNC_CFG_ACCESS
cparata	0:6d69e896ce38	1359	*
cparata	0:6d69e896ce38	1360	*/
cparata	0:6d69e896ce38	1361	int32_t lsm6dso_mem_bank_get(lsm6dso_ctx_t ctx, lsm6dso_reg_access_t val)
cparata	0:6d69e896ce38	1362	{
cparata	4:77faf76e3cd8	1363	lsm6dso_func_cfg_access_t reg;
cparata	4:77faf76e3cd8	1364	int32_t ret;
cparata	4:77faf76e3cd8	1365
cparata	4:77faf76e3cd8	1366	ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1367	switch (reg.reg_access) {
cparata	4:77faf76e3cd8	1368	case LSM6DSO_USER_BANK:
cparata	4:77faf76e3cd8	1369	*val = LSM6DSO_USER_BANK;
cparata	4:77faf76e3cd8	1370	break;
cparata	4:77faf76e3cd8	1371	case LSM6DSO_SENSOR_HUB_BANK:
cparata	4:77faf76e3cd8	1372	*val = LSM6DSO_SENSOR_HUB_BANK;
cparata	4:77faf76e3cd8	1373	break;
cparata	4:77faf76e3cd8	1374	case LSM6DSO_EMBEDDED_FUNC_BANK:
cparata	4:77faf76e3cd8	1375	*val = LSM6DSO_EMBEDDED_FUNC_BANK;
cparata	4:77faf76e3cd8	1376	break;
cparata	4:77faf76e3cd8	1377	default:
cparata	4:77faf76e3cd8	1378	*val = LSM6DSO_USER_BANK;
cparata	4:77faf76e3cd8	1379	break;
cparata	4:77faf76e3cd8	1380	}
cparata	4:77faf76e3cd8	1381	return ret;
cparata	0:6d69e896ce38	1382	}
cparata	0:6d69e896ce38	1383
cparata	0:6d69e896ce38	1384	/**
cparata	0:6d69e896ce38	1385	* @brief Write a line(byte) in a page.[set]
cparata	0:6d69e896ce38	1386	*
cparata	0:6d69e896ce38	1387	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1388	* @param uint8_t address: page line address
cparata	0:6d69e896ce38	1389	* @param val value to write
cparata	0:6d69e896ce38	1390	*
cparata	0:6d69e896ce38	1391	*/
cparata	0:6d69e896ce38	1392	int32_t lsm6dso_ln_pg_write_byte(lsm6dso_ctx_t *ctx, uint16_t address,
cparata	0:6d69e896ce38	1393	uint8_t *val)
cparata	0:6d69e896ce38	1394	{
cparata	4:77faf76e3cd8	1395	lsm6dso_page_rw_t page_rw;
cparata	4:77faf76e3cd8	1396	lsm6dso_page_sel_t page_sel;
cparata	4:77faf76e3cd8	1397	lsm6dso_page_address_t page_address;
cparata	4:77faf76e3cd8	1398	int32_t ret;
cparata	4:77faf76e3cd8	1399
cparata	4:77faf76e3cd8	1400	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	1401
cparata	4:77faf76e3cd8	1402	if (ret == 0) {
cparata	4:77faf76e3cd8	1403	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1404	}
cparata	4:77faf76e3cd8	1405	if (ret == 0) {
cparata	4:77faf76e3cd8	1406	page_rw.page_rw = 0x02; /* page_write enable */
cparata	4:77faf76e3cd8	1407	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1408	}
cparata	4:77faf76e3cd8	1409	if (ret == 0) {
cparata	4:77faf76e3cd8	1410	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1411	}
cparata	4:77faf76e3cd8	1412
cparata	4:77faf76e3cd8	1413	if (ret == 0) {
cparata	4:77faf76e3cd8	1414	page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
cparata	4:77faf76e3cd8	1415	page_sel.not_used_01 = 1;
cparata	4:77faf76e3cd8	1416	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1417	}
cparata	4:77faf76e3cd8	1418	if (ret == 0) {
cparata	4:77faf76e3cd8	1419	page_address.page_addr = (uint8_t)address & 0xFFU;
cparata	4:77faf76e3cd8	1420	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
cparata	4:77faf76e3cd8	1421	(uint8_t*)&page_address, 1);
cparata	4:77faf76e3cd8	1422	}
cparata	4:77faf76e3cd8	1423	if (ret == 0) {
cparata	4:77faf76e3cd8	1424	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1);
cparata	4:77faf76e3cd8	1425	}
cparata	4:77faf76e3cd8	1426	if (ret == 0) {
cparata	4:77faf76e3cd8	1427	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1428	}
cparata	4:77faf76e3cd8	1429	if (ret == 0) {
cparata	4:77faf76e3cd8	1430	page_rw.page_rw = 0x00; /* page_write disable */
cparata	4:77faf76e3cd8	1431	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1432	}
cparata	4:77faf76e3cd8	1433	if (ret == 0) {
cparata	4:77faf76e3cd8	1434
cparata	4:77faf76e3cd8	1435	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	1436	}
cparata	4:77faf76e3cd8	1437	return ret;
cparata	0:6d69e896ce38	1438	}
cparata	0:6d69e896ce38	1439
cparata	0:6d69e896ce38	1440	/**
cparata	0:6d69e896ce38	1441	* @brief Write buffer in a page.[set]
cparata	0:6d69e896ce38	1442	*
cparata	0:6d69e896ce38	1443	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1444	* @param uint8_t address: page line address
cparata	0:6d69e896ce38	1445	* @param uint8_t *buf: buffer to write
cparata	0:6d69e896ce38	1446	* @param uint8_t len: buffer len
cparata	0:6d69e896ce38	1447	*
cparata	0:6d69e896ce38	1448	*/
cparata	0:6d69e896ce38	1449	int32_t lsm6dso_ln_pg_write(lsm6dso_ctx_t *ctx, uint16_t address,
cparata	0:6d69e896ce38	1450	uint8_t *buf, uint8_t len)
cparata	0:6d69e896ce38	1451	{
cparata	4:77faf76e3cd8	1452	lsm6dso_page_rw_t page_rw;
cparata	4:77faf76e3cd8	1453	lsm6dso_page_sel_t page_sel;
cparata	4:77faf76e3cd8	1454	lsm6dso_page_address_t page_address;
cparata	4:77faf76e3cd8	1455	uint16_t addr_pointed;
cparata	4:77faf76e3cd8	1456	int32_t ret;
cparata	4:77faf76e3cd8	1457	uint8_t i ;
cparata	4:77faf76e3cd8	1458
cparata	4:77faf76e3cd8	1459	addr_pointed = address;
cparata	4:77faf76e3cd8	1460
cparata	4:77faf76e3cd8	1461	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	1462	if (ret == 0) {
cparata	4:77faf76e3cd8	1463
cparata	4:77faf76e3cd8	1464	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1465	}
cparata	4:77faf76e3cd8	1466	if (ret == 0) {
cparata	4:77faf76e3cd8	1467	page_rw.page_rw = 0x02; /* page_write enable*/
cparata	4:77faf76e3cd8	1468	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1469	}
cparata	4:77faf76e3cd8	1470	if (ret == 0) {
cparata	4:77faf76e3cd8	1471	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1472	}
cparata	4:77faf76e3cd8	1473	if (ret == 0) {
cparata	4:77faf76e3cd8	1474	page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
cparata	4:77faf76e3cd8	1475	page_sel.not_used_01 = 1;
cparata	4:77faf76e3cd8	1476	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1477	}
cparata	4:77faf76e3cd8	1478	if (ret == 0) {
cparata	4:77faf76e3cd8	1479	page_address.page_addr = (uint8_t)(addr_pointed & 0x00FFU);
cparata	4:77faf76e3cd8	1480	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
cparata	4:77faf76e3cd8	1481	(uint8_t*)&page_address, 1);
cparata	4:77faf76e3cd8	1482	}
cparata	4:77faf76e3cd8	1483
cparata	4:77faf76e3cd8	1484	if (ret == 0) {
cparata	4:77faf76e3cd8	1485	for (i = 0; ( (i < len) && (ret == 0) ); i++) {
cparata	4:77faf76e3cd8	1486	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, &buf[i], 1);
cparata	4:77faf76e3cd8	1487	addr_pointed++;
cparata	4:77faf76e3cd8	1488	/* Check if page wrap */
cparata	4:77faf76e3cd8	1489	if ( ( (addr_pointed % 0x0100U) == 0x00U ) && (ret == 0) ) {
cparata	4:77faf76e3cd8	1490	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*)&page_sel, 1);
cparata	4:77faf76e3cd8	1491	if (ret == 0) {
cparata	4:77faf76e3cd8	1492	page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
cparata	4:77faf76e3cd8	1493	page_sel.not_used_01 = 1;
cparata	4:77faf76e3cd8	1494	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL,
cparata	4:77faf76e3cd8	1495	(uint8_t*)&page_sel, 1);
cparata	4:77faf76e3cd8	1496	}
cparata	4:77faf76e3cd8	1497	}
cparata	3:4274d9103f1d	1498	}
cparata	4:77faf76e3cd8	1499	page_sel.page_sel = 0;
cparata	4:77faf76e3cd8	1500	page_sel.not_used_01 = 1;
cparata	4:77faf76e3cd8	1501	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1502	}
cparata	4:77faf76e3cd8	1503	if (ret == 0) {
cparata	4:77faf76e3cd8	1504	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1505	}
cparata	4:77faf76e3cd8	1506	if (ret == 0) {
cparata	4:77faf76e3cd8	1507	page_rw.page_rw = 0x00; /* page_write disable */
cparata	4:77faf76e3cd8	1508	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1509	}
cparata	4:77faf76e3cd8	1510	if (ret == 0) {
cparata	4:77faf76e3cd8	1511	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	1512	}
cparata	4:77faf76e3cd8	1513	return ret;
cparata	0:6d69e896ce38	1514	}
cparata	0:6d69e896ce38	1515
cparata	0:6d69e896ce38	1516	/**
cparata	0:6d69e896ce38	1517	* @brief Read a line(byte) in a page.[get]
cparata	0:6d69e896ce38	1518	*
cparata	0:6d69e896ce38	1519	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1520	* @param uint8_t address: page line address
cparata	0:6d69e896ce38	1521	* @param val read value
cparata	0:6d69e896ce38	1522	*
cparata	0:6d69e896ce38	1523	*/
cparata	0:6d69e896ce38	1524	int32_t lsm6dso_ln_pg_read_byte(lsm6dso_ctx_t *ctx, uint16_t address,
cparata	0:6d69e896ce38	1525	uint8_t *val)
cparata	0:6d69e896ce38	1526	{
cparata	4:77faf76e3cd8	1527	lsm6dso_page_rw_t page_rw;
cparata	4:77faf76e3cd8	1528	lsm6dso_page_sel_t page_sel;
cparata	4:77faf76e3cd8	1529	lsm6dso_page_address_t page_address;
cparata	4:77faf76e3cd8	1530	int32_t ret;
cparata	4:77faf76e3cd8	1531
cparata	4:77faf76e3cd8	1532	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	1533	if (ret == 0) {
cparata	4:77faf76e3cd8	1534
cparata	4:77faf76e3cd8	1535	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1536	}
cparata	4:77faf76e3cd8	1537	if (ret == 0) {
cparata	4:77faf76e3cd8	1538	page_rw.page_rw = 0x01; /* page_read enable*/
cparata	4:77faf76e3cd8	1539	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1540	}
cparata	4:77faf76e3cd8	1541	if (ret == 0) {
cparata	4:77faf76e3cd8	1542
cparata	4:77faf76e3cd8	1543	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1544	}
cparata	4:77faf76e3cd8	1545	if (ret == 0) {
cparata	4:77faf76e3cd8	1546	page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
cparata	4:77faf76e3cd8	1547	page_sel.not_used_01 = 1;
cparata	4:77faf76e3cd8	1548	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1549	}
cparata	4:77faf76e3cd8	1550	if (ret == 0) {
cparata	4:77faf76e3cd8	1551	page_address.page_addr = (uint8_t)address & 0x00FFU;
cparata	4:77faf76e3cd8	1552	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
cparata	4:77faf76e3cd8	1553	(uint8_t*)&page_address, 1);
cparata	4:77faf76e3cd8	1554	}
cparata	4:77faf76e3cd8	1555	if (ret == 0) {
cparata	4:77faf76e3cd8	1556
cparata	4:77faf76e3cd8	1557	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1);
cparata	4:77faf76e3cd8	1558	}
cparata	4:77faf76e3cd8	1559	if (ret == 0) {
cparata	4:77faf76e3cd8	1560	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1561	}
cparata	4:77faf76e3cd8	1562	if (ret == 0) {
cparata	4:77faf76e3cd8	1563	page_rw.page_rw = 0x00; /* page_read disable */
cparata	4:77faf76e3cd8	1564	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1565	}
cparata	4:77faf76e3cd8	1566	if (ret == 0) {
cparata	4:77faf76e3cd8	1567	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	1568	}
cparata	4:77faf76e3cd8	1569
cparata	4:77faf76e3cd8	1570	return ret;
cparata	0:6d69e896ce38	1571	}
cparata	0:6d69e896ce38	1572
cparata	0:6d69e896ce38	1573	/**
cparata	0:6d69e896ce38	1574	* @brief Data-ready pulsed / letched mode.[set]
cparata	0:6d69e896ce38	1575	*
cparata	0:6d69e896ce38	1576	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1577	* @param val change the values of
cparata	0:6d69e896ce38	1578	* dataready_pulsed in
cparata	0:6d69e896ce38	1579	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	1580	*
cparata	0:6d69e896ce38	1581	*/
cparata	0:6d69e896ce38	1582	int32_t lsm6dso_data_ready_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1583	lsm6dso_dataready_pulsed_t val)
cparata	0:6d69e896ce38	1584	{
cparata	4:77faf76e3cd8	1585	lsm6dso_counter_bdr_reg1_t reg;
cparata	4:77faf76e3cd8	1586	int32_t ret;
cparata	4:77faf76e3cd8	1587
cparata	4:77faf76e3cd8	1588	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1589	if (ret == 0) {
cparata	4:77faf76e3cd8	1590	reg.dataready_pulsed = (uint8_t)val;
cparata	4:77faf76e3cd8	1591	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1592	}
cparata	4:77faf76e3cd8	1593	return ret;
cparata	0:6d69e896ce38	1594	}
cparata	0:6d69e896ce38	1595
cparata	0:6d69e896ce38	1596	/**
cparata	0:6d69e896ce38	1597	* @brief Data-ready pulsed / letched mode.[get]
cparata	0:6d69e896ce38	1598	*
cparata	0:6d69e896ce38	1599	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1600	* @param val Get the values of
cparata	0:6d69e896ce38	1601	* dataready_pulsed in
cparata	0:6d69e896ce38	1602	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	1603	*
cparata	0:6d69e896ce38	1604	*/
cparata	0:6d69e896ce38	1605	int32_t lsm6dso_data_ready_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1606	lsm6dso_dataready_pulsed_t *val)
cparata	0:6d69e896ce38	1607	{
cparata	4:77faf76e3cd8	1608	lsm6dso_counter_bdr_reg1_t reg;
cparata	4:77faf76e3cd8	1609	int32_t ret;
cparata	4:77faf76e3cd8	1610
cparata	4:77faf76e3cd8	1611	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1612	switch (reg.dataready_pulsed) {
cparata	4:77faf76e3cd8	1613	case LSM6DSO_DRDY_LATCHED:
cparata	4:77faf76e3cd8	1614	*val = LSM6DSO_DRDY_LATCHED;
cparata	4:77faf76e3cd8	1615	break;
cparata	4:77faf76e3cd8	1616	case LSM6DSO_DRDY_PULSED:
cparata	4:77faf76e3cd8	1617	*val = LSM6DSO_DRDY_PULSED;
cparata	4:77faf76e3cd8	1618	break;
cparata	4:77faf76e3cd8	1619	default:
cparata	4:77faf76e3cd8	1620	*val = LSM6DSO_DRDY_LATCHED;
cparata	4:77faf76e3cd8	1621	break;
cparata	4:77faf76e3cd8	1622	}
cparata	4:77faf76e3cd8	1623	return ret;
cparata	0:6d69e896ce38	1624	}
cparata	0:6d69e896ce38	1625
cparata	0:6d69e896ce38	1626	/**
cparata	0:6d69e896ce38	1627	* @brief Device "Who am I".[get]
cparata	0:6d69e896ce38	1628	*
cparata	0:6d69e896ce38	1629	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1630	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1631	*
cparata	0:6d69e896ce38	1632	*/
cparata	0:6d69e896ce38	1633	int32_t lsm6dso_device_id_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1634	{
cparata	4:77faf76e3cd8	1635	int32_t ret;
cparata	4:77faf76e3cd8	1636	ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I, buff, 1);
cparata	4:77faf76e3cd8	1637	return ret;
cparata	0:6d69e896ce38	1638	}
cparata	0:6d69e896ce38	1639
cparata	0:6d69e896ce38	1640	/**
cparata	0:6d69e896ce38	1641	* @brief Software reset. Restore the default values
cparata	0:6d69e896ce38	1642	* in user registers[set]
cparata	0:6d69e896ce38	1643	*
cparata	0:6d69e896ce38	1644	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1645	* @param val change the values of sw_reset in reg CTRL3_C
cparata	0:6d69e896ce38	1646	*
cparata	0:6d69e896ce38	1647	*/
cparata	0:6d69e896ce38	1648	int32_t lsm6dso_reset_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1649	{
cparata	4:77faf76e3cd8	1650	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	1651	int32_t ret;
cparata	4:77faf76e3cd8	1652
cparata	4:77faf76e3cd8	1653	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1654	if (ret == 0) {
cparata	4:77faf76e3cd8	1655	reg.sw_reset = val;
cparata	4:77faf76e3cd8	1656	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1657	}
cparata	4:77faf76e3cd8	1658
cparata	4:77faf76e3cd8	1659	return ret;
cparata	0:6d69e896ce38	1660	}
cparata	0:6d69e896ce38	1661
cparata	0:6d69e896ce38	1662	/**
cparata	0:6d69e896ce38	1663	* @brief Software reset. Restore the default values in user registers.[get]
cparata	0:6d69e896ce38	1664	*
cparata	0:6d69e896ce38	1665	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1666	* @param val change the values of sw_reset in reg CTRL3_C
cparata	0:6d69e896ce38	1667	*
cparata	0:6d69e896ce38	1668	*/
cparata	0:6d69e896ce38	1669	int32_t lsm6dso_reset_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1670	{
cparata	4:77faf76e3cd8	1671	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	1672	int32_t ret;
cparata	4:77faf76e3cd8	1673
cparata	4:77faf76e3cd8	1674	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1675	*val = reg.sw_reset;
cparata	4:77faf76e3cd8	1676
cparata	4:77faf76e3cd8	1677	return ret;
cparata	0:6d69e896ce38	1678	}
cparata	0:6d69e896ce38	1679
cparata	0:6d69e896ce38	1680	/**
cparata	0:6d69e896ce38	1681	* @brief Register address automatically incremented during a multiple byte
cparata	0:6d69e896ce38	1682	* access with a serial interface.[set]
cparata	0:6d69e896ce38	1683	*
cparata	0:6d69e896ce38	1684	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1685	* @param val change the values of if_inc in reg CTRL3_C
cparata	0:6d69e896ce38	1686	*
cparata	0:6d69e896ce38	1687	*/
cparata	0:6d69e896ce38	1688	int32_t lsm6dso_auto_increment_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1689	{
cparata	4:77faf76e3cd8	1690	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	1691	int32_t ret;
cparata	4:77faf76e3cd8	1692
cparata	4:77faf76e3cd8	1693	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1694	if (ret == 0) {
cparata	4:77faf76e3cd8	1695	reg.if_inc = val;
cparata	4:77faf76e3cd8	1696	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1697	}
cparata	4:77faf76e3cd8	1698	return ret;
cparata	0:6d69e896ce38	1699	}
cparata	0:6d69e896ce38	1700
cparata	0:6d69e896ce38	1701	/**
cparata	0:6d69e896ce38	1702	* @brief Register address automatically incremented during a multiple byte
cparata	0:6d69e896ce38	1703	* access with a serial interface.[get]
cparata	0:6d69e896ce38	1704	*
cparata	0:6d69e896ce38	1705	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1706	* @param val change the values of if_inc in reg CTRL3_C
cparata	0:6d69e896ce38	1707	*
cparata	0:6d69e896ce38	1708	*/
cparata	0:6d69e896ce38	1709	int32_t lsm6dso_auto_increment_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1710	{
cparata	4:77faf76e3cd8	1711	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	1712	int32_t ret;
cparata	4:77faf76e3cd8	1713
cparata	4:77faf76e3cd8	1714	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1715	*val = reg.if_inc;
cparata	4:77faf76e3cd8	1716
cparata	4:77faf76e3cd8	1717	return ret;
cparata	0:6d69e896ce38	1718	}
cparata	0:6d69e896ce38	1719
cparata	0:6d69e896ce38	1720	/**
cparata	0:6d69e896ce38	1721	* @brief Reboot memory content. Reload the calibration parameters.[set]
cparata	0:6d69e896ce38	1722	*
cparata	0:6d69e896ce38	1723	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1724	* @param val change the values of boot in reg CTRL3_C
cparata	0:6d69e896ce38	1725	*
cparata	0:6d69e896ce38	1726	*/
cparata	0:6d69e896ce38	1727	int32_t lsm6dso_boot_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1728	{
cparata	4:77faf76e3cd8	1729	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	1730	int32_t ret;
cparata	4:77faf76e3cd8	1731
cparata	4:77faf76e3cd8	1732	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1733	if (ret == 0) {
cparata	4:77faf76e3cd8	1734	reg.boot = val;
cparata	4:77faf76e3cd8	1735	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1736	}
cparata	4:77faf76e3cd8	1737	return ret;
cparata	0:6d69e896ce38	1738	}
cparata	0:6d69e896ce38	1739
cparata	0:6d69e896ce38	1740	/**
cparata	0:6d69e896ce38	1741	* @brief Reboot memory content. Reload the calibration parameters.[get]
cparata	0:6d69e896ce38	1742	*
cparata	0:6d69e896ce38	1743	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1744	* @param val change the values of boot in reg CTRL3_C
cparata	0:6d69e896ce38	1745	*
cparata	0:6d69e896ce38	1746	*/
cparata	0:6d69e896ce38	1747	int32_t lsm6dso_boot_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1748	{
cparata	4:77faf76e3cd8	1749	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	1750	int32_t ret;
cparata	4:77faf76e3cd8	1751
cparata	4:77faf76e3cd8	1752	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1753	*val = reg.boot;
cparata	4:77faf76e3cd8	1754
cparata	4:77faf76e3cd8	1755	return ret;
cparata	0:6d69e896ce38	1756	}
cparata	0:6d69e896ce38	1757
cparata	0:6d69e896ce38	1758	/**
cparata	0:6d69e896ce38	1759	* @brief Linear acceleration sensor self-test enable.[set]
cparata	0:6d69e896ce38	1760	*
cparata	0:6d69e896ce38	1761	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1762	* @param val change the values of st_xl in reg CTRL5_C
cparata	0:6d69e896ce38	1763	*
cparata	0:6d69e896ce38	1764	*/
cparata	0:6d69e896ce38	1765	int32_t lsm6dso_xl_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_xl_t val)
cparata	0:6d69e896ce38	1766	{
cparata	4:77faf76e3cd8	1767	lsm6dso_ctrl5_c_t reg;
cparata	4:77faf76e3cd8	1768	int32_t ret;
cparata	4:77faf76e3cd8	1769
cparata	4:77faf76e3cd8	1770	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1771	if (ret == 0) {
cparata	4:77faf76e3cd8	1772	reg.st_xl = (uint8_t)val;
cparata	4:77faf76e3cd8	1773	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1774	}
cparata	4:77faf76e3cd8	1775	return ret;
cparata	0:6d69e896ce38	1776	}
cparata	0:6d69e896ce38	1777
cparata	0:6d69e896ce38	1778	/**
cparata	0:6d69e896ce38	1779	* @brief Linear acceleration sensor self-test enable.[get]
cparata	0:6d69e896ce38	1780	*
cparata	0:6d69e896ce38	1781	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1782	* @param val Get the values of st_xl in reg CTRL5_C
cparata	0:6d69e896ce38	1783	*
cparata	0:6d69e896ce38	1784	*/
cparata	0:6d69e896ce38	1785	int32_t lsm6dso_xl_self_test_get(lsm6dso_ctx_t ctx, lsm6dso_st_xl_t val)
cparata	0:6d69e896ce38	1786	{
cparata	4:77faf76e3cd8	1787	lsm6dso_ctrl5_c_t reg;
cparata	4:77faf76e3cd8	1788	int32_t ret;
cparata	4:77faf76e3cd8	1789
cparata	4:77faf76e3cd8	1790	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1791	switch (reg.st_xl) {
cparata	4:77faf76e3cd8	1792	case LSM6DSO_XL_ST_DISABLE:
cparata	4:77faf76e3cd8	1793	*val = LSM6DSO_XL_ST_DISABLE;
cparata	4:77faf76e3cd8	1794	break;
cparata	4:77faf76e3cd8	1795	case LSM6DSO_XL_ST_POSITIVE:
cparata	4:77faf76e3cd8	1796	*val = LSM6DSO_XL_ST_POSITIVE;
cparata	4:77faf76e3cd8	1797	break;
cparata	4:77faf76e3cd8	1798	case LSM6DSO_XL_ST_NEGATIVE:
cparata	4:77faf76e3cd8	1799	*val = LSM6DSO_XL_ST_NEGATIVE;
cparata	4:77faf76e3cd8	1800	break;
cparata	4:77faf76e3cd8	1801	default:
cparata	4:77faf76e3cd8	1802	*val = LSM6DSO_XL_ST_DISABLE;
cparata	4:77faf76e3cd8	1803	break;
cparata	4:77faf76e3cd8	1804	}
cparata	4:77faf76e3cd8	1805	return ret;
cparata	0:6d69e896ce38	1806	}
cparata	0:6d69e896ce38	1807
cparata	0:6d69e896ce38	1808	/**
cparata	0:6d69e896ce38	1809	* @brief Angular rate sensor self-test enable.[set]
cparata	0:6d69e896ce38	1810	*
cparata	0:6d69e896ce38	1811	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1812	* @param val change the values of st_g in reg CTRL5_C
cparata	0:6d69e896ce38	1813	*
cparata	0:6d69e896ce38	1814	*/
cparata	0:6d69e896ce38	1815	int32_t lsm6dso_gy_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_g_t val)
cparata	0:6d69e896ce38	1816	{
cparata	4:77faf76e3cd8	1817	lsm6dso_ctrl5_c_t reg;
cparata	4:77faf76e3cd8	1818	int32_t ret;
cparata	4:77faf76e3cd8	1819
cparata	4:77faf76e3cd8	1820	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1821	if (ret == 0) {
cparata	4:77faf76e3cd8	1822	reg.st_g = (uint8_t)val;
cparata	4:77faf76e3cd8	1823	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1824	}
cparata	4:77faf76e3cd8	1825	return ret;
cparata	0:6d69e896ce38	1826	}
cparata	0:6d69e896ce38	1827
cparata	0:6d69e896ce38	1828	/**
cparata	0:6d69e896ce38	1829	* @brief Angular rate sensor self-test enable.[get]
cparata	0:6d69e896ce38	1830	*
cparata	0:6d69e896ce38	1831	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1832	* @param val Get the values of st_g in reg CTRL5_C
cparata	0:6d69e896ce38	1833	*
cparata	0:6d69e896ce38	1834	*/
cparata	0:6d69e896ce38	1835	int32_t lsm6dso_gy_self_test_get(lsm6dso_ctx_t ctx, lsm6dso_st_g_t val)
cparata	0:6d69e896ce38	1836	{
cparata	4:77faf76e3cd8	1837	lsm6dso_ctrl5_c_t reg;
cparata	4:77faf76e3cd8	1838	int32_t ret;
cparata	4:77faf76e3cd8	1839
cparata	4:77faf76e3cd8	1840	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1841	switch (reg.st_g) {
cparata	4:77faf76e3cd8	1842	case LSM6DSO_GY_ST_DISABLE:
cparata	4:77faf76e3cd8	1843	*val = LSM6DSO_GY_ST_DISABLE;
cparata	4:77faf76e3cd8	1844	break;
cparata	4:77faf76e3cd8	1845	case LSM6DSO_GY_ST_POSITIVE:
cparata	4:77faf76e3cd8	1846	*val = LSM6DSO_GY_ST_POSITIVE;
cparata	4:77faf76e3cd8	1847	break;
cparata	4:77faf76e3cd8	1848	case LSM6DSO_GY_ST_NEGATIVE:
cparata	4:77faf76e3cd8	1849	*val = LSM6DSO_GY_ST_NEGATIVE;
cparata	4:77faf76e3cd8	1850	break;
cparata	4:77faf76e3cd8	1851	default:
cparata	4:77faf76e3cd8	1852	*val = LSM6DSO_GY_ST_DISABLE;
cparata	4:77faf76e3cd8	1853	break;
cparata	4:77faf76e3cd8	1854	}
cparata	4:77faf76e3cd8	1855	return ret;
cparata	0:6d69e896ce38	1856	}
cparata	0:6d69e896ce38	1857
cparata	0:6d69e896ce38	1858	/**
cparata	0:6d69e896ce38	1859	* @}
cparata	0:6d69e896ce38	1860	*
cparata	0:6d69e896ce38	1861	*/
cparata	0:6d69e896ce38	1862
cparata	0:6d69e896ce38	1863	/**
cparata	0:6d69e896ce38	1864	* @defgroup LSM6DSO_filters
cparata	0:6d69e896ce38	1865	* @brief This section group all the functions concerning the
cparata	0:6d69e896ce38	1866	* filters configuration
cparata	0:6d69e896ce38	1867	* @{
cparata	0:6d69e896ce38	1868	*
cparata	0:6d69e896ce38	1869	*/
cparata	0:6d69e896ce38	1870
cparata	0:6d69e896ce38	1871	/**
cparata	0:6d69e896ce38	1872	* @brief Accelerometer output from LPF2 filtering stage selection.[set]
cparata	0:6d69e896ce38	1873	*
cparata	0:6d69e896ce38	1874	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1875	* @param val change the values of lpf2_xl_en in reg CTRL1_XL
cparata	0:6d69e896ce38	1876	*
cparata	0:6d69e896ce38	1877	*/
cparata	0:6d69e896ce38	1878	int32_t lsm6dso_xl_filter_lp2_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1879	{
cparata	4:77faf76e3cd8	1880	lsm6dso_ctrl1_xl_t reg;
cparata	4:77faf76e3cd8	1881	int32_t ret;
cparata	4:77faf76e3cd8	1882
cparata	4:77faf76e3cd8	1883	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1884	if (ret == 0) {
cparata	4:77faf76e3cd8	1885	reg.lpf2_xl_en = val;
cparata	4:77faf76e3cd8	1886	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1887	}
cparata	4:77faf76e3cd8	1888	return ret;
cparata	0:6d69e896ce38	1889	}
cparata	0:6d69e896ce38	1890
cparata	0:6d69e896ce38	1891	/**
cparata	0:6d69e896ce38	1892	* @brief Accelerometer output from LPF2 filtering stage selection.[get]
cparata	0:6d69e896ce38	1893	*
cparata	0:6d69e896ce38	1894	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1895	* @param val change the values of lpf2_xl_en in reg CTRL1_XL
cparata	0:6d69e896ce38	1896	*
cparata	0:6d69e896ce38	1897	*/
cparata	0:6d69e896ce38	1898	int32_t lsm6dso_xl_filter_lp2_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1899	{
cparata	4:77faf76e3cd8	1900	lsm6dso_ctrl1_xl_t reg;
cparata	4:77faf76e3cd8	1901	int32_t ret;
cparata	4:77faf76e3cd8	1902
cparata	4:77faf76e3cd8	1903	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1904	*val = reg.lpf2_xl_en;
cparata	4:77faf76e3cd8	1905
cparata	4:77faf76e3cd8	1906	return ret;
cparata	0:6d69e896ce38	1907	}
cparata	0:6d69e896ce38	1908
cparata	0:6d69e896ce38	1909	/**
cparata	0:6d69e896ce38	1910	* @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
cparata	0:6d69e896ce38	1911	* the bandwidth can be selected through FTYPE [2:0]
cparata	0:6d69e896ce38	1912	* in CTRL6_C (15h).[set]
cparata	0:6d69e896ce38	1913	*
cparata	0:6d69e896ce38	1914	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1915	* @param val change the values of lpf1_sel_g in reg CTRL4_C
cparata	0:6d69e896ce38	1916	*
cparata	0:6d69e896ce38	1917	*/
cparata	0:6d69e896ce38	1918	int32_t lsm6dso_gy_filter_lp1_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1919	{
cparata	4:77faf76e3cd8	1920	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	1921	int32_t ret;
cparata	4:77faf76e3cd8	1922
cparata	4:77faf76e3cd8	1923	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1924	if (ret == 0) {
cparata	4:77faf76e3cd8	1925	reg.lpf1_sel_g = val;
cparata	4:77faf76e3cd8	1926	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1927	}
cparata	4:77faf76e3cd8	1928	return ret;
cparata	0:6d69e896ce38	1929	}
cparata	0:6d69e896ce38	1930
cparata	0:6d69e896ce38	1931	/**
cparata	0:6d69e896ce38	1932	* @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
cparata	0:6d69e896ce38	1933	* the bandwidth can be selected through FTYPE [2:0]
cparata	0:6d69e896ce38	1934	* in CTRL6_C (15h).[get]
cparata	0:6d69e896ce38	1935	*
cparata	0:6d69e896ce38	1936	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1937	* @param val change the values of lpf1_sel_g in reg CTRL4_C
cparata	0:6d69e896ce38	1938	*
cparata	0:6d69e896ce38	1939	*/
cparata	0:6d69e896ce38	1940	int32_t lsm6dso_gy_filter_lp1_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1941	{
cparata	4:77faf76e3cd8	1942	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	1943	int32_t ret;
cparata	4:77faf76e3cd8	1944
cparata	4:77faf76e3cd8	1945	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1946	*val = reg.lpf1_sel_g;
cparata	4:77faf76e3cd8	1947
cparata	4:77faf76e3cd8	1948	return ret;
cparata	0:6d69e896ce38	1949	}
cparata	0:6d69e896ce38	1950
cparata	0:6d69e896ce38	1951	/**
cparata	0:6d69e896ce38	1952	* @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
cparata	0:6d69e896ce38	1953	* (XL and Gyro independently masked).[set]
cparata	0:6d69e896ce38	1954	*
cparata	0:6d69e896ce38	1955	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1956	* @param val change the values of drdy_mask in reg CTRL4_C
cparata	0:6d69e896ce38	1957	*
cparata	0:6d69e896ce38	1958	*/
cparata	0:6d69e896ce38	1959	int32_t lsm6dso_filter_settling_mask_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1960	{
cparata	4:77faf76e3cd8	1961	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	1962	int32_t ret;
cparata	4:77faf76e3cd8	1963
cparata	4:77faf76e3cd8	1964	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1965	if (ret == 0) {
cparata	4:77faf76e3cd8	1966	reg.drdy_mask = val;
cparata	4:77faf76e3cd8	1967	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1968	}
cparata	4:77faf76e3cd8	1969	return ret;
cparata	0:6d69e896ce38	1970	}
cparata	0:6d69e896ce38	1971
cparata	0:6d69e896ce38	1972	/**
cparata	0:6d69e896ce38	1973	* @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
cparata	0:6d69e896ce38	1974	* (XL and Gyro independently masked).[get]
cparata	0:6d69e896ce38	1975	*
cparata	0:6d69e896ce38	1976	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1977	* @param val change the values of drdy_mask in reg CTRL4_C
cparata	0:6d69e896ce38	1978	*
cparata	0:6d69e896ce38	1979	*/
cparata	0:6d69e896ce38	1980	int32_t lsm6dso_filter_settling_mask_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1981	{
cparata	4:77faf76e3cd8	1982	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	1983	int32_t ret;
cparata	4:77faf76e3cd8	1984
cparata	4:77faf76e3cd8	1985	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1986	*val = reg.drdy_mask;
cparata	4:77faf76e3cd8	1987
cparata	4:77faf76e3cd8	1988	return ret;
cparata	0:6d69e896ce38	1989	}
cparata	0:6d69e896ce38	1990
cparata	0:6d69e896ce38	1991	/**
cparata	0:6d69e896ce38	1992	* @brief Gyroscope lp1 bandwidth.[set]
cparata	0:6d69e896ce38	1993	*
cparata	0:6d69e896ce38	1994	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1995	* @param val change the values of ftype in reg CTRL6_C
cparata	0:6d69e896ce38	1996	*
cparata	0:6d69e896ce38	1997	*/
cparata	0:6d69e896ce38	1998	int32_t lsm6dso_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx, lsm6dso_ftype_t val)
cparata	0:6d69e896ce38	1999	{
cparata	4:77faf76e3cd8	2000	lsm6dso_ctrl6_c_t reg;
cparata	4:77faf76e3cd8	2001	int32_t ret;
cparata	4:77faf76e3cd8	2002
cparata	4:77faf76e3cd8	2003	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2004	if (ret == 0) {
cparata	4:77faf76e3cd8	2005	reg.ftype = (uint8_t)val;
cparata	4:77faf76e3cd8	2006	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2007	}
cparata	4:77faf76e3cd8	2008	return ret;
cparata	0:6d69e896ce38	2009	}
cparata	0:6d69e896ce38	2010
cparata	0:6d69e896ce38	2011	/**
cparata	0:6d69e896ce38	2012	* @brief Gyroscope lp1 bandwidth.[get]
cparata	0:6d69e896ce38	2013	*
cparata	0:6d69e896ce38	2014	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2015	* @param val Get the values of ftype in reg CTRL6_C
cparata	0:6d69e896ce38	2016	*
cparata	0:6d69e896ce38	2017	*/
cparata	0:6d69e896ce38	2018	int32_t lsm6dso_gy_lp1_bandwidth_get(lsm6dso_ctx_t ctx, lsm6dso_ftype_t val)
cparata	0:6d69e896ce38	2019	{
cparata	4:77faf76e3cd8	2020	lsm6dso_ctrl6_c_t reg;
cparata	4:77faf76e3cd8	2021	int32_t ret;
cparata	4:77faf76e3cd8	2022
cparata	4:77faf76e3cd8	2023	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2024	switch (reg.ftype) {
cparata	4:77faf76e3cd8	2025	case LSM6DSO_ULTRA_LIGHT:
cparata	4:77faf76e3cd8	2026	*val = LSM6DSO_ULTRA_LIGHT;
cparata	4:77faf76e3cd8	2027	break;
cparata	4:77faf76e3cd8	2028	case LSM6DSO_VERY_LIGHT:
cparata	4:77faf76e3cd8	2029	*val = LSM6DSO_VERY_LIGHT;
cparata	4:77faf76e3cd8	2030	break;
cparata	4:77faf76e3cd8	2031	case LSM6DSO_LIGHT:
cparata	4:77faf76e3cd8	2032	*val = LSM6DSO_LIGHT;
cparata	4:77faf76e3cd8	2033	break;
cparata	4:77faf76e3cd8	2034	case LSM6DSO_MEDIUM:
cparata	4:77faf76e3cd8	2035	*val = LSM6DSO_MEDIUM;
cparata	4:77faf76e3cd8	2036	break;
cparata	4:77faf76e3cd8	2037	case LSM6DSO_STRONG:
cparata	4:77faf76e3cd8	2038	*val = LSM6DSO_STRONG;
cparata	4:77faf76e3cd8	2039	break;
cparata	4:77faf76e3cd8	2040	case LSM6DSO_VERY_STRONG:
cparata	4:77faf76e3cd8	2041	*val = LSM6DSO_VERY_STRONG;
cparata	4:77faf76e3cd8	2042	break;
cparata	4:77faf76e3cd8	2043	case LSM6DSO_AGGRESSIVE:
cparata	4:77faf76e3cd8	2044	*val = LSM6DSO_AGGRESSIVE;
cparata	4:77faf76e3cd8	2045	break;
cparata	4:77faf76e3cd8	2046	case LSM6DSO_XTREME:
cparata	4:77faf76e3cd8	2047	*val = LSM6DSO_XTREME;
cparata	4:77faf76e3cd8	2048	break;
cparata	4:77faf76e3cd8	2049	default:
cparata	4:77faf76e3cd8	2050	*val = LSM6DSO_ULTRA_LIGHT;
cparata	4:77faf76e3cd8	2051	break;
cparata	4:77faf76e3cd8	2052	}
cparata	4:77faf76e3cd8	2053	return ret;
cparata	0:6d69e896ce38	2054	}
cparata	0:6d69e896ce38	2055
cparata	0:6d69e896ce38	2056	/**
cparata	0:6d69e896ce38	2057	* @brief Low pass filter 2 on 6D function selection.[set]
cparata	0:6d69e896ce38	2058	*
cparata	0:6d69e896ce38	2059	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2060	* @param val change the values of low_pass_on_6d in reg CTRL8_XL
cparata	0:6d69e896ce38	2061	*
cparata	0:6d69e896ce38	2062	*/
cparata	0:6d69e896ce38	2063	int32_t lsm6dso_xl_lp2_on_6d_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	2064	{
cparata	4:77faf76e3cd8	2065	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2066	int32_t ret;
cparata	4:77faf76e3cd8	2067
cparata	4:77faf76e3cd8	2068	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2069	if (ret == 0) {
cparata	4:77faf76e3cd8	2070	reg.low_pass_on_6d = val;
cparata	4:77faf76e3cd8	2071	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2072	}
cparata	4:77faf76e3cd8	2073	return ret;
cparata	0:6d69e896ce38	2074	}
cparata	0:6d69e896ce38	2075
cparata	0:6d69e896ce38	2076	/**
cparata	0:6d69e896ce38	2077	* @brief Low pass filter 2 on 6D function selection.[get]
cparata	0:6d69e896ce38	2078	*
cparata	0:6d69e896ce38	2079	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2080	* @param val change the values of low_pass_on_6d in reg CTRL8_XL
cparata	0:6d69e896ce38	2081	*
cparata	0:6d69e896ce38	2082	*/
cparata	0:6d69e896ce38	2083	int32_t lsm6dso_xl_lp2_on_6d_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2084	{
cparata	4:77faf76e3cd8	2085	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2086	int32_t ret;
cparata	4:77faf76e3cd8	2087
cparata	4:77faf76e3cd8	2088	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2089	*val = reg.low_pass_on_6d;
cparata	4:77faf76e3cd8	2090
cparata	4:77faf76e3cd8	2091	return ret;
cparata	0:6d69e896ce38	2092	}
cparata	0:6d69e896ce38	2093
cparata	0:6d69e896ce38	2094	/**
cparata	0:6d69e896ce38	2095	* @brief Accelerometer slope filter / high-pass filter selection
cparata	0:6d69e896ce38	2096	* on output.[set]
cparata	0:6d69e896ce38	2097	*
cparata	0:6d69e896ce38	2098	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2099	* @param val change the values of hp_slope_xl_en
cparata	0:6d69e896ce38	2100	* in reg CTRL8_XL
cparata	0:6d69e896ce38	2101	*
cparata	0:6d69e896ce38	2102	*/
cparata	0:6d69e896ce38	2103	int32_t lsm6dso_xl_hp_path_on_out_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2104	lsm6dso_hp_slope_xl_en_t val)
cparata	0:6d69e896ce38	2105	{
cparata	4:77faf76e3cd8	2106	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2107	int32_t ret;
cparata	4:77faf76e3cd8	2108
cparata	4:77faf76e3cd8	2109	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2110	if (ret == 0) {
cparata	4:77faf76e3cd8	2111	reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
cparata	4:77faf76e3cd8	2112	reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
cparata	4:77faf76e3cd8	2113	reg.hpcf_xl = (uint8_t)val & 0x07U;
cparata	4:77faf76e3cd8	2114	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2115	}
cparata	4:77faf76e3cd8	2116	return ret;
cparata	0:6d69e896ce38	2117	}
cparata	0:6d69e896ce38	2118
cparata	0:6d69e896ce38	2119	/**
cparata	0:6d69e896ce38	2120	* @brief Accelerometer slope filter / high-pass filter selection
cparata	0:6d69e896ce38	2121	* on output.[get]
cparata	0:6d69e896ce38	2122	*
cparata	0:6d69e896ce38	2123	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2124	* @param val Get the values of hp_slope_xl_en
cparata	0:6d69e896ce38	2125	* in reg CTRL8_XL
cparata	0:6d69e896ce38	2126	*
cparata	0:6d69e896ce38	2127	*/
cparata	0:6d69e896ce38	2128	int32_t lsm6dso_xl_hp_path_on_out_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2129	lsm6dso_hp_slope_xl_en_t *val)
cparata	0:6d69e896ce38	2130	{
cparata	4:77faf76e3cd8	2131	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2132	int32_t ret;
cparata	4:77faf76e3cd8	2133
cparata	4:77faf76e3cd8	2134	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2135	switch ((reg.hp_ref_mode_xl << 5) \| (reg.hp_slope_xl_en << 4) \|
cparata	4:77faf76e3cd8	2136	reg.hpcf_xl) {
cparata	4:77faf76e3cd8	2137	case LSM6DSO_HP_PATH_DISABLE_ON_OUT:
cparata	4:77faf76e3cd8	2138	*val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
cparata	4:77faf76e3cd8	2139	break;
cparata	4:77faf76e3cd8	2140	case LSM6DSO_SLOPE_ODR_DIV_4:
cparata	4:77faf76e3cd8	2141	*val = LSM6DSO_SLOPE_ODR_DIV_4;
cparata	4:77faf76e3cd8	2142	break;
cparata	4:77faf76e3cd8	2143	case LSM6DSO_HP_ODR_DIV_10:
cparata	4:77faf76e3cd8	2144	*val = LSM6DSO_HP_ODR_DIV_10;
cparata	4:77faf76e3cd8	2145	break;
cparata	4:77faf76e3cd8	2146	case LSM6DSO_HP_ODR_DIV_20:
cparata	4:77faf76e3cd8	2147	*val = LSM6DSO_HP_ODR_DIV_20;
cparata	4:77faf76e3cd8	2148	break;
cparata	4:77faf76e3cd8	2149	case LSM6DSO_HP_ODR_DIV_45:
cparata	4:77faf76e3cd8	2150	*val = LSM6DSO_HP_ODR_DIV_45;
cparata	4:77faf76e3cd8	2151	break;
cparata	4:77faf76e3cd8	2152	case LSM6DSO_HP_ODR_DIV_100:
cparata	4:77faf76e3cd8	2153	*val = LSM6DSO_HP_ODR_DIV_100;
cparata	4:77faf76e3cd8	2154	break;
cparata	4:77faf76e3cd8	2155	case LSM6DSO_HP_ODR_DIV_200:
cparata	4:77faf76e3cd8	2156	*val = LSM6DSO_HP_ODR_DIV_200;
cparata	4:77faf76e3cd8	2157	break;
cparata	4:77faf76e3cd8	2158	case LSM6DSO_HP_ODR_DIV_400:
cparata	4:77faf76e3cd8	2159	*val = LSM6DSO_HP_ODR_DIV_400;
cparata	4:77faf76e3cd8	2160	break;
cparata	4:77faf76e3cd8	2161	case LSM6DSO_HP_ODR_DIV_800:
cparata	4:77faf76e3cd8	2162	*val = LSM6DSO_HP_ODR_DIV_800;
cparata	4:77faf76e3cd8	2163	break;
cparata	4:77faf76e3cd8	2164	case LSM6DSO_HP_REF_MD_ODR_DIV_10:
cparata	4:77faf76e3cd8	2165	*val = LSM6DSO_HP_REF_MD_ODR_DIV_10;
cparata	4:77faf76e3cd8	2166	break;
cparata	4:77faf76e3cd8	2167	case LSM6DSO_HP_REF_MD_ODR_DIV_20:
cparata	4:77faf76e3cd8	2168	*val = LSM6DSO_HP_REF_MD_ODR_DIV_20;
cparata	4:77faf76e3cd8	2169	break;
cparata	4:77faf76e3cd8	2170	case LSM6DSO_HP_REF_MD_ODR_DIV_45:
cparata	4:77faf76e3cd8	2171	*val = LSM6DSO_HP_REF_MD_ODR_DIV_45;
cparata	4:77faf76e3cd8	2172	break;
cparata	4:77faf76e3cd8	2173	case LSM6DSO_HP_REF_MD_ODR_DIV_100:
cparata	4:77faf76e3cd8	2174	*val = LSM6DSO_HP_REF_MD_ODR_DIV_100;
cparata	4:77faf76e3cd8	2175	break;
cparata	4:77faf76e3cd8	2176	case LSM6DSO_HP_REF_MD_ODR_DIV_200:
cparata	4:77faf76e3cd8	2177	*val = LSM6DSO_HP_REF_MD_ODR_DIV_200;
cparata	4:77faf76e3cd8	2178	break;
cparata	4:77faf76e3cd8	2179	case LSM6DSO_HP_REF_MD_ODR_DIV_400:
cparata	4:77faf76e3cd8	2180	*val = LSM6DSO_HP_REF_MD_ODR_DIV_400;
cparata	4:77faf76e3cd8	2181	break;
cparata	4:77faf76e3cd8	2182	case LSM6DSO_HP_REF_MD_ODR_DIV_800:
cparata	4:77faf76e3cd8	2183	*val = LSM6DSO_HP_REF_MD_ODR_DIV_800;
cparata	4:77faf76e3cd8	2184	break;
cparata	4:77faf76e3cd8	2185	case LSM6DSO_LP_ODR_DIV_10:
cparata	4:77faf76e3cd8	2186	*val = LSM6DSO_LP_ODR_DIV_10;
cparata	4:77faf76e3cd8	2187	break;
cparata	4:77faf76e3cd8	2188	case LSM6DSO_LP_ODR_DIV_20:
cparata	4:77faf76e3cd8	2189	*val = LSM6DSO_LP_ODR_DIV_20;
cparata	4:77faf76e3cd8	2190	break;
cparata	4:77faf76e3cd8	2191	case LSM6DSO_LP_ODR_DIV_45:
cparata	4:77faf76e3cd8	2192	*val = LSM6DSO_LP_ODR_DIV_45;
cparata	4:77faf76e3cd8	2193	break;
cparata	4:77faf76e3cd8	2194	case LSM6DSO_LP_ODR_DIV_100:
cparata	4:77faf76e3cd8	2195	*val = LSM6DSO_LP_ODR_DIV_100;
cparata	4:77faf76e3cd8	2196	break;
cparata	4:77faf76e3cd8	2197	case LSM6DSO_LP_ODR_DIV_200:
cparata	4:77faf76e3cd8	2198	*val = LSM6DSO_LP_ODR_DIV_200;
cparata	4:77faf76e3cd8	2199	break;
cparata	4:77faf76e3cd8	2200	case LSM6DSO_LP_ODR_DIV_400:
cparata	4:77faf76e3cd8	2201	*val = LSM6DSO_LP_ODR_DIV_400;
cparata	4:77faf76e3cd8	2202	break;
cparata	4:77faf76e3cd8	2203	case LSM6DSO_LP_ODR_DIV_800:
cparata	4:77faf76e3cd8	2204	*val = LSM6DSO_LP_ODR_DIV_800;
cparata	4:77faf76e3cd8	2205	break;
cparata	4:77faf76e3cd8	2206	default:
cparata	4:77faf76e3cd8	2207	*val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
cparata	4:77faf76e3cd8	2208	break;
cparata	4:77faf76e3cd8	2209	}
cparata	4:77faf76e3cd8	2210
cparata	4:77faf76e3cd8	2211	return ret;
cparata	0:6d69e896ce38	2212	}
cparata	0:6d69e896ce38	2213
cparata	0:6d69e896ce38	2214	/**
cparata	0:6d69e896ce38	2215	* @brief Enables accelerometer LPF2 and HPF fast-settling mode.
cparata	0:6d69e896ce38	2216	* The filter sets the second samples after writing this bit.
cparata	0:6d69e896ce38	2217	* Active only during device exit from power-down mode.[set]
cparata	0:6d69e896ce38	2218	*
cparata	0:6d69e896ce38	2219	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2220	* @param val change the values of fastsettl_mode_xl in
cparata	0:6d69e896ce38	2221	* reg CTRL8_XL
cparata	0:6d69e896ce38	2222	*
cparata	0:6d69e896ce38	2223	*/
cparata	0:6d69e896ce38	2224	int32_t lsm6dso_xl_fast_settling_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	2225	{
cparata	4:77faf76e3cd8	2226	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2227	int32_t ret;
cparata	4:77faf76e3cd8	2228
cparata	4:77faf76e3cd8	2229	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2230	if (ret == 0) {
cparata	4:77faf76e3cd8	2231	reg.fastsettl_mode_xl = val;
cparata	4:77faf76e3cd8	2232	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2233	}
cparata	4:77faf76e3cd8	2234	return ret;
cparata	0:6d69e896ce38	2235	}
cparata	0:6d69e896ce38	2236
cparata	0:6d69e896ce38	2237	/**
cparata	0:6d69e896ce38	2238	* @brief Enables accelerometer LPF2 and HPF fast-settling mode.
cparata	0:6d69e896ce38	2239	* The filter sets the second samples after writing this bit.
cparata	0:6d69e896ce38	2240	* Active only during device exit from power-down mode.[get]
cparata	0:6d69e896ce38	2241	*
cparata	0:6d69e896ce38	2242	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2243	* @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
cparata	0:6d69e896ce38	2244	*
cparata	0:6d69e896ce38	2245	*/
cparata	0:6d69e896ce38	2246	int32_t lsm6dso_xl_fast_settling_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2247	{
cparata	4:77faf76e3cd8	2248	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2249	int32_t ret;
cparata	4:77faf76e3cd8	2250
cparata	4:77faf76e3cd8	2251	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2252	*val = reg.fastsettl_mode_xl;
cparata	4:77faf76e3cd8	2253
cparata	4:77faf76e3cd8	2254	return ret;
cparata	0:6d69e896ce38	2255	}
cparata	0:6d69e896ce38	2256
cparata	0:6d69e896ce38	2257	/**
cparata	0:6d69e896ce38	2258	* @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
cparata	0:6d69e896ce38	2259	* functions.[set]
cparata	0:6d69e896ce38	2260	*
cparata	0:6d69e896ce38	2261	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2262	* @param val change the values of slope_fds in reg TAP_CFG0
cparata	0:6d69e896ce38	2263	*
cparata	0:6d69e896ce38	2264	*/
cparata	0:6d69e896ce38	2265	int32_t lsm6dso_xl_hp_path_internal_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2266	lsm6dso_slope_fds_t val)
cparata	0:6d69e896ce38	2267	{
cparata	4:77faf76e3cd8	2268	lsm6dso_tap_cfg0_t reg;
cparata	4:77faf76e3cd8	2269	int32_t ret;
cparata	4:77faf76e3cd8	2270
cparata	4:77faf76e3cd8	2271	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2272	if (ret == 0) {
cparata	4:77faf76e3cd8	2273	reg.slope_fds = (uint8_t)val;
cparata	4:77faf76e3cd8	2274	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2275	}
cparata	4:77faf76e3cd8	2276	return ret;
cparata	0:6d69e896ce38	2277	}
cparata	0:6d69e896ce38	2278
cparata	0:6d69e896ce38	2279	/**
cparata	0:6d69e896ce38	2280	* @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
cparata	0:6d69e896ce38	2281	* functions.[get]
cparata	0:6d69e896ce38	2282	*
cparata	0:6d69e896ce38	2283	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2284	* @param val Get the values of slope_fds in reg TAP_CFG0
cparata	0:6d69e896ce38	2285	*
cparata	0:6d69e896ce38	2286	*/
cparata	0:6d69e896ce38	2287	int32_t lsm6dso_xl_hp_path_internal_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2288	lsm6dso_slope_fds_t *val)
cparata	0:6d69e896ce38	2289	{
cparata	4:77faf76e3cd8	2290	lsm6dso_tap_cfg0_t reg;
cparata	4:77faf76e3cd8	2291	int32_t ret;
cparata	4:77faf76e3cd8	2292
cparata	4:77faf76e3cd8	2293	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2294	switch (reg.slope_fds) {
cparata	4:77faf76e3cd8	2295	case LSM6DSO_USE_SLOPE:
cparata	4:77faf76e3cd8	2296	*val = LSM6DSO_USE_SLOPE;
cparata	4:77faf76e3cd8	2297	break;
cparata	4:77faf76e3cd8	2298	case LSM6DSO_USE_HPF:
cparata	4:77faf76e3cd8	2299	*val = LSM6DSO_USE_HPF;
cparata	4:77faf76e3cd8	2300	break;
cparata	4:77faf76e3cd8	2301	default:
cparata	4:77faf76e3cd8	2302	*val = LSM6DSO_USE_SLOPE;
cparata	4:77faf76e3cd8	2303	break;
cparata	4:77faf76e3cd8	2304	}
cparata	4:77faf76e3cd8	2305	return ret;
cparata	0:6d69e896ce38	2306	}
cparata	0:6d69e896ce38	2307
cparata	0:6d69e896ce38	2308	/**
cparata	0:6d69e896ce38	2309	* @brief Enables gyroscope digital high-pass filter. The filter is
cparata	0:6d69e896ce38	2310	* enabled only if the gyro is in HP mode.[set]
cparata	0:6d69e896ce38	2311	*
cparata	0:6d69e896ce38	2312	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2313	* @param val Get the values of hp_en_g and hp_en_g
cparata	0:6d69e896ce38	2314	* in reg CTRL7_G
cparata	0:6d69e896ce38	2315	*
cparata	0:6d69e896ce38	2316	*/
cparata	0:6d69e896ce38	2317	int32_t lsm6dso_gy_hp_path_internal_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2318	lsm6dso_hpm_g_t val)
cparata	0:6d69e896ce38	2319	{
cparata	4:77faf76e3cd8	2320	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	2321	int32_t ret;
cparata	4:77faf76e3cd8	2322
cparata	4:77faf76e3cd8	2323	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2324	if (ret == 0) {
cparata	4:77faf76e3cd8	2325	reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
cparata	4:77faf76e3cd8	2326	reg.hpm_g = (uint8_t)val & 0x03U;
cparata	4:77faf76e3cd8	2327	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2328	}
cparata	4:77faf76e3cd8	2329	return ret;
cparata	0:6d69e896ce38	2330	}
cparata	0:6d69e896ce38	2331
cparata	0:6d69e896ce38	2332	/**
cparata	0:6d69e896ce38	2333	* @brief Enables gyroscope digital high-pass filter. The filter is
cparata	0:6d69e896ce38	2334	* enabled only if the gyro is in HP mode.[get]
cparata	0:6d69e896ce38	2335	*
cparata	0:6d69e896ce38	2336	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2337	* @param val Get the values of hp_en_g and hp_en_g
cparata	0:6d69e896ce38	2338	* in reg CTRL7_G
cparata	0:6d69e896ce38	2339	*
cparata	0:6d69e896ce38	2340	*/
cparata	0:6d69e896ce38	2341	int32_t lsm6dso_gy_hp_path_internal_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2342	lsm6dso_hpm_g_t *val)
cparata	0:6d69e896ce38	2343	{
cparata	4:77faf76e3cd8	2344	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	2345	int32_t ret;
cparata	4:77faf76e3cd8	2346
cparata	4:77faf76e3cd8	2347	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2348	switch ((reg.hp_en_g << 7) + reg.hpm_g) {
cparata	4:77faf76e3cd8	2349	case LSM6DSO_HP_FILTER_NONE:
cparata	4:77faf76e3cd8	2350	*val = LSM6DSO_HP_FILTER_NONE;
cparata	4:77faf76e3cd8	2351	break;
cparata	4:77faf76e3cd8	2352	case LSM6DSO_HP_FILTER_16mHz:
cparata	4:77faf76e3cd8	2353	*val = LSM6DSO_HP_FILTER_16mHz;
cparata	4:77faf76e3cd8	2354	break;
cparata	4:77faf76e3cd8	2355	case LSM6DSO_HP_FILTER_65mHz:
cparata	4:77faf76e3cd8	2356	*val = LSM6DSO_HP_FILTER_65mHz;
cparata	4:77faf76e3cd8	2357	break;
cparata	4:77faf76e3cd8	2358	case LSM6DSO_HP_FILTER_260mHz:
cparata	4:77faf76e3cd8	2359	*val = LSM6DSO_HP_FILTER_260mHz;
cparata	4:77faf76e3cd8	2360	break;
cparata	4:77faf76e3cd8	2361	case LSM6DSO_HP_FILTER_1Hz04:
cparata	4:77faf76e3cd8	2362	*val = LSM6DSO_HP_FILTER_1Hz04;
cparata	4:77faf76e3cd8	2363	break;
cparata	4:77faf76e3cd8	2364	default:
cparata	4:77faf76e3cd8	2365	*val = LSM6DSO_HP_FILTER_NONE;
cparata	4:77faf76e3cd8	2366	break;
cparata	4:77faf76e3cd8	2367	}
cparata	4:77faf76e3cd8	2368	return ret;
cparata	0:6d69e896ce38	2369	}
cparata	0:6d69e896ce38	2370
cparata	0:6d69e896ce38	2371	/**
cparata	0:6d69e896ce38	2372	* @}
cparata	0:6d69e896ce38	2373	*
cparata	0:6d69e896ce38	2374	*/
cparata	0:6d69e896ce38	2375
cparata	0:6d69e896ce38	2376	/**
cparata	0:6d69e896ce38	2377	* @defgroup LSM6DSO_ Auxiliary_interface
cparata	0:6d69e896ce38	2378	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	2379	* auxiliary interface.
cparata	0:6d69e896ce38	2380	* @{
cparata	0:6d69e896ce38	2381	*
cparata	0:6d69e896ce38	2382	*/
cparata	0:6d69e896ce38	2383
cparata	0:6d69e896ce38	2384	/**
cparata	0:6d69e896ce38	2385	* @brief aOn auxiliary interface connect/disconnect SDO and OCS
cparata	0:6d69e896ce38	2386	* internal pull-up.[set]
cparata	0:6d69e896ce38	2387	*
cparata	0:6d69e896ce38	2388	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2389	* @param val change the values of ois_pu_dis in
cparata	0:6d69e896ce38	2390	* reg PIN_CTRL
cparata	0:6d69e896ce38	2391	*
cparata	0:6d69e896ce38	2392	*/
cparata	0:6d69e896ce38	2393	int32_t lsm6dso_aux_sdo_ocs_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2394	lsm6dso_ois_pu_dis_t val)
cparata	0:6d69e896ce38	2395	{
cparata	4:77faf76e3cd8	2396	lsm6dso_pin_ctrl_t reg;
cparata	4:77faf76e3cd8	2397	int32_t ret;
cparata	4:77faf76e3cd8	2398
cparata	4:77faf76e3cd8	2399	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2400	if (ret == 0) {
cparata	4:77faf76e3cd8	2401	reg.ois_pu_dis = (uint8_t)val;
cparata	4:77faf76e3cd8	2402	ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2403	}
cparata	4:77faf76e3cd8	2404	return ret;
cparata	0:6d69e896ce38	2405	}
cparata	0:6d69e896ce38	2406
cparata	0:6d69e896ce38	2407	/**
cparata	0:6d69e896ce38	2408	* @brief On auxiliary interface connect/disconnect SDO and OCS
cparata	0:6d69e896ce38	2409	* internal pull-up.[get]
cparata	0:6d69e896ce38	2410	*
cparata	0:6d69e896ce38	2411	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2412	* @param val Get the values of ois_pu_dis in reg PIN_CTRL
cparata	0:6d69e896ce38	2413	*
cparata	0:6d69e896ce38	2414	*/
cparata	0:6d69e896ce38	2415	int32_t lsm6dso_aux_sdo_ocs_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2416	lsm6dso_ois_pu_dis_t *val)
cparata	0:6d69e896ce38	2417	{
cparata	4:77faf76e3cd8	2418	lsm6dso_pin_ctrl_t reg;
cparata	4:77faf76e3cd8	2419	int32_t ret;
cparata	4:77faf76e3cd8	2420
cparata	4:77faf76e3cd8	2421	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2422	switch (reg.ois_pu_dis) {
cparata	4:77faf76e3cd8	2423	case LSM6DSO_AUX_PULL_UP_DISC:
cparata	4:77faf76e3cd8	2424	*val = LSM6DSO_AUX_PULL_UP_DISC;
cparata	4:77faf76e3cd8	2425	break;
cparata	4:77faf76e3cd8	2426	case LSM6DSO_AUX_PULL_UP_CONNECT:
cparata	4:77faf76e3cd8	2427	*val = LSM6DSO_AUX_PULL_UP_CONNECT;
cparata	4:77faf76e3cd8	2428	break;
cparata	4:77faf76e3cd8	2429	default:
cparata	4:77faf76e3cd8	2430	*val = LSM6DSO_AUX_PULL_UP_DISC;
cparata	4:77faf76e3cd8	2431	break;
cparata	4:77faf76e3cd8	2432	}
cparata	4:77faf76e3cd8	2433	return ret;
cparata	0:6d69e896ce38	2434	}
cparata	0:6d69e896ce38	2435
cparata	0:6d69e896ce38	2436	/**
cparata	0:6d69e896ce38	2437	* @brief OIS chain on aux interface power on mode.[set]
cparata	0:6d69e896ce38	2438	*
cparata	0:6d69e896ce38	2439	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2440	* @param val change the values of ois_on in reg CTRL7_G
cparata	0:6d69e896ce38	2441	*
cparata	0:6d69e896ce38	2442	*/
cparata	0:6d69e896ce38	2443	int32_t lsm6dso_aux_pw_on_ctrl_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_on_t val)
cparata	0:6d69e896ce38	2444	{
cparata	4:77faf76e3cd8	2445	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	2446	int32_t ret;
cparata	4:77faf76e3cd8	2447
cparata	4:77faf76e3cd8	2448	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2449	if (ret == 0) {
cparata	4:77faf76e3cd8	2450	reg.ois_on_en = (uint8_t)val & 0x01U;
cparata	4:77faf76e3cd8	2451	reg.ois_on = (uint8_t)val & 0x01U;
cparata	4:77faf76e3cd8	2452	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2453	}
cparata	4:77faf76e3cd8	2454	return ret;
cparata	0:6d69e896ce38	2455	}
cparata	0:6d69e896ce38	2456
cparata	0:6d69e896ce38	2457	/**
cparata	0:6d69e896ce38	2458	* @brief aux_pw_on_ctrl: [get] OIS chain on aux interface power on mode
cparata	0:6d69e896ce38	2459	*
cparata	0:6d69e896ce38	2460	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2461	* @param val Get the values of ois_on in reg CTRL7_G
cparata	0:6d69e896ce38	2462	*
cparata	0:6d69e896ce38	2463	*/
cparata	0:6d69e896ce38	2464	int32_t lsm6dso_aux_pw_on_ctrl_get(lsm6dso_ctx_t ctx, lsm6dso_ois_on_t val)
cparata	0:6d69e896ce38	2465	{
cparata	4:77faf76e3cd8	2466	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	2467	int32_t ret;
cparata	4:77faf76e3cd8	2468
cparata	4:77faf76e3cd8	2469	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2470	switch (reg.ois_on) {
cparata	4:77faf76e3cd8	2471	case LSM6DSO_AUX_ON:
cparata	4:77faf76e3cd8	2472	*val = LSM6DSO_AUX_ON;
cparata	4:77faf76e3cd8	2473	break;
cparata	4:77faf76e3cd8	2474	case LSM6DSO_AUX_ON_BY_AUX_INTERFACE:
cparata	4:77faf76e3cd8	2475	*val = LSM6DSO_AUX_ON_BY_AUX_INTERFACE;
cparata	4:77faf76e3cd8	2476	break;
cparata	4:77faf76e3cd8	2477	default:
cparata	4:77faf76e3cd8	2478	*val = LSM6DSO_AUX_ON;
cparata	4:77faf76e3cd8	2479	break;
cparata	4:77faf76e3cd8	2480	}
cparata	4:77faf76e3cd8	2481
cparata	4:77faf76e3cd8	2482	return ret;
cparata	0:6d69e896ce38	2483	}
cparata	0:6d69e896ce38	2484
cparata	0:6d69e896ce38	2485	/**
cparata	0:6d69e896ce38	2486	* @brief Accelerometer full-scale management between UI chain and
cparata	0:6d69e896ce38	2487	* OIS chain. When XL UI is on, the full scale is the same
cparata	0:6d69e896ce38	2488	* between UI/OIS and is chosen by the UI CTRL registers;
cparata	0:6d69e896ce38	2489	* when XL UI is in PD, the OIS can choose the FS.
cparata	0:6d69e896ce38	2490	* Full scales are independent between the UI/OIS chain
cparata	0:6d69e896ce38	2491	* but both bound to 8 g.[set]
cparata	0:6d69e896ce38	2492	*
cparata	0:6d69e896ce38	2493	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2494	* @param val change the values of xl_fs_mode in
cparata	0:6d69e896ce38	2495	* reg CTRL8_XL
cparata	0:6d69e896ce38	2496	*
cparata	0:6d69e896ce38	2497	*/
cparata	0:6d69e896ce38	2498	int32_t lsm6dso_aux_xl_fs_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2499	lsm6dso_xl_fs_mode_t val)
cparata	0:6d69e896ce38	2500	{
cparata	4:77faf76e3cd8	2501	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2502	int32_t ret;
cparata	4:77faf76e3cd8	2503
cparata	4:77faf76e3cd8	2504	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2505	if (ret == 0) {
cparata	4:77faf76e3cd8	2506	reg.xl_fs_mode = (uint8_t)val;
cparata	4:77faf76e3cd8	2507	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2508	}
cparata	4:77faf76e3cd8	2509	return ret;
cparata	0:6d69e896ce38	2510	}
cparata	0:6d69e896ce38	2511
cparata	0:6d69e896ce38	2512	/**
cparata	0:6d69e896ce38	2513	* @brief Accelerometer full-scale management between UI chain and
cparata	0:6d69e896ce38	2514	* OIS chain. When XL UI is on, the full scale is the same
cparata	0:6d69e896ce38	2515	* between UI/OIS and is chosen by the UI CTRL registers;
cparata	0:6d69e896ce38	2516	* when XL UI is in PD, the OIS can choose the FS.
cparata	0:6d69e896ce38	2517	* Full scales are independent between the UI/OIS chain
cparata	0:6d69e896ce38	2518	* but both bound to 8 g.[get]
cparata	0:6d69e896ce38	2519	*
cparata	0:6d69e896ce38	2520	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2521	* @param val Get the values of xl_fs_mode in reg CTRL8_XL
cparata	0:6d69e896ce38	2522	*
cparata	0:6d69e896ce38	2523	*/
cparata	0:6d69e896ce38	2524	int32_t lsm6dso_aux_xl_fs_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2525	lsm6dso_xl_fs_mode_t *val)
cparata	0:6d69e896ce38	2526	{
cparata	4:77faf76e3cd8	2527	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2528	int32_t ret;
cparata	4:77faf76e3cd8	2529
cparata	4:77faf76e3cd8	2530	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2531	switch (reg.xl_fs_mode) {
cparata	4:77faf76e3cd8	2532	case LSM6DSO_USE_SAME_XL_FS:
cparata	4:77faf76e3cd8	2533	*val = LSM6DSO_USE_SAME_XL_FS;
cparata	4:77faf76e3cd8	2534	break;
cparata	4:77faf76e3cd8	2535	case LSM6DSO_USE_DIFFERENT_XL_FS:
cparata	4:77faf76e3cd8	2536	*val = LSM6DSO_USE_DIFFERENT_XL_FS;
cparata	4:77faf76e3cd8	2537	break;
cparata	4:77faf76e3cd8	2538	default:
cparata	4:77faf76e3cd8	2539	*val = LSM6DSO_USE_SAME_XL_FS;
cparata	4:77faf76e3cd8	2540	break;
cparata	4:77faf76e3cd8	2541	}
cparata	4:77faf76e3cd8	2542
cparata	4:77faf76e3cd8	2543	return ret;
cparata	0:6d69e896ce38	2544	}
cparata	0:6d69e896ce38	2545
cparata	0:6d69e896ce38	2546	/**
cparata	0:6d69e896ce38	2547	* @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
cparata	0:6d69e896ce38	2548	*
cparata	0:6d69e896ce38	2549	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2550	* @param lsm6dso_status_spiaux_t: registers STATUS_SPIAUX
cparata	0:6d69e896ce38	2551	*
cparata	0:6d69e896ce38	2552	*/
cparata	0:6d69e896ce38	2553	int32_t lsm6dso_aux_status_reg_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2554	lsm6dso_status_spiaux_t *val)
cparata	0:6d69e896ce38	2555	{
cparata	4:77faf76e3cd8	2556	int32_t ret;
cparata	4:77faf76e3cd8	2557	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*) val, 1);
cparata	4:77faf76e3cd8	2558	return ret;
cparata	0:6d69e896ce38	2559	}
cparata	0:6d69e896ce38	2560
cparata	0:6d69e896ce38	2561	/**
cparata	0:6d69e896ce38	2562	* @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available
cparata	0:6d69e896ce38	2563	*
cparata	0:6d69e896ce38	2564	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2565	* @param val change the values of xlda in reg STATUS_SPIAUX
cparata	0:6d69e896ce38	2566	*
cparata	0:6d69e896ce38	2567	*/
cparata	0:6d69e896ce38	2568	int32_t lsm6dso_aux_xl_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2569	{
cparata	4:77faf76e3cd8	2570	lsm6dso_status_spiaux_t reg;
cparata	4:77faf76e3cd8	2571	int32_t ret;
cparata	4:77faf76e3cd8	2572
cparata	4:77faf76e3cd8	2573	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2574	*val = reg.xlda;
cparata	4:77faf76e3cd8	2575
cparata	4:77faf76e3cd8	2576	return ret;
cparata	0:6d69e896ce38	2577	}
cparata	0:6d69e896ce38	2578
cparata	0:6d69e896ce38	2579	/**
cparata	0:6d69e896ce38	2580	* @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available.
cparata	0:6d69e896ce38	2581	*
cparata	0:6d69e896ce38	2582	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2583	* @param val change the values of gda in reg STATUS_SPIAUX
cparata	0:6d69e896ce38	2584	*
cparata	0:6d69e896ce38	2585	*/
cparata	0:6d69e896ce38	2586	int32_t lsm6dso_aux_gy_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2587	{
cparata	4:77faf76e3cd8	2588	lsm6dso_status_spiaux_t reg;
cparata	4:77faf76e3cd8	2589	int32_t ret;
cparata	4:77faf76e3cd8	2590
cparata	4:77faf76e3cd8	2591	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2592	*val = reg.gda;
cparata	4:77faf76e3cd8	2593
cparata	4:77faf76e3cd8	2594	return ret;
cparata	0:6d69e896ce38	2595	}
cparata	0:6d69e896ce38	2596
cparata	0:6d69e896ce38	2597	/**
cparata	0:6d69e896ce38	2598	* @brief High when the gyroscope output is in the settling phase.[get]
cparata	0:6d69e896ce38	2599	*
cparata	0:6d69e896ce38	2600	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2601	* @param val change the values of gyro_settling in reg STATUS_SPIAUX
cparata	0:6d69e896ce38	2602	*
cparata	0:6d69e896ce38	2603	*/
cparata	0:6d69e896ce38	2604	int32_t lsm6dso_aux_gy_flag_settling_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2605	{
cparata	4:77faf76e3cd8	2606	lsm6dso_status_spiaux_t reg;
cparata	4:77faf76e3cd8	2607	int32_t ret;
cparata	4:77faf76e3cd8	2608
cparata	4:77faf76e3cd8	2609	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2610	*val = reg.gyro_settling;
cparata	4:77faf76e3cd8	2611
cparata	4:77faf76e3cd8	2612	return ret;
cparata	0:6d69e896ce38	2613	}
cparata	0:6d69e896ce38	2614
cparata	0:6d69e896ce38	2615	/**
cparata	0:6d69e896ce38	2616	* @brief Selects accelerometer self-test. Effective only if XL OIS
cparata	0:6d69e896ce38	2617	* chain is enabled.[set]
cparata	0:6d69e896ce38	2618	*
cparata	0:6d69e896ce38	2619	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2620	* @param val change the values of st_xl_ois in reg INT_OIS
cparata	0:6d69e896ce38	2621	*
cparata	0:6d69e896ce38	2622	*/
cparata	0:6d69e896ce38	2623	int32_t lsm6dso_aux_xl_self_test_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2624	lsm6dso_st_xl_ois_t val)
cparata	0:6d69e896ce38	2625	{
cparata	4:77faf76e3cd8	2626	lsm6dso_int_ois_t reg;
cparata	4:77faf76e3cd8	2627	int32_t ret;
cparata	4:77faf76e3cd8	2628
cparata	4:77faf76e3cd8	2629	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2630	if (ret == 0) {
cparata	4:77faf76e3cd8	2631	reg.st_xl_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	2632	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2633	}
cparata	4:77faf76e3cd8	2634	return ret;
cparata	0:6d69e896ce38	2635	}
cparata	0:6d69e896ce38	2636
cparata	0:6d69e896ce38	2637	/**
cparata	0:6d69e896ce38	2638	* @brief Selects accelerometer self-test. Effective only if XL OIS
cparata	0:6d69e896ce38	2639	* chain is enabled.[get]
cparata	0:6d69e896ce38	2640	*
cparata	0:6d69e896ce38	2641	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2642	* @param val Get the values of st_xl_ois in reg INT_OIS
cparata	0:6d69e896ce38	2643	*
cparata	0:6d69e896ce38	2644	*/
cparata	0:6d69e896ce38	2645	int32_t lsm6dso_aux_xl_self_test_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2646	lsm6dso_st_xl_ois_t *val)
cparata	0:6d69e896ce38	2647	{
cparata	4:77faf76e3cd8	2648	lsm6dso_int_ois_t reg;
cparata	4:77faf76e3cd8	2649	int32_t ret;
cparata	4:77faf76e3cd8	2650
cparata	4:77faf76e3cd8	2651	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2652	switch (reg.st_xl_ois) {
cparata	4:77faf76e3cd8	2653	case LSM6DSO_AUX_XL_DISABLE:
cparata	4:77faf76e3cd8	2654	*val = LSM6DSO_AUX_XL_DISABLE;
cparata	4:77faf76e3cd8	2655	break;
cparata	4:77faf76e3cd8	2656	case LSM6DSO_AUX_XL_POS:
cparata	4:77faf76e3cd8	2657	*val = LSM6DSO_AUX_XL_POS;
cparata	4:77faf76e3cd8	2658	break;
cparata	4:77faf76e3cd8	2659	case LSM6DSO_AUX_XL_NEG:
cparata	4:77faf76e3cd8	2660	*val = LSM6DSO_AUX_XL_NEG;
cparata	4:77faf76e3cd8	2661	break;
cparata	4:77faf76e3cd8	2662	default:
cparata	4:77faf76e3cd8	2663	*val = LSM6DSO_AUX_XL_DISABLE;
cparata	4:77faf76e3cd8	2664	break;
cparata	4:77faf76e3cd8	2665	}
cparata	4:77faf76e3cd8	2666	return ret;
cparata	0:6d69e896ce38	2667	}
cparata	0:6d69e896ce38	2668
cparata	0:6d69e896ce38	2669	/**
cparata	0:6d69e896ce38	2670	* @brief Indicates polarity of DEN signal on OIS chain.[set]
cparata	0:6d69e896ce38	2671	*
cparata	0:6d69e896ce38	2672	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2673	* @param val change the values of den_lh_ois in
cparata	0:6d69e896ce38	2674	* reg INT_OIS
cparata	0:6d69e896ce38	2675	*
cparata	0:6d69e896ce38	2676	*/
cparata	0:6d69e896ce38	2677	int32_t lsm6dso_aux_den_polarity_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2678	lsm6dso_den_lh_ois_t val)
cparata	0:6d69e896ce38	2679	{
cparata	4:77faf76e3cd8	2680	lsm6dso_int_ois_t reg;
cparata	4:77faf76e3cd8	2681	int32_t ret;
cparata	4:77faf76e3cd8	2682
cparata	4:77faf76e3cd8	2683	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2684	if (ret == 0) {
cparata	4:77faf76e3cd8	2685	reg.den_lh_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	2686	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2687	}
cparata	4:77faf76e3cd8	2688	return ret;
cparata	0:6d69e896ce38	2689	}
cparata	0:6d69e896ce38	2690
cparata	0:6d69e896ce38	2691	/**
cparata	0:6d69e896ce38	2692	* @brief Indicates polarity of DEN signal on OIS chain.[get]
cparata	0:6d69e896ce38	2693	*
cparata	0:6d69e896ce38	2694	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2695	* @param val Get the values of den_lh_ois in reg INT_OIS
cparata	0:6d69e896ce38	2696	*
cparata	0:6d69e896ce38	2697	*/
cparata	0:6d69e896ce38	2698	int32_t lsm6dso_aux_den_polarity_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2699	lsm6dso_den_lh_ois_t *val)
cparata	0:6d69e896ce38	2700	{
cparata	4:77faf76e3cd8	2701	lsm6dso_int_ois_t reg;
cparata	4:77faf76e3cd8	2702	int32_t ret;
cparata	4:77faf76e3cd8	2703
cparata	4:77faf76e3cd8	2704	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2705	switch (reg.den_lh_ois) {
cparata	4:77faf76e3cd8	2706	case LSM6DSO_AUX_DEN_ACTIVE_LOW:
cparata	4:77faf76e3cd8	2707	*val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
cparata	4:77faf76e3cd8	2708	break;
cparata	4:77faf76e3cd8	2709	case LSM6DSO_AUX_DEN_ACTIVE_HIGH:
cparata	4:77faf76e3cd8	2710	*val = LSM6DSO_AUX_DEN_ACTIVE_HIGH;
cparata	4:77faf76e3cd8	2711	break;
cparata	4:77faf76e3cd8	2712	default:
cparata	4:77faf76e3cd8	2713	*val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
cparata	4:77faf76e3cd8	2714	break;
cparata	4:77faf76e3cd8	2715	}
cparata	4:77faf76e3cd8	2716	return ret;
cparata	0:6d69e896ce38	2717	}
cparata	0:6d69e896ce38	2718
cparata	0:6d69e896ce38	2719	/**
cparata	0:6d69e896ce38	2720	* @brief Configure DEN mode on the OIS chain.[set]
cparata	0:6d69e896ce38	2721	*
cparata	0:6d69e896ce38	2722	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2723	* @param val change the values of lvl2_ois in reg INT_OIS
cparata	0:6d69e896ce38	2724	*
cparata	0:6d69e896ce38	2725	*/
cparata	0:6d69e896ce38	2726	int32_t lsm6dso_aux_den_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_lvl2_ois_t val)
cparata	0:6d69e896ce38	2727	{
cparata	4:77faf76e3cd8	2728	lsm6dso_ctrl1_ois_t ctrl1_ois;
cparata	4:77faf76e3cd8	2729	lsm6dso_int_ois_t int_ois;
cparata	4:77faf76e3cd8	2730	int32_t ret;
cparata	4:77faf76e3cd8	2731
cparata	4:77faf76e3cd8	2732	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1);
cparata	4:77faf76e3cd8	2733	if (ret == 0) {
cparata	4:77faf76e3cd8	2734	int_ois.lvl2_ois = (uint8_t)val & 0x01U;
cparata	4:77faf76e3cd8	2735	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1);
cparata	4:77faf76e3cd8	2736	}
cparata	4:77faf76e3cd8	2737	if (ret == 0) {
cparata	4:77faf76e3cd8	2738	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata	4:77faf76e3cd8	2739	}
cparata	4:77faf76e3cd8	2740	if (ret == 0) {
cparata	4:77faf76e3cd8	2741	ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
cparata	4:77faf76e3cd8	2742	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata	4:77faf76e3cd8	2743	}
cparata	4:77faf76e3cd8	2744	return ret;
cparata	0:6d69e896ce38	2745	}
cparata	0:6d69e896ce38	2746
cparata	0:6d69e896ce38	2747	/**
cparata	0:6d69e896ce38	2748	* @brief Configure DEN mode on the OIS chain.[get]
cparata	0:6d69e896ce38	2749	*
cparata	0:6d69e896ce38	2750	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2751	* @param val Get the values of lvl2_ois in reg INT_OIS
cparata	0:6d69e896ce38	2752	*
cparata	0:6d69e896ce38	2753	*/
cparata	0:6d69e896ce38	2754	int32_t lsm6dso_aux_den_mode_get(lsm6dso_ctx_t ctx, lsm6dso_lvl2_ois_t val)
cparata	0:6d69e896ce38	2755	{
cparata	4:77faf76e3cd8	2756	lsm6dso_ctrl1_ois_t ctrl1_ois;
cparata	4:77faf76e3cd8	2757	lsm6dso_int_ois_t int_ois;
cparata	4:77faf76e3cd8	2758	int32_t ret;
cparata	4:77faf76e3cd8	2759
cparata	4:77faf76e3cd8	2760	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1);
cparata	4:77faf76e3cd8	2761	if (ret == 0) {
cparata	4:77faf76e3cd8	2762	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata	4:77faf76e3cd8	2763	switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) {
cparata	4:77faf76e3cd8	2764	case LSM6DSO_AUX_DEN_DISABLE:
cparata	4:77faf76e3cd8	2765	*val = LSM6DSO_AUX_DEN_DISABLE;
cparata	4:77faf76e3cd8	2766	break;
cparata	4:77faf76e3cd8	2767	case LSM6DSO_AUX_DEN_LEVEL_LATCH:
cparata	4:77faf76e3cd8	2768	*val = LSM6DSO_AUX_DEN_LEVEL_LATCH;
cparata	4:77faf76e3cd8	2769	break;
cparata	4:77faf76e3cd8	2770	case LSM6DSO_AUX_DEN_LEVEL_TRIG:
cparata	4:77faf76e3cd8	2771	*val = LSM6DSO_AUX_DEN_LEVEL_TRIG;
cparata	4:77faf76e3cd8	2772	break;
cparata	4:77faf76e3cd8	2773	default:
cparata	4:77faf76e3cd8	2774	*val = LSM6DSO_AUX_DEN_DISABLE;
cparata	4:77faf76e3cd8	2775	break;
cparata	3:4274d9103f1d	2776	}
cparata	4:77faf76e3cd8	2777	}
cparata	4:77faf76e3cd8	2778	return ret;
cparata	0:6d69e896ce38	2779	}
cparata	0:6d69e896ce38	2780
cparata	0:6d69e896ce38	2781	/**
cparata	0:6d69e896ce38	2782	* @brief Enables/Disable OIS chain DRDY on INT2 pin.
cparata	0:6d69e896ce38	2783	* This setting has priority over all other INT2 settings.[set]
cparata	0:6d69e896ce38	2784	*
cparata	0:6d69e896ce38	2785	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2786	* @param val change the values of int2_drdy_ois in reg INT_OIS
cparata	0:6d69e896ce38	2787	*
cparata	0:6d69e896ce38	2788	*/
cparata	0:6d69e896ce38	2789	int32_t lsm6dso_aux_drdy_on_int2_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	2790	{
cparata	4:77faf76e3cd8	2791	lsm6dso_int_ois_t reg;
cparata	4:77faf76e3cd8	2792	int32_t ret;
cparata	4:77faf76e3cd8	2793
cparata	4:77faf76e3cd8	2794	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2795	if (ret == 0) {
cparata	4:77faf76e3cd8	2796	reg.int2_drdy_ois = val;
cparata	4:77faf76e3cd8	2797	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2798	}
cparata	4:77faf76e3cd8	2799	return ret;
cparata	0:6d69e896ce38	2800	}
cparata	0:6d69e896ce38	2801
cparata	0:6d69e896ce38	2802	/**
cparata	0:6d69e896ce38	2803	* @brief Enables/Disable OIS chain DRDY on INT2 pin.
cparata	0:6d69e896ce38	2804	* This setting has priority over all other INT2 settings.[get]
cparata	0:6d69e896ce38	2805	*
cparata	0:6d69e896ce38	2806	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2807	* @param val change the values of int2_drdy_ois in reg INT_OIS
cparata	0:6d69e896ce38	2808	*
cparata	0:6d69e896ce38	2809	*/
cparata	0:6d69e896ce38	2810	int32_t lsm6dso_aux_drdy_on_int2_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2811	{
cparata	4:77faf76e3cd8	2812	lsm6dso_int_ois_t reg;
cparata	4:77faf76e3cd8	2813	int32_t ret;
cparata	4:77faf76e3cd8	2814
cparata	4:77faf76e3cd8	2815	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2816	*val = reg.int2_drdy_ois;
cparata	4:77faf76e3cd8	2817
cparata	4:77faf76e3cd8	2818	return ret;
cparata	0:6d69e896ce38	2819	}
cparata	0:6d69e896ce38	2820
cparata	0:6d69e896ce38	2821	/**
cparata	0:6d69e896ce38	2822	* @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
cparata	0:6d69e896ce38	2823	* (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
cparata	0:6d69e896ce38	2824	* When the OIS chain is enabled, the OIS outputs are available
cparata	0:6d69e896ce38	2825	* through the SPI2 in registers OUTX_L_G (22h) through
cparata	0:6d69e896ce38	2826	* OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
cparata	0:6d69e896ce38	2827	* LPF1 is dedicated to this chain.[set]
cparata	0:6d69e896ce38	2828	*
cparata	0:6d69e896ce38	2829	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2830	* @param val change the values of ois_en_spi2 in
cparata	0:6d69e896ce38	2831	* reg CTRL1_OIS
cparata	0:6d69e896ce38	2832	*
cparata	0:6d69e896ce38	2833	*/
cparata	0:6d69e896ce38	2834	int32_t lsm6dso_aux_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_en_spi2_t val)
cparata	0:6d69e896ce38	2835	{
cparata	4:77faf76e3cd8	2836	lsm6dso_ctrl1_ois_t reg;
cparata	4:77faf76e3cd8	2837	int32_t ret;
cparata	4:77faf76e3cd8	2838
cparata	4:77faf76e3cd8	2839	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2840	if (ret == 0) {
cparata	4:77faf76e3cd8	2841	reg.ois_en_spi2 = (uint8_t)val & 0x01U;
cparata	4:77faf76e3cd8	2842	reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
cparata	4:77faf76e3cd8	2843	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2844	}
cparata	4:77faf76e3cd8	2845	return ret;
cparata	0:6d69e896ce38	2846	}
cparata	0:6d69e896ce38	2847
cparata	0:6d69e896ce38	2848	/**
cparata	0:6d69e896ce38	2849	* @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
cparata	0:6d69e896ce38	2850	* (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
cparata	0:6d69e896ce38	2851	* When the OIS chain is enabled, the OIS outputs are available
cparata	0:6d69e896ce38	2852	* through the SPI2 in registers OUTX_L_G (22h) through
cparata	0:6d69e896ce38	2853	* OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
cparata	0:6d69e896ce38	2854	* LPF1 is dedicated to this chain.[get]
cparata	0:6d69e896ce38	2855	*
cparata	0:6d69e896ce38	2856	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2857	* @param val Get the values of ois_en_spi2 in
cparata	0:6d69e896ce38	2858	* reg CTRL1_OIS
cparata	0:6d69e896ce38	2859	*
cparata	0:6d69e896ce38	2860	*/
cparata	0:6d69e896ce38	2861	int32_t lsm6dso_aux_mode_get(lsm6dso_ctx_t ctx, lsm6dso_ois_en_spi2_t val)
cparata	0:6d69e896ce38	2862	{
cparata	4:77faf76e3cd8	2863	lsm6dso_ctrl1_ois_t reg;
cparata	4:77faf76e3cd8	2864	int32_t ret;
cparata	4:77faf76e3cd8	2865
cparata	4:77faf76e3cd8	2866	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2867	switch ((reg.mode4_en << 1) \| reg.ois_en_spi2) {
cparata	4:77faf76e3cd8	2868	case LSM6DSO_AUX_DISABLE:
cparata	4:77faf76e3cd8	2869	*val = LSM6DSO_AUX_DISABLE;
cparata	4:77faf76e3cd8	2870	break;
cparata	4:77faf76e3cd8	2871	case LSM6DSO_MODE_3_GY:
cparata	4:77faf76e3cd8	2872	*val = LSM6DSO_MODE_3_GY;
cparata	4:77faf76e3cd8	2873	break;
cparata	4:77faf76e3cd8	2874	case LSM6DSO_MODE_4_GY_XL:
cparata	4:77faf76e3cd8	2875	*val = LSM6DSO_MODE_4_GY_XL;
cparata	4:77faf76e3cd8	2876	break;
cparata	4:77faf76e3cd8	2877	default:
cparata	4:77faf76e3cd8	2878	*val = LSM6DSO_AUX_DISABLE;
cparata	4:77faf76e3cd8	2879	break;
cparata	4:77faf76e3cd8	2880	}
cparata	4:77faf76e3cd8	2881	return ret;
cparata	0:6d69e896ce38	2882	}
cparata	0:6d69e896ce38	2883
cparata	0:6d69e896ce38	2884	/**
cparata	0:6d69e896ce38	2885	* @brief Selects gyroscope OIS chain full-scale.[set]
cparata	0:6d69e896ce38	2886	*
cparata	0:6d69e896ce38	2887	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2888	* @param val change the values of fs_g_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2889	*
cparata	0:6d69e896ce38	2890	*/
cparata	0:6d69e896ce38	2891	int32_t lsm6dso_aux_gy_full_scale_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2892	lsm6dso_fs_g_ois_t val)
cparata	0:6d69e896ce38	2893	{
cparata	4:77faf76e3cd8	2894	lsm6dso_ctrl1_ois_t reg;
cparata	4:77faf76e3cd8	2895	int32_t ret;
cparata	4:77faf76e3cd8	2896
cparata	4:77faf76e3cd8	2897	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2898	if (ret == 0) {
cparata	4:77faf76e3cd8	2899	reg.fs_g_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	2900	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2901	}
cparata	4:77faf76e3cd8	2902	return ret;
cparata	0:6d69e896ce38	2903	}
cparata	0:6d69e896ce38	2904
cparata	0:6d69e896ce38	2905	/**
cparata	0:6d69e896ce38	2906	* @brief Selects gyroscope OIS chain full-scale.[get]
cparata	0:6d69e896ce38	2907	*
cparata	0:6d69e896ce38	2908	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2909	* @param val Get the values of fs_g_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2910	*
cparata	0:6d69e896ce38	2911	*/
cparata	0:6d69e896ce38	2912	int32_t lsm6dso_aux_gy_full_scale_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2913	lsm6dso_fs_g_ois_t *val)
cparata	0:6d69e896ce38	2914	{
cparata	4:77faf76e3cd8	2915	lsm6dso_ctrl1_ois_t reg;
cparata	4:77faf76e3cd8	2916	int32_t ret;
cparata	4:77faf76e3cd8	2917
cparata	4:77faf76e3cd8	2918	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2919	switch (reg.fs_g_ois) {
cparata	4:77faf76e3cd8	2920	case LSM6DSO_250dps_AUX:
cparata	4:77faf76e3cd8	2921	*val = LSM6DSO_250dps_AUX;
cparata	4:77faf76e3cd8	2922	break;
cparata	4:77faf76e3cd8	2923	case LSM6DSO_125dps_AUX:
cparata	4:77faf76e3cd8	2924	*val = LSM6DSO_125dps_AUX;
cparata	4:77faf76e3cd8	2925	break;
cparata	4:77faf76e3cd8	2926	case LSM6DSO_500dps_AUX:
cparata	4:77faf76e3cd8	2927	*val = LSM6DSO_500dps_AUX;
cparata	4:77faf76e3cd8	2928	break;
cparata	4:77faf76e3cd8	2929	case LSM6DSO_1000dps_AUX:
cparata	4:77faf76e3cd8	2930	*val = LSM6DSO_1000dps_AUX;
cparata	4:77faf76e3cd8	2931	break;
cparata	4:77faf76e3cd8	2932	case LSM6DSO_2000dps_AUX:
cparata	4:77faf76e3cd8	2933	*val = LSM6DSO_2000dps_AUX;
cparata	4:77faf76e3cd8	2934	break;
cparata	4:77faf76e3cd8	2935	default:
cparata	4:77faf76e3cd8	2936	*val = LSM6DSO_250dps_AUX;
cparata	4:77faf76e3cd8	2937	break;
cparata	4:77faf76e3cd8	2938	}
cparata	4:77faf76e3cd8	2939	return ret;
cparata	0:6d69e896ce38	2940	}
cparata	0:6d69e896ce38	2941
cparata	0:6d69e896ce38	2942	/**
cparata	0:6d69e896ce38	2943	* @brief SPI2 3- or 4-wire interface.[set]
cparata	0:6d69e896ce38	2944	*
cparata	0:6d69e896ce38	2945	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2946	* @param val change the values of sim_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2947	*
cparata	0:6d69e896ce38	2948	*/
cparata	0:6d69e896ce38	2949	int32_t lsm6dso_aux_spi_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sim_ois_t val)
cparata	0:6d69e896ce38	2950	{
cparata	4:77faf76e3cd8	2951	lsm6dso_ctrl1_ois_t reg;
cparata	4:77faf76e3cd8	2952	int32_t ret;
cparata	4:77faf76e3cd8	2953
cparata	4:77faf76e3cd8	2954	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2955	if (ret == 0) {
cparata	4:77faf76e3cd8	2956	reg.sim_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	2957	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2958	}
cparata	4:77faf76e3cd8	2959	return ret;
cparata	0:6d69e896ce38	2960	}
cparata	0:6d69e896ce38	2961
cparata	0:6d69e896ce38	2962	/**
cparata	0:6d69e896ce38	2963	* @brief SPI2 3- or 4-wire interface.[get]
cparata	0:6d69e896ce38	2964	*
cparata	0:6d69e896ce38	2965	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2966	* @param val Get the values of sim_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2967	*
cparata	0:6d69e896ce38	2968	*/
cparata	0:6d69e896ce38	2969	int32_t lsm6dso_aux_spi_mode_get(lsm6dso_ctx_t ctx, lsm6dso_sim_ois_t val)
cparata	0:6d69e896ce38	2970	{
cparata	4:77faf76e3cd8	2971	lsm6dso_ctrl1_ois_t reg;
cparata	4:77faf76e3cd8	2972	int32_t ret;
cparata	4:77faf76e3cd8	2973
cparata	4:77faf76e3cd8	2974	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2975	switch (reg.sim_ois) {
cparata	4:77faf76e3cd8	2976	case LSM6DSO_AUX_SPI_4_WIRE:
cparata	4:77faf76e3cd8	2977	*val = LSM6DSO_AUX_SPI_4_WIRE;
cparata	4:77faf76e3cd8	2978	break;
cparata	4:77faf76e3cd8	2979	case LSM6DSO_AUX_SPI_3_WIRE:
cparata	4:77faf76e3cd8	2980	*val = LSM6DSO_AUX_SPI_3_WIRE;
cparata	4:77faf76e3cd8	2981	break;
cparata	4:77faf76e3cd8	2982	default:
cparata	4:77faf76e3cd8	2983	*val = LSM6DSO_AUX_SPI_4_WIRE;
cparata	4:77faf76e3cd8	2984	break;
cparata	4:77faf76e3cd8	2985	}
cparata	4:77faf76e3cd8	2986	return ret;
cparata	0:6d69e896ce38	2987	}
cparata	0:6d69e896ce38	2988
cparata	0:6d69e896ce38	2989	/**
cparata	0:6d69e896ce38	2990	* @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
cparata	0:6d69e896ce38	2991	*
cparata	0:6d69e896ce38	2992	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2993	* @param val change the values of ftype_ois in
cparata	0:6d69e896ce38	2994	* reg CTRL2_OIS
cparata	0:6d69e896ce38	2995	*
cparata	0:6d69e896ce38	2996	*/
cparata	0:6d69e896ce38	2997	int32_t lsm6dso_aux_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2998	lsm6dso_ftype_ois_t val)
cparata	0:6d69e896ce38	2999	{
cparata	4:77faf76e3cd8	3000	lsm6dso_ctrl2_ois_t reg;
cparata	4:77faf76e3cd8	3001	int32_t ret;
cparata	4:77faf76e3cd8	3002
cparata	4:77faf76e3cd8	3003	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3004	if (ret == 0) {
cparata	4:77faf76e3cd8	3005	reg.ftype_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	3006	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3007	}
cparata	4:77faf76e3cd8	3008	return ret;
cparata	0:6d69e896ce38	3009	}
cparata	0:6d69e896ce38	3010
cparata	0:6d69e896ce38	3011	/**
cparata	0:6d69e896ce38	3012	* @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
cparata	0:6d69e896ce38	3013	*
cparata	0:6d69e896ce38	3014	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3015	* @param val Get the values of ftype_ois in reg CTRL2_OIS
cparata	0:6d69e896ce38	3016	*
cparata	0:6d69e896ce38	3017	*/
cparata	0:6d69e896ce38	3018	int32_t lsm6dso_aux_gy_lp1_bandwidth_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3019	lsm6dso_ftype_ois_t *val)
cparata	0:6d69e896ce38	3020	{
cparata	4:77faf76e3cd8	3021	lsm6dso_ctrl2_ois_t reg;
cparata	4:77faf76e3cd8	3022	int32_t ret;
cparata	4:77faf76e3cd8	3023
cparata	4:77faf76e3cd8	3024	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3025	switch (reg.ftype_ois) {
cparata	4:77faf76e3cd8	3026	case LSM6DSO_351Hz39:
cparata	4:77faf76e3cd8	3027	*val = LSM6DSO_351Hz39;
cparata	4:77faf76e3cd8	3028	break;
cparata	4:77faf76e3cd8	3029	case LSM6DSO_236Hz63:
cparata	4:77faf76e3cd8	3030	*val = LSM6DSO_236Hz63;
cparata	4:77faf76e3cd8	3031	break;
cparata	4:77faf76e3cd8	3032	case LSM6DSO_172Hz70:
cparata	4:77faf76e3cd8	3033	*val = LSM6DSO_172Hz70;
cparata	4:77faf76e3cd8	3034	break;
cparata	4:77faf76e3cd8	3035	case LSM6DSO_937Hz91:
cparata	4:77faf76e3cd8	3036	*val = LSM6DSO_937Hz91;
cparata	4:77faf76e3cd8	3037	break;
cparata	4:77faf76e3cd8	3038	default:
cparata	4:77faf76e3cd8	3039	*val = LSM6DSO_351Hz39;
cparata	4:77faf76e3cd8	3040	break;
cparata	4:77faf76e3cd8	3041	}
cparata	4:77faf76e3cd8	3042	return ret;
cparata	0:6d69e896ce38	3043	}
cparata	0:6d69e896ce38	3044
cparata	0:6d69e896ce38	3045	/**
cparata	0:6d69e896ce38	3046	* @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
cparata	0:6d69e896ce38	3047	*
cparata	0:6d69e896ce38	3048	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3049	* @param val change the values of hpm_ois in reg CTRL2_OIS
cparata	0:6d69e896ce38	3050	*
cparata	0:6d69e896ce38	3051	*/
cparata	0:6d69e896ce38	3052	int32_t lsm6dso_aux_gy_hp_bandwidth_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3053	lsm6dso_hpm_ois_t val)
cparata	0:6d69e896ce38	3054	{
cparata	4:77faf76e3cd8	3055	lsm6dso_ctrl2_ois_t reg;
cparata	4:77faf76e3cd8	3056	int32_t ret;
cparata	4:77faf76e3cd8	3057
cparata	4:77faf76e3cd8	3058	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3059	if (ret == 0) {
cparata	4:77faf76e3cd8	3060	reg.hpm_ois = (uint8_t)val & 0x03U;
cparata	4:77faf76e3cd8	3061	reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
cparata	4:77faf76e3cd8	3062	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3063	}
cparata	4:77faf76e3cd8	3064	return ret;
cparata	0:6d69e896ce38	3065	}
cparata	0:6d69e896ce38	3066
cparata	0:6d69e896ce38	3067	/**
cparata	0:6d69e896ce38	3068	* @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
cparata	0:6d69e896ce38	3069	*
cparata	0:6d69e896ce38	3070	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3071	* @param val Get the values of hpm_ois in reg CTRL2_OIS
cparata	0:6d69e896ce38	3072	*
cparata	0:6d69e896ce38	3073	*/
cparata	0:6d69e896ce38	3074	int32_t lsm6dso_aux_gy_hp_bandwidth_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3075	lsm6dso_hpm_ois_t *val)
cparata	0:6d69e896ce38	3076	{
cparata	4:77faf76e3cd8	3077	lsm6dso_ctrl2_ois_t reg;
cparata	4:77faf76e3cd8	3078	int32_t ret;
cparata	4:77faf76e3cd8	3079
cparata	4:77faf76e3cd8	3080	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3081	switch ((reg.hp_en_ois << 4) \| reg.hpm_ois) {
cparata	4:77faf76e3cd8	3082	case LSM6DSO_AUX_HP_DISABLE:
cparata	4:77faf76e3cd8	3083	*val = LSM6DSO_AUX_HP_DISABLE;
cparata	4:77faf76e3cd8	3084	break;
cparata	4:77faf76e3cd8	3085	case LSM6DSO_AUX_HP_Hz016:
cparata	4:77faf76e3cd8	3086	*val = LSM6DSO_AUX_HP_Hz016;
cparata	4:77faf76e3cd8	3087	break;
cparata	4:77faf76e3cd8	3088	case LSM6DSO_AUX_HP_Hz065:
cparata	4:77faf76e3cd8	3089	*val = LSM6DSO_AUX_HP_Hz065;
cparata	4:77faf76e3cd8	3090	break;
cparata	4:77faf76e3cd8	3091	case LSM6DSO_AUX_HP_Hz260:
cparata	4:77faf76e3cd8	3092	*val = LSM6DSO_AUX_HP_Hz260;
cparata	4:77faf76e3cd8	3093	break;
cparata	4:77faf76e3cd8	3094	case LSM6DSO_AUX_HP_1Hz040:
cparata	4:77faf76e3cd8	3095	*val = LSM6DSO_AUX_HP_1Hz040;
cparata	4:77faf76e3cd8	3096	break;
cparata	4:77faf76e3cd8	3097	default:
cparata	4:77faf76e3cd8	3098	*val = LSM6DSO_AUX_HP_DISABLE;
cparata	4:77faf76e3cd8	3099	break;
cparata	4:77faf76e3cd8	3100	}
cparata	4:77faf76e3cd8	3101	return ret;
cparata	0:6d69e896ce38	3102	}
cparata	0:6d69e896ce38	3103
cparata	0:6d69e896ce38	3104	/**
cparata	0:6d69e896ce38	3105	* @brief Enable / Disables OIS chain clamp.
cparata	0:6d69e896ce38	3106	* Enable: All OIS chain outputs = 8000h
cparata	0:6d69e896ce38	3107	* during self-test; Disable: OIS chain self-test
cparata	0:6d69e896ce38	3108	* outputs dependent from the aux gyro full
cparata	0:6d69e896ce38	3109	* scale selected.[set]
cparata	0:6d69e896ce38	3110	*
cparata	0:6d69e896ce38	3111	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3112	* @param val change the values of st_ois_clampdis in
cparata	0:6d69e896ce38	3113	* reg CTRL3_OIS
cparata	0:6d69e896ce38	3114	*
cparata	0:6d69e896ce38	3115	*/
cparata	0:6d69e896ce38	3116	int32_t lsm6dso_aux_gy_clamp_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3117	lsm6dso_st_ois_clampdis_t val)
cparata	0:6d69e896ce38	3118	{
cparata	4:77faf76e3cd8	3119	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3120	int32_t ret;
cparata	4:77faf76e3cd8	3121
cparata	4:77faf76e3cd8	3122	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3123	if (ret == 0) {
cparata	4:77faf76e3cd8	3124	reg.st_ois_clampdis = (uint8_t)val;
cparata	4:77faf76e3cd8	3125	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3126	}
cparata	4:77faf76e3cd8	3127	return ret;
cparata	0:6d69e896ce38	3128	}
cparata	0:6d69e896ce38	3129
cparata	0:6d69e896ce38	3130	/**
cparata	0:6d69e896ce38	3131	* @brief Enable / Disables OIS chain clamp.
cparata	0:6d69e896ce38	3132	* Enable: All OIS chain outputs = 8000h
cparata	0:6d69e896ce38	3133	* during self-test; Disable: OIS chain self-test
cparata	0:6d69e896ce38	3134	* outputs dependent from the aux gyro full
cparata	0:6d69e896ce38	3135	* scale selected.[set]
cparata	0:6d69e896ce38	3136	*
cparata	0:6d69e896ce38	3137	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3138	* @param val Get the values of st_ois_clampdis in
cparata	0:6d69e896ce38	3139	* reg CTRL3_OIS
cparata	0:6d69e896ce38	3140	*
cparata	0:6d69e896ce38	3141	*/
cparata	0:6d69e896ce38	3142	int32_t lsm6dso_aux_gy_clamp_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3143	lsm6dso_st_ois_clampdis_t *val)
cparata	0:6d69e896ce38	3144	{
cparata	4:77faf76e3cd8	3145	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3146	int32_t ret;
cparata	4:77faf76e3cd8	3147
cparata	4:77faf76e3cd8	3148	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3149	switch (reg.st_ois_clampdis) {
cparata	4:77faf76e3cd8	3150	case LSM6DSO_ENABLE_CLAMP:
cparata	4:77faf76e3cd8	3151	*val = LSM6DSO_ENABLE_CLAMP;
cparata	4:77faf76e3cd8	3152	break;
cparata	4:77faf76e3cd8	3153	case LSM6DSO_DISABLE_CLAMP:
cparata	4:77faf76e3cd8	3154	*val = LSM6DSO_DISABLE_CLAMP;
cparata	4:77faf76e3cd8	3155	break;
cparata	4:77faf76e3cd8	3156	default:
cparata	4:77faf76e3cd8	3157	*val = LSM6DSO_ENABLE_CLAMP;
cparata	4:77faf76e3cd8	3158	break;
cparata	4:77faf76e3cd8	3159	}
cparata	4:77faf76e3cd8	3160	return ret;
cparata	0:6d69e896ce38	3161	}
cparata	0:6d69e896ce38	3162
cparata	0:6d69e896ce38	3163	/**
cparata	0:6d69e896ce38	3164	* @brief Selects gyroscope OIS chain self-test.[set]
cparata	0:6d69e896ce38	3165	*
cparata	0:6d69e896ce38	3166	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3167	* @param val change the values of st_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3168	*
cparata	0:6d69e896ce38	3169	*/
cparata	0:6d69e896ce38	3170	int32_t lsm6dso_aux_gy_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_ois_t val)
cparata	0:6d69e896ce38	3171	{
cparata	4:77faf76e3cd8	3172	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3173	int32_t ret;
cparata	4:77faf76e3cd8	3174
cparata	4:77faf76e3cd8	3175	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3176	if (ret == 0) {
cparata	4:77faf76e3cd8	3177	reg.st_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	3178	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3179	}
cparata	4:77faf76e3cd8	3180	return ret;
cparata	0:6d69e896ce38	3181	}
cparata	0:6d69e896ce38	3182
cparata	0:6d69e896ce38	3183	/**
cparata	0:6d69e896ce38	3184	* @brief Selects gyroscope OIS chain self-test.[get]
cparata	0:6d69e896ce38	3185	*
cparata	0:6d69e896ce38	3186	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3187	* @param val Get the values of st_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3188	*
cparata	0:6d69e896ce38	3189	*/
cparata	0:6d69e896ce38	3190	int32_t lsm6dso_aux_gy_self_test_get(lsm6dso_ctx_t ctx, lsm6dso_st_ois_t val)
cparata	0:6d69e896ce38	3191	{
cparata	4:77faf76e3cd8	3192	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3193	int32_t ret;
cparata	4:77faf76e3cd8	3194
cparata	4:77faf76e3cd8	3195	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3196	switch (reg.st_ois) {
cparata	4:77faf76e3cd8	3197	case LSM6DSO_AUX_GY_DISABLE:
cparata	4:77faf76e3cd8	3198	*val = LSM6DSO_AUX_GY_DISABLE;
cparata	4:77faf76e3cd8	3199	break;
cparata	4:77faf76e3cd8	3200	case LSM6DSO_AUX_GY_POS:
cparata	4:77faf76e3cd8	3201	*val = LSM6DSO_AUX_GY_POS;
cparata	4:77faf76e3cd8	3202	break;
cparata	4:77faf76e3cd8	3203	case LSM6DSO_AUX_GY_NEG:
cparata	4:77faf76e3cd8	3204	*val = LSM6DSO_AUX_GY_NEG;
cparata	4:77faf76e3cd8	3205	break;
cparata	4:77faf76e3cd8	3206	default:
cparata	4:77faf76e3cd8	3207	*val = LSM6DSO_AUX_GY_DISABLE;
cparata	4:77faf76e3cd8	3208	break;
cparata	4:77faf76e3cd8	3209	}
cparata	4:77faf76e3cd8	3210	return ret;
cparata	0:6d69e896ce38	3211	}
cparata	0:6d69e896ce38	3212
cparata	0:6d69e896ce38	3213	/**
cparata	0:6d69e896ce38	3214	* @brief Selects accelerometer OIS channel bandwidth.[set]
cparata	0:6d69e896ce38	3215	*
cparata	0:6d69e896ce38	3216	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3217	* @param val change the values of
cparata	0:6d69e896ce38	3218	* filter_xl_conf_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3219	*
cparata	0:6d69e896ce38	3220	*/
cparata	0:6d69e896ce38	3221	int32_t lsm6dso_aux_xl_bandwidth_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3222	lsm6dso_filter_xl_conf_ois_t val)
cparata	0:6d69e896ce38	3223	{
cparata	4:77faf76e3cd8	3224	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3225	int32_t ret;
cparata	4:77faf76e3cd8	3226
cparata	4:77faf76e3cd8	3227	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3228	if (ret == 0) {
cparata	4:77faf76e3cd8	3229	reg.filter_xl_conf_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	3230	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3231	}
cparata	4:77faf76e3cd8	3232	return ret;
cparata	0:6d69e896ce38	3233	}
cparata	0:6d69e896ce38	3234
cparata	0:6d69e896ce38	3235	/**
cparata	0:6d69e896ce38	3236	* @brief Selects accelerometer OIS channel bandwidth.[get]
cparata	0:6d69e896ce38	3237	*
cparata	0:6d69e896ce38	3238	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3239	* @param val Get the values of
cparata	0:6d69e896ce38	3240	* filter_xl_conf_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3241	*
cparata	0:6d69e896ce38	3242	*/
cparata	0:6d69e896ce38	3243	int32_t lsm6dso_aux_xl_bandwidth_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3244	lsm6dso_filter_xl_conf_ois_t *val)
cparata	0:6d69e896ce38	3245	{
cparata	4:77faf76e3cd8	3246	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3247	int32_t ret;
cparata	4:77faf76e3cd8	3248
cparata	4:77faf76e3cd8	3249	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3250
cparata	4:77faf76e3cd8	3251	switch (reg.filter_xl_conf_ois) {
cparata	4:77faf76e3cd8	3252	case LSM6DSO_289Hz:
cparata	4:77faf76e3cd8	3253	*val = LSM6DSO_289Hz;
cparata	4:77faf76e3cd8	3254	break;
cparata	4:77faf76e3cd8	3255	case LSM6DSO_258Hz:
cparata	4:77faf76e3cd8	3256	*val = LSM6DSO_258Hz;
cparata	4:77faf76e3cd8	3257	break;
cparata	4:77faf76e3cd8	3258	case LSM6DSO_120Hz:
cparata	4:77faf76e3cd8	3259	*val = LSM6DSO_120Hz;
cparata	4:77faf76e3cd8	3260	break;
cparata	4:7