LSM6DSO - iNEMO inertial module: 3D accelerometer and 3D gy…

ST » Code » LSM6DSO

iNEMO inertial module: 3D accelerometer and 3D gyroscope.

Dependencies: X_NUCLEO_COMMON ST_INTERFACES

Dependents: X_NUCLEO_IKS01A3 X_NUCLEO_IKS01A3

lsm6dso_reg.c@3:4274d9103f1d, 2019-07-24 (annotated)

Committer:: cparata
Date:: Wed Jul 24 14:19:35 2019 +0000
Revision:: 3:4274d9103f1d
Parent:: 2:4d14e9edf37e
Child:: 4:77faf76e3cd8

Format with Astyle

Who changed what in which revision?

User	Revision	Line number	New contents of line
cparata	0:6d69e896ce38	1	/*
cparata	0:6d69e896ce38	2	******************************************************************************
cparata	0:6d69e896ce38	3	* @file lsm6dso_reg.c
cparata	0:6d69e896ce38	4	* @author Sensor Solutions Software Team
cparata	0:6d69e896ce38	5	* @brief LSM6DSO driver file
cparata	0:6d69e896ce38	6	******************************************************************************
cparata	0:6d69e896ce38	7	* @attention
cparata	0:6d69e896ce38	8	*
cparata	0:6d69e896ce38	9	* <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
cparata	0:6d69e896ce38	10	*
cparata	0:6d69e896ce38	11	* Redistribution and use in source and binary forms, with or without
cparata	0:6d69e896ce38	12	* modification, are permitted provided that the following conditions
cparata	0:6d69e896ce38	13	* are met:
cparata	0:6d69e896ce38	14	* 1. Redistributions of source code must retain the above copyright notice,
cparata	0:6d69e896ce38	15	* this list of conditions and the following disclaimer.
cparata	0:6d69e896ce38	16	* 2. Redistributions in binary form must reproduce the above copyright
cparata	0:6d69e896ce38	17	* notice, this list of conditions and the following disclaimer in the
cparata	0:6d69e896ce38	18	* documentation and/or other materials provided with the distribution.
cparata	0:6d69e896ce38	19	* 3. Neither the name of STMicroelectronics nor the names of its
cparata	0:6d69e896ce38	20	* contributors may be used to endorse or promote products derived from
cparata	0:6d69e896ce38	21	* this software without specific prior written permission.
cparata	0:6d69e896ce38	22	*
cparata	0:6d69e896ce38	23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
cparata	0:6d69e896ce38	24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
cparata	0:6d69e896ce38	25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
cparata	0:6d69e896ce38	26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
cparata	0:6d69e896ce38	27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
cparata	0:6d69e896ce38	28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
cparata	0:6d69e896ce38	29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
cparata	0:6d69e896ce38	30	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
cparata	0:6d69e896ce38	31	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
cparata	0:6d69e896ce38	32	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
cparata	0:6d69e896ce38	33	* POSSIBILITY OF SUCH DAMAGE.
cparata	0:6d69e896ce38	34	*
cparata	0:6d69e896ce38	35	*/
cparata	0:6d69e896ce38	36
cparata	0:6d69e896ce38	37	#include "lsm6dso_reg.h"
cparata	0:6d69e896ce38	38
cparata	0:6d69e896ce38	39	/**
cparata	0:6d69e896ce38	40	* @defgroup LSM6DSO
cparata	0:6d69e896ce38	41	* @brief This file provides a set of functions needed to drive the
cparata	0:6d69e896ce38	42	* lsm6dso enhanced inertial module.
cparata	0:6d69e896ce38	43	* @{
cparata	0:6d69e896ce38	44	*
cparata	0:6d69e896ce38	45	*/
cparata	0:6d69e896ce38	46
cparata	0:6d69e896ce38	47	/**
cparata	0:6d69e896ce38	48	* @defgroup LSM6DSO_Interfaces_Functions
cparata	0:6d69e896ce38	49	* @brief This section provide a set of functions used to read and
cparata	0:6d69e896ce38	50	* write a generic register of the device.
cparata	0:6d69e896ce38	51	* MANDATORY: return 0 -> no Error.
cparata	0:6d69e896ce38	52	* @{
cparata	0:6d69e896ce38	53	*
cparata	0:6d69e896ce38	54	*/
cparata	0:6d69e896ce38	55
cparata	0:6d69e896ce38	56	/**
cparata	0:6d69e896ce38	57	* @brief Read generic device register
cparata	0:6d69e896ce38	58	*
cparata	0:6d69e896ce38	59	* @param ctx read / write interface definitions(ptr)
cparata	0:6d69e896ce38	60	* @param reg register to read
cparata	0:6d69e896ce38	61	* @param data pointer to buffer that store the data read(ptr)
cparata	0:6d69e896ce38	62	* @param len number of consecutive register to read
cparata	0:6d69e896ce38	63	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:6d69e896ce38	64	*
cparata	0:6d69e896ce38	65	*/
cparata	3:4274d9103f1d	66	int32_t lsm6dso_read_reg(lsm6dso_ctx_t ctx, uint8_t reg, uint8_t data,
cparata	0:6d69e896ce38	67	uint16_t len)
cparata	0:6d69e896ce38	68	{
cparata	3:4274d9103f1d	69	int32_t ret;
cparata	3:4274d9103f1d	70	ret = ctx->read_reg(ctx->handle, reg, data, len);
cparata	3:4274d9103f1d	71	return ret;
cparata	0:6d69e896ce38	72	}
cparata	0:6d69e896ce38	73
cparata	0:6d69e896ce38	74	/**
cparata	0:6d69e896ce38	75	* @brief Write generic device register
cparata	0:6d69e896ce38	76	*
cparata	0:6d69e896ce38	77	* @param ctx read / write interface definitions(ptr)
cparata	0:6d69e896ce38	78	* @param reg register to write
cparata	0:6d69e896ce38	79	* @param data pointer to data to write in register reg(ptr)
cparata	0:6d69e896ce38	80	* @param len number of consecutive register to write
cparata	0:6d69e896ce38	81	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:6d69e896ce38	82	*
cparata	0:6d69e896ce38	83	*/
cparata	3:4274d9103f1d	84	int32_t lsm6dso_write_reg(lsm6dso_ctx_t ctx, uint8_t reg, uint8_t data,
cparata	0:6d69e896ce38	85	uint16_t len)
cparata	0:6d69e896ce38	86	{
cparata	3:4274d9103f1d	87	int32_t ret;
cparata	3:4274d9103f1d	88	ret = ctx->write_reg(ctx->handle, reg, data, len);
cparata	3:4274d9103f1d	89	return ret;
cparata	0:6d69e896ce38	90	}
cparata	0:6d69e896ce38	91
cparata	0:6d69e896ce38	92	/**
cparata	0:6d69e896ce38	93	* @}
cparata	0:6d69e896ce38	94	*
cparata	0:6d69e896ce38	95	*/
cparata	0:6d69e896ce38	96
cparata	0:6d69e896ce38	97	/**
cparata	0:6d69e896ce38	98	* @defgroup LSM6DSO_Sensitivity
cparata	0:6d69e896ce38	99	* @brief These functions convert raw-data into engineering units.
cparata	0:6d69e896ce38	100	* @{
cparata	0:6d69e896ce38	101	*
cparata	0:6d69e896ce38	102	*/
cparata	2:4d14e9edf37e	103	float_t lsm6dso_from_fs2_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	104	{
cparata	3:4274d9103f1d	105	return ((float_t)lsb) * 0.061f;
cparata	2:4d14e9edf37e	106	}
cparata	2:4d14e9edf37e	107
cparata	2:4d14e9edf37e	108	float_t lsm6dso_from_fs4_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	109	{
cparata	3:4274d9103f1d	110	return ((float_t)lsb) * 0.122f;
cparata	2:4d14e9edf37e	111	}
cparata	2:4d14e9edf37e	112
cparata	2:4d14e9edf37e	113	float_t lsm6dso_from_fs8_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	114	{
cparata	3:4274d9103f1d	115	return ((float_t)lsb) * 0.244f;
cparata	2:4d14e9edf37e	116	}
cparata	2:4d14e9edf37e	117
cparata	2:4d14e9edf37e	118	float_t lsm6dso_from_fs16_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	119	{
cparata	3:4274d9103f1d	120	return ((float_t)lsb) * 0.488f;
cparata	2:4d14e9edf37e	121	}
cparata	2:4d14e9edf37e	122
cparata	2:4d14e9edf37e	123	float_t lsm6dso_from_fs125_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	124	{
cparata	3:4274d9103f1d	125	return ((float_t)lsb) * 4.375f;
cparata	2:4d14e9edf37e	126	}
cparata	2:4d14e9edf37e	127
cparata	2:4d14e9edf37e	128	float_t lsm6dso_from_fs500_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	129	{
cparata	3:4274d9103f1d	130	return ((float_t)lsb) * 17.50f;
cparata	2:4d14e9edf37e	131	}
cparata	2:4d14e9edf37e	132
cparata	2:4d14e9edf37e	133	float_t lsm6dso_from_fs250_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	134	{
cparata	3:4274d9103f1d	135	return ((float_t)lsb) * 8.750f;
cparata	2:4d14e9edf37e	136	}
cparata	2:4d14e9edf37e	137
cparata	2:4d14e9edf37e	138	float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	139	{
cparata	3:4274d9103f1d	140	return ((float_t)lsb) * 35.0f;
cparata	2:4d14e9edf37e	141	}
cparata	2:4d14e9edf37e	142
cparata	2:4d14e9edf37e	143	float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	144	{
cparata	3:4274d9103f1d	145	return ((float_t)lsb) * 70.0f;
cparata	2:4d14e9edf37e	146	}
cparata	2:4d14e9edf37e	147
cparata	2:4d14e9edf37e	148	float_t lsm6dso_from_lsb_to_celsius(int16_t lsb)
cparata	2:4d14e9edf37e	149	{
cparata	3:4274d9103f1d	150	return (((float_t)lsb / 256.0f) + 25.0f);
cparata	2:4d14e9edf37e	151	}
cparata	2:4d14e9edf37e	152
cparata	2:4d14e9edf37e	153	float_t lsm6dso_from_lsb_to_nsec(int16_t lsb)
cparata	2:4d14e9edf37e	154	{
cparata	3:4274d9103f1d	155	return ((float_t)lsb * 25000.0f);
cparata	0:6d69e896ce38	156	}
cparata	0:6d69e896ce38	157
cparata	0:6d69e896ce38	158	/**
cparata	0:6d69e896ce38	159	* @}
cparata	0:6d69e896ce38	160	*
cparata	0:6d69e896ce38	161	*/
cparata	0:6d69e896ce38	162
cparata	0:6d69e896ce38	163	/**
cparata	0:6d69e896ce38	164	* @defgroup LSM6DSO_Data_Generation
cparata	0:6d69e896ce38	165	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	166	* data generation.
cparata	0:6d69e896ce38	167	*
cparata	0:6d69e896ce38	168	*/
cparata	0:6d69e896ce38	169
cparata	0:6d69e896ce38	170	/**
cparata	0:6d69e896ce38	171	* @brief Accelerometer full-scale selection.[set]
cparata	0:6d69e896ce38	172	*
cparata	0:6d69e896ce38	173	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	174	* @param val change the values of fs_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	175	*
cparata	0:6d69e896ce38	176	*/
cparata	0:6d69e896ce38	177	int32_t lsm6dso_xl_full_scale_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	178	lsm6dso_fs_xl_t val)
cparata	0:6d69e896ce38	179	{
cparata	3:4274d9103f1d	180	lsm6dso_ctrl1_xl_t reg;
cparata	3:4274d9103f1d	181	int32_t ret;
cparata	3:4274d9103f1d	182
cparata	3:4274d9103f1d	183	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	184	if (ret == 0) {
cparata	3:4274d9103f1d	185	reg.fs_xl = (uint8_t) val;
cparata	3:4274d9103f1d	186	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	187	}
cparata	3:4274d9103f1d	188	return ret;
cparata	0:6d69e896ce38	189	}
cparata	0:6d69e896ce38	190
cparata	0:6d69e896ce38	191	/**
cparata	0:6d69e896ce38	192	* @brief Accelerometer full-scale selection.[get]
cparata	0:6d69e896ce38	193	*
cparata	0:6d69e896ce38	194	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	195	* @param val Get the values of fs_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	196	*
cparata	0:6d69e896ce38	197	*/
cparata	0:6d69e896ce38	198	int32_t lsm6dso_xl_full_scale_get(lsm6dso_ctx_t ctx, lsm6dso_fs_xl_t val)
cparata	0:6d69e896ce38	199	{
cparata	3:4274d9103f1d	200	lsm6dso_ctrl1_xl_t reg;
cparata	3:4274d9103f1d	201	int32_t ret;
cparata	3:4274d9103f1d	202
cparata	3:4274d9103f1d	203	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	204	switch (reg.fs_xl) {
cparata	3:4274d9103f1d	205	case LSM6DSO_2g:
cparata	3:4274d9103f1d	206	*val = LSM6DSO_2g;
cparata	3:4274d9103f1d	207	break;
cparata	3:4274d9103f1d	208	case LSM6DSO_16g:
cparata	3:4274d9103f1d	209	*val = LSM6DSO_16g;
cparata	3:4274d9103f1d	210	break;
cparata	3:4274d9103f1d	211	case LSM6DSO_4g:
cparata	3:4274d9103f1d	212	*val = LSM6DSO_4g;
cparata	3:4274d9103f1d	213	break;
cparata	3:4274d9103f1d	214	case LSM6DSO_8g:
cparata	3:4274d9103f1d	215	*val = LSM6DSO_8g;
cparata	3:4274d9103f1d	216	break;
cparata	3:4274d9103f1d	217	default:
cparata	3:4274d9103f1d	218	*val = LSM6DSO_2g;
cparata	3:4274d9103f1d	219	break;
cparata	3:4274d9103f1d	220	}
cparata	3:4274d9103f1d	221
cparata	3:4274d9103f1d	222	return ret;
cparata	0:6d69e896ce38	223	}
cparata	0:6d69e896ce38	224
cparata	0:6d69e896ce38	225	/**
cparata	0:6d69e896ce38	226	* @brief Accelerometer UI data rate selection.[set]
cparata	0:6d69e896ce38	227	*
cparata	0:6d69e896ce38	228	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	229	* @param val change the values of odr_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	230	*
cparata	0:6d69e896ce38	231	*/
cparata	0:6d69e896ce38	232	int32_t lsm6dso_xl_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_xl_t val)
cparata	0:6d69e896ce38	233	{
cparata	3:4274d9103f1d	234	lsm6dso_ctrl1_xl_t reg;
cparata	3:4274d9103f1d	235	int32_t ret;
cparata	3:4274d9103f1d	236
cparata	3:4274d9103f1d	237	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	238	if (ret == 0) {
cparata	3:4274d9103f1d	239	reg.odr_xl = (uint8_t) val;
cparata	3:4274d9103f1d	240	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	241	}
cparata	3:4274d9103f1d	242	return ret;
cparata	0:6d69e896ce38	243	}
cparata	0:6d69e896ce38	244
cparata	0:6d69e896ce38	245	/**
cparata	0:6d69e896ce38	246	* @brief Accelerometer UI data rate selection.[get]
cparata	0:6d69e896ce38	247	*
cparata	0:6d69e896ce38	248	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	249	* @param val Get the values of odr_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	250	*
cparata	0:6d69e896ce38	251	*/
cparata	0:6d69e896ce38	252	int32_t lsm6dso_xl_data_rate_get(lsm6dso_ctx_t ctx, lsm6dso_odr_xl_t val)
cparata	0:6d69e896ce38	253	{
cparata	3:4274d9103f1d	254	lsm6dso_ctrl1_xl_t reg;
cparata	3:4274d9103f1d	255	int32_t ret;
cparata	3:4274d9103f1d	256
cparata	3:4274d9103f1d	257	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	258
cparata	3:4274d9103f1d	259	switch (reg.odr_xl) {
cparata	3:4274d9103f1d	260	case LSM6DSO_XL_ODR_OFF:
cparata	3:4274d9103f1d	261	*val = LSM6DSO_XL_ODR_OFF;
cparata	3:4274d9103f1d	262	break;
cparata	3:4274d9103f1d	263	case LSM6DSO_XL_ODR_12Hz5:
cparata	3:4274d9103f1d	264	*val = LSM6DSO_XL_ODR_12Hz5;
cparata	3:4274d9103f1d	265	break;
cparata	3:4274d9103f1d	266	case LSM6DSO_XL_ODR_26Hz:
cparata	3:4274d9103f1d	267	*val = LSM6DSO_XL_ODR_26Hz;
cparata	3:4274d9103f1d	268	break;
cparata	3:4274d9103f1d	269	case LSM6DSO_XL_ODR_52Hz:
cparata	3:4274d9103f1d	270	*val = LSM6DSO_XL_ODR_52Hz;
cparata	3:4274d9103f1d	271	break;
cparata	3:4274d9103f1d	272	case LSM6DSO_XL_ODR_104Hz:
cparata	3:4274d9103f1d	273	*val = LSM6DSO_XL_ODR_104Hz;
cparata	3:4274d9103f1d	274	break;
cparata	3:4274d9103f1d	275	case LSM6DSO_XL_ODR_208Hz:
cparata	3:4274d9103f1d	276	*val = LSM6DSO_XL_ODR_208Hz;
cparata	3:4274d9103f1d	277	break;
cparata	3:4274d9103f1d	278	case LSM6DSO_XL_ODR_417Hz:
cparata	3:4274d9103f1d	279	*val = LSM6DSO_XL_ODR_417Hz;
cparata	3:4274d9103f1d	280	break;
cparata	3:4274d9103f1d	281	case LSM6DSO_XL_ODR_833Hz:
cparata	3:4274d9103f1d	282	*val = LSM6DSO_XL_ODR_833Hz;
cparata	3:4274d9103f1d	283	break;
cparata	3:4274d9103f1d	284	case LSM6DSO_XL_ODR_1667Hz:
cparata	3:4274d9103f1d	285	*val = LSM6DSO_XL_ODR_1667Hz;
cparata	3:4274d9103f1d	286	break;
cparata	3:4274d9103f1d	287	case LSM6DSO_XL_ODR_3333Hz:
cparata	3:4274d9103f1d	288	*val = LSM6DSO_XL_ODR_3333Hz;
cparata	3:4274d9103f1d	289	break;
cparata	3:4274d9103f1d	290	case LSM6DSO_XL_ODR_6667Hz:
cparata	3:4274d9103f1d	291	*val = LSM6DSO_XL_ODR_6667Hz;
cparata	3:4274d9103f1d	292	break;
cparata	3:4274d9103f1d	293	case LSM6DSO_XL_ODR_6Hz5:
cparata	3:4274d9103f1d	294	*val = LSM6DSO_XL_ODR_6Hz5;
cparata	3:4274d9103f1d	295	break;
cparata	3:4274d9103f1d	296	default:
cparata	3:4274d9103f1d	297	*val = LSM6DSO_XL_ODR_OFF;
cparata	3:4274d9103f1d	298	break;
cparata	3:4274d9103f1d	299	}
cparata	3:4274d9103f1d	300	return ret;
cparata	0:6d69e896ce38	301	}
cparata	0:6d69e896ce38	302
cparata	0:6d69e896ce38	303	/**
cparata	0:6d69e896ce38	304	* @brief Gyroscope UI chain full-scale selection.[set]
cparata	0:6d69e896ce38	305	*
cparata	0:6d69e896ce38	306	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	307	* @param val change the values of fs_g in reg CTRL2_G
cparata	0:6d69e896ce38	308	*
cparata	0:6d69e896ce38	309	*/
cparata	0:6d69e896ce38	310	int32_t lsm6dso_gy_full_scale_set(lsm6dso_ctx_t *ctx, lsm6dso_fs_g_t val)
cparata	0:6d69e896ce38	311	{
cparata	3:4274d9103f1d	312	lsm6dso_ctrl2_g_t reg;
cparata	3:4274d9103f1d	313	int32_t ret;
cparata	3:4274d9103f1d	314
cparata	3:4274d9103f1d	315	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	316	if (ret == 0) {
cparata	3:4274d9103f1d	317	reg.fs_g = (uint8_t) val;
cparata	3:4274d9103f1d	318	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	319	}
cparata	3:4274d9103f1d	320
cparata	3:4274d9103f1d	321	return ret;
cparata	0:6d69e896ce38	322	}
cparata	0:6d69e896ce38	323
cparata	0:6d69e896ce38	324	/**
cparata	0:6d69e896ce38	325	* @brief Gyroscope UI chain full-scale selection.[get]
cparata	0:6d69e896ce38	326	*
cparata	0:6d69e896ce38	327	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	328	* @param val Get the values of fs_g in reg CTRL2_G
cparata	0:6d69e896ce38	329	*
cparata	0:6d69e896ce38	330	*/
cparata	0:6d69e896ce38	331	int32_t lsm6dso_gy_full_scale_get(lsm6dso_ctx_t ctx, lsm6dso_fs_g_t val)
cparata	0:6d69e896ce38	332	{
cparata	3:4274d9103f1d	333	lsm6dso_ctrl2_g_t reg;
cparata	3:4274d9103f1d	334	int32_t ret;
cparata	3:4274d9103f1d	335
cparata	3:4274d9103f1d	336	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	337	switch (reg.fs_g) {
cparata	3:4274d9103f1d	338	case LSM6DSO_250dps:
cparata	3:4274d9103f1d	339	*val = LSM6DSO_250dps;
cparata	3:4274d9103f1d	340	break;
cparata	3:4274d9103f1d	341	case LSM6DSO_125dps:
cparata	3:4274d9103f1d	342	*val = LSM6DSO_125dps;
cparata	3:4274d9103f1d	343	break;
cparata	3:4274d9103f1d	344	case LSM6DSO_500dps:
cparata	3:4274d9103f1d	345	*val = LSM6DSO_500dps;
cparata	3:4274d9103f1d	346	break;
cparata	3:4274d9103f1d	347	case LSM6DSO_1000dps:
cparata	3:4274d9103f1d	348	*val = LSM6DSO_1000dps;
cparata	3:4274d9103f1d	349	break;
cparata	3:4274d9103f1d	350	case LSM6DSO_2000dps:
cparata	3:4274d9103f1d	351	*val = LSM6DSO_2000dps;
cparata	3:4274d9103f1d	352	break;
cparata	3:4274d9103f1d	353	default:
cparata	3:4274d9103f1d	354	*val = LSM6DSO_250dps;
cparata	3:4274d9103f1d	355	break;
cparata	3:4274d9103f1d	356	}
cparata	3:4274d9103f1d	357
cparata	3:4274d9103f1d	358	return ret;
cparata	0:6d69e896ce38	359	}
cparata	0:6d69e896ce38	360
cparata	0:6d69e896ce38	361	/**
cparata	0:6d69e896ce38	362	* @brief Gyroscope UI data rate selection.[set]
cparata	0:6d69e896ce38	363	*
cparata	0:6d69e896ce38	364	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	365	* @param val change the values of odr_g in reg CTRL2_G
cparata	0:6d69e896ce38	366	*
cparata	0:6d69e896ce38	367	*/
cparata	0:6d69e896ce38	368	int32_t lsm6dso_gy_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_g_t val)
cparata	0:6d69e896ce38	369	{
cparata	3:4274d9103f1d	370	lsm6dso_ctrl2_g_t reg;
cparata	3:4274d9103f1d	371	int32_t ret;
cparata	3:4274d9103f1d	372
cparata	3:4274d9103f1d	373	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	374	if (ret == 0) {
cparata	3:4274d9103f1d	375	reg.odr_g = (uint8_t) val;
cparata	3:4274d9103f1d	376	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	377	}
cparata	3:4274d9103f1d	378
cparata	3:4274d9103f1d	379	return ret;
cparata	0:6d69e896ce38	380	}
cparata	0:6d69e896ce38	381
cparata	0:6d69e896ce38	382	/**
cparata	0:6d69e896ce38	383	* @brief Gyroscope UI data rate selection.[get]
cparata	0:6d69e896ce38	384	*
cparata	0:6d69e896ce38	385	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	386	* @param val Get the values of odr_g in reg CTRL2_G
cparata	0:6d69e896ce38	387	*
cparata	0:6d69e896ce38	388	*/
cparata	0:6d69e896ce38	389	int32_t lsm6dso_gy_data_rate_get(lsm6dso_ctx_t ctx, lsm6dso_odr_g_t val)
cparata	0:6d69e896ce38	390	{
cparata	3:4274d9103f1d	391	lsm6dso_ctrl2_g_t reg;
cparata	3:4274d9103f1d	392	int32_t ret;
cparata	3:4274d9103f1d	393
cparata	3:4274d9103f1d	394	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	395	switch (reg.odr_g) {
cparata	3:4274d9103f1d	396	case LSM6DSO_GY_ODR_OFF:
cparata	3:4274d9103f1d	397	*val = LSM6DSO_GY_ODR_OFF;
cparata	3:4274d9103f1d	398	break;
cparata	3:4274d9103f1d	399	case LSM6DSO_GY_ODR_12Hz5:
cparata	3:4274d9103f1d	400	*val = LSM6DSO_GY_ODR_12Hz5;
cparata	3:4274d9103f1d	401	break;
cparata	3:4274d9103f1d	402	case LSM6DSO_GY_ODR_26Hz:
cparata	3:4274d9103f1d	403	*val = LSM6DSO_GY_ODR_26Hz;
cparata	3:4274d9103f1d	404	break;
cparata	3:4274d9103f1d	405	case LSM6DSO_GY_ODR_52Hz:
cparata	3:4274d9103f1d	406	*val = LSM6DSO_GY_ODR_52Hz;
cparata	3:4274d9103f1d	407	break;
cparata	3:4274d9103f1d	408	case LSM6DSO_GY_ODR_104Hz:
cparata	3:4274d9103f1d	409	*val = LSM6DSO_GY_ODR_104Hz;
cparata	3:4274d9103f1d	410	break;
cparata	3:4274d9103f1d	411	case LSM6DSO_GY_ODR_208Hz:
cparata	3:4274d9103f1d	412	*val = LSM6DSO_GY_ODR_208Hz;
cparata	3:4274d9103f1d	413	break;
cparata	3:4274d9103f1d	414	case LSM6DSO_GY_ODR_417Hz:
cparata	3:4274d9103f1d	415	*val = LSM6DSO_GY_ODR_417Hz;
cparata	3:4274d9103f1d	416	break;
cparata	3:4274d9103f1d	417	case LSM6DSO_GY_ODR_833Hz:
cparata	3:4274d9103f1d	418	*val = LSM6DSO_GY_ODR_833Hz;
cparata	3:4274d9103f1d	419	break;
cparata	3:4274d9103f1d	420	case LSM6DSO_GY_ODR_1667Hz:
cparata	3:4274d9103f1d	421	*val = LSM6DSO_GY_ODR_1667Hz;
cparata	3:4274d9103f1d	422	break;
cparata	3:4274d9103f1d	423	case LSM6DSO_GY_ODR_3333Hz:
cparata	3:4274d9103f1d	424	*val = LSM6DSO_GY_ODR_3333Hz;
cparata	3:4274d9103f1d	425	break;
cparata	3:4274d9103f1d	426	case LSM6DSO_GY_ODR_6667Hz:
cparata	3:4274d9103f1d	427	*val = LSM6DSO_GY_ODR_6667Hz;
cparata	3:4274d9103f1d	428	break;
cparata	3:4274d9103f1d	429	default:
cparata	3:4274d9103f1d	430	*val = LSM6DSO_GY_ODR_OFF;
cparata	3:4274d9103f1d	431	break;
cparata	3:4274d9103f1d	432	}
cparata	3:4274d9103f1d	433	return ret;
cparata	0:6d69e896ce38	434	}
cparata	0:6d69e896ce38	435
cparata	0:6d69e896ce38	436	/**
cparata	0:6d69e896ce38	437	* @brief Block data update.[set]
cparata	0:6d69e896ce38	438	*
cparata	0:6d69e896ce38	439	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	440	* @param val change the values of bdu in reg CTRL3_C
cparata	0:6d69e896ce38	441	*
cparata	0:6d69e896ce38	442	*/
cparata	0:6d69e896ce38	443	int32_t lsm6dso_block_data_update_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	444	{
cparata	3:4274d9103f1d	445	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	446	int32_t ret;
cparata	3:4274d9103f1d	447
cparata	3:4274d9103f1d	448	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	449	if (ret == 0) {
cparata	3:4274d9103f1d	450	reg.bdu = val;
cparata	3:4274d9103f1d	451	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	452	}
cparata	3:4274d9103f1d	453	return ret;
cparata	0:6d69e896ce38	454	}
cparata	0:6d69e896ce38	455
cparata	0:6d69e896ce38	456	/**
cparata	0:6d69e896ce38	457	* @brief Block data update.[get]
cparata	0:6d69e896ce38	458	*
cparata	0:6d69e896ce38	459	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	460	* @param val change the values of bdu in reg CTRL3_C
cparata	0:6d69e896ce38	461	*
cparata	0:6d69e896ce38	462	*/
cparata	0:6d69e896ce38	463	int32_t lsm6dso_block_data_update_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	464	{
cparata	3:4274d9103f1d	465	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	466	int32_t ret;
cparata	3:4274d9103f1d	467
cparata	3:4274d9103f1d	468	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	469	*val = reg.bdu;
cparata	3:4274d9103f1d	470
cparata	3:4274d9103f1d	471	return ret;
cparata	0:6d69e896ce38	472	}
cparata	0:6d69e896ce38	473
cparata	0:6d69e896ce38	474	/**
cparata	0:6d69e896ce38	475	* @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
cparata	0:6d69e896ce38	476	* Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
cparata	0:6d69e896ce38	477	*
cparata	0:6d69e896ce38	478	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	479	* @param val change the values of usr_off_w in reg CTRL6_C
cparata	0:6d69e896ce38	480	*
cparata	0:6d69e896ce38	481	*/
cparata	0:6d69e896ce38	482	int32_t lsm6dso_xl_offset_weight_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	483	lsm6dso_usr_off_w_t val)
cparata	0:6d69e896ce38	484	{
cparata	3:4274d9103f1d	485	lsm6dso_ctrl6_c_t reg;
cparata	3:4274d9103f1d	486	int32_t ret;
cparata	3:4274d9103f1d	487
cparata	3:4274d9103f1d	488	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	489	if (ret == 0) {
cparata	3:4274d9103f1d	490	reg.usr_off_w = (uint8_t)val;
cparata	3:4274d9103f1d	491	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	492	}
cparata	3:4274d9103f1d	493	return ret;
cparata	0:6d69e896ce38	494	}
cparata	0:6d69e896ce38	495
cparata	0:6d69e896ce38	496	/**
cparata	0:6d69e896ce38	497	* @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
cparata	0:6d69e896ce38	498	* Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
cparata	0:6d69e896ce38	499	*
cparata	0:6d69e896ce38	500	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	501	* @param val Get the values of usr_off_w in reg CTRL6_C
cparata	0:6d69e896ce38	502	*
cparata	0:6d69e896ce38	503	*/
cparata	0:6d69e896ce38	504	int32_t lsm6dso_xl_offset_weight_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	505	lsm6dso_usr_off_w_t *val)
cparata	0:6d69e896ce38	506	{
cparata	3:4274d9103f1d	507	lsm6dso_ctrl6_c_t reg;
cparata	3:4274d9103f1d	508	int32_t ret;
cparata	3:4274d9103f1d	509
cparata	3:4274d9103f1d	510	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	511
cparata	3:4274d9103f1d	512	switch (reg.usr_off_w) {
cparata	3:4274d9103f1d	513	case LSM6DSO_LSb_1mg:
cparata	3:4274d9103f1d	514	*val = LSM6DSO_LSb_1mg;
cparata	3:4274d9103f1d	515	break;
cparata	3:4274d9103f1d	516	case LSM6DSO_LSb_16mg:
cparata	3:4274d9103f1d	517	*val = LSM6DSO_LSb_16mg;
cparata	3:4274d9103f1d	518	break;
cparata	3:4274d9103f1d	519	default:
cparata	3:4274d9103f1d	520	*val = LSM6DSO_LSb_1mg;
cparata	3:4274d9103f1d	521	break;
cparata	3:4274d9103f1d	522	}
cparata	3:4274d9103f1d	523	return ret;
cparata	0:6d69e896ce38	524	}
cparata	0:6d69e896ce38	525
cparata	0:6d69e896ce38	526	/**
cparata	0:6d69e896ce38	527	* @brief Accelerometer power mode.[set]
cparata	0:6d69e896ce38	528	*
cparata	0:6d69e896ce38	529	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	530	* @param val change the values of xl_hm_mode in
cparata	0:6d69e896ce38	531	* reg CTRL6_C
cparata	0:6d69e896ce38	532	*
cparata	0:6d69e896ce38	533	*/
cparata	0:6d69e896ce38	534	int32_t lsm6dso_xl_power_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	535	lsm6dso_xl_hm_mode_t val)
cparata	0:6d69e896ce38	536	{
cparata	3:4274d9103f1d	537	lsm6dso_ctrl5_c_t ctrl5_c;
cparata	3:4274d9103f1d	538	lsm6dso_ctrl6_c_t ctrl6_c;
cparata	3:4274d9103f1d	539	int32_t ret;
cparata	3:4274d9103f1d	540
cparata	3:4274d9103f1d	541	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
cparata	3:4274d9103f1d	542	if (ret == 0) {
cparata	3:4274d9103f1d	543	ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
cparata	3:4274d9103f1d	544	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
cparata	3:4274d9103f1d	545	}
cparata	3:4274d9103f1d	546	if (ret == 0) {
cparata	3:4274d9103f1d	547	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
cparata	3:4274d9103f1d	548	}
cparata	3:4274d9103f1d	549	if (ret == 0) {
cparata	3:4274d9103f1d	550	ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
cparata	3:4274d9103f1d	551	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
cparata	3:4274d9103f1d	552	}
cparata	3:4274d9103f1d	553	return ret;
cparata	0:6d69e896ce38	554	}
cparata	0:6d69e896ce38	555
cparata	0:6d69e896ce38	556	/**
cparata	0:6d69e896ce38	557	* @brief Accelerometer power mode.[get]
cparata	0:6d69e896ce38	558	*
cparata	0:6d69e896ce38	559	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	560	* @param val Get the values of xl_hm_mode in reg CTRL6_C
cparata	0:6d69e896ce38	561	*
cparata	0:6d69e896ce38	562	*/
cparata	0:6d69e896ce38	563	int32_t lsm6dso_xl_power_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	564	lsm6dso_xl_hm_mode_t *val)
cparata	0:6d69e896ce38	565	{
cparata	3:4274d9103f1d	566	lsm6dso_ctrl5_c_t ctrl5_c;
cparata	3:4274d9103f1d	567	lsm6dso_ctrl6_c_t ctrl6_c;
cparata	3:4274d9103f1d	568	int32_t ret;
cparata	3:4274d9103f1d	569
cparata	3:4274d9103f1d	570	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
cparata	3:4274d9103f1d	571	if (ret == 0) {
cparata	3:4274d9103f1d	572	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
cparata	3:4274d9103f1d	573	switch ((ctrl5_c.xl_ulp_en << 1) \| ctrl6_c.xl_hm_mode) {
cparata	3:4274d9103f1d	574	case LSM6DSO_HIGH_PERFORMANCE_MD:
cparata	3:4274d9103f1d	575	*val = LSM6DSO_HIGH_PERFORMANCE_MD;
cparata	3:4274d9103f1d	576	break;
cparata	3:4274d9103f1d	577	case LSM6DSO_LOW_NORMAL_POWER_MD:
cparata	3:4274d9103f1d	578	*val = LSM6DSO_LOW_NORMAL_POWER_MD;
cparata	3:4274d9103f1d	579	break;
cparata	3:4274d9103f1d	580	case LSM6DSO_ULTRA_LOW_POWER_MD:
cparata	3:4274d9103f1d	581	*val = LSM6DSO_ULTRA_LOW_POWER_MD;
cparata	3:4274d9103f1d	582	break;
cparata	3:4274d9103f1d	583	default:
cparata	3:4274d9103f1d	584	*val = LSM6DSO_HIGH_PERFORMANCE_MD;
cparata	3:4274d9103f1d	585	break;
cparata	3:4274d9103f1d	586	}
cparata	3:4274d9103f1d	587	}
cparata	3:4274d9103f1d	588	return ret;
cparata	0:6d69e896ce38	589	}
cparata	0:6d69e896ce38	590
cparata	0:6d69e896ce38	591	/**
cparata	0:6d69e896ce38	592	* @brief Operating mode for gyroscope.[set]
cparata	0:6d69e896ce38	593	*
cparata	0:6d69e896ce38	594	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	595	* @param val change the values of g_hm_mode in reg CTRL7_G
cparata	0:6d69e896ce38	596	*
cparata	0:6d69e896ce38	597	*/
cparata	0:6d69e896ce38	598	int32_t lsm6dso_gy_power_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	599	lsm6dso_g_hm_mode_t val)
cparata	0:6d69e896ce38	600	{
cparata	3:4274d9103f1d	601	lsm6dso_ctrl7_g_t reg;
cparata	3:4274d9103f1d	602	int32_t ret;
cparata	3:4274d9103f1d	603
cparata	3:4274d9103f1d	604	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	605	if (ret == 0) {
cparata	3:4274d9103f1d	606	reg.g_hm_mode = (uint8_t)val;
cparata	3:4274d9103f1d	607	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	608	}
cparata	3:4274d9103f1d	609	return ret;
cparata	0:6d69e896ce38	610	}
cparata	0:6d69e896ce38	611
cparata	0:6d69e896ce38	612	/**
cparata	0:6d69e896ce38	613	* @brief Operating mode for gyroscope.[get]
cparata	0:6d69e896ce38	614	*
cparata	0:6d69e896ce38	615	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	616	* @param val Get the values of g_hm_mode in reg CTRL7_G
cparata	0:6d69e896ce38	617	*
cparata	0:6d69e896ce38	618	*/
cparata	0:6d69e896ce38	619	int32_t lsm6dso_gy_power_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	620	lsm6dso_g_hm_mode_t *val)
cparata	0:6d69e896ce38	621	{
cparata	3:4274d9103f1d	622	lsm6dso_ctrl7_g_t reg;
cparata	3:4274d9103f1d	623	int32_t ret;
cparata	3:4274d9103f1d	624
cparata	3:4274d9103f1d	625	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	626	switch (reg.g_hm_mode) {
cparata	3:4274d9103f1d	627	case LSM6DSO_GY_HIGH_PERFORMANCE:
cparata	3:4274d9103f1d	628	*val = LSM6DSO_GY_HIGH_PERFORMANCE;
cparata	3:4274d9103f1d	629	break;
cparata	3:4274d9103f1d	630	case LSM6DSO_GY_NORMAL:
cparata	3:4274d9103f1d	631	*val = LSM6DSO_GY_NORMAL;
cparata	3:4274d9103f1d	632	break;
cparata	3:4274d9103f1d	633	default:
cparata	3:4274d9103f1d	634	*val = LSM6DSO_GY_HIGH_PERFORMANCE;
cparata	3:4274d9103f1d	635	break;
cparata	3:4274d9103f1d	636	}
cparata	3:4274d9103f1d	637	return ret;
cparata	0:6d69e896ce38	638	}
cparata	0:6d69e896ce38	639
cparata	0:6d69e896ce38	640	/**
cparata	0:6d69e896ce38	641	* @brief Read all the interrupt flag of the device.[get]
cparata	0:6d69e896ce38	642	*
cparata	0:6d69e896ce38	643	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	644	* @param val registers ALL_INT_SRC; WAKE_UP_SRC;
cparata	0:6d69e896ce38	645	* TAP_SRC; D6D_SRC; STATUS_REG;
cparata	0:6d69e896ce38	646	* EMB_FUNC_STATUS; FSM_STATUS_A/B
cparata	0:6d69e896ce38	647	*
cparata	0:6d69e896ce38	648	*/
cparata	0:6d69e896ce38	649	int32_t lsm6dso_all_sources_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	650	lsm6dso_all_sources_t *val)
cparata	0:6d69e896ce38	651	{
cparata	3:4274d9103f1d	652	int32_t ret;
cparata	3:4274d9103f1d	653
cparata	3:4274d9103f1d	654	ret = lsm6dso_read_reg(ctx, LSM6DSO_ALL_INT_SRC,
cparata	3:4274d9103f1d	655	(uint8_t *)&val->all_int_src, 1);
cparata	3:4274d9103f1d	656	if (ret == 0) {
cparata	3:4274d9103f1d	657	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_SRC,
cparata	3:4274d9103f1d	658	(uint8_t *)&val->wake_up_src, 1);
cparata	3:4274d9103f1d	659	}
cparata	3:4274d9103f1d	660	if (ret == 0) {
cparata	3:4274d9103f1d	661	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_SRC,
cparata	3:4274d9103f1d	662	(uint8_t *)&val->tap_src, 1);
cparata	3:4274d9103f1d	663	}
cparata	3:4274d9103f1d	664	if (ret == 0) {
cparata	3:4274d9103f1d	665	ret = lsm6dso_read_reg(ctx, LSM6DSO_D6D_SRC,
cparata	3:4274d9103f1d	666	(uint8_t *)&val->d6d_src, 1);
cparata	3:4274d9103f1d	667	}
cparata	3:4274d9103f1d	668	if (ret == 0) {
cparata	3:4274d9103f1d	669	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG,
cparata	3:4274d9103f1d	670	(uint8_t *)&val->status_reg, 1);
cparata	3:4274d9103f1d	671	}
cparata	3:4274d9103f1d	672	if (ret == 0) {
cparata	3:4274d9103f1d	673
cparata	3:4274d9103f1d	674	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	675	}
cparata	3:4274d9103f1d	676	if (ret == 0) {
cparata	3:4274d9103f1d	677	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS,
cparata	3:4274d9103f1d	678	(uint8_t *)&val->emb_func_status, 1);
cparata	3:4274d9103f1d	679	}
cparata	3:4274d9103f1d	680	if (ret == 0) {
cparata	3:4274d9103f1d	681	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_STATUS_A,
cparata	3:4274d9103f1d	682	(uint8_t *)&val->fsm_status_a, 1);
cparata	3:4274d9103f1d	683	}
cparata	3:4274d9103f1d	684	if (ret == 0) {
cparata	3:4274d9103f1d	685	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_STATUS_B,
cparata	3:4274d9103f1d	686	(uint8_t *)&val->fsm_status_b, 1);
cparata	3:4274d9103f1d	687	}
cparata	3:4274d9103f1d	688	if (ret == 0) {
cparata	3:4274d9103f1d	689	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	690	}
cparata	3:4274d9103f1d	691	return ret;
cparata	0:6d69e896ce38	692	}
cparata	0:6d69e896ce38	693
cparata	0:6d69e896ce38	694	/**
cparata	0:6d69e896ce38	695	* @brief The STATUS_REG register is read by the primary interface.[get]
cparata	0:6d69e896ce38	696	*
cparata	0:6d69e896ce38	697	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	698	* @param val register STATUS_REG
cparata	0:6d69e896ce38	699	*
cparata	0:6d69e896ce38	700	*/
cparata	0:6d69e896ce38	701	int32_t lsm6dso_status_reg_get(lsm6dso_ctx_t ctx, lsm6dso_status_reg_t val)
cparata	0:6d69e896ce38	702	{
cparata	3:4274d9103f1d	703	int32_t ret;
cparata	3:4274d9103f1d	704	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *) val, 1);
cparata	3:4274d9103f1d	705	return ret;
cparata	0:6d69e896ce38	706	}
cparata	0:6d69e896ce38	707
cparata	0:6d69e896ce38	708	/**
cparata	0:6d69e896ce38	709	* @brief Accelerometer new data available.[get]
cparata	0:6d69e896ce38	710	*
cparata	0:6d69e896ce38	711	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	712	* @param val change the values of xlda in reg STATUS_REG
cparata	0:6d69e896ce38	713	*
cparata	0:6d69e896ce38	714	*/
cparata	0:6d69e896ce38	715	int32_t lsm6dso_xl_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	716	{
cparata	3:4274d9103f1d	717	lsm6dso_status_reg_t reg;
cparata	3:4274d9103f1d	718	int32_t ret;
cparata	3:4274d9103f1d	719
cparata	3:4274d9103f1d	720	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	721	*val = reg.xlda;
cparata	3:4274d9103f1d	722
cparata	3:4274d9103f1d	723	return ret;
cparata	0:6d69e896ce38	724	}
cparata	0:6d69e896ce38	725
cparata	0:6d69e896ce38	726	/**
cparata	0:6d69e896ce38	727	* @brief Gyroscope new data available.[get]
cparata	0:6d69e896ce38	728	*
cparata	0:6d69e896ce38	729	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	730	* @param val change the values of gda in reg STATUS_REG
cparata	0:6d69e896ce38	731	*
cparata	0:6d69e896ce38	732	*/
cparata	0:6d69e896ce38	733	int32_t lsm6dso_gy_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	734	{
cparata	3:4274d9103f1d	735	lsm6dso_status_reg_t reg;
cparata	3:4274d9103f1d	736	int32_t ret;
cparata	3:4274d9103f1d	737
cparata	3:4274d9103f1d	738	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	739	*val = reg.gda;
cparata	3:4274d9103f1d	740
cparata	3:4274d9103f1d	741	return ret;
cparata	0:6d69e896ce38	742	}
cparata	0:6d69e896ce38	743
cparata	0:6d69e896ce38	744	/**
cparata	0:6d69e896ce38	745	* @brief Temperature new data available.[get]
cparata	0:6d69e896ce38	746	*
cparata	0:6d69e896ce38	747	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	748	* @param val change the values of tda in reg STATUS_REG
cparata	0:6d69e896ce38	749	*
cparata	0:6d69e896ce38	750	*/
cparata	0:6d69e896ce38	751	int32_t lsm6dso_temp_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	752	{
cparata	3:4274d9103f1d	753	lsm6dso_status_reg_t reg;
cparata	3:4274d9103f1d	754	int32_t ret;
cparata	3:4274d9103f1d	755
cparata	3:4274d9103f1d	756	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	757	*val = reg.tda;
cparata	3:4274d9103f1d	758
cparata	3:4274d9103f1d	759	return ret;
cparata	0:6d69e896ce38	760	}
cparata	0:6d69e896ce38	761
cparata	0:6d69e896ce38	762	/**
cparata	0:6d69e896ce38	763	* @brief Accelerometer X-axis user offset correction expressed in
cparata	0:6d69e896ce38	764	* two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	765	* The value must be in the range [-127 127].[set]
cparata	0:6d69e896ce38	766	*
cparata	0:6d69e896ce38	767	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	768	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	769	*
cparata	0:6d69e896ce38	770	*/
cparata	0:6d69e896ce38	771	int32_t lsm6dso_xl_usr_offset_x_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	772	{
cparata	3:4274d9103f1d	773	int32_t ret;
cparata	3:4274d9103f1d	774	ret = lsm6dso_write_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
cparata	3:4274d9103f1d	775	return ret;
cparata	0:6d69e896ce38	776	}
cparata	0:6d69e896ce38	777
cparata	0:6d69e896ce38	778	/**
cparata	0:6d69e896ce38	779	* @brief Accelerometer X-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	780	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	781	* The value must be in the range [-127 127].[get]
cparata	0:6d69e896ce38	782	*
cparata	0:6d69e896ce38	783	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	784	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	785	*
cparata	0:6d69e896ce38	786	*/
cparata	0:6d69e896ce38	787	int32_t lsm6dso_xl_usr_offset_x_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	788	{
cparata	3:4274d9103f1d	789	int32_t ret;
cparata	3:4274d9103f1d	790	ret = lsm6dso_read_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
cparata	3:4274d9103f1d	791	return ret;
cparata	0:6d69e896ce38	792	}
cparata	0:6d69e896ce38	793
cparata	0:6d69e896ce38	794	/**
cparata	0:6d69e896ce38	795	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	796	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	797	* The value must be in the range [-127 127].[set]
cparata	0:6d69e896ce38	798	*
cparata	0:6d69e896ce38	799	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	800	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	801	*
cparata	0:6d69e896ce38	802	*/
cparata	0:6d69e896ce38	803	int32_t lsm6dso_xl_usr_offset_y_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	804	{
cparata	3:4274d9103f1d	805	int32_t ret;
cparata	3:4274d9103f1d	806	ret = lsm6dso_write_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
cparata	3:4274d9103f1d	807	return ret;
cparata	0:6d69e896ce38	808	}
cparata	0:6d69e896ce38	809
cparata	0:6d69e896ce38	810	/**
cparata	0:6d69e896ce38	811	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	812	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	813	* The value must be in the range [-127 127].[get]
cparata	0:6d69e896ce38	814	*
cparata	0:6d69e896ce38	815	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	816	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	817	*
cparata	0:6d69e896ce38	818	*/
cparata	0:6d69e896ce38	819	int32_t lsm6dso_xl_usr_offset_y_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	820	{
cparata	3:4274d9103f1d	821	int32_t ret;
cparata	3:4274d9103f1d	822	ret = lsm6dso_read_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
cparata	3:4274d9103f1d	823	return ret;
cparata	0:6d69e896ce38	824	}
cparata	0:6d69e896ce38	825
cparata	0:6d69e896ce38	826	/**
cparata	0:6d69e896ce38	827	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	828	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	829	* The value must be in the range [-127 127].[set]
cparata	0:6d69e896ce38	830	*
cparata	0:6d69e896ce38	831	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	832	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	833	*
cparata	0:6d69e896ce38	834	*/
cparata	0:6d69e896ce38	835	int32_t lsm6dso_xl_usr_offset_z_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	836	{
cparata	3:4274d9103f1d	837	int32_t ret;
cparata	3:4274d9103f1d	838	ret = lsm6dso_write_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
cparata	3:4274d9103f1d	839	return ret;
cparata	0:6d69e896ce38	840	}
cparata	0:6d69e896ce38	841
cparata	0:6d69e896ce38	842	/**
cparata	0:6d69e896ce38	843	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	844	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	845	* The value must be in the range [-127 127].[get]
cparata	0:6d69e896ce38	846	*
cparata	0:6d69e896ce38	847	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	848	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	849	*
cparata	0:6d69e896ce38	850	*/
cparata	0:6d69e896ce38	851	int32_t lsm6dso_xl_usr_offset_z_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	852	{
cparata	3:4274d9103f1d	853	int32_t ret;
cparata	3:4274d9103f1d	854	ret = lsm6dso_read_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
cparata	3:4274d9103f1d	855	return ret;
cparata	0:6d69e896ce38	856	}
cparata	0:6d69e896ce38	857
cparata	0:6d69e896ce38	858	/**
cparata	0:6d69e896ce38	859	* @brief Enables user offset on out.[set]
cparata	0:6d69e896ce38	860	*
cparata	0:6d69e896ce38	861	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	862	* @param val change the values of usr_off_on_out in reg CTRL7_G
cparata	0:6d69e896ce38	863	*
cparata	0:6d69e896ce38	864	*/
cparata	0:6d69e896ce38	865	int32_t lsm6dso_xl_usr_offset_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	866	{
cparata	3:4274d9103f1d	867	lsm6dso_ctrl7_g_t reg;
cparata	3:4274d9103f1d	868	int32_t ret;
cparata	3:4274d9103f1d	869
cparata	3:4274d9103f1d	870	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	871	if (ret == 0) {
cparata	3:4274d9103f1d	872	reg.usr_off_on_out = val;
cparata	3:4274d9103f1d	873	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	874	}
cparata	3:4274d9103f1d	875	return ret;
cparata	0:6d69e896ce38	876	}
cparata	0:6d69e896ce38	877
cparata	0:6d69e896ce38	878	/**
cparata	0:6d69e896ce38	879	* @brief User offset on out flag.[get]
cparata	0:6d69e896ce38	880	*
cparata	0:6d69e896ce38	881	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	882	* @param val values of usr_off_on_out in reg CTRL7_G
cparata	0:6d69e896ce38	883	*
cparata	0:6d69e896ce38	884	*/
cparata	0:6d69e896ce38	885	int32_t lsm6dso_xl_usr_offset_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	886	{
cparata	3:4274d9103f1d	887	lsm6dso_ctrl7_g_t reg;
cparata	3:4274d9103f1d	888	int32_t ret;
cparata	3:4274d9103f1d	889
cparata	3:4274d9103f1d	890	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	891	*val = reg.usr_off_on_out;
cparata	3:4274d9103f1d	892
cparata	3:4274d9103f1d	893	return ret;
cparata	0:6d69e896ce38	894	}
cparata	0:6d69e896ce38	895
cparata	0:6d69e896ce38	896	/**
cparata	0:6d69e896ce38	897	* @}
cparata	0:6d69e896ce38	898	*
cparata	0:6d69e896ce38	899	*/
cparata	0:6d69e896ce38	900
cparata	0:6d69e896ce38	901	/**
cparata	0:6d69e896ce38	902	* @defgroup LSM6DSO_Timestamp
cparata	0:6d69e896ce38	903	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	904	* timestamp generation.
cparata	0:6d69e896ce38	905	* @{
cparata	0:6d69e896ce38	906	*
cparata	0:6d69e896ce38	907	*/
cparata	0:6d69e896ce38	908
cparata	0:6d69e896ce38	909	/**
cparata	0:6d69e896ce38	910	* @brief Enables timestamp counter.[set]
cparata	0:6d69e896ce38	911	*
cparata	0:6d69e896ce38	912	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	913	* @param val change the values of timestamp_en in reg CTRL10_C
cparata	0:6d69e896ce38	914	*
cparata	0:6d69e896ce38	915	*/
cparata	0:6d69e896ce38	916	int32_t lsm6dso_timestamp_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	917	{
cparata	3:4274d9103f1d	918	lsm6dso_ctrl10_c_t reg;
cparata	3:4274d9103f1d	919	int32_t ret;
cparata	3:4274d9103f1d	920
cparata	3:4274d9103f1d	921	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	922	if (ret == 0) {
cparata	3:4274d9103f1d	923	reg.timestamp_en = val;
cparata	3:4274d9103f1d	924	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	925	}
cparata	3:4274d9103f1d	926	return ret;
cparata	0:6d69e896ce38	927	}
cparata	0:6d69e896ce38	928
cparata	0:6d69e896ce38	929	/**
cparata	0:6d69e896ce38	930	* @brief Enables timestamp counter.[get]
cparata	0:6d69e896ce38	931	*
cparata	0:6d69e896ce38	932	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	933	* @param val change the values of timestamp_en in reg CTRL10_C
cparata	0:6d69e896ce38	934	*
cparata	0:6d69e896ce38	935	*/
cparata	0:6d69e896ce38	936	int32_t lsm6dso_timestamp_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	937	{
cparata	3:4274d9103f1d	938	lsm6dso_ctrl10_c_t reg;
cparata	3:4274d9103f1d	939	int32_t ret;
cparata	3:4274d9103f1d	940
cparata	3:4274d9103f1d	941	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	942	*val = reg.timestamp_en;
cparata	3:4274d9103f1d	943
cparata	3:4274d9103f1d	944	return ret;
cparata	0:6d69e896ce38	945	}
cparata	0:6d69e896ce38	946
cparata	0:6d69e896ce38	947	/**
cparata	0:6d69e896ce38	948	* @brief Timestamp first data output register (r).
cparata	0:6d69e896ce38	949	* The value is expressed as a 32-bit word and the bit
cparata	0:6d69e896ce38	950	* resolution is 25 μs.[get]
cparata	0:6d69e896ce38	951	*
cparata	0:6d69e896ce38	952	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	953	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	954	*
cparata	0:6d69e896ce38	955	*/
cparata	0:6d69e896ce38	956	int32_t lsm6dso_timestamp_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	957	{
cparata	3:4274d9103f1d	958	int32_t ret;
cparata	3:4274d9103f1d	959	ret = lsm6dso_read_reg(ctx, LSM6DSO_TIMESTAMP0, buff, 4);
cparata	3:4274d9103f1d	960	return ret;
cparata	0:6d69e896ce38	961	}
cparata	0:6d69e896ce38	962
cparata	0:6d69e896ce38	963	/**
cparata	0:6d69e896ce38	964	* @}
cparata	0:6d69e896ce38	965	*
cparata	0:6d69e896ce38	966	*/
cparata	0:6d69e896ce38	967
cparata	0:6d69e896ce38	968	/**
cparata	0:6d69e896ce38	969	* @defgroup LSM6DSO_Data output
cparata	0:6d69e896ce38	970	* @brief This section groups all the data output functions.
cparata	0:6d69e896ce38	971	* @{
cparata	0:6d69e896ce38	972	*
cparata	0:6d69e896ce38	973	*/
cparata	0:6d69e896ce38	974
cparata	0:6d69e896ce38	975	/**
cparata	0:6d69e896ce38	976	* @brief Circular burst-mode (rounding) read of the output
cparata	0:6d69e896ce38	977	* registers.[set]
cparata	0:6d69e896ce38	978	*
cparata	0:6d69e896ce38	979	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	980	* @param val change the values of rounding in reg CTRL5_C
cparata	0:6d69e896ce38	981	*
cparata	0:6d69e896ce38	982	*/
cparata	0:6d69e896ce38	983	int32_t lsm6dso_rounding_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	984	lsm6dso_rounding_t val)
cparata	0:6d69e896ce38	985	{
cparata	3:4274d9103f1d	986	lsm6dso_ctrl5_c_t reg;
cparata	3:4274d9103f1d	987	int32_t ret;
cparata	3:4274d9103f1d	988
cparata	3:4274d9103f1d	989	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	990	if (ret == 0) {
cparata	3:4274d9103f1d	991	reg.rounding = (uint8_t)val;
cparata	3:4274d9103f1d	992	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	993	}
cparata	3:4274d9103f1d	994	return ret;
cparata	0:6d69e896ce38	995	}
cparata	0:6d69e896ce38	996
cparata	0:6d69e896ce38	997	/**
cparata	0:6d69e896ce38	998	* @brief Gyroscope UI chain full-scale selection.[get]
cparata	0:6d69e896ce38	999	*
cparata	0:6d69e896ce38	1000	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1001	* @param val Get the values of rounding in reg CTRL5_C
cparata	0:6d69e896ce38	1002	*
cparata	0:6d69e896ce38	1003	*/
cparata	0:6d69e896ce38	1004	int32_t lsm6dso_rounding_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1005	lsm6dso_rounding_t *val)
cparata	0:6d69e896ce38	1006	{
cparata	3:4274d9103f1d	1007	lsm6dso_ctrl5_c_t reg;
cparata	3:4274d9103f1d	1008	int32_t ret;
cparata	3:4274d9103f1d	1009
cparata	3:4274d9103f1d	1010	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1011	switch (reg.rounding) {
cparata	3:4274d9103f1d	1012	case LSM6DSO_NO_ROUND:
cparata	3:4274d9103f1d	1013	*val = LSM6DSO_NO_ROUND;
cparata	3:4274d9103f1d	1014	break;
cparata	3:4274d9103f1d	1015	case LSM6DSO_ROUND_XL:
cparata	3:4274d9103f1d	1016	*val = LSM6DSO_ROUND_XL;
cparata	3:4274d9103f1d	1017	break;
cparata	3:4274d9103f1d	1018	case LSM6DSO_ROUND_GY:
cparata	3:4274d9103f1d	1019	*val = LSM6DSO_ROUND_GY;
cparata	3:4274d9103f1d	1020	break;
cparata	3:4274d9103f1d	1021	case LSM6DSO_ROUND_GY_XL:
cparata	3:4274d9103f1d	1022	*val = LSM6DSO_ROUND_GY_XL;
cparata	3:4274d9103f1d	1023	break;
cparata	3:4274d9103f1d	1024	default:
cparata	3:4274d9103f1d	1025	*val = LSM6DSO_NO_ROUND;
cparata	3:4274d9103f1d	1026	break;
cparata	3:4274d9103f1d	1027	}
cparata	3:4274d9103f1d	1028	return ret;
cparata	0:6d69e896ce38	1029	}
cparata	0:6d69e896ce38	1030
cparata	0:6d69e896ce38	1031	/**
cparata	0:6d69e896ce38	1032	* @brief Temperature data output register (r).
cparata	0:6d69e896ce38	1033	* L and H registers together express a 16-bit word in two’s
cparata	0:6d69e896ce38	1034	* complement.[get]
cparata	0:6d69e896ce38	1035	*
cparata	0:6d69e896ce38	1036	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1037	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1038	*
cparata	0:6d69e896ce38	1039	*/
cparata	0:6d69e896ce38	1040	int32_t lsm6dso_temperature_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1041	{
cparata	3:4274d9103f1d	1042	int32_t ret;
cparata	3:4274d9103f1d	1043	ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 2);
cparata	3:4274d9103f1d	1044	return ret;
cparata	0:6d69e896ce38	1045	}
cparata	0:6d69e896ce38	1046
cparata	0:6d69e896ce38	1047	/**
cparata	0:6d69e896ce38	1048	* @brief Angular rate sensor. The value is expressed as a 16-bit
cparata	0:6d69e896ce38	1049	* word in two’s complement.[get]
cparata	0:6d69e896ce38	1050	*
cparata	0:6d69e896ce38	1051	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1052	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1053	*
cparata	0:6d69e896ce38	1054	*/
cparata	0:6d69e896ce38	1055	int32_t lsm6dso_angular_rate_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1056	{
cparata	3:4274d9103f1d	1057	int32_t ret;
cparata	3:4274d9103f1d	1058	ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_G, buff, 6);
cparata	3:4274d9103f1d	1059	return ret;
cparata	0:6d69e896ce38	1060	}
cparata	0:6d69e896ce38	1061
cparata	0:6d69e896ce38	1062	/**
cparata	0:6d69e896ce38	1063	* @brief Linear acceleration output register.
cparata	0:6d69e896ce38	1064	* The value is expressed as a 16-bit word in two’s complement.[get]
cparata	0:6d69e896ce38	1065	*
cparata	0:6d69e896ce38	1066	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1067	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1068	*
cparata	0:6d69e896ce38	1069	*/
cparata	0:6d69e896ce38	1070	int32_t lsm6dso_acceleration_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1071	{
cparata	3:4274d9103f1d	1072	int32_t ret;
cparata	3:4274d9103f1d	1073	ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_A, buff, 6);
cparata	3:4274d9103f1d	1074	return ret;
cparata	0:6d69e896ce38	1075	}
cparata	0:6d69e896ce38	1076
cparata	0:6d69e896ce38	1077	/**
cparata	0:6d69e896ce38	1078	* @brief FIFO data output [get]
cparata	0:6d69e896ce38	1079	*
cparata	0:6d69e896ce38	1080	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1081	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1082	*
cparata	0:6d69e896ce38	1083	*/
cparata	0:6d69e896ce38	1084	int32_t lsm6dso_fifo_out_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1085	{
cparata	3:4274d9103f1d	1086	int32_t ret;
cparata	3:4274d9103f1d	1087	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_X_L, buff, 6);
cparata	3:4274d9103f1d	1088	return ret;
cparata	0:6d69e896ce38	1089	}
cparata	0:6d69e896ce38	1090
cparata	0:6d69e896ce38	1091	/**
cparata	0:6d69e896ce38	1092	* @brief Step counter output register.[get]
cparata	0:6d69e896ce38	1093	*
cparata	0:6d69e896ce38	1094	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1095	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1096	*
cparata	0:6d69e896ce38	1097	*/
cparata	0:6d69e896ce38	1098	int32_t lsm6dso_number_of_steps_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1099	{
cparata	3:4274d9103f1d	1100	int32_t ret;
cparata	3:4274d9103f1d	1101
cparata	3:4274d9103f1d	1102	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	1103	if (ret == 0) {
cparata	3:4274d9103f1d	1104	ret = lsm6dso_read_reg(ctx, LSM6DSO_STEP_COUNTER_L, buff, 2);
cparata	3:4274d9103f1d	1105	}
cparata	3:4274d9103f1d	1106	if (ret == 0) {
cparata	3:4274d9103f1d	1107	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	1108	}
cparata	3:4274d9103f1d	1109	return ret;
cparata	0:6d69e896ce38	1110	}
cparata	0:6d69e896ce38	1111
cparata	0:6d69e896ce38	1112	/**
cparata	0:6d69e896ce38	1113	* @brief Reset step counter register.[get]
cparata	0:6d69e896ce38	1114	*
cparata	0:6d69e896ce38	1115	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1116	*
cparata	0:6d69e896ce38	1117	*/
cparata	0:6d69e896ce38	1118	int32_t lsm6dso_steps_reset(lsm6dso_ctx_t *ctx)
cparata	0:6d69e896ce38	1119	{
cparata	3:4274d9103f1d	1120	lsm6dso_emb_func_src_t reg;
cparata	3:4274d9103f1d	1121	int32_t ret;
cparata	3:4274d9103f1d	1122
cparata	3:4274d9103f1d	1123	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	1124	if (ret == 0) {
cparata	3:4274d9103f1d	1125	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1126	}
cparata	3:4274d9103f1d	1127	if (ret == 0) {
cparata	3:4274d9103f1d	1128	reg.pedo_rst_step = PROPERTY_ENABLE;
cparata	3:4274d9103f1d	1129	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1130	}
cparata	3:4274d9103f1d	1131	if (ret == 0) {
cparata	3:4274d9103f1d	1132	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	1133	}
cparata	3:4274d9103f1d	1134	return ret;
cparata	0:6d69e896ce38	1135	}
cparata	0:6d69e896ce38	1136
cparata	0:6d69e896ce38	1137	/**
cparata	0:6d69e896ce38	1138	* @}
cparata	0:6d69e896ce38	1139	*
cparata	0:6d69e896ce38	1140	*/
cparata	0:6d69e896ce38	1141
cparata	0:6d69e896ce38	1142	/**
cparata	0:6d69e896ce38	1143	* @defgroup LSM6DSO_common
cparata	0:6d69e896ce38	1144	* @brief This section groups common usefull functions.
cparata	0:6d69e896ce38	1145	* @{
cparata	0:6d69e896ce38	1146	*
cparata	0:6d69e896ce38	1147	*/
cparata	0:6d69e896ce38	1148
cparata	0:6d69e896ce38	1149	/**
cparata	0:6d69e896ce38	1150	* @brief Difference in percentage of the effective ODR(and timestamp rate)
cparata	0:6d69e896ce38	1151	* with respect to the typical.
cparata	0:6d69e896ce38	1152	* Step: 0.15%. 8-bit format, 2's complement.[set]
cparata	0:6d69e896ce38	1153	*
cparata	0:6d69e896ce38	1154	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1155	* @param val change the values of freq_fine in reg
cparata	0:6d69e896ce38	1156	* INTERNAL_FREQ_FINE
cparata	0:6d69e896ce38	1157	*
cparata	0:6d69e896ce38	1158	*/
cparata	0:6d69e896ce38	1159	int32_t lsm6dso_odr_cal_reg_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1160	{
cparata	3:4274d9103f1d	1161	lsm6dso_internal_freq_fine_t reg;
cparata	3:4274d9103f1d	1162	int32_t ret;
cparata	3:4274d9103f1d	1163
cparata	3:4274d9103f1d	1164	ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1165	if (ret == 0) {
cparata	3:4274d9103f1d	1166	reg.freq_fine = val;
cparata	3:4274d9103f1d	1167	ret = lsm6dso_write_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
cparata	3:4274d9103f1d	1168	(uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1169	}
cparata	3:4274d9103f1d	1170	return ret;
cparata	0:6d69e896ce38	1171	}
cparata	0:6d69e896ce38	1172
cparata	0:6d69e896ce38	1173	/**
cparata	0:6d69e896ce38	1174	* @brief Difference in percentage of the effective ODR(and timestamp rate)
cparata	0:6d69e896ce38	1175	* with respect to the typical.
cparata	0:6d69e896ce38	1176	* Step: 0.15%. 8-bit format, 2's complement.[get]
cparata	0:6d69e896ce38	1177	*
cparata	0:6d69e896ce38	1178	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1179	* @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
cparata	0:6d69e896ce38	1180	*
cparata	0:6d69e896ce38	1181	*/
cparata	0:6d69e896ce38	1182	int32_t lsm6dso_odr_cal_reg_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1183	{
cparata	3:4274d9103f1d	1184	lsm6dso_internal_freq_fine_t reg;
cparata	3:4274d9103f1d	1185	int32_t ret;
cparata	3:4274d9103f1d	1186
cparata	3:4274d9103f1d	1187	ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1188	*val = reg.freq_fine;
cparata	3:4274d9103f1d	1189
cparata	3:4274d9103f1d	1190	return ret;
cparata	0:6d69e896ce38	1191	}
cparata	0:6d69e896ce38	1192
cparata	0:6d69e896ce38	1193
cparata	0:6d69e896ce38	1194	/**
cparata	0:6d69e896ce38	1195	* @brief Enable access to the embedded functions/sensor
cparata	0:6d69e896ce38	1196	* hub configuration registers.[set]
cparata	0:6d69e896ce38	1197	*
cparata	0:6d69e896ce38	1198	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1199	* @param val change the values of reg_access in
cparata	0:6d69e896ce38	1200	* reg FUNC_CFG_ACCESS
cparata	0:6d69e896ce38	1201	*
cparata	0:6d69e896ce38	1202	*/
cparata	0:6d69e896ce38	1203	int32_t lsm6dso_mem_bank_set(lsm6dso_ctx_t *ctx, lsm6dso_reg_access_t val)
cparata	0:6d69e896ce38	1204	{
cparata	3:4274d9103f1d	1205	lsm6dso_func_cfg_access_t reg;
cparata	3:4274d9103f1d	1206	int32_t ret;
cparata	3:4274d9103f1d	1207
cparata	3:4274d9103f1d	1208	ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1209	if (ret == 0) {
cparata	3:4274d9103f1d	1210	reg.reg_access = (uint8_t)val;
cparata	3:4274d9103f1d	1211	ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1212	}
cparata	3:4274d9103f1d	1213	return ret;
cparata	0:6d69e896ce38	1214	}
cparata	0:6d69e896ce38	1215
cparata	0:6d69e896ce38	1216	/**
cparata	0:6d69e896ce38	1217	* @brief Enable access to the embedded functions/sensor
cparata	0:6d69e896ce38	1218	* hub configuration registers.[get]
cparata	0:6d69e896ce38	1219	*
cparata	0:6d69e896ce38	1220	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1221	* @param val Get the values of reg_access in
cparata	0:6d69e896ce38	1222	* reg FUNC_CFG_ACCESS
cparata	0:6d69e896ce38	1223	*
cparata	0:6d69e896ce38	1224	*/
cparata	0:6d69e896ce38	1225	int32_t lsm6dso_mem_bank_get(lsm6dso_ctx_t ctx, lsm6dso_reg_access_t val)
cparata	0:6d69e896ce38	1226	{
cparata	3:4274d9103f1d	1227	lsm6dso_func_cfg_access_t reg;
cparata	3:4274d9103f1d	1228	int32_t ret;
cparata	3:4274d9103f1d	1229
cparata	3:4274d9103f1d	1230	ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1231	switch (reg.reg_access) {
cparata	3:4274d9103f1d	1232	case LSM6DSO_USER_BANK:
cparata	3:4274d9103f1d	1233	*val = LSM6DSO_USER_BANK;
cparata	3:4274d9103f1d	1234	break;
cparata	3:4274d9103f1d	1235	case LSM6DSO_SENSOR_HUB_BANK:
cparata	3:4274d9103f1d	1236	*val = LSM6DSO_SENSOR_HUB_BANK;
cparata	3:4274d9103f1d	1237	break;
cparata	3:4274d9103f1d	1238	case LSM6DSO_EMBEDDED_FUNC_BANK:
cparata	3:4274d9103f1d	1239	*val = LSM6DSO_EMBEDDED_FUNC_BANK;
cparata	3:4274d9103f1d	1240	break;
cparata	3:4274d9103f1d	1241	default:
cparata	3:4274d9103f1d	1242	*val = LSM6DSO_USER_BANK;
cparata	3:4274d9103f1d	1243	break;
cparata	3:4274d9103f1d	1244	}
cparata	3:4274d9103f1d	1245	return ret;
cparata	0:6d69e896ce38	1246	}
cparata	0:6d69e896ce38	1247
cparata	0:6d69e896ce38	1248	/**
cparata	0:6d69e896ce38	1249	* @brief Write a line(byte) in a page.[set]
cparata	0:6d69e896ce38	1250	*
cparata	0:6d69e896ce38	1251	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1252	* @param uint8_t address: page line address
cparata	0:6d69e896ce38	1253	* @param val value to write
cparata	0:6d69e896ce38	1254	*
cparata	0:6d69e896ce38	1255	*/
cparata	0:6d69e896ce38	1256	int32_t lsm6dso_ln_pg_write_byte(lsm6dso_ctx_t *ctx, uint16_t address,
cparata	0:6d69e896ce38	1257	uint8_t *val)
cparata	0:6d69e896ce38	1258	{
cparata	3:4274d9103f1d	1259	lsm6dso_page_rw_t page_rw;
cparata	3:4274d9103f1d	1260	lsm6dso_page_sel_t page_sel;
cparata	3:4274d9103f1d	1261	lsm6dso_page_address_t page_address;
cparata	3:4274d9103f1d	1262	int32_t ret;
cparata	3:4274d9103f1d	1263
cparata	3:4274d9103f1d	1264	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	1265
cparata	3:4274d9103f1d	1266	if (ret == 0) {
cparata	3:4274d9103f1d	1267	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	1268	}
cparata	3:4274d9103f1d	1269	if (ret == 0) {
cparata	3:4274d9103f1d	1270	page_rw.page_rw = 0x02; /* page_write enable */
cparata	3:4274d9103f1d	1271	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	1272	}
cparata	3:4274d9103f1d	1273	if (ret == 0) {
cparata	3:4274d9103f1d	1274	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
cparata	3:4274d9103f1d	1275	}
cparata	3:4274d9103f1d	1276
cparata	3:4274d9103f1d	1277	if (ret == 0) {
cparata	3:4274d9103f1d	1278	page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
cparata	3:4274d9103f1d	1279	page_sel.not_used_01 = 1;
cparata	3:4274d9103f1d	1280	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
cparata	3:4274d9103f1d	1281	}
cparata	3:4274d9103f1d	1282	if (ret == 0) {
cparata	3:4274d9103f1d	1283	page_address.page_addr = (uint8_t)address & 0xFFU;
cparata	3:4274d9103f1d	1284	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
cparata	3:4274d9103f1d	1285	(uint8_t *)&page_address, 1);
cparata	3:4274d9103f1d	1286	}
cparata	3:4274d9103f1d	1287	if (ret == 0) {
cparata	3:4274d9103f1d	1288	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1);
cparata	3:4274d9103f1d	1289	}
cparata	3:4274d9103f1d	1290	if (ret == 0) {
cparata	3:4274d9103f1d	1291	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	1292	}
cparata	3:4274d9103f1d	1293	if (ret == 0) {
cparata	3:4274d9103f1d	1294	page_rw.page_rw = 0x00; /* page_write disable */
cparata	3:4274d9103f1d	1295	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	1296	}
cparata	3:4274d9103f1d	1297	if (ret == 0) {
cparata	3:4274d9103f1d	1298
cparata	3:4274d9103f1d	1299	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	1300	}
cparata	3:4274d9103f1d	1301	return ret;
cparata	0:6d69e896ce38	1302	}
cparata	0:6d69e896ce38	1303
cparata	0:6d69e896ce38	1304	/**
cparata	0:6d69e896ce38	1305	* @brief Write buffer in a page.[set]
cparata	0:6d69e896ce38	1306	*
cparata	0:6d69e896ce38	1307	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1308	* @param uint8_t address: page line address
cparata	0:6d69e896ce38	1309	* @param uint8_t *buf: buffer to write
cparata	0:6d69e896ce38	1310	* @param uint8_t len: buffer len
cparata	0:6d69e896ce38	1311	*
cparata	0:6d69e896ce38	1312	*/
cparata	0:6d69e896ce38	1313	int32_t lsm6dso_ln_pg_write(lsm6dso_ctx_t *ctx, uint16_t address,
cparata	0:6d69e896ce38	1314	uint8_t *buf, uint8_t len)
cparata	0:6d69e896ce38	1315	{
cparata	3:4274d9103f1d	1316	lsm6dso_page_rw_t page_rw;
cparata	3:4274d9103f1d	1317	lsm6dso_page_sel_t page_sel;
cparata	3:4274d9103f1d	1318	lsm6dso_page_address_t page_address;
cparata	3:4274d9103f1d	1319	uint16_t addr_pointed;
cparata	3:4274d9103f1d	1320	int32_t ret;
cparata	3:4274d9103f1d	1321	uint8_t i ;
cparata	3:4274d9103f1d	1322
cparata	3:4274d9103f1d	1323	addr_pointed = address;
cparata	3:4274d9103f1d	1324
cparata	3:4274d9103f1d	1325	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	1326	if (ret == 0) {
cparata	3:4274d9103f1d	1327
cparata	3:4274d9103f1d	1328	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	1329	}
cparata	3:4274d9103f1d	1330	if (ret == 0) {
cparata	3:4274d9103f1d	1331	page_rw.page_rw = 0x02; /* page_write enable*/
cparata	3:4274d9103f1d	1332	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	1333	}
cparata	3:4274d9103f1d	1334	if (ret == 0) {
cparata	3:4274d9103f1d	1335	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
cparata	3:4274d9103f1d	1336	}
cparata	3:4274d9103f1d	1337	if (ret == 0) {
cparata	3:4274d9103f1d	1338	page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
cparata	3:4274d9103f1d	1339	page_sel.not_used_01 = 1;
cparata	3:4274d9103f1d	1340	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
cparata	3:4274d9103f1d	1341	}
cparata	3:4274d9103f1d	1342	if (ret == 0) {
cparata	3:4274d9103f1d	1343	page_address.page_addr = (uint8_t)(addr_pointed & 0x00FFU);
cparata	3:4274d9103f1d	1344	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
cparata	3:4274d9103f1d	1345	(uint8_t *)&page_address, 1);
cparata	3:4274d9103f1d	1346	}
cparata	3:4274d9103f1d	1347
cparata	3:4274d9103f1d	1348	if (ret == 0) {
cparata	3:4274d9103f1d	1349	for (i = 0; ((i < len) && (ret == 0)); i++) {
cparata	3:4274d9103f1d	1350	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, &buf[i], 1);
cparata	3:4274d9103f1d	1351	addr_pointed++;
cparata	3:4274d9103f1d	1352	/* Check if page wrap */
cparata	3:4274d9103f1d	1353	if (((addr_pointed % 0x0100U) == 0x00U) && (ret == 0)) {
cparata	3:4274d9103f1d	1354	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *)&page_sel, 1);
cparata	3:4274d9103f1d	1355	if (ret == 0) {
cparata	3:4274d9103f1d	1356	page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
cparata	3:4274d9103f1d	1357	page_sel.not_used_01 = 1;
cparata	3:4274d9103f1d	1358	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL,
cparata	3:4274d9103f1d	1359	(uint8_t *)&page_sel, 1);
cparata	3:4274d9103f1d	1360	}
cparata	3:4274d9103f1d	1361	}
cparata	0:6d69e896ce38	1362	}
cparata	3:4274d9103f1d	1363	page_sel.page_sel = 0;
cparata	3:4274d9103f1d	1364	page_sel.not_used_01 = 1;
cparata	3:4274d9103f1d	1365	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
cparata	3:4274d9103f1d	1366	}
cparata	3:4274d9103f1d	1367	if (ret == 0) {
cparata	3:4274d9103f1d	1368	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	1369	}
cparata	3:4274d9103f1d	1370	if (ret == 0) {
cparata	3:4274d9103f1d	1371	page_rw.page_rw = 0x00; /* page_write disable */
cparata	3:4274d9103f1d	1372	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	1373	}
cparata	3:4274d9103f1d	1374	if (ret == 0) {
cparata	3:4274d9103f1d	1375	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	1376	}
cparata	3:4274d9103f1d	1377	return ret;
cparata	0:6d69e896ce38	1378	}
cparata	0:6d69e896ce38	1379
cparata	0:6d69e896ce38	1380	/**
cparata	0:6d69e896ce38	1381	* @brief Read a line(byte) in a page.[get]
cparata	0:6d69e896ce38	1382	*
cparata	0:6d69e896ce38	1383	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1384	* @param uint8_t address: page line address
cparata	0:6d69e896ce38	1385	* @param val read value
cparata	0:6d69e896ce38	1386	*
cparata	0:6d69e896ce38	1387	*/
cparata	0:6d69e896ce38	1388	int32_t lsm6dso_ln_pg_read_byte(lsm6dso_ctx_t *ctx, uint16_t address,
cparata	0:6d69e896ce38	1389	uint8_t *val)
cparata	0:6d69e896ce38	1390	{
cparata	3:4274d9103f1d	1391	lsm6dso_page_rw_t page_rw;
cparata	3:4274d9103f1d	1392	lsm6dso_page_sel_t page_sel;
cparata	3:4274d9103f1d	1393	lsm6dso_page_address_t page_address;
cparata	3:4274d9103f1d	1394	int32_t ret;
cparata	3:4274d9103f1d	1395
cparata	3:4274d9103f1d	1396	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	1397	if (ret == 0) {
cparata	3:4274d9103f1d	1398
cparata	3:4274d9103f1d	1399	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	1400	}
cparata	3:4274d9103f1d	1401	if (ret == 0) {
cparata	3:4274d9103f1d	1402	page_rw.page_rw = 0x01; /* page_read enable*/
cparata	3:4274d9103f1d	1403	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	1404	}
cparata	3:4274d9103f1d	1405	if (ret == 0) {
cparata	3:4274d9103f1d	1406
cparata	3:4274d9103f1d	1407	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
cparata	3:4274d9103f1d	1408	}
cparata	3:4274d9103f1d	1409	if (ret == 0) {
cparata	3:4274d9103f1d	1410	page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
cparata	3:4274d9103f1d	1411	page_sel.not_used_01 = 1;
cparata	3:4274d9103f1d	1412	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
cparata	3:4274d9103f1d	1413	}
cparata	3:4274d9103f1d	1414	if (ret == 0) {
cparata	3:4274d9103f1d	1415	page_address.page_addr = (uint8_t)address & 0x00FFU;
cparata	3:4274d9103f1d	1416	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
cparata	3:4274d9103f1d	1417	(uint8_t *)&page_address, 1);
cparata	3:4274d9103f1d	1418	}
cparata	3:4274d9103f1d	1419	if (ret == 0) {
cparata	3:4274d9103f1d	1420
cparata	3:4274d9103f1d	1421	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_VALUE, val, 2);
cparata	3:4274d9103f1d	1422	}
cparata	3:4274d9103f1d	1423	if (ret == 0) {
cparata	3:4274d9103f1d	1424	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	1425	}
cparata	3:4274d9103f1d	1426	if (ret == 0) {
cparata	3:4274d9103f1d	1427	page_rw.page_rw = 0x00; /* page_read disable */
cparata	3:4274d9103f1d	1428	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	1429	}
cparata	3:4274d9103f1d	1430	if (ret == 0) {
cparata	3:4274d9103f1d	1431	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	1432	}
cparata	3:4274d9103f1d	1433
cparata	3:4274d9103f1d	1434	return ret;
cparata	0:6d69e896ce38	1435	}
cparata	0:6d69e896ce38	1436
cparata	0:6d69e896ce38	1437	/**
cparata	0:6d69e896ce38	1438	* @brief Data-ready pulsed / letched mode.[set]
cparata	0:6d69e896ce38	1439	*
cparata	0:6d69e896ce38	1440	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1441	* @param val change the values of
cparata	0:6d69e896ce38	1442	* dataready_pulsed in
cparata	0:6d69e896ce38	1443	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	1444	*
cparata	0:6d69e896ce38	1445	*/
cparata	0:6d69e896ce38	1446	int32_t lsm6dso_data_ready_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1447	lsm6dso_dataready_pulsed_t val)
cparata	0:6d69e896ce38	1448	{
cparata	3:4274d9103f1d	1449	lsm6dso_counter_bdr_reg1_t reg;
cparata	3:4274d9103f1d	1450	int32_t ret;
cparata	3:4274d9103f1d	1451
cparata	3:4274d9103f1d	1452	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1453	if (ret == 0) {
cparata	3:4274d9103f1d	1454	reg.dataready_pulsed = (uint8_t)val;
cparata	3:4274d9103f1d	1455	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1456	}
cparata	3:4274d9103f1d	1457	return ret;
cparata	0:6d69e896ce38	1458	}
cparata	0:6d69e896ce38	1459
cparata	0:6d69e896ce38	1460	/**
cparata	0:6d69e896ce38	1461	* @brief Data-ready pulsed / letched mode.[get]
cparata	0:6d69e896ce38	1462	*
cparata	0:6d69e896ce38	1463	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1464	* @param val Get the values of
cparata	0:6d69e896ce38	1465	* dataready_pulsed in
cparata	0:6d69e896ce38	1466	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	1467	*
cparata	0:6d69e896ce38	1468	*/
cparata	0:6d69e896ce38	1469	int32_t lsm6dso_data_ready_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1470	lsm6dso_dataready_pulsed_t *val)
cparata	0:6d69e896ce38	1471	{
cparata	3:4274d9103f1d	1472	lsm6dso_counter_bdr_reg1_t reg;
cparata	3:4274d9103f1d	1473	int32_t ret;
cparata	3:4274d9103f1d	1474
cparata	3:4274d9103f1d	1475	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1476	switch (reg.dataready_pulsed) {
cparata	3:4274d9103f1d	1477	case LSM6DSO_DRDY_LATCHED:
cparata	3:4274d9103f1d	1478	*val = LSM6DSO_DRDY_LATCHED;
cparata	3:4274d9103f1d	1479	break;
cparata	3:4274d9103f1d	1480	case LSM6DSO_DRDY_PULSED:
cparata	3:4274d9103f1d	1481	*val = LSM6DSO_DRDY_PULSED;
cparata	3:4274d9103f1d	1482	break;
cparata	3:4274d9103f1d	1483	default:
cparata	3:4274d9103f1d	1484	*val = LSM6DSO_DRDY_LATCHED;
cparata	3:4274d9103f1d	1485	break;
cparata	3:4274d9103f1d	1486	}
cparata	3:4274d9103f1d	1487	return ret;
cparata	0:6d69e896ce38	1488	}
cparata	0:6d69e896ce38	1489
cparata	0:6d69e896ce38	1490	/**
cparata	0:6d69e896ce38	1491	* @brief Device "Who am I".[get]
cparata	0:6d69e896ce38	1492	*
cparata	0:6d69e896ce38	1493	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1494	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1495	*
cparata	0:6d69e896ce38	1496	*/
cparata	0:6d69e896ce38	1497	int32_t lsm6dso_device_id_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1498	{
cparata	3:4274d9103f1d	1499	int32_t ret;
cparata	3:4274d9103f1d	1500	ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I, buff, 1);
cparata	3:4274d9103f1d	1501	return ret;
cparata	0:6d69e896ce38	1502	}
cparata	0:6d69e896ce38	1503
cparata	0:6d69e896ce38	1504	/**
cparata	0:6d69e896ce38	1505	* @brief Software reset. Restore the default values
cparata	0:6d69e896ce38	1506	* in user registers[set]
cparata	0:6d69e896ce38	1507	*
cparata	0:6d69e896ce38	1508	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1509	* @param val change the values of sw_reset in reg CTRL3_C
cparata	0:6d69e896ce38	1510	*
cparata	0:6d69e896ce38	1511	*/
cparata	0:6d69e896ce38	1512	int32_t lsm6dso_reset_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1513	{
cparata	3:4274d9103f1d	1514	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	1515	int32_t ret;
cparata	3:4274d9103f1d	1516
cparata	3:4274d9103f1d	1517	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1518	if (ret == 0) {
cparata	3:4274d9103f1d	1519	reg.sw_reset = val;
cparata	3:4274d9103f1d	1520	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1521	}
cparata	3:4274d9103f1d	1522
cparata	3:4274d9103f1d	1523	return ret;
cparata	0:6d69e896ce38	1524	}
cparata	0:6d69e896ce38	1525
cparata	0:6d69e896ce38	1526	/**
cparata	0:6d69e896ce38	1527	* @brief Software reset. Restore the default values in user registers.[get]
cparata	0:6d69e896ce38	1528	*
cparata	0:6d69e896ce38	1529	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1530	* @param val change the values of sw_reset in reg CTRL3_C
cparata	0:6d69e896ce38	1531	*
cparata	0:6d69e896ce38	1532	*/
cparata	0:6d69e896ce38	1533	int32_t lsm6dso_reset_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1534	{
cparata	3:4274d9103f1d	1535	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	1536	int32_t ret;
cparata	3:4274d9103f1d	1537
cparata	3:4274d9103f1d	1538	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1539	*val = reg.sw_reset;
cparata	3:4274d9103f1d	1540
cparata	3:4274d9103f1d	1541	return ret;
cparata	0:6d69e896ce38	1542	}
cparata	0:6d69e896ce38	1543
cparata	0:6d69e896ce38	1544	/**
cparata	0:6d69e896ce38	1545	* @brief Register address automatically incremented during a multiple byte
cparata	0:6d69e896ce38	1546	* access with a serial interface.[set]
cparata	0:6d69e896ce38	1547	*
cparata	0:6d69e896ce38	1548	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1549	* @param val change the values of if_inc in reg CTRL3_C
cparata	0:6d69e896ce38	1550	*
cparata	0:6d69e896ce38	1551	*/
cparata	0:6d69e896ce38	1552	int32_t lsm6dso_auto_increment_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1553	{
cparata	3:4274d9103f1d	1554	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	1555	int32_t ret;
cparata	3:4274d9103f1d	1556
cparata	3:4274d9103f1d	1557	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1558	if (ret == 0) {
cparata	3:4274d9103f1d	1559	reg.if_inc = val;
cparata	3:4274d9103f1d	1560	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1561	}
cparata	3:4274d9103f1d	1562	return ret;
cparata	0:6d69e896ce38	1563	}
cparata	0:6d69e896ce38	1564
cparata	0:6d69e896ce38	1565	/**
cparata	0:6d69e896ce38	1566	* @brief Register address automatically incremented during a multiple byte
cparata	0:6d69e896ce38	1567	* access with a serial interface.[get]
cparata	0:6d69e896ce38	1568	*
cparata	0:6d69e896ce38	1569	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1570	* @param val change the values of if_inc in reg CTRL3_C
cparata	0:6d69e896ce38	1571	*
cparata	0:6d69e896ce38	1572	*/
cparata	0:6d69e896ce38	1573	int32_t lsm6dso_auto_increment_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1574	{
cparata	3:4274d9103f1d	1575	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	1576	int32_t ret;
cparata	3:4274d9103f1d	1577
cparata	3:4274d9103f1d	1578	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1579	*val = reg.if_inc;
cparata	3:4274d9103f1d	1580
cparata	3:4274d9103f1d	1581	return ret;
cparata	0:6d69e896ce38	1582	}
cparata	0:6d69e896ce38	1583
cparata	0:6d69e896ce38	1584	/**
cparata	0:6d69e896ce38	1585	* @brief Reboot memory content. Reload the calibration parameters.[set]
cparata	0:6d69e896ce38	1586	*
cparata	0:6d69e896ce38	1587	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1588	* @param val change the values of boot in reg CTRL3_C
cparata	0:6d69e896ce38	1589	*
cparata	0:6d69e896ce38	1590	*/
cparata	0:6d69e896ce38	1591	int32_t lsm6dso_boot_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1592	{
cparata	3:4274d9103f1d	1593	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	1594	int32_t ret;
cparata	3:4274d9103f1d	1595
cparata	3:4274d9103f1d	1596	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1597	if (ret == 0) {
cparata	3:4274d9103f1d	1598	reg.boot = val;
cparata	3:4274d9103f1d	1599	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1600	}
cparata	3:4274d9103f1d	1601	return ret;
cparata	0:6d69e896ce38	1602	}
cparata	0:6d69e896ce38	1603
cparata	0:6d69e896ce38	1604	/**
cparata	0:6d69e896ce38	1605	* @brief Reboot memory content. Reload the calibration parameters.[get]
cparata	0:6d69e896ce38	1606	*
cparata	0:6d69e896ce38	1607	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1608	* @param val change the values of boot in reg CTRL3_C
cparata	0:6d69e896ce38	1609	*
cparata	0:6d69e896ce38	1610	*/
cparata	0:6d69e896ce38	1611	int32_t lsm6dso_boot_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1612	{
cparata	3:4274d9103f1d	1613	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	1614	int32_t ret;
cparata	3:4274d9103f1d	1615
cparata	3:4274d9103f1d	1616	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1617	*val = reg.boot;
cparata	3:4274d9103f1d	1618
cparata	3:4274d9103f1d	1619	return ret;
cparata	0:6d69e896ce38	1620	}
cparata	0:6d69e896ce38	1621
cparata	0:6d69e896ce38	1622	/**
cparata	0:6d69e896ce38	1623	* @brief Linear acceleration sensor self-test enable.[set]
cparata	0:6d69e896ce38	1624	*
cparata	0:6d69e896ce38	1625	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1626	* @param val change the values of st_xl in reg CTRL5_C
cparata	0:6d69e896ce38	1627	*
cparata	0:6d69e896ce38	1628	*/
cparata	0:6d69e896ce38	1629	int32_t lsm6dso_xl_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_xl_t val)
cparata	0:6d69e896ce38	1630	{
cparata	3:4274d9103f1d	1631	lsm6dso_ctrl5_c_t reg;
cparata	3:4274d9103f1d	1632	int32_t ret;
cparata	3:4274d9103f1d	1633
cparata	3:4274d9103f1d	1634	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1635	if (ret == 0) {
cparata	3:4274d9103f1d	1636	reg.st_xl = (uint8_t)val;
cparata	3:4274d9103f1d	1637	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1638	}
cparata	3:4274d9103f1d	1639	return ret;
cparata	0:6d69e896ce38	1640	}
cparata	0:6d69e896ce38	1641
cparata	0:6d69e896ce38	1642	/**
cparata	0:6d69e896ce38	1643	* @brief Linear acceleration sensor self-test enable.[get]
cparata	0:6d69e896ce38	1644	*
cparata	0:6d69e896ce38	1645	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1646	* @param val Get the values of st_xl in reg CTRL5_C
cparata	0:6d69e896ce38	1647	*
cparata	0:6d69e896ce38	1648	*/
cparata	0:6d69e896ce38	1649	int32_t lsm6dso_xl_self_test_get(lsm6dso_ctx_t ctx, lsm6dso_st_xl_t val)
cparata	0:6d69e896ce38	1650	{
cparata	3:4274d9103f1d	1651	lsm6dso_ctrl5_c_t reg;
cparata	3:4274d9103f1d	1652	int32_t ret;
cparata	3:4274d9103f1d	1653
cparata	3:4274d9103f1d	1654	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1655	switch (reg.st_xl) {
cparata	3:4274d9103f1d	1656	case LSM6DSO_XL_ST_DISABLE:
cparata	3:4274d9103f1d	1657	*val = LSM6DSO_XL_ST_DISABLE;
cparata	3:4274d9103f1d	1658	break;
cparata	3:4274d9103f1d	1659	case LSM6DSO_XL_ST_POSITIVE:
cparata	3:4274d9103f1d	1660	*val = LSM6DSO_XL_ST_POSITIVE;
cparata	3:4274d9103f1d	1661	break;
cparata	3:4274d9103f1d	1662	case LSM6DSO_XL_ST_NEGATIVE:
cparata	3:4274d9103f1d	1663	*val = LSM6DSO_XL_ST_NEGATIVE;
cparata	3:4274d9103f1d	1664	break;
cparata	3:4274d9103f1d	1665	default:
cparata	3:4274d9103f1d	1666	*val = LSM6DSO_XL_ST_DISABLE;
cparata	3:4274d9103f1d	1667	break;
cparata	3:4274d9103f1d	1668	}
cparata	3:4274d9103f1d	1669	return ret;
cparata	0:6d69e896ce38	1670	}
cparata	0:6d69e896ce38	1671
cparata	0:6d69e896ce38	1672	/**
cparata	0:6d69e896ce38	1673	* @brief Angular rate sensor self-test enable.[set]
cparata	0:6d69e896ce38	1674	*
cparata	0:6d69e896ce38	1675	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1676	* @param val change the values of st_g in reg CTRL5_C
cparata	0:6d69e896ce38	1677	*
cparata	0:6d69e896ce38	1678	*/
cparata	0:6d69e896ce38	1679	int32_t lsm6dso_gy_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_g_t val)
cparata	0:6d69e896ce38	1680	{
cparata	3:4274d9103f1d	1681	lsm6dso_ctrl5_c_t reg;
cparata	3:4274d9103f1d	1682	int32_t ret;
cparata	3:4274d9103f1d	1683
cparata	3:4274d9103f1d	1684	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1685	if (ret == 0) {
cparata	3:4274d9103f1d	1686	reg.st_g = (uint8_t)val;
cparata	3:4274d9103f1d	1687	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1688	}
cparata	3:4274d9103f1d	1689	return ret;
cparata	0:6d69e896ce38	1690	}
cparata	0:6d69e896ce38	1691
cparata	0:6d69e896ce38	1692	/**
cparata	0:6d69e896ce38	1693	* @brief Angular rate sensor self-test enable.[get]
cparata	0:6d69e896ce38	1694	*
cparata	0:6d69e896ce38	1695	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1696	* @param val Get the values of st_g in reg CTRL5_C
cparata	0:6d69e896ce38	1697	*
cparata	0:6d69e896ce38	1698	*/
cparata	0:6d69e896ce38	1699	int32_t lsm6dso_gy_self_test_get(lsm6dso_ctx_t ctx, lsm6dso_st_g_t val)
cparata	0:6d69e896ce38	1700	{
cparata	3:4274d9103f1d	1701	lsm6dso_ctrl5_c_t reg;
cparata	3:4274d9103f1d	1702	int32_t ret;
cparata	3:4274d9103f1d	1703
cparata	3:4274d9103f1d	1704	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1705	switch (reg.st_g) {
cparata	3:4274d9103f1d	1706	case LSM6DSO_GY_ST_DISABLE:
cparata	3:4274d9103f1d	1707	*val = LSM6DSO_GY_ST_DISABLE;
cparata	3:4274d9103f1d	1708	break;
cparata	3:4274d9103f1d	1709	case LSM6DSO_GY_ST_POSITIVE:
cparata	3:4274d9103f1d	1710	*val = LSM6DSO_GY_ST_POSITIVE;
cparata	3:4274d9103f1d	1711	break;
cparata	3:4274d9103f1d	1712	case LSM6DSO_GY_ST_NEGATIVE:
cparata	3:4274d9103f1d	1713	*val = LSM6DSO_GY_ST_NEGATIVE;
cparata	3:4274d9103f1d	1714	break;
cparata	3:4274d9103f1d	1715	default:
cparata	3:4274d9103f1d	1716	*val = LSM6DSO_GY_ST_DISABLE;
cparata	3:4274d9103f1d	1717	break;
cparata	3:4274d9103f1d	1718	}
cparata	3:4274d9103f1d	1719	return ret;
cparata	0:6d69e896ce38	1720	}
cparata	0:6d69e896ce38	1721
cparata	0:6d69e896ce38	1722	/**
cparata	0:6d69e896ce38	1723	* @}
cparata	0:6d69e896ce38	1724	*
cparata	0:6d69e896ce38	1725	*/
cparata	0:6d69e896ce38	1726
cparata	0:6d69e896ce38	1727	/**
cparata	0:6d69e896ce38	1728	* @defgroup LSM6DSO_filters
cparata	0:6d69e896ce38	1729	* @brief This section group all the functions concerning the
cparata	0:6d69e896ce38	1730	* filters configuration
cparata	0:6d69e896ce38	1731	* @{
cparata	0:6d69e896ce38	1732	*
cparata	0:6d69e896ce38	1733	*/
cparata	0:6d69e896ce38	1734
cparata	0:6d69e896ce38	1735	/**
cparata	0:6d69e896ce38	1736	* @brief Accelerometer output from LPF2 filtering stage selection.[set]
cparata	0:6d69e896ce38	1737	*
cparata	0:6d69e896ce38	1738	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1739	* @param val change the values of lpf2_xl_en in reg CTRL1_XL
cparata	0:6d69e896ce38	1740	*
cparata	0:6d69e896ce38	1741	*/
cparata	0:6d69e896ce38	1742	int32_t lsm6dso_xl_filter_lp2_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1743	{
cparata	3:4274d9103f1d	1744	lsm6dso_ctrl1_xl_t reg;
cparata	3:4274d9103f1d	1745	int32_t ret;
cparata	3:4274d9103f1d	1746
cparata	3:4274d9103f1d	1747	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1748	if (ret == 0) {
cparata	3:4274d9103f1d	1749	reg.lpf2_xl_en = val;
cparata	3:4274d9103f1d	1750	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1751	}
cparata	3:4274d9103f1d	1752	return ret;
cparata	0:6d69e896ce38	1753	}
cparata	0:6d69e896ce38	1754
cparata	0:6d69e896ce38	1755	/**
cparata	0:6d69e896ce38	1756	* @brief Accelerometer output from LPF2 filtering stage selection.[get]
cparata	0:6d69e896ce38	1757	*
cparata	0:6d69e896ce38	1758	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1759	* @param val change the values of lpf2_xl_en in reg CTRL1_XL
cparata	0:6d69e896ce38	1760	*
cparata	0:6d69e896ce38	1761	*/
cparata	0:6d69e896ce38	1762	int32_t lsm6dso_xl_filter_lp2_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1763	{
cparata	3:4274d9103f1d	1764	lsm6dso_ctrl1_xl_t reg;
cparata	3:4274d9103f1d	1765	int32_t ret;
cparata	3:4274d9103f1d	1766
cparata	3:4274d9103f1d	1767	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1768	*val = reg.lpf2_xl_en;
cparata	3:4274d9103f1d	1769
cparata	3:4274d9103f1d	1770	return ret;
cparata	0:6d69e896ce38	1771	}
cparata	0:6d69e896ce38	1772
cparata	0:6d69e896ce38	1773	/**
cparata	0:6d69e896ce38	1774	* @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
cparata	0:6d69e896ce38	1775	* the bandwidth can be selected through FTYPE [2:0]
cparata	0:6d69e896ce38	1776	* in CTRL6_C (15h).[set]
cparata	0:6d69e896ce38	1777	*
cparata	0:6d69e896ce38	1778	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1779	* @param val change the values of lpf1_sel_g in reg CTRL4_C
cparata	0:6d69e896ce38	1780	*
cparata	0:6d69e896ce38	1781	*/
cparata	0:6d69e896ce38	1782	int32_t lsm6dso_gy_filter_lp1_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1783	{
cparata	3:4274d9103f1d	1784	lsm6dso_ctrl4_c_t reg;
cparata	3:4274d9103f1d	1785	int32_t ret;
cparata	3:4274d9103f1d	1786
cparata	3:4274d9103f1d	1787	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1788	if (ret == 0) {
cparata	3:4274d9103f1d	1789	reg.lpf1_sel_g = val;
cparata	3:4274d9103f1d	1790	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1791	}
cparata	3:4274d9103f1d	1792	return ret;
cparata	0:6d69e896ce38	1793	}
cparata	0:6d69e896ce38	1794
cparata	0:6d69e896ce38	1795	/**
cparata	0:6d69e896ce38	1796	* @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
cparata	0:6d69e896ce38	1797	* the bandwidth can be selected through FTYPE [2:0]
cparata	0:6d69e896ce38	1798	* in CTRL6_C (15h).[get]
cparata	0:6d69e896ce38	1799	*
cparata	0:6d69e896ce38	1800	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1801	* @param val change the values of lpf1_sel_g in reg CTRL4_C
cparata	0:6d69e896ce38	1802	*
cparata	0:6d69e896ce38	1803	*/
cparata	0:6d69e896ce38	1804	int32_t lsm6dso_gy_filter_lp1_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1805	{
cparata	3:4274d9103f1d	1806	lsm6dso_ctrl4_c_t reg;
cparata	3:4274d9103f1d	1807	int32_t ret;
cparata	3:4274d9103f1d	1808
cparata	3:4274d9103f1d	1809	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1810	*val = reg.lpf1_sel_g;
cparata	3:4274d9103f1d	1811
cparata	3:4274d9103f1d	1812	return ret;
cparata	0:6d69e896ce38	1813	}
cparata	0:6d69e896ce38	1814
cparata	0:6d69e896ce38	1815	/**
cparata	0:6d69e896ce38	1816	* @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
cparata	0:6d69e896ce38	1817	* (XL and Gyro independently masked).[set]
cparata	0:6d69e896ce38	1818	*
cparata	0:6d69e896ce38	1819	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1820	* @param val change the values of drdy_mask in reg CTRL4_C
cparata	0:6d69e896ce38	1821	*
cparata	0:6d69e896ce38	1822	*/
cparata	0:6d69e896ce38	1823	int32_t lsm6dso_filter_settling_mask_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1824	{
cparata	3:4274d9103f1d	1825	lsm6dso_ctrl4_c_t reg;
cparata	3:4274d9103f1d	1826	int32_t ret;
cparata	3:4274d9103f1d	1827
cparata	3:4274d9103f1d	1828	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1829	if (ret == 0) {
cparata	3:4274d9103f1d	1830	reg.drdy_mask = val;
cparata	3:4274d9103f1d	1831	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1832	}
cparata	3:4274d9103f1d	1833	return ret;
cparata	0:6d69e896ce38	1834	}
cparata	0:6d69e896ce38	1835
cparata	0:6d69e896ce38	1836	/**
cparata	0:6d69e896ce38	1837	* @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
cparata	0:6d69e896ce38	1838	* (XL and Gyro independently masked).[get]
cparata	0:6d69e896ce38	1839	*
cparata	0:6d69e896ce38	1840	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1841	* @param val change the values of drdy_mask in reg CTRL4_C
cparata	0:6d69e896ce38	1842	*
cparata	0:6d69e896ce38	1843	*/
cparata	0:6d69e896ce38	1844	int32_t lsm6dso_filter_settling_mask_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1845	{
cparata	3:4274d9103f1d	1846	lsm6dso_ctrl4_c_t reg;
cparata	3:4274d9103f1d	1847	int32_t ret;
cparata	3:4274d9103f1d	1848
cparata	3:4274d9103f1d	1849	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1850	*val = reg.drdy_mask;
cparata	3:4274d9103f1d	1851
cparata	3:4274d9103f1d	1852	return ret;
cparata	0:6d69e896ce38	1853	}
cparata	0:6d69e896ce38	1854
cparata	0:6d69e896ce38	1855	/**
cparata	0:6d69e896ce38	1856	* @brief Gyroscope lp1 bandwidth.[set]
cparata	0:6d69e896ce38	1857	*
cparata	0:6d69e896ce38	1858	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1859	* @param val change the values of ftype in reg CTRL6_C
cparata	0:6d69e896ce38	1860	*
cparata	0:6d69e896ce38	1861	*/
cparata	0:6d69e896ce38	1862	int32_t lsm6dso_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx, lsm6dso_ftype_t val)
cparata	0:6d69e896ce38	1863	{
cparata	3:4274d9103f1d	1864	lsm6dso_ctrl6_c_t reg;
cparata	3:4274d9103f1d	1865	int32_t ret;
cparata	3:4274d9103f1d	1866
cparata	3:4274d9103f1d	1867	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1868	if (ret == 0) {
cparata	3:4274d9103f1d	1869	reg.ftype = (uint8_t)val;
cparata	3:4274d9103f1d	1870	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1871	}
cparata	3:4274d9103f1d	1872	return ret;
cparata	0:6d69e896ce38	1873	}
cparata	0:6d69e896ce38	1874
cparata	0:6d69e896ce38	1875	/**
cparata	0:6d69e896ce38	1876	* @brief Gyroscope lp1 bandwidth.[get]
cparata	0:6d69e896ce38	1877	*
cparata	0:6d69e896ce38	1878	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1879	* @param val Get the values of ftype in reg CTRL6_C
cparata	0:6d69e896ce38	1880	*
cparata	0:6d69e896ce38	1881	*/
cparata	0:6d69e896ce38	1882	int32_t lsm6dso_gy_lp1_bandwidth_get(lsm6dso_ctx_t ctx, lsm6dso_ftype_t val)
cparata	0:6d69e896ce38	1883	{
cparata	3:4274d9103f1d	1884	lsm6dso_ctrl6_c_t reg;
cparata	3:4274d9103f1d	1885	int32_t ret;
cparata	3:4274d9103f1d	1886
cparata	3:4274d9103f1d	1887	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1888	switch (reg.ftype) {
cparata	3:4274d9103f1d	1889	case LSM6DSO_ULTRA_LIGHT:
cparata	3:4274d9103f1d	1890	*val = LSM6DSO_ULTRA_LIGHT;
cparata	3:4274d9103f1d	1891	break;
cparata	3:4274d9103f1d	1892	case LSM6DSO_VERY_LIGHT:
cparata	3:4274d9103f1d	1893	*val = LSM6DSO_VERY_LIGHT;
cparata	3:4274d9103f1d	1894	break;
cparata	3:4274d9103f1d	1895	case LSM6DSO_LIGHT:
cparata	3:4274d9103f1d	1896	*val = LSM6DSO_LIGHT;
cparata	3:4274d9103f1d	1897	break;
cparata	3:4274d9103f1d	1898	case LSM6DSO_MEDIUM:
cparata	3:4274d9103f1d	1899	*val = LSM6DSO_MEDIUM;
cparata	3:4274d9103f1d	1900	break;
cparata	3:4274d9103f1d	1901	case LSM6DSO_STRONG:
cparata	3:4274d9103f1d	1902	*val = LSM6DSO_STRONG;
cparata	3:4274d9103f1d	1903	break;
cparata	3:4274d9103f1d	1904	case LSM6DSO_VERY_STRONG:
cparata	3:4274d9103f1d	1905	*val = LSM6DSO_VERY_STRONG;
cparata	3:4274d9103f1d	1906	break;
cparata	3:4274d9103f1d	1907	case LSM6DSO_AGGRESSIVE:
cparata	3:4274d9103f1d	1908	*val = LSM6DSO_AGGRESSIVE;
cparata	3:4274d9103f1d	1909	break;
cparata	3:4274d9103f1d	1910	case LSM6DSO_XTREME:
cparata	3:4274d9103f1d	1911	*val = LSM6DSO_XTREME;
cparata	3:4274d9103f1d	1912	break;
cparata	3:4274d9103f1d	1913	default:
cparata	3:4274d9103f1d	1914	*val = LSM6DSO_ULTRA_LIGHT;
cparata	3:4274d9103f1d	1915	break;
cparata	3:4274d9103f1d	1916	}
cparata	3:4274d9103f1d	1917	return ret;
cparata	0:6d69e896ce38	1918	}
cparata	0:6d69e896ce38	1919
cparata	0:6d69e896ce38	1920	/**
cparata	0:6d69e896ce38	1921	* @brief Low pass filter 2 on 6D function selection.[set]
cparata	0:6d69e896ce38	1922	*
cparata	0:6d69e896ce38	1923	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1924	* @param val change the values of low_pass_on_6d in reg CTRL8_XL
cparata	0:6d69e896ce38	1925	*
cparata	0:6d69e896ce38	1926	*/
cparata	0:6d69e896ce38	1927	int32_t lsm6dso_xl_lp2_on_6d_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1928	{
cparata	3:4274d9103f1d	1929	lsm6dso_ctrl8_xl_t reg;
cparata	3:4274d9103f1d	1930	int32_t ret;
cparata	3:4274d9103f1d	1931
cparata	3:4274d9103f1d	1932	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1933	if (ret == 0) {
cparata	3:4274d9103f1d	1934	reg.low_pass_on_6d = val;
cparata	3:4274d9103f1d	1935	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1936	}
cparata	3:4274d9103f1d	1937	return ret;
cparata	0:6d69e896ce38	1938	}
cparata	0:6d69e896ce38	1939
cparata	0:6d69e896ce38	1940	/**
cparata	0:6d69e896ce38	1941	* @brief Low pass filter 2 on 6D function selection.[get]
cparata	0:6d69e896ce38	1942	*
cparata	0:6d69e896ce38	1943	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1944	* @param val change the values of low_pass_on_6d in reg CTRL8_XL
cparata	0:6d69e896ce38	1945	*
cparata	0:6d69e896ce38	1946	*/
cparata	0:6d69e896ce38	1947	int32_t lsm6dso_xl_lp2_on_6d_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1948	{
cparata	3:4274d9103f1d	1949	lsm6dso_ctrl8_xl_t reg;
cparata	3:4274d9103f1d	1950	int32_t ret;
cparata	3:4274d9103f1d	1951
cparata	3:4274d9103f1d	1952	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1953	*val = reg.low_pass_on_6d;
cparata	3:4274d9103f1d	1954
cparata	3:4274d9103f1d	1955	return ret;
cparata	0:6d69e896ce38	1956	}
cparata	0:6d69e896ce38	1957
cparata	0:6d69e896ce38	1958	/**
cparata	0:6d69e896ce38	1959	* @brief Accelerometer slope filter / high-pass filter selection
cparata	0:6d69e896ce38	1960	* on output.[set]
cparata	0:6d69e896ce38	1961	*
cparata	0:6d69e896ce38	1962	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1963	* @param val change the values of hp_slope_xl_en
cparata	0:6d69e896ce38	1964	* in reg CTRL8_XL
cparata	0:6d69e896ce38	1965	*
cparata	0:6d69e896ce38	1966	*/
cparata	0:6d69e896ce38	1967	int32_t lsm6dso_xl_hp_path_on_out_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1968	lsm6dso_hp_slope_xl_en_t val)
cparata	0:6d69e896ce38	1969	{
cparata	3:4274d9103f1d	1970	lsm6dso_ctrl8_xl_t reg;
cparata	3:4274d9103f1d	1971	int32_t ret;
cparata	3:4274d9103f1d	1972
cparata	3:4274d9103f1d	1973	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1974	if (ret == 0) {
cparata	3:4274d9103f1d	1975	reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
cparata	3:4274d9103f1d	1976	reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
cparata	3:4274d9103f1d	1977	reg.hpcf_xl = (uint8_t)val & 0x07U;
cparata	3:4274d9103f1d	1978	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1979	}
cparata	3:4274d9103f1d	1980	return ret;
cparata	0:6d69e896ce38	1981	}
cparata	0:6d69e896ce38	1982
cparata	0:6d69e896ce38	1983	/**
cparata	0:6d69e896ce38	1984	* @brief Accelerometer slope filter / high-pass filter selection
cparata	0:6d69e896ce38	1985	* on output.[get]
cparata	0:6d69e896ce38	1986	*
cparata	0:6d69e896ce38	1987	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1988	* @param val Get the values of hp_slope_xl_en
cparata	0:6d69e896ce38	1989	* in reg CTRL8_XL
cparata	0:6d69e896ce38	1990	*
cparata	0:6d69e896ce38	1991	*/
cparata	0:6d69e896ce38	1992	int32_t lsm6dso_xl_hp_path_on_out_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1993	lsm6dso_hp_slope_xl_en_t *val)
cparata	0:6d69e896ce38	1994	{
cparata	3:4274d9103f1d	1995	lsm6dso_ctrl8_xl_t reg;
cparata	3:4274d9103f1d	1996	int32_t ret;
cparata	3:4274d9103f1d	1997
cparata	3:4274d9103f1d	1998	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	1999	switch ((reg.hp_ref_mode_xl << 5) \| (reg.hp_slope_xl_en << 4) \|
cparata	3:4274d9103f1d	2000	reg.hpcf_xl) {
cparata	3:4274d9103f1d	2001	case LSM6DSO_HP_PATH_DISABLE_ON_OUT:
cparata	3:4274d9103f1d	2002	*val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
cparata	3:4274d9103f1d	2003	break;
cparata	3:4274d9103f1d	2004	case LSM6DSO_SLOPE_ODR_DIV_4:
cparata	3:4274d9103f1d	2005	*val = LSM6DSO_SLOPE_ODR_DIV_4;
cparata	3:4274d9103f1d	2006	break;
cparata	3:4274d9103f1d	2007	case LSM6DSO_HP_ODR_DIV_10:
cparata	3:4274d9103f1d	2008	*val = LSM6DSO_HP_ODR_DIV_10;
cparata	3:4274d9103f1d	2009	break;
cparata	3:4274d9103f1d	2010	case LSM6DSO_HP_ODR_DIV_20:
cparata	3:4274d9103f1d	2011	*val = LSM6DSO_HP_ODR_DIV_20;
cparata	3:4274d9103f1d	2012	break;
cparata	3:4274d9103f1d	2013	case LSM6DSO_HP_ODR_DIV_45:
cparata	3:4274d9103f1d	2014	*val = LSM6DSO_HP_ODR_DIV_45;
cparata	3:4274d9103f1d	2015	break;
cparata	3:4274d9103f1d	2016	case LSM6DSO_HP_ODR_DIV_100:
cparata	3:4274d9103f1d	2017	*val = LSM6DSO_HP_ODR_DIV_100;
cparata	3:4274d9103f1d	2018	break;
cparata	3:4274d9103f1d	2019	case LSM6DSO_HP_ODR_DIV_200:
cparata	3:4274d9103f1d	2020	*val = LSM6DSO_HP_ODR_DIV_200;
cparata	3:4274d9103f1d	2021	break;
cparata	3:4274d9103f1d	2022	case LSM6DSO_HP_ODR_DIV_400:
cparata	3:4274d9103f1d	2023	*val = LSM6DSO_HP_ODR_DIV_400;
cparata	3:4274d9103f1d	2024	break;
cparata	3:4274d9103f1d	2025	case LSM6DSO_HP_ODR_DIV_800:
cparata	3:4274d9103f1d	2026	*val = LSM6DSO_HP_ODR_DIV_800;
cparata	3:4274d9103f1d	2027	break;
cparata	3:4274d9103f1d	2028	case LSM6DSO_HP_REF_MD_ODR_DIV_10:
cparata	3:4274d9103f1d	2029	*val = LSM6DSO_HP_REF_MD_ODR_DIV_10;
cparata	3:4274d9103f1d	2030	break;
cparata	3:4274d9103f1d	2031	case LSM6DSO_HP_REF_MD_ODR_DIV_20:
cparata	3:4274d9103f1d	2032	*val = LSM6DSO_HP_REF_MD_ODR_DIV_20;
cparata	3:4274d9103f1d	2033	break;
cparata	3:4274d9103f1d	2034	case LSM6DSO_HP_REF_MD_ODR_DIV_45:
cparata	3:4274d9103f1d	2035	*val = LSM6DSO_HP_REF_MD_ODR_DIV_45;
cparata	3:4274d9103f1d	2036	break;
cparata	3:4274d9103f1d	2037	case LSM6DSO_HP_REF_MD_ODR_DIV_100:
cparata	3:4274d9103f1d	2038	*val = LSM6DSO_HP_REF_MD_ODR_DIV_100;
cparata	3:4274d9103f1d	2039	break;
cparata	3:4274d9103f1d	2040	case LSM6DSO_HP_REF_MD_ODR_DIV_200:
cparata	3:4274d9103f1d	2041	*val = LSM6DSO_HP_REF_MD_ODR_DIV_200;
cparata	3:4274d9103f1d	2042	break;
cparata	3:4274d9103f1d	2043	case LSM6DSO_HP_REF_MD_ODR_DIV_400:
cparata	3:4274d9103f1d	2044	*val = LSM6DSO_HP_REF_MD_ODR_DIV_400;
cparata	3:4274d9103f1d	2045	break;
cparata	3:4274d9103f1d	2046	case LSM6DSO_HP_REF_MD_ODR_DIV_800:
cparata	3:4274d9103f1d	2047	*val = LSM6DSO_HP_REF_MD_ODR_DIV_800;
cparata	3:4274d9103f1d	2048	break;
cparata	3:4274d9103f1d	2049	case LSM6DSO_LP_ODR_DIV_10:
cparata	3:4274d9103f1d	2050	*val = LSM6DSO_LP_ODR_DIV_10;
cparata	3:4274d9103f1d	2051	break;
cparata	3:4274d9103f1d	2052	case LSM6DSO_LP_ODR_DIV_20:
cparata	3:4274d9103f1d	2053	*val = LSM6DSO_LP_ODR_DIV_20;
cparata	3:4274d9103f1d	2054	break;
cparata	3:4274d9103f1d	2055	case LSM6DSO_LP_ODR_DIV_45:
cparata	3:4274d9103f1d	2056	*val = LSM6DSO_LP_ODR_DIV_45;
cparata	3:4274d9103f1d	2057	break;
cparata	3:4274d9103f1d	2058	case LSM6DSO_LP_ODR_DIV_100:
cparata	3:4274d9103f1d	2059	*val = LSM6DSO_LP_ODR_DIV_100;
cparata	3:4274d9103f1d	2060	break;
cparata	3:4274d9103f1d	2061	case LSM6DSO_LP_ODR_DIV_200:
cparata	3:4274d9103f1d	2062	*val = LSM6DSO_LP_ODR_DIV_200;
cparata	3:4274d9103f1d	2063	break;
cparata	3:4274d9103f1d	2064	case LSM6DSO_LP_ODR_DIV_400:
cparata	3:4274d9103f1d	2065	*val = LSM6DSO_LP_ODR_DIV_400;
cparata	3:4274d9103f1d	2066	break;
cparata	3:4274d9103f1d	2067	case LSM6DSO_LP_ODR_DIV_800:
cparata	3:4274d9103f1d	2068	*val = LSM6DSO_LP_ODR_DIV_800;
cparata	3:4274d9103f1d	2069	break;
cparata	3:4274d9103f1d	2070	default:
cparata	3:4274d9103f1d	2071	*val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
cparata	3:4274d9103f1d	2072	break;
cparata	3:4274d9103f1d	2073	}
cparata	3:4274d9103f1d	2074
cparata	3:4274d9103f1d	2075	return ret;
cparata	0:6d69e896ce38	2076	}
cparata	0:6d69e896ce38	2077
cparata	0:6d69e896ce38	2078	/**
cparata	0:6d69e896ce38	2079	* @brief Enables accelerometer LPF2 and HPF fast-settling mode.
cparata	0:6d69e896ce38	2080	* The filter sets the second samples after writing this bit.
cparata	0:6d69e896ce38	2081	* Active only during device exit from power-down mode.[set]
cparata	0:6d69e896ce38	2082	*
cparata	0:6d69e896ce38	2083	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2084	* @param val change the values of fastsettl_mode_xl in
cparata	0:6d69e896ce38	2085	* reg CTRL8_XL
cparata	0:6d69e896ce38	2086	*
cparata	0:6d69e896ce38	2087	*/
cparata	0:6d69e896ce38	2088	int32_t lsm6dso_xl_fast_settling_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	2089	{
cparata	3:4274d9103f1d	2090	lsm6dso_ctrl8_xl_t reg;
cparata	3:4274d9103f1d	2091	int32_t ret;
cparata	3:4274d9103f1d	2092
cparata	3:4274d9103f1d	2093	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2094	if (ret == 0) {
cparata	3:4274d9103f1d	2095	reg.fastsettl_mode_xl = val;
cparata	3:4274d9103f1d	2096	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2097	}
cparata	3:4274d9103f1d	2098	return ret;
cparata	0:6d69e896ce38	2099	}
cparata	0:6d69e896ce38	2100
cparata	0:6d69e896ce38	2101	/**
cparata	0:6d69e896ce38	2102	* @brief Enables accelerometer LPF2 and HPF fast-settling mode.
cparata	0:6d69e896ce38	2103	* The filter sets the second samples after writing this bit.
cparata	0:6d69e896ce38	2104	* Active only during device exit from power-down mode.[get]
cparata	0:6d69e896ce38	2105	*
cparata	0:6d69e896ce38	2106	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2107	* @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
cparata	0:6d69e896ce38	2108	*
cparata	0:6d69e896ce38	2109	*/
cparata	0:6d69e896ce38	2110	int32_t lsm6dso_xl_fast_settling_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2111	{
cparata	3:4274d9103f1d	2112	lsm6dso_ctrl8_xl_t reg;
cparata	3:4274d9103f1d	2113	int32_t ret;
cparata	3:4274d9103f1d	2114
cparata	3:4274d9103f1d	2115	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2116	*val = reg.fastsettl_mode_xl;
cparata	3:4274d9103f1d	2117
cparata	3:4274d9103f1d	2118	return ret;
cparata	0:6d69e896ce38	2119	}
cparata	0:6d69e896ce38	2120
cparata	0:6d69e896ce38	2121	/**
cparata	0:6d69e896ce38	2122	* @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
cparata	0:6d69e896ce38	2123	* functions.[set]
cparata	0:6d69e896ce38	2124	*
cparata	0:6d69e896ce38	2125	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2126	* @param val change the values of slope_fds in reg TAP_CFG0
cparata	0:6d69e896ce38	2127	*
cparata	0:6d69e896ce38	2128	*/
cparata	0:6d69e896ce38	2129	int32_t lsm6dso_xl_hp_path_internal_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2130	lsm6dso_slope_fds_t val)
cparata	0:6d69e896ce38	2131	{
cparata	3:4274d9103f1d	2132	lsm6dso_tap_cfg0_t reg;
cparata	3:4274d9103f1d	2133	int32_t ret;
cparata	3:4274d9103f1d	2134
cparata	3:4274d9103f1d	2135	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2136	if (ret == 0) {
cparata	3:4274d9103f1d	2137	reg.slope_fds = (uint8_t)val;
cparata	3:4274d9103f1d	2138	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2139	}
cparata	3:4274d9103f1d	2140	return ret;
cparata	0:6d69e896ce38	2141	}
cparata	0:6d69e896ce38	2142
cparata	0:6d69e896ce38	2143	/**
cparata	0:6d69e896ce38	2144	* @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
cparata	0:6d69e896ce38	2145	* functions.[get]
cparata	0:6d69e896ce38	2146	*
cparata	0:6d69e896ce38	2147	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2148	* @param val Get the values of slope_fds in reg TAP_CFG0
cparata	0:6d69e896ce38	2149	*
cparata	0:6d69e896ce38	2150	*/
cparata	0:6d69e896ce38	2151	int32_t lsm6dso_xl_hp_path_internal_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2152	lsm6dso_slope_fds_t *val)
cparata	0:6d69e896ce38	2153	{
cparata	3:4274d9103f1d	2154	lsm6dso_tap_cfg0_t reg;
cparata	3:4274d9103f1d	2155	int32_t ret;
cparata	3:4274d9103f1d	2156
cparata	3:4274d9103f1d	2157	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2158	switch (reg.slope_fds) {
cparata	3:4274d9103f1d	2159	case LSM6DSO_USE_SLOPE:
cparata	3:4274d9103f1d	2160	*val = LSM6DSO_USE_SLOPE;
cparata	3:4274d9103f1d	2161	break;
cparata	3:4274d9103f1d	2162	case LSM6DSO_USE_HPF:
cparata	3:4274d9103f1d	2163	*val = LSM6DSO_USE_HPF;
cparata	3:4274d9103f1d	2164	break;
cparata	3:4274d9103f1d	2165	default:
cparata	3:4274d9103f1d	2166	*val = LSM6DSO_USE_SLOPE;
cparata	3:4274d9103f1d	2167	break;
cparata	3:4274d9103f1d	2168	}
cparata	3:4274d9103f1d	2169	return ret;
cparata	0:6d69e896ce38	2170	}
cparata	0:6d69e896ce38	2171
cparata	0:6d69e896ce38	2172	/**
cparata	0:6d69e896ce38	2173	* @brief Enables gyroscope digital high-pass filter. The filter is
cparata	0:6d69e896ce38	2174	* enabled only if the gyro is in HP mode.[set]
cparata	0:6d69e896ce38	2175	*
cparata	0:6d69e896ce38	2176	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2177	* @param val Get the values of hp_en_g and hp_en_g
cparata	0:6d69e896ce38	2178	* in reg CTRL7_G
cparata	0:6d69e896ce38	2179	*
cparata	0:6d69e896ce38	2180	*/
cparata	0:6d69e896ce38	2181	int32_t lsm6dso_gy_hp_path_internal_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2182	lsm6dso_hpm_g_t val)
cparata	0:6d69e896ce38	2183	{
cparata	3:4274d9103f1d	2184	lsm6dso_ctrl7_g_t reg;
cparata	3:4274d9103f1d	2185	int32_t ret;
cparata	3:4274d9103f1d	2186
cparata	3:4274d9103f1d	2187	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2188	if (ret == 0) {
cparata	3:4274d9103f1d	2189	reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
cparata	3:4274d9103f1d	2190	reg.hpm_g = (uint8_t)val & 0x03U;
cparata	3:4274d9103f1d	2191	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2192	}
cparata	3:4274d9103f1d	2193	return ret;
cparata	0:6d69e896ce38	2194	}
cparata	0:6d69e896ce38	2195
cparata	0:6d69e896ce38	2196	/**
cparata	0:6d69e896ce38	2197	* @brief Enables gyroscope digital high-pass filter. The filter is
cparata	0:6d69e896ce38	2198	* enabled only if the gyro is in HP mode.[get]
cparata	0:6d69e896ce38	2199	*
cparata	0:6d69e896ce38	2200	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2201	* @param val Get the values of hp_en_g and hp_en_g
cparata	0:6d69e896ce38	2202	* in reg CTRL7_G
cparata	0:6d69e896ce38	2203	*
cparata	0:6d69e896ce38	2204	*/
cparata	0:6d69e896ce38	2205	int32_t lsm6dso_gy_hp_path_internal_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2206	lsm6dso_hpm_g_t *val)
cparata	0:6d69e896ce38	2207	{
cparata	3:4274d9103f1d	2208	lsm6dso_ctrl7_g_t reg;
cparata	3:4274d9103f1d	2209	int32_t ret;
cparata	3:4274d9103f1d	2210
cparata	3:4274d9103f1d	2211	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2212	switch ((reg.hp_en_g << 7) + reg.hpm_g) {
cparata	3:4274d9103f1d	2213	case LSM6DSO_HP_FILTER_NONE:
cparata	3:4274d9103f1d	2214	*val = LSM6DSO_HP_FILTER_NONE;
cparata	3:4274d9103f1d	2215	break;
cparata	3:4274d9103f1d	2216	case LSM6DSO_HP_FILTER_16mHz:
cparata	3:4274d9103f1d	2217	*val = LSM6DSO_HP_FILTER_16mHz;
cparata	3:4274d9103f1d	2218	break;
cparata	3:4274d9103f1d	2219	case LSM6DSO_HP_FILTER_65mHz:
cparata	3:4274d9103f1d	2220	*val = LSM6DSO_HP_FILTER_65mHz;
cparata	3:4274d9103f1d	2221	break;
cparata	3:4274d9103f1d	2222	case LSM6DSO_HP_FILTER_260mHz:
cparata	3:4274d9103f1d	2223	*val = LSM6DSO_HP_FILTER_260mHz;
cparata	3:4274d9103f1d	2224	break;
cparata	3:4274d9103f1d	2225	case LSM6DSO_HP_FILTER_1Hz04:
cparata	3:4274d9103f1d	2226	*val = LSM6DSO_HP_FILTER_1Hz04;
cparata	3:4274d9103f1d	2227	break;
cparata	3:4274d9103f1d	2228	default:
cparata	3:4274d9103f1d	2229	*val = LSM6DSO_HP_FILTER_NONE;
cparata	3:4274d9103f1d	2230	break;
cparata	3:4274d9103f1d	2231	}
cparata	3:4274d9103f1d	2232	return ret;
cparata	0:6d69e896ce38	2233	}
cparata	0:6d69e896ce38	2234
cparata	0:6d69e896ce38	2235	/**
cparata	0:6d69e896ce38	2236	* @}
cparata	0:6d69e896ce38	2237	*
cparata	0:6d69e896ce38	2238	*/
cparata	0:6d69e896ce38	2239
cparata	0:6d69e896ce38	2240	/**
cparata	0:6d69e896ce38	2241	* @defgroup LSM6DSO_ Auxiliary_interface
cparata	0:6d69e896ce38	2242	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	2243	* auxiliary interface.
cparata	0:6d69e896ce38	2244	* @{
cparata	0:6d69e896ce38	2245	*
cparata	0:6d69e896ce38	2246	*/
cparata	0:6d69e896ce38	2247
cparata	0:6d69e896ce38	2248	/**
cparata	0:6d69e896ce38	2249	* @brief aOn auxiliary interface connect/disconnect SDO and OCS
cparata	0:6d69e896ce38	2250	* internal pull-up.[set]
cparata	0:6d69e896ce38	2251	*
cparata	0:6d69e896ce38	2252	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2253	* @param val change the values of ois_pu_dis in
cparata	0:6d69e896ce38	2254	* reg PIN_CTRL
cparata	0:6d69e896ce38	2255	*
cparata	0:6d69e896ce38	2256	*/
cparata	0:6d69e896ce38	2257	int32_t lsm6dso_aux_sdo_ocs_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2258	lsm6dso_ois_pu_dis_t val)
cparata	0:6d69e896ce38	2259	{
cparata	3:4274d9103f1d	2260	lsm6dso_pin_ctrl_t reg;
cparata	3:4274d9103f1d	2261	int32_t ret;
cparata	3:4274d9103f1d	2262
cparata	3:4274d9103f1d	2263	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2264	if (ret == 0) {
cparata	3:4274d9103f1d	2265	reg.ois_pu_dis = (uint8_t)val;
cparata	3:4274d9103f1d	2266	ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2267	}
cparata	3:4274d9103f1d	2268	return ret;
cparata	0:6d69e896ce38	2269	}
cparata	0:6d69e896ce38	2270
cparata	0:6d69e896ce38	2271	/**
cparata	0:6d69e896ce38	2272	* @brief On auxiliary interface connect/disconnect SDO and OCS
cparata	0:6d69e896ce38	2273	* internal pull-up.[get]
cparata	0:6d69e896ce38	2274	*
cparata	0:6d69e896ce38	2275	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2276	* @param val Get the values of ois_pu_dis in reg PIN_CTRL
cparata	0:6d69e896ce38	2277	*
cparata	0:6d69e896ce38	2278	*/
cparata	0:6d69e896ce38	2279	int32_t lsm6dso_aux_sdo_ocs_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2280	lsm6dso_ois_pu_dis_t *val)
cparata	0:6d69e896ce38	2281	{
cparata	3:4274d9103f1d	2282	lsm6dso_pin_ctrl_t reg;
cparata	3:4274d9103f1d	2283	int32_t ret;
cparata	3:4274d9103f1d	2284
cparata	3:4274d9103f1d	2285	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2286	switch (reg.ois_pu_dis) {
cparata	3:4274d9103f1d	2287	case LSM6DSO_AUX_PULL_UP_DISC:
cparata	3:4274d9103f1d	2288	*val = LSM6DSO_AUX_PULL_UP_DISC;
cparata	3:4274d9103f1d	2289	break;
cparata	3:4274d9103f1d	2290	case LSM6DSO_AUX_PULL_UP_CONNECT:
cparata	3:4274d9103f1d	2291	*val = LSM6DSO_AUX_PULL_UP_CONNECT;
cparata	3:4274d9103f1d	2292	break;
cparata	3:4274d9103f1d	2293	default:
cparata	3:4274d9103f1d	2294	*val = LSM6DSO_AUX_PULL_UP_DISC;
cparata	3:4274d9103f1d	2295	break;
cparata	3:4274d9103f1d	2296	}
cparata	3:4274d9103f1d	2297	return ret;
cparata	0:6d69e896ce38	2298	}
cparata	0:6d69e896ce38	2299
cparata	0:6d69e896ce38	2300	/**
cparata	0:6d69e896ce38	2301	* @brief OIS chain on aux interface power on mode.[set]
cparata	0:6d69e896ce38	2302	*
cparata	0:6d69e896ce38	2303	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2304	* @param val change the values of ois_on in reg CTRL7_G
cparata	0:6d69e896ce38	2305	*
cparata	0:6d69e896ce38	2306	*/
cparata	0:6d69e896ce38	2307	int32_t lsm6dso_aux_pw_on_ctrl_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_on_t val)
cparata	0:6d69e896ce38	2308	{
cparata	3:4274d9103f1d	2309	lsm6dso_ctrl7_g_t reg;
cparata	3:4274d9103f1d	2310	int32_t ret;
cparata	3:4274d9103f1d	2311
cparata	3:4274d9103f1d	2312	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2313	if (ret == 0) {
cparata	3:4274d9103f1d	2314	reg.ois_on_en = (uint8_t)val & 0x01U;
cparata	3:4274d9103f1d	2315	reg.ois_on = (uint8_t)val & 0x01U;
cparata	3:4274d9103f1d	2316	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2317	}
cparata	3:4274d9103f1d	2318	return ret;
cparata	0:6d69e896ce38	2319	}
cparata	0:6d69e896ce38	2320
cparata	0:6d69e896ce38	2321	/**
cparata	0:6d69e896ce38	2322	* @brief aux_pw_on_ctrl: [get] OIS chain on aux interface power on mode
cparata	0:6d69e896ce38	2323	*
cparata	0:6d69e896ce38	2324	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2325	* @param val Get the values of ois_on in reg CTRL7_G
cparata	0:6d69e896ce38	2326	*
cparata	0:6d69e896ce38	2327	*/
cparata	0:6d69e896ce38	2328	int32_t lsm6dso_aux_pw_on_ctrl_get(lsm6dso_ctx_t ctx, lsm6dso_ois_on_t val)
cparata	0:6d69e896ce38	2329	{
cparata	3:4274d9103f1d	2330	lsm6dso_ctrl7_g_t reg;
cparata	3:4274d9103f1d	2331	int32_t ret;
cparata	3:4274d9103f1d	2332
cparata	3:4274d9103f1d	2333	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2334	switch (reg.ois_on) {
cparata	3:4274d9103f1d	2335	case LSM6DSO_AUX_ON:
cparata	3:4274d9103f1d	2336	*val = LSM6DSO_AUX_ON;
cparata	3:4274d9103f1d	2337	break;
cparata	3:4274d9103f1d	2338	case LSM6DSO_AUX_ON_BY_AUX_INTERFACE:
cparata	3:4274d9103f1d	2339	*val = LSM6DSO_AUX_ON_BY_AUX_INTERFACE;
cparata	3:4274d9103f1d	2340	break;
cparata	3:4274d9103f1d	2341	default:
cparata	3:4274d9103f1d	2342	*val = LSM6DSO_AUX_ON;
cparata	3:4274d9103f1d	2343	break;
cparata	3:4274d9103f1d	2344	}
cparata	3:4274d9103f1d	2345
cparata	3:4274d9103f1d	2346	return ret;
cparata	0:6d69e896ce38	2347	}
cparata	0:6d69e896ce38	2348
cparata	0:6d69e896ce38	2349	/**
cparata	0:6d69e896ce38	2350	* @brief Accelerometer full-scale management between UI chain and
cparata	0:6d69e896ce38	2351	* OIS chain. When XL UI is on, the full scale is the same
cparata	0:6d69e896ce38	2352	* between UI/OIS and is chosen by the UI CTRL registers;
cparata	0:6d69e896ce38	2353	* when XL UI is in PD, the OIS can choose the FS.
cparata	0:6d69e896ce38	2354	* Full scales are independent between the UI/OIS chain
cparata	0:6d69e896ce38	2355	* but both bound to 8 g.[set]
cparata	0:6d69e896ce38	2356	*
cparata	0:6d69e896ce38	2357	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2358	* @param val change the values of xl_fs_mode in
cparata	0:6d69e896ce38	2359	* reg CTRL8_XL
cparata	0:6d69e896ce38	2360	*
cparata	0:6d69e896ce38	2361	*/
cparata	0:6d69e896ce38	2362	int32_t lsm6dso_aux_xl_fs_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2363	lsm6dso_xl_fs_mode_t val)
cparata	0:6d69e896ce38	2364	{
cparata	3:4274d9103f1d	2365	lsm6dso_ctrl8_xl_t reg;
cparata	3:4274d9103f1d	2366	int32_t ret;
cparata	3:4274d9103f1d	2367
cparata	3:4274d9103f1d	2368	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2369	if (ret == 0) {
cparata	3:4274d9103f1d	2370	reg.xl_fs_mode = (uint8_t)val;
cparata	3:4274d9103f1d	2371	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2372	}
cparata	3:4274d9103f1d	2373	return ret;
cparata	0:6d69e896ce38	2374	}
cparata	0:6d69e896ce38	2375
cparata	0:6d69e896ce38	2376	/**
cparata	0:6d69e896ce38	2377	* @brief Accelerometer full-scale management between UI chain and
cparata	0:6d69e896ce38	2378	* OIS chain. When XL UI is on, the full scale is the same
cparata	0:6d69e896ce38	2379	* between UI/OIS and is chosen by the UI CTRL registers;
cparata	0:6d69e896ce38	2380	* when XL UI is in PD, the OIS can choose the FS.
cparata	0:6d69e896ce38	2381	* Full scales are independent between the UI/OIS chain
cparata	0:6d69e896ce38	2382	* but both bound to 8 g.[get]
cparata	0:6d69e896ce38	2383	*
cparata	0:6d69e896ce38	2384	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2385	* @param val Get the values of xl_fs_mode in reg CTRL8_XL
cparata	0:6d69e896ce38	2386	*
cparata	0:6d69e896ce38	2387	*/
cparata	0:6d69e896ce38	2388	int32_t lsm6dso_aux_xl_fs_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2389	lsm6dso_xl_fs_mode_t *val)
cparata	0:6d69e896ce38	2390	{
cparata	3:4274d9103f1d	2391	lsm6dso_ctrl8_xl_t reg;
cparata	3:4274d9103f1d	2392	int32_t ret;
cparata	3:4274d9103f1d	2393
cparata	3:4274d9103f1d	2394	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2395	switch (reg.xl_fs_mode) {
cparata	3:4274d9103f1d	2396	case LSM6DSO_USE_SAME_XL_FS:
cparata	3:4274d9103f1d	2397	*val = LSM6DSO_USE_SAME_XL_FS;
cparata	3:4274d9103f1d	2398	break;
cparata	3:4274d9103f1d	2399	case LSM6DSO_USE_DIFFERENT_XL_FS:
cparata	3:4274d9103f1d	2400	*val = LSM6DSO_USE_DIFFERENT_XL_FS;
cparata	3:4274d9103f1d	2401	break;
cparata	3:4274d9103f1d	2402	default:
cparata	3:4274d9103f1d	2403	*val = LSM6DSO_USE_SAME_XL_FS;
cparata	3:4274d9103f1d	2404	break;
cparata	3:4274d9103f1d	2405	}
cparata	3:4274d9103f1d	2406
cparata	3:4274d9103f1d	2407	return ret;
cparata	0:6d69e896ce38	2408	}
cparata	0:6d69e896ce38	2409
cparata	0:6d69e896ce38	2410	/**
cparata	0:6d69e896ce38	2411	* @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
cparata	0:6d69e896ce38	2412	*
cparata	0:6d69e896ce38	2413	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2414	* @param lsm6dso_status_spiaux_t: registers STATUS_SPIAUX
cparata	0:6d69e896ce38	2415	*
cparata	0:6d69e896ce38	2416	*/
cparata	0:6d69e896ce38	2417	int32_t lsm6dso_aux_status_reg_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2418	lsm6dso_status_spiaux_t *val)
cparata	0:6d69e896ce38	2419	{
cparata	3:4274d9103f1d	2420	int32_t ret;
cparata	3:4274d9103f1d	2421	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *) val, 1);
cparata	3:4274d9103f1d	2422	return ret;
cparata	0:6d69e896ce38	2423	}
cparata	0:6d69e896ce38	2424
cparata	0:6d69e896ce38	2425	/**
cparata	0:6d69e896ce38	2426	* @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available
cparata	0:6d69e896ce38	2427	*
cparata	0:6d69e896ce38	2428	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2429	* @param val change the values of xlda in reg STATUS_SPIAUX
cparata	0:6d69e896ce38	2430	*
cparata	0:6d69e896ce38	2431	*/
cparata	0:6d69e896ce38	2432	int32_t lsm6dso_aux_xl_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2433	{
cparata	3:4274d9103f1d	2434	lsm6dso_status_spiaux_t reg;
cparata	3:4274d9103f1d	2435	int32_t ret;
cparata	3:4274d9103f1d	2436
cparata	3:4274d9103f1d	2437	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2438	*val = reg.xlda;
cparata	3:4274d9103f1d	2439
cparata	3:4274d9103f1d	2440	return ret;
cparata	0:6d69e896ce38	2441	}
cparata	0:6d69e896ce38	2442
cparata	0:6d69e896ce38	2443	/**
cparata	0:6d69e896ce38	2444	* @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available.
cparata	0:6d69e896ce38	2445	*
cparata	0:6d69e896ce38	2446	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2447	* @param val change the values of gda in reg STATUS_SPIAUX
cparata	0:6d69e896ce38	2448	*
cparata	0:6d69e896ce38	2449	*/
cparata	0:6d69e896ce38	2450	int32_t lsm6dso_aux_gy_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2451	{
cparata	3:4274d9103f1d	2452	lsm6dso_status_spiaux_t reg;
cparata	3:4274d9103f1d	2453	int32_t ret;
cparata	3:4274d9103f1d	2454
cparata	3:4274d9103f1d	2455	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2456	*val = reg.gda;
cparata	3:4274d9103f1d	2457
cparata	3:4274d9103f1d	2458	return ret;
cparata	0:6d69e896ce38	2459	}
cparata	0:6d69e896ce38	2460
cparata	0:6d69e896ce38	2461	/**
cparata	0:6d69e896ce38	2462	* @brief High when the gyroscope output is in the settling phase.[get]
cparata	0:6d69e896ce38	2463	*
cparata	0:6d69e896ce38	2464	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2465	* @param val change the values of gyro_settling in reg STATUS_SPIAUX
cparata	0:6d69e896ce38	2466	*
cparata	0:6d69e896ce38	2467	*/
cparata	0:6d69e896ce38	2468	int32_t lsm6dso_aux_gy_flag_settling_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2469	{
cparata	3:4274d9103f1d	2470	lsm6dso_status_spiaux_t reg;
cparata	3:4274d9103f1d	2471	int32_t ret;
cparata	3:4274d9103f1d	2472
cparata	3:4274d9103f1d	2473	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2474	*val = reg.gyro_settling;
cparata	3:4274d9103f1d	2475
cparata	3:4274d9103f1d	2476	return ret;
cparata	0:6d69e896ce38	2477	}
cparata	0:6d69e896ce38	2478
cparata	0:6d69e896ce38	2479	/**
cparata	0:6d69e896ce38	2480	* @brief Selects accelerometer self-test. Effective only if XL OIS
cparata	0:6d69e896ce38	2481	* chain is enabled.[set]
cparata	0:6d69e896ce38	2482	*
cparata	0:6d69e896ce38	2483	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2484	* @param val change the values of st_xl_ois in reg INT_OIS
cparata	0:6d69e896ce38	2485	*
cparata	0:6d69e896ce38	2486	*/
cparata	0:6d69e896ce38	2487	int32_t lsm6dso_aux_xl_self_test_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2488	lsm6dso_st_xl_ois_t val)
cparata	0:6d69e896ce38	2489	{
cparata	3:4274d9103f1d	2490	lsm6dso_int_ois_t reg;
cparata	3:4274d9103f1d	2491	int32_t ret;
cparata	3:4274d9103f1d	2492
cparata	3:4274d9103f1d	2493	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2494	if (ret == 0) {
cparata	3:4274d9103f1d	2495	reg.st_xl_ois = (uint8_t)val;
cparata	3:4274d9103f1d	2496	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2497	}
cparata	3:4274d9103f1d	2498	return ret;
cparata	0:6d69e896ce38	2499	}
cparata	0:6d69e896ce38	2500
cparata	0:6d69e896ce38	2501	/**
cparata	0:6d69e896ce38	2502	* @brief Selects accelerometer self-test. Effective only if XL OIS
cparata	0:6d69e896ce38	2503	* chain is enabled.[get]
cparata	0:6d69e896ce38	2504	*
cparata	0:6d69e896ce38	2505	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2506	* @param val Get the values of st_xl_ois in reg INT_OIS
cparata	0:6d69e896ce38	2507	*
cparata	0:6d69e896ce38	2508	*/
cparata	0:6d69e896ce38	2509	int32_t lsm6dso_aux_xl_self_test_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2510	lsm6dso_st_xl_ois_t *val)
cparata	0:6d69e896ce38	2511	{
cparata	3:4274d9103f1d	2512	lsm6dso_int_ois_t reg;
cparata	3:4274d9103f1d	2513	int32_t ret;
cparata	3:4274d9103f1d	2514
cparata	3:4274d9103f1d	2515	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2516	switch (reg.st_xl_ois) {
cparata	3:4274d9103f1d	2517	case LSM6DSO_AUX_XL_DISABLE:
cparata	3:4274d9103f1d	2518	*val = LSM6DSO_AUX_XL_DISABLE;
cparata	3:4274d9103f1d	2519	break;
cparata	3:4274d9103f1d	2520	case LSM6DSO_AUX_XL_POS:
cparata	3:4274d9103f1d	2521	*val = LSM6DSO_AUX_XL_POS;
cparata	3:4274d9103f1d	2522	break;
cparata	3:4274d9103f1d	2523	case LSM6DSO_AUX_XL_NEG:
cparata	3:4274d9103f1d	2524	*val = LSM6DSO_AUX_XL_NEG;
cparata	3:4274d9103f1d	2525	break;
cparata	3:4274d9103f1d	2526	default:
cparata	3:4274d9103f1d	2527	*val = LSM6DSO_AUX_XL_DISABLE;
cparata	3:4274d9103f1d	2528	break;
cparata	3:4274d9103f1d	2529	}
cparata	3:4274d9103f1d	2530	return ret;
cparata	0:6d69e896ce38	2531	}
cparata	0:6d69e896ce38	2532
cparata	0:6d69e896ce38	2533	/**
cparata	0:6d69e896ce38	2534	* @brief Indicates polarity of DEN signal on OIS chain.[set]
cparata	0:6d69e896ce38	2535	*
cparata	0:6d69e896ce38	2536	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2537	* @param val change the values of den_lh_ois in
cparata	0:6d69e896ce38	2538	* reg INT_OIS
cparata	0:6d69e896ce38	2539	*
cparata	0:6d69e896ce38	2540	*/
cparata	0:6d69e896ce38	2541	int32_t lsm6dso_aux_den_polarity_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2542	lsm6dso_den_lh_ois_t val)
cparata	0:6d69e896ce38	2543	{
cparata	3:4274d9103f1d	2544	lsm6dso_int_ois_t reg;
cparata	3:4274d9103f1d	2545	int32_t ret;
cparata	3:4274d9103f1d	2546
cparata	3:4274d9103f1d	2547	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2548	if (ret == 0) {
cparata	3:4274d9103f1d	2549	reg.den_lh_ois = (uint8_t)val;
cparata	3:4274d9103f1d	2550	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2551	}
cparata	3:4274d9103f1d	2552	return ret;
cparata	0:6d69e896ce38	2553	}
cparata	0:6d69e896ce38	2554
cparata	0:6d69e896ce38	2555	/**
cparata	0:6d69e896ce38	2556	* @brief Indicates polarity of DEN signal on OIS chain.[get]
cparata	0:6d69e896ce38	2557	*
cparata	0:6d69e896ce38	2558	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2559	* @param val Get the values of den_lh_ois in reg INT_OIS
cparata	0:6d69e896ce38	2560	*
cparata	0:6d69e896ce38	2561	*/
cparata	0:6d69e896ce38	2562	int32_t lsm6dso_aux_den_polarity_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2563	lsm6dso_den_lh_ois_t *val)
cparata	0:6d69e896ce38	2564	{
cparata	3:4274d9103f1d	2565	lsm6dso_int_ois_t reg;
cparata	3:4274d9103f1d	2566	int32_t ret;
cparata	3:4274d9103f1d	2567
cparata	3:4274d9103f1d	2568	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2569	switch (reg.den_lh_ois) {
cparata	3:4274d9103f1d	2570	case LSM6DSO_AUX_DEN_ACTIVE_LOW:
cparata	3:4274d9103f1d	2571	*val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
cparata	3:4274d9103f1d	2572	break;
cparata	3:4274d9103f1d	2573	case LSM6DSO_AUX_DEN_ACTIVE_HIGH:
cparata	3:4274d9103f1d	2574	*val = LSM6DSO_AUX_DEN_ACTIVE_HIGH;
cparata	3:4274d9103f1d	2575	break;
cparata	3:4274d9103f1d	2576	default:
cparata	3:4274d9103f1d	2577	*val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
cparata	3:4274d9103f1d	2578	break;
cparata	3:4274d9103f1d	2579	}
cparata	3:4274d9103f1d	2580	return ret;
cparata	0:6d69e896ce38	2581	}
cparata	0:6d69e896ce38	2582
cparata	0:6d69e896ce38	2583	/**
cparata	0:6d69e896ce38	2584	* @brief Configure DEN mode on the OIS chain.[set]
cparata	0:6d69e896ce38	2585	*
cparata	0:6d69e896ce38	2586	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2587	* @param val change the values of lvl2_ois in reg INT_OIS
cparata	0:6d69e896ce38	2588	*
cparata	0:6d69e896ce38	2589	*/
cparata	0:6d69e896ce38	2590	int32_t lsm6dso_aux_den_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_lvl2_ois_t val)
cparata	0:6d69e896ce38	2591	{
cparata	3:4274d9103f1d	2592	lsm6dso_ctrl1_ois_t ctrl1_ois;
cparata	3:4274d9103f1d	2593	lsm6dso_int_ois_t int_ois;
cparata	3:4274d9103f1d	2594	int32_t ret;
cparata	3:4274d9103f1d	2595
cparata	3:4274d9103f1d	2596	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
cparata	3:4274d9103f1d	2597	if (ret == 0) {
cparata	3:4274d9103f1d	2598	int_ois.lvl2_ois = (uint8_t)val & 0x01U;
cparata	3:4274d9103f1d	2599	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
cparata	3:4274d9103f1d	2600	}
cparata	3:4274d9103f1d	2601	if (ret == 0) {
cparata	3:4274d9103f1d	2602	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1);
cparata	3:4274d9103f1d	2603	}
cparata	3:4274d9103f1d	2604	if (ret == 0) {
cparata	3:4274d9103f1d	2605	ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
cparata	3:4274d9103f1d	2606	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1);
cparata	3:4274d9103f1d	2607	}
cparata	3:4274d9103f1d	2608	return ret;
cparata	0:6d69e896ce38	2609	}
cparata	0:6d69e896ce38	2610
cparata	0:6d69e896ce38	2611	/**
cparata	0:6d69e896ce38	2612	* @brief Configure DEN mode on the OIS chain.[get]
cparata	0:6d69e896ce38	2613	*
cparata	0:6d69e896ce38	2614	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2615	* @param val Get the values of lvl2_ois in reg INT_OIS
cparata	0:6d69e896ce38	2616	*
cparata	0:6d69e896ce38	2617	*/
cparata	0:6d69e896ce38	2618	int32_t lsm6dso_aux_den_mode_get(lsm6dso_ctx_t ctx, lsm6dso_lvl2_ois_t val)
cparata	0:6d69e896ce38	2619	{
cparata	3:4274d9103f1d	2620	lsm6dso_ctrl1_ois_t ctrl1_ois;
cparata	3:4274d9103f1d	2621	lsm6dso_int_ois_t int_ois;
cparata	3:4274d9103f1d	2622	int32_t ret;
cparata	3:4274d9103f1d	2623
cparata	3:4274d9103f1d	2624	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
cparata	3:4274d9103f1d	2625	if (ret == 0) {
cparata	3:4274d9103f1d	2626	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1);
cparata	3:4274d9103f1d	2627	switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) {
cparata	3:4274d9103f1d	2628	case LSM6DSO_AUX_DEN_DISABLE:
cparata	3:4274d9103f1d	2629	*val = LSM6DSO_AUX_DEN_DISABLE;
cparata	3:4274d9103f1d	2630	break;
cparata	3:4274d9103f1d	2631	case LSM6DSO_AUX_DEN_LEVEL_LATCH:
cparata	3:4274d9103f1d	2632	*val = LSM6DSO_AUX_DEN_LEVEL_LATCH;
cparata	3:4274d9103f1d	2633	break;
cparata	3:4274d9103f1d	2634	case LSM6DSO_AUX_DEN_LEVEL_TRIG:
cparata	3:4274d9103f1d	2635	*val = LSM6DSO_AUX_DEN_LEVEL_TRIG;
cparata	3:4274d9103f1d	2636	break;
cparata	3:4274d9103f1d	2637	default:
cparata	3:4274d9103f1d	2638	*val = LSM6DSO_AUX_DEN_DISABLE;
cparata	3:4274d9103f1d	2639	break;
cparata	3:4274d9103f1d	2640	}
cparata	3:4274d9103f1d	2641	}
cparata	3:4274d9103f1d	2642	return ret;
cparata	0:6d69e896ce38	2643	}
cparata	0:6d69e896ce38	2644
cparata	0:6d69e896ce38	2645	/**
cparata	0:6d69e896ce38	2646	* @brief Enables/Disable OIS chain DRDY on INT2 pin.
cparata	0:6d69e896ce38	2647	* This setting has priority over all other INT2 settings.[set]
cparata	0:6d69e896ce38	2648	*
cparata	0:6d69e896ce38	2649	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2650	* @param val change the values of int2_drdy_ois in reg INT_OIS
cparata	0:6d69e896ce38	2651	*
cparata	0:6d69e896ce38	2652	*/
cparata	0:6d69e896ce38	2653	int32_t lsm6dso_aux_drdy_on_int2_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	2654	{
cparata	3:4274d9103f1d	2655	lsm6dso_int_ois_t reg;
cparata	3:4274d9103f1d	2656	int32_t ret;
cparata	3:4274d9103f1d	2657
cparata	3:4274d9103f1d	2658	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2659	if (ret == 0) {
cparata	3:4274d9103f1d	2660	reg.int2_drdy_ois = val;
cparata	3:4274d9103f1d	2661	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2662	}
cparata	3:4274d9103f1d	2663	return ret;
cparata	0:6d69e896ce38	2664	}
cparata	0:6d69e896ce38	2665
cparata	0:6d69e896ce38	2666	/**
cparata	0:6d69e896ce38	2667	* @brief Enables/Disable OIS chain DRDY on INT2 pin.
cparata	0:6d69e896ce38	2668	* This setting has priority over all other INT2 settings.[get]
cparata	0:6d69e896ce38	2669	*
cparata	0:6d69e896ce38	2670	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2671	* @param val change the values of int2_drdy_ois in reg INT_OIS
cparata	0:6d69e896ce38	2672	*
cparata	0:6d69e896ce38	2673	*/
cparata	0:6d69e896ce38	2674	int32_t lsm6dso_aux_drdy_on_int2_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2675	{
cparata	3:4274d9103f1d	2676	lsm6dso_int_ois_t reg;
cparata	3:4274d9103f1d	2677	int32_t ret;
cparata	3:4274d9103f1d	2678
cparata	3:4274d9103f1d	2679	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2680	*val = reg.int2_drdy_ois;
cparata	3:4274d9103f1d	2681
cparata	3:4274d9103f1d	2682	return ret;
cparata	0:6d69e896ce38	2683	}
cparata	0:6d69e896ce38	2684
cparata	0:6d69e896ce38	2685	/**
cparata	0:6d69e896ce38	2686	* @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
cparata	0:6d69e896ce38	2687	* (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
cparata	0:6d69e896ce38	2688	* When the OIS chain is enabled, the OIS outputs are available
cparata	0:6d69e896ce38	2689	* through the SPI2 in registers OUTX_L_G (22h) through
cparata	0:6d69e896ce38	2690	* OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
cparata	0:6d69e896ce38	2691	* LPF1 is dedicated to this chain.[set]
cparata	0:6d69e896ce38	2692	*
cparata	0:6d69e896ce38	2693	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2694	* @param val change the values of ois_en_spi2 in
cparata	0:6d69e896ce38	2695	* reg CTRL1_OIS
cparata	0:6d69e896ce38	2696	*
cparata	0:6d69e896ce38	2697	*/
cparata	0:6d69e896ce38	2698	int32_t lsm6dso_aux_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_en_spi2_t val)
cparata	0:6d69e896ce38	2699	{
cparata	3:4274d9103f1d	2700	lsm6dso_ctrl1_ois_t reg;
cparata	3:4274d9103f1d	2701	int32_t ret;
cparata	3:4274d9103f1d	2702
cparata	3:4274d9103f1d	2703	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2704	if (ret == 0) {
cparata	3:4274d9103f1d	2705	reg.ois_en_spi2 = (uint8_t)val & 0x01U;
cparata	3:4274d9103f1d	2706	reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
cparata	3:4274d9103f1d	2707	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2708	}
cparata	3:4274d9103f1d	2709	return ret;
cparata	0:6d69e896ce38	2710	}
cparata	0:6d69e896ce38	2711
cparata	0:6d69e896ce38	2712	/**
cparata	0:6d69e896ce38	2713	* @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
cparata	0:6d69e896ce38	2714	* (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
cparata	0:6d69e896ce38	2715	* When the OIS chain is enabled, the OIS outputs are available
cparata	0:6d69e896ce38	2716	* through the SPI2 in registers OUTX_L_G (22h) through
cparata	0:6d69e896ce38	2717	* OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
cparata	0:6d69e896ce38	2718	* LPF1 is dedicated to this chain.[get]
cparata	0:6d69e896ce38	2719	*
cparata	0:6d69e896ce38	2720	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2721	* @param val Get the values of ois_en_spi2 in
cparata	0:6d69e896ce38	2722	* reg CTRL1_OIS
cparata	0:6d69e896ce38	2723	*
cparata	0:6d69e896ce38	2724	*/
cparata	0:6d69e896ce38	2725	int32_t lsm6dso_aux_mode_get(lsm6dso_ctx_t ctx, lsm6dso_ois_en_spi2_t val)
cparata	0:6d69e896ce38	2726	{
cparata	3:4274d9103f1d	2727	lsm6dso_ctrl1_ois_t reg;
cparata	3:4274d9103f1d	2728	int32_t ret;
cparata	3:4274d9103f1d	2729
cparata	3:4274d9103f1d	2730	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2731	switch ((reg.mode4_en << 1) \| reg.ois_en_spi2) {
cparata	3:4274d9103f1d	2732	case LSM6DSO_AUX_DISABLE:
cparata	3:4274d9103f1d	2733	*val = LSM6DSO_AUX_DISABLE;
cparata	3:4274d9103f1d	2734	break;
cparata	3:4274d9103f1d	2735	case LSM6DSO_MODE_3_GY:
cparata	3:4274d9103f1d	2736	*val = LSM6DSO_MODE_3_GY;
cparata	3:4274d9103f1d	2737	break;
cparata	3:4274d9103f1d	2738	case LSM6DSO_MODE_4_GY_XL:
cparata	3:4274d9103f1d	2739	*val = LSM6DSO_MODE_4_GY_XL;
cparata	3:4274d9103f1d	2740	break;
cparata	3:4274d9103f1d	2741	default:
cparata	3:4274d9103f1d	2742	*val = LSM6DSO_AUX_DISABLE;
cparata	3:4274d9103f1d	2743	break;
cparata	3:4274d9103f1d	2744	}
cparata	3:4274d9103f1d	2745	return ret;
cparata	0:6d69e896ce38	2746	}
cparata	0:6d69e896ce38	2747
cparata	0:6d69e896ce38	2748	/**
cparata	0:6d69e896ce38	2749	* @brief Selects gyroscope OIS chain full-scale.[set]
cparata	0:6d69e896ce38	2750	*
cparata	0:6d69e896ce38	2751	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2752	* @param val change the values of fs_g_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2753	*
cparata	0:6d69e896ce38	2754	*/
cparata	0:6d69e896ce38	2755	int32_t lsm6dso_aux_gy_full_scale_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2756	lsm6dso_fs_g_ois_t val)
cparata	0:6d69e896ce38	2757	{
cparata	3:4274d9103f1d	2758	lsm6dso_ctrl1_ois_t reg;
cparata	3:4274d9103f1d	2759	int32_t ret;
cparata	3:4274d9103f1d	2760
cparata	3:4274d9103f1d	2761	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2762	if (ret == 0) {
cparata	3:4274d9103f1d	2763	reg.fs_g_ois = (uint8_t)val;
cparata	3:4274d9103f1d	2764	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2765	}
cparata	3:4274d9103f1d	2766	return ret;
cparata	0:6d69e896ce38	2767	}
cparata	0:6d69e896ce38	2768
cparata	0:6d69e896ce38	2769	/**
cparata	0:6d69e896ce38	2770	* @brief Selects gyroscope OIS chain full-scale.[get]
cparata	0:6d69e896ce38	2771	*
cparata	0:6d69e896ce38	2772	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2773	* @param val Get the values of fs_g_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2774	*
cparata	0:6d69e896ce38	2775	*/
cparata	0:6d69e896ce38	2776	int32_t lsm6dso_aux_gy_full_scale_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2777	lsm6dso_fs_g_ois_t *val)
cparata	0:6d69e896ce38	2778	{
cparata	3:4274d9103f1d	2779	lsm6dso_ctrl1_ois_t reg;
cparata	3:4274d9103f1d	2780	int32_t ret;
cparata	3:4274d9103f1d	2781
cparata	3:4274d9103f1d	2782	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2783	switch (reg.fs_g_ois) {
cparata	3:4274d9103f1d	2784	case LSM6DSO_250dps_AUX:
cparata	3:4274d9103f1d	2785	*val = LSM6DSO_250dps_AUX;
cparata	3:4274d9103f1d	2786	break;
cparata	3:4274d9103f1d	2787	case LSM6DSO_125dps_AUX:
cparata	3:4274d9103f1d	2788	*val = LSM6DSO_125dps_AUX;
cparata	3:4274d9103f1d	2789	break;
cparata	3:4274d9103f1d	2790	case LSM6DSO_500dps_AUX:
cparata	3:4274d9103f1d	2791	*val = LSM6DSO_500dps_AUX;
cparata	3:4274d9103f1d	2792	break;
cparata	3:4274d9103f1d	2793	case LSM6DSO_1000dps_AUX:
cparata	3:4274d9103f1d	2794	*val = LSM6DSO_1000dps_AUX;
cparata	3:4274d9103f1d	2795	break;
cparata	3:4274d9103f1d	2796	case LSM6DSO_2000dps_AUX:
cparata	3:4274d9103f1d	2797	*val = LSM6DSO_2000dps_AUX;
cparata	3:4274d9103f1d	2798	break;
cparata	3:4274d9103f1d	2799	default:
cparata	3:4274d9103f1d	2800	*val = LSM6DSO_250dps_AUX;
cparata	3:4274d9103f1d	2801	break;
cparata	3:4274d9103f1d	2802	}
cparata	3:4274d9103f1d	2803	return ret;
cparata	0:6d69e896ce38	2804	}
cparata	0:6d69e896ce38	2805
cparata	0:6d69e896ce38	2806	/**
cparata	0:6d69e896ce38	2807	* @brief SPI2 3- or 4-wire interface.[set]
cparata	0:6d69e896ce38	2808	*
cparata	0:6d69e896ce38	2809	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2810	* @param val change the values of sim_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2811	*
cparata	0:6d69e896ce38	2812	*/
cparata	0:6d69e896ce38	2813	int32_t lsm6dso_aux_spi_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sim_ois_t val)
cparata	0:6d69e896ce38	2814	{
cparata	3:4274d9103f1d	2815	lsm6dso_ctrl1_ois_t reg;
cparata	3:4274d9103f1d	2816	int32_t ret;
cparata	3:4274d9103f1d	2817
cparata	3:4274d9103f1d	2818	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2819	if (ret == 0) {
cparata	3:4274d9103f1d	2820	reg.sim_ois = (uint8_t)val;
cparata	3:4274d9103f1d	2821	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2822	}
cparata	3:4274d9103f1d	2823	return ret;
cparata	0:6d69e896ce38	2824	}
cparata	0:6d69e896ce38	2825
cparata	0:6d69e896ce38	2826	/**
cparata	0:6d69e896ce38	2827	* @brief SPI2 3- or 4-wire interface.[get]
cparata	0:6d69e896ce38	2828	*
cparata	0:6d69e896ce38	2829	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2830	* @param val Get the values of sim_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2831	*
cparata	0:6d69e896ce38	2832	*/
cparata	0:6d69e896ce38	2833	int32_t lsm6dso_aux_spi_mode_get(lsm6dso_ctx_t ctx, lsm6dso_sim_ois_t val)
cparata	0:6d69e896ce38	2834	{
cparata	3:4274d9103f1d	2835	lsm6dso_ctrl1_ois_t reg;
cparata	3:4274d9103f1d	2836	int32_t ret;
cparata	3:4274d9103f1d	2837
cparata	3:4274d9103f1d	2838	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2839	switch (reg.sim_ois) {
cparata	3:4274d9103f1d	2840	case LSM6DSO_AUX_SPI_4_WIRE:
cparata	3:4274d9103f1d	2841	*val = LSM6DSO_AUX_SPI_4_WIRE;
cparata	3:4274d9103f1d	2842	break;
cparata	3:4274d9103f1d	2843	case LSM6DSO_AUX_SPI_3_WIRE:
cparata	3:4274d9103f1d	2844	*val = LSM6DSO_AUX_SPI_3_WIRE;
cparata	3:4274d9103f1d	2845	break;
cparata	3:4274d9103f1d	2846	default:
cparata	3:4274d9103f1d	2847	*val = LSM6DSO_AUX_SPI_4_WIRE;
cparata	3:4274d9103f1d	2848	break;
cparata	3:4274d9103f1d	2849	}
cparata	3:4274d9103f1d	2850	return ret;
cparata	0:6d69e896ce38	2851	}
cparata	0:6d69e896ce38	2852
cparata	0:6d69e896ce38	2853	/**
cparata	0:6d69e896ce38	2854	* @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
cparata	0:6d69e896ce38	2855	*
cparata	0:6d69e896ce38	2856	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2857	* @param val change the values of ftype_ois in
cparata	0:6d69e896ce38	2858	* reg CTRL2_OIS
cparata	0:6d69e896ce38	2859	*
cparata	0:6d69e896ce38	2860	*/
cparata	0:6d69e896ce38	2861	int32_t lsm6dso_aux_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2862	lsm6dso_ftype_ois_t val)
cparata	0:6d69e896ce38	2863	{
cparata	3:4274d9103f1d	2864	lsm6dso_ctrl2_ois_t reg;
cparata	3:4274d9103f1d	2865	int32_t ret;
cparata	3:4274d9103f1d	2866
cparata	3:4274d9103f1d	2867	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2868	if (ret == 0) {
cparata	3:4274d9103f1d	2869	reg.ftype_ois = (uint8_t)val;
cparata	3:4274d9103f1d	2870	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2871	}
cparata	3:4274d9103f1d	2872	return ret;
cparata	0:6d69e896ce38	2873	}
cparata	0:6d69e896ce38	2874
cparata	0:6d69e896ce38	2875	/**
cparata	0:6d69e896ce38	2876	* @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
cparata	0:6d69e896ce38	2877	*
cparata	0:6d69e896ce38	2878	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2879	* @param val Get the values of ftype_ois in reg CTRL2_OIS
cparata	0:6d69e896ce38	2880	*
cparata	0:6d69e896ce38	2881	*/
cparata	0:6d69e896ce38	2882	int32_t lsm6dso_aux_gy_lp1_bandwidth_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2883	lsm6dso_ftype_ois_t *val)
cparata	0:6d69e896ce38	2884	{
cparata	3:4274d9103f1d	2885	lsm6dso_ctrl2_ois_t reg;
cparata	3:4274d9103f1d	2886	int32_t ret;
cparata	3:4274d9103f1d	2887
cparata	3:4274d9103f1d	2888	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2889	switch (reg.ftype_ois) {
cparata	3:4274d9103f1d	2890	case LSM6DSO_351Hz39:
cparata	3:4274d9103f1d	2891	*val = LSM6DSO_351Hz39;
cparata	3:4274d9103f1d	2892	break;
cparata	3:4274d9103f1d	2893	case LSM6DSO_236Hz63:
cparata	3:4274d9103f1d	2894	*val = LSM6DSO_236Hz63;
cparata	3:4274d9103f1d	2895	break;
cparata	3:4274d9103f1d	2896	case LSM6DSO_172Hz70:
cparata	3:4274d9103f1d	2897	*val = LSM6DSO_172Hz70;
cparata	3:4274d9103f1d	2898	break;
cparata	3:4274d9103f1d	2899	case LSM6DSO_937Hz91:
cparata	3:4274d9103f1d	2900	*val = LSM6DSO_937Hz91;
cparata	3:4274d9103f1d	2901	break;
cparata	3:4274d9103f1d	2902	default:
cparata	3:4274d9103f1d	2903	*val = LSM6DSO_351Hz39;
cparata	3:4274d9103f1d	2904	break;
cparata	3:4274d9103f1d	2905	}
cparata	3:4274d9103f1d	2906	return ret;
cparata	0:6d69e896ce38	2907	}
cparata	0:6d69e896ce38	2908
cparata	0:6d69e896ce38	2909	/**
cparata	0:6d69e896ce38	2910	* @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
cparata	0:6d69e896ce38	2911	*
cparata	0:6d69e896ce38	2912	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2913	* @param val change the values of hpm_ois in reg CTRL2_OIS
cparata	0:6d69e896ce38	2914	*
cparata	0:6d69e896ce38	2915	*/
cparata	0:6d69e896ce38	2916	int32_t lsm6dso_aux_gy_hp_bandwidth_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2917	lsm6dso_hpm_ois_t val)
cparata	0:6d69e896ce38	2918	{
cparata	3:4274d9103f1d	2919	lsm6dso_ctrl2_ois_t reg;
cparata	3:4274d9103f1d	2920	int32_t ret;
cparata	3:4274d9103f1d	2921
cparata	3:4274d9103f1d	2922	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2923	if (ret == 0) {
cparata	3:4274d9103f1d	2924	reg.hpm_ois = (uint8_t)val & 0x03U;
cparata	3:4274d9103f1d	2925	reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
cparata	3:4274d9103f1d	2926	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2927	}
cparata	3:4274d9103f1d	2928	return ret;
cparata	0:6d69e896ce38	2929	}
cparata	0:6d69e896ce38	2930
cparata	0:6d69e896ce38	2931	/**
cparata	0:6d69e896ce38	2932	* @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
cparata	0:6d69e896ce38	2933	*
cparata	0:6d69e896ce38	2934	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2935	* @param val Get the values of hpm_ois in reg CTRL2_OIS
cparata	0:6d69e896ce38	2936	*
cparata	0:6d69e896ce38	2937	*/
cparata	0:6d69e896ce38	2938	int32_t lsm6dso_aux_gy_hp_bandwidth_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2939	lsm6dso_hpm_ois_t *val)
cparata	0:6d69e896ce38	2940	{
cparata	3:4274d9103f1d	2941	lsm6dso_ctrl2_ois_t reg;
cparata	3:4274d9103f1d	2942	int32_t ret;
cparata	3:4274d9103f1d	2943
cparata	3:4274d9103f1d	2944	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2945	switch ((reg.hp_en_ois << 4) \| reg.hpm_ois) {
cparata	3:4274d9103f1d	2946	case LSM6DSO_AUX_HP_DISABLE:
cparata	3:4274d9103f1d	2947	*val = LSM6DSO_AUX_HP_DISABLE;
cparata	3:4274d9103f1d	2948	break;
cparata	3:4274d9103f1d	2949	case LSM6DSO_AUX_HP_Hz016:
cparata	3:4274d9103f1d	2950	*val = LSM6DSO_AUX_HP_Hz016;
cparata	3:4274d9103f1d	2951	break;
cparata	3:4274d9103f1d	2952	case LSM6DSO_AUX_HP_Hz065:
cparata	3:4274d9103f1d	2953	*val = LSM6DSO_AUX_HP_Hz065;
cparata	3:4274d9103f1d	2954	break;
cparata	3:4274d9103f1d	2955	case LSM6DSO_AUX_HP_Hz260:
cparata	3:4274d9103f1d	2956	*val = LSM6DSO_AUX_HP_Hz260;
cparata	3:4274d9103f1d	2957	break;
cparata	3:4274d9103f1d	2958	case LSM6DSO_AUX_HP_1Hz040:
cparata	3:4274d9103f1d	2959	*val = LSM6DSO_AUX_HP_1Hz040;
cparata	3:4274d9103f1d	2960	break;
cparata	3:4274d9103f1d	2961	default:
cparata	3:4274d9103f1d	2962	*val = LSM6DSO_AUX_HP_DISABLE;
cparata	3:4274d9103f1d	2963	break;
cparata	3:4274d9103f1d	2964	}
cparata	3:4274d9103f1d	2965	return ret;
cparata	0:6d69e896ce38	2966	}
cparata	0:6d69e896ce38	2967
cparata	0:6d69e896ce38	2968	/**
cparata	0:6d69e896ce38	2969	* @brief Enable / Disables OIS chain clamp.
cparata	0:6d69e896ce38	2970	* Enable: All OIS chain outputs = 8000h
cparata	0:6d69e896ce38	2971	* during self-test; Disable: OIS chain self-test
cparata	0:6d69e896ce38	2972	* outputs dependent from the aux gyro full
cparata	0:6d69e896ce38	2973	* scale selected.[set]
cparata	0:6d69e896ce38	2974	*
cparata	0:6d69e896ce38	2975	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2976	* @param val change the values of st_ois_clampdis in
cparata	0:6d69e896ce38	2977	* reg CTRL3_OIS
cparata	0:6d69e896ce38	2978	*
cparata	0:6d69e896ce38	2979	*/
cparata	0:6d69e896ce38	2980	int32_t lsm6dso_aux_gy_clamp_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2981	lsm6dso_st_ois_clampdis_t val)
cparata	0:6d69e896ce38	2982	{
cparata	3:4274d9103f1d	2983	lsm6dso_ctrl3_ois_t reg;
cparata	3:4274d9103f1d	2984	int32_t ret;
cparata	3:4274d9103f1d	2985
cparata	3:4274d9103f1d	2986	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2987	if (ret == 0) {
cparata	3:4274d9103f1d	2988	reg.st_ois_clampdis = (uint8_t)val;
cparata	3:4274d9103f1d	2989	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	2990	}
cparata	3:4274d9103f1d	2991	return ret;
cparata	0:6d69e896ce38	2992	}
cparata	0:6d69e896ce38	2993
cparata	0:6d69e896ce38	2994	/**
cparata	0:6d69e896ce38	2995	* @brief Enable / Disables OIS chain clamp.
cparata	0:6d69e896ce38	2996	* Enable: All OIS chain outputs = 8000h
cparata	0:6d69e896ce38	2997	* during self-test; Disable: OIS chain self-test
cparata	0:6d69e896ce38	2998	* outputs dependent from the aux gyro full
cparata	0:6d69e896ce38	2999	* scale selected.[set]
cparata	0:6d69e896ce38	3000	*
cparata	0:6d69e896ce38	3001	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3002	* @param val Get the values of st_ois_clampdis in
cparata	0:6d69e896ce38	3003	* reg CTRL3_OIS
cparata	0:6d69e896ce38	3004	*
cparata	0:6d69e896ce38	3005	*/
cparata	0:6d69e896ce38	3006	int32_t lsm6dso_aux_gy_clamp_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3007	lsm6dso_st_ois_clampdis_t *val)
cparata	0:6d69e896ce38	3008	{
cparata	3:4274d9103f1d	3009	lsm6dso_ctrl3_ois_t reg;
cparata	3:4274d9103f1d	3010	int32_t ret;
cparata	3:4274d9103f1d	3011
cparata	3:4274d9103f1d	3012	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3013	switch (reg.st_ois_clampdis) {
cparata	3:4274d9103f1d	3014	case LSM6DSO_ENABLE_CLAMP:
cparata	3:4274d9103f1d	3015	*val = LSM6DSO_ENABLE_CLAMP;
cparata	3:4274d9103f1d	3016	break;
cparata	3:4274d9103f1d	3017	case LSM6DSO_DISABLE_CLAMP:
cparata	3:4274d9103f1d	3018	*val = LSM6DSO_DISABLE_CLAMP;
cparata	3:4274d9103f1d	3019	break;
cparata	3:4274d9103f1d	3020	default:
cparata	3:4274d9103f1d	3021	*val = LSM6DSO_ENABLE_CLAMP;
cparata	3:4274d9103f1d	3022	break;
cparata	3:4274d9103f1d	3023	}
cparata	3:4274d9103f1d	3024	return ret;
cparata	0:6d69e896ce38	3025	}
cparata	0:6d69e896ce38	3026
cparata	0:6d69e896ce38	3027	/**
cparata	0:6d69e896ce38	3028	* @brief Selects gyroscope OIS chain self-test.[set]
cparata	0:6d69e896ce38	3029	*
cparata	0:6d69e896ce38	3030	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3031	* @param val change the values of st_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3032	*
cparata	0:6d69e896ce38	3033	*/
cparata	0:6d69e896ce38	3034	int32_t lsm6dso_aux_gy_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_ois_t val)
cparata	0:6d69e896ce38	3035	{
cparata	3:4274d9103f1d	3036	lsm6dso_ctrl3_ois_t reg;
cparata	3:4274d9103f1d	3037	int32_t ret;
cparata	3:4274d9103f1d	3038
cparata	3:4274d9103f1d	3039	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3040	if (ret == 0) {
cparata	3:4274d9103f1d	3041	reg.st_ois = (uint8_t)val;
cparata	3:4274d9103f1d	3042	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3043	}
cparata	3:4274d9103f1d	3044	return ret;
cparata	0:6d69e896ce38	3045	}
cparata	0:6d69e896ce38	3046
cparata	0:6d69e896ce38	3047	/**
cparata	0:6d69e896ce38	3048	* @brief Selects gyroscope OIS chain self-test.[get]
cparata	0:6d69e896ce38	3049	*
cparata	0:6d69e896ce38	3050	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3051	* @param val Get the values of st_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3052	*
cparata	0:6d69e896ce38	3053	*/
cparata	0:6d69e896ce38	3054	int32_t lsm6dso_aux_gy_self_test_get(lsm6dso_ctx_t ctx, lsm6dso_st_ois_t val)
cparata	0:6d69e896ce38	3055	{
cparata	3:4274d9103f1d	3056	lsm6dso_ctrl3_ois_t reg;
cparata	3:4274d9103f1d	3057	int32_t ret;
cparata	3:4274d9103f1d	3058
cparata	3:4274d9103f1d	3059	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3060	switch (reg.st_ois) {
cparata	3:4274d9103f1d	3061	case LSM6DSO_AUX_GY_DISABLE:
cparata	3:4274d9103f1d	3062	*val = LSM6DSO_AUX_GY_DISABLE;
cparata	3:4274d9103f1d	3063	break;
cparata	3:4274d9103f1d	3064	case LSM6DSO_AUX_GY_POS:
cparata	3:4274d9103f1d	3065	*val = LSM6DSO_AUX_GY_POS;
cparata	3:4274d9103f1d	3066	break;
cparata	3:4274d9103f1d	3067	case LSM6DSO_AUX_GY_NEG:
cparata	3:4274d9103f1d	3068	*val = LSM6DSO_AUX_GY_NEG;
cparata	3:4274d9103f1d	3069	break;
cparata	3:4274d9103f1d	3070	default:
cparata	3:4274d9103f1d	3071	*val = LSM6DSO_AUX_GY_DISABLE;
cparata	3:4274d9103f1d	3072	break;
cparata	3:4274d9103f1d	3073	}
cparata	3:4274d9103f1d	3074	return ret;
cparata	0:6d69e896ce38	3075	}
cparata	0:6d69e896ce38	3076
cparata	0:6d69e896ce38	3077	/**
cparata	0:6d69e896ce38	3078	* @brief Selects accelerometer OIS channel bandwidth.[set]
cparata	0:6d69e896ce38	3079	*
cparata	0:6d69e896ce38	3080	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3081	* @param val change the values of
cparata	0:6d69e896ce38	3082	* filter_xl_conf_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3083	*
cparata	0:6d69e896ce38	3084	*/
cparata	0:6d69e896ce38	3085	int32_t lsm6dso_aux_xl_bandwidth_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3086	lsm6dso_filter_xl_conf_ois_t val)
cparata	0:6d69e896ce38	3087	{
cparata	3:4274d9103f1d	3088	lsm6dso_ctrl3_ois_t reg;
cparata	3:4274d9103f1d	3089	int32_t ret;
cparata	3:4274d9103f1d	3090
cparata	3:4274d9103f1d	3091	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3092	if (ret == 0) {
cparata	3:4274d9103f1d	3093	reg.filter_xl_conf_ois = (uint8_t)val;
cparata	3:4274d9103f1d	3094	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3095	}
cparata	3:4274d9103f1d	3096	return ret;
cparata	0:6d69e896ce38	3097	}
cparata	0:6d69e896ce38	3098
cparata	0:6d69e896ce38	3099	/**
cparata	0:6d69e896ce38	3100	* @brief Selects accelerometer OIS channel bandwidth.[get]
cparata	0:6d69e896ce38	3101	*
cparata	0:6d69e896ce38	3102	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3103	* @param val Get the values of
cparata	0:6d69e896ce38	3104	* filter_xl_conf_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3105	*
cparata	0:6d69e896ce38	3106	*/
cparata	0:6d69e896ce38	3107	int32_t lsm6dso_aux_xl_bandwidth_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3108	lsm6dso_filter_xl_conf_ois_t *val)
cparata	0:6d69e896ce38	3109	{
cparata	3:4274d9103f1d	3110	lsm6dso_ctrl3_ois_t reg;
cparata	3:4274d9103f1d	3111	int32_t ret;
cparata	3:4274d9103f1d	3112
cparata	3:4274d9103f1d	3113	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3114
cparata	3:4274d9103f1d	3115	switch (reg.filter_xl_conf_ois) {
cparata	3:4274d9103f1d	3116	case LSM6DSO_289Hz:
cparata	3:4274d9103f1d	3117	*val = LSM6DSO_289Hz;
cparata	3:4274d9103f1d	3118	break;
cparata	3:4274d9103f1d	3119	case LSM6DSO_258Hz:
cparata	3:4274d9103f1d	3120	*val = LSM6DSO_258Hz;
cparata	3:4274d9103f1d	3121	break;
cparata	3:4274d9103f1d	3122	case LSM6DSO_120Hz:
cparata	3:4274d9103f1d	3123	*val = LSM6DSO_120Hz;
cparata	3:4274d9103f1d	3124	break;
cparata	3:4274d9103f1d	3125	case LSM6DSO_65Hz2:
cparata	3:4274d9103f1d	3126	*val = LSM6DSO_65Hz2;
cparata	3:4274d9103f1d	3127	break;
cparata	3:4274d9103f1d	3128	case LSM6DSO_33Hz2:
cparata	3:4274d9103f1d	3129	*val = LSM6DSO_33Hz2;
cparata	3:4274d9103f1d	3130	break;
cparata	3:4274d9103f1d	3131	case LSM6DSO_16Hz6:
cparata	3:4274d9103f1d	3132	*val = LSM6DSO_16Hz6;
cparata	3:4274d9103f1d	3133	break;
cparata	3:4274d9103f1d	3134	case LSM6DSO_8Hz30:
cparata	3:4274d9103f1d	3135	*val = LSM6DSO_8Hz30;
cparata	3:4274d9103f1d	3136	break;
cparata	3:4274d9103f1d	3137	case LSM6DSO_4Hz15:
cparata	3:4274d9103f1d	3138	*val = LSM6DSO_4Hz15;
cparata	3:4274d9103f1d	3139	break;
cparata	3:4274d9103f1d	3140	default:
cparata	3:4274d9103f1d	3141	*val = LSM6DSO_289Hz;
cparata	3:4274d9103f1d	3142	break;
cparata	3:4274d9103f1d	3143	}
cparata	3:4274d9103f1d	3144	return ret;
cparata	0:6d69e896ce38	3145	}
cparata	0:6d69e896ce38	3146
cparata	0:6d69e896ce38	3147	/**
cparata	0:6d69e896ce38	3148	* @brief Selects accelerometer OIS channel full-scale.[set]
cparata	0:6d69e896ce38	3149	*
cparata	0:6d69e896ce38	3150	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3151	* @param val change the values of fs_xl_ois in
cparata	0:6d69e896ce38	3152	* reg CTRL3_OIS
cparata	0:6d69e896ce38	3153	*
cparata	0:6d69e896ce38	3154	*/
cparata	0:6d69e896ce38	3155	int32_t lsm6dso_aux_xl_full_scale_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3156	lsm6dso_fs_xl_ois_t val)
cparata	0:6d69e896ce38	3157	{
cparata	3:4274d9103f1d	3158	lsm6dso_ctrl3_ois_t reg;
cparata	3:4274d9103f1d	3159	int32_t ret;
cparata	3:4274d9103f1d	3160
cparata	3:4274d9103f1d	3161	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3162	if (ret == 0) {
cparata	3:4274d9103f1d	3163	reg.fs_xl_ois = (uint8_t)val;
cparata	3:4274d9103f1d	3164	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3165	}
cparata	3:4274d9103f1d	3166	return ret;
cparata	0:6d69e896ce38	3167	}
cparata	0:6d69e896ce38	3168
cparata	0:6d69e896ce38	3169	/**
cparata	0:6d69e896ce38	3170	* @brief Selects accelerometer OIS channel full-scale.[get]
cparata	0:6d69e896ce38	3171	*
cparata	0:6d69e896ce38	3172	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3173	* @param val Get the values of fs_xl_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3174	*
cparata	0:6d69e896ce38	3175	*/
cparata	0:6d69e896ce38	3176	int32_t lsm6dso_aux_xl_full_scale_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3177	lsm6dso_fs_xl_ois_t *val)
cparata	0:6d69e896ce38	3178	{
cparata	3:4274d9103f1d	3179	lsm6dso_ctrl3_ois_t reg;
cparata	3:4274d9103f1d	3180	int32_t ret;
cparata	3:4274d9103f1d	3181
cparata	3:4274d9103f1d	3182	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3183	switch (reg.fs_xl_ois) {
cparata	3:4274d9103f1d	3184	case LSM6DSO_AUX_2g:
cparata	3:4274d9103f1d	3185	*val = LSM6DSO_AUX_2g;
cparata	3:4274d9103f1d	3186	break;
cparata	3:4274d9103f1d	3187	case LSM6DSO_AUX_16g:
cparata	3:4274d9103f1d	3188	*val = LSM6DSO_AUX_16g;
cparata	3:4274d9103f1d	3189	break;
cparata	3:4274d9103f1d	3190	case LSM6DSO_AUX_4g:
cparata	3:4274d9103f1d	3191	*val = LSM6DSO_AUX_4g;
cparata	3:4274d9103f1d	3192	break;
cparata	3:4274d9103f1d	3193	case LSM6DSO_AUX_8g:
cparata	3:4274d9103f1d	3194	*val = LSM6DSO_AUX_8g;
cparata	3:4274d9103f1d	3195	break;
cparata	3:4274d9103f1d	3196	default:
cparata	3:4274d9103f1d	3197	*val = LSM6DSO_AUX_2g;
cparata	3:4274d9103f1d	3198	break;
cparata	3:4274d9103f1d	3199	}
cparata	3:4274d9103f1d	3200	return ret;
cparata	0:6d69e896ce38	3201	}
cparata	0:6d69e896ce38	3202
cparata	0:6d69e896ce38	3203	/**
cparata	0:6d69e896ce38	3204	* @}
cparata	0:6d69e896ce38	3205	*
cparata	0:6d69e896ce38	3206	*/
cparata	0:6d69e896ce38	3207
cparata	0:6d69e896ce38	3208	/**
cparata	0:6d69e896ce38	3209	* @defgroup LSM6DSO_ main_serial_interface
cparata	0:6d69e896ce38	3210	* @brief This section groups all the functions concerning main
cparata	0:6d69e896ce38	3211	* serial interface management (not auxiliary)
cparata	0:6d69e896ce38	3212	* @{
cparata	0:6d69e896ce38	3213	*
cparata	0:6d69e896ce38	3214	*/
cparata	0:6d69e896ce38	3215
cparata	0:6d69e896ce38	3216	/**
cparata	0:6d69e896ce38	3217	* @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
cparata	0:6d69e896ce38	3218	*
cparata	0:6d69e896ce38	3219	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3220	* @param val change the values of sdo_pu_en in
cparata	0:6d69e896ce38	3221	* reg PIN_CTRL
cparata	0:6d69e896ce38	3222	*
cparata	0:6d69e896ce38	3223	*/
cparata	0:6d69e896ce38	3224	int32_t lsm6dso_sdo_sa0_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sdo_pu_en_t val)
cparata	0:6d69e896ce38	3225	{
cparata	3:4274d9103f1d	3226	lsm6dso_pin_ctrl_t reg;
cparata	3:4274d9103f1d	3227	int32_t ret;
cparata	3:4274d9103f1d	3228
cparata	3:4274d9103f1d	3229	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3230	if (ret == 0) {
cparata	3:4274d9103f1d	3231	reg.sdo_pu_en = (uint8_t)val;
cparata	3:4274d9103f1d	3232	ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3233	}
cparata	3:4274d9103f1d	3234	return ret;
cparata	0:6d69e896ce38	3235	}
cparata	0:6d69e896ce38	3236
cparata	0:6d69e896ce38	3237	/**
cparata	0:6d69e896ce38	3238	* @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
cparata	0:6d69e896ce38	3239	*
cparata	0:6d69e896ce38	3240	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3241	* @param val Get the values of sdo_pu_en in reg PIN_CTRL
cparata	0:6d69e896ce38	3242	*
cparata	0:6d69e896ce38	3243	*/
cparata	0:6d69e896ce38	3244	int32_t lsm6dso_sdo_sa0_mode_get(lsm6dso_ctx_t ctx, lsm6dso_sdo_pu_en_t val)
cparata	0:6d69e896ce38	3245	{
cparata	3:4274d9103f1d	3246	lsm6dso_pin_ctrl_t reg;
cparata	3:4274d9103f1d	3247	int32_t ret;
cparata	3:4274d9103f1d	3248
cparata	3:4274d9103f1d	3249	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3250	switch (reg.sdo_pu_en) {
cparata	3:4274d9103f1d	3251	case LSM6DSO_PULL_UP_DISC:
cparata	3:4274d9103f1d	3252	*val = LSM6DSO_PULL_UP_DISC;
cparata	3:4274d9103f1d	3253	break;
cparata	3:4274d9103f1d	3254	case LSM6DSO_PULL_UP_CONNECT:
cparata	3:4274d9103f1d	3255	*val = LSM6DSO_PULL_UP_CONNECT;
cparata	3:4274d9103f1d	3256	break;
cparata	3:4274d9103f1d	3257	default:
cparata	3:4274d9103f1d	3258	*val = LSM6DSO_PULL_UP_DISC;
cparata	3:4274d9103f1d	3259	break;
cparata	3:4274d9103f1d	3260	}
cparata	3:4274d9103f1d	3261	return ret;
cparata	0:6d69e896ce38	3262	}
cparata	0:6d69e896ce38	3263
cparata	0:6d69e896ce38	3264	/**
cparata	0:6d69e896ce38	3265	* @brief SPI Serial Interface Mode selection.[set]
cparata	0:6d69e896ce38	3266	*
cparata	0:6d69e896ce38	3267	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3268	* @param val change the values of sim in reg CTRL3_C
cparata	0:6d69e896ce38	3269	*
cparata	0:6d69e896ce38	3270	*/
cparata	0:6d69e896ce38	3271	int32_t lsm6dso_spi_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sim_t val)
cparata	0:6d69e896ce38	3272	{
cparata	3:4274d9103f1d	3273	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	3274	int32_t ret;
cparata	3:4274d9103f1d	3275
cparata	3:4274d9103f1d	3276	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3277	if (ret == 0) {
cparata	3:4274d9103f1d	3278	reg.sim = (uint8_t)val;
cparata	3:4274d9103f1d	3279	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3280	}
cparata	3:4274d9103f1d	3281	return ret;
cparata	0:6d69e896ce38	3282	}
cparata	0:6d69e896ce38	3283
cparata	0:6d69e896ce38	3284	/**
cparata	0:6d69e896ce38	3285	* @brief SPI Serial Interface Mode selection.[get]
cparata	0:6d69e896ce38	3286	*
cparata	0:6d69e896ce38	3287	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3288	* @param val Get the values of sim in reg CTRL3_C
cparata	0:6d69e896ce38	3289	*
cparata	0:6d69e896ce38	3290	*/
cparata	0:6d69e896ce38	3291	int32_t lsm6dso_spi_mode_get(lsm6dso_ctx_t ctx, lsm6dso_sim_t val)
cparata	0:6d69e896ce38	3292	{
cparata	3:4274d9103f1d	3293	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	3294	int32_t ret;
cparata	3:4274d9103f1d	3295
cparata	3:4274d9103f1d	3296	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3297	switch (reg.sim) {
cparata	3:4274d9103f1d	3298	case LSM6DSO_SPI_4_WIRE:
cparata	3:4274d9103f1d	3299	*val = LSM6DSO_SPI_4_WIRE;
cparata	3:4274d9103f1d	3300	break;
cparata	3:4274d9103f1d	3301	case LSM6DSO_SPI_3_WIRE:
cparata	3:4274d9103f1d	3302	*val = LSM6DSO_SPI_3_WIRE;
cparata	3:4274d9103f1d	3303	break;
cparata	3:4274d9103f1d	3304	default:
cparata	3:4274d9103f1d	3305	*val = LSM6DSO_SPI_4_WIRE;
cparata	3:4274d9103f1d	3306	break;
cparata	3:4274d9103f1d	3307	}
cparata	3:4274d9103f1d	3308	return ret;
cparata	0:6d69e896ce38	3309	}
cparata	0:6d69e896ce38	3310
cparata	0:6d69e896ce38	3311	/**
cparata	0:6d69e896ce38	3312	* @brief Disable / Enable I2C interface.[set]
cparata	0:6d69e896ce38	3313	*
cparata	0:6d69e896ce38	3314	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3315	* @param val change the values of i2c_disable in
cparata	0:6d69e896ce38	3316	* reg CTRL4_C
cparata	0:6d69e896ce38	3317	*
cparata	0:6d69e896ce38	3318	*/
cparata	0:6d69e896ce38	3319	int32_t lsm6dso_i2c_interface_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3320	lsm6dso_i2c_disable_t val)
cparata	0:6d69e896ce38	3321	{
cparata	3:4274d9103f1d	3322	lsm6dso_ctrl4_c_t reg;
cparata	3:4274d9103f1d	3323	int32_t ret;
cparata	3:4274d9103f1d	3324
cparata	3:4274d9103f1d	3325	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3326	if (ret == 0) {
cparata	3:4274d9103f1d	3327	reg.i2c_disable = (uint8_t)val;
cparata	3:4274d9103f1d	3328	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3329	}
cparata	3:4274d9103f1d	3330	return ret;
cparata	0:6d69e896ce38	3331	}
cparata	0:6d69e896ce38	3332
cparata	0:6d69e896ce38	3333	/**
cparata	0:6d69e896ce38	3334	* @brief Disable / Enable I2C interface.[get]
cparata	0:6d69e896ce38	3335	*
cparata	0:6d69e896ce38	3336	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3337	* @param val Get the values of i2c_disable in
cparata	0:6d69e896ce38	3338	* reg CTRL4_C
cparata	0:6d69e896ce38	3339	*
cparata	0:6d69e896ce38	3340	*/
cparata	0:6d69e896ce38	3341	int32_t lsm6dso_i2c_interface_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3342	lsm6dso_i2c_disable_t *val)
cparata	0:6d69e896ce38	3343	{
cparata	3:4274d9103f1d	3344	lsm6dso_ctrl4_c_t reg;
cparata	3:4274d9103f1d	3345	int32_t ret;
cparata	3:4274d9103f1d	3346
cparata	3:4274d9103f1d	3347	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3348	switch (reg.i2c_disable) {
cparata	3:4274d9103f1d	3349	case LSM6DSO_I2C_ENABLE:
cparata	3:4274d9103f1d	3350	*val = LSM6DSO_I2C_ENABLE;
cparata	3:4274d9103f1d	3351	break;
cparata	3:4274d9103f1d	3352	case LSM6DSO_I2C_DISABLE:
cparata	3:4274d9103f1d	3353	*val = LSM6DSO_I2C_DISABLE;
cparata	3:4274d9103f1d	3354	break;
cparata	3:4274d9103f1d	3355	default:
cparata	3:4274d9103f1d	3356	*val = LSM6DSO_I2C_ENABLE;
cparata	3:4274d9103f1d	3357	break;
cparata	3:4274d9103f1d	3358	}
cparata	3:4274d9103f1d	3359	return ret;
cparata	0:6d69e896ce38	3360	}
cparata	0:6d69e896ce38	3361
cparata	0:6d69e896ce38	3362	/**
cparata	0:6d69e896ce38	3363	* @brief I3C Enable/Disable communication protocol[.set]
cparata	0:6d69e896ce38	3364	*
cparata	0:6d69e896ce38	3365	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3366	* @param val change the values of i3c_disable
cparata	0:6d69e896ce38	3367	* in reg CTRL9_XL
cparata	0:6d69e896ce38	3368	*
cparata	0:6d69e896ce38	3369	*/
cparata	0:6d69e896ce38	3370	int32_t lsm6dso_i3c_disable_set(lsm6dso_ctx_t *ctx, lsm6dso_i3c_disable_t val)
cparata	0:6d69e896ce38	3371	{
cparata	3:4274d9103f1d	3372	lsm6dso_i3c_bus_avb_t i3c_bus_avb;
cparata	3:4274d9103f1d	3373	lsm6dso_ctrl9_xl_t ctrl9_xl;
cparata	3:4274d9103f1d	3374	int32_t ret;
cparata	3:4274d9103f1d	3375
cparata	3:4274d9103f1d	3376	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
cparata	3:4274d9103f1d	3377	if (ret == 0) {
cparata	3:4274d9103f1d	3378	ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
cparata	3:4274d9103f1d	3379	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
cparata	3:4274d9103f1d	3380	}
cparata	3:4274d9103f1d	3381	if (ret == 0) {
cparata	3:4274d9103f1d	3382
cparata	3:4274d9103f1d	3383	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	3:4274d9103f1d	3384	(uint8_t *)&i3c_bus_avb, 1);
cparata	3:4274d9103f1d	3385	}
cparata	3:4274d9103f1d	3386	if (ret == 0) {
cparata	3:4274d9103f1d	3387	i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
cparata	3:4274d9103f1d	3388	ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	3:4274d9103f1d	3389	(uint8_t *)&i3c_bus_avb, 1);
cparata	3:4274d9103f1d	3390	}
cparata	3:4274d9103f1d	3391
cparata	3:4274d9103f1d	3392	return ret;
cparata	0:6d69e896ce38	3393	}
cparata	0:6d69e896ce38	3394
cparata	0:6d69e896ce38	3395	/**
cparata	0:6d69e896ce38	3396	* @brief I3C Enable/Disable communication protocol.[get]
cparata	0:6d69e896ce38	3397	*
cparata	0:6d69e896ce38	3398	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3399	* @param val change the values of i3c_disable in
cparata	0:6d69e896ce38	3400	* reg CTRL9_XL
cparata	0:6d69e896ce38	3401	*
cparata	0:6d69e896ce38	3402	*/
cparata	0:6d69e896ce38	3403	int32_t lsm6dso_i3c_disable_get(lsm6dso_ctx_t ctx, lsm6dso_i3c_disable_t val)
cparata	0:6d69e896ce38	3404	{
cparata	3:4274d9103f1d	3405	lsm6dso_ctrl9_xl_t ctrl9_xl;
cparata	3:4274d9103f1d	3406	lsm6dso_i3c_bus_avb_t i3c_bus_avb;
cparata	3:4274d9103f1d	3407	int32_t ret;
cparata	3:4274d9103f1d	3408
cparata	3:4274d9103f1d	3409	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
cparata	3:4274d9103f1d	3410	if (ret == 0) {
cparata	3:4274d9103f1d	3411	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	3:4274d9103f1d	3412	(uint8_t *)&i3c_bus_avb, 1);
cparata	3:4274d9103f1d	3413
cparata	3:4274d9103f1d	3414	switch ((ctrl9_xl.i3c_disable << 7) \| i3c_bus_avb.i3c_bus_avb_sel) {
cparata	3:4274d9103f1d	3415	case LSM6DSO_I3C_DISABLE:
cparata	3:4274d9103f1d	3416	*val = LSM6DSO_I3C_DISABLE;
cparata	3:4274d9103f1d	3417	break;
cparata	3:4274d9103f1d	3418	case LSM6DSO_I3C_ENABLE_T_50us:
cparata	3:4274d9103f1d	3419	*val = LSM6DSO_I3C_ENABLE_T_50us;
cparata	3:4274d9103f1d	3420	break;
cparata	3:4274d9103f1d	3421	case LSM6DSO_I3C_ENABLE_T_2us:
cparata	3:4274d9103f1d	3422	*val = LSM6DSO_I3C_ENABLE_T_2us;
cparata	3:4274d9103f1d	3423	break;
cparata	3:4274d9103f1d	3424	case LSM6DSO_I3C_ENABLE_T_1ms:
cparata	3:4274d9103f1d	3425	*val = LSM6DSO_I3C_ENABLE_T_1ms;
cparata	3:4274d9103f1d	3426	break;
cparata	3:4274d9103f1d	3427	case LSM6DSO_I3C_ENABLE_T_25ms:
cparata	3:4274d9103f1d	3428	*val = LSM6DSO_I3C_ENABLE_T_25ms;
cparata	3:4274d9103f1d	3429	break;
cparata	3:4274d9103f1d	3430	default:
cparata	3:4274d9103f1d	3431	*val = LSM6DSO_I3C_DISABLE;
cparata	3:4274d9103f1d	3432	break;
cparata	3:4274d9103f1d	3433	}
cparata	3:4274d9103f1d	3434	}
cparata	3:4274d9103f1d	3435	return ret;
cparata	0:6d69e896ce38	3436	}
cparata	0:6d69e896ce38	3437
cparata	0:6d69e896ce38	3438	/**
cparata	0:6d69e896ce38	3439	* @}
cparata	0:6d69e896ce38	3440	*
cparata	0:6d69e896ce38	3441	*/
cparata	0:6d69e896ce38	3442
cparata	0:6d69e896ce38	3443	/**
cparata	0:6d69e896ce38	3444	* @defgroup LSM6DSO_interrupt_pins
cparata	0:6d69e896ce38	3445	* @brief This section groups all the functions that manage interrup pins
cparata	0:6d69e896ce38	3446	* @{
cparata	0:6d69e896ce38	3447	*
cparata	0:6d69e896ce38	3448	*/
cparata	0:6d69e896ce38	3449
cparata	0:6d69e896ce38	3450	/**
cparata	0:6d69e896ce38	3451	* @brief Connect/Disconnect INT1 internal pull-down.[set]
cparata	0:6d69e896ce38	3452	*
cparata	0:6d69e896ce38	3453	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3454	* @param val change the values of pd_dis_int1 in reg I3C_BUS_AVB
cparata	0:6d69e896ce38	3455	*
cparata	0:6d69e896ce38	3456	*/
cparata	0:6d69e896ce38	3457	int32_t lsm6dso_int1_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_int1_pd_en_t val)
cparata	0:6d69e896ce38	3458	{
cparata	3:4274d9103f1d	3459	lsm6dso_i3c_bus_avb_t reg;
cparata	3:4274d9103f1d	3460	int32_t ret;
cparata	3:4274d9103f1d	3461
cparata	3:4274d9103f1d	3462	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3463	if (ret == 0) {
cparata	3:4274d9103f1d	3464	reg.pd_dis_int1 = (uint8_t)val;
cparata	3:4274d9103f1d	3465	ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3466	}
cparata	3:4274d9103f1d	3467	return ret;
cparata	0:6d69e896ce38	3468	}
cparata	0:6d69e896ce38	3469
cparata	0:6d69e896ce38	3470	/**
cparata	0:6d69e896ce38	3471	* @brief Connect/Disconnect INT1 internal pull-down.[get]
cparata	0:6d69e896ce38	3472	*
cparata	0:6d69e896ce38	3473	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3474	* @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
cparata	0:6d69e896ce38	3475	*
cparata	0:6d69e896ce38	3476	*/
cparata	0:6d69e896ce38	3477	int32_t lsm6dso_int1_mode_get(lsm6dso_ctx_t ctx, lsm6dso_int1_pd_en_t val)
cparata	0:6d69e896ce38	3478	{
cparata	3:4274d9103f1d	3479	lsm6dso_i3c_bus_avb_t reg;
cparata	3:4274d9103f1d	3480	int32_t ret;
cparata	3:4274d9103f1d	3481
cparata	3:4274d9103f1d	3482	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3483	switch (reg.pd_dis_int1) {
cparata	3:4274d9103f1d	3484	case LSM6DSO_PULL_DOWN_DISC:
cparata	3:4274d9103f1d	3485	*val = LSM6DSO_PULL_DOWN_DISC;
cparata	3:4274d9103f1d	3486	break;
cparata	3:4274d9103f1d	3487	case LSM6DSO_PULL_DOWN_CONNECT:
cparata	3:4274d9103f1d	3488	*val = LSM6DSO_PULL_DOWN_CONNECT;
cparata	3:4274d9103f1d	3489	break;
cparata	3:4274d9103f1d	3490	default:
cparata	3:4274d9103f1d	3491	*val = LSM6DSO_PULL_DOWN_DISC;
cparata	3:4274d9103f1d	3492	break;
cparata	3:4274d9103f1d	3493	}
cparata	3:4274d9103f1d	3494	return ret;
cparata	0:6d69e896ce38	3495	}
cparata	0:6d69e896ce38	3496
cparata	0:6d69e896ce38	3497	/**
cparata	0:6d69e896ce38	3498	* @brief Select the signal that need to route on int1 pad.[set]
cparata	0:6d69e896ce38	3499	*
cparata	0:6d69e896ce38	3500	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3501	* @param val struct of registers: INT1_CTRL,
cparata	0:6d69e896ce38	3502	* MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A,
cparata	0:6d69e896ce38	3503	* FSM_INT1_B
cparata	0:6d69e896ce38	3504	*
cparata	0:6d69e896ce38	3505	*/
cparata	0:6d69e896ce38	3506	int32_t lsm6dso_pin_int1_route_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3507	lsm6dso_pin_int1_route_t *val)
cparata	0:6d69e896ce38	3508	{
cparata	3:4274d9103f1d	3509	lsm6dso_pin_int2_route_t pin_int2_route;
cparata	3:4274d9103f1d	3510	lsm6dso_tap_cfg2_t tap_cfg2;
cparata	3:4274d9103f1d	3511	int32_t ret;
cparata	3:4274d9103f1d	3512
cparata	3:4274d9103f1d	3513	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	3514	if (ret == 0) {
cparata	3:4274d9103f1d	3515	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT1,
cparata	3:4274d9103f1d	3516	(uint8_t *)&val->emb_func_int1, 1);
cparata	3:4274d9103f1d	3517	}
cparata	3:4274d9103f1d	3518	if (ret == 0) {
cparata	3:4274d9103f1d	3519	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_A,
cparata	3:4274d9103f1d	3520	(uint8_t *)&val->fsm_int1_a, 1);
cparata	3:4274d9103f1d	3521	}
cparata	3:4274d9103f1d	3522	if (ret == 0) {
cparata	3:4274d9103f1d	3523	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_B,
cparata	3:4274d9103f1d	3524	(uint8_t *)&val->fsm_int1_b, 1);
cparata	3:4274d9103f1d	3525	}
cparata	3:4274d9103f1d	3526	if (ret == 0) {
cparata	3:4274d9103f1d	3527	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	3528	}
cparata	3:4274d9103f1d	3529
cparata	3:4274d9103f1d	3530	if (ret == 0) {
cparata	3:4274d9103f1d	3531	if ((val->emb_func_int1.int1_fsm_lc
cparata	3:4274d9103f1d	3532	\| val->emb_func_int1.int1_sig_mot
cparata	3:4274d9103f1d	3533	\| val->emb_func_int1.int1_step_detector
cparata	3:4274d9103f1d	3534	\| val->emb_func_int1.int1_tilt
cparata	3:4274d9103f1d	3535	\| val->fsm_int1_a.int1_fsm1
cparata	3:4274d9103f1d	3536	\| val->fsm_int1_a.int1_fsm2
cparata	3:4274d9103f1d	3537	\| val->fsm_int1_a.int1_fsm3
cparata	3:4274d9103f1d	3538	\| val->fsm_int1_a.int1_fsm4
cparata	3:4274d9103f1d	3539	\| val->fsm_int1_a.int1_fsm5
cparata	3:4274d9103f1d	3540	\| val->fsm_int1_a.int1_fsm6
cparata	3:4274d9103f1d	3541	\| val->fsm_int1_a.int1_fsm7
cparata	3:4274d9103f1d	3542	\| val->fsm_int1_a.int1_fsm8
cparata	3:4274d9103f1d	3543	\| val->fsm_int1_b.int1_fsm9
cparata	3:4274d9103f1d	3544	\| val->fsm_int1_b.int1_fsm10
cparata	3:4274d9103f1d	3545	\| val->fsm_int1_b.int1_fsm11
cparata	3:4274d9103f1d	3546	\| val->fsm_int1_b.int1_fsm12
cparata	3:4274d9103f1d	3547	\| val->fsm_int1_b.int1_fsm13
cparata	3:4274d9103f1d	3548	\| val->fsm_int1_b.int1_fsm14
cparata	3:4274d9103f1d	3549	\| val->fsm_int1_b.int1_fsm15
cparata	3:4274d9103f1d	3550	\| val->fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE) {
cparata	3:4274d9103f1d	3551	val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
cparata	3:4274d9103f1d	3552	} else {
cparata	3:4274d9103f1d	3553	val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
cparata	3:4274d9103f1d	3554	}
cparata	3:4274d9103f1d	3555	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT1_CTRL,
cparata	3:4274d9103f1d	3556	(uint8_t *)&val->int1_ctrl, 1);
cparata	3:4274d9103f1d	3557	}
cparata	3:4274d9103f1d	3558	if (ret == 0) {
cparata	3:4274d9103f1d	3559	ret = lsm6dso_write_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t *)&val->md1_cfg, 1);
cparata	3:4274d9103f1d	3560	}
cparata	3:4274d9103f1d	3561	if (ret == 0) {
cparata	3:4274d9103f1d	3562	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
cparata	3:4274d9103f1d	3563	}
cparata	3:4274d9103f1d	3564
cparata	3:4274d9103f1d	3565	if (ret == 0) {
cparata	3:4274d9103f1d	3566	ret = lsm6dso_pin_int2_route_get(ctx, &pin_int2_route);
cparata	3:4274d9103f1d	3567	}
cparata	3:4274d9103f1d	3568	if (ret == 0) {
cparata	3:4274d9103f1d	3569	if ((pin_int2_route.int2_ctrl.int2_cnt_bdr
cparata	3:4274d9103f1d	3570	\| pin_int2_route.int2_ctrl.int2_drdy_g
cparata	3:4274d9103f1d	3571	\| pin_int2_route.int2_ctrl.int2_drdy_temp
cparata	3:4274d9103f1d	3572	\| pin_int2_route.int2_ctrl.int2_drdy_xl
cparata	3:4274d9103f1d	3573	\| pin_int2_route.int2_ctrl.int2_fifo_full
cparata	3:4274d9103f1d	3574	\| pin_int2_route.int2_ctrl.int2_fifo_ovr
cparata	3:4274d9103f1d	3575	\| pin_int2_route.int2_ctrl.int2_fifo_th
cparata	3:4274d9103f1d	3576	\| pin_int2_route.md2_cfg.int2_6d
cparata	3:4274d9103f1d	3577	\| pin_int2_route.md2_cfg.int2_double_tap
cparata	3:4274d9103f1d	3578	\| pin_int2_route.md2_cfg.int2_ff
cparata	3:4274d9103f1d	3579	\| pin_int2_route.md2_cfg.int2_wu
cparata	3:4274d9103f1d	3580	\| pin_int2_route.md2_cfg.int2_single_tap
cparata	3:4274d9103f1d	3581	\| pin_int2_route.md2_cfg.int2_sleep_change
cparata	3:4274d9103f1d	3582	\| val->int1_ctrl.den_drdy_flag
cparata	3:4274d9103f1d	3583	\| val->int1_ctrl.int1_boot
cparata	3:4274d9103f1d	3584	\| val->int1_ctrl.int1_cnt_bdr
cparata	3:4274d9103f1d	3585	\| val->int1_ctrl.int1_drdy_g
cparata	3:4274d9103f1d	3586	\| val->int1_ctrl.int1_drdy_xl
cparata	3:4274d9103f1d	3587	\| val->int1_ctrl.int1_fifo_full
cparata	3:4274d9103f1d	3588	\| val->int1_ctrl.int1_fifo_ovr
cparata	3:4274d9103f1d	3589	\| val->int1_ctrl.int1_fifo_th
cparata	3:4274d9103f1d	3590	\| val->md1_cfg.int1_6d
cparata	3:4274d9103f1d	3591	\| val->md1_cfg.int1_double_tap
cparata	3:4274d9103f1d	3592	\| val->md1_cfg.int1_ff
cparata	3:4274d9103f1d	3593	\| val->md1_cfg.int1_wu
cparata	3:4274d9103f1d	3594	\| val->md1_cfg.int1_single_tap
cparata	3:4274d9103f1d	3595	\| val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) {
cparata	3:4274d9103f1d	3596	tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
cparata	3:4274d9103f1d	3597	} else {
cparata	3:4274d9103f1d	3598	tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
cparata	3:4274d9103f1d	3599	}
cparata	3:4274d9103f1d	3600	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
cparata	3:4274d9103f1d	3601	}
cparata	3:4274d9103f1d	3602	return ret;
cparata	0:6d69e896ce38	3603	}
cparata	0:6d69e896ce38	3604
cparata	0:6d69e896ce38	3605	/**
cparata	0:6d69e896ce38	3606	* @brief Select the signal that need to route on int1 pad.[get]
cparata	0:6d69e896ce38	3607	*
cparata	0:6d69e896ce38	3608	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3609	* @param val struct of registers: INT1_CTRL, MD1_CFG,
cparata	0:6d69e896ce38	3610	* EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
cparata	0:6d69e896ce38	3611	*
cparata	0:6d69e896ce38	3612	*/
cparata	0:6d69e896ce38	3613	int32_t lsm6dso_pin_int1_route_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3614	lsm6dso_pin_int1_route_t *val)
cparata	0:6d69e896ce38	3615	{
cparata	3:4274d9103f1d	3616	int32_t ret;
cparata	3:4274d9103f1d	3617
cparata	3:4274d9103f1d	3618	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	3619	if (ret == 0) {
cparata	3:4274d9103f1d	3620	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT1,
cparata	3:4274d9103f1d	3621	(uint8_t *)&val->emb_func_int1, 1);
cparata	3:4274d9103f1d	3622	}
cparata	3:4274d9103f1d	3623	if (ret == 0) {
cparata	3:4274d9103f1d	3624	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_A,
cparata	3:4274d9103f1d	3625	(uint8_t *)&val->fsm_int1_a, 1);
cparata	3:4274d9103f1d	3626	}
cparata	3:4274d9103f1d	3627	if (ret == 0) {
cparata	3:4274d9103f1d	3628	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_B,
cparata	3:4274d9103f1d	3629	(uint8_t *)&val->fsm_int1_b, 1);
cparata	3:4274d9103f1d	3630	}
cparata	3:4274d9103f1d	3631	if (ret == 0) {
cparata	3:4274d9103f1d	3632	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	3633	}
cparata	3:4274d9103f1d	3634	if (ret == 0) {
cparata	3:4274d9103f1d	3635
cparata	3:4274d9103f1d	3636	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT1_CTRL,
cparata	3:4274d9103f1d	3637	(uint8_t *)&val->int1_ctrl, 1);
cparata	3:4274d9103f1d	3638	}
cparata	3:4274d9103f1d	3639	if (ret == 0) {
cparata	3:4274d9103f1d	3640	ret = lsm6dso_read_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t *)&val->md1_cfg, 1);
cparata	3:4274d9103f1d	3641	}
cparata	3:4274d9103f1d	3642
cparata	3:4274d9103f1d	3643	return ret;
cparata	0:6d69e896ce38	3644	}
cparata	0:6d69e896ce38	3645
cparata	0:6d69e896ce38	3646	/**
cparata	0:6d69e896ce38	3647	* @brief Select the signal that need to route on int2 pad.[set]
cparata	0:6d69e896ce38	3648	*
cparata	0:6d69e896ce38	3649	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3650	* @param val union of registers INT2_CTRL, MD2_CFG,
cparata	0:6d69e896ce38	3651	* EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
cparata	0:6d69e896ce38	3652	*
cparata	0:6d69e896ce38	3653	*/
cparata	0:6d69e896ce38	3654	int32_t lsm6dso_pin_int2_route_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3655	lsm6dso_pin_int2_route_t *val)
cparata	0:6d69e896ce38	3656	{
cparata	3:4274d9103f1d	3657	lsm6dso_pin_int1_route_t pin_int1_route;
cparata	3:4274d9103f1d	3658	lsm6dso_tap_cfg2_t tap_cfg2;
cparata	3:4274d9103f1d	3659	int32_t ret;
cparata	3:4274d9103f1d	3660
cparata	3:4274d9103f1d	3661	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	3662	if (ret == 0) {
cparata	3:4274d9103f1d	3663	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT2,
cparata	3:4274d9103f1d	3664	(uint8_t *)&val->emb_func_int2, 1);
cparata	3:4274d9103f1d	3665	}
cparata	3:4274d9103f1d	3666	if (ret == 0) {
cparata	3:4274d9103f1d	3667	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_A,
cparata	3:4274d9103f1d	3668	(uint8_t *)&val->fsm_int2_a, 1);
cparata	3:4274d9103f1d	3669	}
cparata	3:4274d9103f1d	3670	if (ret == 0) {
cparata	3:4274d9103f1d	3671	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_B,
cparata	3:4274d9103f1d	3672	(uint8_t *)&val->fsm_int2_b, 1);
cparata	3:4274d9103f1d	3673	}
cparata	3:4274d9103f1d	3674	if (ret == 0) {
cparata	3:4274d9103f1d	3675	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	3676	}
cparata	3:4274d9103f1d	3677
cparata	3:4274d9103f1d	3678	if (ret == 0) {
cparata	3:4274d9103f1d	3679	if ((val->emb_func_int2.int2_fsm_lc
cparata	3:4274d9103f1d	3680	\| val->emb_func_int2.int2_sig_mot
cparata	3:4274d9103f1d	3681	\| val->emb_func_int2.int2_step_detector
cparata	3:4274d9103f1d	3682	\| val->emb_func_int2.int2_tilt
cparata	3:4274d9103f1d	3683	\| val->fsm_int2_a.int2_fsm1
cparata	3:4274d9103f1d	3684	\| val->fsm_int2_a.int2_fsm2
cparata	3:4274d9103f1d	3685	\| val->fsm_int2_a.int2_fsm3
cparata	3:4274d9103f1d	3686	\| val->fsm_int2_a.int2_fsm4
cparata	3:4274d9103f1d	3687	\| val->fsm_int2_a.int2_fsm5
cparata	3:4274d9103f1d	3688	\| val->fsm_int2_a.int2_fsm6
cparata	3:4274d9103f1d	3689	\| val->fsm_int2_a.int2_fsm7
cparata	3:4274d9103f1d	3690	\| val->fsm_int2_a.int2_fsm8
cparata	3:4274d9103f1d	3691	\| val->fsm_int2_b.int2_fsm9
cparata	3:4274d9103f1d	3692	\| val->fsm_int2_b.int2_fsm10
cparata	3:4274d9103f1d	3693	\| val->fsm_int2_b.int2_fsm11
cparata	3:4274d9103f1d	3694	\| val->fsm_int2_b.int2_fsm12
cparata	3:4274d9103f1d	3695	\| val->fsm_int2_b.int2_fsm13
cparata	3:4274d9103f1d	3696	\| val->fsm_int2_b.int2_fsm14
cparata	3:4274d9103f1d	3697	\| val->fsm_int2_b.int2_fsm15
cparata	3:4274d9103f1d	3698	\| val->fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE) {
cparata	3:4274d9103f1d	3699	val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
cparata	3:4274d9103f1d	3700	} else {
cparata	3:4274d9103f1d	3701	val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
cparata	3:4274d9103f1d	3702	}
cparata	3:4274d9103f1d	3703	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL,
cparata	3:4274d9103f1d	3704	(uint8_t *)&val->int2_ctrl, 1);
cparata	3:4274d9103f1d	3705	}
cparata	3:4274d9103f1d	3706	if (ret == 0) {
cparata	3:4274d9103f1d	3707	ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&val->md2_cfg, 1);
cparata	3:4274d9103f1d	3708	}
cparata	3:4274d9103f1d	3709	if (ret == 0) {
cparata	3:4274d9103f1d	3710	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
cparata	3:4274d9103f1d	3711	}
cparata	3:4274d9103f1d	3712
cparata	3:4274d9103f1d	3713	if (ret == 0) {
cparata	3:4274d9103f1d	3714	ret = lsm6dso_pin_int1_route_get(ctx, &pin_int1_route);
cparata	3:4274d9103f1d	3715	}
cparata	3:4274d9103f1d	3716
cparata	3:4274d9103f1d	3717	if (ret == 0) {
cparata	3:4274d9103f1d	3718	if ((val->int2_ctrl.int2_cnt_bdr
cparata	3:4274d9103f1d	3719	\| val->int2_ctrl.int2_drdy_g
cparata	3:4274d9103f1d	3720	\| val->int2_ctrl.int2_drdy_temp
cparata	3:4274d9103f1d	3721	\| val->int2_ctrl.int2_drdy_xl
cparata	3:4274d9103f1d	3722	\| val->int2_ctrl.int2_fifo_full
cparata	3:4274d9103f1d	3723	\| val->int2_ctrl.int2_fifo_ovr
cparata	3:4274d9103f1d	3724	\| val->int2_ctrl.int2_fifo_th
cparata	3:4274d9103f1d	3725	\| val->md2_cfg.int2_6d
cparata	3:4274d9103f1d	3726	\| val->md2_cfg.int2_double_tap
cparata	3:4274d9103f1d	3727	\| val->md2_cfg.int2_ff
cparata	3:4274d9103f1d	3728	\| val->md2_cfg.int2_wu
cparata	3:4274d9103f1d	3729	\| val->md2_cfg.int2_single_tap
cparata	3:4274d9103f1d	3730	\| val->md2_cfg.int2_sleep_change
cparata	3:4274d9103f1d	3731	\| pin_int1_route.int1_ctrl.den_drdy_flag
cparata	3:4274d9103f1d	3732	\| pin_int1_route.int1_ctrl.int1_boot
cparata	3:4274d9103f1d	3733	\| pin_int1_route.int1_ctrl.int1_cnt_bdr
cparata	3:4274d9103f1d	3734	\| pin_int1_route.int1_ctrl.int1_drdy_g
cparata	3:4274d9103f1d	3735	\| pin_int1_route.int1_ctrl.int1_drdy_xl
cparata	3:4274d9103f1d	3736	\| pin_int1_route.int1_ctrl.int1_fifo_full
cparata	3:4274d9103f1d	3737	\| pin_int1_route.int1_ctrl.int1_fifo_ovr
cparata	3:4274d9103f1d	3738	\| pin_int1_route.int1_ctrl.int1_fifo_th
cparata	3:4274d9103f1d	3739	\| pin_int1_route.md1_cfg.int1_6d
cparata	3:4274d9103f1d	3740	\| pin_int1_route.md1_cfg.int1_double_tap
cparata	3:4274d9103f1d	3741	\| pin_int1_route.md1_cfg.int1_ff
cparata	3:4274d9103f1d	3742	\| pin_int1_route.md1_cfg.int1_wu
cparata	3:4274d9103f1d	3743	\| pin_int1_route.md1_cfg.int1_single_tap
cparata	3:4274d9103f1d	3744	\| pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) {
cparata	3:4274d9103f1d	3745	tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
cparata	3:4274d9103f1d	3746	} else {
cparata	3:4274d9103f1d	3747	tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
cparata	3:4274d9103f1d	3748	}
cparata	3:4274d9103f1d	3749	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
cparata	3:4274d9103f1d	3750	}
cparata	3:4274d9103f1d	3751	return ret;
cparata	0:6d69e896ce38	3752	}
cparata	0:6d69e896ce38	3753
cparata	0:6d69e896ce38	3754	/**
cparata	0:6d69e896ce38	3755	* @brief Select the signal that need to route on int2 pad.[get]
cparata	0:6d69e896ce38	3756	*
cparata	0:6d69e896ce38	3757	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3758	* @param val union of registers INT2_CTRL, MD2_CFG,
cparata	0:6d69e896ce38	3759	* EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
cparata	0:6d69e896ce38	3760	*
cparata	0:6d69e896ce38	3761	*/
cparata	0:6d69e896ce38	3762	int32_t lsm6dso_pin_int2_route_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3763	lsm6dso_pin_int2_route_t *val)
cparata	0:6d69e896ce38	3764	{
cparata	3:4274d9103f1d	3765	int32_t ret;
cparata	3:4274d9103f1d	3766
cparata	3:4274d9103f1d	3767	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	3768	if (ret == 0) {
cparata	3:4274d9103f1d	3769	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT2,
cparata	3:4274d9103f1d	3770	(uint8_t *)&val->emb_func_int2, 1);
cparata	3:4274d9103f1d	3771	}
cparata	3:4274d9103f1d	3772	if (ret == 0) {
cparata	3:4274d9103f1d	3773	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_A,
cparata	3:4274d9103f1d	3774	(uint8_t *)&val->fsm_int2_a, 1);
cparata	3:4274d9103f1d	3775	}
cparata	3:4274d9103f1d	3776	if (ret == 0) {
cparata	3:4274d9103f1d	3777	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_B,
cparata	3:4274d9103f1d	3778	(uint8_t *)&val->fsm_int2_b, 1);
cparata	3:4274d9103f1d	3779	}
cparata	3:4274d9103f1d	3780	if (ret == 0) {
cparata	3:4274d9103f1d	3781	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	3782	}
cparata	3:4274d9103f1d	3783	if (ret == 0) {
cparata	3:4274d9103f1d	3784
cparata	3:4274d9103f1d	3785	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL,
cparata	3:4274d9103f1d	3786	(uint8_t *)&val->int2_ctrl, 1);
cparata	3:4274d9103f1d	3787	}
cparata	3:4274d9103f1d	3788	if (ret == 0) {
cparata	3:4274d9103f1d	3789	ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&val->md2_cfg, 1);
cparata	3:4274d9103f1d	3790	}
cparata	3:4274d9103f1d	3791	return ret;
cparata	0:6d69e896ce38	3792	}
cparata	0:6d69e896ce38	3793
cparata	0:6d69e896ce38	3794	/**
cparata	0:6d69e896ce38	3795	* @brief Push-pull/open drain selection on interrupt pads.[set]
cparata	0:6d69e896ce38	3796	*
cparata	0:6d69e896ce38	3797	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3798	* @param val change the values of pp_od in reg CTRL3_C
cparata	0:6d69e896ce38	3799	*
cparata	0:6d69e896ce38	3800	*/
cparata	0:6d69e896ce38	3801	int32_t lsm6dso_pin_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_pp_od_t val)
cparata	0:6d69e896ce38	3802	{
cparata	3:4274d9103f1d	3803	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	3804	int32_t ret;
cparata	3:4274d9103f1d	3805
cparata	3:4274d9103f1d	3806	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3807	if (ret == 0) {
cparata	3:4274d9103f1d	3808	reg.pp_od = (uint8_t)val;
cparata	3:4274d9103f1d	3809	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3810	}
cparata	3:4274d9103f1d	3811	return ret;
cparata	0:6d69e896ce38	3812	}
cparata	0:6d69e896ce38	3813
cparata	0:6d69e896ce38	3814	/**
cparata	0:6d69e896ce38	3815	* @brief Push-pull/open drain selection on interrupt pads.[get]
cparata	0:6d69e896ce38	3816	*
cparata	0:6d69e896ce38	3817	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3818	* @param val Get the values of pp_od in reg CTRL3_C
cparata	0:6d69e896ce38	3819	*
cparata	0:6d69e896ce38	3820	*/
cparata	0:6d69e896ce38	3821	int32_t lsm6dso_pin_mode_get(lsm6dso_ctx_t ctx, lsm6dso_pp_od_t val)
cparata	0:6d69e896ce38	3822	{
cparata	3:4274d9103f1d	3823	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	3824	int32_t ret;
cparata	3:4274d9103f1d	3825
cparata	3:4274d9103f1d	3826	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3827
cparata	3:4274d9103f1d	3828	switch (reg.pp_od) {
cparata	3:4274d9103f1d	3829	case LSM6DSO_PUSH_PULL:
cparata	3:4274d9103f1d	3830	*val = LSM6DSO_PUSH_PULL;
cparata	3:4274d9103f1d	3831	break;
cparata	3:4274d9103f1d	3832	case LSM6DSO_OPEN_DRAIN:
cparata	3:4274d9103f1d	3833	*val = LSM6DSO_OPEN_DRAIN;
cparata	3:4274d9103f1d	3834	break;
cparata	3:4274d9103f1d	3835	default:
cparata	3:4274d9103f1d	3836	*val = LSM6DSO_PUSH_PULL;
cparata	3:4274d9103f1d	3837	break;
cparata	3:4274d9103f1d	3838	}
cparata	3:4274d9103f1d	3839	return ret;
cparata	0:6d69e896ce38	3840	}
cparata	0:6d69e896ce38	3841
cparata	0:6d69e896ce38	3842	/**
cparata	0:6d69e896ce38	3843	* @brief Interrupt active-high/low.[set]
cparata	0:6d69e896ce38	3844	*
cparata	0:6d69e896ce38	3845	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3846	* @param val change the values of h_lactive in reg CTRL3_C
cparata	0:6d69e896ce38	3847	*
cparata	0:6d69e896ce38	3848	*/
cparata	0:6d69e896ce38	3849	int32_t lsm6dso_pin_polarity_set(lsm6dso_ctx_t *ctx, lsm6dso_h_lactive_t val)
cparata	0:6d69e896ce38	3850	{
cparata	3:4274d9103f1d	3851	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	3852	int32_t ret;
cparata	3:4274d9103f1d	3853
cparata	3:4274d9103f1d	3854	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3855	if (ret == 0) {
cparata	3:4274d9103f1d	3856	reg.h_lactive = (uint8_t)val;
cparata	3:4274d9103f1d	3857	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3858	}
cparata	3:4274d9103f1d	3859
cparata	3:4274d9103f1d	3860	return ret;
cparata	0:6d69e896ce38	3861	}
cparata	0:6d69e896ce38	3862
cparata	0:6d69e896ce38	3863	/**
cparata	0:6d69e896ce38	3864	* @brief Interrupt active-high/low.[get]
cparata	0:6d69e896ce38	3865	*
cparata	0:6d69e896ce38	3866	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3867	* @param val Get the values of h_lactive in reg CTRL3_C
cparata	0:6d69e896ce38	3868	*
cparata	0:6d69e896ce38	3869	*/
cparata	0:6d69e896ce38	3870	int32_t lsm6dso_pin_polarity_get(lsm6dso_ctx_t ctx, lsm6dso_h_lactive_t val)
cparata	0:6d69e896ce38	3871	{
cparata	3:4274d9103f1d	3872	lsm6dso_ctrl3_c_t reg;
cparata	3:4274d9103f1d	3873	int32_t ret;
cparata	3:4274d9103f1d	3874
cparata	3:4274d9103f1d	3875	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3876
cparata	3:4274d9103f1d	3877	switch (reg.h_lactive) {
cparata	3:4274d9103f1d	3878	case LSM6DSO_ACTIVE_HIGH:
cparata	3:4274d9103f1d	3879	*val = LSM6DSO_ACTIVE_HIGH;
cparata	3:4274d9103f1d	3880	break;
cparata	3:4274d9103f1d	3881	case LSM6DSO_ACTIVE_LOW:
cparata	3:4274d9103f1d	3882	*val = LSM6DSO_ACTIVE_LOW;
cparata	3:4274d9103f1d	3883	break;
cparata	3:4274d9103f1d	3884	default:
cparata	3:4274d9103f1d	3885	*val = LSM6DSO_ACTIVE_HIGH;
cparata	3:4274d9103f1d	3886	break;
cparata	3:4274d9103f1d	3887	}
cparata	3:4274d9103f1d	3888	return ret;
cparata	0:6d69e896ce38	3889	}
cparata	0:6d69e896ce38	3890
cparata	0:6d69e896ce38	3891	/**
cparata	0:6d69e896ce38	3892	* @brief All interrupt signals become available on INT1 pin.[set]
cparata	0:6d69e896ce38	3893	*
cparata	0:6d69e896ce38	3894	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3895	* @param val change the values of int2_on_int1 in reg CTRL4_C
cparata	0:6d69e896ce38	3896	*
cparata	0:6d69e896ce38	3897	*/
cparata	0:6d69e896ce38	3898	int32_t lsm6dso_all_on_int1_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	3899	{
cparata	3:4274d9103f1d	3900	lsm6dso_ctrl4_c_t reg;
cparata	3:4274d9103f1d	3901	int32_t ret;
cparata	3:4274d9103f1d	3902
cparata	3:4274d9103f1d	3903	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3904	if (ret == 0) {
cparata	3:4274d9103f1d	3905	reg.int2_on_int1 = val;
cparata	3:4274d9103f1d	3906	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3907	}
cparata	3:4274d9103f1d	3908
cparata	3:4274d9103f1d	3909	return ret;
cparata	0:6d69e896ce38	3910	}
cparata	0:6d69e896ce38	3911
cparata	0:6d69e896ce38	3912	/**
cparata	0:6d69e896ce38	3913	* @brief All interrupt signals become available on INT1 pin.[get]
cparata	0:6d69e896ce38	3914	*
cparata	0:6d69e896ce38	3915	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3916	* @param val change the values of int2_on_int1 in reg CTRL4_C
cparata	0:6d69e896ce38	3917	*
cparata	0:6d69e896ce38	3918	*/
cparata	0:6d69e896ce38	3919	int32_t lsm6dso_all_on_int1_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	3920	{
cparata	3:4274d9103f1d	3921	lsm6dso_ctrl4_c_t reg;
cparata	3:4274d9103f1d	3922	int32_t ret;
cparata	3:4274d9103f1d	3923
cparata	3:4274d9103f1d	3924	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	3925	*val = reg.int2_on_int1;
cparata	3:4274d9103f1d	3926
cparata	3:4274d9103f1d	3927	return ret;
cparata	0:6d69e896ce38	3928	}
cparata	0:6d69e896ce38	3929
cparata	0:6d69e896ce38	3930	/**
cparata	0:6d69e896ce38	3931	* @brief Interrupt notification mode.[set]
cparata	0:6d69e896ce38	3932	*
cparata	0:6d69e896ce38	3933	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3934	* @param val change the values of lir in reg TAP_CFG0
cparata	0:6d69e896ce38	3935	*
cparata	0:6d69e896ce38	3936	*/
cparata	0:6d69e896ce38	3937	int32_t lsm6dso_int_notification_set(lsm6dso_ctx_t *ctx, lsm6dso_lir_t val)
cparata	0:6d69e896ce38	3938	{
cparata	3:4274d9103f1d	3939	lsm6dso_tap_cfg0_t tap_cfg0;
cparata	3:4274d9103f1d	3940	lsm6dso_page_rw_t page_rw;
cparata	3:4274d9103f1d	3941	int32_t ret;
cparata	3:4274d9103f1d	3942
cparata	3:4274d9103f1d	3943	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
cparata	3:4274d9103f1d	3944	if (ret == 0) {
cparata	3:4274d9103f1d	3945	tap_cfg0.lir = (uint8_t)val & 0x01U;
cparata	3:4274d9103f1d	3946	tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
cparata	3:4274d9103f1d	3947	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
cparata	3:4274d9103f1d	3948	}
cparata	3:4274d9103f1d	3949	if (ret == 0) {
cparata	3:4274d9103f1d	3950
cparata	3:4274d9103f1d	3951	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	3952	}
cparata	3:4274d9103f1d	3953	if (ret == 0) {
cparata	3:4274d9103f1d	3954	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	3955	}
cparata	3:4274d9103f1d	3956	if (ret == 0) {
cparata	3:4274d9103f1d	3957	page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
cparata	3:4274d9103f1d	3958	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	3959	}
cparata	3:4274d9103f1d	3960	if (ret == 0) {
cparata	3:4274d9103f1d	3961	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	3962	}
cparata	3:4274d9103f1d	3963
cparata	3:4274d9103f1d	3964	return ret;
cparata	0:6d69e896ce38	3965	}
cparata	0:6d69e896ce38	3966
cparata	0:6d69e896ce38	3967	/**
cparata	0:6d69e896ce38	3968	* @brief Interrupt notification mode.[get]
cparata	0:6d69e896ce38	3969	*
cparata	0:6d69e896ce38	3970	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3971	* @param val Get the values of lir in reg TAP_CFG0
cparata	0:6d69e896ce38	3972	*
cparata	0:6d69e896ce38	3973	*/
cparata	0:6d69e896ce38	3974	int32_t lsm6dso_int_notification_get(lsm6dso_ctx_t ctx, lsm6dso_lir_t val)
cparata	0:6d69e896ce38	3975	{
cparata	3:4274d9103f1d	3976	lsm6dso_tap_cfg0_t tap_cfg0;
cparata	3:4274d9103f1d	3977	lsm6dso_page_rw_t page_rw;
cparata	3:4274d9103f1d	3978	int32_t ret;
cparata	3:4274d9103f1d	3979
cparata	3:4274d9103f1d	3980
cparata	3:4274d9103f1d	3981	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
cparata	3:4274d9103f1d	3982	if (ret == 0) {
cparata	3:4274d9103f1d	3983
cparata	3:4274d9103f1d	3984	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	3985	}
cparata	3:4274d9103f1d	3986	if (ret == 0) {
cparata	3:4274d9103f1d	3987	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	3988	}
cparata	3:4274d9103f1d	3989	if (ret == 0) {
cparata	3:4274d9103f1d	3990	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	3991	}
cparata	3:4274d9103f1d	3992	if (ret == 0) {
cparata	3:4274d9103f1d	3993	switch ((page_rw.emb_func_lir << 1) \| tap_cfg0.lir) {
cparata	3:4274d9103f1d	3994	case LSM6DSO_ALL_INT_PULSED:
cparata	3:4274d9103f1d	3995	*val = LSM6DSO_ALL_INT_PULSED;
cparata	3:4274d9103f1d	3996	break;
cparata	3:4274d9103f1d	3997	case LSM6DSO_BASE_LATCHED_EMB_PULSED:
cparata	3:4274d9103f1d	3998	*val = LSM6DSO_BASE_LATCHED_EMB_PULSED;
cparata	3:4274d9103f1d	3999	break;
cparata	3:4274d9103f1d	4000	case LSM6DSO_BASE_PULSED_EMB_LATCHED:
cparata	3:4274d9103f1d	4001	*val = LSM6DSO_BASE_PULSED_EMB_LATCHED;
cparata	3:4274d9103f1d	4002	break;
cparata	3:4274d9103f1d	4003	case LSM6DSO_ALL_INT_LATCHED:
cparata	3:4274d9103f1d	4004	*val = LSM6DSO_ALL_INT_LATCHED;
cparata	3:4274d9103f1d	4005	break;
cparata	3:4274d9103f1d	4006	default:
cparata	3:4274d9103f1d	4007	*val = LSM6DSO_ALL_INT_PULSED;
cparata	3:4274d9103f1d	4008	break;
cparata	3:4274d9103f1d	4009	}
cparata	3:4274d9103f1d	4010	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	4011	}
cparata	3:4274d9103f1d	4012	if (ret == 0) {
cparata	3:4274d9103f1d	4013	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
cparata	3:4274d9103f1d	4014	}
cparata	3:4274d9103f1d	4015	if (ret == 0) {
cparata	3:4274d9103f1d	4016	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	4017	}
cparata	3:4274d9103f1d	4018
cparata	3:4274d9103f1d	4019	return ret;
cparata	0:6d69e896ce38	4020	}
cparata	0:6d69e896ce38	4021
cparata	0:6d69e896ce38	4022	/**
cparata	0:6d69e896ce38	4023	* @}
cparata	0:6d69e896ce38	4024	*
cparata	0:6d69e896ce38	4025	*/
cparata	0:6d69e896ce38	4026
cparata	0:6d69e896ce38	4027	/**
cparata	0:6d69e896ce38	4028	* @defgroup LSM6DSO_Wake_Up_event
cparata	0:6d69e896ce38	4029	* @brief This section groups all the functions that manage the Wake Up
cparata	0:6d69e896ce38	4030	* event generation.
cparata	0:6d69e896ce38	4031	* @{
cparata	0:6d69e896ce38	4032	*
cparata	0:6d69e896ce38	4033	*/
cparata	0:6d69e896ce38	4034
cparata	0:6d69e896ce38	4035	/**
cparata	0:6d69e896ce38	4036	* @brief Weight of 1 LSB of wakeup threshold.[set]
cparata	0:6d69e896ce38	4037	* 0: 1 LSB =FS_XL / 64
cparata	0:6d69e896ce38	4038	* 1: 1 LSB = FS_XL / 256
cparata	0:6d69e896ce38	4039	*
cparata	0:6d69e896ce38	4040	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4041	* @param val change the values of wake_ths_w in
cparata	0:6d69e896ce38	4042	* reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4043	*
cparata	0:6d69e896ce38	4044	*/
cparata	0:6d69e896ce38	4045	int32_t lsm6dso_wkup_ths_weight_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4046	lsm6dso_wake_ths_w_t val)
cparata	0:6d69e896ce38	4047	{
cparata	3:4274d9103f1d	4048	lsm6dso_wake_up_dur_t reg;
cparata	3:4274d9103f1d	4049	int32_t ret;
cparata	3:4274d9103f1d	4050
cparata	3:4274d9103f1d	4051	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4052	if (ret == 0) {
cparata	3:4274d9103f1d	4053	reg.wake_ths_w = (uint8_t)val;
cparata	3:4274d9103f1d	4054	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4055	}
cparata	3:4274d9103f1d	4056	return ret;
cparata	0:6d69e896ce38	4057	}
cparata	0:6d69e896ce38	4058
cparata	0:6d69e896ce38	4059	/**
cparata	0:6d69e896ce38	4060	* @brief Weight of 1 LSB of wakeup threshold.[get]
cparata	0:6d69e896ce38	4061	* 0: 1 LSB =FS_XL / 64
cparata	0:6d69e896ce38	4062	* 1: 1 LSB = FS_XL / 256
cparata	0:6d69e896ce38	4063	*
cparata	0:6d69e896ce38	4064	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4065	* @param val Get the values of wake_ths_w in
cparata	0:6d69e896ce38	4066	* reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4067	*
cparata	0:6d69e896ce38	4068	*/
cparata	0:6d69e896ce38	4069	int32_t lsm6dso_wkup_ths_weight_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4070	lsm6dso_wake_ths_w_t *val)
cparata	0:6d69e896ce38	4071	{
cparata	3:4274d9103f1d	4072	lsm6dso_wake_up_dur_t reg;
cparata	3:4274d9103f1d	4073	int32_t ret;
cparata	3:4274d9103f1d	4074
cparata	3:4274d9103f1d	4075	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4076
cparata	3:4274d9103f1d	4077	switch (reg.wake_ths_w) {
cparata	3:4274d9103f1d	4078	case LSM6DSO_LSb_FS_DIV_64:
cparata	3:4274d9103f1d	4079	*val = LSM6DSO_LSb_FS_DIV_64;
cparata	3:4274d9103f1d	4080	break;
cparata	3:4274d9103f1d	4081	case LSM6DSO_LSb_FS_DIV_256:
cparata	3:4274d9103f1d	4082	*val = LSM6DSO_LSb_FS_DIV_256;
cparata	3:4274d9103f1d	4083	break;
cparata	3:4274d9103f1d	4084	default:
cparata	3:4274d9103f1d	4085	*val = LSM6DSO_LSb_FS_DIV_64;
cparata	3:4274d9103f1d	4086	break;
cparata	3:4274d9103f1d	4087	}
cparata	3:4274d9103f1d	4088	return ret;
cparata	0:6d69e896ce38	4089	}
cparata	0:6d69e896ce38	4090
cparata	0:6d69e896ce38	4091	/**
cparata	0:6d69e896ce38	4092	* @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
cparata	0:6d69e896ce38	4093	* WAKE_UP_DUR.[set]
cparata	0:6d69e896ce38	4094	*
cparata	0:6d69e896ce38	4095	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4096	* @param val change the values of wk_ths in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4097	*
cparata	0:6d69e896ce38	4098	*/
cparata	0:6d69e896ce38	4099	int32_t lsm6dso_wkup_threshold_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4100	{
cparata	3:4274d9103f1d	4101	lsm6dso_wake_up_ths_t reg;
cparata	3:4274d9103f1d	4102	int32_t ret;
cparata	3:4274d9103f1d	4103
cparata	3:4274d9103f1d	4104	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4105	if (ret == 0) {
cparata	3:4274d9103f1d	4106	reg.wk_ths = val;
cparata	3:4274d9103f1d	4107	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4108	}
cparata	3:4274d9103f1d	4109	return ret;
cparata	0:6d69e896ce38	4110	}
cparata	0:6d69e896ce38	4111
cparata	0:6d69e896ce38	4112	/**
cparata	0:6d69e896ce38	4113	* @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
cparata	0:6d69e896ce38	4114	* WAKE_UP_DUR.[get]
cparata	0:6d69e896ce38	4115	*
cparata	0:6d69e896ce38	4116	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4117	* @param val change the values of wk_ths in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4118	*
cparata	0:6d69e896ce38	4119	*/
cparata	0:6d69e896ce38	4120	int32_t lsm6dso_wkup_threshold_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4121	{
cparata	3:4274d9103f1d	4122	lsm6dso_wake_up_ths_t reg;
cparata	3:4274d9103f1d	4123	int32_t ret;
cparata	3:4274d9103f1d	4124
cparata	3:4274d9103f1d	4125	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4126	*val = reg.wk_ths;
cparata	3:4274d9103f1d	4127
cparata	3:4274d9103f1d	4128	return ret;
cparata	0:6d69e896ce38	4129	}
cparata	0:6d69e896ce38	4130
cparata	0:6d69e896ce38	4131	/**
cparata	0:6d69e896ce38	4132	* @brief Wake up duration event.[set]
cparata	0:6d69e896ce38	4133	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	4134	*
cparata	0:6d69e896ce38	4135	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4136	* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4137	*
cparata	0:6d69e896ce38	4138	*/
cparata	0:6d69e896ce38	4139	int32_t lsm6dso_xl_usr_offset_on_wkup_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4140	{
cparata	3:4274d9103f1d	4141	lsm6dso_wake_up_ths_t reg;
cparata	3:4274d9103f1d	4142	int32_t ret;
cparata	3:4274d9103f1d	4143
cparata	3:4274d9103f1d	4144	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4145	if (ret == 0) {
cparata	3:4274d9103f1d	4146	reg.usr_off_on_wu = val;
cparata	3:4274d9103f1d	4147	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4148	}
cparata	3:4274d9103f1d	4149	return ret;
cparata	0:6d69e896ce38	4150	}
cparata	0:6d69e896ce38	4151
cparata	0:6d69e896ce38	4152	/**
cparata	0:6d69e896ce38	4153	* @brief Wake up duration event.[get]
cparata	0:6d69e896ce38	4154	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	4155	*
cparata	0:6d69e896ce38	4156	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4157	* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4158	*
cparata	0:6d69e896ce38	4159	*/
cparata	0:6d69e896ce38	4160	int32_t lsm6dso_xl_usr_offset_on_wkup_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4161	{
cparata	3:4274d9103f1d	4162	lsm6dso_wake_up_ths_t reg;
cparata	3:4274d9103f1d	4163	int32_t ret;
cparata	3:4274d9103f1d	4164
cparata	3:4274d9103f1d	4165	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4166	*val = reg.usr_off_on_wu;
cparata	3:4274d9103f1d	4167
cparata	3:4274d9103f1d	4168	return ret;
cparata	0:6d69e896ce38	4169	}
cparata	0:6d69e896ce38	4170
cparata	0:6d69e896ce38	4171	/**
cparata	0:6d69e896ce38	4172	* @brief Wake up duration event.[set]
cparata	0:6d69e896ce38	4173	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	4174	*
cparata	0:6d69e896ce38	4175	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4176	* @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4177	*
cparata	0:6d69e896ce38	4178	*/
cparata	0:6d69e896ce38	4179	int32_t lsm6dso_wkup_dur_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4180	{
cparata	3:4274d9103f1d	4181	lsm6dso_wake_up_dur_t reg;
cparata	3:4274d9103f1d	4182	int32_t ret;
cparata	3:4274d9103f1d	4183
cparata	3:4274d9103f1d	4184	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4185	if (ret == 0) {
cparata	3:4274d9103f1d	4186	reg.wake_dur = val;
cparata	3:4274d9103f1d	4187	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4188	}
cparata	3:4274d9103f1d	4189	return ret;
cparata	0:6d69e896ce38	4190	}
cparata	0:6d69e896ce38	4191
cparata	0:6d69e896ce38	4192	/**
cparata	0:6d69e896ce38	4193	* @brief Wake up duration event.[get]
cparata	0:6d69e896ce38	4194	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	4195	*
cparata	0:6d69e896ce38	4196	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4197	* @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4198	*
cparata	0:6d69e896ce38	4199	*/
cparata	0:6d69e896ce38	4200	int32_t lsm6dso_wkup_dur_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4201	{
cparata	3:4274d9103f1d	4202	lsm6dso_wake_up_dur_t reg;
cparata	3:4274d9103f1d	4203	int32_t ret;
cparata	3:4274d9103f1d	4204
cparata	3:4274d9103f1d	4205	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4206	*val = reg.wake_dur;
cparata	3:4274d9103f1d	4207
cparata	3:4274d9103f1d	4208	return ret;
cparata	0:6d69e896ce38	4209	}
cparata	0:6d69e896ce38	4210
cparata	0:6d69e896ce38	4211	/**
cparata	0:6d69e896ce38	4212	* @}
cparata	0:6d69e896ce38	4213	*
cparata	0:6d69e896ce38	4214	*/
cparata	0:6d69e896ce38	4215
cparata	0:6d69e896ce38	4216	/**
cparata	0:6d69e896ce38	4217	* @defgroup LSM6DSO_ Activity/Inactivity_detection
cparata	0:6d69e896ce38	4218	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	4219	* activity/inactivity detection.
cparata	0:6d69e896ce38	4220	* @{
cparata	0:6d69e896ce38	4221	*
cparata	0:6d69e896ce38	4222	*/
cparata	0:6d69e896ce38	4223
cparata	0:6d69e896ce38	4224	/**
cparata	0:6d69e896ce38	4225	* @brief Enables gyroscope Sleep mode.[set]
cparata	0:6d69e896ce38	4226	*
cparata	0:6d69e896ce38	4227	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4228	* @param val change the values of sleep_g in reg CTRL4_C
cparata	0:6d69e896ce38	4229	*
cparata	0:6d69e896ce38	4230	*/
cparata	0:6d69e896ce38	4231	int32_t lsm6dso_gy_sleep_mode_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4232	{
cparata	3:4274d9103f1d	4233	lsm6dso_ctrl4_c_t reg;
cparata	3:4274d9103f1d	4234	int32_t ret;
cparata	3:4274d9103f1d	4235
cparata	3:4274d9103f1d	4236	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4237	if (ret == 0) {
cparata	3:4274d9103f1d	4238	reg.sleep_g = val;
cparata	3:4274d9103f1d	4239	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4240	}
cparata	3:4274d9103f1d	4241	return ret;
cparata	0:6d69e896ce38	4242	}
cparata	0:6d69e896ce38	4243
cparata	0:6d69e896ce38	4244	/**
cparata	0:6d69e896ce38	4245	* @brief Enables gyroscope Sleep mode.[get]
cparata	0:6d69e896ce38	4246	*
cparata	0:6d69e896ce38	4247	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4248	* @param val change the values of sleep_g in reg CTRL4_C
cparata	0:6d69e896ce38	4249	*
cparata	0:6d69e896ce38	4250	*/
cparata	0:6d69e896ce38	4251	int32_t lsm6dso_gy_sleep_mode_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4252	{
cparata	3:4274d9103f1d	4253	lsm6dso_ctrl4_c_t reg;
cparata	3:4274d9103f1d	4254	int32_t ret;
cparata	3:4274d9103f1d	4255
cparata	3:4274d9103f1d	4256	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4257	*val = reg.sleep_g;
cparata	3:4274d9103f1d	4258
cparata	3:4274d9103f1d	4259	return ret;
cparata	0:6d69e896ce38	4260	}
cparata	0:6d69e896ce38	4261
cparata	0:6d69e896ce38	4262	/**
cparata	0:6d69e896ce38	4263	* @brief Drives the sleep status instead of
cparata	0:6d69e896ce38	4264	* sleep change on INT pins
cparata	0:6d69e896ce38	4265	* (only if INT1_SLEEP_CHANGE or
cparata	0:6d69e896ce38	4266	* INT2_SLEEP_CHANGE bits are enabled).[set]
cparata	0:6d69e896ce38	4267	*
cparata	0:6d69e896ce38	4268	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4269	* @param val change the values of sleep_status_on_int in reg TAP_CFG0
cparata	0:6d69e896ce38	4270	*
cparata	0:6d69e896ce38	4271	*/
cparata	0:6d69e896ce38	4272	int32_t lsm6dso_act_pin_notification_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4273	lsm6dso_sleep_status_on_int_t val)
cparata	0:6d69e896ce38	4274	{
cparata	3:4274d9103f1d	4275	lsm6dso_tap_cfg0_t reg;
cparata	3:4274d9103f1d	4276	int32_t ret;
cparata	3:4274d9103f1d	4277
cparata	3:4274d9103f1d	4278	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4279	if (ret == 0) {
cparata	3:4274d9103f1d	4280	reg.sleep_status_on_int = (uint8_t)val;
cparata	3:4274d9103f1d	4281	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4282	}
cparata	3:4274d9103f1d	4283	return ret;
cparata	0:6d69e896ce38	4284	}
cparata	0:6d69e896ce38	4285
cparata	0:6d69e896ce38	4286	/**
cparata	0:6d69e896ce38	4287	* @brief Drives the sleep status instead of
cparata	0:6d69e896ce38	4288	* sleep change on INT pins (only if
cparata	0:6d69e896ce38	4289	* INT1_SLEEP_CHANGE or
cparata	0:6d69e896ce38	4290	* INT2_SLEEP_CHANGE bits are enabled).[get]
cparata	0:6d69e896ce38	4291	*
cparata	0:6d69e896ce38	4292	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4293	* @param val Get the values of sleep_status_on_int in reg TAP_CFG0
cparata	0:6d69e896ce38	4294	*
cparata	0:6d69e896ce38	4295	*/
cparata	0:6d69e896ce38	4296	int32_t lsm6dso_act_pin_notification_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4297	lsm6dso_sleep_status_on_int_t *val)
cparata	0:6d69e896ce38	4298	{
cparata	3:4274d9103f1d	4299	lsm6dso_tap_cfg0_t reg;
cparata	3:4274d9103f1d	4300	int32_t ret;
cparata	3:4274d9103f1d	4301
cparata	3:4274d9103f1d	4302	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4303	switch (reg.sleep_status_on_int) {
cparata	3:4274d9103f1d	4304	case LSM6DSO_DRIVE_SLEEP_CHG_EVENT:
cparata	3:4274d9103f1d	4305	*val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
cparata	3:4274d9103f1d	4306	break;
cparata	3:4274d9103f1d	4307	case LSM6DSO_DRIVE_SLEEP_STATUS:
cparata	3:4274d9103f1d	4308	*val = LSM6DSO_DRIVE_SLEEP_STATUS;
cparata	3:4274d9103f1d	4309	break;
cparata	3:4274d9103f1d	4310	default:
cparata	3:4274d9103f1d	4311	*val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
cparata	3:4274d9103f1d	4312	break;
cparata	3:4274d9103f1d	4313	}
cparata	3:4274d9103f1d	4314	return ret;
cparata	0:6d69e896ce38	4315	}
cparata	0:6d69e896ce38	4316
cparata	0:6d69e896ce38	4317	/**
cparata	0:6d69e896ce38	4318	* @brief Enable inactivity function.[set]
cparata	0:6d69e896ce38	4319	*
cparata	0:6d69e896ce38	4320	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4321	* @param val change the values of inact_en in reg TAP_CFG2
cparata	0:6d69e896ce38	4322	*
cparata	0:6d69e896ce38	4323	*/
cparata	0:6d69e896ce38	4324	int32_t lsm6dso_act_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_inact_en_t val)
cparata	0:6d69e896ce38	4325	{
cparata	3:4274d9103f1d	4326	lsm6dso_tap_cfg2_t reg;
cparata	3:4274d9103f1d	4327	int32_t ret;
cparata	3:4274d9103f1d	4328
cparata	3:4274d9103f1d	4329	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4330	if (ret == 0) {
cparata	3:4274d9103f1d	4331	reg.inact_en = (uint8_t)val;
cparata	3:4274d9103f1d	4332	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4333	}
cparata	3:4274d9103f1d	4334	return ret;
cparata	0:6d69e896ce38	4335	}
cparata	0:6d69e896ce38	4336
cparata	0:6d69e896ce38	4337	/**
cparata	0:6d69e896ce38	4338	* @brief Enable inactivity function.[get]
cparata	0:6d69e896ce38	4339	*
cparata	0:6d69e896ce38	4340	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4341	* @param val Get the values of inact_en in reg TAP_CFG2
cparata	0:6d69e896ce38	4342	*
cparata	0:6d69e896ce38	4343	*/
cparata	0:6d69e896ce38	4344	int32_t lsm6dso_act_mode_get(lsm6dso_ctx_t ctx, lsm6dso_inact_en_t val)
cparata	0:6d69e896ce38	4345	{
cparata	3:4274d9103f1d	4346	lsm6dso_tap_cfg2_t reg;
cparata	3:4274d9103f1d	4347	int32_t ret;
cparata	3:4274d9103f1d	4348
cparata	3:4274d9103f1d	4349	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4350	switch (reg.inact_en) {
cparata	3:4274d9103f1d	4351	case LSM6DSO_XL_AND_GY_NOT_AFFECTED:
cparata	3:4274d9103f1d	4352	*val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
cparata	3:4274d9103f1d	4353	break;
cparata	3:4274d9103f1d	4354	case LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED:
cparata	3:4274d9103f1d	4355	*val = LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED;
cparata	3:4274d9103f1d	4356	break;
cparata	3:4274d9103f1d	4357	case LSM6DSO_XL_12Hz5_GY_SLEEP:
cparata	3:4274d9103f1d	4358	*val = LSM6DSO_XL_12Hz5_GY_SLEEP;
cparata	3:4274d9103f1d	4359	break;
cparata	3:4274d9103f1d	4360	case LSM6DSO_XL_12Hz5_GY_PD:
cparata	3:4274d9103f1d	4361	*val = LSM6DSO_XL_12Hz5_GY_PD;
cparata	3:4274d9103f1d	4362	break;
cparata	3:4274d9103f1d	4363	default:
cparata	3:4274d9103f1d	4364	*val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
cparata	3:4274d9103f1d	4365	break;
cparata	3:4274d9103f1d	4366	}
cparata	3:4274d9103f1d	4367	return ret;
cparata	0:6d69e896ce38	4368	}
cparata	0:6d69e896ce38	4369
cparata	0:6d69e896ce38	4370	/**
cparata	0:6d69e896ce38	4371	* @brief Duration to go in sleep mode.[set]
cparata	0:6d69e896ce38	4372	* 1 LSb = 512 / ODR
cparata	0:6d69e896ce38	4373	*
cparata	0:6d69e896ce38	4374	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4375	* @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4376	*
cparata	0:6d69e896ce38	4377	*/
cparata	0:6d69e896ce38	4378	int32_t lsm6dso_act_sleep_dur_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4379	{
cparata	3:4274d9103f1d	4380	lsm6dso_wake_up_dur_t reg;
cparata	3:4274d9103f1d	4381	int32_t ret;
cparata	3:4274d9103f1d	4382
cparata	3:4274d9103f1d	4383	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4384	if (ret == 0) {
cparata	3:4274d9103f1d	4385	reg.sleep_dur = val;
cparata	3:4274d9103f1d	4386	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4387	}
cparata	3:4274d9103f1d	4388	return ret;
cparata	0:6d69e896ce38	4389	}
cparata	0:6d69e896ce38	4390
cparata	0:6d69e896ce38	4391	/**
cparata	0:6d69e896ce38	4392	* @brief Duration to go in sleep mode.[get]
cparata	0:6d69e896ce38	4393	* 1 LSb = 512 / ODR
cparata	0:6d69e896ce38	4394	*
cparata	0:6d69e896ce38	4395	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4396	* @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4397	*
cparata	0:6d69e896ce38	4398	*/
cparata	0:6d69e896ce38	4399	int32_t lsm6dso_act_sleep_dur_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4400	{
cparata	3:4274d9103f1d	4401	lsm6dso_wake_up_dur_t reg;
cparata	3:4274d9103f1d	4402	int32_t ret;
cparata	3:4274d9103f1d	4403
cparata	3:4274d9103f1d	4404	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4405	*val = reg.sleep_dur;
cparata	3:4274d9103f1d	4406
cparata	3:4274d9103f1d	4407	return ret;
cparata	0:6d69e896ce38	4408	}
cparata	0:6d69e896ce38	4409
cparata	0:6d69e896ce38	4410	/**
cparata	0:6d69e896ce38	4411	* @}
cparata	0:6d69e896ce38	4412	*
cparata	0:6d69e896ce38	4413	*/
cparata	0:6d69e896ce38	4414
cparata	0:6d69e896ce38	4415	/**
cparata	0:6d69e896ce38	4416	* @defgroup LSM6DSO_tap_generator
cparata	0:6d69e896ce38	4417	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	4418	* tap and double tap event generation.
cparata	0:6d69e896ce38	4419	* @{
cparata	0:6d69e896ce38	4420	*
cparata	0:6d69e896ce38	4421	*/
cparata	0:6d69e896ce38	4422
cparata	0:6d69e896ce38	4423	/**
cparata	0:6d69e896ce38	4424	* @brief Enable Z direction in tap recognition.[set]
cparata	0:6d69e896ce38	4425	*
cparata	0:6d69e896ce38	4426	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4427	* @param val change the values of tap_z_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4428	*
cparata	0:6d69e896ce38	4429	*/
cparata	0:6d69e896ce38	4430	int32_t lsm6dso_tap_detection_on_z_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4431	{
cparata	3:4274d9103f1d	4432	lsm6dso_tap_cfg0_t reg;
cparata	3:4274d9103f1d	4433	int32_t ret;
cparata	3:4274d9103f1d	4434
cparata	3:4274d9103f1d	4435	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4436	if (ret == 0) {
cparata	3:4274d9103f1d	4437	reg.tap_z_en = val;
cparata	3:4274d9103f1d	4438	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4439	}
cparata	3:4274d9103f1d	4440	return ret;
cparata	0:6d69e896ce38	4441	}
cparata	0:6d69e896ce38	4442
cparata	0:6d69e896ce38	4443	/**
cparata	0:6d69e896ce38	4444	* @brief Enable Z direction in tap recognition.[get]
cparata	0:6d69e896ce38	4445	*
cparata	0:6d69e896ce38	4446	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4447	* @param val change the values of tap_z_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4448	*
cparata	0:6d69e896ce38	4449	*/
cparata	0:6d69e896ce38	4450	int32_t lsm6dso_tap_detection_on_z_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4451	{
cparata	3:4274d9103f1d	4452	lsm6dso_tap_cfg0_t reg;
cparata	3:4274d9103f1d	4453	int32_t ret;
cparata	3:4274d9103f1d	4454
cparata	3:4274d9103f1d	4455	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4456	*val = reg.tap_z_en;
cparata	3:4274d9103f1d	4457
cparata	3:4274d9103f1d	4458	return ret;
cparata	0:6d69e896ce38	4459	}
cparata	0:6d69e896ce38	4460
cparata	0:6d69e896ce38	4461	/**
cparata	0:6d69e896ce38	4462	* @brief Enable Y direction in tap recognition.[set]
cparata	0:6d69e896ce38	4463	*
cparata	0:6d69e896ce38	4464	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4465	* @param val change the values of tap_y_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4466	*
cparata	0:6d69e896ce38	4467	*/
cparata	0:6d69e896ce38	4468	int32_t lsm6dso_tap_detection_on_y_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4469	{
cparata	3:4274d9103f1d	4470	lsm6dso_tap_cfg0_t reg;
cparata	3:4274d9103f1d	4471	int32_t ret;
cparata	3:4274d9103f1d	4472
cparata	3:4274d9103f1d	4473	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4474	if (ret == 0) {
cparata	3:4274d9103f1d	4475	reg.tap_y_en = val;
cparata	3:4274d9103f1d	4476	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4477	}
cparata	3:4274d9103f1d	4478	return ret;
cparata	0:6d69e896ce38	4479	}
cparata	0:6d69e896ce38	4480
cparata	0:6d69e896ce38	4481	/**
cparata	0:6d69e896ce38	4482	* @brief Enable Y direction in tap recognition.[get]
cparata	0:6d69e896ce38	4483	*
cparata	0:6d69e896ce38	4484	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4485	* @param val change the values of tap_y_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4486	*
cparata	0:6d69e896ce38	4487	*/
cparata	0:6d69e896ce38	4488	int32_t lsm6dso_tap_detection_on_y_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4489	{
cparata	3:4274d9103f1d	4490	lsm6dso_tap_cfg0_t reg;
cparata	3:4274d9103f1d	4491	int32_t ret;
cparata	3:4274d9103f1d	4492
cparata	3:4274d9103f1d	4493	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4494	*val = reg.tap_y_en;
cparata	3:4274d9103f1d	4495
cparata	3:4274d9103f1d	4496	return ret;
cparata	0:6d69e896ce38	4497	}
cparata	0:6d69e896ce38	4498
cparata	0:6d69e896ce38	4499	/**
cparata	0:6d69e896ce38	4500	* @brief Enable X direction in tap recognition.[set]
cparata	0:6d69e896ce38	4501	*
cparata	0:6d69e896ce38	4502	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4503	* @param val change the values of tap_x_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4504	*
cparata	0:6d69e896ce38	4505	*/
cparata	0:6d69e896ce38	4506	int32_t lsm6dso_tap_detection_on_x_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4507	{
cparata	3:4274d9103f1d	4508	lsm6dso_tap_cfg0_t reg;
cparata	3:4274d9103f1d	4509	int32_t ret;
cparata	3:4274d9103f1d	4510
cparata	3:4274d9103f1d	4511	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4512	if (ret == 0) {
cparata	3:4274d9103f1d	4513	reg.tap_x_en = val;
cparata	3:4274d9103f1d	4514	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4515	}
cparata	3:4274d9103f1d	4516	return ret;
cparata	0:6d69e896ce38	4517	}
cparata	0:6d69e896ce38	4518
cparata	0:6d69e896ce38	4519	/**
cparata	0:6d69e896ce38	4520	* @brief Enable X direction in tap recognition.[get]
cparata	0:6d69e896ce38	4521	*
cparata	0:6d69e896ce38	4522	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4523	* @param val change the values of tap_x_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4524	*
cparata	0:6d69e896ce38	4525	*/
cparata	0:6d69e896ce38	4526	int32_t lsm6dso_tap_detection_on_x_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4527	{
cparata	3:4274d9103f1d	4528	lsm6dso_tap_cfg0_t reg;
cparata	3:4274d9103f1d	4529	int32_t ret;
cparata	3:4274d9103f1d	4530
cparata	3:4274d9103f1d	4531	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4532	*val = reg.tap_x_en;
cparata	3:4274d9103f1d	4533
cparata	3:4274d9103f1d	4534	return ret;
cparata	0:6d69e896ce38	4535	}
cparata	0:6d69e896ce38	4536
cparata	0:6d69e896ce38	4537	/**
cparata	0:6d69e896ce38	4538	* @brief X-axis tap recognition threshold.[set]
cparata	0:6d69e896ce38	4539	*
cparata	0:6d69e896ce38	4540	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4541	* @param val change the values of tap_ths_x in reg TAP_CFG1
cparata	0:6d69e896ce38	4542	*
cparata	0:6d69e896ce38	4543	*/
cparata	0:6d69e896ce38	4544	int32_t lsm6dso_tap_threshold_x_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4545	{
cparata	3:4274d9103f1d	4546	lsm6dso_tap_cfg1_t reg;
cparata	3:4274d9103f1d	4547	int32_t ret;
cparata	3:4274d9103f1d	4548
cparata	3:4274d9103f1d	4549	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4550	if (ret == 0) {
cparata	3:4274d9103f1d	4551	reg.tap_ths_x = val;
cparata	3:4274d9103f1d	4552	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4553	}
cparata	3:4274d9103f1d	4554	return ret;
cparata	0:6d69e896ce38	4555	}
cparata	0:6d69e896ce38	4556
cparata	0:6d69e896ce38	4557	/**
cparata	0:6d69e896ce38	4558	* @brief X-axis tap recognition threshold.[get]
cparata	0:6d69e896ce38	4559	*
cparata	0:6d69e896ce38	4560	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4561	* @param val change the values of tap_ths_x in reg TAP_CFG1
cparata	0:6d69e896ce38	4562	*
cparata	0:6d69e896ce38	4563	*/
cparata	0:6d69e896ce38	4564	int32_t lsm6dso_tap_threshold_x_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4565	{
cparata	3:4274d9103f1d	4566	lsm6dso_tap_cfg1_t reg;
cparata	3:4274d9103f1d	4567	int32_t ret;
cparata	3:4274d9103f1d	4568
cparata	3:4274d9103f1d	4569	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4570	*val = reg.tap_ths_x;
cparata	3:4274d9103f1d	4571
cparata	3:4274d9103f1d	4572	return ret;
cparata	0:6d69e896ce38	4573	}
cparata	0:6d69e896ce38	4574
cparata	0:6d69e896ce38	4575	/**
cparata	0:6d69e896ce38	4576	* @brief Selection of axis priority for TAP detection.[set]
cparata	0:6d69e896ce38	4577	*
cparata	0:6d69e896ce38	4578	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4579	* @param val change the values of tap_priority in
cparata	0:6d69e896ce38	4580	* reg TAP_CFG1
cparata	0:6d69e896ce38	4581	*
cparata	0:6d69e896ce38	4582	*/
cparata	0:6d69e896ce38	4583	int32_t lsm6dso_tap_axis_priority_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4584	lsm6dso_tap_priority_t val)
cparata	0:6d69e896ce38	4585	{
cparata	3:4274d9103f1d	4586	lsm6dso_tap_cfg1_t reg;
cparata	3:4274d9103f1d	4587	int32_t ret;
cparata	3:4274d9103f1d	4588
cparata	3:4274d9103f1d	4589	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4590	if (ret == 0) {
cparata	3:4274d9103f1d	4591	reg.tap_priority = (uint8_t)val;
cparata	3:4274d9103f1d	4592	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4593	}
cparata	3:4274d9103f1d	4594	return ret;
cparata	0:6d69e896ce38	4595	}
cparata	0:6d69e896ce38	4596
cparata	0:6d69e896ce38	4597	/**
cparata	0:6d69e896ce38	4598	* @brief Selection of axis priority for TAP detection.[get]
cparata	0:6d69e896ce38	4599	*
cparata	0:6d69e896ce38	4600	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4601	* @param val Get the values of tap_priority in
cparata	0:6d69e896ce38	4602	* reg TAP_CFG1
cparata	0:6d69e896ce38	4603	*
cparata	0:6d69e896ce38	4604	*/
cparata	0:6d69e896ce38	4605	int32_t lsm6dso_tap_axis_priority_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4606	lsm6dso_tap_priority_t *val)
cparata	0:6d69e896ce38	4607	{
cparata	3:4274d9103f1d	4608	lsm6dso_tap_cfg1_t reg;
cparata	3:4274d9103f1d	4609	int32_t ret;
cparata	3:4274d9103f1d	4610
cparata	3:4274d9103f1d	4611	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4612	switch (reg.tap_priority) {
cparata	3:4274d9103f1d	4613	case LSM6DSO_XYZ:
cparata	3:4274d9103f1d	4614	*val = LSM6DSO_XYZ;
cparata	3:4274d9103f1d	4615	break;
cparata	3:4274d9103f1d	4616	case LSM6DSO_YXZ:
cparata	3:4274d9103f1d	4617	*val = LSM6DSO_YXZ;
cparata	3:4274d9103f1d	4618	break;
cparata	3:4274d9103f1d	4619	case LSM6DSO_XZY:
cparata	3:4274d9103f1d	4620	*val = LSM6DSO_XZY;
cparata	3:4274d9103f1d	4621	break;
cparata	3:4274d9103f1d	4622	case LSM6DSO_ZYX:
cparata	3:4274d9103f1d	4623	*val = LSM6DSO_ZYX;
cparata	3:4274d9103f1d	4624	break;
cparata	3:4274d9103f1d	4625	case LSM6DSO_YZX:
cparata	3:4274d9103f1d	4626	*val = LSM6DSO_YZX;
cparata	3:4274d9103f1d	4627	break;
cparata	3:4274d9103f1d	4628	case LSM6DSO_ZXY:
cparata	3:4274d9103f1d	4629	*val = LSM6DSO_ZXY;
cparata	3:4274d9103f1d	4630	break;
cparata	3:4274d9103f1d	4631	default:
cparata	3:4274d9103f1d	4632	*val = LSM6DSO_XYZ;
cparata	3:4274d9103f1d	4633	break;
cparata	3:4274d9103f1d	4634	}
cparata	3:4274d9103f1d	4635	return ret;
cparata	0:6d69e896ce38	4636	}
cparata	0:6d69e896ce38	4637
cparata	0:6d69e896ce38	4638	/**
cparata	0:6d69e896ce38	4639	* @brief Y-axis tap recognition threshold.[set]
cparata	0:6d69e896ce38	4640	*
cparata	0:6d69e896ce38	4641	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4642	* @param val change the values of tap_ths_y in reg TAP_CFG2
cparata	0:6d69e896ce38	4643	*
cparata	0:6d69e896ce38	4644	*/
cparata	0:6d69e896ce38	4645	int32_t lsm6dso_tap_threshold_y_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4646	{
cparata	3:4274d9103f1d	4647	lsm6dso_tap_cfg2_t reg;
cparata	3:4274d9103f1d	4648	int32_t ret;
cparata	3:4274d9103f1d	4649
cparata	3:4274d9103f1d	4650	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4651	if (ret == 0) {
cparata	3:4274d9103f1d	4652	reg.tap_ths_y = val;
cparata	3:4274d9103f1d	4653	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4654	}
cparata	3:4274d9103f1d	4655	return ret;
cparata	0:6d69e896ce38	4656	}
cparata	0:6d69e896ce38	4657
cparata	0:6d69e896ce38	4658	/**
cparata	0:6d69e896ce38	4659	* @brief Y-axis tap recognition threshold.[get]
cparata	0:6d69e896ce38	4660	*
cparata	0:6d69e896ce38	4661	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4662	* @param val change the values of tap_ths_y in reg TAP_CFG2
cparata	0:6d69e896ce38	4663	*
cparata	0:6d69e896ce38	4664	*/
cparata	0:6d69e896ce38	4665	int32_t lsm6dso_tap_threshold_y_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4666	{
cparata	3:4274d9103f1d	4667	lsm6dso_tap_cfg2_t reg;
cparata	3:4274d9103f1d	4668	int32_t ret;
cparata	3:4274d9103f1d	4669
cparata	3:4274d9103f1d	4670	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4671	*val = reg.tap_ths_y;
cparata	3:4274d9103f1d	4672
cparata	3:4274d9103f1d	4673	return ret;
cparata	0:6d69e896ce38	4674	}
cparata	0:6d69e896ce38	4675
cparata	0:6d69e896ce38	4676	/**
cparata	0:6d69e896ce38	4677	* @brief Z-axis recognition threshold.[set]
cparata	0:6d69e896ce38	4678	*
cparata	0:6d69e896ce38	4679	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4680	* @param val change the values of tap_ths_z in reg TAP_THS_6D
cparata	0:6d69e896ce38	4681	*
cparata	0:6d69e896ce38	4682	*/
cparata	0:6d69e896ce38	4683	int32_t lsm6dso_tap_threshold_z_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4684	{
cparata	3:4274d9103f1d	4685	lsm6dso_tap_ths_6d_t reg;
cparata	3:4274d9103f1d	4686	int32_t ret;
cparata	3:4274d9103f1d	4687
cparata	3:4274d9103f1d	4688	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4689	if (ret == 0) {
cparata	3:4274d9103f1d	4690	reg.tap_ths_z = val;
cparata	3:4274d9103f1d	4691	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4692	}
cparata	3:4274d9103f1d	4693	return ret;
cparata	0:6d69e896ce38	4694	}
cparata	0:6d69e896ce38	4695
cparata	0:6d69e896ce38	4696	/**
cparata	0:6d69e896ce38	4697	* @brief Z-axis recognition threshold.[get]
cparata	0:6d69e896ce38	4698	*
cparata	0:6d69e896ce38	4699	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4700	* @param val change the values of tap_ths_z in reg TAP_THS_6D
cparata	0:6d69e896ce38	4701	*
cparata	0:6d69e896ce38	4702	*/
cparata	0:6d69e896ce38	4703	int32_t lsm6dso_tap_threshold_z_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4704	{
cparata	3:4274d9103f1d	4705	lsm6dso_tap_ths_6d_t reg;
cparata	3:4274d9103f1d	4706	int32_t ret;
cparata	3:4274d9103f1d	4707
cparata	3:4274d9103f1d	4708	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4709	*val = reg.tap_ths_z;
cparata	3:4274d9103f1d	4710
cparata	3:4274d9103f1d	4711	return ret;
cparata	0:6d69e896ce38	4712	}
cparata	0:6d69e896ce38	4713
cparata	0:6d69e896ce38	4714	/**
cparata	0:6d69e896ce38	4715	* @brief Maximum duration is the maximum time of an
cparata	0:6d69e896ce38	4716	* over threshold signal detection to be recognized
cparata	0:6d69e896ce38	4717	* as a tap event. The default value of these bits
cparata	0:6d69e896ce38	4718	* is 00b which corresponds to 4*ODR_XL time.
cparata	0:6d69e896ce38	4719	* If the SHOCK[1:0] bits are set to a different
cparata	0:6d69e896ce38	4720	* value, 1LSB corresponds to 8*ODR_XL time.[set]
cparata	0:6d69e896ce38	4721	*
cparata	0:6d69e896ce38	4722	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4723	* @param val change the values of shock in reg INT_DUR2
cparata	0:6d69e896ce38	4724	*
cparata	0:6d69e896ce38	4725	*/
cparata	0:6d69e896ce38	4726	int32_t lsm6dso_tap_shock_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4727	{
cparata	3:4274d9103f1d	4728	lsm6dso_int_dur2_t reg;
cparata	3:4274d9103f1d	4729	int32_t ret;
cparata	3:4274d9103f1d	4730
cparata	3:4274d9103f1d	4731	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4732	if (ret == 0) {
cparata	3:4274d9103f1d	4733	reg.shock = val;
cparata	3:4274d9103f1d	4734	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4735	}
cparata	3:4274d9103f1d	4736	return ret;
cparata	0:6d69e896ce38	4737	}
cparata	0:6d69e896ce38	4738
cparata	0:6d69e896ce38	4739	/**
cparata	0:6d69e896ce38	4740	* @brief Maximum duration is the maximum time of an
cparata	0:6d69e896ce38	4741	* over threshold signal detection to be recognized
cparata	0:6d69e896ce38	4742	* as a tap event. The default value of these bits
cparata	0:6d69e896ce38	4743	* is 00b which corresponds to 4*ODR_XL time.
cparata	0:6d69e896ce38	4744	* If the SHOCK[1:0] bits are set to a different
cparata	0:6d69e896ce38	4745	* value, 1LSB corresponds to 8*ODR_XL time.[get]
cparata	0:6d69e896ce38	4746	*
cparata	0:6d69e896ce38	4747	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4748	* @param val change the values of shock in reg INT_DUR2
cparata	0:6d69e896ce38	4749	*
cparata	0:6d69e896ce38	4750	*/
cparata	0:6d69e896ce38	4751	int32_t lsm6dso_tap_shock_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4752	{
cparata	3:4274d9103f1d	4753	lsm6dso_int_dur2_t reg;
cparata	3:4274d9103f1d	4754	int32_t ret;
cparata	3:4274d9103f1d	4755
cparata	3:4274d9103f1d	4756	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4757	*val = reg.shock;
cparata	3:4274d9103f1d	4758
cparata	3:4274d9103f1d	4759	return ret;
cparata	0:6d69e896ce38	4760	}
cparata	0:6d69e896ce38	4761
cparata	0:6d69e896ce38	4762	/**
cparata	0:6d69e896ce38	4763	* @brief Quiet time is the time after the first detected
cparata	0:6d69e896ce38	4764	* tap in which there must not be any over threshold
cparata	0:6d69e896ce38	4765	* event.
cparata	0:6d69e896ce38	4766	* The default value of these bits is 00b which
cparata	0:6d69e896ce38	4767	* corresponds to 2*ODR_XL time. If the QUIET[1:0]
cparata	0:6d69e896ce38	4768	* bits are set to a different value,
cparata	0:6d69e896ce38	4769	* 1LSB corresponds to 4*ODR_XL time.[set]
cparata	0:6d69e896ce38	4770	*
cparata	0:6d69e896ce38	4771	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4772	* @param val change the values of quiet in reg INT_DUR2
cparata	0:6d69e896ce38	4773	*
cparata	0:6d69e896ce38	4774	*/
cparata	0:6d69e896ce38	4775	int32_t lsm6dso_tap_quiet_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4776	{
cparata	3:4274d9103f1d	4777	lsm6dso_int_dur2_t reg;
cparata	3:4274d9103f1d	4778	int32_t ret;
cparata	3:4274d9103f1d	4779
cparata	3:4274d9103f1d	4780	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4781	if (ret == 0) {
cparata	3:4274d9103f1d	4782	reg.quiet = val;
cparata	3:4274d9103f1d	4783	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4784	}
cparata	3:4274d9103f1d	4785	return ret;
cparata	0:6d69e896ce38	4786	}
cparata	0:6d69e896ce38	4787
cparata	0:6d69e896ce38	4788	/**
cparata	0:6d69e896ce38	4789	* @brief Quiet time is the time after the first detected
cparata	0:6d69e896ce38	4790	* tap in which there must not be any over threshold
cparata	0:6d69e896ce38	4791	* event.
cparata	0:6d69e896ce38	4792	* The default value of these bits is 00b which
cparata	0:6d69e896ce38	4793	* corresponds to 2*ODR_XL time.
cparata	0:6d69e896ce38	4794	* If the QUIET[1:0] bits are set to a different
cparata	0:6d69e896ce38	4795	* value, 1LSB corresponds to 4*ODR_XL time.[get]
cparata	0:6d69e896ce38	4796	*
cparata	0:6d69e896ce38	4797	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4798	* @param val change the values of quiet in reg INT_DUR2
cparata	0:6d69e896ce38	4799	*
cparata	0:6d69e896ce38	4800	*/
cparata	0:6d69e896ce38	4801	int32_t lsm6dso_tap_quiet_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4802	{
cparata	3:4274d9103f1d	4803	lsm6dso_int_dur2_t reg;
cparata	3:4274d9103f1d	4804	int32_t ret;
cparata	3:4274d9103f1d	4805
cparata	3:4274d9103f1d	4806	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4807	*val = reg.quiet;
cparata	3:4274d9103f1d	4808
cparata	3:4274d9103f1d	4809	return ret;
cparata	0:6d69e896ce38	4810	}
cparata	0:6d69e896ce38	4811
cparata	0:6d69e896ce38	4812	/**
cparata	0:6d69e896ce38	4813	* @brief When double tap recognition is enabled,
cparata	0:6d69e896ce38	4814	* this register expresses the maximum time
cparata	0:6d69e896ce38	4815	* between two consecutive detected taps to
cparata	0:6d69e896ce38	4816	* determine a double tap event.
cparata	0:6d69e896ce38	4817	* The default value of these bits is 0000b which
cparata	0:6d69e896ce38	4818	* corresponds to 16*ODR_XL time.
cparata	0:6d69e896ce38	4819	* If the DUR[3:0] bits are set to a different value,
cparata	0:6d69e896ce38	4820	* 1LSB corresponds to 32*ODR_XL time.[set]
cparata	0:6d69e896ce38	4821	*
cparata	0:6d69e896ce38	4822	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4823	* @param val change the values of dur in reg INT_DUR2
cparata	0:6d69e896ce38	4824	*
cparata	0:6d69e896ce38	4825	*/
cparata	0:6d69e896ce38	4826	int32_t lsm6dso_tap_dur_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4827	{
cparata	3:4274d9103f1d	4828	lsm6dso_int_dur2_t reg;
cparata	3:4274d9103f1d	4829	int32_t ret;
cparata	3:4274d9103f1d	4830
cparata	3:4274d9103f1d	4831	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4832	if (ret == 0) {
cparata	3:4274d9103f1d	4833	reg.dur = val;
cparata	3:4274d9103f1d	4834	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4835	}
cparata	3:4274d9103f1d	4836	return ret;
cparata	0:6d69e896ce38	4837	}
cparata	0:6d69e896ce38	4838
cparata	0:6d69e896ce38	4839	/**
cparata	0:6d69e896ce38	4840	* @brief When double tap recognition is enabled,
cparata	0:6d69e896ce38	4841	* this register expresses the maximum time
cparata	0:6d69e896ce38	4842	* between two consecutive detected taps to
cparata	0:6d69e896ce38	4843	* determine a double tap event.
cparata	0:6d69e896ce38	4844	* The default value of these bits is 0000b which
cparata	0:6d69e896ce38	4845	* corresponds to 16*ODR_XL time. If the DUR[3:0]
cparata	0:6d69e896ce38	4846	* bits are set to a different value,
cparata	0:6d69e896ce38	4847	* 1LSB corresponds to 32*ODR_XL time.[get]
cparata	0:6d69e896ce38	4848	*
cparata	0:6d69e896ce38	4849	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4850	* @param val change the values of dur in reg INT_DUR2
cparata	0:6d69e896ce38	4851	*
cparata	0:6d69e896ce38	4852	*/
cparata	0:6d69e896ce38	4853	int32_t lsm6dso_tap_dur_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4854	{
cparata	3:4274d9103f1d	4855	lsm6dso_int_dur2_t reg;
cparata	3:4274d9103f1d	4856	int32_t ret;
cparata	3:4274d9103f1d	4857
cparata	3:4274d9103f1d	4858	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4859	*val = reg.dur;
cparata	3:4274d9103f1d	4860
cparata	3:4274d9103f1d	4861	return ret;
cparata	0:6d69e896ce38	4862	}
cparata	0:6d69e896ce38	4863
cparata	0:6d69e896ce38	4864	/**
cparata	0:6d69e896ce38	4865	* @brief Single/double-tap event enable.[set]
cparata	0:6d69e896ce38	4866	*
cparata	0:6d69e896ce38	4867	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4868	* @param val change the values of single_double_tap in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4869	*
cparata	0:6d69e896ce38	4870	*/
cparata	0:6d69e896ce38	4871	int32_t lsm6dso_tap_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4872	lsm6dso_single_double_tap_t val)
cparata	0:6d69e896ce38	4873	{
cparata	3:4274d9103f1d	4874	lsm6dso_wake_up_ths_t reg;
cparata	3:4274d9103f1d	4875	int32_t ret;
cparata	3:4274d9103f1d	4876
cparata	3:4274d9103f1d	4877	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4878	if (ret == 0) {
cparata	3:4274d9103f1d	4879	reg.single_double_tap = (uint8_t)val;
cparata	3:4274d9103f1d	4880	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4881	}
cparata	3:4274d9103f1d	4882	return ret;
cparata	0:6d69e896ce38	4883	}
cparata	0:6d69e896ce38	4884
cparata	0:6d69e896ce38	4885	/**
cparata	0:6d69e896ce38	4886	* @brief Single/double-tap event enable.[get]
cparata	0:6d69e896ce38	4887	*
cparata	0:6d69e896ce38	4888	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4889	* @param val Get the values of single_double_tap in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4890	*
cparata	0:6d69e896ce38	4891	*/
cparata	0:6d69e896ce38	4892	int32_t lsm6dso_tap_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4893	lsm6dso_single_double_tap_t *val)
cparata	0:6d69e896ce38	4894	{
cparata	3:4274d9103f1d	4895	lsm6dso_wake_up_ths_t reg;
cparata	3:4274d9103f1d	4896	int32_t ret;
cparata	3:4274d9103f1d	4897
cparata	3:4274d9103f1d	4898	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4899
cparata	3:4274d9103f1d	4900	switch (reg.single_double_tap) {
cparata	3:4274d9103f1d	4901	case LSM6DSO_ONLY_SINGLE:
cparata	3:4274d9103f1d	4902	*val = LSM6DSO_ONLY_SINGLE;
cparata	3:4274d9103f1d	4903	break;
cparata	3:4274d9103f1d	4904	case LSM6DSO_BOTH_SINGLE_DOUBLE:
cparata	3:4274d9103f1d	4905	*val = LSM6DSO_BOTH_SINGLE_DOUBLE;
cparata	3:4274d9103f1d	4906	break;
cparata	3:4274d9103f1d	4907	default:
cparata	3:4274d9103f1d	4908	*val = LSM6DSO_ONLY_SINGLE;
cparata	3:4274d9103f1d	4909	break;
cparata	3:4274d9103f1d	4910	}
cparata	3:4274d9103f1d	4911
cparata	3:4274d9103f1d	4912	return ret;
cparata	0:6d69e896ce38	4913	}
cparata	0:6d69e896ce38	4914
cparata	0:6d69e896ce38	4915	/**
cparata	0:6d69e896ce38	4916	* @}
cparata	0:6d69e896ce38	4917	*
cparata	0:6d69e896ce38	4918	*/
cparata	0:6d69e896ce38	4919
cparata	0:6d69e896ce38	4920	/**
cparata	0:6d69e896ce38	4921	* @defgroup LSM6DSO_ Six_position_detection(6D/4D)
cparata	0:6d69e896ce38	4922	* @brief This section groups all the functions concerning six position
cparata	0:6d69e896ce38	4923	* detection (6D).
cparata	0:6d69e896ce38	4924	* @{
cparata	0:6d69e896ce38	4925	*
cparata	0:6d69e896ce38	4926	*/
cparata	0:6d69e896ce38	4927
cparata	0:6d69e896ce38	4928	/**
cparata	0:6d69e896ce38	4929	* @brief Threshold for 4D/6D function.[set]
cparata	0:6d69e896ce38	4930	*
cparata	0:6d69e896ce38	4931	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4932	* @param val change the values of sixd_ths in reg TAP_THS_6D
cparata	0:6d69e896ce38	4933	*
cparata	0:6d69e896ce38	4934	*/
cparata	0:6d69e896ce38	4935	int32_t lsm6dso_6d_threshold_set(lsm6dso_ctx_t *ctx, lsm6dso_sixd_ths_t val)
cparata	0:6d69e896ce38	4936	{
cparata	3:4274d9103f1d	4937	lsm6dso_tap_ths_6d_t reg;
cparata	3:4274d9103f1d	4938	int32_t ret;
cparata	3:4274d9103f1d	4939
cparata	3:4274d9103f1d	4940	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4941	if (ret == 0) {
cparata	3:4274d9103f1d	4942	reg.sixd_ths = (uint8_t)val;
cparata	3:4274d9103f1d	4943	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4944	}
cparata	3:4274d9103f1d	4945	return ret;
cparata	0:6d69e896ce38	4946	}
cparata	0:6d69e896ce38	4947
cparata	0:6d69e896ce38	4948	/**
cparata	0:6d69e896ce38	4949	* @brief Threshold for 4D/6D function.[get]
cparata	0:6d69e896ce38	4950	*
cparata	0:6d69e896ce38	4951	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4952	* @param val Get the values of sixd_ths in reg TAP_THS_6D
cparata	0:6d69e896ce38	4953	*
cparata	0:6d69e896ce38	4954	*/
cparata	0:6d69e896ce38	4955	int32_t lsm6dso_6d_threshold_get(lsm6dso_ctx_t ctx, lsm6dso_sixd_ths_t val)
cparata	0:6d69e896ce38	4956	{
cparata	3:4274d9103f1d	4957	lsm6dso_tap_ths_6d_t reg;
cparata	3:4274d9103f1d	4958	int32_t ret;
cparata	3:4274d9103f1d	4959
cparata	3:4274d9103f1d	4960	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4961	switch (reg.sixd_ths) {
cparata	3:4274d9103f1d	4962	case LSM6DSO_DEG_80:
cparata	3:4274d9103f1d	4963	*val = LSM6DSO_DEG_80;
cparata	3:4274d9103f1d	4964	break;
cparata	3:4274d9103f1d	4965	case LSM6DSO_DEG_70:
cparata	3:4274d9103f1d	4966	*val = LSM6DSO_DEG_70;
cparata	3:4274d9103f1d	4967	break;
cparata	3:4274d9103f1d	4968	case LSM6DSO_DEG_60:
cparata	3:4274d9103f1d	4969	*val = LSM6DSO_DEG_60;
cparata	3:4274d9103f1d	4970	break;
cparata	3:4274d9103f1d	4971	case LSM6DSO_DEG_50:
cparata	3:4274d9103f1d	4972	*val = LSM6DSO_DEG_50;
cparata	3:4274d9103f1d	4973	break;
cparata	3:4274d9103f1d	4974	default:
cparata	3:4274d9103f1d	4975	*val = LSM6DSO_DEG_80;
cparata	3:4274d9103f1d	4976	break;
cparata	3:4274d9103f1d	4977	}
cparata	3:4274d9103f1d	4978	return ret;
cparata	0:6d69e896ce38	4979	}
cparata	0:6d69e896ce38	4980
cparata	0:6d69e896ce38	4981	/**
cparata	0:6d69e896ce38	4982	* @brief 4D orientation detection enable.[set]
cparata	0:6d69e896ce38	4983	*
cparata	0:6d69e896ce38	4984	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4985	* @param val change the values of d4d_en in reg TAP_THS_6D
cparata	0:6d69e896ce38	4986	*
cparata	0:6d69e896ce38	4987	*/
cparata	0:6d69e896ce38	4988	int32_t lsm6dso_4d_mode_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4989	{
cparata	3:4274d9103f1d	4990	lsm6dso_tap_ths_6d_t reg;
cparata	3:4274d9103f1d	4991	int32_t ret;
cparata	3:4274d9103f1d	4992
cparata	3:4274d9103f1d	4993	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4994	if (ret == 0) {
cparata	3:4274d9103f1d	4995	reg.d4d_en = val;
cparata	3:4274d9103f1d	4996	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	4997	}
cparata	3:4274d9103f1d	4998	return ret;
cparata	0:6d69e896ce38	4999	}
cparata	0:6d69e896ce38	5000
cparata	0:6d69e896ce38	5001	/**
cparata	0:6d69e896ce38	5002	* @brief 4D orientation detection enable.[get]
cparata	0:6d69e896ce38	5003	*
cparata	0:6d69e896ce38	5004	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5005	* @param val change the values of d4d_en in reg TAP_THS_6D
cparata	0:6d69e896ce38	5006	*
cparata	0:6d69e896ce38	5007	*/
cparata	0:6d69e896ce38	5008	int32_t lsm6dso_4d_mode_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5009	{
cparata	3:4274d9103f1d	5010	lsm6dso_tap_ths_6d_t reg;
cparata	3:4274d9103f1d	5011	int32_t ret;
cparata	3:4274d9103f1d	5012
cparata	3:4274d9103f1d	5013	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5014	*val = reg.d4d_en;
cparata	3:4274d9103f1d	5015
cparata	3:4274d9103f1d	5016	return ret;
cparata	0:6d69e896ce38	5017	}
cparata	0:6d69e896ce38	5018
cparata	0:6d69e896ce38	5019	/**
cparata	0:6d69e896ce38	5020	* @}
cparata	0:6d69e896ce38	5021	*
cparata	0:6d69e896ce38	5022	*/
cparata	0:6d69e896ce38	5023
cparata	0:6d69e896ce38	5024	/**
cparata	0:6d69e896ce38	5025	* @defgroup LSM6DSO_free_fall
cparata	0:6d69e896ce38	5026	* @brief This section group all the functions concerning the free
cparata	0:6d69e896ce38	5027	* fall detection.
cparata	0:6d69e896ce38	5028	* @{
cparata	0:6d69e896ce38	5029	*
cparata	0:6d69e896ce38	5030	*/
cparata	0:6d69e896ce38	5031	/**
cparata	0:6d69e896ce38	5032	* @brief Free fall threshold setting.[set]
cparata	0:6d69e896ce38	5033	*
cparata	0:6d69e896ce38	5034	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5035	* @param val change the values of ff_ths in reg FREE_FALL
cparata	0:6d69e896ce38	5036	*
cparata	0:6d69e896ce38	5037	*/
cparata	0:6d69e896ce38	5038	int32_t lsm6dso_ff_threshold_set(lsm6dso_ctx_t *ctx, lsm6dso_ff_ths_t val)
cparata	0:6d69e896ce38	5039	{
cparata	3:4274d9103f1d	5040	lsm6dso_free_fall_t reg;
cparata	3:4274d9103f1d	5041	int32_t ret;
cparata	3:4274d9103f1d	5042
cparata	3:4274d9103f1d	5043	ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5044	if (ret == 0) {
cparata	3:4274d9103f1d	5045	reg.ff_ths = (uint8_t)val;
cparata	3:4274d9103f1d	5046	ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5047	}
cparata	3:4274d9103f1d	5048	return ret;
cparata	0:6d69e896ce38	5049	}
cparata	0:6d69e896ce38	5050
cparata	0:6d69e896ce38	5051	/**
cparata	0:6d69e896ce38	5052	* @brief Free fall threshold setting.[get]
cparata	0:6d69e896ce38	5053	*
cparata	0:6d69e896ce38	5054	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5055	* @param val Get the values of ff_ths in reg FREE_FALL
cparata	0:6d69e896ce38	5056	*
cparata	0:6d69e896ce38	5057	*/
cparata	0:6d69e896ce38	5058	int32_t lsm6dso_ff_threshold_get(lsm6dso_ctx_t ctx, lsm6dso_ff_ths_t val)
cparata	0:6d69e896ce38	5059	{
cparata	3:4274d9103f1d	5060	lsm6dso_free_fall_t reg;
cparata	3:4274d9103f1d	5061	int32_t ret;
cparata	3:4274d9103f1d	5062
cparata	3:4274d9103f1d	5063	ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5064	switch (reg.ff_ths) {
cparata	3:4274d9103f1d	5065	case LSM6DSO_FF_TSH_156mg:
cparata	3:4274d9103f1d	5066	*val = LSM6DSO_FF_TSH_156mg;
cparata	3:4274d9103f1d	5067	break;
cparata	3:4274d9103f1d	5068	case LSM6DSO_FF_TSH_219mg:
cparata	3:4274d9103f1d	5069	*val = LSM6DSO_FF_TSH_219mg;
cparata	3:4274d9103f1d	5070	break;
cparata	3:4274d9103f1d	5071	case LSM6DSO_FF_TSH_250mg:
cparata	3:4274d9103f1d	5072	*val = LSM6DSO_FF_TSH_250mg;
cparata	3:4274d9103f1d	5073	break;
cparata	3:4274d9103f1d	5074	case LSM6DSO_FF_TSH_312mg:
cparata	3:4274d9103f1d	5075	*val = LSM6DSO_FF_TSH_312mg;
cparata	3:4274d9103f1d	5076	break;
cparata	3:4274d9103f1d	5077	case LSM6DSO_FF_TSH_344mg:
cparata	3:4274d9103f1d	5078	*val = LSM6DSO_FF_TSH_344mg;
cparata	3:4274d9103f1d	5079	break;
cparata	3:4274d9103f1d	5080	case LSM6DSO_FF_TSH_406mg:
cparata	3:4274d9103f1d	5081	*val = LSM6DSO_FF_TSH_406mg;
cparata	3:4274d9103f1d	5082	break;
cparata	3:4274d9103f1d	5083	case LSM6DSO_FF_TSH_469mg:
cparata	3:4274d9103f1d	5084	*val = LSM6DSO_FF_TSH_469mg;
cparata	3:4274d9103f1d	5085	break;
cparata	3:4274d9103f1d	5086	case LSM6DSO_FF_TSH_500mg:
cparata	3:4274d9103f1d	5087	*val = LSM6DSO_FF_TSH_500mg;
cparata	3:4274d9103f1d	5088	break;
cparata	3:4274d9103f1d	5089	default:
cparata	3:4274d9103f1d	5090	*val = LSM6DSO_FF_TSH_156mg;
cparata	3:4274d9103f1d	5091	break;
cparata	3:4274d9103f1d	5092	}
cparata	3:4274d9103f1d	5093	return ret;
cparata	0:6d69e896ce38	5094	}
cparata	0:6d69e896ce38	5095
cparata	0:6d69e896ce38	5096	/**
cparata	0:6d69e896ce38	5097	* @brief Free-fall duration event.[set]
cparata	0:6d69e896ce38	5098	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	5099	*
cparata	0:6d69e896ce38	5100	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5101	* @param val change the values of ff_dur in reg FREE_FALL
cparata	0:6d69e896ce38	5102	*
cparata	0:6d69e896ce38	5103	*/
cparata	0:6d69e896ce38	5104	int32_t lsm6dso_ff_dur_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	5105	{
cparata	3:4274d9103f1d	5106	lsm6dso_wake_up_dur_t wake_up_dur;
cparata	3:4274d9103f1d	5107	lsm6dso_free_fall_t free_fall;
cparata	3:4274d9103f1d	5108	int32_t ret;
cparata	3:4274d9103f1d	5109
cparata	3:4274d9103f1d	5110	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
cparata	3:4274d9103f1d	5111	if (ret == 0) {
cparata	3:4274d9103f1d	5112	ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
cparata	3:4274d9103f1d	5113	}
cparata	3:4274d9103f1d	5114	if (ret == 0) {
cparata	3:4274d9103f1d	5115	wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
cparata	3:4274d9103f1d	5116	free_fall.ff_dur = (uint8_t)val & 0x1FU;
cparata	3:4274d9103f1d	5117	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR,
cparata	3:4274d9103f1d	5118	(uint8_t *)&wake_up_dur, 1);
cparata	3:4274d9103f1d	5119	}
cparata	3:4274d9103f1d	5120	if (ret == 0) {
cparata	3:4274d9103f1d	5121	ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
cparata	3:4274d9103f1d	5122	}
cparata	3:4274d9103f1d	5123	return ret;
cparata	0:6d69e896ce38	5124	}
cparata	0:6d69e896ce38	5125
cparata	0:6d69e896ce38	5126	/**
cparata	0:6d69e896ce38	5127	* @brief Free-fall duration event.[get]
cparata	0:6d69e896ce38	5128	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	5129	*
cparata	0:6d69e896ce38	5130	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5131	* @param val change the values of ff_dur in reg FREE_FALL
cparata	0:6d69e896ce38	5132	*
cparata	0:6d69e896ce38	5133	*/
cparata	0:6d69e896ce38	5134	int32_t lsm6dso_ff_dur_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5135	{
cparata	3:4274d9103f1d	5136	lsm6dso_wake_up_dur_t wake_up_dur;
cparata	3:4274d9103f1d	5137	lsm6dso_free_fall_t free_fall;
cparata	3:4274d9103f1d	5138	int32_t ret;
cparata	3:4274d9103f1d	5139
cparata	3:4274d9103f1d	5140	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
cparata	3:4274d9103f1d	5141	if (ret == 0) {
cparata	3:4274d9103f1d	5142	ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
cparata	3:4274d9103f1d	5143	*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
cparata	3:4274d9103f1d	5144	}
cparata	3:4274d9103f1d	5145	return ret;
cparata	0:6d69e896ce38	5146	}
cparata	0:6d69e896ce38	5147
cparata	0:6d69e896ce38	5148	/**
cparata	0:6d69e896ce38	5149	* @}
cparata	0:6d69e896ce38	5150	*
cparata	0:6d69e896ce38	5151	*/
cparata	0:6d69e896ce38	5152
cparata	0:6d69e896ce38	5153	/**
cparata	0:6d69e896ce38	5154	* @defgroup LSM6DSO_fifo
cparata	0:6d69e896ce38	5155	* @brief This section group all the functions concerning the fifo usage
cparata	0:6d69e896ce38	5156	* @{
cparata	0:6d69e896ce38	5157	*
cparata	0:6d69e896ce38	5158	*/
cparata	0:6d69e896ce38	5159
cparata	0:6d69e896ce38	5160	/**
cparata	0:6d69e896ce38	5161	* @brief FIFO watermark level selection.[set]
cparata	0:6d69e896ce38	5162	*
cparata	0:6d69e896ce38	5163	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5164	* @param val change the values of wtm in reg FIFO_CTRL1
cparata	0:6d69e896ce38	5165	*
cparata	0:6d69e896ce38	5166	*/
cparata	0:6d69e896ce38	5167	int32_t lsm6dso_fifo_watermark_set(lsm6dso_ctx_t *ctx, uint16_t val)
cparata	0:6d69e896ce38	5168	{
cparata	3:4274d9103f1d	5169	lsm6dso_fifo_ctrl1_t fifo_ctrl1;
cparata	3:4274d9103f1d	5170	lsm6dso_fifo_ctrl2_t fifo_ctrl2;
cparata	3:4274d9103f1d	5171	int32_t ret;
cparata	3:4274d9103f1d	5172
cparata	3:4274d9103f1d	5173	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
cparata	3:4274d9103f1d	5174	if (ret == 0) {
cparata	3:4274d9103f1d	5175	fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
cparata	3:4274d9103f1d	5176	fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
cparata	3:4274d9103f1d	5177	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
cparata	3:4274d9103f1d	5178	}
cparata	3:4274d9103f1d	5179	if (ret == 0) {
cparata	3:4274d9103f1d	5180	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
cparata	3:4274d9103f1d	5181	}
cparata	3:4274d9103f1d	5182	return ret;
cparata	0:6d69e896ce38	5183	}
cparata	0:6d69e896ce38	5184
cparata	0:6d69e896ce38	5185	/**
cparata	0:6d69e896ce38	5186	* @brief FIFO watermark level selection.[get]
cparata	0:6d69e896ce38	5187	*
cparata	0:6d69e896ce38	5188	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5189	* @param val change the values of wtm in reg FIFO_CTRL1
cparata	0:6d69e896ce38	5190	*
cparata	0:6d69e896ce38	5191	*/
cparata	0:6d69e896ce38	5192	int32_t lsm6dso_fifo_watermark_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	0:6d69e896ce38	5193	{
cparata	3:4274d9103f1d	5194	lsm6dso_fifo_ctrl1_t fifo_ctrl1;
cparata	3:4274d9103f1d	5195	lsm6dso_fifo_ctrl2_t fifo_ctrl2;
cparata	3:4274d9103f1d	5196	int32_t ret;
cparata	3:4274d9103f1d	5197
cparata	3:4274d9103f1d	5198	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
cparata	3:4274d9103f1d	5199	if (ret == 0) {
cparata	3:4274d9103f1d	5200	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
cparata	3:4274d9103f1d	5201	*val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
cparata	3:4274d9103f1d	5202	}
cparata	3:4274d9103f1d	5203	return ret;
cparata	0:6d69e896ce38	5204	}
cparata	0:6d69e896ce38	5205
cparata	0:6d69e896ce38	5206	/**
cparata	0:6d69e896ce38	5207	* @brief FIFO compression feature initialization request [set].
cparata	0:6d69e896ce38	5208	*
cparata	0:6d69e896ce38	5209	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5210	* @param val change the values of FIFO_COMPR_INIT in
cparata	0:6d69e896ce38	5211	* reg EMB_FUNC_INIT_B
cparata	0:6d69e896ce38	5212	*
cparata	0:6d69e896ce38	5213	*/
cparata	0:6d69e896ce38	5214	int32_t lsm6dso_compression_algo_init_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	5215	{
cparata	3:4274d9103f1d	5216	lsm6dso_emb_func_init_b_t reg;
cparata	3:4274d9103f1d	5217	int32_t ret;
cparata	3:4274d9103f1d	5218
cparata	3:4274d9103f1d	5219	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	5220	if (ret == 0) {
cparata	3:4274d9103f1d	5221	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5222	}
cparata	3:4274d9103f1d	5223	if (ret == 0) {
cparata	3:4274d9103f1d	5224	reg.fifo_compr_init = val;
cparata	3:4274d9103f1d	5225	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5226	}
cparata	3:4274d9103f1d	5227	if (ret == 0) {
cparata	3:4274d9103f1d	5228	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	5229	}
cparata	3:4274d9103f1d	5230
cparata	3:4274d9103f1d	5231	return ret;
cparata	0:6d69e896ce38	5232	}
cparata	0:6d69e896ce38	5233
cparata	0:6d69e896ce38	5234	/**
cparata	0:6d69e896ce38	5235	* @brief FIFO compression feature initialization request [get].
cparata	0:6d69e896ce38	5236	*
cparata	0:6d69e896ce38	5237	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5238	* @param val change the values of FIFO_COMPR_INIT in
cparata	0:6d69e896ce38	5239	* reg EMB_FUNC_INIT_B
cparata	0:6d69e896ce38	5240	*
cparata	0:6d69e896ce38	5241	*/
cparata	0:6d69e896ce38	5242	int32_t lsm6dso_compression_algo_init_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5243	{
cparata	3:4274d9103f1d	5244	lsm6dso_emb_func_init_b_t reg;
cparata	3:4274d9103f1d	5245	int32_t ret;
cparata	3:4274d9103f1d	5246
cparata	3:4274d9103f1d	5247	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	5248	if (ret == 0) {
cparata	3:4274d9103f1d	5249	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5250	}
cparata	3:4274d9103f1d	5251	if (ret == 0) {
cparata	3:4274d9103f1d	5252	*val = reg.fifo_compr_init;
cparata	3:4274d9103f1d	5253	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	5254	}
cparata	3:4274d9103f1d	5255
cparata	3:4274d9103f1d	5256	return ret;
cparata	0:6d69e896ce38	5257	}
cparata	0:6d69e896ce38	5258
cparata	0:6d69e896ce38	5259	/**
cparata	0:6d69e896ce38	5260	* @brief Enable and configure compression algo.[set]
cparata	0:6d69e896ce38	5261	*
cparata	0:6d69e896ce38	5262	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5263	* @param val change the values of uncoptr_rate in
cparata	0:6d69e896ce38	5264	* reg FIFO_CTRL2
cparata	0:6d69e896ce38	5265	*
cparata	0:6d69e896ce38	5266	*/
cparata	0:6d69e896ce38	5267	int32_t lsm6dso_compression_algo_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5268	lsm6dso_uncoptr_rate_t val)
cparata	0:6d69e896ce38	5269	{
cparata	3:4274d9103f1d	5270	lsm6dso_emb_func_en_b_t emb_func_en_b;
cparata	3:4274d9103f1d	5271	lsm6dso_fifo_ctrl2_t fifo_ctrl2;
cparata	3:4274d9103f1d	5272	int32_t ret;
cparata	3:4274d9103f1d	5273
cparata	3:4274d9103f1d	5274	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	5275	if (ret == 0) {
cparata	3:4274d9103f1d	5276	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	3:4274d9103f1d	5277	(uint8_t *)&emb_func_en_b, 1);
cparata	3:4274d9103f1d	5278	}
cparata	3:4274d9103f1d	5279	if (ret == 0) {
cparata	3:4274d9103f1d	5280	emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
cparata	3:4274d9103f1d	5281	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	3:4274d9103f1d	5282	(uint8_t *)&emb_func_en_b, 1);
cparata	3:4274d9103f1d	5283	}
cparata	3:4274d9103f1d	5284	if (ret == 0) {
cparata	3:4274d9103f1d	5285	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	5286	}
cparata	3:4274d9103f1d	5287	if (ret == 0) {
cparata	3:4274d9103f1d	5288
cparata	3:4274d9103f1d	5289	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
cparata	3:4274d9103f1d	5290	(uint8_t *)&fifo_ctrl2, 1);
cparata	3:4274d9103f1d	5291	}
cparata	3:4274d9103f1d	5292	if (ret == 0) {
cparata	3:4274d9103f1d	5293	fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
cparata	3:4274d9103f1d	5294	fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
cparata	3:4274d9103f1d	5295	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2,
cparata	3:4274d9103f1d	5296	(uint8_t *)&fifo_ctrl2, 1);
cparata	3:4274d9103f1d	5297	}
cparata	3:4274d9103f1d	5298	return ret;
cparata	0:6d69e896ce38	5299	}
cparata	0:6d69e896ce38	5300
cparata	0:6d69e896ce38	5301	/**
cparata	0:6d69e896ce38	5302	* @brief Enable and configure compression algo.[get]
cparata	0:6d69e896ce38	5303	*
cparata	0:6d69e896ce38	5304	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5305	* @param val Get the values of uncoptr_rate in
cparata	0:6d69e896ce38	5306	* reg FIFO_CTRL2
cparata	0:6d69e896ce38	5307	*
cparata	0:6d69e896ce38	5308	*/
cparata	0:6d69e896ce38	5309	int32_t lsm6dso_compression_algo_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5310	lsm6dso_uncoptr_rate_t *val)
cparata	0:6d69e896ce38	5311	{
cparata	3:4274d9103f1d	5312	lsm6dso_fifo_ctrl2_t reg;
cparata	3:4274d9103f1d	5313	int32_t ret;
cparata	3:4274d9103f1d	5314
cparata	3:4274d9103f1d	5315	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5316
cparata	3:4274d9103f1d	5317	switch ((reg.fifo_compr_rt_en << 2) \| reg.uncoptr_rate) {
cparata	3:4274d9103f1d	5318	case LSM6DSO_CMP_DISABLE:
cparata	3:4274d9103f1d	5319	*val = LSM6DSO_CMP_DISABLE;
cparata	3:4274d9103f1d	5320	break;
cparata	3:4274d9103f1d	5321	case LSM6DSO_CMP_ALWAYS:
cparata	3:4274d9103f1d	5322	*val = LSM6DSO_CMP_ALWAYS;
cparata	3:4274d9103f1d	5323	break;
cparata	3:4274d9103f1d	5324	case LSM6DSO_CMP_8_TO_1:
cparata	3:4274d9103f1d	5325	*val = LSM6DSO_CMP_8_TO_1;
cparata	3:4274d9103f1d	5326	break;
cparata	3:4274d9103f1d	5327	case LSM6DSO_CMP_16_TO_1:
cparata	3:4274d9103f1d	5328	*val = LSM6DSO_CMP_16_TO_1;
cparata	3:4274d9103f1d	5329	break;
cparata	3:4274d9103f1d	5330	case LSM6DSO_CMP_32_TO_1:
cparata	3:4274d9103f1d	5331	*val = LSM6DSO_CMP_32_TO_1;
cparata	3:4274d9103f1d	5332	break;
cparata	3:4274d9103f1d	5333	default:
cparata	3:4274d9103f1d	5334	*val = LSM6DSO_CMP_DISABLE;
cparata	3:4274d9103f1d	5335	break;
cparata	3:4274d9103f1d	5336	}
cparata	3:4274d9103f1d	5337	return ret;
cparata	0:6d69e896ce38	5338	}
cparata	0:6d69e896ce38	5339
cparata	0:6d69e896ce38	5340	/**
cparata	0:6d69e896ce38	5341	* @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
cparata	0:6d69e896ce38	5342	*
cparata	0:6d69e896ce38	5343	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5344	* @param val change the values of odrchg_en in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5345	*
cparata	0:6d69e896ce38	5346	*/
cparata	0:6d69e896ce38	5347	int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5348	uint8_t val)
cparata	0:6d69e896ce38	5349	{
cparata	3:4274d9103f1d	5350	lsm6dso_fifo_ctrl2_t reg;
cparata	3:4274d9103f1d	5351	int32_t ret;
cparata	3:4274d9103f1d	5352
cparata	3:4274d9103f1d	5353	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5354	if (ret == 0) {
cparata	3:4274d9103f1d	5355	reg.odrchg_en = val;
cparata	3:4274d9103f1d	5356	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5357	}
cparata	3:4274d9103f1d	5358	return ret;
cparata	0:6d69e896ce38	5359	}
cparata	0:6d69e896ce38	5360
cparata	0:6d69e896ce38	5361	/**
cparata	0:6d69e896ce38	5362	* @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
cparata	0:6d69e896ce38	5363	*
cparata	0:6d69e896ce38	5364	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5365	* @param val change the values of odrchg_en in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5366	*
cparata	0:6d69e896ce38	5367	*/
cparata	0:6d69e896ce38	5368	int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5369	uint8_t *val)
cparata	0:6d69e896ce38	5370	{
cparata	3:4274d9103f1d	5371	lsm6dso_fifo_ctrl2_t reg;
cparata	3:4274d9103f1d	5372	int32_t ret;
cparata	3:4274d9103f1d	5373
cparata	3:4274d9103f1d	5374	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5375	*val = reg.odrchg_en;
cparata	3:4274d9103f1d	5376
cparata	3:4274d9103f1d	5377	return ret;
cparata	0:6d69e896ce38	5378	}
cparata	0:6d69e896ce38	5379
cparata	0:6d69e896ce38	5380	/**
cparata	0:6d69e896ce38	5381	* @brief Enables/Disables compression algorithm runtime.[set]
cparata	0:6d69e896ce38	5382	*
cparata	0:6d69e896ce38	5383	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5384	* @param val change the values of fifo_compr_rt_en in
cparata	0:6d69e896ce38	5385	* reg FIFO_CTRL2
cparata	0:6d69e896ce38	5386	*
cparata	0:6d69e896ce38	5387	*/
cparata	0:6d69e896ce38	5388	int32_t lsm6dso_compression_algo_real_time_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5389	uint8_t val)
cparata	0:6d69e896ce38	5390	{
cparata	3:4274d9103f1d	5391	lsm6dso_fifo_ctrl2_t reg;
cparata	3:4274d9103f1d	5392	int32_t ret;
cparata	3:4274d9103f1d	5393
cparata	3:4274d9103f1d	5394	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5395	if (ret == 0) {
cparata	3:4274d9103f1d	5396	reg.fifo_compr_rt_en = val;
cparata	3:4274d9103f1d	5397	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5398	}
cparata	3:4274d9103f1d	5399	return ret;
cparata	0:6d69e896ce38	5400	}
cparata	0:6d69e896ce38	5401
cparata	0:6d69e896ce38	5402	/**
cparata	0:6d69e896ce38	5403	* @brief Enables/Disables compression algorithm runtime. [get]
cparata	0:6d69e896ce38	5404	*
cparata	0:6d69e896ce38	5405	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5406	* @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5407	*
cparata	0:6d69e896ce38	5408	*/
cparata	0:6d69e896ce38	5409	int32_t lsm6dso_compression_algo_real_time_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5410	uint8_t *val)
cparata	0:6d69e896ce38	5411	{
cparata	3:4274d9103f1d	5412	lsm6dso_fifo_ctrl2_t reg;
cparata	3:4274d9103f1d	5413	int32_t ret;
cparata	3:4274d9103f1d	5414
cparata	3:4274d9103f1d	5415	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5416	*val = reg.fifo_compr_rt_en;
cparata	3:4274d9103f1d	5417
cparata	3:4274d9103f1d	5418	return ret;
cparata	0:6d69e896ce38	5419	}
cparata	0:6d69e896ce38	5420
cparata	0:6d69e896ce38	5421	/**
cparata	0:6d69e896ce38	5422	* @brief Sensing chain FIFO stop values memorization at
cparata	0:6d69e896ce38	5423	* threshold level.[set]
cparata	0:6d69e896ce38	5424	*
cparata	0:6d69e896ce38	5425	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5426	* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5427	*
cparata	0:6d69e896ce38	5428	*/
cparata	0:6d69e896ce38	5429	int32_t lsm6dso_fifo_stop_on_wtm_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	5430	{
cparata	3:4274d9103f1d	5431	lsm6dso_fifo_ctrl2_t reg;
cparata	3:4274d9103f1d	5432	int32_t ret;
cparata	3:4274d9103f1d	5433
cparata	3:4274d9103f1d	5434	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5435	if (ret == 0) {
cparata	3:4274d9103f1d	5436	reg.stop_on_wtm = val;
cparata	3:4274d9103f1d	5437	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5438	}
cparata	3:4274d9103f1d	5439	return ret;
cparata	0:6d69e896ce38	5440	}
cparata	0:6d69e896ce38	5441
cparata	0:6d69e896ce38	5442	/**
cparata	0:6d69e896ce38	5443	* @brief Sensing chain FIFO stop values memorization at
cparata	0:6d69e896ce38	5444	* threshold level.[get]
cparata	0:6d69e896ce38	5445	*
cparata	0:6d69e896ce38	5446	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5447	* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5448	*
cparata	0:6d69e896ce38	5449	*/
cparata	0:6d69e896ce38	5450	int32_t lsm6dso_fifo_stop_on_wtm_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5451	{
cparata	3:4274d9103f1d	5452	lsm6dso_fifo_ctrl2_t reg;
cparata	3:4274d9103f1d	5453	int32_t ret;
cparata	3:4274d9103f1d	5454
cparata	3:4274d9103f1d	5455	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5456	*val = reg.stop_on_wtm;
cparata	3:4274d9103f1d	5457
cparata	3:4274d9103f1d	5458	return ret;
cparata	0:6d69e896ce38	5459	}
cparata	0:6d69e896ce38	5460
cparata	0:6d69e896ce38	5461	/**
cparata	0:6d69e896ce38	5462	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5463	* for accelerometer data.[set]
cparata	0:6d69e896ce38	5464	*
cparata	0:6d69e896ce38	5465	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5466	* @param val change the values of bdr_xl in reg FIFO_CTRL3
cparata	0:6d69e896ce38	5467	*
cparata	0:6d69e896ce38	5468	*/
cparata	0:6d69e896ce38	5469	int32_t lsm6dso_fifo_xl_batch_set(lsm6dso_ctx_t *ctx, lsm6dso_bdr_xl_t val)
cparata	0:6d69e896ce38	5470	{
cparata	3:4274d9103f1d	5471	lsm6dso_fifo_ctrl3_t reg;
cparata	3:4274d9103f1d	5472	int32_t ret;
cparata	3:4274d9103f1d	5473
cparata	3:4274d9103f1d	5474	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5475	if (ret == 0) {
cparata	3:4274d9103f1d	5476	reg.bdr_xl = (uint8_t)val;
cparata	3:4274d9103f1d	5477	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5478	}
cparata	3:4274d9103f1d	5479	return ret;
cparata	0:6d69e896ce38	5480	}
cparata	0:6d69e896ce38	5481
cparata	0:6d69e896ce38	5482	/**
cparata	0:6d69e896ce38	5483	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5484	* for accelerometer data.[get]
cparata	0:6d69e896ce38	5485	*
cparata	0:6d69e896ce38	5486	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5487	* @param val Get the values of bdr_xl in reg FIFO_CTRL3
cparata	0:6d69e896ce38	5488	*
cparata	0:6d69e896ce38	5489	*/
cparata	0:6d69e896ce38	5490	int32_t lsm6dso_fifo_xl_batch_get(lsm6dso_ctx_t ctx, lsm6dso_bdr_xl_t val)
cparata	0:6d69e896ce38	5491	{
cparata	3:4274d9103f1d	5492	lsm6dso_fifo_ctrl3_t reg;
cparata	3:4274d9103f1d	5493	int32_t ret;
cparata	3:4274d9103f1d	5494
cparata	3:4274d9103f1d	5495	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5496	switch (reg.bdr_xl) {
cparata	3:4274d9103f1d	5497	case LSM6DSO_XL_NOT_BATCHED:
cparata	3:4274d9103f1d	5498	*val = LSM6DSO_XL_NOT_BATCHED;
cparata	3:4274d9103f1d	5499	break;
cparata	3:4274d9103f1d	5500	case LSM6DSO_XL_BATCHED_AT_12Hz5:
cparata	3:4274d9103f1d	5501	*val = LSM6DSO_XL_BATCHED_AT_12Hz5;
cparata	3:4274d9103f1d	5502	break;
cparata	3:4274d9103f1d	5503	case LSM6DSO_XL_BATCHED_AT_26Hz:
cparata	3:4274d9103f1d	5504	*val = LSM6DSO_XL_BATCHED_AT_26Hz;
cparata	3:4274d9103f1d	5505	break;
cparata	3:4274d9103f1d	5506	case LSM6DSO_XL_BATCHED_AT_52Hz:
cparata	3:4274d9103f1d	5507	*val = LSM6DSO_XL_BATCHED_AT_52Hz;
cparata	3:4274d9103f1d	5508	break;
cparata	3:4274d9103f1d	5509	case LSM6DSO_XL_BATCHED_AT_104Hz:
cparata	3:4274d9103f1d	5510	*val = LSM6DSO_XL_BATCHED_AT_104Hz;
cparata	3:4274d9103f1d	5511	break;
cparata	3:4274d9103f1d	5512	case LSM6DSO_XL_BATCHED_AT_208Hz:
cparata	3:4274d9103f1d	5513	*val = LSM6DSO_XL_BATCHED_AT_208Hz;
cparata	3:4274d9103f1d	5514	break;
cparata	3:4274d9103f1d	5515	case LSM6DSO_XL_BATCHED_AT_417Hz:
cparata	3:4274d9103f1d	5516	*val = LSM6DSO_XL_BATCHED_AT_417Hz;
cparata	3:4274d9103f1d	5517	break;
cparata	3:4274d9103f1d	5518	case LSM6DSO_XL_BATCHED_AT_833Hz:
cparata	3:4274d9103f1d	5519	*val = LSM6DSO_XL_BATCHED_AT_833Hz;
cparata	3:4274d9103f1d	5520	break;
cparata	3:4274d9103f1d	5521	case LSM6DSO_XL_BATCHED_AT_1667Hz:
cparata	3:4274d9103f1d	5522	*val = LSM6DSO_XL_BATCHED_AT_1667Hz;
cparata	3:4274d9103f1d	5523	break;
cparata	3:4274d9103f1d	5524	case LSM6DSO_XL_BATCHED_AT_3333Hz:
cparata	3:4274d9103f1d	5525	*val = LSM6DSO_XL_BATCHED_AT_3333Hz;
cparata	3:4274d9103f1d	5526	break;
cparata	3:4274d9103f1d	5527	case LSM6DSO_XL_BATCHED_AT_6667Hz:
cparata	3:4274d9103f1d	5528	*val = LSM6DSO_XL_BATCHED_AT_6667Hz;
cparata	3:4274d9103f1d	5529	break;
cparata	3:4274d9103f1d	5530	case LSM6DSO_XL_BATCHED_AT_6Hz5:
cparata	3:4274d9103f1d	5531	*val = LSM6DSO_XL_BATCHED_AT_6Hz5;
cparata	3:4274d9103f1d	5532	break;
cparata	3:4274d9103f1d	5533	default:
cparata	3:4274d9103f1d	5534	*val = LSM6DSO_XL_NOT_BATCHED;
cparata	3:4274d9103f1d	5535	break;
cparata	3:4274d9103f1d	5536	}
cparata	3:4274d9103f1d	5537
cparata	3:4274d9103f1d	5538	return ret;
cparata	0:6d69e896ce38	5539	}
cparata	0:6d69e896ce38	5540
cparata	0:6d69e896ce38	5541	/**
cparata	0:6d69e896ce38	5542	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5543	* for gyroscope data.[set]
cparata	0:6d69e896ce38	5544	*
cparata	0:6d69e896ce38	5545	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5546	* @param val change the values of bdr_gy in reg FIFO_CTRL3
cparata	0:6d69e896ce38	5547	*
cparata	0:6d69e896ce38	5548	*/
cparata	0:6d69e896ce38	5549	int32_t lsm6dso_fifo_gy_batch_set(lsm6dso_ctx_t *ctx, lsm6dso_bdr_gy_t val)
cparata	0:6d69e896ce38	5550	{
cparata	3:4274d9103f1d	5551	lsm6dso_fifo_ctrl3_t reg;
cparata	3:4274d9103f1d	5552	int32_t ret;
cparata	3:4274d9103f1d	5553
cparata	3:4274d9103f1d	5554	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5555	if (ret == 0) {
cparata	3:4274d9103f1d	5556	reg.bdr_gy = (uint8_t)val;
cparata	3:4274d9103f1d	5557	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5558	}
cparata	3:4274d9103f1d	5559	return ret;
cparata	0:6d69e896ce38	5560	}
cparata	0:6d69e896ce38	5561
cparata	0:6d69e896ce38	5562	/**
cparata	0:6d69e896ce38	5563	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5564	* for gyroscope data.[get]
cparata	0:6d69e896ce38	5565	*
cparata	0:6d69e896ce38	5566	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5567	* @param val Get the values of bdr_gy in reg FIFO_CTRL3
cparata	0:6d69e896ce38	5568	*
cparata	0:6d69e896ce38	5569	*/
cparata	0:6d69e896ce38	5570	int32_t lsm6dso_fifo_gy_batch_get(lsm6dso_ctx_t ctx, lsm6dso_bdr_gy_t val)
cparata	0:6d69e896ce38	5571	{
cparata	3:4274d9103f1d	5572	lsm6dso_fifo_ctrl3_t reg;
cparata	3:4274d9103f1d	5573	int32_t ret;
cparata	3:4274d9103f1d	5574
cparata	3:4274d9103f1d	5575	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5576	switch (reg.bdr_gy) {
cparata	3:4274d9103f1d	5577	case LSM6DSO_GY_NOT_BATCHED:
cparata	3:4274d9103f1d	5578	*val = LSM6DSO_GY_NOT_BATCHED;
cparata	3:4274d9103f1d	5579	break;
cparata	3:4274d9103f1d	5580	case LSM6DSO_GY_BATCHED_AT_12Hz5:
cparata	3:4274d9103f1d	5581	*val = LSM6DSO_GY_BATCHED_AT_12Hz5;
cparata	3:4274d9103f1d	5582	break;
cparata	3:4274d9103f1d	5583	case LSM6DSO_GY_BATCHED_AT_26Hz:
cparata	3:4274d9103f1d	5584	*val = LSM6DSO_GY_BATCHED_AT_26Hz;
cparata	3:4274d9103f1d	5585	break;
cparata	3:4274d9103f1d	5586	case LSM6DSO_GY_BATCHED_AT_52Hz:
cparata	3:4274d9103f1d	5587	*val = LSM6DSO_GY_BATCHED_AT_52Hz;
cparata	3:4274d9103f1d	5588	break;
cparata	3:4274d9103f1d	5589	case LSM6DSO_GY_BATCHED_AT_104Hz:
cparata	3:4274d9103f1d	5590	*val = LSM6DSO_GY_BATCHED_AT_104Hz;
cparata	3:4274d9103f1d	5591	break;
cparata	3:4274d9103f1d	5592	case LSM6DSO_GY_BATCHED_AT_208Hz:
cparata	3:4274d9103f1d	5593	*val = LSM6DSO_GY_BATCHED_AT_208Hz;
cparata	3:4274d9103f1d	5594	break;
cparata	3:4274d9103f1d	5595	case LSM6DSO_GY_BATCHED_AT_417Hz:
cparata	3:4274d9103f1d	5596	*val = LSM6DSO_GY_BATCHED_AT_417Hz;
cparata	3:4274d9103f1d	5597	break;
cparata	3:4274d9103f1d	5598	case LSM6DSO_GY_BATCHED_AT_833Hz:
cparata	3:4274d9103f1d	5599	*val = LSM6DSO_GY_BATCHED_AT_833Hz;
cparata	3:4274d9103f1d	5600	break;
cparata	3:4274d9103f1d	5601	case LSM6DSO_GY_BATCHED_AT_1667Hz:
cparata	3:4274d9103f1d	5602	*val = LSM6DSO_GY_BATCHED_AT_1667Hz;
cparata	3:4274d9103f1d	5603	break;
cparata	3:4274d9103f1d	5604	case LSM6DSO_GY_BATCHED_AT_3333Hz:
cparata	3:4274d9103f1d	5605	*val = LSM6DSO_GY_BATCHED_AT_3333Hz;
cparata	3:4274d9103f1d	5606	break;
cparata	3:4274d9103f1d	5607	case LSM6DSO_GY_BATCHED_AT_6667Hz:
cparata	3:4274d9103f1d	5608	*val = LSM6DSO_GY_BATCHED_AT_6667Hz;
cparata	3:4274d9103f1d	5609	break;
cparata	3:4274d9103f1d	5610	case LSM6DSO_GY_BATCHED_AT_6Hz5:
cparata	3:4274d9103f1d	5611	*val = LSM6DSO_GY_BATCHED_AT_6Hz5;
cparata	3:4274d9103f1d	5612	break;
cparata	3:4274d9103f1d	5613	default:
cparata	3:4274d9103f1d	5614	*val = LSM6DSO_GY_NOT_BATCHED;
cparata	3:4274d9103f1d	5615	break;
cparata	3:4274d9103f1d	5616	}
cparata	3:4274d9103f1d	5617	return ret;
cparata	0:6d69e896ce38	5618	}
cparata	0:6d69e896ce38	5619
cparata	0:6d69e896ce38	5620	/**
cparata	0:6d69e896ce38	5621	* @brief FIFO mode selection.[set]
cparata	0:6d69e896ce38	5622	*
cparata	0:6d69e896ce38	5623	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5624	* @param val change the values of fifo_mode in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5625	*
cparata	0:6d69e896ce38	5626	*/
cparata	0:6d69e896ce38	5627	int32_t lsm6dso_fifo_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_fifo_mode_t val)
cparata	0:6d69e896ce38	5628	{
cparata	3:4274d9103f1d	5629	lsm6dso_fifo_ctrl4_t reg;
cparata	3:4274d9103f1d	5630	int32_t ret;
cparata	3:4274d9103f1d	5631
cparata	3:4274d9103f1d	5632	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5633	if (ret == 0) {
cparata	3:4274d9103f1d	5634	reg.fifo_mode = (uint8_t)val;
cparata	3:4274d9103f1d	5635	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5636	}
cparata	3:4274d9103f1d	5637	return ret;
cparata	0:6d69e896ce38	5638	}
cparata	0:6d69e896ce38	5639
cparata	0:6d69e896ce38	5640	/**
cparata	0:6d69e896ce38	5641	* @brief FIFO mode selection.[get]
cparata	0:6d69e896ce38	5642	*
cparata	0:6d69e896ce38	5643	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5644	* @param val Get the values of fifo_mode in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5645	*
cparata	0:6d69e896ce38	5646	*/
cparata	0:6d69e896ce38	5647	int32_t lsm6dso_fifo_mode_get(lsm6dso_ctx_t ctx, lsm6dso_fifo_mode_t val)
cparata	0:6d69e896ce38	5648	{
cparata	3:4274d9103f1d	5649	lsm6dso_fifo_ctrl4_t reg;
cparata	3:4274d9103f1d	5650	int32_t ret;
cparata	3:4274d9103f1d	5651
cparata	3:4274d9103f1d	5652	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5653
cparata	3:4274d9103f1d	5654	switch (reg.fifo_mode) {
cparata	3:4274d9103f1d	5655	case LSM6DSO_BYPASS_MODE:
cparata	3:4274d9103f1d	5656	*val = LSM6DSO_BYPASS_MODE;
cparata	3:4274d9103f1d	5657	break;
cparata	3:4274d9103f1d	5658	case LSM6DSO_FIFO_MODE:
cparata	3:4274d9103f1d	5659	*val = LSM6DSO_FIFO_MODE;
cparata	3:4274d9103f1d	5660	break;
cparata	3:4274d9103f1d	5661	case LSM6DSO_STREAM_TO_FIFO_MODE:
cparata	3:4274d9103f1d	5662	*val = LSM6DSO_STREAM_TO_FIFO_MODE;
cparata	3:4274d9103f1d	5663	break;
cparata	3:4274d9103f1d	5664	case LSM6DSO_BYPASS_TO_STREAM_MODE:
cparata	3:4274d9103f1d	5665	*val = LSM6DSO_BYPASS_TO_STREAM_MODE;
cparata	3:4274d9103f1d	5666	break;
cparata	3:4274d9103f1d	5667	case LSM6DSO_STREAM_MODE:
cparata	3:4274d9103f1d	5668	*val = LSM6DSO_STREAM_MODE;
cparata	3:4274d9103f1d	5669	break;
cparata	3:4274d9103f1d	5670	case LSM6DSO_BYPASS_TO_FIFO_MODE:
cparata	3:4274d9103f1d	5671	*val = LSM6DSO_BYPASS_TO_FIFO_MODE;
cparata	3:4274d9103f1d	5672	break;
cparata	3:4274d9103f1d	5673	default:
cparata	3:4274d9103f1d	5674	*val = LSM6DSO_BYPASS_MODE;
cparata	3:4274d9103f1d	5675	break;
cparata	3:4274d9103f1d	5676	}
cparata	3:4274d9103f1d	5677	return ret;
cparata	0:6d69e896ce38	5678	}
cparata	0:6d69e896ce38	5679
cparata	0:6d69e896ce38	5680	/**
cparata	0:6d69e896ce38	5681	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5682	* for temperature data.[set]
cparata	0:6d69e896ce38	5683	*
cparata	0:6d69e896ce38	5684	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5685	* @param val change the values of odr_t_batch in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5686	*
cparata	0:6d69e896ce38	5687	*/
cparata	0:6d69e896ce38	5688	int32_t lsm6dso_fifo_temp_batch_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5689	lsm6dso_odr_t_batch_t val)
cparata	0:6d69e896ce38	5690	{
cparata	3:4274d9103f1d	5691	lsm6dso_fifo_ctrl4_t reg;
cparata	3:4274d9103f1d	5692	int32_t ret;
cparata	3:4274d9103f1d	5693
cparata	3:4274d9103f1d	5694	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5695	if (ret == 0) {
cparata	3:4274d9103f1d	5696	reg.odr_t_batch = (uint8_t)val;
cparata	3:4274d9103f1d	5697	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5698	}
cparata	3:4274d9103f1d	5699	return ret;
cparata	0:6d69e896ce38	5700	}
cparata	0:6d69e896ce38	5701
cparata	0:6d69e896ce38	5702	/**
cparata	0:6d69e896ce38	5703	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5704	* for temperature data.[get]
cparata	0:6d69e896ce38	5705	*
cparata	0:6d69e896ce38	5706	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5707	* @param val Get the values of odr_t_batch in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5708	*
cparata	0:6d69e896ce38	5709	*/
cparata	0:6d69e896ce38	5710	int32_t lsm6dso_fifo_temp_batch_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5711	lsm6dso_odr_t_batch_t *val)
cparata	0:6d69e896ce38	5712	{
cparata	3:4274d9103f1d	5713	lsm6dso_fifo_ctrl4_t reg;
cparata	3:4274d9103f1d	5714	int32_t ret;
cparata	3:4274d9103f1d	5715
cparata	3:4274d9103f1d	5716	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5717
cparata	3:4274d9103f1d	5718	switch (reg.odr_t_batch) {
cparata	3:4274d9103f1d	5719	case LSM6DSO_TEMP_NOT_BATCHED:
cparata	3:4274d9103f1d	5720	*val = LSM6DSO_TEMP_NOT_BATCHED;
cparata	3:4274d9103f1d	5721	break;
cparata	3:4274d9103f1d	5722	case LSM6DSO_TEMP_BATCHED_AT_1Hz6:
cparata	3:4274d9103f1d	5723	*val = LSM6DSO_TEMP_BATCHED_AT_1Hz6;
cparata	3:4274d9103f1d	5724	break;
cparata	3:4274d9103f1d	5725	case LSM6DSO_TEMP_BATCHED_AT_12Hz5:
cparata	3:4274d9103f1d	5726	*val = LSM6DSO_TEMP_BATCHED_AT_12Hz5;
cparata	3:4274d9103f1d	5727	break;
cparata	3:4274d9103f1d	5728	case LSM6DSO_TEMP_BATCHED_AT_52Hz:
cparata	3:4274d9103f1d	5729	*val = LSM6DSO_TEMP_BATCHED_AT_52Hz;
cparata	3:4274d9103f1d	5730	break;
cparata	3:4274d9103f1d	5731	default:
cparata	3:4274d9103f1d	5732	*val = LSM6DSO_TEMP_NOT_BATCHED;
cparata	3:4274d9103f1d	5733	break;
cparata	3:4274d9103f1d	5734	}
cparata	3:4274d9103f1d	5735	return ret;
cparata	0:6d69e896ce38	5736	}
cparata	0:6d69e896ce38	5737
cparata	0:6d69e896ce38	5738	/**
cparata	0:6d69e896ce38	5739	* @brief Selects decimation for timestamp batching in FIFO.
cparata	0:6d69e896ce38	5740	* Writing rate will be the maximum rate between XL and
cparata	0:6d69e896ce38	5741	* GYRO BDR divided by decimation decoder.[set]
cparata	0:6d69e896ce38	5742	*
cparata	0:6d69e896ce38	5743	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5744	* @param val change the values of odr_ts_batch in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5745	*
cparata	0:6d69e896ce38	5746	*/
cparata	0:6d69e896ce38	5747	int32_t lsm6dso_fifo_timestamp_decimation_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5748	lsm6dso_odr_ts_batch_t val)
cparata	0:6d69e896ce38	5749	{
cparata	3:4274d9103f1d	5750	lsm6dso_fifo_ctrl4_t reg;
cparata	3:4274d9103f1d	5751	int32_t ret;
cparata	3:4274d9103f1d	5752
cparata	3:4274d9103f1d	5753	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5754	if (ret == 0) {
cparata	3:4274d9103f1d	5755	reg.odr_ts_batch = (uint8_t)val;
cparata	3:4274d9103f1d	5756	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5757	}
cparata	3:4274d9103f1d	5758	return ret;
cparata	0:6d69e896ce38	5759	}
cparata	0:6d69e896ce38	5760
cparata	0:6d69e896ce38	5761	/**
cparata	0:6d69e896ce38	5762	* @brief Selects decimation for timestamp batching in FIFO.
cparata	0:6d69e896ce38	5763	* Writing rate will be the maximum rate between XL and
cparata	0:6d69e896ce38	5764	* GYRO BDR divided by decimation decoder.[get]
cparata	0:6d69e896ce38	5765	*
cparata	0:6d69e896ce38	5766	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5767	* @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5768	*
cparata	0:6d69e896ce38	5769	*/
cparata	0:6d69e896ce38	5770	int32_t lsm6dso_fifo_timestamp_decimation_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5771	lsm6dso_odr_ts_batch_t *val)
cparata	0:6d69e896ce38	5772	{
cparata	3:4274d9103f1d	5773	lsm6dso_fifo_ctrl4_t reg;
cparata	3:4274d9103f1d	5774	int32_t ret;
cparata	3:4274d9103f1d	5775
cparata	3:4274d9103f1d	5776	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5777	switch (reg.odr_ts_batch) {
cparata	3:4274d9103f1d	5778	case LSM6DSO_NO_DECIMATION:
cparata	3:4274d9103f1d	5779	*val = LSM6DSO_NO_DECIMATION;
cparata	3:4274d9103f1d	5780	break;
cparata	3:4274d9103f1d	5781	case LSM6DSO_DEC_1:
cparata	3:4274d9103f1d	5782	*val = LSM6DSO_DEC_1;
cparata	3:4274d9103f1d	5783	break;
cparata	3:4274d9103f1d	5784	case LSM6DSO_DEC_8:
cparata	3:4274d9103f1d	5785	*val = LSM6DSO_DEC_8;
cparata	3:4274d9103f1d	5786	break;
cparata	3:4274d9103f1d	5787	case LSM6DSO_DEC_32:
cparata	3:4274d9103f1d	5788	*val = LSM6DSO_DEC_32;
cparata	3:4274d9103f1d	5789	break;
cparata	3:4274d9103f1d	5790	default:
cparata	3:4274d9103f1d	5791	*val = LSM6DSO_NO_DECIMATION;
cparata	3:4274d9103f1d	5792	break;
cparata	3:4274d9103f1d	5793	}
cparata	3:4274d9103f1d	5794	return ret;
cparata	0:6d69e896ce38	5795	}
cparata	0:6d69e896ce38	5796
cparata	0:6d69e896ce38	5797	/**
cparata	0:6d69e896ce38	5798	* @brief Selects the trigger for the internal counter of batching events
cparata	0:6d69e896ce38	5799	* between XL and gyro.[set]
cparata	0:6d69e896ce38	5800	*
cparata	0:6d69e896ce38	5801	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5802	* @param val change the values of trig_counter_bdr
cparata	0:6d69e896ce38	5803	* in reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	5804	*
cparata	0:6d69e896ce38	5805	*/
cparata	0:6d69e896ce38	5806	int32_t lsm6dso_fifo_cnt_event_batch_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5807	lsm6dso_trig_counter_bdr_t val)
cparata	0:6d69e896ce38	5808	{
cparata	3:4274d9103f1d	5809	lsm6dso_counter_bdr_reg1_t reg;
cparata	3:4274d9103f1d	5810	int32_t ret;
cparata	3:4274d9103f1d	5811
cparata	3:4274d9103f1d	5812	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5813	if (ret == 0) {
cparata	3:4274d9103f1d	5814	reg.trig_counter_bdr = (uint8_t)val;
cparata	3:4274d9103f1d	5815	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5816	}
cparata	3:4274d9103f1d	5817	return ret;
cparata	0:6d69e896ce38	5818	}
cparata	0:6d69e896ce38	5819
cparata	0:6d69e896ce38	5820	/**
cparata	0:6d69e896ce38	5821	* @brief Selects the trigger for the internal counter of batching events
cparata	0:6d69e896ce38	5822	* between XL and gyro.[get]
cparata	0:6d69e896ce38	5823	*
cparata	0:6d69e896ce38	5824	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5825	* @param val Get the values of trig_counter_bdr
cparata	0:6d69e896ce38	5826	* in reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	5827	*
cparata	0:6d69e896ce38	5828	*/
cparata	0:6d69e896ce38	5829	int32_t lsm6dso_fifo_cnt_event_batch_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5830	lsm6dso_trig_counter_bdr_t *val)
cparata	0:6d69e896ce38	5831	{
cparata	3:4274d9103f1d	5832	lsm6dso_counter_bdr_reg1_t reg;
cparata	3:4274d9103f1d	5833	int32_t ret;
cparata	3:4274d9103f1d	5834
cparata	3:4274d9103f1d	5835	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5836	switch (reg.trig_counter_bdr) {
cparata	3:4274d9103f1d	5837	case LSM6DSO_XL_BATCH_EVENT:
cparata	3:4274d9103f1d	5838	*val = LSM6DSO_XL_BATCH_EVENT;
cparata	3:4274d9103f1d	5839	break;
cparata	3:4274d9103f1d	5840	case LSM6DSO_GYRO_BATCH_EVENT:
cparata	3:4274d9103f1d	5841	*val = LSM6DSO_GYRO_BATCH_EVENT;
cparata	3:4274d9103f1d	5842	break;
cparata	3:4274d9103f1d	5843	default:
cparata	3:4274d9103f1d	5844	*val = LSM6DSO_XL_BATCH_EVENT;
cparata	3:4274d9103f1d	5845	break;
cparata	3:4274d9103f1d	5846	}
cparata	3:4274d9103f1d	5847	return ret;
cparata	0:6d69e896ce38	5848	}
cparata	0:6d69e896ce38	5849
cparata	0:6d69e896ce38	5850	/**
cparata	0:6d69e896ce38	5851	* @brief Resets the internal counter of batching vents for a single sensor.
cparata	0:6d69e896ce38	5852	* This bit is automatically reset to zero if it was set to ‘1’.[set]
cparata	0:6d69e896ce38	5853	*
cparata	0:6d69e896ce38	5854	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5855	* @param val change the values of rst_counter_bdr in
cparata	0:6d69e896ce38	5856	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	5857	*
cparata	0:6d69e896ce38	5858	*/
cparata	0:6d69e896ce38	5859	int32_t lsm6dso_rst_batch_counter_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	5860	{
cparata	3:4274d9103f1d	5861	lsm6dso_counter_bdr_reg1_t reg;
cparata	3:4274d9103f1d	5862	int32_t ret;
cparata	3:4274d9103f1d	5863
cparata	3:4274d9103f1d	5864	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5865	if (ret == 0) {
cparata	3:4274d9103f1d	5866	reg.rst_counter_bdr = val;
cparata	3:4274d9103f1d	5867	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5868	}
cparata	3:4274d9103f1d	5869	return ret;
cparata	0:6d69e896ce38	5870	}
cparata	0:6d69e896ce38	5871
cparata	0:6d69e896ce38	5872	/**
cparata	0:6d69e896ce38	5873	* @brief Resets the internal counter of batching events for a single sensor.
cparata	0:6d69e896ce38	5874	* This bit is automatically reset to zero if it was set to ‘1’.[get]
cparata	0:6d69e896ce38	5875	*
cparata	0:6d69e896ce38	5876	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5877	* @param val change the values of rst_counter_bdr in
cparata	0:6d69e896ce38	5878	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	5879	*
cparata	0:6d69e896ce38	5880	*/
cparata	0:6d69e896ce38	5881	int32_t lsm6dso_rst_batch_counter_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5882	{
cparata	3:4274d9103f1d	5883	lsm6dso_counter_bdr_reg1_t reg;
cparata	3:4274d9103f1d	5884	int32_t ret;
cparata	3:4274d9103f1d	5885
cparata	3:4274d9103f1d	5886	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	5887	*val = reg.rst_counter_bdr;
cparata	3:4274d9103f1d	5888
cparata	3:4274d9103f1d	5889	return ret;
cparata	0:6d69e896ce38	5890	}
cparata	0:6d69e896ce38	5891
cparata	0:6d69e896ce38	5892	/**
cparata	0:6d69e896ce38	5893	* @brief Batch data rate counter.[set]
cparata	0:6d69e896ce38	5894	*
cparata	0:6d69e896ce38	5895	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5896	* @param val change the values of cnt_bdr_th in
cparata	0:6d69e896ce38	5897	* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
cparata	0:6d69e896ce38	5898	*
cparata	0:6d69e896ce38	5899	*/
cparata	0:6d69e896ce38	5900	int32_t lsm6dso_batch_counter_threshold_set(lsm6dso_ctx_t *ctx, uint16_t val)
cparata	0:6d69e896ce38	5901	{
cparata	3:4274d9103f1d	5902	lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
cparata	3:4274d9103f1d	5903	lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
cparata	3:4274d9103f1d	5904	int32_t ret;
cparata	3:4274d9103f1d	5905
cparata	3:4274d9103f1d	5906	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
cparata	3:4274d9103f1d	5907	(uint8_t *)&counter_bdr_reg1, 1);
cparata	3:4274d9103f1d	5908	if (ret == 0) {
cparata	3:4274d9103f1d	5909	counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
cparata	3:4274d9103f1d	5910	counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
cparata	3:4274d9103f1d	5911	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
cparata	3:4274d9103f1d	5912	(uint8_t *)&counter_bdr_reg1, 1);
cparata	3:4274d9103f1d	5913	}
cparata	3:4274d9103f1d	5914	if (ret == 0) {
cparata	3:4274d9103f1d	5915	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
cparata	3:4274d9103f1d	5916	(uint8_t *)&counter_bdr_reg2, 1);
cparata	3:4274d9103f1d	5917	}
cparata	3:4274d9103f1d	5918	return ret;
cparata	0:6d69e896ce38	5919	}
cparata	0:6d69e896ce38	5920
cparata	0:6d69e896ce38	5921	/**
cparata	0:6d69e896ce38	5922	* @brief Batch data rate counter.[get]
cparata	0:6d69e896ce38	5923	*
cparata	0:6d69e896ce38	5924	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5925	* @param val change the values of cnt_bdr_th in
cparata	0:6d69e896ce38	5926	* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
cparata	0:6d69e896ce38	5927	*
cparata	0:6d69e896ce38	5928	*/
cparata	0:6d69e896ce38	5929	int32_t lsm6dso_batch_counter_threshold_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	0:6d69e896ce38	5930	{
cparata	3:4274d9103f1d	5931	lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
cparata	3:4274d9103f1d	5932	lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
cparata	3:4274d9103f1d	5933	int32_t ret;
cparata	3:4274d9103f1d	5934
cparata	3:4274d9103f1d	5935	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
cparata	3:4274d9103f1d	5936	(uint8_t *)&counter_bdr_reg1, 1);
cparata	3:4274d9103f1d	5937	if (ret == 0) {
cparata	3:4274d9103f1d	5938	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
cparata	3:4274d9103f1d	5939	(uint8_t *)&counter_bdr_reg2, 1);
cparata	3:4274d9103f1d	5940
cparata	3:4274d9103f1d	5941	*val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
cparata	3:4274d9103f1d	5942	+ (uint16_t)counter_bdr_reg2.cnt_bdr_th;
cparata	3:4274d9103f1d	5943	}
cparata	3:4274d9103f1d	5944
cparata	3:4274d9103f1d	5945	return ret;
cparata	0:6d69e896ce38	5946	}
cparata	0:6d69e896ce38	5947
cparata	0:6d69e896ce38	5948	/**
cparata	0:6d69e896ce38	5949	* @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get]
cparata	0:6d69e896ce38	5950	*
cparata	0:6d69e896ce38	5951	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5952	* @param val change the values of diff_fifo in reg FIFO_STATUS1
cparata	0:6d69e896ce38	5953	*
cparata	0:6d69e896ce38	5954	*/
cparata	0:6d69e896ce38	5955	int32_t lsm6dso_fifo_data_level_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	0:6d69e896ce38	5956	{
cparata	3:4274d9103f1d	5957	lsm6dso_fifo_status1_t fifo_status1;
cparata	3:4274d9103f1d	5958	lsm6dso_fifo_status2_t fifo_status2;
cparata	3:4274d9103f1d	5959	int32_t ret;
cparata	3:4274d9103f1d	5960
cparata	3:4274d9103f1d	5961	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS1,
cparata	3:4274d9103f1d	5962	(uint8_t *)&fifo_status1, 1);
cparata	3:4274d9103f1d	5963	if (ret == 0) {
cparata	3:4274d9103f1d	5964	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2,
cparata	3:4274d9103f1d	5965	(uint8_t *)&fifo_status2, 1);
cparata	3:4274d9103f1d	5966	*val = ((uint16_t)fifo_status2.diff_fifo << 8) +
cparata	3:4274d9103f1d	5967	(uint16_t)fifo_status1.diff_fifo;
cparata	3:4274d9103f1d	5968	}
cparata	3:4274d9103f1d	5969	return ret;
cparata	0:6d69e896ce38	5970	}
cparata	0:6d69e896ce38	5971
cparata	0:6d69e896ce38	5972	/**
cparata	0:6d69e896ce38	5973	* @brief FIFO status.[get]
cparata	0:6d69e896ce38	5974	*
cparata	0:6d69e896ce38	5975	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5976	* @param val registers FIFO_STATUS2
cparata	0:6d69e896ce38	5977	*
cparata	0:6d69e896ce38	5978	*/
cparata	0:6d69e896ce38	5979	int32_t lsm6dso_fifo_status_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5980	lsm6dso_fifo_status2_t *val)
cparata	0:6d69e896ce38	5981	{
cparata	3:4274d9103f1d	5982	int32_t ret;
cparata	3:4274d9103f1d	5983	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *) val, 1);
cparata	3:4274d9103f1d	5984	return ret;
cparata	0:6d69e896ce38	5985	}
cparata	0:6d69e896ce38	5986
cparata	0:6d69e896ce38	5987	/**
cparata	0:6d69e896ce38	5988	* @brief Smart FIFO full status.[get]
cparata	0:6d69e896ce38	5989	*
cparata	0:6d69e896ce38	5990	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5991	* @param val change the values of fifo_full_ia in reg FIFO_STATUS2
cparata	0:6d69e896ce38	5992	*
cparata	0:6d69e896ce38	5993	*/
cparata	0:6d69e896ce38	5994	int32_t lsm6dso_fifo_full_flag_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5995	{
cparata	3:4274d9103f1d	5996	lsm6dso_fifo_status2_t reg;
cparata	3:4274d9103f1d	5997	int32_t ret;
cparata	3:4274d9103f1d	5998
cparata	3:4274d9103f1d	5999	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6000	*val = reg.fifo_full_ia;
cparata	3:4274d9103f1d	6001
cparata	3:4274d9103f1d	6002	return ret;
cparata	0:6d69e896ce38	6003	}
cparata	0:6d69e896ce38	6004
cparata	0:6d69e896ce38	6005	/**
cparata	0:6d69e896ce38	6006	* @brief FIFO overrun status.[get]
cparata	0:6d69e896ce38	6007	*
cparata	0:6d69e896ce38	6008	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6009	* @param val change the values of fifo_over_run_latched in
cparata	0:6d69e896ce38	6010	* reg FIFO_STATUS2
cparata	0:6d69e896ce38	6011	*
cparata	0:6d69e896ce38	6012	*/
cparata	0:6d69e896ce38	6013	int32_t lsm6dso_fifo_ovr_flag_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6014	{
cparata	3:4274d9103f1d	6015	lsm6dso_fifo_status2_t reg;
cparata	3:4274d9103f1d	6016	int32_t ret;
cparata	3:4274d9103f1d	6017
cparata	3:4274d9103f1d	6018	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6019	*val = reg.fifo_ovr_ia;
cparata	3:4274d9103f1d	6020
cparata	3:4274d9103f1d	6021	return ret;
cparata	0:6d69e896ce38	6022	}
cparata	0:6d69e896ce38	6023
cparata	0:6d69e896ce38	6024	/**
cparata	0:6d69e896ce38	6025	* @brief FIFO watermark status.[get]
cparata	0:6d69e896ce38	6026	*
cparata	0:6d69e896ce38	6027	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6028	* @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
cparata	0:6d69e896ce38	6029	*
cparata	0:6d69e896ce38	6030	*/
cparata	0:6d69e896ce38	6031	int32_t lsm6dso_fifo_wtm_flag_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6032	{
cparata	3:4274d9103f1d	6033	lsm6dso_fifo_status2_t reg;
cparata	3:4274d9103f1d	6034	int32_t ret;
cparata	3:4274d9103f1d	6035
cparata	3:4274d9103f1d	6036	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6037	*val = reg.fifo_wtm_ia;
cparata	3:4274d9103f1d	6038
cparata	3:4274d9103f1d	6039	return ret;
cparata	0:6d69e896ce38	6040	}
cparata	0:6d69e896ce38	6041
cparata	0:6d69e896ce38	6042	/**
cparata	0:6d69e896ce38	6043	* @brief Identifies the sensor in FIFO_DATA_OUT.[get]
cparata	0:6d69e896ce38	6044	*
cparata	0:6d69e896ce38	6045	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6046	* @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
cparata	0:6d69e896ce38	6047	*
cparata	0:6d69e896ce38	6048	*/
cparata	0:6d69e896ce38	6049	int32_t lsm6dso_fifo_sensor_tag_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	6050	lsm6dso_fifo_tag_t *val)
cparata	0:6d69e896ce38	6051	{
cparata	3:4274d9103f1d	6052	lsm6dso_fifo_data_out_tag_t reg;
cparata	3:4274d9103f1d	6053	int32_t ret;
cparata	3:4274d9103f1d	6054
cparata	3:4274d9103f1d	6055	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_TAG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6056	switch (reg.tag_sensor) {
cparata	3:4274d9103f1d	6057	case LSM6DSO_GYRO_NC_TAG:
cparata	3:4274d9103f1d	6058	*val = LSM6DSO_GYRO_NC_TAG;
cparata	3:4274d9103f1d	6059	break;
cparata	3:4274d9103f1d	6060	case LSM6DSO_XL_NC_TAG:
cparata	3:4274d9103f1d	6061	*val = LSM6DSO_XL_NC_TAG;
cparata	3:4274d9103f1d	6062	break;
cparata	3:4274d9103f1d	6063	case LSM6DSO_TEMPERATURE_TAG:
cparata	3:4274d9103f1d	6064	*val = LSM6DSO_TEMPERATURE_TAG;
cparata	3:4274d9103f1d	6065	break;
cparata	3:4274d9103f1d	6066	case LSM6DSO_CFG_CHANGE_TAG:
cparata	3:4274d9103f1d	6067	*val = LSM6DSO_CFG_CHANGE_TAG;
cparata	3:4274d9103f1d	6068	break;
cparata	3:4274d9103f1d	6069	case LSM6DSO_XL_NC_T_2_TAG:
cparata	3:4274d9103f1d	6070	*val = LSM6DSO_XL_NC_T_2_TAG;
cparata	3:4274d9103f1d	6071	break;
cparata	3:4274d9103f1d	6072	case LSM6DSO_XL_NC_T_1_TAG:
cparata	3:4274d9103f1d	6073	*val = LSM6DSO_XL_NC_T_1_TAG;
cparata	3:4274d9103f1d	6074	break;
cparata	3:4274d9103f1d	6075	case LSM6DSO_XL_2XC_TAG:
cparata	3:4274d9103f1d	6076	*val = LSM6DSO_XL_2XC_TAG;
cparata	3:4274d9103f1d	6077	break;
cparata	3:4274d9103f1d	6078	case LSM6DSO_XL_3XC_TAG:
cparata	3:4274d9103f1d	6079	*val = LSM6DSO_XL_3XC_TAG;
cparata	3:4274d9103f1d	6080	break;
cparata	3:4274d9103f1d	6081	case LSM6DSO_GYRO_NC_T_2_TAG:
cparata	3:4274d9103f1d	6082	*val = LSM6DSO_GYRO_NC_T_2_TAG;
cparata	3:4274d9103f1d	6083	break;
cparata	3:4274d9103f1d	6084	case LSM6DSO_GYRO_NC_T_1_TAG:
cparata	3:4274d9103f1d	6085	*val = LSM6DSO_GYRO_NC_T_1_TAG;
cparata	3:4274d9103f1d	6086	break;
cparata	3:4274d9103f1d	6087	case LSM6DSO_GYRO_2XC_TAG:
cparata	3:4274d9103f1d	6088	*val = LSM6DSO_GYRO_2XC_TAG;
cparata	3:4274d9103f1d	6089	break;
cparata	3:4274d9103f1d	6090	case LSM6DSO_GYRO_3XC_TAG:
cparata	3:4274d9103f1d	6091	*val = LSM6DSO_GYRO_3XC_TAG;
cparata	3:4274d9103f1d	6092	break;
cparata	3:4274d9103f1d	6093	case LSM6DSO_SENSORHUB_SLAVE0_TAG:
cparata	3:4274d9103f1d	6094	*val = LSM6DSO_SENSORHUB_SLAVE0_TAG;
cparata	3:4274d9103f1d	6095	break;
cparata	3:4274d9103f1d	6096	case LSM6DSO_SENSORHUB_SLAVE1_TAG:
cparata	3:4274d9103f1d	6097	*val = LSM6DSO_SENSORHUB_SLAVE1_TAG;
cparata	3:4274d9103f1d	6098	break;
cparata	3:4274d9103f1d	6099	case LSM6DSO_SENSORHUB_SLAVE2_TAG:
cparata	3:4274d9103f1d	6100	*val = LSM6DSO_SENSORHUB_SLAVE2_TAG;
cparata	3:4274d9103f1d	6101	break;
cparata	3:4274d9103f1d	6102	case LSM6DSO_SENSORHUB_SLAVE3_TAG:
cparata	3:4274d9103f1d	6103	*val = LSM6DSO_SENSORHUB_SLAVE3_TAG;
cparata	3:4274d9103f1d	6104	break;
cparata	3:4274d9103f1d	6105	case LSM6DSO_STEP_CPUNTER_TAG:
cparata	3:4274d9103f1d	6106	*val = LSM6DSO_STEP_CPUNTER_TAG;
cparata	3:4274d9103f1d	6107	break;
cparata	3:4274d9103f1d	6108	case LSM6DSO_GAME_ROTATION_TAG:
cparata	3:4274d9103f1d	6109	*val = LSM6DSO_GAME_ROTATION_TAG;
cparata	3:4274d9103f1d	6110	break;
cparata	3:4274d9103f1d	6111	case LSM6DSO_GEOMAG_ROTATION_TAG:
cparata	3:4274d9103f1d	6112	*val = LSM6DSO_GEOMAG_ROTATION_TAG;
cparata	3:4274d9103f1d	6113	break;
cparata	3:4274d9103f1d	6114	case LSM6DSO_ROTATION_TAG:
cparata	3:4274d9103f1d	6115	*val = LSM6DSO_ROTATION_TAG;
cparata	3:4274d9103f1d	6116	break;
cparata	3:4274d9103f1d	6117	case LSM6DSO_SENSORHUB_NACK_TAG:
cparata	3:4274d9103f1d	6118	*val = LSM6DSO_SENSORHUB_NACK_TAG;
cparata	3:4274d9103f1d	6119	break;
cparata	3:4274d9103f1d	6120	default:
cparata	3:4274d9103f1d	6121	*val = LSM6DSO_GYRO_NC_TAG;
cparata	3:4274d9103f1d	6122	break;
cparata	3:4274d9103f1d	6123	}
cparata	3:4274d9103f1d	6124	return ret;
cparata	0:6d69e896ce38	6125	}
cparata	0:6d69e896ce38	6126
cparata	0:6d69e896ce38	6127	/**
cparata	0:6d69e896ce38	6128	* @brief : Enable FIFO batching of pedometer embedded
cparata	0:6d69e896ce38	6129	* function values.[set]
cparata	0:6d69e896ce38	6130	*
cparata	0:6d69e896ce38	6131	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6132	* @param val change the values of gbias_fifo_en in
cparata	0:6d69e896ce38	6133	* reg LSM6DSO_EMB_FUNC_FIFO_CFG
cparata	0:6d69e896ce38	6134	*
cparata	0:6d69e896ce38	6135	*/
cparata	0:6d69e896ce38	6136	int32_t lsm6dso_fifo_pedo_batch_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6137	{
cparata	3:4274d9103f1d	6138	lsm6dso_emb_func_fifo_cfg_t reg;
cparata	3:4274d9103f1d	6139	int32_t ret;
cparata	3:4274d9103f1d	6140
cparata	3:4274d9103f1d	6141	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	6142	if (ret == 0) {
cparata	3:4274d9103f1d	6143	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6144	}
cparata	3:4274d9103f1d	6145	if (ret == 0) {
cparata	3:4274d9103f1d	6146	reg.pedo_fifo_en = val;
cparata	3:4274d9103f1d	6147	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG,
cparata	3:4274d9103f1d	6148	(uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6149	}
cparata	3:4274d9103f1d	6150	if (ret == 0) {
cparata	3:4274d9103f1d	6151	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6152	}
cparata	3:4274d9103f1d	6153	return ret;
cparata	0:6d69e896ce38	6154	}
cparata	0:6d69e896ce38	6155
cparata	0:6d69e896ce38	6156	/**
cparata	0:6d69e896ce38	6157	* @brief Enable FIFO batching of pedometer embedded function values.[get]
cparata	0:6d69e896ce38	6158	*
cparata	0:6d69e896ce38	6159	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6160	* @param val change the values of pedo_fifo_en in
cparata	0:6d69e896ce38	6161	* reg LSM6DSO_EMB_FUNC_FIFO_CFG
cparata	0:6d69e896ce38	6162	*
cparata	0:6d69e896ce38	6163	*/
cparata	0:6d69e896ce38	6164	int32_t lsm6dso_fifo_pedo_batch_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6165	{
cparata	3:4274d9103f1d	6166	lsm6dso_emb_func_fifo_cfg_t reg;
cparata	3:4274d9103f1d	6167	int32_t ret;
cparata	3:4274d9103f1d	6168
cparata	3:4274d9103f1d	6169	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	6170	if (ret == 0) {
cparata	3:4274d9103f1d	6171	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6172	}
cparata	3:4274d9103f1d	6173	if (ret == 0) {
cparata	3:4274d9103f1d	6174	*val = reg.pedo_fifo_en;
cparata	3:4274d9103f1d	6175	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6176	}
cparata	3:4274d9103f1d	6177	return ret;
cparata	0:6d69e896ce38	6178	}
cparata	0:6d69e896ce38	6179
cparata	0:6d69e896ce38	6180	/**
cparata	0:6d69e896ce38	6181	* @brief Enable FIFO batching data of first slave.[set]
cparata	0:6d69e896ce38	6182	*
cparata	0:6d69e896ce38	6183	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6184	* @param val change the values of batch_ext_sens_0_en in
cparata	0:6d69e896ce38	6185	* reg SLV0_CONFIG
cparata	0:6d69e896ce38	6186	*
cparata	0:6d69e896ce38	6187	*/
cparata	0:6d69e896ce38	6188	int32_t lsm6dso_sh_batch_slave_0_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6189	{
cparata	3:4274d9103f1d	6190	lsm6dso_slv0_config_t reg;
cparata	3:4274d9103f1d	6191	int32_t ret;
cparata	3:4274d9103f1d	6192
cparata	3:4274d9103f1d	6193	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	6194	if (ret == 0) {
cparata	3:4274d9103f1d	6195	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6196	}
cparata	3:4274d9103f1d	6197	if (ret == 0) {
cparata	3:4274d9103f1d	6198	reg.batch_ext_sens_0_en = val;
cparata	3:4274d9103f1d	6199	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6200	}
cparata	3:4274d9103f1d	6201	if (ret == 0) {
cparata	3:4274d9103f1d	6202	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6203	}
cparata	3:4274d9103f1d	6204	return ret;
cparata	0:6d69e896ce38	6205	}
cparata	0:6d69e896ce38	6206
cparata	0:6d69e896ce38	6207	/**
cparata	0:6d69e896ce38	6208	* @brief Enable FIFO batching data of first slave.[get]
cparata	0:6d69e896ce38	6209	*
cparata	0:6d69e896ce38	6210	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6211	* @param val change the values of batch_ext_sens_0_en in
cparata	0:6d69e896ce38	6212	* reg SLV0_CONFIG
cparata	0:6d69e896ce38	6213	*
cparata	0:6d69e896ce38	6214	*/
cparata	0:6d69e896ce38	6215	int32_t lsm6dso_sh_batch_slave_0_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6216	{
cparata	3:4274d9103f1d	6217	lsm6dso_slv0_config_t reg;
cparata	3:4274d9103f1d	6218	int32_t ret;
cparata	3:4274d9103f1d	6219
cparata	3:4274d9103f1d	6220	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	6221	if (ret == 0) {
cparata	3:4274d9103f1d	6222	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6223	}
cparata	3:4274d9103f1d	6224	if (ret == 0) {
cparata	3:4274d9103f1d	6225	*val = reg.batch_ext_sens_0_en;
cparata	3:4274d9103f1d	6226	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6227	}
cparata	3:4274d9103f1d	6228	return ret;
cparata	0:6d69e896ce38	6229	}
cparata	0:6d69e896ce38	6230
cparata	0:6d69e896ce38	6231	/**
cparata	0:6d69e896ce38	6232	* @brief Enable FIFO batching data of second slave.[set]
cparata	0:6d69e896ce38	6233	*
cparata	0:6d69e896ce38	6234	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6235	* @param val change the values of batch_ext_sens_1_en in
cparata	0:6d69e896ce38	6236	* reg SLV1_CONFIG
cparata	0:6d69e896ce38	6237	*
cparata	0:6d69e896ce38	6238	*/
cparata	0:6d69e896ce38	6239	int32_t lsm6dso_sh_batch_slave_1_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6240	{
cparata	3:4274d9103f1d	6241	lsm6dso_slv1_config_t reg;
cparata	3:4274d9103f1d	6242	int32_t ret;
cparata	3:4274d9103f1d	6243
cparata	3:4274d9103f1d	6244	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	6245	if (ret == 0) {
cparata	3:4274d9103f1d	6246	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6247	}
cparata	3:4274d9103f1d	6248	if (ret == 0) {
cparata	3:4274d9103f1d	6249	reg.batch_ext_sens_1_en = val;
cparata	3:4274d9103f1d	6250	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6251	}
cparata	3:4274d9103f1d	6252	if (ret == 0) {
cparata	3:4274d9103f1d	6253	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6254	}
cparata	3:4274d9103f1d	6255
cparata	3:4274d9103f1d	6256	return ret;
cparata	0:6d69e896ce38	6257	}
cparata	0:6d69e896ce38	6258
cparata	0:6d69e896ce38	6259	/**
cparata	0:6d69e896ce38	6260	* @brief Enable FIFO batching data of second slave.[get]
cparata	0:6d69e896ce38	6261	*
cparata	0:6d69e896ce38	6262	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6263	* @param val change the values of batch_ext_sens_1_en in
cparata	0:6d69e896ce38	6264	* reg SLV1_CONFIG
cparata	0:6d69e896ce38	6265	*
cparata	0:6d69e896ce38	6266	*/
cparata	0:6d69e896ce38	6267	int32_t lsm6dso_sh_batch_slave_1_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6268	{
cparata	3:4274d9103f1d	6269	lsm6dso_slv1_config_t reg;
cparata	3:4274d9103f1d	6270	int32_t ret;
cparata	3:4274d9103f1d	6271
cparata	3:4274d9103f1d	6272	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	6273	if (ret == 0) {
cparata	3:4274d9103f1d	6274	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6275	*val = reg.batch_ext_sens_1_en;
cparata	3:4274d9103f1d	6276	}
cparata	3:4274d9103f1d	6277	if (ret == 0) {
cparata	3:4274d9103f1d	6278	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6279	}
cparata	3:4274d9103f1d	6280	return ret;
cparata	0:6d69e896ce38	6281	}
cparata	0:6d69e896ce38	6282
cparata	0:6d69e896ce38	6283	/**
cparata	0:6d69e896ce38	6284	* @brief Enable FIFO batching data of third slave.[set]
cparata	0:6d69e896ce38	6285	*
cparata	0:6d69e896ce38	6286	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6287	* @param val change the values of batch_ext_sens_2_en in
cparata	0:6d69e896ce38	6288	* reg SLV2_CONFIG
cparata	0:6d69e896ce38	6289	*
cparata	0:6d69e896ce38	6290	*/
cparata	0:6d69e896ce38	6291	int32_t lsm6dso_sh_batch_slave_2_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6292	{
cparata	3:4274d9103f1d	6293	lsm6dso_slv2_config_t reg;
cparata	3:4274d9103f1d	6294	int32_t ret;
cparata	3:4274d9103f1d	6295
cparata	3:4274d9103f1d	6296	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	6297
cparata	3:4274d9103f1d	6298	if (ret == 0) {
cparata	3:4274d9103f1d	6299	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6300	}
cparata	3:4274d9103f1d	6301	if (ret == 0) {
cparata	3:4274d9103f1d	6302	reg.batch_ext_sens_2_en = val;
cparata	3:4274d9103f1d	6303	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6304	}
cparata	3:4274d9103f1d	6305	if (ret == 0) {
cparata	3:4274d9103f1d	6306	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6307	}
cparata	3:4274d9103f1d	6308	return ret;
cparata	0:6d69e896ce38	6309	}
cparata	0:6d69e896ce38	6310
cparata	0:6d69e896ce38	6311	/**
cparata	0:6d69e896ce38	6312	* @brief Enable FIFO batching data of third slave.[get]
cparata	0:6d69e896ce38	6313	*
cparata	0:6d69e896ce38	6314	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6315	* @param val change the values of batch_ext_sens_2_en in
cparata	0:6d69e896ce38	6316	* reg SLV2_CONFIG
cparata	0:6d69e896ce38	6317	*
cparata	0:6d69e896ce38	6318	*/
cparata	0:6d69e896ce38	6319	int32_t lsm6dso_sh_batch_slave_2_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6320	{
cparata	3:4274d9103f1d	6321	lsm6dso_slv2_config_t reg;
cparata	3:4274d9103f1d	6322	int32_t ret;
cparata	3:4274d9103f1d	6323
cparata	3:4274d9103f1d	6324	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	6325	if (ret == 0) {
cparata	3:4274d9103f1d	6326	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6327	}
cparata	3:4274d9103f1d	6328	if (ret == 0) {
cparata	3:4274d9103f1d	6329	*val = reg.batch_ext_sens_2_en;
cparata	3:4274d9103f1d	6330	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6331	}
cparata	3:4274d9103f1d	6332
cparata	3:4274d9103f1d	6333	return ret;
cparata	0:6d69e896ce38	6334	}
cparata	0:6d69e896ce38	6335
cparata	0:6d69e896ce38	6336	/**
cparata	0:6d69e896ce38	6337	* @brief Enable FIFO batching data of fourth slave.[set]
cparata	0:6d69e896ce38	6338	*
cparata	0:6d69e896ce38	6339	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6340	* @param val change the values of batch_ext_sens_3_en
cparata	0:6d69e896ce38	6341	* in reg SLV3_CONFIG
cparata	0:6d69e896ce38	6342	*
cparata	0:6d69e896ce38	6343	*/
cparata	0:6d69e896ce38	6344	int32_t lsm6dso_sh_batch_slave_3_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6345	{
cparata	3:4274d9103f1d	6346	lsm6dso_slv3_config_t reg;
cparata	3:4274d9103f1d	6347	int32_t ret;
cparata	3:4274d9103f1d	6348
cparata	3:4274d9103f1d	6349	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	6350	if (ret == 0) {
cparata	3:4274d9103f1d	6351	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6352	}
cparata	3:4274d9103f1d	6353	if (ret == 0) {
cparata	3:4274d9103f1d	6354	reg.batch_ext_sens_3_en = val;
cparata	3:4274d9103f1d	6355	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6356	}
cparata	3:4274d9103f1d	6357	if (ret == 0) {
cparata	3:4274d9103f1d	6358	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6359	}
cparata	3:4274d9103f1d	6360
cparata	3:4274d9103f1d	6361	return ret;
cparata	0:6d69e896ce38	6362	}
cparata	0:6d69e896ce38	6363
cparata	0:6d69e896ce38	6364	/**
cparata	0:6d69e896ce38	6365	* @brief Enable FIFO batching data of fourth slave.[get]
cparata	0:6d69e896ce38	6366	*
cparata	0:6d69e896ce38	6367	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6368	* @param val change the values of batch_ext_sens_3_en in
cparata	0:6d69e896ce38	6369	* reg SLV3_CONFIG
cparata	0:6d69e896ce38	6370	*
cparata	0:6d69e896ce38	6371	*/
cparata	0:6d69e896ce38	6372	int32_t lsm6dso_sh_batch_slave_3_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6373	{
cparata	3:4274d9103f1d	6374	lsm6dso_slv3_config_t reg;
cparata	3:4274d9103f1d	6375	int32_t ret;
cparata	3:4274d9103f1d	6376
cparata	3:4274d9103f1d	6377	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	6378	if (ret == 0) {
cparata	3:4274d9103f1d	6379	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6380	}
cparata	3:4274d9103f1d	6381	if (ret == 0) {
cparata	3:4274d9103f1d	6382	*val = reg.batch_ext_sens_3_en;
cparata	3:4274d9103f1d	6383	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6384	}
cparata	3:4274d9103f1d	6385
cparata	3:4274d9103f1d	6386	return ret;
cparata	0:6d69e896ce38	6387	}
cparata	0:6d69e896ce38	6388
cparata	0:6d69e896ce38	6389	/**
cparata	0:6d69e896ce38	6390	* @}
cparata	0:6d69e896ce38	6391	*
cparata	0:6d69e896ce38	6392	*/
cparata	0:6d69e896ce38	6393
cparata	0:6d69e896ce38	6394	/**
cparata	0:6d69e896ce38	6395	* @defgroup LSM6DSO_DEN_functionality
cparata	0:6d69e896ce38	6396	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	6397	* DEN functionality.
cparata	0:6d69e896ce38	6398	* @{
cparata	0:6d69e896ce38	6399	*
cparata	0:6d69e896ce38	6400	*/
cparata	0:6d69e896ce38	6401
cparata	0:6d69e896ce38	6402	/**
cparata	0:6d69e896ce38	6403	* @brief DEN functionality marking mode.[set]
cparata	0:6d69e896ce38	6404	*
cparata	0:6d69e896ce38	6405	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6406	* @param val change the values of den_mode in reg CTRL6_C
cparata	0:6d69e896ce38	6407	*
cparata	0:6d69e896ce38	6408	*/
cparata	0:6d69e896ce38	6409	int32_t lsm6dso_den_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_den_mode_t val)
cparata	0:6d69e896ce38	6410	{
cparata	3:4274d9103f1d	6411	lsm6dso_ctrl6_c_t reg;
cparata	3:4274d9103f1d	6412	int32_t ret;
cparata	3:4274d9103f1d	6413
cparata	3:4274d9103f1d	6414	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6415	if (ret == 0) {
cparata	3:4274d9103f1d	6416	reg.den_mode = (uint8_t)val;
cparata	3:4274d9103f1d	6417	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6418	}
cparata	3:4274d9103f1d	6419
cparata	3:4274d9103f1d	6420	return ret;
cparata	0:6d69e896ce38	6421	}
cparata	0:6d69e896ce38	6422
cparata	0:6d69e896ce38	6423	/**
cparata	0:6d69e896ce38	6424	* @brief DEN functionality marking mode.[get]
cparata	0:6d69e896ce38	6425	*
cparata	0:6d69e896ce38	6426	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6427	* @param val Get the values of den_mode in reg CTRL6_C
cparata	0:6d69e896ce38	6428	*
cparata	0:6d69e896ce38	6429	*/
cparata	0:6d69e896ce38	6430	int32_t lsm6dso_den_mode_get(lsm6dso_ctx_t ctx, lsm6dso_den_mode_t val)
cparata	0:6d69e896ce38	6431	{
cparata	3:4274d9103f1d	6432	lsm6dso_ctrl6_c_t reg;
cparata	3:4274d9103f1d	6433	int32_t ret;
cparata	3:4274d9103f1d	6434
cparata	3:4274d9103f1d	6435	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6436
cparata	3:4274d9103f1d	6437	switch (reg.den_mode) {
cparata	3:4274d9103f1d	6438	case LSM6DSO_DEN_DISABLE:
cparata	3:4274d9103f1d	6439	*val = LSM6DSO_DEN_DISABLE;
cparata	3:4274d9103f1d	6440	break;
cparata	3:4274d9103f1d	6441	case LSM6DSO_LEVEL_FIFO:
cparata	3:4274d9103f1d	6442	*val = LSM6DSO_LEVEL_FIFO;
cparata	3:4274d9103f1d	6443	break;
cparata	3:4274d9103f1d	6444	case LSM6DSO_LEVEL_LETCHED:
cparata	3:4274d9103f1d	6445	*val = LSM6DSO_LEVEL_LETCHED;
cparata	3:4274d9103f1d	6446	break;
cparata	3:4274d9103f1d	6447	case LSM6DSO_LEVEL_TRIGGER:
cparata	3:4274d9103f1d	6448	*val = LSM6DSO_LEVEL_TRIGGER;
cparata	3:4274d9103f1d	6449	break;
cparata	3:4274d9103f1d	6450	case LSM6DSO_EDGE_TRIGGER:
cparata	3:4274d9103f1d	6451	*val = LSM6DSO_EDGE_TRIGGER;
cparata	3:4274d9103f1d	6452	break;
cparata	3:4274d9103f1d	6453	default:
cparata	3:4274d9103f1d	6454	*val = LSM6DSO_DEN_DISABLE;
cparata	3:4274d9103f1d	6455	break;
cparata	3:4274d9103f1d	6456	}
cparata	3:4274d9103f1d	6457	return ret;
cparata	0:6d69e896ce38	6458	}
cparata	0:6d69e896ce38	6459
cparata	0:6d69e896ce38	6460	/**
cparata	0:6d69e896ce38	6461	* @brief DEN active level configuration.[set]
cparata	0:6d69e896ce38	6462	*
cparata	0:6d69e896ce38	6463	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6464	* @param val change the values of den_lh in reg CTRL9_XL
cparata	0:6d69e896ce38	6465	*
cparata	0:6d69e896ce38	6466	*/
cparata	0:6d69e896ce38	6467	int32_t lsm6dso_den_polarity_set(lsm6dso_ctx_t *ctx, lsm6dso_den_lh_t val)
cparata	0:6d69e896ce38	6468	{
cparata	3:4274d9103f1d	6469	lsm6dso_ctrl9_xl_t reg;
cparata	3:4274d9103f1d	6470	int32_t ret;
cparata	3:4274d9103f1d	6471
cparata	3:4274d9103f1d	6472	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6473	if (ret == 0) {
cparata	3:4274d9103f1d	6474	reg.den_lh = (uint8_t)val;
cparata	3:4274d9103f1d	6475	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6476	}
cparata	3:4274d9103f1d	6477
cparata	3:4274d9103f1d	6478	return ret;
cparata	0:6d69e896ce38	6479	}
cparata	0:6d69e896ce38	6480
cparata	0:6d69e896ce38	6481	/**
cparata	0:6d69e896ce38	6482	* @brief DEN active level configuration.[get]
cparata	0:6d69e896ce38	6483	*
cparata	0:6d69e896ce38	6484	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6485	* @param val Get the values of den_lh in reg CTRL9_XL
cparata	0:6d69e896ce38	6486	*
cparata	0:6d69e896ce38	6487	*/
cparata	0:6d69e896ce38	6488	int32_t lsm6dso_den_polarity_get(lsm6dso_ctx_t ctx, lsm6dso_den_lh_t val)
cparata	0:6d69e896ce38	6489	{
cparata	3:4274d9103f1d	6490	lsm6dso_ctrl9_xl_t reg;
cparata	3:4274d9103f1d	6491	int32_t ret;
cparata	3:4274d9103f1d	6492
cparata	3:4274d9103f1d	6493	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6494
cparata	3:4274d9103f1d	6495	switch (reg.den_lh) {
cparata	3:4274d9103f1d	6496	case LSM6DSO_DEN_ACT_LOW:
cparata	3:4274d9103f1d	6497	*val = LSM6DSO_DEN_ACT_LOW;
cparata	3:4274d9103f1d	6498	break;
cparata	3:4274d9103f1d	6499	case LSM6DSO_DEN_ACT_HIGH:
cparata	3:4274d9103f1d	6500	*val = LSM6DSO_DEN_ACT_HIGH;
cparata	3:4274d9103f1d	6501	break;
cparata	3:4274d9103f1d	6502	default:
cparata	3:4274d9103f1d	6503	*val = LSM6DSO_DEN_ACT_LOW;
cparata	3:4274d9103f1d	6504	break;
cparata	3:4274d9103f1d	6505	}
cparata	3:4274d9103f1d	6506	return ret;
cparata	0:6d69e896ce38	6507	}
cparata	0:6d69e896ce38	6508
cparata	0:6d69e896ce38	6509	/**
cparata	0:6d69e896ce38	6510	* @brief DEN enable.[set]
cparata	0:6d69e896ce38	6511	*
cparata	0:6d69e896ce38	6512	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6513	* @param val change the values of den_xl_g in reg CTRL9_XL
cparata	0:6d69e896ce38	6514	*
cparata	0:6d69e896ce38	6515	*/
cparata	0:6d69e896ce38	6516	int32_t lsm6dso_den_enable_set(lsm6dso_ctx_t *ctx, lsm6dso_den_xl_g_t val)
cparata	0:6d69e896ce38	6517	{
cparata	3:4274d9103f1d	6518	lsm6dso_ctrl9_xl_t reg;
cparata	3:4274d9103f1d	6519	int32_t ret;
cparata	3:4274d9103f1d	6520
cparata	3:4274d9103f1d	6521	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6522	if (ret == 0) {
cparata	3:4274d9103f1d	6523	reg.den_xl_g = (uint8_t)val;
cparata	3:4274d9103f1d	6524	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6525	}
cparata	3:4274d9103f1d	6526
cparata	3:4274d9103f1d	6527	return ret;
cparata	0:6d69e896ce38	6528	}
cparata	0:6d69e896ce38	6529
cparata	0:6d69e896ce38	6530	/**
cparata	0:6d69e896ce38	6531	* @brief DEN enable.[get]
cparata	0:6d69e896ce38	6532	*
cparata	0:6d69e896ce38	6533	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6534	* @param val Get the values of den_xl_g in reg CTRL9_XL
cparata	0:6d69e896ce38	6535	*
cparata	0:6d69e896ce38	6536	*/
cparata	0:6d69e896ce38	6537	int32_t lsm6dso_den_enable_get(lsm6dso_ctx_t ctx, lsm6dso_den_xl_g_t val)
cparata	0:6d69e896ce38	6538	{
cparata	3:4274d9103f1d	6539	lsm6dso_ctrl9_xl_t reg;
cparata	3:4274d9103f1d	6540	int32_t ret;
cparata	3:4274d9103f1d	6541
cparata	3:4274d9103f1d	6542	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6543
cparata	3:4274d9103f1d	6544	switch (reg.den_xl_g) {
cparata	3:4274d9103f1d	6545	case LSM6DSO_STAMP_IN_GY_DATA:
cparata	3:4274d9103f1d	6546	*val = LSM6DSO_STAMP_IN_GY_DATA;
cparata	3:4274d9103f1d	6547	break;
cparata	3:4274d9103f1d	6548	case LSM6DSO_STAMP_IN_XL_DATA:
cparata	3:4274d9103f1d	6549	*val = LSM6DSO_STAMP_IN_XL_DATA;
cparata	3:4274d9103f1d	6550	break;
cparata	3:4274d9103f1d	6551	case LSM6DSO_STAMP_IN_GY_XL_DATA:
cparata	3:4274d9103f1d	6552	*val = LSM6DSO_STAMP_IN_GY_XL_DATA;
cparata	3:4274d9103f1d	6553	break;
cparata	3:4274d9103f1d	6554	default:
cparata	3:4274d9103f1d	6555	*val = LSM6DSO_STAMP_IN_GY_DATA;
cparata	3:4274d9103f1d	6556	break;
cparata	3:4274d9103f1d	6557	}
cparata	3:4274d9103f1d	6558	return ret;
cparata	0:6d69e896ce38	6559	}
cparata	0:6d69e896ce38	6560
cparata	0:6d69e896ce38	6561	/**
cparata	0:6d69e896ce38	6562	* @brief DEN value stored in LSB of X-axis.[set]
cparata	0:6d69e896ce38	6563	*
cparata	0:6d69e896ce38	6564	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6565	* @param val change the values of den_z in reg CTRL9_XL
cparata	0:6d69e896ce38	6566	*
cparata	0:6d69e896ce38	6567	*/
cparata	0:6d69e896ce38	6568	int32_t lsm6dso_den_mark_axis_x_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6569	{
cparata	3:4274d9103f1d	6570	lsm6dso_ctrl9_xl_t reg;
cparata	3:4274d9103f1d	6571	int32_t ret;
cparata	3:4274d9103f1d	6572
cparata	3:4274d9103f1d	6573	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6574	if (ret == 0) {
cparata	3:4274d9103f1d	6575	reg.den_z = val;
cparata	3:4274d9103f1d	6576	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6577	}
cparata	3:4274d9103f1d	6578
cparata	3:4274d9103f1d	6579	return ret;
cparata	0:6d69e896ce38	6580	}
cparata	0:6d69e896ce38	6581
cparata	0:6d69e896ce38	6582	/**
cparata	0:6d69e896ce38	6583	* @brief DEN value stored in LSB of X-axis.[get]
cparata	0:6d69e896ce38	6584	*
cparata	0:6d69e896ce38	6585	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6586	* @param val change the values of den_z in reg CTRL9_XL
cparata	0:6d69e896ce38	6587	*
cparata	0:6d69e896ce38	6588	*/
cparata	0:6d69e896ce38	6589	int32_t lsm6dso_den_mark_axis_x_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6590	{
cparata	3:4274d9103f1d	6591	lsm6dso_ctrl9_xl_t reg;
cparata	3:4274d9103f1d	6592	int32_t ret;
cparata	3:4274d9103f1d	6593
cparata	3:4274d9103f1d	6594	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6595	*val = reg.den_z;
cparata	3:4274d9103f1d	6596
cparata	3:4274d9103f1d	6597	return ret;
cparata	0:6d69e896ce38	6598	}
cparata	0:6d69e896ce38	6599
cparata	0:6d69e896ce38	6600	/**
cparata	0:6d69e896ce38	6601	* @brief DEN value stored in LSB of Y-axis.[set]
cparata	0:6d69e896ce38	6602	*
cparata	0:6d69e896ce38	6603	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6604	* @param val change the values of den_y in reg CTRL9_XL
cparata	0:6d69e896ce38	6605	*
cparata	0:6d69e896ce38	6606	*/
cparata	0:6d69e896ce38	6607	int32_t lsm6dso_den_mark_axis_y_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6608	{
cparata	3:4274d9103f1d	6609	lsm6dso_ctrl9_xl_t reg;
cparata	3:4274d9103f1d	6610	int32_t ret;
cparata	3:4274d9103f1d	6611
cparata	3:4274d9103f1d	6612	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6613	if (ret == 0) {
cparata	3:4274d9103f1d	6614	reg.den_y = val;
cparata	3:4274d9103f1d	6615	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6616	}
cparata	3:4274d9103f1d	6617
cparata	3:4274d9103f1d	6618	return ret;
cparata	0:6d69e896ce38	6619	}
cparata	0:6d69e896ce38	6620
cparata	0:6d69e896ce38	6621	/**
cparata	0:6d69e896ce38	6622	* @brief DEN value stored in LSB of Y-axis.[get]
cparata	0:6d69e896ce38	6623	*
cparata	0:6d69e896ce38	6624	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6625	* @param val change the values of den_y in reg CTRL9_XL
cparata	0:6d69e896ce38	6626	*
cparata	0:6d69e896ce38	6627	*/
cparata	0:6d69e896ce38	6628	int32_t lsm6dso_den_mark_axis_y_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6629	{
cparata	3:4274d9103f1d	6630	lsm6dso_ctrl9_xl_t reg;
cparata	3:4274d9103f1d	6631	int32_t ret;
cparata	3:4274d9103f1d	6632
cparata	3:4274d9103f1d	6633	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6634	*val = reg.den_y;
cparata	3:4274d9103f1d	6635
cparata	3:4274d9103f1d	6636	return ret;
cparata	0:6d69e896ce38	6637	}
cparata	0:6d69e896ce38	6638
cparata	0:6d69e896ce38	6639	/**
cparata	0:6d69e896ce38	6640	* @brief DEN value stored in LSB of Z-axis.[set]
cparata	0:6d69e896ce38	6641	*
cparata	0:6d69e896ce38	6642	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6643	* @param val change the values of den_x in reg CTRL9_XL
cparata	0:6d69e896ce38	6644	*
cparata	0:6d69e896ce38	6645	*/
cparata	0:6d69e896ce38	6646	int32_t lsm6dso_den_mark_axis_z_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6647	{
cparata	3:4274d9103f1d	6648	lsm6dso_ctrl9_xl_t reg;
cparata	3:4274d9103f1d	6649	int32_t ret;
cparata	3:4274d9103f1d	6650
cparata	3:4274d9103f1d	6651	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6652	if (ret == 0) {
cparata	3:4274d9103f1d	6653	reg.den_x = val;
cparata	3:4274d9103f1d	6654	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6655	}
cparata	3:4274d9103f1d	6656
cparata	3:4274d9103f1d	6657	return ret;
cparata	0:6d69e896ce38	6658	}
cparata	0:6d69e896ce38	6659
cparata	0:6d69e896ce38	6660	/**
cparata	0:6d69e896ce38	6661	* @brief DEN value stored in LSB of Z-axis.[get]
cparata	0:6d69e896ce38	6662	*
cparata	0:6d69e896ce38	6663	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6664	* @param val change the values of den_x in reg CTRL9_XL
cparata	0:6d69e896ce38	6665	*
cparata	0:6d69e896ce38	6666	*/
cparata	0:6d69e896ce38	6667	int32_t lsm6dso_den_mark_axis_z_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6668	{
cparata	3:4274d9103f1d	6669	lsm6dso_ctrl9_xl_t reg;
cparata	3:4274d9103f1d	6670	int32_t ret;
cparata	3:4274d9103f1d	6671
cparata	3:4274d9103f1d	6672	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6673	*val = reg.den_x;
cparata	3:4274d9103f1d	6674
cparata	3:4274d9103f1d	6675	return ret;
cparata	0:6d69e896ce38	6676	}
cparata	0:6d69e896ce38	6677
cparata	0:6d69e896ce38	6678	/**
cparata	0:6d69e896ce38	6679	* @}
cparata	0:6d69e896ce38	6680	*
cparata	0:6d69e896ce38	6681	*/
cparata	0:6d69e896ce38	6682
cparata	0:6d69e896ce38	6683	/**
cparata	0:6d69e896ce38	6684	* @defgroup LSM6DSO_Pedometer
cparata	0:6d69e896ce38	6685	* @brief This section groups all the functions that manage pedometer.
cparata	0:6d69e896ce38	6686	* @{
cparata	0:6d69e896ce38	6687	*
cparata	0:6d69e896ce38	6688	*/
cparata	0:6d69e896ce38	6689
cparata	0:6d69e896ce38	6690	/**
cparata	0:6d69e896ce38	6691	* @brief Enable pedometer algorithm.[set]
cparata	0:6d69e896ce38	6692	*
cparata	0:6d69e896ce38	6693	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6694	* @param val turn on and configure pedometer
cparata	0:6d69e896ce38	6695	*
cparata	0:6d69e896ce38	6696	*/
cparata	0:6d69e896ce38	6697	int32_t lsm6dso_pedo_sens_set(lsm6dso_ctx_t *ctx, lsm6dso_pedo_md_t val)
cparata	0:6d69e896ce38	6698	{
cparata	3:4274d9103f1d	6699	lsm6dso_emb_func_en_a_t emb_func_en_a;
cparata	3:4274d9103f1d	6700	lsm6dso_emb_func_en_b_t emb_func_en_b;
cparata	3:4274d9103f1d	6701	lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
cparata	3:4274d9103f1d	6702	int32_t ret;
cparata	3:4274d9103f1d	6703
cparata	3:4274d9103f1d	6704	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
cparata	3:4274d9103f1d	6705	(uint8_t *)&pedo_cmd_reg);
cparata	3:4274d9103f1d	6706	if (ret == 0) {
cparata	3:4274d9103f1d	6707	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	6708	}
cparata	3:4274d9103f1d	6709	if (ret == 0) {
cparata	3:4274d9103f1d	6710	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
cparata	3:4274d9103f1d	6711	(uint8_t *)&emb_func_en_a, 1);
cparata	3:4274d9103f1d	6712	}
cparata	3:4274d9103f1d	6713	if (ret == 0) {
cparata	3:4274d9103f1d	6714	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	3:4274d9103f1d	6715	(uint8_t *)&emb_func_en_b, 1);
cparata	3:4274d9103f1d	6716
cparata	3:4274d9103f1d	6717	emb_func_en_a.pedo_en = (uint8_t)val & 0x01U;
cparata	3:4274d9103f1d	6718	emb_func_en_b.pedo_adv_en = ((uint8_t)val & 0x02U) >> 1;
cparata	3:4274d9103f1d	6719	pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4;
cparata	3:4274d9103f1d	6720	pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5;
cparata	3:4274d9103f1d	6721	}
cparata	3:4274d9103f1d	6722	if (ret == 0) {
cparata	3:4274d9103f1d	6723	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
cparata	3:4274d9103f1d	6724	(uint8_t *)&emb_func_en_a, 1);
cparata	3:4274d9103f1d	6725	}
cparata	3:4274d9103f1d	6726	if (ret == 0) {
cparata	3:4274d9103f1d	6727	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	3:4274d9103f1d	6728	(uint8_t *)&emb_func_en_b, 1);
cparata	3:4274d9103f1d	6729	}
cparata	3:4274d9103f1d	6730	if (ret == 0) {
cparata	3:4274d9103f1d	6731	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6732	}
cparata	3:4274d9103f1d	6733	if (ret == 0) {
cparata	3:4274d9103f1d	6734	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
cparata	3:4274d9103f1d	6735	(uint8_t *)&pedo_cmd_reg);
cparata	3:4274d9103f1d	6736	}
cparata	3:4274d9103f1d	6737	return ret;
cparata	0:6d69e896ce38	6738	}
cparata	0:6d69e896ce38	6739
cparata	0:6d69e896ce38	6740	/**
cparata	0:6d69e896ce38	6741	* @brief Enable pedometer algorithm.[get]
cparata	0:6d69e896ce38	6742	*
cparata	0:6d69e896ce38	6743	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6744	* @param val turn on and configure pedometer
cparata	0:6d69e896ce38	6745	*
cparata	0:6d69e896ce38	6746	*/
cparata	0:6d69e896ce38	6747	int32_t lsm6dso_pedo_sens_get(lsm6dso_ctx_t ctx, lsm6dso_pedo_md_t val)
cparata	0:6d69e896ce38	6748	{
cparata	3:4274d9103f1d	6749	lsm6dso_emb_func_en_a_t emb_func_en_a;
cparata	3:4274d9103f1d	6750	lsm6dso_emb_func_en_b_t emb_func_en_b;
cparata	3:4274d9103f1d	6751	lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
cparata	3:4274d9103f1d	6752	int32_t ret;
cparata	3:4274d9103f1d	6753
cparata	3:4274d9103f1d	6754	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
cparata	3:4274d9103f1d	6755	(uint8_t *)&pedo_cmd_reg);
cparata	3:4274d9103f1d	6756	if (ret == 0) {
cparata	3:4274d9103f1d	6757	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	6758	}
cparata	3:4274d9103f1d	6759	if (ret == 0) {
cparata	3:4274d9103f1d	6760	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
cparata	3:4274d9103f1d	6761	(uint8_t *)&emb_func_en_a, 1);
cparata	3:4274d9103f1d	6762	}
cparata	3:4274d9103f1d	6763	if (ret == 0) {
cparata	3:4274d9103f1d	6764	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	3:4274d9103f1d	6765	(uint8_t *)&emb_func_en_b, 1);
cparata	3:4274d9103f1d	6766	}
cparata	3:4274d9103f1d	6767	if (ret == 0) {
cparata	3:4274d9103f1d	6768	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6769	}
cparata	3:4274d9103f1d	6770	switch ((pedo_cmd_reg.ad_det_en << 5) \| (pedo_cmd_reg.fp_rejection_en << 4) \|
cparata	3:4274d9103f1d	6771	(emb_func_en_b.pedo_adv_en << 1) \| emb_func_en_a.pedo_en) {
cparata	3:4274d9103f1d	6772	case LSM6DSO_PEDO_DISABLE:
cparata	3:4274d9103f1d	6773	*val = LSM6DSO_PEDO_DISABLE;
cparata	3:4274d9103f1d	6774	break;
cparata	3:4274d9103f1d	6775	case LSM6DSO_PEDO_BASE_MODE:
cparata	3:4274d9103f1d	6776	*val = LSM6DSO_PEDO_BASE_MODE;
cparata	3:4274d9103f1d	6777	break;
cparata	3:4274d9103f1d	6778	case LSM6DSO_PEDO_ADV_MODE:
cparata	3:4274d9103f1d	6779	*val = LSM6DSO_PEDO_ADV_MODE;
cparata	3:4274d9103f1d	6780	break;
cparata	3:4274d9103f1d	6781	case LSM6DSO_FALSE_STEP_REJ:
cparata	3:4274d9103f1d	6782	*val = LSM6DSO_FALSE_STEP_REJ;
cparata	3:4274d9103f1d	6783	break;
cparata	3:4274d9103f1d	6784	case LSM6DSO_FALSE_STEP_REJ_ADV_MODE:
cparata	3:4274d9103f1d	6785	*val = LSM6DSO_FALSE_STEP_REJ_ADV_MODE;
cparata	3:4274d9103f1d	6786	break;
cparata	3:4274d9103f1d	6787	default:
cparata	3:4274d9103f1d	6788	*val = LSM6DSO_PEDO_DISABLE;
cparata	3:4274d9103f1d	6789	break;
cparata	3:4274d9103f1d	6790	}
cparata	3:4274d9103f1d	6791	return ret;
cparata	0:6d69e896ce38	6792	}
cparata	0:6d69e896ce38	6793
cparata	0:6d69e896ce38	6794	/**
cparata	0:6d69e896ce38	6795	* @brief Interrupt status bit for step detection.[get]
cparata	0:6d69e896ce38	6796	*
cparata	0:6d69e896ce38	6797	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6798	* @param val change the values of is_step_det in reg EMB_FUNC_STATUS
cparata	0:6d69e896ce38	6799	*
cparata	0:6d69e896ce38	6800	*/
cparata	0:6d69e896ce38	6801	int32_t lsm6dso_pedo_step_detect_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6802	{
cparata	3:4274d9103f1d	6803	lsm6dso_emb_func_status_t reg;
cparata	3:4274d9103f1d	6804	int32_t ret;
cparata	3:4274d9103f1d	6805
cparata	3:4274d9103f1d	6806	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	6807	if (ret == 0) {
cparata	3:4274d9103f1d	6808	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6809	}
cparata	3:4274d9103f1d	6810	if (ret == 0) {
cparata	3:4274d9103f1d	6811	*val = reg.is_step_det;
cparata	3:4274d9103f1d	6812	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6813	}
cparata	3:4274d9103f1d	6814
cparata	3:4274d9103f1d	6815	return ret;
cparata	0:6d69e896ce38	6816	}
cparata	0:6d69e896ce38	6817
cparata	0:6d69e896ce38	6818	/**
cparata	0:6d69e896ce38	6819	* @brief Pedometer debounce configuration register (r/w).[set]
cparata	0:6d69e896ce38	6820	*
cparata	0:6d69e896ce38	6821	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6822	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	6823	*
cparata	0:6d69e896ce38	6824	*/
cparata	0:6d69e896ce38	6825	int32_t lsm6dso_pedo_debounce_steps_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6826	{
cparata	3:4274d9103f1d	6827	int32_t ret;
cparata	3:4274d9103f1d	6828	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff);
cparata	3:4274d9103f1d	6829	return ret;
cparata	0:6d69e896ce38	6830	}
cparata	0:6d69e896ce38	6831
cparata	0:6d69e896ce38	6832	/**
cparata	0:6d69e896ce38	6833	* @brief Pedometer debounce configuration register (r/w).[get]
cparata	0:6d69e896ce38	6834	*
cparata	0:6d69e896ce38	6835	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6836	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	6837	*
cparata	0:6d69e896ce38	6838	*/
cparata	0:6d69e896ce38	6839	int32_t lsm6dso_pedo_debounce_steps_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6840	{
cparata	3:4274d9103f1d	6841	int32_t ret;
cparata	3:4274d9103f1d	6842	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff);
cparata	3:4274d9103f1d	6843	return ret;
cparata	0:6d69e896ce38	6844	}
cparata	0:6d69e896ce38	6845
cparata	0:6d69e896ce38	6846	/**
cparata	0:6d69e896ce38	6847	* @brief Time period register for step detection on delta time (r/w).[set]
cparata	0:6d69e896ce38	6848	*
cparata	0:6d69e896ce38	6849	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6850	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	6851	*
cparata	0:6d69e896ce38	6852	*/
cparata	0:6d69e896ce38	6853	int32_t lsm6dso_pedo_steps_period_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6854	{
cparata	3:4274d9103f1d	6855	int32_t ret;
cparata	3:4274d9103f1d	6856	uint8_t index;
cparata	3:4274d9103f1d	6857
cparata	3:4274d9103f1d	6858	index = 0x00U;
cparata	3:4274d9103f1d	6859	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[index]);
cparata	3:4274d9103f1d	6860	if (ret == 0) {
cparata	3:4274d9103f1d	6861	index++;
cparata	3:4274d9103f1d	6862	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H,
cparata	3:4274d9103f1d	6863	&buff[index]);
cparata	3:4274d9103f1d	6864	}
cparata	3:4274d9103f1d	6865	return ret;
cparata	0:6d69e896ce38	6866	}
cparata	0:6d69e896ce38	6867
cparata	0:6d69e896ce38	6868	/**
cparata	0:6d69e896ce38	6869	* @brief Time period register for step detection on delta time (r/w).[get]
cparata	0:6d69e896ce38	6870	*
cparata	0:6d69e896ce38	6871	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6872	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	6873	*
cparata	0:6d69e896ce38	6874	*/
cparata	0:6d69e896ce38	6875	int32_t lsm6dso_pedo_steps_period_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6876	{
cparata	3:4274d9103f1d	6877	int32_t ret;
cparata	3:4274d9103f1d	6878	uint8_t index;
cparata	3:4274d9103f1d	6879
cparata	3:4274d9103f1d	6880	index = 0x00U;
cparata	3:4274d9103f1d	6881	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[index]);
cparata	3:4274d9103f1d	6882	if (ret == 0) {
cparata	3:4274d9103f1d	6883	index++;
cparata	3:4274d9103f1d	6884	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H,
cparata	3:4274d9103f1d	6885	&buff[index]);
cparata	3:4274d9103f1d	6886	}
cparata	3:4274d9103f1d	6887	return ret;
cparata	0:6d69e896ce38	6888	}
cparata	0:6d69e896ce38	6889
cparata	0:6d69e896ce38	6890	/**
cparata	0:6d69e896ce38	6891	* @brief Set when user wants to generate interrupt on count overflow
cparata	0:6d69e896ce38	6892	* event/every step.[set]
cparata	0:6d69e896ce38	6893	*
cparata	0:6d69e896ce38	6894	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6895	* @param val change the values of carry_count_en in reg PEDO_CMD_REG
cparata	0:6d69e896ce38	6896	*
cparata	0:6d69e896ce38	6897	*/
cparata	0:6d69e896ce38	6898	int32_t lsm6dso_pedo_int_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	6899	lsm6dso_carry_count_en_t val)
cparata	0:6d69e896ce38	6900	{
cparata	3:4274d9103f1d	6901	lsm6dso_pedo_cmd_reg_t reg;
cparata	3:4274d9103f1d	6902	int32_t ret;
cparata	3:4274d9103f1d	6903
cparata	3:4274d9103f1d	6904	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, (uint8_t *)&reg);
cparata	3:4274d9103f1d	6905	if (ret == 0) {
cparata	3:4274d9103f1d	6906	reg.carry_count_en = (uint8_t)val;
cparata	3:4274d9103f1d	6907	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
cparata	3:4274d9103f1d	6908	(uint8_t *)&reg);
cparata	3:4274d9103f1d	6909	}
cparata	3:4274d9103f1d	6910	return ret;
cparata	0:6d69e896ce38	6911	}
cparata	0:6d69e896ce38	6912
cparata	0:6d69e896ce38	6913	/**
cparata	0:6d69e896ce38	6914	* @brief Set when user wants to generate interrupt on count overflow
cparata	0:6d69e896ce38	6915	* event/every step.[get]
cparata	0:6d69e896ce38	6916	*
cparata	0:6d69e896ce38	6917	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6918	* @param val Get the values of carry_count_en in reg PEDO_CMD_REG
cparata	0:6d69e896ce38	6919	*
cparata	0:6d69e896ce38	6920	*/
cparata	0:6d69e896ce38	6921	int32_t lsm6dso_pedo_int_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	6922	lsm6dso_carry_count_en_t *val)
cparata	0:6d69e896ce38	6923	{
cparata	3:4274d9103f1d	6924	lsm6dso_pedo_cmd_reg_t reg;
cparata	3:4274d9103f1d	6925	int32_t ret;
cparata	3:4274d9103f1d	6926
cparata	3:4274d9103f1d	6927	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, (uint8_t *)&reg);
cparata	3:4274d9103f1d	6928	switch (reg.carry_count_en) {
cparata	3:4274d9103f1d	6929	case LSM6DSO_EVERY_STEP:
cparata	3:4274d9103f1d	6930	*val = LSM6DSO_EVERY_STEP;
cparata	3:4274d9103f1d	6931	break;
cparata	3:4274d9103f1d	6932	case LSM6DSO_COUNT_OVERFLOW:
cparata	3:4274d9103f1d	6933	*val = LSM6DSO_COUNT_OVERFLOW;
cparata	3:4274d9103f1d	6934	break;
cparata	3:4274d9103f1d	6935	default:
cparata	3:4274d9103f1d	6936	*val = LSM6DSO_EVERY_STEP;
cparata	3:4274d9103f1d	6937	break;
cparata	3:4274d9103f1d	6938	}
cparata	3:4274d9103f1d	6939	return ret;
cparata	0:6d69e896ce38	6940	}
cparata	0:6d69e896ce38	6941
cparata	0:6d69e896ce38	6942	/**
cparata	0:6d69e896ce38	6943	* @}
cparata	0:6d69e896ce38	6944	*
cparata	0:6d69e896ce38	6945	*/
cparata	0:6d69e896ce38	6946
cparata	0:6d69e896ce38	6947	/**
cparata	0:6d69e896ce38	6948	* @defgroup LSM6DSO_significant_motion
cparata	0:6d69e896ce38	6949	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	6950	* significant motion detection.
cparata	0:6d69e896ce38	6951	* @{
cparata	0:6d69e896ce38	6952	*
cparata	0:6d69e896ce38	6953	*/
cparata	0:6d69e896ce38	6954
cparata	0:6d69e896ce38	6955	/**
cparata	0:6d69e896ce38	6956	* @brief Enable significant motion detection function.[set]
cparata	0:6d69e896ce38	6957	*
cparata	0:6d69e896ce38	6958	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6959	* @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
cparata	0:6d69e896ce38	6960	*
cparata	0:6d69e896ce38	6961	*/
cparata	0:6d69e896ce38	6962	int32_t lsm6dso_motion_sens_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6963	{
cparata	3:4274d9103f1d	6964	lsm6dso_emb_func_en_a_t reg;
cparata	3:4274d9103f1d	6965	int32_t ret;
cparata	3:4274d9103f1d	6966
cparata	3:4274d9103f1d	6967	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	6968	if (ret == 0) {
cparata	3:4274d9103f1d	6969	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6970	}
cparata	3:4274d9103f1d	6971	if (ret == 0) {
cparata	3:4274d9103f1d	6972	reg.sign_motion_en = val;
cparata	3:4274d9103f1d	6973	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6974	}
cparata	3:4274d9103f1d	6975	if (ret == 0) {
cparata	3:4274d9103f1d	6976	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	6977	}
cparata	3:4274d9103f1d	6978	return ret;
cparata	0:6d69e896ce38	6979	}
cparata	0:6d69e896ce38	6980
cparata	0:6d69e896ce38	6981	/**
cparata	0:6d69e896ce38	6982	* @brief Enable significant motion detection function.[get]
cparata	0:6d69e896ce38	6983	*
cparata	0:6d69e896ce38	6984	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6985	* @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
cparata	0:6d69e896ce38	6986	*
cparata	0:6d69e896ce38	6987	*/
cparata	0:6d69e896ce38	6988	int32_t lsm6dso_motion_sens_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6989	{
cparata	3:4274d9103f1d	6990	lsm6dso_emb_func_en_a_t reg;
cparata	3:4274d9103f1d	6991	int32_t ret;
cparata	3:4274d9103f1d	6992
cparata	3:4274d9103f1d	6993	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	6994	if (ret == 0) {
cparata	3:4274d9103f1d	6995	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	6996	}
cparata	3:4274d9103f1d	6997	if (ret == 0) {
cparata	3:4274d9103f1d	6998	*val = reg.sign_motion_en;
cparata	3:4274d9103f1d	6999	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7000	}
cparata	3:4274d9103f1d	7001	return ret;
cparata	0:6d69e896ce38	7002	}
cparata	0:6d69e896ce38	7003
cparata	0:6d69e896ce38	7004	/**
cparata	0:6d69e896ce38	7005	* @brief Interrupt status bit for significant motion detection.[get]
cparata	0:6d69e896ce38	7006	*
cparata	0:6d69e896ce38	7007	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7008	* @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
cparata	0:6d69e896ce38	7009	*
cparata	0:6d69e896ce38	7010	*/
cparata	0:6d69e896ce38	7011	int32_t lsm6dso_motion_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	7012	{
cparata	3:4274d9103f1d	7013	lsm6dso_emb_func_status_t reg;
cparata	3:4274d9103f1d	7014	int32_t ret;
cparata	3:4274d9103f1d	7015
cparata	3:4274d9103f1d	7016	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7017	if (ret == 0) {
cparata	3:4274d9103f1d	7018	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7019	}
cparata	3:4274d9103f1d	7020	if (ret == 0) {
cparata	3:4274d9103f1d	7021	*val = reg.is_sigmot;
cparata	3:4274d9103f1d	7022	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7023	}
cparata	3:4274d9103f1d	7024
cparata	3:4274d9103f1d	7025	return ret;
cparata	0:6d69e896ce38	7026	}
cparata	0:6d69e896ce38	7027
cparata	0:6d69e896ce38	7028	/**
cparata	0:6d69e896ce38	7029	* @}
cparata	0:6d69e896ce38	7030	*
cparata	0:6d69e896ce38	7031	*/
cparata	0:6d69e896ce38	7032
cparata	0:6d69e896ce38	7033	/**
cparata	0:6d69e896ce38	7034	* @defgroup LSM6DSO_tilt_detection
cparata	0:6d69e896ce38	7035	* @brief This section groups all the functions that manage the tilt
cparata	0:6d69e896ce38	7036	* event detection.
cparata	0:6d69e896ce38	7037	* @{
cparata	0:6d69e896ce38	7038	*
cparata	0:6d69e896ce38	7039	*/
cparata	0:6d69e896ce38	7040
cparata	0:6d69e896ce38	7041	/**
cparata	0:6d69e896ce38	7042	* @brief Enable tilt calculation.[set]
cparata	0:6d69e896ce38	7043	*
cparata	0:6d69e896ce38	7044	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7045	* @param val change the values of tilt_en in reg EMB_FUNC_EN_A
cparata	0:6d69e896ce38	7046	*
cparata	0:6d69e896ce38	7047	*/
cparata	0:6d69e896ce38	7048	int32_t lsm6dso_tilt_sens_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	7049	{
cparata	3:4274d9103f1d	7050	lsm6dso_emb_func_en_a_t reg;
cparata	3:4274d9103f1d	7051	int32_t ret;
cparata	3:4274d9103f1d	7052
cparata	3:4274d9103f1d	7053	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7054	if (ret == 0) {
cparata	3:4274d9103f1d	7055	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7056	}
cparata	3:4274d9103f1d	7057	if (ret == 0) {
cparata	3:4274d9103f1d	7058	reg.tilt_en = val;
cparata	3:4274d9103f1d	7059	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7060	}
cparata	3:4274d9103f1d	7061	if (ret == 0) {
cparata	3:4274d9103f1d	7062	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7063	}
cparata	3:4274d9103f1d	7064	return ret;
cparata	0:6d69e896ce38	7065	}
cparata	0:6d69e896ce38	7066
cparata	0:6d69e896ce38	7067	/**
cparata	0:6d69e896ce38	7068	* @brief Enable tilt calculation.[get]
cparata	0:6d69e896ce38	7069	*
cparata	0:6d69e896ce38	7070	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7071	* @param val change the values of tilt_en in reg EMB_FUNC_EN_A
cparata	0:6d69e896ce38	7072	*
cparata	0:6d69e896ce38	7073	*/
cparata	0:6d69e896ce38	7074	int32_t lsm6dso_tilt_sens_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	7075	{
cparata	3:4274d9103f1d	7076	lsm6dso_emb_func_en_a_t reg;
cparata	3:4274d9103f1d	7077	int32_t ret;
cparata	3:4274d9103f1d	7078
cparata	3:4274d9103f1d	7079	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7080	if (ret == 0) {
cparata	3:4274d9103f1d	7081	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7082	}
cparata	3:4274d9103f1d	7083	if (ret == 0) {
cparata	3:4274d9103f1d	7084	*val = reg.tilt_en;
cparata	3:4274d9103f1d	7085	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7086	}
cparata	3:4274d9103f1d	7087
cparata	3:4274d9103f1d	7088	return ret;
cparata	0:6d69e896ce38	7089	}
cparata	0:6d69e896ce38	7090
cparata	0:6d69e896ce38	7091	/**
cparata	0:6d69e896ce38	7092	* @brief Interrupt status bit for tilt detection.[get]
cparata	0:6d69e896ce38	7093	*
cparata	0:6d69e896ce38	7094	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7095	* @param val change the values of is_tilt in reg EMB_FUNC_STATUS
cparata	0:6d69e896ce38	7096	*
cparata	0:6d69e896ce38	7097	*/
cparata	0:6d69e896ce38	7098	int32_t lsm6dso_tilt_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	7099	{
cparata	3:4274d9103f1d	7100	lsm6dso_emb_func_status_t reg;
cparata	3:4274d9103f1d	7101	int32_t ret;
cparata	3:4274d9103f1d	7102
cparata	3:4274d9103f1d	7103	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7104	if (ret == 0) {
cparata	3:4274d9103f1d	7105	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7106	}
cparata	3:4274d9103f1d	7107	if (ret == 0) {
cparata	3:4274d9103f1d	7108	*val = reg.is_tilt;
cparata	3:4274d9103f1d	7109	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7110	}
cparata	3:4274d9103f1d	7111
cparata	3:4274d9103f1d	7112	return ret;
cparata	0:6d69e896ce38	7113	}
cparata	0:6d69e896ce38	7114
cparata	0:6d69e896ce38	7115	/**
cparata	0:6d69e896ce38	7116	* @}
cparata	0:6d69e896ce38	7117	*
cparata	0:6d69e896ce38	7118	*/
cparata	0:6d69e896ce38	7119
cparata	0:6d69e896ce38	7120	/**
cparata	0:6d69e896ce38	7121	* @defgroup LSM6DSO_ magnetometer_sensor
cparata	0:6d69e896ce38	7122	* @brief This section groups all the functions that manage additional
cparata	0:6d69e896ce38	7123	* magnetometer sensor.
cparata	0:6d69e896ce38	7124	* @{
cparata	0:6d69e896ce38	7125	*
cparata	0:6d69e896ce38	7126	*/
cparata	0:6d69e896ce38	7127
cparata	0:6d69e896ce38	7128	/**
cparata	0:6d69e896ce38	7129	* @brief External magnetometer sensitivity value register.[set]
cparata	0:6d69e896ce38	7130	*
cparata	0:6d69e896ce38	7131	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7132	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	7133	*
cparata	0:6d69e896ce38	7134	*/
cparata	0:6d69e896ce38	7135	int32_t lsm6dso_mag_sensitivity_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7136	{
cparata	3:4274d9103f1d	7137	int32_t ret;
cparata	3:4274d9103f1d	7138	uint8_t index;
cparata	3:4274d9103f1d	7139
cparata	3:4274d9103f1d	7140	index = 0x00U;
cparata	3:4274d9103f1d	7141	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L,
cparata	0:6d69e896ce38	7142	&buff[index]);
cparata	3:4274d9103f1d	7143	if (ret == 0) {
cparata	3:4274d9103f1d	7144	index++;
cparata	3:4274d9103f1d	7145	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H,
cparata	3:4274d9103f1d	7146	&buff[index]);
cparata	3:4274d9103f1d	7147	}
cparata	3:4274d9103f1d	7148
cparata	3:4274d9103f1d	7149	return ret;
cparata	0:6d69e896ce38	7150	}
cparata	0:6d69e896ce38	7151
cparata	0:6d69e896ce38	7152	/**
cparata	0:6d69e896ce38	7153	* @brief External magnetometer sensitivity value register.[get]
cparata	0:6d69e896ce38	7154	*
cparata	0:6d69e896ce38	7155	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7156	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	7157	*
cparata	0:6d69e896ce38	7158	*/
cparata	0:6d69e896ce38	7159	int32_t lsm6dso_mag_sensitivity_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7160	{
cparata	3:4274d9103f1d	7161	int32_t ret;
cparata	3:4274d9103f1d	7162	uint8_t index;
cparata	3:4274d9103f1d	7163
cparata	3:4274d9103f1d	7164	index = 0x00U;
cparata	3:4274d9103f1d	7165	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L,
cparata	0:6d69e896ce38	7166	&buff[index]);
cparata	3:4274d9103f1d	7167	if (ret == 0) {
cparata	3:4274d9103f1d	7168	index++;
cparata	3:4274d9103f1d	7169	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H,
cparata	3:4274d9103f1d	7170	&buff[index]);
cparata	3:4274d9103f1d	7171	}
cparata	3:4274d9103f1d	7172
cparata	3:4274d9103f1d	7173	return ret;
cparata	0:6d69e896ce38	7174	}
cparata	0:6d69e896ce38	7175
cparata	0:6d69e896ce38	7176	/**
cparata	0:6d69e896ce38	7177	* @brief Offset for hard-iron compensation register (r/w).[set]
cparata	0:6d69e896ce38	7178	*
cparata	0:6d69e896ce38	7179	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7180	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	7181	*
cparata	0:6d69e896ce38	7182	*/
cparata	0:6d69e896ce38	7183	int32_t lsm6dso_mag_offset_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7184	{
cparata	3:4274d9103f1d	7185	int32_t ret;
cparata	3:4274d9103f1d	7186	uint8_t index;
cparata	3:4274d9103f1d	7187
cparata	3:4274d9103f1d	7188	index = 0x00U;
cparata	3:4274d9103f1d	7189	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[index]);
cparata	3:4274d9103f1d	7190	if (ret == 0) {
cparata	3:4274d9103f1d	7191	index++;
cparata	3:4274d9103f1d	7192	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[index]);
cparata	3:4274d9103f1d	7193	}
cparata	3:4274d9103f1d	7194	if (ret == 0) {
cparata	3:4274d9103f1d	7195	index++;
cparata	3:4274d9103f1d	7196	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[index]);
cparata	3:4274d9103f1d	7197	}
cparata	3:4274d9103f1d	7198	if (ret == 0) {
cparata	3:4274d9103f1d	7199	index++;
cparata	3:4274d9103f1d	7200	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[index]);
cparata	3:4274d9103f1d	7201	}
cparata	3:4274d9103f1d	7202	if (ret == 0) {
cparata	3:4274d9103f1d	7203	index++;
cparata	3:4274d9103f1d	7204
cparata	3:4274d9103f1d	7205	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[index]);
cparata	3:4274d9103f1d	7206	}
cparata	3:4274d9103f1d	7207	if (ret == 0) {
cparata	3:4274d9103f1d	7208	index++;
cparata	3:4274d9103f1d	7209	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[index]);
cparata	3:4274d9103f1d	7210	}
cparata	3:4274d9103f1d	7211
cparata	3:4274d9103f1d	7212	return ret;
cparata	0:6d69e896ce38	7213	}
cparata	0:6d69e896ce38	7214
cparata	0:6d69e896ce38	7215	/**
cparata	0:6d69e896ce38	7216	* @brief Offset for hard-iron compensation register (r/w).[get]
cparata	0:6d69e896ce38	7217	*
cparata	0:6d69e896ce38	7218	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7219	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	7220	*
cparata	0:6d69e896ce38	7221	*/
cparata	0:6d69e896ce38	7222	int32_t lsm6dso_mag_offset_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7223	{
cparata	3:4274d9103f1d	7224	int32_t ret;
cparata	3:4274d9103f1d	7225	uint8_t index;
cparata	3:4274d9103f1d	7226
cparata	3:4274d9103f1d	7227	index = 0x00U;
cparata	3:4274d9103f1d	7228	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[index]);
cparata	3:4274d9103f1d	7229	if (ret == 0) {
cparata	3:4274d9103f1d	7230	index++;
cparata	3:4274d9103f1d	7231	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[index]);
cparata	3:4274d9103f1d	7232	}
cparata	3:4274d9103f1d	7233	if (ret == 0) {
cparata	3:4274d9103f1d	7234	index++;
cparata	3:4274d9103f1d	7235
cparata	3:4274d9103f1d	7236	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[index]);
cparata	3:4274d9103f1d	7237	}
cparata	3:4274d9103f1d	7238	if (ret == 0) {
cparata	3:4274d9103f1d	7239	index++;
cparata	3:4274d9103f1d	7240	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[index]);
cparata	3:4274d9103f1d	7241	}
cparata	3:4274d9103f1d	7242	if (ret == 0) {
cparata	3:4274d9103f1d	7243	index++;
cparata	3:4274d9103f1d	7244
cparata	3:4274d9103f1d	7245	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[index]);
cparata	3:4274d9103f1d	7246	}
cparata	3:4274d9103f1d	7247	if (ret == 0) {
cparata	3:4274d9103f1d	7248	index++;
cparata	3:4274d9103f1d	7249	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[index]);
cparata	3:4274d9103f1d	7250	}
cparata	3:4274d9103f1d	7251	return ret;
cparata	0:6d69e896ce38	7252	}
cparata	0:6d69e896ce38	7253
cparata	0:6d69e896ce38	7254	/**
cparata	0:6d69e896ce38	7255	* @brief Soft-iron (3x3 symmetric) matrix correction
cparata	0:6d69e896ce38	7256	* register (r/w). The value is expressed as
cparata	0:6d69e896ce38	7257	* half-precision floating-point format:
cparata	0:6d69e896ce38	7258	* SEEEEEFFFFFFFFFF
cparata	0:6d69e896ce38	7259	* S: 1 sign bit;
cparata	0:6d69e896ce38	7260	* E: 5 exponent bits;
cparata	0:6d69e896ce38	7261	* F: 10 fraction bits).[set]
cparata	0:6d69e896ce38	7262	*
cparata	0:6d69e896ce38	7263	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7264	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	7265	*
cparata	0:6d69e896ce38	7266	*/
cparata	0:6d69e896ce38	7267	int32_t lsm6dso_mag_soft_iron_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7268	{
cparata	3:4274d9103f1d	7269	int32_t ret;
cparata	3:4274d9103f1d	7270	uint8_t index;
cparata	3:4274d9103f1d	7271
cparata	3:4274d9103f1d	7272	index = 0x00U;
cparata	3:4274d9103f1d	7273	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]);
cparata	3:4274d9103f1d	7274	if (ret == 0) {
cparata	3:4274d9103f1d	7275	index++;
cparata	3:4274d9103f1d	7276	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]);
cparata	3:4274d9103f1d	7277	}
cparata	3:4274d9103f1d	7278	if (ret == 0) {
cparata	3:4274d9103f1d	7279	index++;
cparata	3:4274d9103f1d	7280
cparata	3:4274d9103f1d	7281	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]);
cparata	3:4274d9103f1d	7282	}
cparata	3:4274d9103f1d	7283	if (ret == 0) {
cparata	3:4274d9103f1d	7284	index++;
cparata	3:4274d9103f1d	7285	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]);
cparata	3:4274d9103f1d	7286	}
cparata	3:4274d9103f1d	7287	if (ret == 0) {
cparata	3:4274d9103f1d	7288	index++;
cparata	3:4274d9103f1d	7289
cparata	3:4274d9103f1d	7290	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]);
cparata	3:4274d9103f1d	7291	}
cparata	3:4274d9103f1d	7292	if (ret == 0) {
cparata	3:4274d9103f1d	7293	index++;
cparata	3:4274d9103f1d	7294	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]);
cparata	3:4274d9103f1d	7295	}
cparata	3:4274d9103f1d	7296	if (ret == 0) {
cparata	3:4274d9103f1d	7297	index++;
cparata	3:4274d9103f1d	7298
cparata	3:4274d9103f1d	7299	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]);
cparata	3:4274d9103f1d	7300	}
cparata	3:4274d9103f1d	7301	if (ret == 0) {
cparata	3:4274d9103f1d	7302	index++;
cparata	3:4274d9103f1d	7303	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]);
cparata	3:4274d9103f1d	7304	}
cparata	3:4274d9103f1d	7305	if (ret == 0) {
cparata	3:4274d9103f1d	7306	index++;
cparata	3:4274d9103f1d	7307
cparata	3:4274d9103f1d	7308	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]);
cparata	3:4274d9103f1d	7309	}
cparata	3:4274d9103f1d	7310	if (ret == 0) {
cparata	3:4274d9103f1d	7311	index++;
cparata	3:4274d9103f1d	7312	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]);
cparata	3:4274d9103f1d	7313	}
cparata	3:4274d9103f1d	7314	if (ret == 0) {
cparata	3:4274d9103f1d	7315	index++;
cparata	3:4274d9103f1d	7316
cparata	3:4274d9103f1d	7317	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]);
cparata	3:4274d9103f1d	7318	}
cparata	3:4274d9103f1d	7319	if (ret == 0) {
cparata	3:4274d9103f1d	7320	index++;
cparata	3:4274d9103f1d	7321	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]);
cparata	3:4274d9103f1d	7322	}
cparata	3:4274d9103f1d	7323
cparata	3:4274d9103f1d	7324	return ret;
cparata	0:6d69e896ce38	7325	}
cparata	0:6d69e896ce38	7326
cparata	0:6d69e896ce38	7327	/**
cparata	0:6d69e896ce38	7328	* @brief Soft-iron (3x3 symmetric) matrix
cparata	0:6d69e896ce38	7329	* correction register (r/w).
cparata	0:6d69e896ce38	7330	* The value is expressed as half-precision
cparata	0:6d69e896ce38	7331	* floating-point format:
cparata	0:6d69e896ce38	7332	* SEEEEEFFFFFFFFFF
cparata	0:6d69e896ce38	7333	* S: 1 sign bit;
cparata	0:6d69e896ce38	7334	* E: 5 exponent bits;
cparata	0:6d69e896ce38	7335	* F: 10 fraction bits.[get]
cparata	0:6d69e896ce38	7336	*
cparata	0:6d69e896ce38	7337	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7338	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	7339	*
cparata	0:6d69e896ce38	7340	*/
cparata	0:6d69e896ce38	7341	int32_t lsm6dso_mag_soft_iron_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7342	{
cparata	3:4274d9103f1d	7343	int32_t ret;
cparata	3:4274d9103f1d	7344	uint8_t index;
cparata	3:4274d9103f1d	7345
cparata	3:4274d9103f1d	7346	index = 0x00U;
cparata	3:4274d9103f1d	7347	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]);
cparata	3:4274d9103f1d	7348	if (ret == 0) {
cparata	3:4274d9103f1d	7349	index++;
cparata	3:4274d9103f1d	7350	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]);
cparata	3:4274d9103f1d	7351	}
cparata	3:4274d9103f1d	7352	if (ret == 0) {
cparata	3:4274d9103f1d	7353	index++;
cparata	3:4274d9103f1d	7354
cparata	3:4274d9103f1d	7355	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]);
cparata	3:4274d9103f1d	7356	}
cparata	3:4274d9103f1d	7357	if (ret == 0) {
cparata	3:4274d9103f1d	7358	index++;
cparata	3:4274d9103f1d	7359	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]);
cparata	3:4274d9103f1d	7360	}
cparata	3:4274d9103f1d	7361	if (ret == 0) {
cparata	3:4274d9103f1d	7362	index++;
cparata	3:4274d9103f1d	7363
cparata	3:4274d9103f1d	7364	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]);
cparata	3:4274d9103f1d	7365	}
cparata	3:4274d9103f1d	7366	if (ret == 0) {
cparata	3:4274d9103f1d	7367	index++;
cparata	3:4274d9103f1d	7368	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]);
cparata	3:4274d9103f1d	7369	}
cparata	3:4274d9103f1d	7370	if (ret == 0) {
cparata	3:4274d9103f1d	7371	index++;
cparata	3:4274d9103f1d	7372
cparata	3:4274d9103f1d	7373	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]);
cparata	3:4274d9103f1d	7374	}
cparata	3:4274d9103f1d	7375	if (ret == 0) {
cparata	3:4274d9103f1d	7376	index++;
cparata	3:4274d9103f1d	7377	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]);
cparata	3:4274d9103f1d	7378	}
cparata	3:4274d9103f1d	7379	if (ret == 0) {
cparata	3:4274d9103f1d	7380	index++;
cparata	3:4274d9103f1d	7381
cparata	3:4274d9103f1d	7382	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]);
cparata	3:4274d9103f1d	7383	}
cparata	3:4274d9103f1d	7384	if (ret == 0) {
cparata	3:4274d9103f1d	7385	index++;
cparata	3:4274d9103f1d	7386	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]);
cparata	3:4274d9103f1d	7387	}
cparata	3:4274d9103f1d	7388	if (ret == 0) {
cparata	3:4274d9103f1d	7389	index++;
cparata	3:4274d9103f1d	7390
cparata	3:4274d9103f1d	7391	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]);
cparata	3:4274d9103f1d	7392	}
cparata	3:4274d9103f1d	7393	if (ret == 0) {
cparata	3:4274d9103f1d	7394	index++;
cparata	3:4274d9103f1d	7395	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]);
cparata	3:4274d9103f1d	7396	}
cparata	3:4274d9103f1d	7397
cparata	3:4274d9103f1d	7398	return ret;
cparata	0:6d69e896ce38	7399	}
cparata	0:6d69e896ce38	7400
cparata	0:6d69e896ce38	7401	/**
cparata	0:6d69e896ce38	7402	* @brief Magnetometer Z-axis coordinates
cparata	0:6d69e896ce38	7403	* rotation (to be aligned to
cparata	0:6d69e896ce38	7404	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7405	* orientation).[set]
cparata	0:6d69e896ce38	7406	*
cparata	0:6d69e896ce38	7407	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7408	* @param val change the values of mag_z_axis in reg MAG_CFG_A
cparata	0:6d69e896ce38	7409	*
cparata	0:6d69e896ce38	7410	*/
cparata	0:6d69e896ce38	7411	int32_t lsm6dso_mag_z_orient_set(lsm6dso_ctx_t *ctx, lsm6dso_mag_z_axis_t val)
cparata	0:6d69e896ce38	7412	{
cparata	3:4274d9103f1d	7413	lsm6dso_mag_cfg_a_t reg;
cparata	3:4274d9103f1d	7414	int32_t ret;
cparata	3:4274d9103f1d	7415
cparata	3:4274d9103f1d	7416	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *)&reg);
cparata	3:4274d9103f1d	7417	if (ret == 0) {
cparata	3:4274d9103f1d	7418	reg.mag_z_axis = (uint8_t) val;
cparata	3:4274d9103f1d	7419	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *)&reg);
cparata	3:4274d9103f1d	7420	}
cparata	3:4274d9103f1d	7421
cparata	3:4274d9103f1d	7422	return ret;
cparata	0:6d69e896ce38	7423	}
cparata	0:6d69e896ce38	7424
cparata	0:6d69e896ce38	7425	/**
cparata	0:6d69e896ce38	7426	* @brief Magnetometer Z-axis coordinates
cparata	0:6d69e896ce38	7427	* rotation (to be aligned to
cparata	0:6d69e896ce38	7428	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7429	* orientation).[get]
cparata	0:6d69e896ce38	7430	*
cparata	0:6d69e896ce38	7431	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7432	* @param val Get the values of mag_z_axis in reg MAG_CFG_A
cparata	0:6d69e896ce38	7433	*
cparata	0:6d69e896ce38	7434	*/
cparata	0:6d69e896ce38	7435	int32_t lsm6dso_mag_z_orient_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7436	lsm6dso_mag_z_axis_t *val)
cparata	0:6d69e896ce38	7437	{
cparata	3:4274d9103f1d	7438	lsm6dso_mag_cfg_a_t reg;
cparata	3:4274d9103f1d	7439	int32_t ret;
cparata	3:4274d9103f1d	7440	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *)&reg);
cparata	3:4274d9103f1d	7441	switch (reg.mag_z_axis) {
cparata	3:4274d9103f1d	7442	case LSM6DSO_Z_EQ_Y:
cparata	3:4274d9103f1d	7443	*val = LSM6DSO_Z_EQ_Y;
cparata	3:4274d9103f1d	7444	break;
cparata	3:4274d9103f1d	7445	case LSM6DSO_Z_EQ_MIN_Y:
cparata	3:4274d9103f1d	7446	*val = LSM6DSO_Z_EQ_MIN_Y;
cparata	3:4274d9103f1d	7447	break;
cparata	3:4274d9103f1d	7448	case LSM6DSO_Z_EQ_X:
cparata	3:4274d9103f1d	7449	*val = LSM6DSO_Z_EQ_X;
cparata	3:4274d9103f1d	7450	break;
cparata	3:4274d9103f1d	7451	case LSM6DSO_Z_EQ_MIN_X:
cparata	3:4274d9103f1d	7452	*val = LSM6DSO_Z_EQ_MIN_X;
cparata	3:4274d9103f1d	7453	break;
cparata	3:4274d9103f1d	7454	case LSM6DSO_Z_EQ_MIN_Z:
cparata	3:4274d9103f1d	7455	*val = LSM6DSO_Z_EQ_MIN_Z;
cparata	3:4274d9103f1d	7456	break;
cparata	3:4274d9103f1d	7457	case LSM6DSO_Z_EQ_Z:
cparata	3:4274d9103f1d	7458	*val = LSM6DSO_Z_EQ_Z;
cparata	3:4274d9103f1d	7459	break;
cparata	3:4274d9103f1d	7460	default:
cparata	3:4274d9103f1d	7461	*val = LSM6DSO_Z_EQ_Y;
cparata	3:4274d9103f1d	7462	break;
cparata	3:4274d9103f1d	7463	}
cparata	3:4274d9103f1d	7464	return ret;
cparata	0:6d69e896ce38	7465	}
cparata	0:6d69e896ce38	7466
cparata	0:6d69e896ce38	7467	/**
cparata	0:6d69e896ce38	7468	* @brief Magnetometer Y-axis coordinates
cparata	0:6d69e896ce38	7469	* rotation (to be aligned to
cparata	0:6d69e896ce38	7470	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7471	* orientation).[set]
cparata	0:6d69e896ce38	7472	*
cparata	0:6d69e896ce38	7473	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7474	* @param val change the values of mag_y_axis in reg MAG_CFG_A
cparata	0:6d69e896ce38	7475	*
cparata	0:6d69e896ce38	7476	*/
cparata	0:6d69e896ce38	7477	int32_t lsm6dso_mag_y_orient_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7478	lsm6dso_mag_y_axis_t val)
cparata	0:6d69e896ce38	7479	{
cparata	3:4274d9103f1d	7480	lsm6dso_mag_cfg_a_t reg;
cparata	3:4274d9103f1d	7481	int32_t ret;
cparata	3:4274d9103f1d	7482
cparata	3:4274d9103f1d	7483	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *)&reg);
cparata	3:4274d9103f1d	7484	if (ret == 0) {
cparata	3:4274d9103f1d	7485	reg.mag_y_axis = (uint8_t)val;
cparata	3:4274d9103f1d	7486	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *) &reg);
cparata	3:4274d9103f1d	7487	}
cparata	3:4274d9103f1d	7488	return ret;
cparata	0:6d69e896ce38	7489	}
cparata	0:6d69e896ce38	7490
cparata	0:6d69e896ce38	7491	/**
cparata	0:6d69e896ce38	7492	* @brief Magnetometer Y-axis coordinates
cparata	0:6d69e896ce38	7493	* rotation (to be aligned to
cparata	0:6d69e896ce38	7494	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7495	* orientation).[get]
cparata	0:6d69e896ce38	7496	*
cparata	0:6d69e896ce38	7497	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7498	* @param val Get the values of mag_y_axis in reg MAG_CFG_A
cparata	0:6d69e896ce38	7499	*
cparata	0:6d69e896ce38	7500	*/
cparata	0:6d69e896ce38	7501	int32_t lsm6dso_mag_y_orient_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7502	lsm6dso_mag_y_axis_t *val)
cparata	0:6d69e896ce38	7503	{
cparata	3:4274d9103f1d	7504	lsm6dso_mag_cfg_a_t reg;
cparata	3:4274d9103f1d	7505	int32_t ret;
cparata	3:4274d9103f1d	7506
cparata	3:4274d9103f1d	7507	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *)&reg);
cparata	3:4274d9103f1d	7508	switch (reg.mag_y_axis) {
cparata	3:4274d9103f1d	7509	case LSM6DSO_Y_EQ_Y:
cparata	3:4274d9103f1d	7510	*val = LSM6DSO_Y_EQ_Y;
cparata	3:4274d9103f1d	7511	break;
cparata	3:4274d9103f1d	7512	case LSM6DSO_Y_EQ_MIN_Y:
cparata	3:4274d9103f1d	7513	*val = LSM6DSO_Y_EQ_MIN_Y;
cparata	3:4274d9103f1d	7514	break;
cparata	3:4274d9103f1d	7515	case LSM6DSO_Y_EQ_X:
cparata	3:4274d9103f1d	7516	*val = LSM6DSO_Y_EQ_X;
cparata	3:4274d9103f1d	7517	break;
cparata	3:4274d9103f1d	7518	case LSM6DSO_Y_EQ_MIN_X:
cparata	3:4274d9103f1d	7519	*val = LSM6DSO_Y_EQ_MIN_X;
cparata	3:4274d9103f1d	7520	break;
cparata	3:4274d9103f1d	7521	case LSM6DSO_Y_EQ_MIN_Z:
cparata	3:4274d9103f1d	7522	*val = LSM6DSO_Y_EQ_MIN_Z;
cparata	3:4274d9103f1d	7523	break;
cparata	3:4274d9103f1d	7524	case LSM6DSO_Y_EQ_Z:
cparata	3:4274d9103f1d	7525	*val = LSM6DSO_Y_EQ_Z;
cparata	3:4274d9103f1d	7526	break;
cparata	3:4274d9103f1d	7527	default:
cparata	3:4274d9103f1d	7528	*val = LSM6DSO_Y_EQ_Y;
cparata	3:4274d9103f1d	7529	break;
cparata	3:4274d9103f1d	7530	}
cparata	3:4274d9103f1d	7531	return ret;
cparata	0:6d69e896ce38	7532	}
cparata	0:6d69e896ce38	7533
cparata	0:6d69e896ce38	7534	/**
cparata	0:6d69e896ce38	7535	* @brief Magnetometer X-axis coordinates
cparata	0:6d69e896ce38	7536	* rotation (to be aligned to
cparata	0:6d69e896ce38	7537	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7538	* orientation).[set]
cparata	0:6d69e896ce38	7539	*
cparata	0:6d69e896ce38	7540	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7541	* @param val change the values of mag_x_axis in reg MAG_CFG_B
cparata	0:6d69e896ce38	7542	*
cparata	0:6d69e896ce38	7543	*/
cparata	0:6d69e896ce38	7544	int32_t lsm6dso_mag_x_orient_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7545	lsm6dso_mag_x_axis_t val)
cparata	0:6d69e896ce38	7546	{
cparata	3:4274d9103f1d	7547	lsm6dso_mag_cfg_b_t reg;
cparata	3:4274d9103f1d	7548	int32_t ret;
cparata	3:4274d9103f1d	7549
cparata	3:4274d9103f1d	7550	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t *)&reg);
cparata	3:4274d9103f1d	7551	if (ret == 0) {
cparata	3:4274d9103f1d	7552	reg.mag_x_axis = (uint8_t)val;
cparata	3:4274d9103f1d	7553	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t *)&reg);
cparata	3:4274d9103f1d	7554	}
cparata	3:4274d9103f1d	7555	return ret;
cparata	0:6d69e896ce38	7556	}
cparata	0:6d69e896ce38	7557
cparata	0:6d69e896ce38	7558	/**
cparata	0:6d69e896ce38	7559	* @brief Magnetometer X-axis coordinates
cparata	0:6d69e896ce38	7560	* rotation (to be aligned to
cparata	0:6d69e896ce38	7561	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7562	* orientation).[get]
cparata	0:6d69e896ce38	7563	*
cparata	0:6d69e896ce38	7564	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7565	* @param val Get the values of mag_x_axis in reg MAG_CFG_B
cparata	0:6d69e896ce38	7566	*
cparata	0:6d69e896ce38	7567	*/
cparata	0:6d69e896ce38	7568	int32_t lsm6dso_mag_x_orient_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7569	lsm6dso_mag_x_axis_t *val)
cparata	0:6d69e896ce38	7570	{
cparata	3:4274d9103f1d	7571	lsm6dso_mag_cfg_b_t reg;
cparata	3:4274d9103f1d	7572	int32_t ret;
cparata	3:4274d9103f1d	7573
cparata	3:4274d9103f1d	7574	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t *)&reg);
cparata	3:4274d9103f1d	7575	switch (reg.mag_x_axis) {
cparata	3:4274d9103f1d	7576	case LSM6DSO_X_EQ_Y:
cparata	3:4274d9103f1d	7577	*val = LSM6DSO_X_EQ_Y;
cparata	3:4274d9103f1d	7578	break;
cparata	3:4274d9103f1d	7579	case LSM6DSO_X_EQ_MIN_Y:
cparata	3:4274d9103f1d	7580	*val = LSM6DSO_X_EQ_MIN_Y;
cparata	3:4274d9103f1d	7581	break;
cparata	3:4274d9103f1d	7582	case LSM6DSO_X_EQ_X:
cparata	3:4274d9103f1d	7583	*val = LSM6DSO_X_EQ_X;
cparata	3:4274d9103f1d	7584	break;
cparata	3:4274d9103f1d	7585	case LSM6DSO_X_EQ_MIN_X:
cparata	3:4274d9103f1d	7586	*val = LSM6DSO_X_EQ_MIN_X;
cparata	3:4274d9103f1d	7587	break;
cparata	3:4274d9103f1d	7588	case LSM6DSO_X_EQ_MIN_Z:
cparata	3:4274d9103f1d	7589	*val = LSM6DSO_X_EQ_MIN_Z;
cparata	3:4274d9103f1d	7590	break;
cparata	3:4274d9103f1d	7591	case LSM6DSO_X_EQ_Z:
cparata	3:4274d9103f1d	7592	*val = LSM6DSO_X_EQ_Z;
cparata	3:4274d9103f1d	7593	break;
cparata	3:4274d9103f1d	7594	default:
cparata	3:4274d9103f1d	7595	*val = LSM6DSO_X_EQ_Y;
cparata	3:4274d9103f1d	7596	break;
cparata	3:4274d9103f1d	7597	}
cparata	3:4274d9103f1d	7598	return ret;
cparata	0:6d69e896ce38	7599	}
cparata	0:6d69e896ce38	7600
cparata	0:6d69e896ce38	7601	/**
cparata	0:6d69e896ce38	7602	* @}
cparata	0:6d69e896ce38	7603	*
cparata	0:6d69e896ce38	7604	*/
cparata	0:6d69e896ce38	7605
cparata	0:6d69e896ce38	7606	/**
cparata	0:6d69e896ce38	7607	* @defgroup LSM6DSO_significant_motion
cparata	0:6d69e896ce38	7608	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	7609	* state_machine.
cparata	0:6d69e896ce38	7610	* @{
cparata	0:6d69e896ce38	7611	*
cparata	0:6d69e896ce38	7612	*/
cparata	0:6d69e896ce38	7613
cparata	0:6d69e896ce38	7614	/**
cparata	0:6d69e896ce38	7615	* @brief Interrupt status bit for FSM long counter
cparata	0:6d69e896ce38	7616	* timeout interrupt event.[get]
cparata	0:6d69e896ce38	7617	*
cparata	0:6d69e896ce38	7618	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7619	* @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
cparata	0:6d69e896ce38	7620	*
cparata	0:6d69e896ce38	7621	*/
cparata	0:6d69e896ce38	7622	int32_t lsm6dso_long_cnt_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	7623	{
cparata	3:4274d9103f1d	7624	lsm6dso_emb_func_status_t reg;
cparata	3:4274d9103f1d	7625	int32_t ret;
cparata	3:4274d9103f1d	7626
cparata	3:4274d9103f1d	7627	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7628	if (ret == 0) {
cparata	3:4274d9103f1d	7629	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7630	}
cparata	3:4274d9103f1d	7631	if (ret == 0) {
cparata	3:4274d9103f1d	7632	*val = reg.is_fsm_lc;
cparata	3:4274d9103f1d	7633	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7634	}
cparata	3:4274d9103f1d	7635	return ret;
cparata	0:6d69e896ce38	7636	}
cparata	0:6d69e896ce38	7637
cparata	0:6d69e896ce38	7638	/**
cparata	0:6d69e896ce38	7639	* @brief Final State Machine global enable.[set]
cparata	0:6d69e896ce38	7640	*
cparata	0:6d69e896ce38	7641	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7642	* @param val change the values of fsm_en in reg EMB_FUNC_EN_B
cparata	0:6d69e896ce38	7643	*
cparata	0:6d69e896ce38	7644	*/
cparata	0:6d69e896ce38	7645	int32_t lsm6dso_emb_fsm_en_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	7646	{
cparata	3:4274d9103f1d	7647	int32_t ret;
cparata	3:4274d9103f1d	7648	lsm6dso_emb_func_en_b_t reg;
cparata	3:4274d9103f1d	7649
cparata	3:4274d9103f1d	7650	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7651	if (ret == 0) {
cparata	3:4274d9103f1d	7652	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7653	}
cparata	3:4274d9103f1d	7654	if (ret == 0) {
cparata	3:4274d9103f1d	7655	reg.fsm_en = val;
cparata	3:4274d9103f1d	7656	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7657	}
cparata	3:4274d9103f1d	7658	if (ret == 0) {
cparata	3:4274d9103f1d	7659	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7660	}
cparata	3:4274d9103f1d	7661	return ret;
cparata	0:6d69e896ce38	7662	}
cparata	0:6d69e896ce38	7663
cparata	0:6d69e896ce38	7664	/**
cparata	0:6d69e896ce38	7665	* @brief Final State Machine global enable.[get]
cparata	0:6d69e896ce38	7666	*
cparata	0:6d69e896ce38	7667	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7668	* @param uint8_t *: return the values of fsm_en in reg EMB_FUNC_EN_B
cparata	0:6d69e896ce38	7669	*
cparata	0:6d69e896ce38	7670	*/
cparata	0:6d69e896ce38	7671	int32_t lsm6dso_emb_fsm_en_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	7672	{
cparata	3:4274d9103f1d	7673	int32_t ret;
cparata	3:4274d9103f1d	7674	lsm6dso_emb_func_en_b_t reg;
cparata	3:4274d9103f1d	7675
cparata	3:4274d9103f1d	7676	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7677	if (ret == 0) {
cparata	3:4274d9103f1d	7678	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7679	}
cparata	3:4274d9103f1d	7680	if (ret == 0) {
cparata	3:4274d9103f1d	7681	*val = reg.fsm_en;
cparata	3:4274d9103f1d	7682	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7683	}
cparata	3:4274d9103f1d	7684	if (ret == 0) {
cparata	3:4274d9103f1d	7685	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7686	}
cparata	3:4274d9103f1d	7687
cparata	3:4274d9103f1d	7688	return ret;
cparata	0:6d69e896ce38	7689	}
cparata	0:6d69e896ce38	7690
cparata	0:6d69e896ce38	7691	/**
cparata	0:6d69e896ce38	7692	* @brief Final State Machine enable.[set]
cparata	0:6d69e896ce38	7693	*
cparata	0:6d69e896ce38	7694	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7695	* @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
cparata	0:6d69e896ce38	7696	*
cparata	0:6d69e896ce38	7697	*/
cparata	0:6d69e896ce38	7698	int32_t lsm6dso_fsm_enable_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7699	lsm6dso_emb_fsm_enable_t *val)
cparata	0:6d69e896ce38	7700	{
cparata	3:4274d9103f1d	7701	int32_t ret;
cparata	3:4274d9103f1d	7702	lsm6dso_emb_func_en_b_t reg;
cparata	3:4274d9103f1d	7703
cparata	3:4274d9103f1d	7704	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7705	if (ret == 0) {
cparata	3:4274d9103f1d	7706	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_A,
cparata	3:4274d9103f1d	7707	(uint8_t *)&val->fsm_enable_a, 1);
cparata	3:4274d9103f1d	7708	}
cparata	3:4274d9103f1d	7709	if (ret == 0) {
cparata	3:4274d9103f1d	7710	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_B,
cparata	3:4274d9103f1d	7711	(uint8_t *)&val->fsm_enable_b, 1);
cparata	3:4274d9103f1d	7712	}
cparata	3:4274d9103f1d	7713	if (ret == 0) {
cparata	3:4274d9103f1d	7714	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7715	}
cparata	3:4274d9103f1d	7716	if (ret == 0) {
cparata	3:4274d9103f1d	7717	if ((val->fsm_enable_a.fsm1_en \|
cparata	3:4274d9103f1d	7718	val->fsm_enable_a.fsm2_en \|
cparata	3:4274d9103f1d	7719	val->fsm_enable_a.fsm3_en \|
cparata	3:4274d9103f1d	7720	val->fsm_enable_a.fsm4_en \|
cparata	3:4274d9103f1d	7721	val->fsm_enable_a.fsm5_en \|
cparata	3:4274d9103f1d	7722	val->fsm_enable_a.fsm6_en \|
cparata	3:4274d9103f1d	7723	val->fsm_enable_a.fsm7_en \|
cparata	3:4274d9103f1d	7724	val->fsm_enable_a.fsm8_en \|
cparata	3:4274d9103f1d	7725	val->fsm_enable_b.fsm9_en \|
cparata	3:4274d9103f1d	7726	val->fsm_enable_b.fsm10_en \|
cparata	3:4274d9103f1d	7727	val->fsm_enable_b.fsm11_en \|
cparata	3:4274d9103f1d	7728	val->fsm_enable_b.fsm12_en \|
cparata	3:4274d9103f1d	7729	val->fsm_enable_b.fsm13_en \|
cparata	3:4274d9103f1d	7730	val->fsm_enable_b.fsm14_en \|
cparata	3:4274d9103f1d	7731	val->fsm_enable_b.fsm15_en \|
cparata	3:4274d9103f1d	7732	val->fsm_enable_b.fsm16_en)
cparata	3:4274d9103f1d	7733	!= PROPERTY_DISABLE) {
cparata	3:4274d9103f1d	7734	reg.fsm_en = PROPERTY_ENABLE;
cparata	3:4274d9103f1d	7735	} else {
cparata	3:4274d9103f1d	7736	reg.fsm_en = PROPERTY_DISABLE;
cparata	3:4274d9103f1d	7737	}
cparata	3:4274d9103f1d	7738
cparata	3:4274d9103f1d	7739	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7740	}
cparata	3:4274d9103f1d	7741	if (ret == 0) {
cparata	3:4274d9103f1d	7742	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7743	}
cparata	3:4274d9103f1d	7744
cparata	3:4274d9103f1d	7745	return ret;
cparata	0:6d69e896ce38	7746	}
cparata	0:6d69e896ce38	7747
cparata	0:6d69e896ce38	7748	/**
cparata	0:6d69e896ce38	7749	* @brief Final State Machine enable.[get]
cparata	0:6d69e896ce38	7750	*
cparata	0:6d69e896ce38	7751	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7752	* @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
cparata	0:6d69e896ce38	7753	*
cparata	0:6d69e896ce38	7754	*/
cparata	0:6d69e896ce38	7755	int32_t lsm6dso_fsm_enable_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7756	lsm6dso_emb_fsm_enable_t *val)
cparata	0:6d69e896ce38	7757	{
cparata	3:4274d9103f1d	7758	int32_t ret;
cparata	3:4274d9103f1d	7759
cparata	3:4274d9103f1d	7760	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7761	if (ret == 0) {
cparata	3:4274d9103f1d	7762	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, (uint8_t *) val, 2);
cparata	3:4274d9103f1d	7763	}
cparata	3:4274d9103f1d	7764	if (ret == 0) {
cparata	3:4274d9103f1d	7765	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7766	}
cparata	3:4274d9103f1d	7767	return ret;
cparata	0:6d69e896ce38	7768	}
cparata	0:6d69e896ce38	7769
cparata	0:6d69e896ce38	7770	/**
cparata	0:6d69e896ce38	7771	* @brief FSM long counter status register. Long counter value is an
cparata	0:6d69e896ce38	7772	* unsigned integer value (16-bit format).[set]
cparata	0:6d69e896ce38	7773	*
cparata	0:6d69e896ce38	7774	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7775	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	7776	*
cparata	0:6d69e896ce38	7777	*/
cparata	0:6d69e896ce38	7778	int32_t lsm6dso_long_cnt_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7779	{
cparata	3:4274d9103f1d	7780	int32_t ret;
cparata	3:4274d9103f1d	7781
cparata	3:4274d9103f1d	7782	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7783	if (ret == 0) {
cparata	3:4274d9103f1d	7784	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
cparata	3:4274d9103f1d	7785	}
cparata	3:4274d9103f1d	7786	if (ret == 0) {
cparata	3:4274d9103f1d	7787	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7788	}
cparata	3:4274d9103f1d	7789
cparata	3:4274d9103f1d	7790	return ret;
cparata	0:6d69e896ce38	7791	}
cparata	0:6d69e896ce38	7792
cparata	0:6d69e896ce38	7793	/**
cparata	0:6d69e896ce38	7794	* @brief FSM long counter status register. Long counter value is an
cparata	0:6d69e896ce38	7795	* unsigned integer value (16-bit format).[get]
cparata	0:6d69e896ce38	7796	*
cparata	0:6d69e896ce38	7797	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7798	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	7799	*
cparata	0:6d69e896ce38	7800	*/
cparata	0:6d69e896ce38	7801	int32_t lsm6dso_long_cnt_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7802	{
cparata	3:4274d9103f1d	7803	int32_t ret;
cparata	3:4274d9103f1d	7804
cparata	3:4274d9103f1d	7805	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7806	if (ret == 0) {
cparata	3:4274d9103f1d	7807	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
cparata	3:4274d9103f1d	7808	}
cparata	3:4274d9103f1d	7809	if (ret == 0) {
cparata	3:4274d9103f1d	7810	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7811	}
cparata	3:4274d9103f1d	7812
cparata	3:4274d9103f1d	7813	return ret;
cparata	0:6d69e896ce38	7814	}
cparata	0:6d69e896ce38	7815
cparata	0:6d69e896ce38	7816	/**
cparata	0:6d69e896ce38	7817	* @brief Clear FSM long counter value.[set]
cparata	0:6d69e896ce38	7818	*
cparata	0:6d69e896ce38	7819	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7820	* @param val change the values of fsm_lc_clr in
cparata	0:6d69e896ce38	7821	* reg FSM_LONG_COUNTER_CLEAR
cparata	0:6d69e896ce38	7822	*
cparata	0:6d69e896ce38	7823	*/
cparata	0:6d69e896ce38	7824	int32_t lsm6dso_long_clr_set(lsm6dso_ctx_t *ctx, lsm6dso_fsm_lc_clr_t val)
cparata	0:6d69e896ce38	7825	{
cparata	3:4274d9103f1d	7826	lsm6dso_fsm_long_counter_clear_t reg;
cparata	3:4274d9103f1d	7827	int32_t ret;
cparata	3:4274d9103f1d	7828
cparata	3:4274d9103f1d	7829	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7830	if (ret == 0) {
cparata	3:4274d9103f1d	7831	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
cparata	3:4274d9103f1d	7832	(uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7833	}
cparata	3:4274d9103f1d	7834	if (ret == 0) {
cparata	3:4274d9103f1d	7835	reg. fsm_lc_clr = (uint8_t)val;
cparata	3:4274d9103f1d	7836	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
cparata	3:4274d9103f1d	7837	(uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7838	}
cparata	3:4274d9103f1d	7839	if (ret == 0) {
cparata	3:4274d9103f1d	7840	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7841	}
cparata	3:4274d9103f1d	7842	return ret;
cparata	0:6d69e896ce38	7843	}
cparata	0:6d69e896ce38	7844
cparata	0:6d69e896ce38	7845	/**
cparata	0:6d69e896ce38	7846	* @brief Clear FSM long counter value.[get]
cparata	0:6d69e896ce38	7847	*
cparata	0:6d69e896ce38	7848	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7849	* @param val Get the values of fsm_lc_clr in
cparata	0:6d69e896ce38	7850	* reg FSM_LONG_COUNTER_CLEAR
cparata	0:6d69e896ce38	7851	*
cparata	0:6d69e896ce38	7852	*/
cparata	0:6d69e896ce38	7853	int32_t lsm6dso_long_clr_get(lsm6dso_ctx_t ctx, lsm6dso_fsm_lc_clr_t val)
cparata	0:6d69e896ce38	7854	{
cparata	3:4274d9103f1d	7855	lsm6dso_fsm_long_counter_clear_t reg;
cparata	3:4274d9103f1d	7856	int32_t ret;
cparata	3:4274d9103f1d	7857
cparata	3:4274d9103f1d	7858	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7859	if (ret == 0) {
cparata	3:4274d9103f1d	7860	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
cparata	3:4274d9103f1d	7861	(uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7862	}
cparata	3:4274d9103f1d	7863	if (ret == 0) {
cparata	3:4274d9103f1d	7864	switch (reg.fsm_lc_clr) {
cparata	3:4274d9103f1d	7865	case LSM6DSO_LC_NORMAL:
cparata	3:4274d9103f1d	7866	*val = LSM6DSO_LC_NORMAL;
cparata	3:4274d9103f1d	7867	break;
cparata	3:4274d9103f1d	7868	case LSM6DSO_LC_CLEAR:
cparata	3:4274d9103f1d	7869	*val = LSM6DSO_LC_CLEAR;
cparata	3:4274d9103f1d	7870	break;
cparata	3:4274d9103f1d	7871	case LSM6DSO_LC_CLEAR_DONE:
cparata	3:4274d9103f1d	7872	*val = LSM6DSO_LC_CLEAR_DONE;
cparata	3:4274d9103f1d	7873	break;
cparata	3:4274d9103f1d	7874	default:
cparata	3:4274d9103f1d	7875	*val = LSM6DSO_LC_NORMAL;
cparata	3:4274d9103f1d	7876	break;
cparata	3:4274d9103f1d	7877	}
cparata	3:4274d9103f1d	7878	}
cparata	3:4274d9103f1d	7879
cparata	3:4274d9103f1d	7880	if (ret == 0) {
cparata	3:4274d9103f1d	7881	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7882	}
cparata	3:4274d9103f1d	7883
cparata	3:4274d9103f1d	7884	return ret;
cparata	0:6d69e896ce38	7885	}
cparata	0:6d69e896ce38	7886
cparata	0:6d69e896ce38	7887	/**
cparata	0:6d69e896ce38	7888	* @brief FSM output registers[get]
cparata	0:6d69e896ce38	7889	*
cparata	0:6d69e896ce38	7890	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7891	* @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
cparata	0:6d69e896ce38	7892	*
cparata	0:6d69e896ce38	7893	*/
cparata	0:6d69e896ce38	7894	int32_t lsm6dso_fsm_out_get(lsm6dso_ctx_t ctx, lsm6dso_fsm_out_t val)
cparata	0:6d69e896ce38	7895	{
cparata	3:4274d9103f1d	7896	int32_t ret;
cparata	3:4274d9103f1d	7897
cparata	3:4274d9103f1d	7898	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7899	if (ret == 0) {
cparata	3:4274d9103f1d	7900	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_OUTS1, (uint8_t *)val, 16);
cparata	3:4274d9103f1d	7901	}
cparata	3:4274d9103f1d	7902	if (ret == 0) {
cparata	3:4274d9103f1d	7903	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7904	}
cparata	3:4274d9103f1d	7905
cparata	3:4274d9103f1d	7906	return ret;
cparata	0:6d69e896ce38	7907	}
cparata	0:6d69e896ce38	7908
cparata	0:6d69e896ce38	7909	/**
cparata	0:6d69e896ce38	7910	* @brief Finite State Machine ODR configuration.[set]
cparata	0:6d69e896ce38	7911	*
cparata	0:6d69e896ce38	7912	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7913	* @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
cparata	0:6d69e896ce38	7914	*
cparata	0:6d69e896ce38	7915	*/
cparata	0:6d69e896ce38	7916	int32_t lsm6dso_fsm_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_fsm_odr_t val)
cparata	0:6d69e896ce38	7917	{
cparata	3:4274d9103f1d	7918	lsm6dso_emb_func_odr_cfg_b_t reg;
cparata	3:4274d9103f1d	7919	int32_t ret;
cparata	3:4274d9103f1d	7920
cparata	3:4274d9103f1d	7921	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7922	if (ret == 0) {
cparata	3:4274d9103f1d	7923	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
cparata	3:4274d9103f1d	7924	(uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7925	}
cparata	3:4274d9103f1d	7926	if (ret == 0) {
cparata	3:4274d9103f1d	7927	reg.not_used_01 = 3; /* set default values */
cparata	3:4274d9103f1d	7928	reg.not_used_02 = 2; /* set default values */
cparata	3:4274d9103f1d	7929	reg.fsm_odr = (uint8_t)val;
cparata	3:4274d9103f1d	7930	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
cparata	3:4274d9103f1d	7931	(uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7932	}
cparata	3:4274d9103f1d	7933	if (ret == 0) {
cparata	3:4274d9103f1d	7934	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7935	}
cparata	3:4274d9103f1d	7936	return ret;
cparata	0:6d69e896ce38	7937	}
cparata	0:6d69e896ce38	7938
cparata	0:6d69e896ce38	7939	/**
cparata	0:6d69e896ce38	7940	* @brief Finite State Machine ODR configuration.[get]
cparata	0:6d69e896ce38	7941	*
cparata	0:6d69e896ce38	7942	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7943	* @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
cparata	0:6d69e896ce38	7944	*
cparata	0:6d69e896ce38	7945	*/
cparata	0:6d69e896ce38	7946	int32_t lsm6dso_fsm_data_rate_get(lsm6dso_ctx_t ctx, lsm6dso_fsm_odr_t val)
cparata	0:6d69e896ce38	7947	{
cparata	3:4274d9103f1d	7948	lsm6dso_emb_func_odr_cfg_b_t reg;
cparata	3:4274d9103f1d	7949	int32_t ret;
cparata	3:4274d9103f1d	7950
cparata	3:4274d9103f1d	7951	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7952	if (ret == 0) {
cparata	3:4274d9103f1d	7953	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
cparata	3:4274d9103f1d	7954	(uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7955	}
cparata	3:4274d9103f1d	7956	if (ret == 0) {
cparata	3:4274d9103f1d	7957	switch (reg.fsm_odr) {
cparata	3:4274d9103f1d	7958	case LSM6DSO_ODR_FSM_12Hz5:
cparata	3:4274d9103f1d	7959	*val = LSM6DSO_ODR_FSM_12Hz5;
cparata	3:4274d9103f1d	7960	break;
cparata	3:4274d9103f1d	7961	case LSM6DSO_ODR_FSM_26Hz:
cparata	3:4274d9103f1d	7962	*val = LSM6DSO_ODR_FSM_26Hz;
cparata	3:4274d9103f1d	7963	break;
cparata	3:4274d9103f1d	7964	case LSM6DSO_ODR_FSM_52Hz:
cparata	3:4274d9103f1d	7965	*val = LSM6DSO_ODR_FSM_52Hz;
cparata	3:4274d9103f1d	7966	break;
cparata	3:4274d9103f1d	7967	case LSM6DSO_ODR_FSM_104Hz:
cparata	3:4274d9103f1d	7968	*val = LSM6DSO_ODR_FSM_104Hz;
cparata	3:4274d9103f1d	7969	break;
cparata	3:4274d9103f1d	7970	default:
cparata	3:4274d9103f1d	7971	*val = LSM6DSO_ODR_FSM_12Hz5;
cparata	3:4274d9103f1d	7972	break;
cparata	3:4274d9103f1d	7973	}
cparata	3:4274d9103f1d	7974	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	7975	}
cparata	3:4274d9103f1d	7976
cparata	3:4274d9103f1d	7977	return ret;
cparata	0:6d69e896ce38	7978	}
cparata	0:6d69e896ce38	7979
cparata	0:6d69e896ce38	7980	/**
cparata	0:6d69e896ce38	7981	* @brief FSM initialization request.[set]
cparata	0:6d69e896ce38	7982	*
cparata	0:6d69e896ce38	7983	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7984	* @param val change the values of fsm_init in reg FSM_INIT
cparata	0:6d69e896ce38	7985	*
cparata	0:6d69e896ce38	7986	*/
cparata	0:6d69e896ce38	7987	int32_t lsm6dso_fsm_init_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	7988	{
cparata	3:4274d9103f1d	7989	lsm6dso_emb_func_init_b_t reg;
cparata	3:4274d9103f1d	7990	int32_t ret;
cparata	3:4274d9103f1d	7991
cparata	3:4274d9103f1d	7992	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	7993	if (ret == 0) {
cparata	3:4274d9103f1d	7994	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7995	}
cparata	3:4274d9103f1d	7996	if (ret == 0) {
cparata	3:4274d9103f1d	7997	reg.fsm_init = val;
cparata	3:4274d9103f1d	7998	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	7999	}
cparata	3:4274d9103f1d	8000	if (ret == 0) {
cparata	3:4274d9103f1d	8001	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8002	}
cparata	3:4274d9103f1d	8003
cparata	3:4274d9103f1d	8004	return ret;
cparata	0:6d69e896ce38	8005	}
cparata	0:6d69e896ce38	8006
cparata	0:6d69e896ce38	8007	/**
cparata	0:6d69e896ce38	8008	* @brief FSM initialization request.[get]
cparata	0:6d69e896ce38	8009	*
cparata	0:6d69e896ce38	8010	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8011	* @param val change the values of fsm_init in reg FSM_INIT
cparata	0:6d69e896ce38	8012	*
cparata	0:6d69e896ce38	8013	*/
cparata	0:6d69e896ce38	8014	int32_t lsm6dso_fsm_init_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	8015	{
cparata	3:4274d9103f1d	8016	lsm6dso_emb_func_init_b_t reg;
cparata	3:4274d9103f1d	8017	int32_t ret;
cparata	3:4274d9103f1d	8018
cparata	3:4274d9103f1d	8019	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	3:4274d9103f1d	8020	if (ret == 0) {
cparata	3:4274d9103f1d	8021	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8022	}
cparata	3:4274d9103f1d	8023	if (ret == 0) {
cparata	3:4274d9103f1d	8024	*val = reg.fsm_init;
cparata	3:4274d9103f1d	8025	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8026	}
cparata	3:4274d9103f1d	8027	return ret;
cparata	0:6d69e896ce38	8028	}
cparata	0:6d69e896ce38	8029
cparata	0:6d69e896ce38	8030	/**
cparata	0:6d69e896ce38	8031	* @brief FSM long counter timeout register (r/w). The long counter
cparata	0:6d69e896ce38	8032	* timeout value is an unsigned integer value (16-bit format).
cparata	0:6d69e896ce38	8033	* When the long counter value reached this value,
cparata	0:6d69e896ce38	8034	* the FSM generates an interrupt.[set]
cparata	0:6d69e896ce38	8035	*
cparata	0:6d69e896ce38	8036	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8037	* @param val the value of long counter
cparata	2:4d14e9edf37e	8038	*
cparata	2:4d14e9edf37e	8039	*/
cparata	2:4d14e9edf37e	8040	int32_t lsm6dso_long_cnt_int_value_set(lsm6dso_ctx_t *ctx, uint16_t val)
cparata	2:4d14e9edf37e	8041	{
cparata	3:4274d9103f1d	8042	int32_t ret;
cparata	3:4274d9103f1d	8043	uint8_t add_l;
cparata	3:4274d9103f1d	8044	uint8_t add_h;
cparata	3:4274d9103f1d	8045
cparata	3:4274d9103f1d	8046	add_h = (uint8_t)((val & 0xFF00U) >> 8);
cparata	3:4274d9103f1d	8047	add_l = (uint8_t)(val & 0x00FFU);
cparata	3:4274d9103f1d	8048
cparata	3:4274d9103f1d	8049	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &add_l);
cparata	3:4274d9103f1d	8050	if (ret == 0) {
cparata	3:4274d9103f1d	8051	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &add_h);
cparata	3:4274d9103f1d	8052	}
cparata	3:4274d9103f1d	8053
cparata	3:4274d9103f1d	8054	return ret;
cparata	0:6d69e896ce38	8055	}
cparata	0:6d69e896ce38	8056
cparata	0:6d69e896ce38	8057	/**
cparata	0:6d69e896ce38	8058	* @brief FSM long counter timeout register (r/w). The long counter
cparata	0:6d69e896ce38	8059	* timeout value is an unsigned integer value (16-bit format).
cparata	0:6d69e896ce38	8060	* When the long counter value reached this value,
cparata	0:6d69e896ce38	8061	* the FSM generates an interrupt.[get]
cparata	0:6d69e896ce38	8062	*
cparata	2:4d14e9edf37e	8063	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8064	* @param val buffer that stores the value of long counter
cparata	2:4d14e9edf37e	8065	*
cparata	2:4d14e9edf37e	8066	*/
cparata	2:4d14e9edf37e	8067	int32_t lsm6dso_long_cnt_int_value_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	2:4d14e9edf37e	8068	{
cparata	3:4274d9103f1d	8069	int32_t ret;
cparata	3:4274d9103f1d	8070	uint8_t add_l;
cparata	3:4274d9103f1d	8071	uint8_t add_h;
cparata	3:4274d9103f1d	8072
cparata	3:4274d9103f1d	8073	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &add_l);
cparata	3:4274d9103f1d	8074	if (ret == 0) {
cparata	3:4274d9103f1d	8075	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &add_h);
cparata	3:4274d9103f1d	8076	*val = add_h;
cparata	3:4274d9103f1d	8077	val = val << 8;
cparata	3:4274d9103f1d	8078	*val += add_l;
cparata	3:4274d9103f1d	8079	}
cparata	3:4274d9103f1d	8080
cparata	3:4274d9103f1d	8081	return ret;
cparata	0:6d69e896ce38	8082	}
cparata	0:6d69e896ce38	8083
cparata	0:6d69e896ce38	8084	/**
cparata	0:6d69e896ce38	8085	* @brief FSM number of programs register.[set]
cparata	0:6d69e896ce38	8086	*
cparata	0:6d69e896ce38	8087	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8088	* @param val value to write
cparata	2:4d14e9edf37e	8089	*
cparata	2:4d14e9edf37e	8090	*/
cparata	2:4d14e9edf37e	8091	int32_t lsm6dso_fsm_number_of_programs_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	2:4d14e9edf37e	8092	{
cparata	3:4274d9103f1d	8093	int32_t ret;
cparata	3:4274d9103f1d	8094
cparata	3:4274d9103f1d	8095	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_PROGRAMS, &val);
cparata	3:4274d9103f1d	8096
cparata	3:4274d9103f1d	8097	return ret;
cparata	0:6d69e896ce38	8098	}
cparata	0:6d69e896ce38	8099
cparata	0:6d69e896ce38	8100	/**
cparata	0:6d69e896ce38	8101	* @brief FSM number of programs register.[get]
cparata	0:6d69e896ce38	8102	*
cparata	0:6d69e896ce38	8103	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8104	* @param val buffer that stores data read.
cparata	2:4d14e9edf37e	8105	*
cparata	2:4d14e9edf37e	8106	*/
cparata	2:4d14e9edf37e	8107	int32_t lsm6dso_fsm_number_of_programs_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	2:4d14e9edf37e	8108	{
cparata	3:4274d9103f1d	8109	int32_t ret;
cparata	3:4274d9103f1d	8110
cparata	3:4274d9103f1d	8111	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_PROGRAMS, val);
cparata	3:4274d9103f1d	8112
cparata	3:4274d9103f1d	8113	return ret;
cparata	0:6d69e896ce38	8114	}
cparata	0:6d69e896ce38	8115
cparata	0:6d69e896ce38	8116	/**
cparata	0:6d69e896ce38	8117	* @brief FSM start address register (r/w).
cparata	0:6d69e896ce38	8118	* First available address is 0x033C.[set]
cparata	0:6d69e896ce38	8119	*
cparata	0:6d69e896ce38	8120	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8121	* @param val the value of start address
cparata	2:4d14e9edf37e	8122	*
cparata	2:4d14e9edf37e	8123	*/
cparata	2:4d14e9edf37e	8124	int32_t lsm6dso_fsm_start_address_set(lsm6dso_ctx_t *ctx, uint16_t val)
cparata	2:4d14e9edf37e	8125	{
cparata	3:4274d9103f1d	8126	int32_t ret;
cparata	3:4274d9103f1d	8127	uint8_t add_l;
cparata	3:4274d9103f1d	8128	uint8_t add_h;
cparata	3:4274d9103f1d	8129
cparata	3:4274d9103f1d	8130	add_h = (uint8_t)((val & 0xFF00U) >> 8);
cparata	3:4274d9103f1d	8131	add_l = (uint8_t)(val & 0x00FFU);
cparata	3:4274d9103f1d	8132
cparata	3:4274d9103f1d	8133	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_L, &add_l);
cparata	3:4274d9103f1d	8134	if (ret == 0) {
cparata	3:4274d9103f1d	8135	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_H, &add_h);
cparata	3:4274d9103f1d	8136	}
cparata	3:4274d9103f1d	8137	return ret;
cparata	0:6d69e896ce38	8138	}
cparata	0:6d69e896ce38	8139
cparata	0:6d69e896ce38	8140	/**
cparata	0:6d69e896ce38	8141	* @brief FSM start address register (r/w).
cparata	0:6d69e896ce38	8142	* First available address is 0x033C.[get]
cparata	0:6d69e896ce38	8143	*
cparata	0:6d69e896ce38	8144	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8145	* @param val buffer the value of start address.
cparata	2:4d14e9edf37e	8146	*
cparata	2:4d14e9edf37e	8147	*/
cparata	2:4d14e9edf37e	8148	int32_t lsm6dso_fsm_start_address_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	2:4d14e9edf37e	8149	{
cparata	3:4274d9103f1d	8150	int32_t ret;
cparata	3:4274d9103f1d	8151	uint8_t add_l;
cparata	3:4274d9103f1d	8152	uint8_t add_h;
cparata	3:4274d9103f1d	8153
cparata	3:4274d9103f1d	8154	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_L, &add_l);
cparata	3:4274d9103f1d	8155	if (ret == 0) {
cparata	3:4274d9103f1d	8156	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_H, &add_h);
cparata	3:4274d9103f1d	8157	*val = add_h;
cparata	3:4274d9103f1d	8158	val = val << 8;
cparata	3:4274d9103f1d	8159	*val += add_l;
cparata	3:4274d9103f1d	8160	}
cparata	3:4274d9103f1d	8161	return ret;
cparata	0:6d69e896ce38	8162	}
cparata	0:6d69e896ce38	8163
cparata	0:6d69e896ce38	8164	/**
cparata	0:6d69e896ce38	8165	* @}
cparata	0:6d69e896ce38	8166	*
cparata	0:6d69e896ce38	8167	*/
cparata	0:6d69e896ce38	8168
cparata	0:6d69e896ce38	8169	/**
cparata	0:6d69e896ce38	8170	* @defgroup LSM6DSO_Sensor_hub
cparata	0:6d69e896ce38	8171	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	8172	* sensor hub.
cparata	0:6d69e896ce38	8173	* @{
cparata	0:6d69e896ce38	8174	*
cparata	0:6d69e896ce38	8175	*/
cparata	0:6d69e896ce38	8176
cparata	0:6d69e896ce38	8177	/**
cparata	2:4d14e9edf37e	8178	* @brief Sensor hub output registers.[get]
cparata	2:4d14e9edf37e	8179	*
cparata	2:4d14e9edf37e	8180	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8181	* @param val values read from registers SENSOR_HUB_1 to SENSOR_HUB_18
cparata	2:4d14e9edf37e	8182	* @param len number of consecutive register to read (max 18)
cparata	2:4d14e9edf37e	8183	*
cparata	2:4d14e9edf37e	8184	*/
cparata	2:4d14e9edf37e	8185	int32_t lsm6dso_sh_read_data_raw_get(lsm6dso_ctx_t ctx, uint8_t val,
cparata	2:4d14e9edf37e	8186	uint8_t len)
cparata	0:6d69e896ce38	8187	{
cparata	3:4274d9103f1d	8188	int32_t ret;
cparata	3:4274d9103f1d	8189
cparata	3:4274d9103f1d	8190	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8191	if (ret == 0) {
cparata	3:4274d9103f1d	8192	ret = lsm6dso_read_reg(ctx, LSM6DSO_SENSOR_HUB_1, (uint8_t *) val, len);
cparata	3:4274d9103f1d	8193	}
cparata	3:4274d9103f1d	8194	if (ret == 0) {
cparata	3:4274d9103f1d	8195	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8196	}
cparata	3:4274d9103f1d	8197
cparata	3:4274d9103f1d	8198	return ret;
cparata	0:6d69e896ce38	8199	}
cparata	0:6d69e896ce38	8200
cparata	0:6d69e896ce38	8201	/**
cparata	0:6d69e896ce38	8202	* @brief Number of external sensors to be read by the sensor hub.[set]
cparata	0:6d69e896ce38	8203	*
cparata	0:6d69e896ce38	8204	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8205	* @param val change the values of aux_sens_on in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8206	*
cparata	0:6d69e896ce38	8207	*/
cparata	0:6d69e896ce38	8208	int32_t lsm6dso_sh_slave_connected_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8209	lsm6dso_aux_sens_on_t val)
cparata	0:6d69e896ce38	8210	{
cparata	3:4274d9103f1d	8211	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8212	int32_t ret;
cparata	3:4274d9103f1d	8213
cparata	3:4274d9103f1d	8214	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8215	if (ret == 0) {
cparata	3:4274d9103f1d	8216	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8217	}
cparata	3:4274d9103f1d	8218	if (ret == 0) {
cparata	3:4274d9103f1d	8219	reg.aux_sens_on = (uint8_t)val;
cparata	3:4274d9103f1d	8220	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8221	}
cparata	3:4274d9103f1d	8222	if (ret == 0) {
cparata	3:4274d9103f1d	8223	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8224	}
cparata	3:4274d9103f1d	8225	return ret;
cparata	0:6d69e896ce38	8226	}
cparata	0:6d69e896ce38	8227
cparata	0:6d69e896ce38	8228	/**
cparata	0:6d69e896ce38	8229	* @brief Number of external sensors to be read by the sensor hub.[get]
cparata	0:6d69e896ce38	8230	*
cparata	0:6d69e896ce38	8231	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8232	* @param val Get the values of aux_sens_on in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8233	*
cparata	0:6d69e896ce38	8234	*/
cparata	0:6d69e896ce38	8235	int32_t lsm6dso_sh_slave_connected_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8236	lsm6dso_aux_sens_on_t *val)
cparata	0:6d69e896ce38	8237	{
cparata	3:4274d9103f1d	8238	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8239	int32_t ret;
cparata	3:4274d9103f1d	8240
cparata	3:4274d9103f1d	8241	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8242	if (ret == 0) {
cparata	3:4274d9103f1d	8243	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8244	}
cparata	3:4274d9103f1d	8245	if (ret == 0) {
cparata	3:4274d9103f1d	8246	switch (reg.aux_sens_on) {
cparata	3:4274d9103f1d	8247	case LSM6DSO_SLV_0:
cparata	3:4274d9103f1d	8248	*val = LSM6DSO_SLV_0;
cparata	3:4274d9103f1d	8249	break;
cparata	3:4274d9103f1d	8250	case LSM6DSO_SLV_0_1:
cparata	3:4274d9103f1d	8251	*val = LSM6DSO_SLV_0_1;
cparata	3:4274d9103f1d	8252	break;
cparata	3:4274d9103f1d	8253	case LSM6DSO_SLV_0_1_2:
cparata	3:4274d9103f1d	8254	*val = LSM6DSO_SLV_0_1_2;
cparata	3:4274d9103f1d	8255	break;
cparata	3:4274d9103f1d	8256	case LSM6DSO_SLV_0_1_2_3:
cparata	3:4274d9103f1d	8257	*val = LSM6DSO_SLV_0_1_2_3;
cparata	3:4274d9103f1d	8258	break;
cparata	3:4274d9103f1d	8259	default:
cparata	3:4274d9103f1d	8260	*val = LSM6DSO_SLV_0;
cparata	3:4274d9103f1d	8261	break;
cparata	3:4274d9103f1d	8262	}
cparata	3:4274d9103f1d	8263	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8264	}
cparata	3:4274d9103f1d	8265
cparata	3:4274d9103f1d	8266	return ret;
cparata	0:6d69e896ce38	8267	}
cparata	0:6d69e896ce38	8268
cparata	0:6d69e896ce38	8269	/**
cparata	0:6d69e896ce38	8270	* @brief Sensor hub I2C master enable.[set]
cparata	0:6d69e896ce38	8271	*
cparata	0:6d69e896ce38	8272	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8273	* @param val change the values of master_on in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8274	*
cparata	0:6d69e896ce38	8275	*/
cparata	0:6d69e896ce38	8276	int32_t lsm6dso_sh_master_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	8277	{
cparata	3:4274d9103f1d	8278	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8279	int32_t ret;
cparata	3:4274d9103f1d	8280
cparata	3:4274d9103f1d	8281	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8282	if (ret == 0) {
cparata	3:4274d9103f1d	8283	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8284	}
cparata	3:4274d9103f1d	8285	if (ret == 0) {
cparata	3:4274d9103f1d	8286	reg.master_on = val;
cparata	3:4274d9103f1d	8287	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8288	}
cparata	3:4274d9103f1d	8289	if (ret == 0) {
cparata	3:4274d9103f1d	8290	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8291	}
cparata	3:4274d9103f1d	8292	return ret;
cparata	0:6d69e896ce38	8293	}
cparata	0:6d69e896ce38	8294
cparata	0:6d69e896ce38	8295	/**
cparata	0:6d69e896ce38	8296	* @brief Sensor hub I2C master enable.[get]
cparata	0:6d69e896ce38	8297	*
cparata	0:6d69e896ce38	8298	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8299	* @param val change the values of master_on in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8300	*
cparata	0:6d69e896ce38	8301	*/
cparata	0:6d69e896ce38	8302	int32_t lsm6dso_sh_master_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	8303	{
cparata	3:4274d9103f1d	8304	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8305	int32_t ret;
cparata	3:4274d9103f1d	8306
cparata	3:4274d9103f1d	8307	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8308	if (ret == 0) {
cparata	3:4274d9103f1d	8309	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8310	}
cparata	3:4274d9103f1d	8311	if (ret == 0) {
cparata	3:4274d9103f1d	8312	*val = reg.master_on;
cparata	3:4274d9103f1d	8313	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8314	}
cparata	3:4274d9103f1d	8315
cparata	3:4274d9103f1d	8316	return ret;
cparata	0:6d69e896ce38	8317	}
cparata	0:6d69e896ce38	8318
cparata	0:6d69e896ce38	8319	/**
cparata	0:6d69e896ce38	8320	* @brief Master I2C pull-up enable.[set]
cparata	0:6d69e896ce38	8321	*
cparata	0:6d69e896ce38	8322	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8323	* @param val change the values of shub_pu_en in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8324	*
cparata	0:6d69e896ce38	8325	*/
cparata	0:6d69e896ce38	8326	int32_t lsm6dso_sh_pin_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_shub_pu_en_t val)
cparata	0:6d69e896ce38	8327	{
cparata	3:4274d9103f1d	8328	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8329	int32_t ret;
cparata	3:4274d9103f1d	8330
cparata	3:4274d9103f1d	8331	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8332	if (ret == 0) {
cparata	3:4274d9103f1d	8333	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8334	}
cparata	3:4274d9103f1d	8335	if (ret == 0) {
cparata	3:4274d9103f1d	8336	reg.shub_pu_en = (uint8_t)val;
cparata	3:4274d9103f1d	8337	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8338	}
cparata	3:4274d9103f1d	8339	if (ret == 0) {
cparata	3:4274d9103f1d	8340	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8341	}
cparata	3:4274d9103f1d	8342
cparata	3:4274d9103f1d	8343	return ret;
cparata	0:6d69e896ce38	8344	}
cparata	0:6d69e896ce38	8345
cparata	0:6d69e896ce38	8346	/**
cparata	0:6d69e896ce38	8347	* @brief Master I2C pull-up enable.[get]
cparata	0:6d69e896ce38	8348	*
cparata	0:6d69e896ce38	8349	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8350	* @param val Get the values of shub_pu_en in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8351	*
cparata	0:6d69e896ce38	8352	*/
cparata	0:6d69e896ce38	8353	int32_t lsm6dso_sh_pin_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8354	lsm6dso_shub_pu_en_t *val)
cparata	0:6d69e896ce38	8355	{
cparata	3:4274d9103f1d	8356	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8357	int32_t ret;
cparata	3:4274d9103f1d	8358
cparata	3:4274d9103f1d	8359	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8360	if (ret == 0) {
cparata	3:4274d9103f1d	8361	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8362	}
cparata	3:4274d9103f1d	8363	if (ret == 0) {
cparata	3:4274d9103f1d	8364	switch (reg.shub_pu_en) {
cparata	3:4274d9103f1d	8365	case LSM6DSO_EXT_PULL_UP:
cparata	3:4274d9103f1d	8366	*val = LSM6DSO_EXT_PULL_UP;
cparata	3:4274d9103f1d	8367	break;
cparata	3:4274d9103f1d	8368	case LSM6DSO_INTERNAL_PULL_UP:
cparata	3:4274d9103f1d	8369	*val = LSM6DSO_INTERNAL_PULL_UP;
cparata	3:4274d9103f1d	8370	break;
cparata	3:4274d9103f1d	8371	default:
cparata	3:4274d9103f1d	8372	*val = LSM6DSO_EXT_PULL_UP;
cparata	3:4274d9103f1d	8373	break;
cparata	3:4274d9103f1d	8374	}
cparata	3:4274d9103f1d	8375	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8376	}
cparata	3:4274d9103f1d	8377
cparata	3:4274d9103f1d	8378	return ret;
cparata	0:6d69e896ce38	8379	}
cparata	0:6d69e896ce38	8380
cparata	0:6d69e896ce38	8381	/**
cparata	0:6d69e896ce38	8382	* @brief I2C interface pass-through.[set]
cparata	0:6d69e896ce38	8383	*
cparata	0:6d69e896ce38	8384	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8385	* @param val change the values of pass_through_mode in
cparata	0:6d69e896ce38	8386	* reg MASTER_CONFIG
cparata	0:6d69e896ce38	8387	*
cparata	0:6d69e896ce38	8388	*/
cparata	0:6d69e896ce38	8389	int32_t lsm6dso_sh_pass_through_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	8390	{
cparata	3:4274d9103f1d	8391	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8392	int32_t ret;
cparata	3:4274d9103f1d	8393
cparata	3:4274d9103f1d	8394	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8395	if (ret == 0) {
cparata	3:4274d9103f1d	8396	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8397	}
cparata	3:4274d9103f1d	8398	if (ret == 0) {
cparata	3:4274d9103f1d	8399	reg.pass_through_mode = val;
cparata	3:4274d9103f1d	8400	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8401	}
cparata	3:4274d9103f1d	8402	if (ret == 0) {
cparata	3:4274d9103f1d	8403	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8404	}
cparata	3:4274d9103f1d	8405
cparata	3:4274d9103f1d	8406	return ret;
cparata	0:6d69e896ce38	8407	}
cparata	0:6d69e896ce38	8408
cparata	0:6d69e896ce38	8409	/**
cparata	0:6d69e896ce38	8410	* @brief I2C interface pass-through.[get]
cparata	0:6d69e896ce38	8411	*
cparata	0:6d69e896ce38	8412	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8413	* @param val change the values of pass_through_mode in
cparata	0:6d69e896ce38	8414	* reg MASTER_CONFIG
cparata	0:6d69e896ce38	8415	*
cparata	0:6d69e896ce38	8416	*/
cparata	0:6d69e896ce38	8417	int32_t lsm6dso_sh_pass_through_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	8418	{
cparata	3:4274d9103f1d	8419	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8420	int32_t ret;
cparata	3:4274d9103f1d	8421
cparata	3:4274d9103f1d	8422	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8423	if (ret == 0) {
cparata	3:4274d9103f1d	8424	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8425	}
cparata	3:4274d9103f1d	8426	if (ret == 0) {
cparata	3:4274d9103f1d	8427	*val = reg.pass_through_mode;
cparata	3:4274d9103f1d	8428	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8429	}
cparata	3:4274d9103f1d	8430
cparata	3:4274d9103f1d	8431	return ret;
cparata	0:6d69e896ce38	8432	}
cparata	0:6d69e896ce38	8433
cparata	0:6d69e896ce38	8434	/**
cparata	0:6d69e896ce38	8435	* @brief Sensor hub trigger signal selection.[set]
cparata	0:6d69e896ce38	8436	*
cparata	0:6d69e896ce38	8437	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8438	* @param val change the values of start_config in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8439	*
cparata	0:6d69e896ce38	8440	*/
cparata	0:6d69e896ce38	8441	int32_t lsm6dso_sh_syncro_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8442	lsm6dso_start_config_t val)
cparata	0:6d69e896ce38	8443	{
cparata	3:4274d9103f1d	8444	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8445	int32_t ret;
cparata	3:4274d9103f1d	8446
cparata	3:4274d9103f1d	8447	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8448	if (ret == 0) {
cparata	3:4274d9103f1d	8449	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8450	}
cparata	3:4274d9103f1d	8451	if (ret == 0) {
cparata	3:4274d9103f1d	8452	reg.start_config = (uint8_t)val;
cparata	3:4274d9103f1d	8453	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8454	}
cparata	3:4274d9103f1d	8455	if (ret == 0) {
cparata	3:4274d9103f1d	8456	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8457	}
cparata	3:4274d9103f1d	8458
cparata	3:4274d9103f1d	8459	return ret;
cparata	0:6d69e896ce38	8460	}
cparata	0:6d69e896ce38	8461
cparata	0:6d69e896ce38	8462	/**
cparata	0:6d69e896ce38	8463	* @brief Sensor hub trigger signal selection.[get]
cparata	0:6d69e896ce38	8464	*
cparata	0:6d69e896ce38	8465	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8466	* @param val Get the values of start_config in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8467	*
cparata	0:6d69e896ce38	8468	*/
cparata	0:6d69e896ce38	8469	int32_t lsm6dso_sh_syncro_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8470	lsm6dso_start_config_t *val)
cparata	0:6d69e896ce38	8471	{
cparata	3:4274d9103f1d	8472	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8473	int32_t ret;
cparata	3:4274d9103f1d	8474
cparata	3:4274d9103f1d	8475	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8476	if (ret == 0) {
cparata	3:4274d9103f1d	8477	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8478	}
cparata	3:4274d9103f1d	8479	if (ret == 0) {
cparata	3:4274d9103f1d	8480	switch (reg.start_config) {
cparata	3:4274d9103f1d	8481	case LSM6DSO_EXT_ON_INT2_PIN:
cparata	3:4274d9103f1d	8482	*val = LSM6DSO_EXT_ON_INT2_PIN;
cparata	3:4274d9103f1d	8483	break;
cparata	3:4274d9103f1d	8484	case LSM6DSO_XL_GY_DRDY:
cparata	3:4274d9103f1d	8485	*val = LSM6DSO_XL_GY_DRDY;
cparata	3:4274d9103f1d	8486	break;
cparata	3:4274d9103f1d	8487	default:
cparata	3:4274d9103f1d	8488	*val = LSM6DSO_EXT_ON_INT2_PIN;
cparata	3:4274d9103f1d	8489	break;
cparata	3:4274d9103f1d	8490	}
cparata	3:4274d9103f1d	8491	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8492	}
cparata	3:4274d9103f1d	8493	return ret;
cparata	0:6d69e896ce38	8494	}
cparata	0:6d69e896ce38	8495
cparata	0:6d69e896ce38	8496	/**
cparata	0:6d69e896ce38	8497	* @brief Slave 0 write operation is performed only at the first
cparata	0:6d69e896ce38	8498	* sensor hub cycle.[set]
cparata	0:6d69e896ce38	8499	*
cparata	0:6d69e896ce38	8500	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8501	* @param val change the values of write_once in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8502	*
cparata	0:6d69e896ce38	8503	*/
cparata	0:6d69e896ce38	8504	int32_t lsm6dso_sh_write_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8505	lsm6dso_write_once_t val)
cparata	0:6d69e896ce38	8506	{
cparata	3:4274d9103f1d	8507	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8508	int32_t ret;
cparata	3:4274d9103f1d	8509
cparata	3:4274d9103f1d	8510	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8511	if (ret == 0) {
cparata	3:4274d9103f1d	8512	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8513	}
cparata	3:4274d9103f1d	8514	if (ret == 0) {
cparata	3:4274d9103f1d	8515	reg.write_once = (uint8_t)val;
cparata	3:4274d9103f1d	8516	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8517	}
cparata	3:4274d9103f1d	8518	if (ret == 0) {
cparata	3:4274d9103f1d	8519	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8520	}
cparata	3:4274d9103f1d	8521
cparata	3:4274d9103f1d	8522	return ret;
cparata	0:6d69e896ce38	8523	}
cparata	0:6d69e896ce38	8524
cparata	0:6d69e896ce38	8525	/**
cparata	0:6d69e896ce38	8526	* @brief Slave 0 write operation is performed only at the first sensor
cparata	0:6d69e896ce38	8527	* hub cycle.[get]
cparata	0:6d69e896ce38	8528	*
cparata	0:6d69e896ce38	8529	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8530	* @param val Get the values of write_once in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8531	*
cparata	0:6d69e896ce38	8532	*/
cparata	0:6d69e896ce38	8533	int32_t lsm6dso_sh_write_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8534	lsm6dso_write_once_t *val)
cparata	0:6d69e896ce38	8535	{
cparata	3:4274d9103f1d	8536	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8537	int32_t ret;
cparata	3:4274d9103f1d	8538
cparata	3:4274d9103f1d	8539	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8540	if (ret == 0) {
cparata	3:4274d9103f1d	8541	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8542	}
cparata	3:4274d9103f1d	8543	if (ret == 0) {
cparata	3:4274d9103f1d	8544	switch (reg.write_once) {
cparata	3:4274d9103f1d	8545	case LSM6DSO_EACH_SH_CYCLE:
cparata	3:4274d9103f1d	8546	*val = LSM6DSO_EACH_SH_CYCLE;
cparata	3:4274d9103f1d	8547	break;
cparata	3:4274d9103f1d	8548	case LSM6DSO_ONLY_FIRST_CYCLE:
cparata	3:4274d9103f1d	8549	*val = LSM6DSO_ONLY_FIRST_CYCLE;
cparata	3:4274d9103f1d	8550	break;
cparata	3:4274d9103f1d	8551	default:
cparata	3:4274d9103f1d	8552	*val = LSM6DSO_EACH_SH_CYCLE;
cparata	3:4274d9103f1d	8553	break;
cparata	3:4274d9103f1d	8554	}
cparata	3:4274d9103f1d	8555	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8556	}
cparata	3:4274d9103f1d	8557
cparata	3:4274d9103f1d	8558	return ret;
cparata	0:6d69e896ce38	8559	}
cparata	0:6d69e896ce38	8560
cparata	0:6d69e896ce38	8561	/**
cparata	0:6d69e896ce38	8562	* @brief Reset Master logic and output registers.[set]
cparata	0:6d69e896ce38	8563	*
cparata	0:6d69e896ce38	8564	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8565	*
cparata	0:6d69e896ce38	8566	*/
cparata	0:6d69e896ce38	8567	int32_t lsm6dso_sh_reset_set(lsm6dso_ctx_t *ctx)
cparata	0:6d69e896ce38	8568	{
cparata	3:4274d9103f1d	8569	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8570	int32_t ret;
cparata	3:4274d9103f1d	8571
cparata	3:4274d9103f1d	8572	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8573	if (ret == 0) {
cparata	3:4274d9103f1d	8574	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8575	}
cparata	3:4274d9103f1d	8576	if (ret == 0) {
cparata	3:4274d9103f1d	8577	reg.rst_master_regs = PROPERTY_ENABLE;
cparata	3:4274d9103f1d	8578	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8579	}
cparata	3:4274d9103f1d	8580	if (ret == 0) {
cparata	3:4274d9103f1d	8581	reg.rst_master_regs = PROPERTY_DISABLE;
cparata	3:4274d9103f1d	8582	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8583	}
cparata	3:4274d9103f1d	8584	if (ret == 0) {
cparata	3:4274d9103f1d	8585	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8586	}
cparata	3:4274d9103f1d	8587
cparata	3:4274d9103f1d	8588	return ret;
cparata	0:6d69e896ce38	8589	}
cparata	0:6d69e896ce38	8590
cparata	0:6d69e896ce38	8591	/**
cparata	0:6d69e896ce38	8592	* @brief Reset Master logic and output registers.[get]
cparata	0:6d69e896ce38	8593	*
cparata	0:6d69e896ce38	8594	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8595	* @param val change the values of rst_master_regs in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8596	*
cparata	0:6d69e896ce38	8597	*/
cparata	0:6d69e896ce38	8598	int32_t lsm6dso_sh_reset_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	8599	{
cparata	3:4274d9103f1d	8600	lsm6dso_master_config_t reg;
cparata	3:4274d9103f1d	8601	int32_t ret;
cparata	3:4274d9103f1d	8602
cparata	3:4274d9103f1d	8603	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8604	if (ret == 0) {
cparata	3:4274d9103f1d	8605	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8606	}
cparata	3:4274d9103f1d	8607	if (ret == 0) {
cparata	3:4274d9103f1d	8608	*val = reg.rst_master_regs;
cparata	3:4274d9103f1d	8609	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8610	}
cparata	3:4274d9103f1d	8611	return ret;
cparata	0:6d69e896ce38	8612	}
cparata	0:6d69e896ce38	8613
cparata	0:6d69e896ce38	8614	/**
cparata	0:6d69e896ce38	8615	* @brief Rate at which the master communicates.[set]
cparata	0:6d69e896ce38	8616	*
cparata	0:6d69e896ce38	8617	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8618	* @param val change the values of shub_odr in reg slv1_CONFIG
cparata	0:6d69e896ce38	8619	*
cparata	0:6d69e896ce38	8620	*/
cparata	0:6d69e896ce38	8621	int32_t lsm6dso_sh_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_shub_odr_t val)
cparata	0:6d69e896ce38	8622	{
cparata	3:4274d9103f1d	8623	lsm6dso_slv0_config_t reg;
cparata	3:4274d9103f1d	8624	int32_t ret;
cparata	3:4274d9103f1d	8625
cparata	3:4274d9103f1d	8626	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8627	if (ret == 0) {
cparata	3:4274d9103f1d	8628	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8629	}
cparata	3:4274d9103f1d	8630	if (ret == 0) {
cparata	3:4274d9103f1d	8631	reg.shub_odr = (uint8_t)val;
cparata	3:4274d9103f1d	8632	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8633	}
cparata	3:4274d9103f1d	8634	if (ret == 0) {
cparata	3:4274d9103f1d	8635	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8636	}
cparata	3:4274d9103f1d	8637
cparata	3:4274d9103f1d	8638	return ret;
cparata	0:6d69e896ce38	8639	}
cparata	0:6d69e896ce38	8640
cparata	0:6d69e896ce38	8641	/**
cparata	0:6d69e896ce38	8642	* @brief Rate at which the master communicates.[get]
cparata	0:6d69e896ce38	8643	*
cparata	0:6d69e896ce38	8644	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8645	* @param val Get the values of shub_odr in reg slv1_CONFIG
cparata	0:6d69e896ce38	8646	*
cparata	0:6d69e896ce38	8647	*/
cparata	0:6d69e896ce38	8648	int32_t lsm6dso_sh_data_rate_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8649	lsm6dso_shub_odr_t *val)
cparata	0:6d69e896ce38	8650	{
cparata	3:4274d9103f1d	8651	lsm6dso_slv0_config_t reg;
cparata	3:4274d9103f1d	8652	int32_t ret;
cparata	3:4274d9103f1d	8653
cparata	3:4274d9103f1d	8654	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8655	if (ret == 0) {
cparata	3:4274d9103f1d	8656	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8657	}
cparata	3:4274d9103f1d	8658	if (ret == 0) {
cparata	3:4274d9103f1d	8659	switch (reg.shub_odr) {
cparata	3:4274d9103f1d	8660	case LSM6DSO_SH_ODR_104Hz:
cparata	3:4274d9103f1d	8661	*val = LSM6DSO_SH_ODR_104Hz;
cparata	3:4274d9103f1d	8662	break;
cparata	3:4274d9103f1d	8663	case LSM6DSO_SH_ODR_52Hz:
cparata	3:4274d9103f1d	8664	*val = LSM6DSO_SH_ODR_52Hz;
cparata	3:4274d9103f1d	8665	break;
cparata	3:4274d9103f1d	8666	case LSM6DSO_SH_ODR_26Hz:
cparata	3:4274d9103f1d	8667	*val = LSM6DSO_SH_ODR_26Hz;
cparata	3:4274d9103f1d	8668	break;
cparata	3:4274d9103f1d	8669	case LSM6DSO_SH_ODR_13Hz:
cparata	3:4274d9103f1d	8670	*val = LSM6DSO_SH_ODR_13Hz;
cparata	3:4274d9103f1d	8671	break;
cparata	3:4274d9103f1d	8672	default:
cparata	3:4274d9103f1d	8673	*val = LSM6DSO_SH_ODR_104Hz;
cparata	3:4274d9103f1d	8674	break;
cparata	3:4274d9103f1d	8675	}
cparata	3:4274d9103f1d	8676	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8677	}
cparata	3:4274d9103f1d	8678
cparata	3:4274d9103f1d	8679	return ret;
cparata	0:6d69e896ce38	8680	}
cparata	0:6d69e896ce38	8681
cparata	0:6d69e896ce38	8682	/**
cparata	0:6d69e896ce38	8683	* @brief Configure slave 0 for perform a write.[set]
cparata	0:6d69e896ce38	8684	*
cparata	0:6d69e896ce38	8685	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8686	* @param val a structure that contain
cparata	0:6d69e896ce38	8687	* - uint8_t slv1_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8688	* - uint8_t slv1_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8689	* - uint8_t slv1_data; 8 bit data to write
cparata	0:6d69e896ce38	8690	*
cparata	0:6d69e896ce38	8691	*/
cparata	0:6d69e896ce38	8692	int32_t lsm6dso_sh_cfg_write(lsm6dso_ctx_t ctx, lsm6dso_sh_cfg_write_t val)
cparata	0:6d69e896ce38	8693	{
cparata	3:4274d9103f1d	8694	lsm6dso_slv0_add_t reg;
cparata	3:4274d9103f1d	8695	int32_t ret;
cparata	3:4274d9103f1d	8696
cparata	3:4274d9103f1d	8697	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8698	if (ret == 0) {
cparata	3:4274d9103f1d	8699	reg.slave0 = val->slv0_add;
cparata	3:4274d9103f1d	8700	reg.rw_0 = 0;
cparata	3:4274d9103f1d	8701	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t *)&reg, 1);
cparata	3:4274d9103f1d	8702	}
cparata	3:4274d9103f1d	8703	if (ret == 0) {
cparata	3:4274d9103f1d	8704	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD,
cparata	3:4274d9103f1d	8705	&(val->slv0_subadd), 1);
cparata	3:4274d9103f1d	8706	}
cparata	3:4274d9103f1d	8707	if (ret == 0) {
cparata	3:4274d9103f1d	8708	ret = lsm6dso_write_reg(ctx, LSM6DSO_DATAWRITE_SLV0,
cparata	3:4274d9103f1d	8709	&(val->slv0_data), 1);
cparata	3:4274d9103f1d	8710	}
cparata	3:4274d9103f1d	8711	if (ret == 0) {
cparata	3:4274d9103f1d	8712	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8713	}
cparata	3:4274d9103f1d	8714	return ret;
cparata	0:6d69e896ce38	8715	}
cparata	0:6d69e896ce38	8716
cparata	0:6d69e896ce38	8717	/**
cparata	0:6d69e896ce38	8718	* @brief Configure slave 0 for perform a read.[set]
cparata	0:6d69e896ce38	8719	*
cparata	0:6d69e896ce38	8720	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8721	* @param val Structure that contain
cparata	0:6d69e896ce38	8722	* - uint8_t slv1_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8723	* - uint8_t slv1_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8724	* - uint8_t slv1_len; num of bit to read
cparata	0:6d69e896ce38	8725	*
cparata	0:6d69e896ce38	8726	*/
cparata	0:6d69e896ce38	8727	int32_t lsm6dso_sh_slv0_cfg_read(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8728	lsm6dso_sh_cfg_read_t *val)
cparata	0:6d69e896ce38	8729	{
cparata	3:4274d9103f1d	8730	lsm6dso_slv0_add_t slv0_add;
cparata	3:4274d9103f1d	8731	lsm6dso_slv0_config_t slv0_config;
cparata	3:4274d9103f1d	8732	int32_t ret;
cparata	3:4274d9103f1d	8733
cparata	3:4274d9103f1d	8734	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8735	if (ret == 0) {
cparata	3:4274d9103f1d	8736	slv0_add.slave0 = val->slv_add;
cparata	3:4274d9103f1d	8737	slv0_add.rw_0 = 1;
cparata	3:4274d9103f1d	8738	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t *)&slv0_add, 1);
cparata	3:4274d9103f1d	8739	}
cparata	3:4274d9103f1d	8740	if (ret == 0) {
cparata	3:4274d9103f1d	8741	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD,
cparata	3:4274d9103f1d	8742	&(val->slv_subadd), 1);
cparata	3:4274d9103f1d	8743	}
cparata	3:4274d9103f1d	8744	if (ret == 0) {
cparata	3:4274d9103f1d	8745	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG,
cparata	3:4274d9103f1d	8746	(uint8_t *)&slv0_config, 1);
cparata	3:4274d9103f1d	8747	}
cparata	3:4274d9103f1d	8748	if (ret == 0) {
cparata	3:4274d9103f1d	8749	slv0_config.slave0_numop = val->slv_len;
cparata	3:4274d9103f1d	8750	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG,
cparata	3:4274d9103f1d	8751	(uint8_t *)&slv0_config, 1);
cparata	3:4274d9103f1d	8752	}
cparata	3:4274d9103f1d	8753	if (ret == 0) {
cparata	3:4274d9103f1d	8754	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8755	}
cparata	3:4274d9103f1d	8756
cparata	3:4274d9103f1d	8757	return ret;
cparata	0:6d69e896ce38	8758	}
cparata	0:6d69e896ce38	8759
cparata	0:6d69e896ce38	8760	/**
cparata	0:6d69e896ce38	8761	* @brief Configure slave 0 for perform a write/read.[set]
cparata	0:6d69e896ce38	8762	*
cparata	0:6d69e896ce38	8763	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8764	* @param val Structure that contain
cparata	0:6d69e896ce38	8765	* - uint8_t slv1_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8766	* - uint8_t slv1_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8767	* - uint8_t slv1_len; num of bit to read
cparata	0:6d69e896ce38	8768	*
cparata	0:6d69e896ce38	8769	*/
cparata	0:6d69e896ce38	8770	int32_t lsm6dso_sh_slv1_cfg_read(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8771	lsm6dso_sh_cfg_read_t *val)
cparata	0:6d69e896ce38	8772	{
cparata	3:4274d9103f1d	8773	lsm6dso_slv1_add_t slv1_add;
cparata	3:4274d9103f1d	8774	lsm6dso_slv1_config_t slv1_config;
cparata	3:4274d9103f1d	8775	int32_t ret;
cparata	3:4274d9103f1d	8776
cparata	3:4274d9103f1d	8777	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8778	if (ret == 0) {
cparata	3:4274d9103f1d	8779	slv1_add.slave1_add = val->slv_add;
cparata	3:4274d9103f1d	8780	slv1_add.r_1 = 1;
cparata	3:4274d9103f1d	8781	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_ADD, (uint8_t *)&slv1_add, 1);
cparata	3:4274d9103f1d	8782	}
cparata	3:4274d9103f1d	8783	if (ret == 0) {
cparata	3:4274d9103f1d	8784	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_SUBADD,
cparata	3:4274d9103f1d	8785	&(val->slv_subadd), 1);
cparata	3:4274d9103f1d	8786	}
cparata	3:4274d9103f1d	8787	if (ret == 0) {
cparata	3:4274d9103f1d	8788	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG,
cparata	3:4274d9103f1d	8789	(uint8_t *)&slv1_config, 1);
cparata	3:4274d9103f1d	8790	}
cparata	3:4274d9103f1d	8791	if (ret == 0) {
cparata	3:4274d9103f1d	8792	slv1_config.slave1_numop = val->slv_len;
cparata	3:4274d9103f1d	8793	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG,
cparata	3:4274d9103f1d	8794	(uint8_t *)&slv1_config, 1);
cparata	3:4274d9103f1d	8795	}
cparata	3:4274d9103f1d	8796	if (ret == 0) {
cparata	3:4274d9103f1d	8797	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8798	}
cparata	3:4274d9103f1d	8799
cparata	3:4274d9103f1d	8800	return ret;
cparata	0:6d69e896ce38	8801	}
cparata	0:6d69e896ce38	8802
cparata	0:6d69e896ce38	8803	/**
cparata	0:6d69e896ce38	8804	* @brief Configure slave 0 for perform a write/read.[set]
cparata	0:6d69e896ce38	8805	*
cparata	0:6d69e896ce38	8806	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8807	* @param val Structure that contain
cparata	0:6d69e896ce38	8808	* - uint8_t slv2_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8809	* - uint8_t slv2_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8810	* - uint8_t slv2_len; num of bit to read
cparata	0:6d69e896ce38	8811	*
cparata	0:6d69e896ce38	8812	*/
cparata	0:6d69e896ce38	8813	int32_t lsm6dso_sh_slv2_cfg_read(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8814	lsm6dso_sh_cfg_read_t *val)
cparata	0:6d69e896ce38	8815	{
cparata	3:4274d9103f1d	8816	lsm6dso_slv2_add_t slv2_add;
cparata	3:4274d9103f1d	8817	lsm6dso_slv2_config_t slv2_config;
cparata	3:4274d9103f1d	8818	int32_t ret;
cparata	3:4274d9103f1d	8819
cparata	3:4274d9103f1d	8820	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8821	if (ret == 0) {
cparata	3:4274d9103f1d	8822	slv2_add.slave2_add = val->slv_add;
cparata	3:4274d9103f1d	8823	slv2_add.r_2 = 1;
cparata	3:4274d9103f1d	8824	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_ADD, (uint8_t *)&slv2_add, 1);
cparata	3:4274d9103f1d	8825	}
cparata	3:4274d9103f1d	8826	if (ret == 0) {
cparata	3:4274d9103f1d	8827	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_SUBADD,
cparata	3:4274d9103f1d	8828	&(val->slv_subadd), 1);
cparata	3:4274d9103f1d	8829	}
cparata	3:4274d9103f1d	8830	if (ret == 0) {
cparata	3:4274d9103f1d	8831	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG,
cparata	3:4274d9103f1d	8832	(uint8_t *)&slv2_config, 1);
cparata	3:4274d9103f1d	8833	}
cparata	3:4274d9103f1d	8834	if (ret == 0) {
cparata	3:4274d9103f1d	8835	slv2_config.slave2_numop = val->slv_len;
cparata	3:4274d9103f1d	8836	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG,
cparata	3:4274d9103f1d	8837	(uint8_t *)&slv2_config, 1);
cparata	3:4274d9103f1d	8838	}
cparata	3:4274d9103f1d	8839	if (ret == 0) {
cparata	3:4274d9103f1d	8840	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8841	}
cparata	3:4274d9103f1d	8842	return ret;
cparata	0:6d69e896ce38	8843	}
cparata	0:6d69e896ce38	8844
cparata	0:6d69e896ce38	8845	/**
cparata	0:6d69e896ce38	8846	* @brief Configure slave 0 for perform a write/read.[set]
cparata	0:6d69e896ce38	8847	*
cparata	0:6d69e896ce38	8848	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8849	* @param val Structure that contain
cparata	0:6d69e896ce38	8850	* - uint8_t slv3_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8851	* - uint8_t slv3_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8852	* - uint8_t slv3_len; num of bit to read
cparata	0:6d69e896ce38	8853	*
cparata	0:6d69e896ce38	8854	*/
cparata	0:6d69e896ce38	8855	int32_t lsm6dso_sh_slv3_cfg_read(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8856	lsm6dso_sh_cfg_read_t *val)
cparata	0:6d69e896ce38	8857	{
cparata	3:4274d9103f1d	8858	lsm6dso_slv3_add_t slv3_add;
cparata	3:4274d9103f1d	8859	lsm6dso_slv3_config_t slv3_config;
cparata	3:4274d9103f1d	8860	int32_t ret;
cparata	3:4274d9103f1d	8861
cparata	3:4274d9103f1d	8862	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8863	if (ret == 0) {
cparata	3:4274d9103f1d	8864	slv3_add.slave3_add = val->slv_add;
cparata	3:4274d9103f1d	8865	slv3_add.r_3 = 1;
cparata	3:4274d9103f1d	8866	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_ADD, (uint8_t *)&slv3_add, 1);
cparata	3:4274d9103f1d	8867	}
cparata	3:4274d9103f1d	8868	if (ret == 0) {
cparata	3:4274d9103f1d	8869	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_SUBADD,
cparata	3:4274d9103f1d	8870	&(val->slv_subadd), 1);
cparata	3:4274d9103f1d	8871	}
cparata	3:4274d9103f1d	8872	if (ret == 0) {
cparata	3:4274d9103f1d	8873	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG,
cparata	3:4274d9103f1d	8874	(uint8_t *)&slv3_config, 1);
cparata	3:4274d9103f1d	8875	}
cparata	3:4274d9103f1d	8876	if (ret == 0) {
cparata	3:4274d9103f1d	8877	slv3_config.slave3_numop = val->slv_len;
cparata	3:4274d9103f1d	8878	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG,
cparata	3:4274d9103f1d	8879	(uint8_t *)&slv3_config, 1);
cparata	3:4274d9103f1d	8880	}
cparata	3:4274d9103f1d	8881	if (ret == 0) {
cparata	3:4274d9103f1d	8882	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8883	}
cparata	3:4274d9103f1d	8884	return ret;
cparata	0:6d69e896ce38	8885	}
cparata	0:6d69e896ce38	8886
cparata	0:6d69e896ce38	8887	/**
cparata	0:6d69e896ce38	8888	* @brief Sensor hub source register.[get]
cparata	0:6d69e896ce38	8889	*
cparata	0:6d69e896ce38	8890	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8891	* @param val union of registers from STATUS_MASTER to
cparata	0:6d69e896ce38	8892	*
cparata	0:6d69e896ce38	8893	*/
cparata	0:6d69e896ce38	8894	int32_t lsm6dso_sh_status_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8895	lsm6dso_status_master_t *val)
cparata	0:6d69e896ce38	8896	{
cparata	3:4274d9103f1d	8897	int32_t ret;
cparata	3:4274d9103f1d	8898
cparata	3:4274d9103f1d	8899	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	3:4274d9103f1d	8900	if (ret == 0) {
cparata	3:4274d9103f1d	8901	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER, (uint8_t *) val, 1);
cparata	3:4274d9103f1d	8902	}
cparata	3:4274d9103f1d	8903	if (ret == 0) {
cparata	3:4274d9103f1d	8904	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	3:4274d9103f1d	8905	}
cparata	3:4274d9103f1d	8906
cparata	3:4274d9103f1d	8907	return ret;
cparata	0:6d69e896ce38	8908	}
cparata	0:6d69e896ce38	8909
cparata	0:6d69e896ce38	8910	/**
cparata	0:6d69e896ce38	8911	* @}
cparata	0:6d69e896ce38	8912	*
cparata	0:6d69e896ce38	8913	*/
cparata	0:6d69e896ce38	8914
cparata	0:6d69e896ce38	8915	/**
cparata	0:6d69e896ce38	8916	* @}
cparata	0:6d69e896ce38	8917	*
cparata	0:6d69e896ce38	8918	*/
cparata	0:6d69e896ce38	8919
cparata	0:6d69e896ce38	8920	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	07 Mar 2019
Imports:	15
Forks:	0
Commits:	7
Dependents:	2
Dependencies:	2
Followers:	401

The code in this repository is Apache licensed.

lsm6dso_reg.c@3:4274d9103f1d, 2019-07-24 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning