stm32746g_discovery_sdram.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32746g_discovery_sdram.h
00004   * @author  MCD Application Team
00005   * @brief   This file contains the common defines and functions prototypes for
00006   *          the stm32746g_discovery_sdram.c driver.
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00011   *
00012   * Redistribution and use in source and binary forms, with or without modification,
00013   * are permitted provided that the following conditions are met:
00014   *   1. Redistributions of source code must retain the above copyright notice,
00015   *      this list of conditions and the following disclaimer.
00016   *   2. Redistributions in binary form must reproduce the above copyright notice,
00017   *      this list of conditions and the following disclaimer in the documentation
00018   *      and/or other materials provided with the distribution.
00019   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00020   *      may be used to endorse or promote products derived from this software
00021   *      without specific prior written permission.
00022   *
00023   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00024   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00025   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00026   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00027   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00028   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00029   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00030   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00031   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00032   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00033   *
00034   ******************************************************************************
00035   */ 
00036 
00037 /* Define to prevent recursive inclusion -------------------------------------*/
00038 #ifndef __STM32746G_DISCOVERY_SDRAM_H
00039 #define __STM32746G_DISCOVERY_SDRAM_H
00040 
00041 #ifdef __cplusplus
00042  extern "C" {
00043 #endif 
00044 
00045 /* Includes ------------------------------------------------------------------*/
00046 #include "stm32f7xx_hal.h"
00047 
00048 /** @addtogroup BSP
00049   * @{
00050   */ 
00051 
00052 /** @addtogroup STM32746G_DISCOVERY
00053   * @{
00054   */
00055     
00056 /** @addtogroup STM32746G_DISCOVERY_SDRAM
00057   * @{
00058   */    
00059 
00060 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types
00061   * @{
00062   */
00063 
00064 /** 
00065   * @brief  SDRAM status structure definition  
00066   */     
00067 #define   SDRAM_OK         ((uint8_t)0x00)
00068 #define   SDRAM_ERROR      ((uint8_t)0x01)
00069 
00070 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants
00071   * @{
00072   */ 
00073 #define SDRAM_DEVICE_ADDR  ((uint32_t)0xC0000000)
00074 #define SDRAM_DEVICE_SIZE  ((uint32_t)0x800000)  /* SDRAM device size in MBytes */
00075 
00076 /* #define SDRAM_MEMORY_WIDTH            FMC_SDRAM_MEM_BUS_WIDTH_8  */
00077 #define SDRAM_MEMORY_WIDTH               FMC_SDRAM_MEM_BUS_WIDTH_16
00078 
00079 #define SDCLOCK_PERIOD                   FMC_SDRAM_CLOCK_PERIOD_2
00080 /* #define SDCLOCK_PERIOD                FMC_SDRAM_CLOCK_PERIOD_3 */   
00081 
00082 #define REFRESH_COUNT                    ((uint32_t)0x0603)   /* SDRAM refresh counter (100Mhz SD clock) */
00083    
00084 #define SDRAM_TIMEOUT                    ((uint32_t)0xFFFF)
00085 
00086 /* DMA definitions for SDRAM DMA transfer */
00087 #define __DMAx_CLK_ENABLE                 __HAL_RCC_DMA2_CLK_ENABLE
00088 #define __DMAx_CLK_DISABLE                __HAL_RCC_DMA2_CLK_DISABLE
00089 #define SDRAM_DMAx_CHANNEL                DMA_CHANNEL_0
00090 #define SDRAM_DMAx_STREAM                 DMA2_Stream0  
00091 #define SDRAM_DMAx_IRQn                   DMA2_Stream0_IRQn
00092 #define BSP_SDRAM_DMA_IRQHandler          DMA2_Stream0_IRQHandler  
00093 /**
00094   * @}
00095   */ 
00096   
00097 /**
00098   * @brief  FMC SDRAM Mode definition register defines
00099   */
00100 #define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
00101 #define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
00102 #define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
00103 #define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
00104 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
00105 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
00106 #define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
00107 #define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
00108 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
00109 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) 
00110 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200) 
00111 /**
00112   * @}
00113   */ 
00114   
00115 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro
00116   * @{
00117   */  
00118 /**
00119   * @}
00120   */ 
00121    
00122 /** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions
00123   * @{
00124   */  
00125 uint8_t BSP_SDRAM_Init(void);
00126 uint8_t BSP_SDRAM_DeInit(void);
00127 void    BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
00128 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
00129 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
00130 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
00131 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
00132 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
00133    
00134 /* These functions can be modified in case the current settings (e.g. DMA stream)
00135    need to be changed for specific application needs */
00136 void    BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
00137 void    BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
00138 
00139 
00140 /**
00141   * @}
00142   */ 
00143 
00144 /**
00145   * @}
00146   */ 
00147 
00148 /**
00149   * @}
00150   */ 
00151 
00152 /**
00153   * @}
00154   */ 
00155 
00156 #ifdef __cplusplus
00157 }
00158 #endif
00159 
00160 #endif /* __STM32746G_DISCOVERY_SDRAM_H */
00161 
00162 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/