stm32746g_discovery_sdram.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32746g_discovery_sdram.c
00004   * @author  MCD Application Team
00005   * @brief   This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory 
00006   *          device mounted on STM32746G-Discovery board.
00007   @verbatim
00008    1. How To use this driver:
00009    --------------------------
00010       - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
00011         on STM32746G-Discovery board.
00012       - This driver does not need a specific component driver for the SDRAM device
00013         to be included with.
00014    
00015    2. Driver description:
00016    ---------------------
00017      + Initialization steps:
00018         o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This 
00019           function includes the MSP layer hardware resources initialization and the
00020           FMC controller configuration to interface with the external SDRAM memory.
00021         o It contains the SDRAM initialization sequence to program the SDRAM external 
00022           device using the function BSP_SDRAM_Initialization_sequence(). Note that this 
00023           sequence is standard for all SDRAM devices, but can include some differences
00024           from a device to another. If it is the case, the right sequence should be 
00025           implemented separately.
00026      
00027      + SDRAM read/write operations
00028         o SDRAM external memory can be accessed with read/write operations once it is
00029           initialized.
00030           Read/write operation can be performed with AHB access using the functions
00031           BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
00032           BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
00033         o The AHB access is performed with 32-bit width transaction, the DMA transfer
00034           configuration is fixed at single (no burst) word transfer (see the 
00035           SDRAM_MspInit() static function).
00036         o User can implement his own functions for read/write access with his desired 
00037           configurations.
00038         o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
00039           is called in IRQ handler file, to serve the generated interrupt once the DMA 
00040           transfer is complete.
00041         o You can send a command to the SDRAM device in runtime using the function 
00042           BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between 
00043           the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure. 
00044  
00045   @endverbatim
00046   ******************************************************************************
00047   * @attention
00048   *
00049   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00050   *
00051   * Redistribution and use in source and binary forms, with or without modification,
00052   * are permitted provided that the following conditions are met:
00053   *   1. Redistributions of source code must retain the above copyright notice,
00054   *      this list of conditions and the following disclaimer.
00055   *   2. Redistributions in binary form must reproduce the above copyright notice,
00056   *      this list of conditions and the following disclaimer in the documentation
00057   *      and/or other materials provided with the distribution.
00058   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00059   *      may be used to endorse or promote products derived from this software
00060   *      without specific prior written permission.
00061   *
00062   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00063   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00064   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00065   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00066   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00067   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00068   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00069   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00070   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00071   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00072   *
00073   ******************************************************************************
00074   */
00075 
00076 /* Dependencies
00077 - stm32f7xx_hal_sdram.c
00078 - stm32f7xx_ll_fmc.c
00079 - stm32f7xx_hal_dma.c  
00080 - stm32f7xx_hal_gpio.c
00081 - stm32f7xx_hal_cortex.c
00082 - stm32f7xx_hal_rcc_ex.h
00083 EndDependencies */
00084 
00085 /* Includes ------------------------------------------------------------------*/
00086 #include "stm32746g_discovery_sdram.h"
00087 
00088 /** @addtogroup BSP
00089   * @{
00090   */
00091 
00092 /** @addtogroup STM32746G_DISCOVERY
00093   * @{
00094   */ 
00095   
00096 /** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM
00097   * @{
00098   */ 
00099 
00100 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions
00101   * @{
00102   */ 
00103 /**
00104   * @}
00105   */
00106 
00107 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines
00108   * @{
00109   */
00110 /**
00111   * @}
00112   */
00113 
00114 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros
00115   * @{
00116   */  
00117 /**
00118   * @}
00119   */
00120 
00121 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables
00122   * @{
00123   */       
00124 SDRAM_HandleTypeDef sdramHandle;
00125 static FMC_SDRAM_TimingTypeDef Timing;
00126 static FMC_SDRAM_CommandTypeDef Command;
00127 /**
00128   * @}
00129   */ 
00130 
00131 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes
00132   * @{
00133   */ 
00134 /**
00135   * @}
00136   */
00137     
00138 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions
00139   * @{
00140   */ 
00141 
00142 /**
00143   * @brief  Initializes the SDRAM device.
00144   * @retval SDRAM status
00145   */
00146 uint8_t BSP_SDRAM_Init(void)
00147 { 
00148   static uint8_t sdramstatus = SDRAM_ERROR;
00149   /* SDRAM device configuration */
00150   sdramHandle.Instance = FMC_SDRAM_DEVICE;
00151     
00152   /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
00153   Timing.LoadToActiveDelay    = 2;
00154   Timing.ExitSelfRefreshDelay = 7;
00155   Timing.SelfRefreshTime      = 4;
00156   Timing.RowCycleDelay        = 7;
00157   Timing.WriteRecoveryTime    = 2;
00158   Timing.RPDelay              = 2;
00159   Timing.RCDDelay             = 2;
00160   
00161   sdramHandle.Init.SDBank             = FMC_SDRAM_BANK1;
00162   sdramHandle.Init.ColumnBitsNumber   = FMC_SDRAM_COLUMN_BITS_NUM_8;
00163   sdramHandle.Init.RowBitsNumber      = FMC_SDRAM_ROW_BITS_NUM_12;
00164   sdramHandle.Init.MemoryDataWidth    = SDRAM_MEMORY_WIDTH;
00165   sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
00166   sdramHandle.Init.CASLatency         = FMC_SDRAM_CAS_LATENCY_2;
00167   sdramHandle.Init.WriteProtection    = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
00168   sdramHandle.Init.SDClockPeriod      = SDCLOCK_PERIOD;
00169   sdramHandle.Init.ReadBurst          = FMC_SDRAM_RBURST_ENABLE;
00170   sdramHandle.Init.ReadPipeDelay      = FMC_SDRAM_RPIPE_DELAY_0;
00171   
00172   /* SDRAM controller initialization */
00173 
00174   BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
00175 
00176   if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
00177   {
00178     sdramstatus = SDRAM_ERROR;
00179   }
00180   else
00181   {
00182     sdramstatus = SDRAM_OK;
00183   }
00184   
00185   /* SDRAM initialization sequence */
00186   BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
00187   
00188   return sdramstatus;
00189 }
00190 
00191 /**
00192   * @brief  DeInitializes the SDRAM device.
00193   * @retval SDRAM status
00194   */
00195 uint8_t BSP_SDRAM_DeInit(void)
00196 { 
00197   static uint8_t sdramstatus = SDRAM_ERROR;
00198   /* SDRAM device de-initialization */
00199   sdramHandle.Instance = FMC_SDRAM_DEVICE;
00200 
00201   if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK)
00202   {
00203     sdramstatus = SDRAM_ERROR;
00204   }
00205   else
00206   {
00207     sdramstatus = SDRAM_OK;
00208   }
00209   
00210   /* SDRAM controller de-initialization */
00211   BSP_SDRAM_MspDeInit(&sdramHandle, NULL);
00212   
00213   return sdramstatus;
00214 }
00215 
00216 /**
00217   * @brief  Programs the SDRAM device.
00218   * @param  RefreshCount: SDRAM refresh counter value 
00219   * @retval None
00220   */
00221 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
00222 {
00223   __IO uint32_t tmpmrd = 0;
00224   
00225   /* Step 1: Configure a clock configuration enable command */
00226   Command.CommandMode            = FMC_SDRAM_CMD_CLK_ENABLE;
00227   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
00228   Command.AutoRefreshNumber      = 1;
00229   Command.ModeRegisterDefinition = 0;
00230 
00231   /* Send the command */
00232   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00233 
00234   /* Step 2: Insert 100 us minimum delay */ 
00235   /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
00236   HAL_Delay(1);
00237     
00238   /* Step 3: Configure a PALL (precharge all) command */ 
00239   Command.CommandMode            = FMC_SDRAM_CMD_PALL;
00240   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
00241   Command.AutoRefreshNumber      = 1;
00242   Command.ModeRegisterDefinition = 0;
00243 
00244   /* Send the command */
00245   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);  
00246   
00247   /* Step 4: Configure an Auto Refresh command */ 
00248   Command.CommandMode            = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
00249   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
00250   Command.AutoRefreshNumber      = 8;
00251   Command.ModeRegisterDefinition = 0;
00252 
00253   /* Send the command */
00254   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00255   
00256   /* Step 5: Program the external memory mode register */
00257   tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1          |\
00258                      SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |\
00259                      SDRAM_MODEREG_CAS_LATENCY_2           |\
00260                      SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
00261                      SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
00262   
00263   Command.CommandMode            = FMC_SDRAM_CMD_LOAD_MODE;
00264   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
00265   Command.AutoRefreshNumber      = 1;
00266   Command.ModeRegisterDefinition = tmpmrd;
00267 
00268   /* Send the command */
00269   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00270   
00271   /* Step 6: Set the refresh rate counter */
00272   /* Set the device refresh rate */
00273   HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); 
00274 }
00275 
00276 /**
00277   * @brief  Reads an amount of data from the SDRAM memory in polling mode.
00278   * @param  uwStartAddress: Read start address
00279   * @param  pData: Pointer to data to be read  
00280   * @param  uwDataSize: Size of read data from the memory
00281   * @retval SDRAM status
00282   */
00283 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
00284 {
00285   if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00286   {
00287     return SDRAM_ERROR;
00288   }
00289   else
00290   {
00291     return SDRAM_OK;
00292   } 
00293 }
00294 
00295 /**
00296   * @brief  Reads an amount of data from the SDRAM memory in DMA mode.
00297   * @param  uwStartAddress: Read start address
00298   * @param  pData: Pointer to data to be read  
00299   * @param  uwDataSize: Size of read data from the memory
00300   * @retval SDRAM status
00301   */
00302 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
00303 {
00304   if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00305   {
00306     return SDRAM_ERROR;
00307   }
00308   else
00309   {
00310     return SDRAM_OK;
00311   }     
00312 }
00313 
00314 /**
00315   * @brief  Writes an amount of data to the SDRAM memory in polling mode.
00316   * @param  uwStartAddress: Write start address
00317   * @param  pData: Pointer to data to be written  
00318   * @param  uwDataSize: Size of written data from the memory
00319   * @retval SDRAM status
00320   */
00321 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 
00322 {
00323   if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00324   {
00325     return SDRAM_ERROR;
00326   }
00327   else
00328   {
00329     return SDRAM_OK;
00330   }
00331 }
00332 
00333 /**
00334   * @brief  Writes an amount of data to the SDRAM memory in DMA mode.
00335   * @param  uwStartAddress: Write start address
00336   * @param  pData: Pointer to data to be written  
00337   * @param  uwDataSize: Size of written data from the memory
00338   * @retval SDRAM status
00339   */
00340 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 
00341 {
00342   if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00343   {
00344     return SDRAM_ERROR;
00345   }
00346   else
00347   {
00348     return SDRAM_OK;
00349   } 
00350 }
00351 
00352 /**
00353   * @brief  Sends command to the SDRAM bank.
00354   * @param  SdramCmd: Pointer to SDRAM command structure 
00355   * @retval SDRAM status
00356   */  
00357 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
00358 {
00359   if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
00360   {
00361     return SDRAM_ERROR;
00362   }
00363   else
00364   {
00365     return SDRAM_OK;
00366   }
00367 }
00368 
00369 /**
00370   * @brief  Initializes SDRAM MSP.
00371   * @param  hsdram: SDRAM handle
00372   * @param  Params
00373   * @retval None
00374   */
00375 __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
00376 {  
00377   static DMA_HandleTypeDef dma_handle;
00378   GPIO_InitTypeDef gpio_init_structure;
00379   
00380   /* Enable FMC clock */
00381   __HAL_RCC_FMC_CLK_ENABLE();
00382   
00383   /* Enable chosen DMAx clock */
00384   __DMAx_CLK_ENABLE();
00385 
00386   /* Enable GPIOs clock */
00387   __HAL_RCC_GPIOC_CLK_ENABLE();
00388   __HAL_RCC_GPIOD_CLK_ENABLE();
00389   __HAL_RCC_GPIOE_CLK_ENABLE();
00390   __HAL_RCC_GPIOF_CLK_ENABLE();
00391   __HAL_RCC_GPIOG_CLK_ENABLE();
00392   __HAL_RCC_GPIOH_CLK_ENABLE();
00393   
00394   /* Common GPIO configuration */
00395   gpio_init_structure.Mode      = GPIO_MODE_AF_PP;
00396   gpio_init_structure.Pull      = GPIO_PULLUP;
00397   gpio_init_structure.Speed     = GPIO_SPEED_FAST;
00398   gpio_init_structure.Alternate = GPIO_AF12_FMC;
00399   
00400   /* GPIOC configuration */
00401   gpio_init_structure.Pin   = GPIO_PIN_3;
00402   HAL_GPIO_Init(GPIOC, &gpio_init_structure);
00403 
00404   /* GPIOD configuration */
00405   gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
00406                               GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
00407   HAL_GPIO_Init(GPIOD, &gpio_init_structure);
00408 
00409   /* GPIOE configuration */  
00410   gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
00411                               GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
00412                               GPIO_PIN_15;
00413   HAL_GPIO_Init(GPIOE, &gpio_init_structure);
00414   
00415   /* GPIOF configuration */  
00416   gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
00417                               GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
00418                               GPIO_PIN_15;
00419   HAL_GPIO_Init(GPIOF, &gpio_init_structure);
00420   
00421   /* GPIOG configuration */  
00422   gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
00423                               GPIO_PIN_15;
00424   HAL_GPIO_Init(GPIOG, &gpio_init_structure);
00425 
00426   /* GPIOH configuration */  
00427   gpio_init_structure.Pin   = GPIO_PIN_3 | GPIO_PIN_5;
00428   HAL_GPIO_Init(GPIOH, &gpio_init_structure); 
00429   
00430   /* Configure common DMA parameters */
00431   dma_handle.Init.Channel             = SDRAM_DMAx_CHANNEL;
00432   dma_handle.Init.Direction           = DMA_MEMORY_TO_MEMORY;
00433   dma_handle.Init.PeriphInc           = DMA_PINC_ENABLE;
00434   dma_handle.Init.MemInc              = DMA_MINC_ENABLE;
00435   dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
00436   dma_handle.Init.MemDataAlignment    = DMA_MDATAALIGN_WORD;
00437   dma_handle.Init.Mode                = DMA_NORMAL;
00438   dma_handle.Init.Priority            = DMA_PRIORITY_HIGH;
00439   dma_handle.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;         
00440   dma_handle.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
00441   dma_handle.Init.MemBurst            = DMA_MBURST_SINGLE;
00442   dma_handle.Init.PeriphBurst         = DMA_PBURST_SINGLE; 
00443   
00444   dma_handle.Instance = SDRAM_DMAx_STREAM;
00445   
00446    /* Associate the DMA handle */
00447   __HAL_LINKDMA(hsdram, hdma, dma_handle);
00448   
00449   /* Deinitialize the stream for new transfer */
00450   HAL_DMA_DeInit(&dma_handle);
00451   
00452   /* Configure the DMA stream */
00453   HAL_DMA_Init(&dma_handle); 
00454   
00455   /* NVIC configuration for DMA transfer complete interrupt */
00456   HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0x0F, 0);
00457   HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
00458 }
00459 
00460 /**
00461   * @brief  DeInitializes SDRAM MSP.
00462   * @param  hsdram: SDRAM handle
00463   * @param  Params
00464   * @retval None
00465   */
00466 __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
00467 {  
00468     static DMA_HandleTypeDef dma_handle;
00469   
00470     /* Disable NVIC configuration for DMA interrupt */
00471     HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
00472 
00473     /* Deinitialize the stream for new transfer */
00474     dma_handle.Instance = SDRAM_DMAx_STREAM;
00475     HAL_DMA_DeInit(&dma_handle);
00476 
00477     /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications
00478        by surcharging this __weak function */ 
00479 }
00480 
00481 /**
00482   * @}
00483   */  
00484   
00485 /**
00486   * @}
00487   */ 
00488   
00489 /**
00490   * @}
00491   */ 
00492   
00493 /**
00494   * @}
00495   */ 
00496 
00497 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/