ST Expansion SW Team / VL53L1

Fork, renaming of VL53L1CB-2

Dependencies:   X_NUCLEO_COMMON ST_INTERFACES

Dependents:   X_NUCLEO_53L1CB

inc/vl53l1_register_structs.h@13:3f1b341901dd, 2021-06-11 (annotated)

Committer:
Charles MacNeill
Date:
Fri Jun 11 17:08:27 2021 +0100
Revision:
13:3f1b341901dd
Parent:
7:1add29d51e72 
changing case of vl53l1cb.* so it works in linux

Who changed what in which revision?

UserRevisionLine numberNew contents of line
charlesmn 0:3ac96e360672 1
Charles MacNeill 7:1add29d51e72 2 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
Charles MacNeill 7:1add29d51e72 3 /******************************************************************************
charlesmn 0:3ac96e360672 4 * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
charlesmn 0:3ac96e360672 5
Charles MacNeill 7:1add29d51e72 6 This file is part of VL53L1 and is dual licensed,
Charles MacNeill 7:1add29d51e72 7 either GPL-2.0+
charlesmn 0:3ac96e360672 8 or 'BSD 3-clause "New" or "Revised" License' , at your option.
Charles MacNeill 7:1add29d51e72 9 ******************************************************************************
Charles MacNeill 7:1add29d51e72 10 */
charlesmn 0:3ac96e360672 11
charlesmn 0:3ac96e360672 12
charlesmn 0:3ac96e360672 13
charlesmn 0:3ac96e360672 14
charlesmn 0:3ac96e360672 15 #ifndef _VL53L1_REGISTER_STRUCTS_H_
charlesmn 0:3ac96e360672 16 #define _VL53L1_REGISTER_STRUCTS_H_
charlesmn 0:3ac96e360672 17
charlesmn 0:3ac96e360672 18 #include "vl53l1_types.h"
charlesmn 0:3ac96e360672 19 #include "vl53l1_register_map.h"
charlesmn 0:3ac96e360672 20
charlesmn 0:3ac96e360672 21 #define VL53L1_STATIC_NVM_MANAGED_I2C_INDEX \
charlesmn 0:3ac96e360672 22 VL53L1_I2C_SLAVE__DEVICE_ADDRESS
charlesmn 0:3ac96e360672 23 #define VL53L1_CUSTOMER_NVM_MANAGED_I2C_INDEX \
charlesmn 0:3ac96e360672 24 VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_0
charlesmn 0:3ac96e360672 25 #define VL53L1_STATIC_CONFIG_I2C_INDEX \
charlesmn 0:3ac96e360672 26 VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS
charlesmn 0:3ac96e360672 27 #define VL53L1_GENERAL_CONFIG_I2C_INDEX \
charlesmn 0:3ac96e360672 28 VL53L1_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE
charlesmn 0:3ac96e360672 29 #define VL53L1_TIMING_CONFIG_I2C_INDEX \
charlesmn 0:3ac96e360672 30 VL53L1_MM_CONFIG__TIMEOUT_MACROP_A_HI
charlesmn 0:3ac96e360672 31 #define VL53L1_DYNAMIC_CONFIG_I2C_INDEX \
charlesmn 0:3ac96e360672 32 VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD_0
charlesmn 0:3ac96e360672 33 #define VL53L1_SYSTEM_CONTROL_I2C_INDEX \
charlesmn 0:3ac96e360672 34 VL53L1_POWER_MANAGEMENT__GO1_POWER_FORCE
charlesmn 0:3ac96e360672 35 #define VL53L1_SYSTEM_RESULTS_I2C_INDEX \
charlesmn 0:3ac96e360672 36 VL53L1_RESULT__INTERRUPT_STATUS
charlesmn 0:3ac96e360672 37 #define VL53L1_CORE_RESULTS_I2C_INDEX \
charlesmn 0:3ac96e360672 38 VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
charlesmn 0:3ac96e360672 39 #define VL53L1_DEBUG_RESULTS_I2C_INDEX \
charlesmn 0:3ac96e360672 40 VL53L1_PHASECAL_RESULT__REFERENCE_PHASE
charlesmn 0:3ac96e360672 41 #define VL53L1_NVM_COPY_DATA_I2C_INDEX \
charlesmn 0:3ac96e360672 42 VL53L1_IDENTIFICATION__MODEL_ID
charlesmn 0:3ac96e360672 43 #define VL53L1_PREV_SHADOW_SYSTEM_RESULTS_I2C_INDEX \
charlesmn 0:3ac96e360672 44 VL53L1_PREV_SHADOW_RESULT__INTERRUPT_STATUS
charlesmn 0:3ac96e360672 45 #define VL53L1_PREV_SHADOW_CORE_RESULTS_I2C_INDEX \
charlesmn 0:3ac96e360672 46 VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
charlesmn 0:3ac96e360672 47 #define VL53L1_PATCH_DEBUG_I2C_INDEX \
charlesmn 0:3ac96e360672 48 VL53L1_RESULT__DEBUG_STATUS
charlesmn 0:3ac96e360672 49 #define VL53L1_GPH_GENERAL_CONFIG_I2C_INDEX \
charlesmn 0:3ac96e360672 50 VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH
charlesmn 0:3ac96e360672 51 #define VL53L1_GPH_STATIC_CONFIG_I2C_INDEX \
charlesmn 0:3ac96e360672 52 VL53L1_GPH__DSS_CONFIG__ROI_MODE_CONTROL
charlesmn 0:3ac96e360672 53 #define VL53L1_GPH_TIMING_CONFIG_I2C_INDEX \
charlesmn 0:3ac96e360672 54 VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI
charlesmn 0:3ac96e360672 55 #define VL53L1_FW_INTERNAL_I2C_INDEX \
charlesmn 0:3ac96e360672 56 VL53L1_FIRMWARE__INTERNAL_STREAM_COUNT_DIV
charlesmn 0:3ac96e360672 57 #define VL53L1_PATCH_RESULTS_I2C_INDEX \
charlesmn 0:3ac96e360672 58 VL53L1_DSS_CALC__ROI_CTRL
charlesmn 0:3ac96e360672 59 #define VL53L1_SHADOW_SYSTEM_RESULTS_I2C_INDEX \
charlesmn 0:3ac96e360672 60 VL53L1_SHADOW_PHASECAL_RESULT__VCSEL_START
charlesmn 0:3ac96e360672 61 #define VL53L1_SHADOW_CORE_RESULTS_I2C_INDEX \
charlesmn 0:3ac96e360672 62 VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
charlesmn 0:3ac96e360672 63
charlesmn 0:3ac96e360672 64 #define VL53L1_STATIC_NVM_MANAGED_I2C_SIZE_BYTES 11
charlesmn 0:3ac96e360672 65 #define VL53L1_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES 23
charlesmn 0:3ac96e360672 66 #define VL53L1_STATIC_CONFIG_I2C_SIZE_BYTES 32
charlesmn 0:3ac96e360672 67 #define VL53L1_GENERAL_CONFIG_I2C_SIZE_BYTES 22
charlesmn 0:3ac96e360672 68 #define VL53L1_TIMING_CONFIG_I2C_SIZE_BYTES 23
charlesmn 0:3ac96e360672 69 #define VL53L1_DYNAMIC_CONFIG_I2C_SIZE_BYTES 18
charlesmn 0:3ac96e360672 70 #define VL53L1_SYSTEM_CONTROL_I2C_SIZE_BYTES 5
charlesmn 0:3ac96e360672 71 #define VL53L1_SYSTEM_RESULTS_I2C_SIZE_BYTES 44
charlesmn 0:3ac96e360672 72 #define VL53L1_CORE_RESULTS_I2C_SIZE_BYTES 33
charlesmn 0:3ac96e360672 73 #define VL53L1_DEBUG_RESULTS_I2C_SIZE_BYTES 56
charlesmn 0:3ac96e360672 74 #define VL53L1_NVM_COPY_DATA_I2C_SIZE_BYTES 49
charlesmn 0:3ac96e360672 75 #define VL53L1_PREV_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 44
charlesmn 0:3ac96e360672 76 #define VL53L1_PREV_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33
charlesmn 0:3ac96e360672 77 #define VL53L1_PATCH_DEBUG_I2C_SIZE_BYTES 2
charlesmn 0:3ac96e360672 78 #define VL53L1_GPH_GENERAL_CONFIG_I2C_SIZE_BYTES 5
charlesmn 0:3ac96e360672 79 #define VL53L1_GPH_STATIC_CONFIG_I2C_SIZE_BYTES 6
charlesmn 0:3ac96e360672 80 #define VL53L1_GPH_TIMING_CONFIG_I2C_SIZE_BYTES 16
charlesmn 0:3ac96e360672 81 #define VL53L1_FW_INTERNAL_I2C_SIZE_BYTES 2
charlesmn 0:3ac96e360672 82 #define VL53L1_PATCH_RESULTS_I2C_SIZE_BYTES 90
charlesmn 0:3ac96e360672 83 #define VL53L1_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 82
charlesmn 0:3ac96e360672 84 #define VL53L1_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33
charlesmn 0:3ac96e360672 85
charlesmn 0:3ac96e360672 86
charlesmn 0:3ac96e360672 87
charlesmn 0:3ac96e360672 88
charlesmn 0:3ac96e360672 89 typedef struct {
charlesmn 0:3ac96e360672 90 uint8_t i2c_slave__device_address;
charlesmn 0:3ac96e360672 91
charlesmn 0:3ac96e360672 92 uint8_t ana_config__vhv_ref_sel_vddpix;
charlesmn 0:3ac96e360672 93
charlesmn 0:3ac96e360672 94 uint8_t ana_config__vhv_ref_sel_vquench;
charlesmn 0:3ac96e360672 95
charlesmn 0:3ac96e360672 96 uint8_t ana_config__reg_avdd1v2_sel;
charlesmn 0:3ac96e360672 97
charlesmn 0:3ac96e360672 98 uint8_t ana_config__fast_osc__trim;
charlesmn 0:3ac96e360672 99
charlesmn 0:3ac96e360672 100 uint16_t osc_measured__fast_osc__frequency;
charlesmn 0:3ac96e360672 101
charlesmn 0:3ac96e360672 102 uint8_t vhv_config__timeout_macrop_loop_bound;
charlesmn 0:3ac96e360672 103
charlesmn 0:3ac96e360672 104 uint8_t vhv_config__count_thresh;
charlesmn 0:3ac96e360672 105
charlesmn 0:3ac96e360672 106 uint8_t vhv_config__offset;
charlesmn 0:3ac96e360672 107
charlesmn 0:3ac96e360672 108 uint8_t vhv_config__init;
charlesmn 0:3ac96e360672 109
charlesmn 0:3ac96e360672 110 } VL53L1_static_nvm_managed_t;
charlesmn 0:3ac96e360672 111
charlesmn 0:3ac96e360672 112
charlesmn 0:3ac96e360672 113
charlesmn 0:3ac96e360672 114
charlesmn 0:3ac96e360672 115 typedef struct {
charlesmn 0:3ac96e360672 116 uint8_t global_config__spad_enables_ref_0;
charlesmn 0:3ac96e360672 117
charlesmn 0:3ac96e360672 118 uint8_t global_config__spad_enables_ref_1;
charlesmn 0:3ac96e360672 119
charlesmn 0:3ac96e360672 120 uint8_t global_config__spad_enables_ref_2;
charlesmn 0:3ac96e360672 121
charlesmn 0:3ac96e360672 122 uint8_t global_config__spad_enables_ref_3;
charlesmn 0:3ac96e360672 123
charlesmn 0:3ac96e360672 124 uint8_t global_config__spad_enables_ref_4;
charlesmn 0:3ac96e360672 125
charlesmn 0:3ac96e360672 126 uint8_t global_config__spad_enables_ref_5;
charlesmn 0:3ac96e360672 127
charlesmn 0:3ac96e360672 128 uint8_t global_config__ref_en_start_select;
charlesmn 0:3ac96e360672 129
charlesmn 0:3ac96e360672 130 uint8_t ref_spad_man__num_requested_ref_spads;
charlesmn 0:3ac96e360672 131
charlesmn 0:3ac96e360672 132 uint8_t ref_spad_man__ref_location;
charlesmn 0:3ac96e360672 133
charlesmn 0:3ac96e360672 134 uint16_t algo__crosstalk_compensation_plane_offset_kcps;
charlesmn 0:3ac96e360672 135
charlesmn 0:3ac96e360672 136 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn 0:3ac96e360672 137
charlesmn 0:3ac96e360672 138 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn 0:3ac96e360672 139
charlesmn 0:3ac96e360672 140 uint16_t ref_spad_char__total_rate_target_mcps;
charlesmn 0:3ac96e360672 141
charlesmn 0:3ac96e360672 142 int16_t algo__part_to_part_range_offset_mm;
charlesmn 0:3ac96e360672 143
charlesmn 0:3ac96e360672 144 int16_t mm_config__inner_offset_mm;
charlesmn 0:3ac96e360672 145
charlesmn 0:3ac96e360672 146 int16_t mm_config__outer_offset_mm;
charlesmn 0:3ac96e360672 147
charlesmn 0:3ac96e360672 148 } VL53L1_customer_nvm_managed_t;
charlesmn 0:3ac96e360672 149
charlesmn 0:3ac96e360672 150
charlesmn 0:3ac96e360672 151
charlesmn 0:3ac96e360672 152
charlesmn 0:3ac96e360672 153 typedef struct {
charlesmn 0:3ac96e360672 154 uint16_t dss_config__target_total_rate_mcps;
charlesmn 0:3ac96e360672 155
charlesmn 0:3ac96e360672 156 uint8_t debug__ctrl;
charlesmn 0:3ac96e360672 157
charlesmn 0:3ac96e360672 158 uint8_t test_mode__ctrl;
charlesmn 0:3ac96e360672 159
charlesmn 0:3ac96e360672 160 uint8_t clk_gating__ctrl;
charlesmn 0:3ac96e360672 161
charlesmn 0:3ac96e360672 162 uint8_t nvm_bist__ctrl;
charlesmn 0:3ac96e360672 163
charlesmn 0:3ac96e360672 164 uint8_t nvm_bist__num_nvm_words;
charlesmn 0:3ac96e360672 165
charlesmn 0:3ac96e360672 166 uint8_t nvm_bist__start_address;
charlesmn 0:3ac96e360672 167
charlesmn 0:3ac96e360672 168 uint8_t host_if__status;
charlesmn 0:3ac96e360672 169
charlesmn 0:3ac96e360672 170 uint8_t pad_i2c_hv__config;
charlesmn 0:3ac96e360672 171
charlesmn 0:3ac96e360672 172 uint8_t pad_i2c_hv__extsup_config;
charlesmn 0:3ac96e360672 173
charlesmn 0:3ac96e360672 174 uint8_t gpio_hv_pad__ctrl;
charlesmn 0:3ac96e360672 175
charlesmn 0:3ac96e360672 176 uint8_t gpio_hv_mux__ctrl;
charlesmn 0:3ac96e360672 177
charlesmn 0:3ac96e360672 178 uint8_t gpio__tio_hv_status;
charlesmn 0:3ac96e360672 179
charlesmn 0:3ac96e360672 180 uint8_t gpio__fio_hv_status;
charlesmn 0:3ac96e360672 181
charlesmn 0:3ac96e360672 182 uint8_t ana_config__spad_sel_pswidth;
charlesmn 0:3ac96e360672 183
charlesmn 0:3ac96e360672 184 uint8_t ana_config__vcsel_pulse_width_offset;
charlesmn 0:3ac96e360672 185
charlesmn 0:3ac96e360672 186 uint8_t ana_config__fast_osc__config_ctrl;
charlesmn 0:3ac96e360672 187
charlesmn 0:3ac96e360672 188 uint8_t sigma_estimator__effective_pulse_width_ns;
charlesmn 0:3ac96e360672 189
charlesmn 0:3ac96e360672 190 uint8_t sigma_estimator__effective_ambient_width_ns;
charlesmn 0:3ac96e360672 191
charlesmn 0:3ac96e360672 192 uint8_t sigma_estimator__sigma_ref_mm;
charlesmn 0:3ac96e360672 193
charlesmn 0:3ac96e360672 194 uint8_t algo__crosstalk_compensation_valid_height_mm;
charlesmn 0:3ac96e360672 195
charlesmn 0:3ac96e360672 196 uint8_t spare_host_config__static_config_spare_0;
charlesmn 0:3ac96e360672 197
charlesmn 0:3ac96e360672 198 uint8_t spare_host_config__static_config_spare_1;
charlesmn 0:3ac96e360672 199
charlesmn 0:3ac96e360672 200 uint16_t algo__range_ignore_threshold_mcps;
charlesmn 0:3ac96e360672 201
charlesmn 0:3ac96e360672 202 uint8_t algo__range_ignore_valid_height_mm;
charlesmn 0:3ac96e360672 203
charlesmn 0:3ac96e360672 204 uint8_t algo__range_min_clip;
charlesmn 0:3ac96e360672 205
charlesmn 0:3ac96e360672 206 uint8_t algo__consistency_check__tolerance;
charlesmn 0:3ac96e360672 207
charlesmn 0:3ac96e360672 208 uint8_t spare_host_config__static_config_spare_2;
charlesmn 0:3ac96e360672 209
charlesmn 0:3ac96e360672 210 uint8_t sd_config__reset_stages_msb;
charlesmn 0:3ac96e360672 211
charlesmn 0:3ac96e360672 212 uint8_t sd_config__reset_stages_lsb;
charlesmn 0:3ac96e360672 213
charlesmn 0:3ac96e360672 214 } VL53L1_static_config_t;
charlesmn 0:3ac96e360672 215
charlesmn 0:3ac96e360672 216
charlesmn 0:3ac96e360672 217
charlesmn 0:3ac96e360672 218
charlesmn 0:3ac96e360672 219 typedef struct {
charlesmn 0:3ac96e360672 220 uint8_t gph_config__stream_count_update_value;
charlesmn 0:3ac96e360672 221
charlesmn 0:3ac96e360672 222 uint8_t global_config__stream_divider;
charlesmn 0:3ac96e360672 223
charlesmn 0:3ac96e360672 224 uint8_t system__interrupt_config_gpio;
charlesmn 0:3ac96e360672 225
charlesmn 0:3ac96e360672 226 uint8_t cal_config__vcsel_start;
charlesmn 0:3ac96e360672 227
charlesmn 0:3ac96e360672 228 uint16_t cal_config__repeat_rate;
charlesmn 0:3ac96e360672 229
charlesmn 0:3ac96e360672 230 uint8_t global_config__vcsel_width;
charlesmn 0:3ac96e360672 231
charlesmn 0:3ac96e360672 232 uint8_t phasecal_config__timeout_macrop;
charlesmn 0:3ac96e360672 233
charlesmn 0:3ac96e360672 234 uint8_t phasecal_config__target;
charlesmn 0:3ac96e360672 235
charlesmn 0:3ac96e360672 236 uint8_t phasecal_config__override;
charlesmn 0:3ac96e360672 237
charlesmn 0:3ac96e360672 238 uint8_t dss_config__roi_mode_control;
charlesmn 0:3ac96e360672 239
charlesmn 0:3ac96e360672 240 uint16_t system__thresh_rate_high;
charlesmn 0:3ac96e360672 241
charlesmn 0:3ac96e360672 242 uint16_t system__thresh_rate_low;
charlesmn 0:3ac96e360672 243
charlesmn 0:3ac96e360672 244 uint16_t dss_config__manual_effective_spads_select;
charlesmn 0:3ac96e360672 245
charlesmn 0:3ac96e360672 246 uint8_t dss_config__manual_block_select;
charlesmn 0:3ac96e360672 247
charlesmn 0:3ac96e360672 248 uint8_t dss_config__aperture_attenuation;
charlesmn 0:3ac96e360672 249
charlesmn 0:3ac96e360672 250 uint8_t dss_config__max_spads_limit;
charlesmn 0:3ac96e360672 251
charlesmn 0:3ac96e360672 252 uint8_t dss_config__min_spads_limit;
charlesmn 0:3ac96e360672 253
charlesmn 0:3ac96e360672 254 } VL53L1_general_config_t;
charlesmn 0:3ac96e360672 255
charlesmn 0:3ac96e360672 256
charlesmn 0:3ac96e360672 257
charlesmn 0:3ac96e360672 258
charlesmn 0:3ac96e360672 259 typedef struct {
charlesmn 0:3ac96e360672 260 uint8_t mm_config__timeout_macrop_a_hi;
charlesmn 0:3ac96e360672 261
charlesmn 0:3ac96e360672 262 uint8_t mm_config__timeout_macrop_a_lo;
charlesmn 0:3ac96e360672 263
charlesmn 0:3ac96e360672 264 uint8_t mm_config__timeout_macrop_b_hi;
charlesmn 0:3ac96e360672 265
charlesmn 0:3ac96e360672 266 uint8_t mm_config__timeout_macrop_b_lo;
charlesmn 0:3ac96e360672 267
charlesmn 0:3ac96e360672 268 uint8_t range_config__timeout_macrop_a_hi;
charlesmn 0:3ac96e360672 269
charlesmn 0:3ac96e360672 270 uint8_t range_config__timeout_macrop_a_lo;
charlesmn 0:3ac96e360672 271
charlesmn 0:3ac96e360672 272 uint8_t range_config__vcsel_period_a;
charlesmn 0:3ac96e360672 273
charlesmn 0:3ac96e360672 274 uint8_t range_config__timeout_macrop_b_hi;
charlesmn 0:3ac96e360672 275
charlesmn 0:3ac96e360672 276 uint8_t range_config__timeout_macrop_b_lo;
charlesmn 0:3ac96e360672 277
charlesmn 0:3ac96e360672 278 uint8_t range_config__vcsel_period_b;
charlesmn 0:3ac96e360672 279
charlesmn 0:3ac96e360672 280 uint16_t range_config__sigma_thresh;
charlesmn 0:3ac96e360672 281
charlesmn 0:3ac96e360672 282 uint16_t range_config__min_count_rate_rtn_limit_mcps;
charlesmn 0:3ac96e360672 283
charlesmn 0:3ac96e360672 284 uint8_t range_config__valid_phase_low;
charlesmn 0:3ac96e360672 285
charlesmn 0:3ac96e360672 286 uint8_t range_config__valid_phase_high;
charlesmn 0:3ac96e360672 287
charlesmn 0:3ac96e360672 288 uint32_t system__intermeasurement_period;
charlesmn 0:3ac96e360672 289
charlesmn 0:3ac96e360672 290 uint8_t system__fractional_enable;
charlesmn 0:3ac96e360672 291
charlesmn 0:3ac96e360672 292 } VL53L1_timing_config_t;
charlesmn 0:3ac96e360672 293
charlesmn 0:3ac96e360672 294
charlesmn 0:3ac96e360672 295
charlesmn 0:3ac96e360672 296
charlesmn 0:3ac96e360672 297 typedef struct {
charlesmn 0:3ac96e360672 298 uint8_t system__grouped_parameter_hold_0;
charlesmn 0:3ac96e360672 299
charlesmn 0:3ac96e360672 300 uint16_t system__thresh_high;
charlesmn 0:3ac96e360672 301
charlesmn 0:3ac96e360672 302 uint16_t system__thresh_low;
charlesmn 0:3ac96e360672 303
charlesmn 0:3ac96e360672 304 uint8_t system__enable_xtalk_per_quadrant;
charlesmn 0:3ac96e360672 305
charlesmn 0:3ac96e360672 306 uint8_t system__seed_config;
charlesmn 0:3ac96e360672 307
charlesmn 0:3ac96e360672 308 uint8_t sd_config__woi_sd0;
charlesmn 0:3ac96e360672 309
charlesmn 0:3ac96e360672 310 uint8_t sd_config__woi_sd1;
charlesmn 0:3ac96e360672 311
charlesmn 0:3ac96e360672 312 uint8_t sd_config__initial_phase_sd0;
charlesmn 0:3ac96e360672 313
charlesmn 0:3ac96e360672 314 uint8_t sd_config__initial_phase_sd1;
charlesmn 0:3ac96e360672 315
charlesmn 0:3ac96e360672 316 uint8_t system__grouped_parameter_hold_1;
charlesmn 0:3ac96e360672 317
charlesmn 0:3ac96e360672 318 uint8_t sd_config__first_order_select;
charlesmn 0:3ac96e360672 319
charlesmn 0:3ac96e360672 320 uint8_t sd_config__quantifier;
charlesmn 0:3ac96e360672 321
charlesmn 0:3ac96e360672 322 uint8_t roi_config__user_roi_centre_spad;
charlesmn 0:3ac96e360672 323
charlesmn 0:3ac96e360672 324 uint8_t roi_config__user_roi_requested_global_xy_size;
charlesmn 0:3ac96e360672 325
charlesmn 0:3ac96e360672 326 uint8_t system__sequence_config;
charlesmn 0:3ac96e360672 327
charlesmn 0:3ac96e360672 328 uint8_t system__grouped_parameter_hold;
charlesmn 0:3ac96e360672 329
charlesmn 0:3ac96e360672 330 } VL53L1_dynamic_config_t;
charlesmn 0:3ac96e360672 331
charlesmn 0:3ac96e360672 332
charlesmn 0:3ac96e360672 333
charlesmn 0:3ac96e360672 334
charlesmn 0:3ac96e360672 335 typedef struct {
charlesmn 0:3ac96e360672 336 uint8_t power_management__go1_power_force;
charlesmn 0:3ac96e360672 337
charlesmn 0:3ac96e360672 338 uint8_t system__stream_count_ctrl;
charlesmn 0:3ac96e360672 339
charlesmn 0:3ac96e360672 340 uint8_t firmware__enable;
charlesmn 0:3ac96e360672 341
charlesmn 0:3ac96e360672 342 uint8_t system__interrupt_clear;
charlesmn 0:3ac96e360672 343
charlesmn 0:3ac96e360672 344 uint8_t system__mode_start;
charlesmn 0:3ac96e360672 345
charlesmn 0:3ac96e360672 346 } VL53L1_system_control_t;
charlesmn 0:3ac96e360672 347
charlesmn 0:3ac96e360672 348
charlesmn 0:3ac96e360672 349
charlesmn 0:3ac96e360672 350
charlesmn 0:3ac96e360672 351 typedef struct {
charlesmn 0:3ac96e360672 352 uint8_t result__interrupt_status;
charlesmn 0:3ac96e360672 353
charlesmn 0:3ac96e360672 354 uint8_t result__range_status;
charlesmn 0:3ac96e360672 355
charlesmn 0:3ac96e360672 356 uint8_t result__report_status;
charlesmn 0:3ac96e360672 357
charlesmn 0:3ac96e360672 358 uint8_t result__stream_count;
charlesmn 0:3ac96e360672 359
charlesmn 0:3ac96e360672 360 uint16_t result__dss_actual_effective_spads_sd0;
charlesmn 0:3ac96e360672 361
charlesmn 0:3ac96e360672 362 uint16_t result__peak_signal_count_rate_mcps_sd0;
charlesmn 0:3ac96e360672 363
charlesmn 0:3ac96e360672 364 uint16_t result__ambient_count_rate_mcps_sd0;
charlesmn 0:3ac96e360672 365
charlesmn 0:3ac96e360672 366 uint16_t result__sigma_sd0;
charlesmn 0:3ac96e360672 367
charlesmn 0:3ac96e360672 368 uint16_t result__phase_sd0;
charlesmn 0:3ac96e360672 369
charlesmn 0:3ac96e360672 370 uint16_t result__final_crosstalk_corrected_range_mm_sd0;
charlesmn 0:3ac96e360672 371
charlesmn 0:3ac96e360672 372 uint16_t result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;
charlesmn 0:3ac96e360672 373
charlesmn 0:3ac96e360672 374 uint16_t result__mm_inner_actual_effective_spads_sd0;
charlesmn 0:3ac96e360672 375
charlesmn 0:3ac96e360672 376 uint16_t result__mm_outer_actual_effective_spads_sd0;
charlesmn 0:3ac96e360672 377
charlesmn 0:3ac96e360672 378 uint16_t result__avg_signal_count_rate_mcps_sd0;
charlesmn 0:3ac96e360672 379
charlesmn 0:3ac96e360672 380 uint16_t result__dss_actual_effective_spads_sd1;
charlesmn 0:3ac96e360672 381
charlesmn 0:3ac96e360672 382 uint16_t result__peak_signal_count_rate_mcps_sd1;
charlesmn 0:3ac96e360672 383
charlesmn 0:3ac96e360672 384 uint16_t result__ambient_count_rate_mcps_sd1;
charlesmn 0:3ac96e360672 385
charlesmn 0:3ac96e360672 386 uint16_t result__sigma_sd1;
charlesmn 0:3ac96e360672 387
charlesmn 0:3ac96e360672 388 uint16_t result__phase_sd1;
charlesmn 0:3ac96e360672 389
charlesmn 0:3ac96e360672 390 uint16_t result__final_crosstalk_corrected_range_mm_sd1;
charlesmn 0:3ac96e360672 391
charlesmn 0:3ac96e360672 392 uint16_t result__spare_0_sd1;
charlesmn 0:3ac96e360672 393
charlesmn 0:3ac96e360672 394 uint16_t result__spare_1_sd1;
charlesmn 0:3ac96e360672 395
charlesmn 0:3ac96e360672 396 uint16_t result__spare_2_sd1;
charlesmn 0:3ac96e360672 397
charlesmn 0:3ac96e360672 398 uint8_t result__spare_3_sd1;
charlesmn 0:3ac96e360672 399
charlesmn 0:3ac96e360672 400 uint8_t result__thresh_info;
charlesmn 0:3ac96e360672 401
charlesmn 0:3ac96e360672 402 } VL53L1_system_results_t;
charlesmn 0:3ac96e360672 403
charlesmn 0:3ac96e360672 404
charlesmn 0:3ac96e360672 405
charlesmn 0:3ac96e360672 406
charlesmn 0:3ac96e360672 407 typedef struct {
charlesmn 0:3ac96e360672 408 uint32_t result_core__ambient_window_events_sd0;
charlesmn 0:3ac96e360672 409
charlesmn 0:3ac96e360672 410 uint32_t result_core__ranging_total_events_sd0;
charlesmn 0:3ac96e360672 411
charlesmn 0:3ac96e360672 412 int32_t result_core__signal_total_events_sd0;
charlesmn 0:3ac96e360672 413
charlesmn 0:3ac96e360672 414 uint32_t result_core__total_periods_elapsed_sd0;
charlesmn 0:3ac96e360672 415
charlesmn 0:3ac96e360672 416 uint32_t result_core__ambient_window_events_sd1;
charlesmn 0:3ac96e360672 417
charlesmn 0:3ac96e360672 418 uint32_t result_core__ranging_total_events_sd1;
charlesmn 0:3ac96e360672 419
charlesmn 0:3ac96e360672 420 int32_t result_core__signal_total_events_sd1;
charlesmn 0:3ac96e360672 421
charlesmn 0:3ac96e360672 422 uint32_t result_core__total_periods_elapsed_sd1;
charlesmn 0:3ac96e360672 423
charlesmn 0:3ac96e360672 424 uint8_t result_core__spare_0;
charlesmn 0:3ac96e360672 425
charlesmn 0:3ac96e360672 426 } VL53L1_core_results_t;
charlesmn 0:3ac96e360672 427
charlesmn 0:3ac96e360672 428
charlesmn 0:3ac96e360672 429
charlesmn 0:3ac96e360672 430
charlesmn 0:3ac96e360672 431 typedef struct {
charlesmn 0:3ac96e360672 432 uint16_t phasecal_result__reference_phase;
charlesmn 0:3ac96e360672 433
charlesmn 0:3ac96e360672 434 uint8_t phasecal_result__vcsel_start;
charlesmn 0:3ac96e360672 435
charlesmn 0:3ac96e360672 436 uint8_t ref_spad_char_result__num_actual_ref_spads;
charlesmn 0:3ac96e360672 437
charlesmn 0:3ac96e360672 438 uint8_t ref_spad_char_result__ref_location;
charlesmn 0:3ac96e360672 439
charlesmn 0:3ac96e360672 440 uint8_t vhv_result__coldboot_status;
charlesmn 0:3ac96e360672 441
charlesmn 0:3ac96e360672 442 uint8_t vhv_result__search_result;
charlesmn 0:3ac96e360672 443
charlesmn 0:3ac96e360672 444 uint8_t vhv_result__latest_setting;
charlesmn 0:3ac96e360672 445
charlesmn 0:3ac96e360672 446 uint16_t result__osc_calibrate_val;
charlesmn 0:3ac96e360672 447
charlesmn 0:3ac96e360672 448 uint8_t ana_config__powerdown_go1;
charlesmn 0:3ac96e360672 449
charlesmn 0:3ac96e360672 450 uint8_t ana_config__ref_bg_ctrl;
charlesmn 0:3ac96e360672 451
charlesmn 0:3ac96e360672 452 uint8_t ana_config__regdvdd1v2_ctrl;
charlesmn 0:3ac96e360672 453
charlesmn 0:3ac96e360672 454 uint8_t ana_config__osc_slow_ctrl;
charlesmn 0:3ac96e360672 455
charlesmn 0:3ac96e360672 456 uint8_t test_mode__status;
charlesmn 0:3ac96e360672 457
charlesmn 0:3ac96e360672 458 uint8_t firmware__system_status;
charlesmn 0:3ac96e360672 459
charlesmn 0:3ac96e360672 460 uint8_t firmware__mode_status;
charlesmn 0:3ac96e360672 461
charlesmn 0:3ac96e360672 462 uint8_t firmware__secondary_mode_status;
charlesmn 0:3ac96e360672 463
charlesmn 0:3ac96e360672 464 uint16_t firmware__cal_repeat_rate_counter;
charlesmn 0:3ac96e360672 465
charlesmn 0:3ac96e360672 466 uint16_t gph__system__thresh_high;
charlesmn 0:3ac96e360672 467
charlesmn 0:3ac96e360672 468 uint16_t gph__system__thresh_low;
charlesmn 0:3ac96e360672 469
charlesmn 0:3ac96e360672 470 uint8_t gph__system__enable_xtalk_per_quadrant;
charlesmn 0:3ac96e360672 471
charlesmn 0:3ac96e360672 472 uint8_t gph__spare_0;
charlesmn 0:3ac96e360672 473
charlesmn 0:3ac96e360672 474 uint8_t gph__sd_config__woi_sd0;
charlesmn 0:3ac96e360672 475
charlesmn 0:3ac96e360672 476 uint8_t gph__sd_config__woi_sd1;
charlesmn 0:3ac96e360672 477
charlesmn 0:3ac96e360672 478 uint8_t gph__sd_config__initial_phase_sd0;
charlesmn 0:3ac96e360672 479
charlesmn 0:3ac96e360672 480 uint8_t gph__sd_config__initial_phase_sd1;
charlesmn 0:3ac96e360672 481
charlesmn 0:3ac96e360672 482 uint8_t gph__sd_config__first_order_select;
charlesmn 0:3ac96e360672 483
charlesmn 0:3ac96e360672 484 uint8_t gph__sd_config__quantifier;
charlesmn 0:3ac96e360672 485
charlesmn 0:3ac96e360672 486 uint8_t gph__roi_config__user_roi_centre_spad;
charlesmn 0:3ac96e360672 487
charlesmn 0:3ac96e360672 488 uint8_t gph__roi_config__user_roi_requested_global_xy_size;
charlesmn 0:3ac96e360672 489
charlesmn 0:3ac96e360672 490 uint8_t gph__system__sequence_config;
charlesmn 0:3ac96e360672 491
charlesmn 0:3ac96e360672 492 uint8_t gph__gph_id;
charlesmn 0:3ac96e360672 493
charlesmn 0:3ac96e360672 494 uint8_t system__interrupt_set;
charlesmn 0:3ac96e360672 495
charlesmn 0:3ac96e360672 496 uint8_t interrupt_manager__enables;
charlesmn 0:3ac96e360672 497
charlesmn 0:3ac96e360672 498 uint8_t interrupt_manager__clear;
charlesmn 0:3ac96e360672 499
charlesmn 0:3ac96e360672 500 uint8_t interrupt_manager__status;
charlesmn 0:3ac96e360672 501
charlesmn 0:3ac96e360672 502 uint8_t mcu_to_host_bank__wr_access_en;
charlesmn 0:3ac96e360672 503
charlesmn 0:3ac96e360672 504 uint8_t power_management__go1_reset_status;
charlesmn 0:3ac96e360672 505
charlesmn 0:3ac96e360672 506 uint8_t pad_startup_mode__value_ro;
charlesmn 0:3ac96e360672 507
charlesmn 0:3ac96e360672 508 uint8_t pad_startup_mode__value_ctrl;
charlesmn 0:3ac96e360672 509
charlesmn 0:3ac96e360672 510 uint32_t pll_period_us;
charlesmn 0:3ac96e360672 511
charlesmn 0:3ac96e360672 512 uint32_t interrupt_scheduler__data_out;
charlesmn 0:3ac96e360672 513
charlesmn 0:3ac96e360672 514 uint8_t nvm_bist__complete;
charlesmn 0:3ac96e360672 515
charlesmn 0:3ac96e360672 516 uint8_t nvm_bist__status;
charlesmn 0:3ac96e360672 517
charlesmn 0:3ac96e360672 518 } VL53L1_debug_results_t;
charlesmn 0:3ac96e360672 519
charlesmn 0:3ac96e360672 520
charlesmn 0:3ac96e360672 521
charlesmn 0:3ac96e360672 522
charlesmn 0:3ac96e360672 523 typedef struct {
charlesmn 0:3ac96e360672 524 uint8_t identification__model_id;
charlesmn 0:3ac96e360672 525
charlesmn 0:3ac96e360672 526 uint8_t identification__module_type;
charlesmn 0:3ac96e360672 527
charlesmn 0:3ac96e360672 528 uint8_t identification__revision_id;
charlesmn 0:3ac96e360672 529
charlesmn 0:3ac96e360672 530 uint16_t identification__module_id;
charlesmn 0:3ac96e360672 531
charlesmn 0:3ac96e360672 532 uint8_t ana_config__fast_osc__trim_max;
charlesmn 0:3ac96e360672 533
charlesmn 0:3ac96e360672 534 uint8_t ana_config__fast_osc__freq_set;
charlesmn 0:3ac96e360672 535
charlesmn 0:3ac96e360672 536 uint8_t ana_config__vcsel_trim;
charlesmn 0:3ac96e360672 537
charlesmn 0:3ac96e360672 538 uint8_t ana_config__vcsel_selion;
charlesmn 0:3ac96e360672 539
charlesmn 0:3ac96e360672 540 uint8_t ana_config__vcsel_selion_max;
charlesmn 0:3ac96e360672 541
charlesmn 0:3ac96e360672 542 uint8_t protected_laser_safety__lock_bit;
charlesmn 0:3ac96e360672 543
charlesmn 0:3ac96e360672 544 uint8_t laser_safety__key;
charlesmn 0:3ac96e360672 545
charlesmn 0:3ac96e360672 546 uint8_t laser_safety__key_ro;
charlesmn 0:3ac96e360672 547
charlesmn 0:3ac96e360672 548 uint8_t laser_safety__clip;
charlesmn 0:3ac96e360672 549
charlesmn 0:3ac96e360672 550 uint8_t laser_safety__mult;
charlesmn 0:3ac96e360672 551
charlesmn 0:3ac96e360672 552 uint8_t global_config__spad_enables_rtn_0;
charlesmn 0:3ac96e360672 553
charlesmn 0:3ac96e360672 554 uint8_t global_config__spad_enables_rtn_1;
charlesmn 0:3ac96e360672 555
charlesmn 0:3ac96e360672 556 uint8_t global_config__spad_enables_rtn_2;
charlesmn 0:3ac96e360672 557
charlesmn 0:3ac96e360672 558 uint8_t global_config__spad_enables_rtn_3;
charlesmn 0:3ac96e360672 559
charlesmn 0:3ac96e360672 560 uint8_t global_config__spad_enables_rtn_4;
charlesmn 0:3ac96e360672 561
charlesmn 0:3ac96e360672 562 uint8_t global_config__spad_enables_rtn_5;
charlesmn 0:3ac96e360672 563
charlesmn 0:3ac96e360672 564 uint8_t global_config__spad_enables_rtn_6;
charlesmn 0:3ac96e360672 565
charlesmn 0:3ac96e360672 566 uint8_t global_config__spad_enables_rtn_7;
charlesmn 0:3ac96e360672 567
charlesmn 0:3ac96e360672 568 uint8_t global_config__spad_enables_rtn_8;
charlesmn 0:3ac96e360672 569
charlesmn 0:3ac96e360672 570 uint8_t global_config__spad_enables_rtn_9;
charlesmn 0:3ac96e360672 571
charlesmn 0:3ac96e360672 572 uint8_t global_config__spad_enables_rtn_10;
charlesmn 0:3ac96e360672 573
charlesmn 0:3ac96e360672 574 uint8_t global_config__spad_enables_rtn_11;
charlesmn 0:3ac96e360672 575
charlesmn 0:3ac96e360672 576 uint8_t global_config__spad_enables_rtn_12;
charlesmn 0:3ac96e360672 577
charlesmn 0:3ac96e360672 578 uint8_t global_config__spad_enables_rtn_13;
charlesmn 0:3ac96e360672 579
charlesmn 0:3ac96e360672 580 uint8_t global_config__spad_enables_rtn_14;
charlesmn 0:3ac96e360672 581
charlesmn 0:3ac96e360672 582 uint8_t global_config__spad_enables_rtn_15;
charlesmn 0:3ac96e360672 583
charlesmn 0:3ac96e360672 584 uint8_t global_config__spad_enables_rtn_16;
charlesmn 0:3ac96e360672 585
charlesmn 0:3ac96e360672 586 uint8_t global_config__spad_enables_rtn_17;
charlesmn 0:3ac96e360672 587
charlesmn 0:3ac96e360672 588 uint8_t global_config__spad_enables_rtn_18;
charlesmn 0:3ac96e360672 589
charlesmn 0:3ac96e360672 590 uint8_t global_config__spad_enables_rtn_19;
charlesmn 0:3ac96e360672 591
charlesmn 0:3ac96e360672 592 uint8_t global_config__spad_enables_rtn_20;
charlesmn 0:3ac96e360672 593
charlesmn 0:3ac96e360672 594 uint8_t global_config__spad_enables_rtn_21;
charlesmn 0:3ac96e360672 595
charlesmn 0:3ac96e360672 596 uint8_t global_config__spad_enables_rtn_22;
charlesmn 0:3ac96e360672 597
charlesmn 0:3ac96e360672 598 uint8_t global_config__spad_enables_rtn_23;
charlesmn 0:3ac96e360672 599
charlesmn 0:3ac96e360672 600 uint8_t global_config__spad_enables_rtn_24;
charlesmn 0:3ac96e360672 601
charlesmn 0:3ac96e360672 602 uint8_t global_config__spad_enables_rtn_25;
charlesmn 0:3ac96e360672 603
charlesmn 0:3ac96e360672 604 uint8_t global_config__spad_enables_rtn_26;
charlesmn 0:3ac96e360672 605
charlesmn 0:3ac96e360672 606 uint8_t global_config__spad_enables_rtn_27;
charlesmn 0:3ac96e360672 607
charlesmn 0:3ac96e360672 608 uint8_t global_config__spad_enables_rtn_28;
charlesmn 0:3ac96e360672 609
charlesmn 0:3ac96e360672 610 uint8_t global_config__spad_enables_rtn_29;
charlesmn 0:3ac96e360672 611
charlesmn 0:3ac96e360672 612 uint8_t global_config__spad_enables_rtn_30;
charlesmn 0:3ac96e360672 613
charlesmn 0:3ac96e360672 614 uint8_t global_config__spad_enables_rtn_31;
charlesmn 0:3ac96e360672 615
charlesmn 0:3ac96e360672 616 uint8_t roi_config__mode_roi_centre_spad;
charlesmn 0:3ac96e360672 617
charlesmn 0:3ac96e360672 618 uint8_t roi_config__mode_roi_xy_size;
charlesmn 0:3ac96e360672 619
charlesmn 0:3ac96e360672 620 } VL53L1_nvm_copy_data_t;
charlesmn 0:3ac96e360672 621
charlesmn 0:3ac96e360672 622
charlesmn 0:3ac96e360672 623
charlesmn 0:3ac96e360672 624
charlesmn 0:3ac96e360672 625 typedef struct {
charlesmn 0:3ac96e360672 626 uint8_t prev_shadow_result__interrupt_status;
charlesmn 0:3ac96e360672 627
charlesmn 0:3ac96e360672 628 uint8_t prev_shadow_result__range_status;
charlesmn 0:3ac96e360672 629
charlesmn 0:3ac96e360672 630 uint8_t prev_shadow_result__report_status;
charlesmn 0:3ac96e360672 631
charlesmn 0:3ac96e360672 632 uint8_t prev_shadow_result__stream_count;
charlesmn 0:3ac96e360672 633
charlesmn 0:3ac96e360672 634 uint16_t prev_shadow_result__dss_actual_effective_spads_sd0;
charlesmn 0:3ac96e360672 635
charlesmn 0:3ac96e360672 636 uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd0;
charlesmn 0:3ac96e360672 637
charlesmn 0:3ac96e360672 638 uint16_t prev_shadow_result__ambient_count_rate_mcps_sd0;
charlesmn 0:3ac96e360672 639
charlesmn 0:3ac96e360672 640 uint16_t prev_shadow_result__sigma_sd0;
charlesmn 0:3ac96e360672 641
charlesmn 0:3ac96e360672 642 uint16_t prev_shadow_result__phase_sd0;
charlesmn 0:3ac96e360672 643
charlesmn 0:3ac96e360672 644 uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd0;
charlesmn 0:3ac96e360672 645
charlesmn 0:3ac96e360672 646 uint16_t
charlesmn 0:3ac96e360672 647 psr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;
charlesmn 0:3ac96e360672 648
charlesmn 0:3ac96e360672 649 uint16_t prev_shadow_result__mm_inner_actual_effective_spads_sd0;
charlesmn 0:3ac96e360672 650
charlesmn 0:3ac96e360672 651 uint16_t prev_shadow_result__mm_outer_actual_effective_spads_sd0;
charlesmn 0:3ac96e360672 652
charlesmn 0:3ac96e360672 653 uint16_t prev_shadow_result__avg_signal_count_rate_mcps_sd0;
charlesmn 0:3ac96e360672 654
charlesmn 0:3ac96e360672 655 uint16_t prev_shadow_result__dss_actual_effective_spads_sd1;
charlesmn 0:3ac96e360672 656
charlesmn 0:3ac96e360672 657 uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd1;
charlesmn 0:3ac96e360672 658
charlesmn 0:3ac96e360672 659 uint16_t prev_shadow_result__ambient_count_rate_mcps_sd1;
charlesmn 0:3ac96e360672 660
charlesmn 0:3ac96e360672 661 uint16_t prev_shadow_result__sigma_sd1;
charlesmn 0:3ac96e360672 662
charlesmn 0:3ac96e360672 663 uint16_t prev_shadow_result__phase_sd1;
charlesmn 0:3ac96e360672 664
charlesmn 0:3ac96e360672 665 uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd1;
charlesmn 0:3ac96e360672 666
charlesmn 0:3ac96e360672 667 uint16_t prev_shadow_result__spare_0_sd1;
charlesmn 0:3ac96e360672 668
charlesmn 0:3ac96e360672 669 uint16_t prev_shadow_result__spare_1_sd1;
charlesmn 0:3ac96e360672 670
charlesmn 0:3ac96e360672 671 uint16_t prev_shadow_result__spare_2_sd1;
charlesmn 0:3ac96e360672 672
charlesmn 0:3ac96e360672 673 uint16_t prev_shadow_result__spare_3_sd1;
charlesmn 0:3ac96e360672 674
charlesmn 0:3ac96e360672 675 } VL53L1_prev_shadow_system_results_t;
charlesmn 0:3ac96e360672 676
charlesmn 0:3ac96e360672 677
charlesmn 0:3ac96e360672 678
charlesmn 0:3ac96e360672 679
charlesmn 0:3ac96e360672 680 typedef struct {
charlesmn 0:3ac96e360672 681 uint32_t prev_shadow_result_core__ambient_window_events_sd0;
charlesmn 0:3ac96e360672 682
charlesmn 0:3ac96e360672 683 uint32_t prev_shadow_result_core__ranging_total_events_sd0;
charlesmn 0:3ac96e360672 684
charlesmn 0:3ac96e360672 685 int32_t prev_shadow_result_core__signal_total_events_sd0;
charlesmn 0:3ac96e360672 686
charlesmn 0:3ac96e360672 687 uint32_t prev_shadow_result_core__total_periods_elapsed_sd0;
charlesmn 0:3ac96e360672 688
charlesmn 0:3ac96e360672 689 uint32_t prev_shadow_result_core__ambient_window_events_sd1;
charlesmn 0:3ac96e360672 690
charlesmn 0:3ac96e360672 691 uint32_t prev_shadow_result_core__ranging_total_events_sd1;
charlesmn 0:3ac96e360672 692
charlesmn 0:3ac96e360672 693 int32_t prev_shadow_result_core__signal_total_events_sd1;
charlesmn 0:3ac96e360672 694
charlesmn 0:3ac96e360672 695 uint32_t prev_shadow_result_core__total_periods_elapsed_sd1;
charlesmn 0:3ac96e360672 696
charlesmn 0:3ac96e360672 697 uint8_t prev_shadow_result_core__spare_0;
charlesmn 0:3ac96e360672 698
charlesmn 0:3ac96e360672 699 } VL53L1_prev_shadow_core_results_t;
charlesmn 0:3ac96e360672 700
charlesmn 0:3ac96e360672 701
charlesmn 0:3ac96e360672 702
charlesmn 0:3ac96e360672 703
charlesmn 0:3ac96e360672 704 typedef struct {
charlesmn 0:3ac96e360672 705 uint8_t result__debug_status;
charlesmn 0:3ac96e360672 706
charlesmn 0:3ac96e360672 707 uint8_t result__debug_stage;
charlesmn 0:3ac96e360672 708
charlesmn 0:3ac96e360672 709 } VL53L1_patch_debug_t;
charlesmn 0:3ac96e360672 710
charlesmn 0:3ac96e360672 711
charlesmn 0:3ac96e360672 712
charlesmn 0:3ac96e360672 713
charlesmn 0:3ac96e360672 714 typedef struct {
charlesmn 0:3ac96e360672 715 uint16_t gph__system__thresh_rate_high;
charlesmn 0:3ac96e360672 716
charlesmn 0:3ac96e360672 717 uint16_t gph__system__thresh_rate_low;
charlesmn 0:3ac96e360672 718
charlesmn 0:3ac96e360672 719 uint8_t gph__system__interrupt_config_gpio;
charlesmn 0:3ac96e360672 720
charlesmn 0:3ac96e360672 721 } VL53L1_gph_general_config_t;
charlesmn 0:3ac96e360672 722
charlesmn 0:3ac96e360672 723
charlesmn 0:3ac96e360672 724
charlesmn 0:3ac96e360672 725
charlesmn 0:3ac96e360672 726 typedef struct {
charlesmn 0:3ac96e360672 727 uint8_t gph__dss_config__roi_mode_control;
charlesmn 0:3ac96e360672 728
charlesmn 0:3ac96e360672 729 uint16_t gph__dss_config__manual_effective_spads_select;
charlesmn 0:3ac96e360672 730
charlesmn 0:3ac96e360672 731 uint8_t gph__dss_config__manual_block_select;
charlesmn 0:3ac96e360672 732
charlesmn 0:3ac96e360672 733 uint8_t gph__dss_config__max_spads_limit;
charlesmn 0:3ac96e360672 734
charlesmn 0:3ac96e360672 735 uint8_t gph__dss_config__min_spads_limit;
charlesmn 0:3ac96e360672 736
charlesmn 0:3ac96e360672 737 } VL53L1_gph_static_config_t;
charlesmn 0:3ac96e360672 738
charlesmn 0:3ac96e360672 739
charlesmn 0:3ac96e360672 740
charlesmn 0:3ac96e360672 741
charlesmn 0:3ac96e360672 742 typedef struct {
charlesmn 0:3ac96e360672 743 uint8_t gph__mm_config__timeout_macrop_a_hi;
charlesmn 0:3ac96e360672 744
charlesmn 0:3ac96e360672 745 uint8_t gph__mm_config__timeout_macrop_a_lo;
charlesmn 0:3ac96e360672 746
charlesmn 0:3ac96e360672 747 uint8_t gph__mm_config__timeout_macrop_b_hi;
charlesmn 0:3ac96e360672 748
charlesmn 0:3ac96e360672 749 uint8_t gph__mm_config__timeout_macrop_b_lo;
charlesmn 0:3ac96e360672 750
charlesmn 0:3ac96e360672 751 uint8_t gph__range_config__timeout_macrop_a_hi;
charlesmn 0:3ac96e360672 752
charlesmn 0:3ac96e360672 753 uint8_t gph__range_config__timeout_macrop_a_lo;
charlesmn 0:3ac96e360672 754
charlesmn 0:3ac96e360672 755 uint8_t gph__range_config__vcsel_period_a;
charlesmn 0:3ac96e360672 756
charlesmn 0:3ac96e360672 757 uint8_t gph__range_config__vcsel_period_b;
charlesmn 0:3ac96e360672 758
charlesmn 0:3ac96e360672 759 uint8_t gph__range_config__timeout_macrop_b_hi;
charlesmn 0:3ac96e360672 760
charlesmn 0:3ac96e360672 761 uint8_t gph__range_config__timeout_macrop_b_lo;
charlesmn 0:3ac96e360672 762
charlesmn 0:3ac96e360672 763 uint16_t gph__range_config__sigma_thresh;
charlesmn 0:3ac96e360672 764
charlesmn 0:3ac96e360672 765 uint16_t gph__range_config__min_count_rate_rtn_limit_mcps;
charlesmn 0:3ac96e360672 766
charlesmn 0:3ac96e360672 767 uint8_t gph__range_config__valid_phase_low;
charlesmn 0:3ac96e360672 768
charlesmn 0:3ac96e360672 769 uint8_t gph__range_config__valid_phase_high;
charlesmn 0:3ac96e360672 770
charlesmn 0:3ac96e360672 771 } VL53L1_gph_timing_config_t;
charlesmn 0:3ac96e360672 772
charlesmn 0:3ac96e360672 773
charlesmn 0:3ac96e360672 774
charlesmn 0:3ac96e360672 775
charlesmn 0:3ac96e360672 776 typedef struct {
charlesmn 0:3ac96e360672 777 uint8_t firmware__internal_stream_count_div;
charlesmn 0:3ac96e360672 778
charlesmn 0:3ac96e360672 779 uint8_t firmware__internal_stream_counter_val;
charlesmn 0:3ac96e360672 780
charlesmn 0:3ac96e360672 781 } VL53L1_fw_internal_t;
charlesmn 0:3ac96e360672 782
charlesmn 0:3ac96e360672 783
charlesmn 0:3ac96e360672 784
charlesmn 0:3ac96e360672 785
charlesmn 0:3ac96e360672 786 typedef struct {
charlesmn 0:3ac96e360672 787 uint8_t dss_calc__roi_ctrl;
charlesmn 0:3ac96e360672 788
charlesmn 0:3ac96e360672 789 uint8_t dss_calc__spare_1;
charlesmn 0:3ac96e360672 790
charlesmn 0:3ac96e360672 791 uint8_t dss_calc__spare_2;
charlesmn 0:3ac96e360672 792
charlesmn 0:3ac96e360672 793 uint8_t dss_calc__spare_3;
charlesmn 0:3ac96e360672 794
charlesmn 0:3ac96e360672 795 uint8_t dss_calc__spare_4;
charlesmn 0:3ac96e360672 796
charlesmn 0:3ac96e360672 797 uint8_t dss_calc__spare_5;
charlesmn 0:3ac96e360672 798
charlesmn 0:3ac96e360672 799 uint8_t dss_calc__spare_6;
charlesmn 0:3ac96e360672 800
charlesmn 0:3ac96e360672 801 uint8_t dss_calc__spare_7;
charlesmn 0:3ac96e360672 802
charlesmn 0:3ac96e360672 803 uint8_t dss_calc__user_roi_spad_en_0;
charlesmn 0:3ac96e360672 804
charlesmn 0:3ac96e360672 805 uint8_t dss_calc__user_roi_spad_en_1;
charlesmn 0:3ac96e360672 806
charlesmn 0:3ac96e360672 807 uint8_t dss_calc__user_roi_spad_en_2;
charlesmn 0:3ac96e360672 808
charlesmn 0:3ac96e360672 809 uint8_t dss_calc__user_roi_spad_en_3;
charlesmn 0:3ac96e360672 810
charlesmn 0:3ac96e360672 811 uint8_t dss_calc__user_roi_spad_en_4;
charlesmn 0:3ac96e360672 812
charlesmn 0:3ac96e360672 813 uint8_t dss_calc__user_roi_spad_en_5;
charlesmn 0:3ac96e360672 814
charlesmn 0:3ac96e360672 815 uint8_t dss_calc__user_roi_spad_en_6;
charlesmn 0:3ac96e360672 816
charlesmn 0:3ac96e360672 817 uint8_t dss_calc__user_roi_spad_en_7;
charlesmn 0:3ac96e360672 818
charlesmn 0:3ac96e360672 819 uint8_t dss_calc__user_roi_spad_en_8;
charlesmn 0:3ac96e360672 820
charlesmn 0:3ac96e360672 821 uint8_t dss_calc__user_roi_spad_en_9;
charlesmn 0:3ac96e360672 822
charlesmn 0:3ac96e360672 823 uint8_t dss_calc__user_roi_spad_en_10;
charlesmn 0:3ac96e360672 824
charlesmn 0:3ac96e360672 825 uint8_t dss_calc__user_roi_spad_en_11;
charlesmn 0:3ac96e360672 826
charlesmn 0:3ac96e360672 827 uint8_t dss_calc__user_roi_spad_en_12;
charlesmn 0:3ac96e360672 828
charlesmn 0:3ac96e360672 829 uint8_t dss_calc__user_roi_spad_en_13;
charlesmn 0:3ac96e360672 830
charlesmn 0:3ac96e360672 831 uint8_t dss_calc__user_roi_spad_en_14;
charlesmn 0:3ac96e360672 832
charlesmn 0:3ac96e360672 833 uint8_t dss_calc__user_roi_spad_en_15;
charlesmn 0:3ac96e360672 834
charlesmn 0:3ac96e360672 835 uint8_t dss_calc__user_roi_spad_en_16;
charlesmn 0:3ac96e360672 836
charlesmn 0:3ac96e360672 837 uint8_t dss_calc__user_roi_spad_en_17;
charlesmn 0:3ac96e360672 838
charlesmn 0:3ac96e360672 839 uint8_t dss_calc__user_roi_spad_en_18;
charlesmn 0:3ac96e360672 840
charlesmn 0:3ac96e360672 841 uint8_t dss_calc__user_roi_spad_en_19;
charlesmn 0:3ac96e360672 842
charlesmn 0:3ac96e360672 843 uint8_t dss_calc__user_roi_spad_en_20;
charlesmn 0:3ac96e360672 844
charlesmn 0:3ac96e360672 845 uint8_t dss_calc__user_roi_spad_en_21;
charlesmn 0:3ac96e360672 846
charlesmn 0:3ac96e360672 847 uint8_t dss_calc__user_roi_spad_en_22;
charlesmn 0:3ac96e360672 848
charlesmn 0:3ac96e360672 849 uint8_t dss_calc__user_roi_spad_en_23;
charlesmn 0:3ac96e360672 850
charlesmn 0:3ac96e360672 851 uint8_t dss_calc__user_roi_spad_en_24;
charlesmn 0:3ac96e360672 852
charlesmn 0:3ac96e360672 853 uint8_t dss_calc__user_roi_spad_en_25;
charlesmn 0:3ac96e360672 854
charlesmn 0:3ac96e360672 855 uint8_t dss_calc__user_roi_spad_en_26;
charlesmn 0:3ac96e360672 856
charlesmn 0:3ac96e360672 857 uint8_t dss_calc__user_roi_spad_en_27;
charlesmn 0:3ac96e360672 858
charlesmn 0:3ac96e360672 859 uint8_t dss_calc__user_roi_spad_en_28;
charlesmn 0:3ac96e360672 860
charlesmn 0:3ac96e360672 861 uint8_t dss_calc__user_roi_spad_en_29;
charlesmn 0:3ac96e360672 862
charlesmn 0:3ac96e360672 863 uint8_t dss_calc__user_roi_spad_en_30;
charlesmn 0:3ac96e360672 864
charlesmn 0:3ac96e360672 865 uint8_t dss_calc__user_roi_spad_en_31;
charlesmn 0:3ac96e360672 866
charlesmn 0:3ac96e360672 867 uint8_t dss_calc__user_roi_0;
charlesmn 0:3ac96e360672 868
charlesmn 0:3ac96e360672 869 uint8_t dss_calc__user_roi_1;
charlesmn 0:3ac96e360672 870
charlesmn 0:3ac96e360672 871 uint8_t dss_calc__mode_roi_0;
charlesmn 0:3ac96e360672 872
charlesmn 0:3ac96e360672 873 uint8_t dss_calc__mode_roi_1;
charlesmn 0:3ac96e360672 874
charlesmn 0:3ac96e360672 875 uint8_t sigma_estimator_calc__spare_0;
charlesmn 0:3ac96e360672 876
charlesmn 0:3ac96e360672 877 uint16_t vhv_result__peak_signal_rate_mcps;
charlesmn 0:3ac96e360672 878
charlesmn 0:3ac96e360672 879 uint32_t vhv_result__signal_total_events_ref;
charlesmn 0:3ac96e360672 880
charlesmn 0:3ac96e360672 881 uint16_t phasecal_result__phase_output_ref;
charlesmn 0:3ac96e360672 882
charlesmn 0:3ac96e360672 883 uint16_t dss_result__total_rate_per_spad;
charlesmn 0:3ac96e360672 884
charlesmn 0:3ac96e360672 885 uint8_t dss_result__enabled_blocks;
charlesmn 0:3ac96e360672 886
charlesmn 0:3ac96e360672 887 uint16_t dss_result__num_requested_spads;
charlesmn 0:3ac96e360672 888
charlesmn 0:3ac96e360672 889 uint16_t mm_result__inner_intersection_rate;
charlesmn 0:3ac96e360672 890
charlesmn 0:3ac96e360672 891 uint16_t mm_result__outer_complement_rate;
charlesmn 0:3ac96e360672 892
charlesmn 0:3ac96e360672 893 uint16_t mm_result__total_offset;
charlesmn 0:3ac96e360672 894
charlesmn 0:3ac96e360672 895 uint32_t xtalk_calc__xtalk_for_enabled_spads;
charlesmn 0:3ac96e360672 896
charlesmn 0:3ac96e360672 897 uint32_t xtalk_result__avg_xtalk_user_roi_kcps;
charlesmn 0:3ac96e360672 898
charlesmn 0:3ac96e360672 899 uint32_t xtalk_result__avg_xtalk_mm_inner_roi_kcps;
charlesmn 0:3ac96e360672 900
charlesmn 0:3ac96e360672 901 uint32_t xtalk_result__avg_xtalk_mm_outer_roi_kcps;
charlesmn 0:3ac96e360672 902
charlesmn 0:3ac96e360672 903 uint32_t range_result__accum_phase;
charlesmn 0:3ac96e360672 904
charlesmn 0:3ac96e360672 905 uint16_t range_result__offset_corrected_range;
charlesmn 0:3ac96e360672 906
charlesmn 0:3ac96e360672 907 } VL53L1_patch_results_t;
charlesmn 0:3ac96e360672 908
charlesmn 0:3ac96e360672 909
charlesmn 0:3ac96e360672 910
charlesmn 0:3ac96e360672 911
charlesmn 0:3ac96e360672 912 typedef struct {
charlesmn 0:3ac96e360672 913 uint8_t shadow_phasecal_result__vcsel_start;
charlesmn 0:3ac96e360672 914
charlesmn 0:3ac96e360672 915 uint8_t shadow_result__interrupt_status;
charlesmn 0:3ac96e360672 916
charlesmn 0:3ac96e360672 917 uint8_t shadow_result__range_status;
charlesmn 0:3ac96e360672 918
charlesmn 0:3ac96e360672 919 uint8_t shadow_result__report_status;
charlesmn 0:3ac96e360672 920
charlesmn 0:3ac96e360672 921 uint8_t shadow_result__stream_count;
charlesmn 0:3ac96e360672 922
charlesmn 0:3ac96e360672 923 uint16_t shadow_result__dss_actual_effective_spads_sd0;
charlesmn 0:3ac96e360672 924
charlesmn 0:3ac96e360672 925 uint16_t shadow_result__peak_signal_count_rate_mcps_sd0;
charlesmn 0:3ac96e360672 926
charlesmn 0:3ac96e360672 927 uint16_t shadow_result__ambient_count_rate_mcps_sd0;
charlesmn 0:3ac96e360672 928
charlesmn 0:3ac96e360672 929 uint16_t shadow_result__sigma_sd0;
charlesmn 0:3ac96e360672 930
charlesmn 0:3ac96e360672 931 uint16_t shadow_result__phase_sd0;
charlesmn 0:3ac96e360672 932
charlesmn 0:3ac96e360672 933 uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd0;
charlesmn 0:3ac96e360672 934
charlesmn 0:3ac96e360672 935 uint16_t
charlesmn 0:3ac96e360672 936 shr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;
charlesmn 0:3ac96e360672 937
charlesmn 0:3ac96e360672 938 uint16_t shadow_result__mm_inner_actual_effective_spads_sd0;
charlesmn 0:3ac96e360672 939
charlesmn 0:3ac96e360672 940 uint16_t shadow_result__mm_outer_actual_effective_spads_sd0;
charlesmn 0:3ac96e360672 941
charlesmn 0:3ac96e360672 942 uint16_t shadow_result__avg_signal_count_rate_mcps_sd0;
charlesmn 0:3ac96e360672 943
charlesmn 0:3ac96e360672 944 uint16_t shadow_result__dss_actual_effective_spads_sd1;
charlesmn 0:3ac96e360672 945
charlesmn 0:3ac96e360672 946 uint16_t shadow_result__peak_signal_count_rate_mcps_sd1;
charlesmn 0:3ac96e360672 947
charlesmn 0:3ac96e360672 948 uint16_t shadow_result__ambient_count_rate_mcps_sd1;
charlesmn 0:3ac96e360672 949
charlesmn 0:3ac96e360672 950 uint16_t shadow_result__sigma_sd1;
charlesmn 0:3ac96e360672 951
charlesmn 0:3ac96e360672 952 uint16_t shadow_result__phase_sd1;
charlesmn 0:3ac96e360672 953
charlesmn 0:3ac96e360672 954 uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd1;
charlesmn 0:3ac96e360672 955
charlesmn 0:3ac96e360672 956 uint16_t shadow_result__spare_0_sd1;
charlesmn 0:3ac96e360672 957
charlesmn 0:3ac96e360672 958 uint16_t shadow_result__spare_1_sd1;
charlesmn 0:3ac96e360672 959
charlesmn 0:3ac96e360672 960 uint16_t shadow_result__spare_2_sd1;
charlesmn 0:3ac96e360672 961
charlesmn 0:3ac96e360672 962 uint8_t shadow_result__spare_3_sd1;
charlesmn 0:3ac96e360672 963
charlesmn 0:3ac96e360672 964 uint8_t shadow_result__thresh_info;
charlesmn 0:3ac96e360672 965
charlesmn 0:3ac96e360672 966 uint8_t shadow_phasecal_result__reference_phase_hi;
charlesmn 0:3ac96e360672 967
charlesmn 0:3ac96e360672 968 uint8_t shadow_phasecal_result__reference_phase_lo;
charlesmn 0:3ac96e360672 969
charlesmn 0:3ac96e360672 970 } VL53L1_shadow_system_results_t;
charlesmn 0:3ac96e360672 971
charlesmn 0:3ac96e360672 972
charlesmn 0:3ac96e360672 973
charlesmn 0:3ac96e360672 974
charlesmn 0:3ac96e360672 975 typedef struct {
charlesmn 0:3ac96e360672 976 uint32_t shadow_result_core__ambient_window_events_sd0;
charlesmn 0:3ac96e360672 977
charlesmn 0:3ac96e360672 978 uint32_t shadow_result_core__ranging_total_events_sd0;
charlesmn 0:3ac96e360672 979
charlesmn 0:3ac96e360672 980 int32_t shadow_result_core__signal_total_events_sd0;
charlesmn 0:3ac96e360672 981
charlesmn 0:3ac96e360672 982 uint32_t shadow_result_core__total_periods_elapsed_sd0;
charlesmn 0:3ac96e360672 983
charlesmn 0:3ac96e360672 984 uint32_t shadow_result_core__ambient_window_events_sd1;
charlesmn 0:3ac96e360672 985
charlesmn 0:3ac96e360672 986 uint32_t shadow_result_core__ranging_total_events_sd1;
charlesmn 0:3ac96e360672 987
charlesmn 0:3ac96e360672 988 int32_t shadow_result_core__signal_total_events_sd1;
charlesmn 0:3ac96e360672 989
charlesmn 0:3ac96e360672 990 uint32_t shadow_result_core__total_periods_elapsed_sd1;
charlesmn 0:3ac96e360672 991
charlesmn 0:3ac96e360672 992 uint8_t shadow_result_core__spare_0;
charlesmn 0:3ac96e360672 993
charlesmn 0:3ac96e360672 994 } VL53L1_shadow_core_results_t;
charlesmn 0:3ac96e360672 995
charlesmn 0:3ac96e360672 996
charlesmn 0:3ac96e360672 997 #endif
charlesmn 0:3ac96e360672 998
charlesmn 0:3ac96e360672 999