ST Expansion SW Team / VL53L1

Fork, renaming of VL53L1CB-2

Dependencies:   X_NUCLEO_COMMON ST_INTERFACES

Dependents:   X_NUCLEO_53L1CB

inc/vl53l1_ll_def.h@13:3f1b341901dd, 2021-06-11 (annotated)

Committer:
Charles MacNeill
Date:
Fri Jun 11 17:08:27 2021 +0100
Revision:
13:3f1b341901dd
Parent:
7:1add29d51e72 
changing case of vl53l1cb.* so it works in linux

Who changed what in which revision?

UserRevisionLine numberNew contents of line
charlesmn 0:3ac96e360672 1
Charles MacNeill 7:1add29d51e72 2 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
Charles MacNeill 7:1add29d51e72 3 /******************************************************************************
charlesmn 0:3ac96e360672 4 * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
charlesmn 0:3ac96e360672 5
Charles MacNeill 7:1add29d51e72 6 This file is part of VL53L1 and is dual licensed,
Charles MacNeill 7:1add29d51e72 7 either GPL-2.0+
charlesmn 0:3ac96e360672 8 or 'BSD 3-clause "New" or "Revised" License' , at your option.
Charles MacNeill 7:1add29d51e72 9 ******************************************************************************
Charles MacNeill 7:1add29d51e72 10 */
charlesmn 0:3ac96e360672 11
charlesmn 0:3ac96e360672 12
charlesmn 0:3ac96e360672 13
charlesmn 0:3ac96e360672 14
charlesmn 0:3ac96e360672 15
charlesmn 0:3ac96e360672 16 #ifndef _VL53L1_LL_DEF_H_
charlesmn 0:3ac96e360672 17 #define _VL53L1_LL_DEF_H_
charlesmn 0:3ac96e360672 18
charlesmn 0:3ac96e360672 19 #include "vl53l1_error_codes.h"
charlesmn 0:3ac96e360672 20 #include "vl53l1_register_structs.h"
charlesmn 0:3ac96e360672 21 #include "vl53l1_platform_user_config.h"
charlesmn 0:3ac96e360672 22 #include "vl53l1_platform_user_defines.h"
charlesmn 0:3ac96e360672 23 #include "vl53l1_hist_structs.h"
charlesmn 0:3ac96e360672 24 #include "vl53l1_dmax_structs.h"
charlesmn 0:3ac96e360672 25 #include "vl53l1_error_exceptions.h"
charlesmn 0:3ac96e360672 26
charlesmn 0:3ac96e360672 27 #ifdef __cplusplus
charlesmn 0:3ac96e360672 28 extern "C" {
charlesmn 0:3ac96e360672 29 #endif
charlesmn 0:3ac96e360672 30
charlesmn 0:3ac96e360672 31
charlesmn 0:3ac96e360672 32
charlesmn 0:3ac96e360672 33
charlesmn 0:3ac96e360672 34 #define VL53L1_LL_API_IMPLEMENTATION_VER_MAJOR 1
charlesmn 0:3ac96e360672 35
charlesmn 0:3ac96e360672 36 #define VL53L1_LL_API_IMPLEMENTATION_VER_MINOR 1
charlesmn 0:3ac96e360672 37
charlesmn 0:3ac96e360672 38 #define VL53L1_LL_API_IMPLEMENTATION_VER_SUB 48
charlesmn 0:3ac96e360672 39
charlesmn 0:3ac96e360672 40 #define VL53L1_LL_API_IMPLEMENTATION_VER_REVISION 12224
charlesmn 0:3ac96e360672 41
charlesmn 0:3ac96e360672 42 #define VL53L1_LL_API_IMPLEMENTATION_VER_STRING "1.1.48.12224"
charlesmn 0:3ac96e360672 43
charlesmn 0:3ac96e360672 44
charlesmn 0:3ac96e360672 45 #define VL53L1_FIRMWARE_VER_MINIMUM 398
charlesmn 0:3ac96e360672 46 #define VL53L1_FIRMWARE_VER_MAXIMUM 400
charlesmn 0:3ac96e360672 47
charlesmn 0:3ac96e360672 48
charlesmn 0:3ac96e360672 49
charlesmn 0:3ac96e360672 50
charlesmn 0:3ac96e360672 51 #define VL53L1_LL_CALIBRATION_DATA_STRUCT_VERSION 0xECAB0102
charlesmn 0:3ac96e360672 52
charlesmn 0:3ac96e360672 53
charlesmn 0:3ac96e360672 54
charlesmn 0:3ac96e360672 55
charlesmn 0:3ac96e360672 56 #define VL53L1_LL_ZONE_CALIBRATION_DATA_STRUCT_VERSION 0xECAE0101
charlesmn 0:3ac96e360672 57
charlesmn 0:3ac96e360672 58
charlesmn 0:3ac96e360672 59
charlesmn 0:3ac96e360672 60
charlesmn 0:3ac96e360672 61
charlesmn 0:3ac96e360672 62 #define VL53L1_BIN_REC_SIZE 6
charlesmn 0:3ac96e360672 63
charlesmn 0:3ac96e360672 64 #define VL53L1_TIMING_CONF_A_B_SIZE 2
charlesmn 0:3ac96e360672 65
charlesmn 0:3ac96e360672 66 #define VL53L1_FRAME_WAIT_EVENT 6
charlesmn 0:3ac96e360672 67
charlesmn 0:3ac96e360672 68
charlesmn 0:3ac96e360672 69
charlesmn 0:3ac96e360672 70 #define VL53L1_MAX_XTALK_RANGE_RESULTS 5
charlesmn 0:3ac96e360672 71
charlesmn 0:3ac96e360672 72
charlesmn 0:3ac96e360672 73 #define VL53L1_MAX_OFFSET_RANGE_RESULTS 3
charlesmn 0:3ac96e360672 74
charlesmn 0:3ac96e360672 75
charlesmn 0:3ac96e360672 76 #define VL53L1_NVM_MAX_FMT_RANGE_DATA 4
charlesmn 0:3ac96e360672 77
charlesmn 0:3ac96e360672 78
charlesmn 0:3ac96e360672 79 #define VL53L1_NVM_PEAK_RATE_MAP_SAMPLES 25
charlesmn 0:3ac96e360672 80
charlesmn 0:3ac96e360672 81 #define VL53L1_NVM_PEAK_RATE_MAP_WIDTH 5
charlesmn 0:3ac96e360672 82
charlesmn 0:3ac96e360672 83 #define VL53L1_NVM_PEAK_RATE_MAP_HEIGHT 5
charlesmn 0:3ac96e360672 84
charlesmn 0:3ac96e360672 85
charlesmn 0:3ac96e360672 86
charlesmn 0:3ac96e360672 87
charlesmn 0:3ac96e360672 88 #define VL53L1_ERROR_DEVICE_FIRMWARE_TOO_OLD ((VL53L1_Error) - 80)
charlesmn 0:3ac96e360672 89
charlesmn 0:3ac96e360672 90 #define VL53L1_ERROR_DEVICE_FIRMWARE_TOO_NEW ((VL53L1_Error) - 85)
charlesmn 0:3ac96e360672 91
charlesmn 0:3ac96e360672 92 #define VL53L1_ERROR_UNIT_TEST_FAIL ((VL53L1_Error) - 90)
charlesmn 0:3ac96e360672 93
charlesmn 0:3ac96e360672 94 #define VL53L1_ERROR_FILE_READ_FAIL ((VL53L1_Error) - 95)
charlesmn 0:3ac96e360672 95
charlesmn 0:3ac96e360672 96 #define VL53L1_ERROR_FILE_WRITE_FAIL ((VL53L1_Error) - 96)
charlesmn 0:3ac96e360672 97
charlesmn 0:3ac96e360672 98
charlesmn 0:3ac96e360672 99
charlesmn 0:3ac96e360672 100
charlesmn 0:3ac96e360672 101
charlesmn 0:3ac96e360672 102
charlesmn 0:3ac96e360672 103 typedef struct {
charlesmn 0:3ac96e360672 104 uint32_t ll_revision;
charlesmn 0:3ac96e360672 105 uint8_t ll_major;
charlesmn 0:3ac96e360672 106 uint8_t ll_minor;
charlesmn 0:3ac96e360672 107 uint8_t ll_build;
charlesmn 0:3ac96e360672 108 } VL53L1_ll_version_t;
charlesmn 0:3ac96e360672 109
charlesmn 0:3ac96e360672 110
charlesmn 0:3ac96e360672 111
charlesmn 0:3ac96e360672 112
charlesmn 0:3ac96e360672 113 typedef struct {
charlesmn 0:3ac96e360672 114
charlesmn 0:3ac96e360672 115 uint8_t device_test_mode;
charlesmn 0:3ac96e360672 116 uint8_t VL53L1_p_009;
charlesmn 0:3ac96e360672 117 uint32_t timeout_us;
charlesmn 0:3ac96e360672 118 uint16_t target_count_rate_mcps;
charlesmn 0:3ac96e360672 119
charlesmn 0:3ac96e360672 120 uint16_t min_count_rate_limit_mcps;
charlesmn 0:3ac96e360672 121
charlesmn 0:3ac96e360672 122 uint16_t max_count_rate_limit_mcps;
charlesmn 0:3ac96e360672 123
charlesmn 0:3ac96e360672 124
charlesmn 0:3ac96e360672 125 } VL53L1_refspadchar_config_t;
charlesmn 0:3ac96e360672 126
charlesmn 0:3ac96e360672 127
charlesmn 0:3ac96e360672 128
charlesmn 0:3ac96e360672 129
charlesmn 0:3ac96e360672 130 typedef struct {
charlesmn 0:3ac96e360672 131
charlesmn 0:3ac96e360672 132 uint16_t dss_config__target_total_rate_mcps;
charlesmn 0:3ac96e360672 133
charlesmn 0:3ac96e360672 134 uint32_t phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 135
charlesmn 0:3ac96e360672 136 uint32_t mm_config_timeout_us;
charlesmn 0:3ac96e360672 137
charlesmn 0:3ac96e360672 138 uint32_t range_config_timeout_us;
charlesmn 0:3ac96e360672 139
charlesmn 0:3ac96e360672 140 uint8_t num_of_samples;
charlesmn 0:3ac96e360672 141
charlesmn 0:3ac96e360672 142 int16_t algo__crosstalk_extract_min_valid_range_mm;
charlesmn 0:3ac96e360672 143
charlesmn 0:3ac96e360672 144 int16_t algo__crosstalk_extract_max_valid_range_mm;
charlesmn 0:3ac96e360672 145
charlesmn 0:3ac96e360672 146 uint16_t algo__crosstalk_extract_max_valid_rate_kcps;
charlesmn 0:3ac96e360672 147
charlesmn 0:3ac96e360672 148 uint16_t algo__crosstalk_extract_max_sigma_mm;
charlesmn 0:3ac96e360672 149
charlesmn 0:3ac96e360672 150
charlesmn 0:3ac96e360672 151 } VL53L1_xtalkextract_config_t;
charlesmn 0:3ac96e360672 152
charlesmn 0:3ac96e360672 153
charlesmn 0:3ac96e360672 154
charlesmn 0:3ac96e360672 155
charlesmn 0:3ac96e360672 156 typedef struct {
charlesmn 0:3ac96e360672 157
charlesmn 0:3ac96e360672 158 uint16_t dss_config__target_total_rate_mcps;
charlesmn 0:3ac96e360672 159
charlesmn 0:3ac96e360672 160 uint32_t phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 161
charlesmn 0:3ac96e360672 162 uint32_t range_config_timeout_us;
charlesmn 0:3ac96e360672 163
charlesmn 0:3ac96e360672 164 uint32_t mm_config_timeout_us;
charlesmn 0:3ac96e360672 165
charlesmn 0:3ac96e360672 166 uint8_t pre_num_of_samples;
charlesmn 0:3ac96e360672 167
charlesmn 0:3ac96e360672 168 uint8_t mm1_num_of_samples;
charlesmn 0:3ac96e360672 169
charlesmn 0:3ac96e360672 170 uint8_t mm2_num_of_samples;
charlesmn 0:3ac96e360672 171
charlesmn 0:3ac96e360672 172
charlesmn 0:3ac96e360672 173 } VL53L1_offsetcal_config_t;
charlesmn 0:3ac96e360672 174
charlesmn 0:3ac96e360672 175
charlesmn 0:3ac96e360672 176
charlesmn 0:3ac96e360672 177
charlesmn 0:3ac96e360672 178 typedef struct {
charlesmn 0:3ac96e360672 179
charlesmn 0:3ac96e360672 180 uint16_t dss_config__target_total_rate_mcps;
charlesmn 0:3ac96e360672 181
charlesmn 0:3ac96e360672 182 uint32_t phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 183
charlesmn 0:3ac96e360672 184 uint32_t mm_config_timeout_us;
charlesmn 0:3ac96e360672 185
charlesmn 0:3ac96e360672 186 uint32_t range_config_timeout_us;
charlesmn 0:3ac96e360672 187
charlesmn 0:3ac96e360672 188 uint16_t phasecal_num_of_samples;
charlesmn 0:3ac96e360672 189
charlesmn 0:3ac96e360672 190 uint16_t zone_num_of_samples;
charlesmn 0:3ac96e360672 191
charlesmn 0:3ac96e360672 192
charlesmn 0:3ac96e360672 193 } VL53L1_zonecal_config_t;
charlesmn 0:3ac96e360672 194
charlesmn 0:3ac96e360672 195
charlesmn 0:3ac96e360672 196
charlesmn 0:3ac96e360672 197
charlesmn 0:3ac96e360672 198
charlesmn 0:3ac96e360672 199 typedef struct {
charlesmn 0:3ac96e360672 200
charlesmn 0:3ac96e360672 201 VL53L1_DeviceSscArray array_select;
charlesmn 0:3ac96e360672 202
charlesmn 0:3ac96e360672 203 uint8_t VL53L1_p_009;
charlesmn 0:3ac96e360672 204
charlesmn 0:3ac96e360672 205 uint8_t vcsel_start;
charlesmn 0:3ac96e360672 206
charlesmn 0:3ac96e360672 207 uint8_t vcsel_width;
charlesmn 0:3ac96e360672 208
charlesmn 0:3ac96e360672 209 uint32_t timeout_us;
charlesmn 0:3ac96e360672 210
charlesmn 0:3ac96e360672 211 uint16_t rate_limit_mcps;
charlesmn 0:3ac96e360672 212
charlesmn 0:3ac96e360672 213
charlesmn 0:3ac96e360672 214 } VL53L1_ssc_config_t;
charlesmn 0:3ac96e360672 215
charlesmn 0:3ac96e360672 216
charlesmn 0:3ac96e360672 217
charlesmn 0:3ac96e360672 218
charlesmn 0:3ac96e360672 219 typedef struct {
charlesmn 0:3ac96e360672 220
charlesmn 0:3ac96e360672 221
charlesmn 0:3ac96e360672 222 uint32_t algo__crosstalk_compensation_plane_offset_kcps;
charlesmn 0:3ac96e360672 223
charlesmn 0:3ac96e360672 224 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn 0:3ac96e360672 225
charlesmn 0:3ac96e360672 226 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn 0:3ac96e360672 227
charlesmn 0:3ac96e360672 228 uint32_t nvm_default__crosstalk_compensation_plane_offset_kcps;
charlesmn 0:3ac96e360672 229
charlesmn 0:3ac96e360672 230 int16_t nvm_default__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn 0:3ac96e360672 231
charlesmn 0:3ac96e360672 232 int16_t nvm_default__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn 0:3ac96e360672 233
charlesmn 0:3ac96e360672 234 uint8_t global_crosstalk_compensation_enable;
charlesmn 0:3ac96e360672 235
charlesmn 0:3ac96e360672 236 int16_t histogram_mode_crosstalk_margin_kcps;
charlesmn 0:3ac96e360672 237
charlesmn 0:3ac96e360672 238 int16_t lite_mode_crosstalk_margin_kcps;
charlesmn 0:3ac96e360672 239
charlesmn 0:3ac96e360672 240 uint8_t crosstalk_range_ignore_threshold_mult;
charlesmn 0:3ac96e360672 241
charlesmn 0:3ac96e360672 242 uint16_t crosstalk_range_ignore_threshold_rate_mcps;
charlesmn 0:3ac96e360672 243
charlesmn 0:3ac96e360672 244 int16_t algo__crosstalk_detect_min_valid_range_mm;
charlesmn 0:3ac96e360672 245
charlesmn 0:3ac96e360672 246 int16_t algo__crosstalk_detect_max_valid_range_mm;
charlesmn 0:3ac96e360672 247
charlesmn 0:3ac96e360672 248 uint16_t algo__crosstalk_detect_max_valid_rate_kcps;
charlesmn 0:3ac96e360672 249
charlesmn 0:3ac96e360672 250 uint16_t algo__crosstalk_detect_max_sigma_mm;
charlesmn 0:3ac96e360672 251
charlesmn 0:3ac96e360672 252
charlesmn 0:3ac96e360672 253
charlesmn 0:3ac96e360672 254 } VL53L1_xtalk_config_t;
charlesmn 0:3ac96e360672 255
charlesmn 0:3ac96e360672 256
charlesmn 0:3ac96e360672 257
charlesmn 0:3ac96e360672 258
charlesmn 0:3ac96e360672 259 typedef struct {
charlesmn 0:3ac96e360672 260
charlesmn 0:3ac96e360672 261
charlesmn 0:3ac96e360672 262 uint16_t tp_tuning_parm_version;
charlesmn 0:3ac96e360672 263
charlesmn 0:3ac96e360672 264 uint16_t tp_tuning_parm_key_table_version;
charlesmn 0:3ac96e360672 265
charlesmn 0:3ac96e360672 266 uint16_t tp_tuning_parm_lld_version;
charlesmn 0:3ac96e360672 267
charlesmn 0:3ac96e360672 268 uint8_t tp_init_phase_rtn_lite_long;
charlesmn 0:3ac96e360672 269
charlesmn 0:3ac96e360672 270 uint8_t tp_init_phase_rtn_lite_med;
charlesmn 0:3ac96e360672 271
charlesmn 0:3ac96e360672 272 uint8_t tp_init_phase_rtn_lite_short;
charlesmn 0:3ac96e360672 273
charlesmn 0:3ac96e360672 274 uint8_t tp_init_phase_ref_lite_long;
charlesmn 0:3ac96e360672 275
charlesmn 0:3ac96e360672 276 uint8_t tp_init_phase_ref_lite_med;
charlesmn 0:3ac96e360672 277
charlesmn 0:3ac96e360672 278 uint8_t tp_init_phase_ref_lite_short;
charlesmn 0:3ac96e360672 279
charlesmn 0:3ac96e360672 280
charlesmn 0:3ac96e360672 281 uint8_t tp_init_phase_rtn_hist_long;
charlesmn 0:3ac96e360672 282
charlesmn 0:3ac96e360672 283 uint8_t tp_init_phase_rtn_hist_med;
charlesmn 0:3ac96e360672 284
charlesmn 0:3ac96e360672 285 uint8_t tp_init_phase_rtn_hist_short;
charlesmn 0:3ac96e360672 286
charlesmn 0:3ac96e360672 287 uint8_t tp_init_phase_ref_hist_long;
charlesmn 0:3ac96e360672 288
charlesmn 0:3ac96e360672 289 uint8_t tp_init_phase_ref_hist_med;
charlesmn 0:3ac96e360672 290
charlesmn 0:3ac96e360672 291 uint8_t tp_init_phase_ref_hist_short;
charlesmn 0:3ac96e360672 292
charlesmn 0:3ac96e360672 293
charlesmn 0:3ac96e360672 294 uint8_t tp_consistency_lite_phase_tolerance;
charlesmn 0:3ac96e360672 295
charlesmn 0:3ac96e360672 296 uint8_t tp_phasecal_target;
charlesmn 0:3ac96e360672 297
charlesmn 0:3ac96e360672 298 uint16_t tp_cal_repeat_rate;
charlesmn 0:3ac96e360672 299
charlesmn 0:3ac96e360672 300 uint8_t tp_lite_min_clip;
charlesmn 0:3ac96e360672 301
charlesmn 0:3ac96e360672 302
charlesmn 0:3ac96e360672 303 uint16_t tp_lite_long_sigma_thresh_mm;
charlesmn 0:3ac96e360672 304
charlesmn 0:3ac96e360672 305 uint16_t tp_lite_med_sigma_thresh_mm;
charlesmn 0:3ac96e360672 306
charlesmn 0:3ac96e360672 307 uint16_t tp_lite_short_sigma_thresh_mm;
charlesmn 0:3ac96e360672 308
charlesmn 0:3ac96e360672 309
charlesmn 0:3ac96e360672 310 uint16_t tp_lite_long_min_count_rate_rtn_mcps;
charlesmn 0:3ac96e360672 311
charlesmn 0:3ac96e360672 312 uint16_t tp_lite_med_min_count_rate_rtn_mcps;
charlesmn 0:3ac96e360672 313
charlesmn 0:3ac96e360672 314 uint16_t tp_lite_short_min_count_rate_rtn_mcps;
charlesmn 0:3ac96e360672 315
charlesmn 0:3ac96e360672 316
charlesmn 0:3ac96e360672 317 uint8_t tp_lite_sigma_est_pulse_width_ns;
charlesmn 0:3ac96e360672 318
charlesmn 0:3ac96e360672 319 uint8_t tp_lite_sigma_est_amb_width_ns;
charlesmn 0:3ac96e360672 320
charlesmn 0:3ac96e360672 321 uint8_t tp_lite_sigma_ref_mm;
charlesmn 0:3ac96e360672 322
charlesmn 0:3ac96e360672 323 uint8_t tp_lite_seed_cfg;
charlesmn 0:3ac96e360672 324
charlesmn 0:3ac96e360672 325 uint8_t tp_timed_seed_cfg;
charlesmn 0:3ac96e360672 326
charlesmn 0:3ac96e360672 327
charlesmn 0:3ac96e360672 328 uint8_t tp_lite_quantifier;
charlesmn 0:3ac96e360672 329
charlesmn 0:3ac96e360672 330 uint8_t tp_lite_first_order_select;
charlesmn 0:3ac96e360672 331
charlesmn 0:3ac96e360672 332
charlesmn 0:3ac96e360672 333 uint16_t tp_dss_target_lite_mcps;
charlesmn 0:3ac96e360672 334
charlesmn 0:3ac96e360672 335 uint16_t tp_dss_target_histo_mcps;
charlesmn 0:3ac96e360672 336
charlesmn 0:3ac96e360672 337 uint16_t tp_dss_target_histo_mz_mcps;
charlesmn 0:3ac96e360672 338
charlesmn 0:3ac96e360672 339 uint16_t tp_dss_target_timed_mcps;
charlesmn 0:3ac96e360672 340
charlesmn 0:3ac96e360672 341 uint16_t tp_dss_target_very_short_mcps;
charlesmn 0:3ac96e360672 342
charlesmn 0:3ac96e360672 343
charlesmn 0:3ac96e360672 344 uint32_t tp_phasecal_timeout_lite_us;
charlesmn 0:3ac96e360672 345
charlesmn 0:3ac96e360672 346 uint32_t tp_phasecal_timeout_hist_long_us;
charlesmn 0:3ac96e360672 347
charlesmn 0:3ac96e360672 348 uint32_t tp_phasecal_timeout_hist_med_us;
charlesmn 0:3ac96e360672 349
charlesmn 0:3ac96e360672 350 uint32_t tp_phasecal_timeout_hist_short_us;
charlesmn 0:3ac96e360672 351
charlesmn 0:3ac96e360672 352
charlesmn 0:3ac96e360672 353 uint32_t tp_phasecal_timeout_mz_long_us;
charlesmn 0:3ac96e360672 354
charlesmn 0:3ac96e360672 355 uint32_t tp_phasecal_timeout_mz_med_us;
charlesmn 0:3ac96e360672 356
charlesmn 0:3ac96e360672 357 uint32_t tp_phasecal_timeout_mz_short_us;
charlesmn 0:3ac96e360672 358
charlesmn 0:3ac96e360672 359 uint32_t tp_phasecal_timeout_timed_us;
charlesmn 0:3ac96e360672 360
charlesmn 0:3ac96e360672 361
charlesmn 0:3ac96e360672 362 uint32_t tp_mm_timeout_lite_us;
charlesmn 0:3ac96e360672 363
charlesmn 0:3ac96e360672 364 uint32_t tp_mm_timeout_histo_us;
charlesmn 0:3ac96e360672 365
charlesmn 0:3ac96e360672 366 uint32_t tp_mm_timeout_mz_us;
charlesmn 0:3ac96e360672 367
charlesmn 0:3ac96e360672 368 uint32_t tp_mm_timeout_timed_us;
charlesmn 0:3ac96e360672 369
charlesmn 0:3ac96e360672 370 uint32_t tp_mm_timeout_lpa_us;
charlesmn 0:3ac96e360672 371
charlesmn 0:3ac96e360672 372
charlesmn 0:3ac96e360672 373 uint32_t tp_range_timeout_lite_us;
charlesmn 0:3ac96e360672 374
charlesmn 0:3ac96e360672 375 uint32_t tp_range_timeout_histo_us;
charlesmn 0:3ac96e360672 376
charlesmn 0:3ac96e360672 377 uint32_t tp_range_timeout_mz_us;
charlesmn 0:3ac96e360672 378
charlesmn 0:3ac96e360672 379 uint32_t tp_range_timeout_timed_us;
charlesmn 0:3ac96e360672 380
charlesmn 0:3ac96e360672 381 uint32_t tp_range_timeout_lpa_us;
charlesmn 0:3ac96e360672 382
charlesmn 0:3ac96e360672 383 uint32_t tp_phasecal_patch_power;
charlesmn 0:3ac96e360672 384
charlesmn 0:3ac96e360672 385 uint8_t tp_hist_merge;
charlesmn 0:3ac96e360672 386
charlesmn 0:3ac96e360672 387 uint32_t tp_reset_merge_threshold;
charlesmn 0:3ac96e360672 388
charlesmn 0:3ac96e360672 389 uint8_t tp_hist_merge_max_size;
charlesmn 0:3ac96e360672 390
charlesmn 0:3ac96e360672 391 uint8_t tp_uwr_enable;
charlesmn 0:3ac96e360672 392 int16_t tp_uwr_med_z_1_min;
charlesmn 0:3ac96e360672 393 int16_t tp_uwr_med_z_1_max;
charlesmn 0:3ac96e360672 394 int16_t tp_uwr_med_z_2_min;
charlesmn 0:3ac96e360672 395 int16_t tp_uwr_med_z_2_max;
charlesmn 0:3ac96e360672 396 int16_t tp_uwr_med_z_3_min;
charlesmn 0:3ac96e360672 397 int16_t tp_uwr_med_z_3_max;
charlesmn 0:3ac96e360672 398 int16_t tp_uwr_med_z_4_min;
charlesmn 0:3ac96e360672 399 int16_t tp_uwr_med_z_4_max;
charlesmn 0:3ac96e360672 400 int16_t tp_uwr_med_z_5_min;
charlesmn 0:3ac96e360672 401 int16_t tp_uwr_med_z_5_max;
charlesmn 0:3ac96e360672 402 int16_t tp_uwr_med_z_6_min;
charlesmn 0:3ac96e360672 403 int16_t tp_uwr_med_z_6_max;
charlesmn 0:3ac96e360672 404 int16_t tp_uwr_med_corr_z_1_rangea;
charlesmn 0:3ac96e360672 405 int16_t tp_uwr_med_corr_z_1_rangeb;
charlesmn 0:3ac96e360672 406 int16_t tp_uwr_med_corr_z_2_rangea;
charlesmn 0:3ac96e360672 407 int16_t tp_uwr_med_corr_z_2_rangeb;
charlesmn 0:3ac96e360672 408 int16_t tp_uwr_med_corr_z_3_rangea;
charlesmn 0:3ac96e360672 409 int16_t tp_uwr_med_corr_z_3_rangeb;
charlesmn 0:3ac96e360672 410 int16_t tp_uwr_med_corr_z_4_rangea;
charlesmn 0:3ac96e360672 411 int16_t tp_uwr_med_corr_z_4_rangeb;
charlesmn 0:3ac96e360672 412 int16_t tp_uwr_med_corr_z_5_rangea;
charlesmn 0:3ac96e360672 413 int16_t tp_uwr_med_corr_z_5_rangeb;
charlesmn 0:3ac96e360672 414 int16_t tp_uwr_med_corr_z_6_rangea;
charlesmn 0:3ac96e360672 415 int16_t tp_uwr_med_corr_z_6_rangeb;
charlesmn 0:3ac96e360672 416 int16_t tp_uwr_lng_z_1_min;
charlesmn 0:3ac96e360672 417 int16_t tp_uwr_lng_z_1_max;
charlesmn 0:3ac96e360672 418 int16_t tp_uwr_lng_z_2_min;
charlesmn 0:3ac96e360672 419 int16_t tp_uwr_lng_z_2_max;
charlesmn 0:3ac96e360672 420 int16_t tp_uwr_lng_z_3_min;
charlesmn 0:3ac96e360672 421 int16_t tp_uwr_lng_z_3_max;
charlesmn 0:3ac96e360672 422 int16_t tp_uwr_lng_z_4_min;
charlesmn 0:3ac96e360672 423 int16_t tp_uwr_lng_z_4_max;
charlesmn 0:3ac96e360672 424 int16_t tp_uwr_lng_z_5_min;
charlesmn 0:3ac96e360672 425 int16_t tp_uwr_lng_z_5_max;
charlesmn 0:3ac96e360672 426 int16_t tp_uwr_lng_corr_z_1_rangea;
charlesmn 0:3ac96e360672 427 int16_t tp_uwr_lng_corr_z_1_rangeb;
charlesmn 0:3ac96e360672 428 int16_t tp_uwr_lng_corr_z_2_rangea;
charlesmn 0:3ac96e360672 429 int16_t tp_uwr_lng_corr_z_2_rangeb;
charlesmn 0:3ac96e360672 430 int16_t tp_uwr_lng_corr_z_3_rangea;
charlesmn 0:3ac96e360672 431 int16_t tp_uwr_lng_corr_z_3_rangeb;
charlesmn 0:3ac96e360672 432 int16_t tp_uwr_lng_corr_z_4_rangea;
charlesmn 0:3ac96e360672 433 int16_t tp_uwr_lng_corr_z_4_rangeb;
charlesmn 0:3ac96e360672 434 int16_t tp_uwr_lng_corr_z_5_rangea;
charlesmn 0:3ac96e360672 435 int16_t tp_uwr_lng_corr_z_5_rangeb;
charlesmn 0:3ac96e360672 436
charlesmn 0:3ac96e360672 437 } VL53L1_tuning_parm_storage_t;
charlesmn 0:3ac96e360672 438
charlesmn 0:3ac96e360672 439
charlesmn 0:3ac96e360672 440
charlesmn 0:3ac96e360672 441
charlesmn 0:3ac96e360672 442
charlesmn 0:3ac96e360672 443 typedef struct {
charlesmn 0:3ac96e360672 444
charlesmn 0:3ac96e360672 445 uint8_t x_centre;
charlesmn 0:3ac96e360672 446 uint8_t y_centre;
charlesmn 0:3ac96e360672 447
charlesmn 0:3ac96e360672 448 } VL53L1_optical_centre_t;
charlesmn 0:3ac96e360672 449
charlesmn 0:3ac96e360672 450
charlesmn 0:3ac96e360672 451
charlesmn 0:3ac96e360672 452
charlesmn 0:3ac96e360672 453 typedef struct {
charlesmn 0:3ac96e360672 454
charlesmn 0:3ac96e360672 455 uint8_t x_centre;
charlesmn 0:3ac96e360672 456 uint8_t y_centre;
charlesmn 0:3ac96e360672 457 uint8_t width;
charlesmn 0:3ac96e360672 458 uint8_t height;
charlesmn 0:3ac96e360672 459
charlesmn 0:3ac96e360672 460 } VL53L1_user_zone_t;
charlesmn 0:3ac96e360672 461
charlesmn 0:3ac96e360672 462
charlesmn 0:3ac96e360672 463
charlesmn 0:3ac96e360672 464
charlesmn 0:3ac96e360672 465 typedef struct {
charlesmn 0:3ac96e360672 466
charlesmn 0:3ac96e360672 467 uint8_t max_zones;
charlesmn 0:3ac96e360672 468 uint8_t active_zones;
charlesmn 0:3ac96e360672 469
charlesmn 0:3ac96e360672 470
charlesmn 0:3ac96e360672 471
charlesmn 0:3ac96e360672 472 VL53L1_histogram_config_t multizone_hist_cfg;
charlesmn 0:3ac96e360672 473
charlesmn 0:3ac96e360672 474 VL53L1_user_zone_t user_zones[VL53L1_MAX_USER_ZONES];
charlesmn 0:3ac96e360672 475
charlesmn 0:3ac96e360672 476
charlesmn 0:3ac96e360672 477 uint8_t bin_config[VL53L1_MAX_USER_ZONES];
charlesmn 0:3ac96e360672 478
charlesmn 0:3ac96e360672 479
charlesmn 0:3ac96e360672 480 } VL53L1_zone_config_t;
charlesmn 0:3ac96e360672 481
charlesmn 0:3ac96e360672 482
charlesmn 0:3ac96e360672 483
charlesmn 0:3ac96e360672 484 typedef struct {
charlesmn 0:3ac96e360672 485
charlesmn 0:3ac96e360672 486
charlesmn 0:3ac96e360672 487 VL53L1_GPIO_Interrupt_Mode intr_mode_distance;
charlesmn 0:3ac96e360672 488
charlesmn 0:3ac96e360672 489
charlesmn 0:3ac96e360672 490 VL53L1_GPIO_Interrupt_Mode intr_mode_rate;
charlesmn 0:3ac96e360672 491
charlesmn 0:3ac96e360672 492
charlesmn 0:3ac96e360672 493 uint8_t intr_new_measure_ready;
charlesmn 0:3ac96e360672 494
charlesmn 0:3ac96e360672 495
charlesmn 0:3ac96e360672 496 uint8_t intr_no_target;
charlesmn 0:3ac96e360672 497
charlesmn 0:3ac96e360672 498
charlesmn 0:3ac96e360672 499 uint8_t intr_combined_mode;
charlesmn 0:3ac96e360672 500
charlesmn 0:3ac96e360672 501
charlesmn 0:3ac96e360672 502
charlesmn 0:3ac96e360672 503
charlesmn 0:3ac96e360672 504
charlesmn 0:3ac96e360672 505 uint16_t threshold_distance_high;
charlesmn 0:3ac96e360672 506
charlesmn 0:3ac96e360672 507
charlesmn 0:3ac96e360672 508 uint16_t threshold_distance_low;
charlesmn 0:3ac96e360672 509
charlesmn 0:3ac96e360672 510
charlesmn 0:3ac96e360672 511 uint16_t threshold_rate_high;
charlesmn 0:3ac96e360672 512
charlesmn 0:3ac96e360672 513
charlesmn 0:3ac96e360672 514 uint16_t threshold_rate_low;
charlesmn 0:3ac96e360672 515
charlesmn 0:3ac96e360672 516 } VL53L1_GPIO_interrupt_config_t;
charlesmn 0:3ac96e360672 517
charlesmn 0:3ac96e360672 518
charlesmn 0:3ac96e360672 519
charlesmn 0:3ac96e360672 520
charlesmn 0:3ac96e360672 521 typedef struct {
charlesmn 0:3ac96e360672 522
charlesmn 0:3ac96e360672 523
charlesmn 0:3ac96e360672 524 uint8_t vhv_loop_bound;
charlesmn 0:3ac96e360672 525
charlesmn 0:3ac96e360672 526
charlesmn 0:3ac96e360672 527 uint8_t is_low_power_auto_mode;
charlesmn 0:3ac96e360672 528
charlesmn 0:3ac96e360672 529
charlesmn 0:3ac96e360672 530 uint8_t low_power_auto_range_count;
charlesmn 0:3ac96e360672 531
charlesmn 0:3ac96e360672 532
charlesmn 0:3ac96e360672 533 uint8_t saved_interrupt_config;
charlesmn 0:3ac96e360672 534
charlesmn 0:3ac96e360672 535
charlesmn 0:3ac96e360672 536 uint8_t saved_vhv_init;
charlesmn 0:3ac96e360672 537
charlesmn 0:3ac96e360672 538
charlesmn 0:3ac96e360672 539 uint8_t saved_vhv_timeout;
charlesmn 0:3ac96e360672 540
charlesmn 0:3ac96e360672 541
charlesmn 0:3ac96e360672 542 uint8_t first_run_phasecal_result;
charlesmn 0:3ac96e360672 543
charlesmn 0:3ac96e360672 544
charlesmn 0:3ac96e360672 545 uint32_t dss__total_rate_per_spad_mcps;
charlesmn 0:3ac96e360672 546
charlesmn 0:3ac96e360672 547
charlesmn 0:3ac96e360672 548 uint16_t dss__required_spads;
charlesmn 0:3ac96e360672 549
charlesmn 0:3ac96e360672 550 } VL53L1_low_power_auto_data_t;
charlesmn 0:3ac96e360672 551
charlesmn 0:3ac96e360672 552
charlesmn 0:3ac96e360672 553
charlesmn 0:3ac96e360672 554
charlesmn 0:3ac96e360672 555
charlesmn 0:3ac96e360672 556
charlesmn 0:3ac96e360672 557
charlesmn 0:3ac96e360672 558 typedef struct {
charlesmn 0:3ac96e360672 559
charlesmn 0:3ac96e360672 560
charlesmn 0:3ac96e360672 561 uint8_t smudge_corr_enabled;
charlesmn 0:3ac96e360672 562
charlesmn 0:3ac96e360672 563
charlesmn 0:3ac96e360672 564 uint8_t smudge_corr_apply_enabled;
charlesmn 0:3ac96e360672 565
charlesmn 0:3ac96e360672 566
charlesmn 0:3ac96e360672 567 uint8_t smudge_corr_single_apply;
charlesmn 0:3ac96e360672 568
charlesmn 0:3ac96e360672 569
charlesmn 0:3ac96e360672 570
charlesmn 0:3ac96e360672 571
charlesmn 0:3ac96e360672 572 uint16_t smudge_margin;
charlesmn 0:3ac96e360672 573
charlesmn 0:3ac96e360672 574
charlesmn 0:3ac96e360672 575 uint32_t noise_margin;
charlesmn 0:3ac96e360672 576
charlesmn 0:3ac96e360672 577
charlesmn 0:3ac96e360672 578 uint32_t user_xtalk_offset_limit;
charlesmn 0:3ac96e360672 579
charlesmn 0:3ac96e360672 580
charlesmn 0:3ac96e360672 581 uint8_t user_xtalk_offset_limit_hi;
charlesmn 0:3ac96e360672 582
charlesmn 0:3ac96e360672 583
charlesmn 0:3ac96e360672 584 uint32_t sample_limit;
charlesmn 0:3ac96e360672 585
charlesmn 0:3ac96e360672 586
charlesmn 0:3ac96e360672 587 uint32_t single_xtalk_delta;
charlesmn 0:3ac96e360672 588
charlesmn 0:3ac96e360672 589
charlesmn 0:3ac96e360672 590 uint32_t averaged_xtalk_delta;
charlesmn 0:3ac96e360672 591
charlesmn 0:3ac96e360672 592
charlesmn 0:3ac96e360672 593 uint32_t smudge_corr_clip_limit;
charlesmn 0:3ac96e360672 594
charlesmn 0:3ac96e360672 595
charlesmn 0:3ac96e360672 596 uint32_t smudge_corr_ambient_threshold;
charlesmn 0:3ac96e360672 597
charlesmn 0:3ac96e360672 598
charlesmn 0:3ac96e360672 599 uint8_t scaler_calc_method;
charlesmn 0:3ac96e360672 600
charlesmn 0:3ac96e360672 601
charlesmn 0:3ac96e360672 602 int16_t x_gradient_scaler;
charlesmn 0:3ac96e360672 603
charlesmn 0:3ac96e360672 604
charlesmn 0:3ac96e360672 605 int16_t y_gradient_scaler;
charlesmn 0:3ac96e360672 606
charlesmn 0:3ac96e360672 607
charlesmn 0:3ac96e360672 608 uint8_t user_scaler_set;
charlesmn 0:3ac96e360672 609
charlesmn 0:3ac96e360672 610
charlesmn 0:3ac96e360672 611 uint32_t nodetect_ambient_threshold;
charlesmn 0:3ac96e360672 612
charlesmn 0:3ac96e360672 613
charlesmn 0:3ac96e360672 614 uint32_t nodetect_sample_limit;
charlesmn 0:3ac96e360672 615
charlesmn 0:3ac96e360672 616
charlesmn 0:3ac96e360672 617 uint32_t nodetect_xtalk_offset;
charlesmn 0:3ac96e360672 618
charlesmn 0:3ac96e360672 619
charlesmn 0:3ac96e360672 620 uint16_t nodetect_min_range_mm;
charlesmn 0:3ac96e360672 621
charlesmn 0:3ac96e360672 622
charlesmn 0:3ac96e360672 623 uint32_t max_smudge_factor;
charlesmn 0:3ac96e360672 624
charlesmn 0:3ac96e360672 625 } VL53L1_smudge_corrector_config_t;
charlesmn 0:3ac96e360672 626
charlesmn 0:3ac96e360672 627
charlesmn 0:3ac96e360672 628
charlesmn 0:3ac96e360672 629 typedef struct {
charlesmn 0:3ac96e360672 630
charlesmn 0:3ac96e360672 631
charlesmn 0:3ac96e360672 632 uint32_t current_samples;
charlesmn 0:3ac96e360672 633
charlesmn 0:3ac96e360672 634
charlesmn 0:3ac96e360672 635 uint32_t required_samples;
charlesmn 0:3ac96e360672 636
charlesmn 0:3ac96e360672 637
charlesmn 0:3ac96e360672 638 uint64_t accumulator;
charlesmn 0:3ac96e360672 639
charlesmn 0:3ac96e360672 640
charlesmn 0:3ac96e360672 641 uint32_t nodetect_counter;
charlesmn 0:3ac96e360672 642
charlesmn 0:3ac96e360672 643 } VL53L1_smudge_corrector_internals_t;
charlesmn 0:3ac96e360672 644
charlesmn 0:3ac96e360672 645
charlesmn 0:3ac96e360672 646
charlesmn 0:3ac96e360672 647 typedef struct {
charlesmn 0:3ac96e360672 648
charlesmn 0:3ac96e360672 649
charlesmn 0:3ac96e360672 650 uint8_t smudge_corr_valid;
charlesmn 0:3ac96e360672 651
charlesmn 0:3ac96e360672 652
charlesmn 0:3ac96e360672 653 uint8_t smudge_corr_clipped;
charlesmn 0:3ac96e360672 654
charlesmn 0:3ac96e360672 655
charlesmn 0:3ac96e360672 656 uint8_t single_xtalk_delta_flag;
charlesmn 0:3ac96e360672 657
charlesmn 0:3ac96e360672 658
charlesmn 0:3ac96e360672 659 uint8_t averaged_xtalk_delta_flag;
charlesmn 0:3ac96e360672 660
charlesmn 0:3ac96e360672 661
charlesmn 0:3ac96e360672 662 uint8_t sample_limit_exceeded_flag;
charlesmn 0:3ac96e360672 663
charlesmn 0:3ac96e360672 664
charlesmn 0:3ac96e360672 665 uint8_t gradient_zero_flag;
charlesmn 0:3ac96e360672 666
charlesmn 0:3ac96e360672 667
charlesmn 0:3ac96e360672 668 uint8_t new_xtalk_applied_flag;
charlesmn 0:3ac96e360672 669
charlesmn 0:3ac96e360672 670
charlesmn 0:3ac96e360672 671 uint32_t algo__crosstalk_compensation_plane_offset_kcps;
charlesmn 0:3ac96e360672 672
charlesmn 0:3ac96e360672 673
charlesmn 0:3ac96e360672 674 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn 0:3ac96e360672 675
charlesmn 0:3ac96e360672 676
charlesmn 0:3ac96e360672 677 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn 0:3ac96e360672 678
charlesmn 0:3ac96e360672 679
charlesmn 0:3ac96e360672 680 } VL53L1_smudge_corrector_data_t;
charlesmn 0:3ac96e360672 681
charlesmn 0:3ac96e360672 682
charlesmn 0:3ac96e360672 683
charlesmn 0:3ac96e360672 684
charlesmn 0:3ac96e360672 685
charlesmn 0:3ac96e360672 686 typedef struct {
charlesmn 0:3ac96e360672 687
charlesmn 0:3ac96e360672 688
charlesmn 0:3ac96e360672 689
charlesmn 0:3ac96e360672 690 uint8_t range_id;
charlesmn 0:3ac96e360672 691
charlesmn 0:3ac96e360672 692 uint32_t time_stamp;
charlesmn 0:3ac96e360672 693
charlesmn 0:3ac96e360672 694 uint8_t VL53L1_p_015;
charlesmn 0:3ac96e360672 695
charlesmn 0:3ac96e360672 696 uint8_t VL53L1_p_022;
charlesmn 0:3ac96e360672 697
charlesmn 0:3ac96e360672 698 uint8_t VL53L1_p_025;
charlesmn 0:3ac96e360672 699
charlesmn 0:3ac96e360672 700 uint8_t VL53L1_p_026;
charlesmn 0:3ac96e360672 701
charlesmn 0:3ac96e360672 702 uint8_t VL53L1_p_016;
charlesmn 0:3ac96e360672 703
charlesmn 0:3ac96e360672 704 uint8_t VL53L1_p_027;
charlesmn 0:3ac96e360672 705
charlesmn 0:3ac96e360672 706
charlesmn 0:3ac96e360672 707 uint16_t width;
charlesmn 0:3ac96e360672 708
charlesmn 0:3ac96e360672 709 uint8_t VL53L1_p_030;
charlesmn 0:3ac96e360672 710
charlesmn 0:3ac96e360672 711
charlesmn 0:3ac96e360672 712 uint16_t fast_osc_frequency;
charlesmn 0:3ac96e360672 713
charlesmn 0:3ac96e360672 714 uint16_t zero_distance_phase;
charlesmn 0:3ac96e360672 715
charlesmn 0:3ac96e360672 716 uint16_t VL53L1_p_006;
charlesmn 0:3ac96e360672 717
charlesmn 0:3ac96e360672 718
charlesmn 0:3ac96e360672 719 uint32_t total_periods_elapsed;
charlesmn 0:3ac96e360672 720
charlesmn 0:3ac96e360672 721
charlesmn 0:3ac96e360672 722 uint32_t peak_duration_us;
charlesmn 0:3ac96e360672 723
charlesmn 0:3ac96e360672 724
charlesmn 0:3ac96e360672 725 uint32_t woi_duration_us;
charlesmn 0:3ac96e360672 726
charlesmn 0:3ac96e360672 727
charlesmn 0:3ac96e360672 728
charlesmn 0:3ac96e360672 729
charlesmn 0:3ac96e360672 730
charlesmn 0:3ac96e360672 731 uint32_t VL53L1_p_020;
charlesmn 0:3ac96e360672 732
charlesmn 0:3ac96e360672 733 uint32_t VL53L1_p_021;
charlesmn 0:3ac96e360672 734
charlesmn 0:3ac96e360672 735 int32_t VL53L1_p_013;
charlesmn 0:3ac96e360672 736
charlesmn 0:3ac96e360672 737
charlesmn 0:3ac96e360672 738
charlesmn 0:3ac96e360672 739
charlesmn 0:3ac96e360672 740 uint16_t peak_signal_count_rate_mcps;
charlesmn 0:3ac96e360672 741
charlesmn 0:3ac96e360672 742 uint16_t avg_signal_count_rate_mcps;
charlesmn 0:3ac96e360672 743
charlesmn 0:3ac96e360672 744 uint16_t ambient_count_rate_mcps;
charlesmn 0:3ac96e360672 745
charlesmn 0:3ac96e360672 746 uint16_t total_rate_per_spad_mcps;
charlesmn 0:3ac96e360672 747
charlesmn 0:3ac96e360672 748 uint32_t VL53L1_p_012;
charlesmn 0:3ac96e360672 749
charlesmn 0:3ac96e360672 750
charlesmn 0:3ac96e360672 751
charlesmn 0:3ac96e360672 752
charlesmn 0:3ac96e360672 753 uint16_t VL53L1_p_005;
charlesmn 0:3ac96e360672 754
charlesmn 0:3ac96e360672 755
charlesmn 0:3ac96e360672 756
charlesmn 0:3ac96e360672 757
charlesmn 0:3ac96e360672 758 uint16_t VL53L1_p_028;
charlesmn 0:3ac96e360672 759
charlesmn 0:3ac96e360672 760 uint16_t VL53L1_p_014;
charlesmn 0:3ac96e360672 761
charlesmn 0:3ac96e360672 762 uint16_t VL53L1_p_029;
charlesmn 0:3ac96e360672 763
charlesmn 0:3ac96e360672 764
charlesmn 0:3ac96e360672 765
charlesmn 0:3ac96e360672 766
charlesmn 0:3ac96e360672 767 int16_t min_range_mm;
charlesmn 0:3ac96e360672 768
charlesmn 0:3ac96e360672 769 int16_t median_range_mm;
charlesmn 0:3ac96e360672 770
charlesmn 0:3ac96e360672 771 int16_t max_range_mm;
charlesmn 0:3ac96e360672 772
charlesmn 0:3ac96e360672 773
charlesmn 0:3ac96e360672 774
charlesmn 0:3ac96e360672 775
charlesmn 0:3ac96e360672 776 uint8_t range_status;
charlesmn 0:3ac96e360672 777
charlesmn 0:3ac96e360672 778 } VL53L1_range_data_t;
charlesmn 0:3ac96e360672 779
charlesmn 0:3ac96e360672 780
charlesmn 0:3ac96e360672 781
charlesmn 0:3ac96e360672 782
charlesmn 0:3ac96e360672 783 typedef struct {
charlesmn 0:3ac96e360672 784
charlesmn 0:3ac96e360672 785 VL53L1_DeviceState cfg_device_state;
charlesmn 0:3ac96e360672 786
charlesmn 0:3ac96e360672 787 VL53L1_DeviceState rd_device_state;
charlesmn 0:3ac96e360672 788
charlesmn 0:3ac96e360672 789 uint8_t zone_id;
charlesmn 0:3ac96e360672 790
charlesmn 0:3ac96e360672 791 uint8_t stream_count;
charlesmn 0:3ac96e360672 792
charlesmn 0:3ac96e360672 793
charlesmn 0:3ac96e360672 794 int16_t VL53L1_p_007[VL53L1_MAX_AMBIENT_DMAX_VALUES];
charlesmn 0:3ac96e360672 795
charlesmn 0:3ac96e360672 796 int16_t wrap_dmax_mm;
charlesmn 0:3ac96e360672 797
charlesmn 0:3ac96e360672 798
charlesmn 0:3ac96e360672 799 uint8_t device_status;
charlesmn 0:3ac96e360672 800
charlesmn 0:3ac96e360672 801
charlesmn 0:3ac96e360672 802 uint8_t max_results;
charlesmn 0:3ac96e360672 803
charlesmn 0:3ac96e360672 804 uint8_t active_results;
charlesmn 0:3ac96e360672 805
charlesmn 0:3ac96e360672 806 VL53L1_range_data_t VL53L1_p_002[VL53L1_MAX_RANGE_RESULTS];
charlesmn 0:3ac96e360672 807
charlesmn 0:3ac96e360672 808 VL53L1_range_data_t xmonitor;
charlesmn 0:3ac96e360672 809
charlesmn 0:3ac96e360672 810 VL53L1_smudge_corrector_data_t smudge_corrector_data;
charlesmn 0:3ac96e360672 811
charlesmn 0:3ac96e360672 812
charlesmn 0:3ac96e360672 813
charlesmn 0:3ac96e360672 814 } VL53L1_range_results_t;
charlesmn 0:3ac96e360672 815
charlesmn 0:3ac96e360672 816
charlesmn 0:3ac96e360672 817
charlesmn 0:3ac96e360672 818
charlesmn 0:3ac96e360672 819 typedef struct {
charlesmn 0:3ac96e360672 820
charlesmn 0:3ac96e360672 821 uint8_t no_of_samples;
charlesmn 0:3ac96e360672 822
charlesmn 0:3ac96e360672 823 uint32_t rate_per_spad_kcps_sum;
charlesmn 0:3ac96e360672 824
charlesmn 0:3ac96e360672 825 uint32_t rate_per_spad_kcps_avg;
charlesmn 0:3ac96e360672 826
charlesmn 0:3ac96e360672 827 int32_t signal_total_events_sum;
charlesmn 0:3ac96e360672 828
charlesmn 0:3ac96e360672 829 int32_t signal_total_events_avg;
charlesmn 0:3ac96e360672 830
charlesmn 0:3ac96e360672 831 uint32_t sigma_mm_sum;
charlesmn 0:3ac96e360672 832
charlesmn 0:3ac96e360672 833 uint32_t sigma_mm_avg;
charlesmn 0:3ac96e360672 834
charlesmn 0:3ac96e360672 835 uint32_t median_phase_sum;
charlesmn 0:3ac96e360672 836
charlesmn 0:3ac96e360672 837 uint32_t median_phase_avg;
charlesmn 0:3ac96e360672 838
charlesmn 0:3ac96e360672 839
charlesmn 0:3ac96e360672 840 } VL53L1_xtalk_range_data_t;
charlesmn 0:3ac96e360672 841
charlesmn 0:3ac96e360672 842
charlesmn 0:3ac96e360672 843
charlesmn 0:3ac96e360672 844
charlesmn 0:3ac96e360672 845 typedef struct {
charlesmn 0:3ac96e360672 846
charlesmn 0:3ac96e360672 847 VL53L1_Error cal_status;
charlesmn 0:3ac96e360672 848
charlesmn 0:3ac96e360672 849 uint8_t num_of_samples_status;
charlesmn 0:3ac96e360672 850
charlesmn 0:3ac96e360672 851 uint8_t zero_samples_status;
charlesmn 0:3ac96e360672 852
charlesmn 0:3ac96e360672 853 uint8_t max_sigma_status;
charlesmn 0:3ac96e360672 854
charlesmn 0:3ac96e360672 855 uint8_t max_results;
charlesmn 0:3ac96e360672 856
charlesmn 0:3ac96e360672 857 uint8_t active_results;
charlesmn 0:3ac96e360672 858
charlesmn 0:3ac96e360672 859
charlesmn 0:3ac96e360672 860 VL53L1_xtalk_range_data_t
charlesmn 0:3ac96e360672 861 VL53L1_p_002[VL53L1_MAX_XTALK_RANGE_RESULTS];
charlesmn 0:3ac96e360672 862
charlesmn 0:3ac96e360672 863 VL53L1_histogram_bin_data_t central_histogram_sum;
charlesmn 0:3ac96e360672 864
charlesmn 0:3ac96e360672 865 VL53L1_histogram_bin_data_t central_histogram_avg;
charlesmn 0:3ac96e360672 866
charlesmn 0:3ac96e360672 867 uint8_t central_histogram__window_start;
charlesmn 0:3ac96e360672 868
charlesmn 0:3ac96e360672 869 uint8_t central_histogram__window_end;
charlesmn 0:3ac96e360672 870
charlesmn 0:3ac96e360672 871 VL53L1_histogram_bin_data_t
charlesmn 0:3ac96e360672 872 histogram_avg_1[VL53L1_MAX_XTALK_RANGE_RESULTS];
charlesmn 0:3ac96e360672 873
charlesmn 0:3ac96e360672 874 VL53L1_histogram_bin_data_t
charlesmn 0:3ac96e360672 875 histogram_avg_2[VL53L1_MAX_XTALK_RANGE_RESULTS];
charlesmn 0:3ac96e360672 876
charlesmn 0:3ac96e360672 877 VL53L1_histogram_bin_data_t
charlesmn 0:3ac96e360672 878 xtalk_avg[VL53L1_MAX_XTALK_RANGE_RESULTS];
charlesmn 0:3ac96e360672 879
charlesmn 0:3ac96e360672 880
charlesmn 0:3ac96e360672 881 } VL53L1_xtalk_range_results_t;
charlesmn 0:3ac96e360672 882
charlesmn 0:3ac96e360672 883
charlesmn 0:3ac96e360672 884
charlesmn 0:3ac96e360672 885
charlesmn 0:3ac96e360672 886 typedef struct {
charlesmn 0:3ac96e360672 887
charlesmn 0:3ac96e360672 888 uint8_t preset_mode;
charlesmn 0:3ac96e360672 889
charlesmn 0:3ac96e360672 890 uint8_t dss_config__roi_mode_control;
charlesmn 0:3ac96e360672 891
charlesmn 0:3ac96e360672 892 uint16_t dss_config__manual_effective_spads_select;
charlesmn 0:3ac96e360672 893
charlesmn 0:3ac96e360672 894 uint8_t no_of_samples;
charlesmn 0:3ac96e360672 895
charlesmn 0:3ac96e360672 896 uint32_t effective_spads;
charlesmn 0:3ac96e360672 897
charlesmn 0:3ac96e360672 898 uint32_t peak_rate_mcps;
charlesmn 0:3ac96e360672 899
charlesmn 0:3ac96e360672 900 uint32_t VL53L1_p_005;
charlesmn 0:3ac96e360672 901
charlesmn 0:3ac96e360672 902 int32_t median_range_mm;
charlesmn 0:3ac96e360672 903
charlesmn 0:3ac96e360672 904 int32_t range_mm_offset;
charlesmn 0:3ac96e360672 905
charlesmn 0:3ac96e360672 906
charlesmn 0:3ac96e360672 907 } VL53L1_offset_range_data_t;
charlesmn 0:3ac96e360672 908
charlesmn 0:3ac96e360672 909
charlesmn 0:3ac96e360672 910
charlesmn 0:3ac96e360672 911
charlesmn 0:3ac96e360672 912 typedef struct {
charlesmn 0:3ac96e360672 913
charlesmn 0:3ac96e360672 914 int16_t cal_distance_mm;
charlesmn 0:3ac96e360672 915
charlesmn 0:3ac96e360672 916 uint16_t cal_reflectance_pc;
charlesmn 0:3ac96e360672 917
charlesmn 0:3ac96e360672 918 VL53L1_Error cal_status;
charlesmn 0:3ac96e360672 919
charlesmn 0:3ac96e360672 920 uint8_t cal_report;
charlesmn 0:3ac96e360672 921
charlesmn 0:3ac96e360672 922 uint8_t max_results;
charlesmn 0:3ac96e360672 923
charlesmn 0:3ac96e360672 924 uint8_t active_results;
charlesmn 0:3ac96e360672 925
charlesmn 0:3ac96e360672 926 VL53L1_offset_range_data_t
charlesmn 0:3ac96e360672 927 VL53L1_p_002[VL53L1_MAX_OFFSET_RANGE_RESULTS];
charlesmn 0:3ac96e360672 928
charlesmn 0:3ac96e360672 929
charlesmn 0:3ac96e360672 930 } VL53L1_offset_range_results_t;
charlesmn 0:3ac96e360672 931
charlesmn 0:3ac96e360672 932
charlesmn 0:3ac96e360672 933
charlesmn 0:3ac96e360672 934
charlesmn 0:3ac96e360672 935 typedef struct {
charlesmn 0:3ac96e360672 936
charlesmn 0:3ac96e360672 937 uint16_t result__mm_inner_actual_effective_spads;
charlesmn 0:3ac96e360672 938
charlesmn 0:3ac96e360672 939 uint16_t result__mm_outer_actual_effective_spads;
charlesmn 0:3ac96e360672 940
charlesmn 0:3ac96e360672 941 uint16_t result__mm_inner_peak_signal_count_rtn_mcps;
charlesmn 0:3ac96e360672 942
charlesmn 0:3ac96e360672 943 uint16_t result__mm_outer_peak_signal_count_rtn_mcps;
charlesmn 0:3ac96e360672 944
charlesmn 0:3ac96e360672 945
charlesmn 0:3ac96e360672 946 } VL53L1_additional_offset_cal_data_t;
charlesmn 0:3ac96e360672 947
charlesmn 0:3ac96e360672 948
charlesmn 0:3ac96e360672 949
charlesmn 0:3ac96e360672 950 typedef struct {
charlesmn 0:3ac96e360672 951 int16_t short_a_offset_mm;
charlesmn 0:3ac96e360672 952 int16_t short_b_offset_mm;
charlesmn 0:3ac96e360672 953 int16_t medium_a_offset_mm;
charlesmn 0:3ac96e360672 954 int16_t medium_b_offset_mm;
charlesmn 0:3ac96e360672 955 int16_t long_a_offset_mm;
charlesmn 0:3ac96e360672 956 int16_t long_b_offset_mm;
charlesmn 0:3ac96e360672 957 } VL53L1_per_vcsel_period_offset_cal_data_t;
charlesmn 0:3ac96e360672 958
charlesmn 0:3ac96e360672 959
charlesmn 0:3ac96e360672 960
charlesmn 0:3ac96e360672 961
charlesmn 0:3ac96e360672 962
charlesmn 0:3ac96e360672 963 typedef struct {
charlesmn 0:3ac96e360672 964
charlesmn 0:3ac96e360672 965 uint32_t VL53L1_p_020;
charlesmn 0:3ac96e360672 966
charlesmn 0:3ac96e360672 967 uint32_t VL53L1_p_021;
charlesmn 0:3ac96e360672 968
charlesmn 0:3ac96e360672 969 uint16_t VL53L1_p_014;
charlesmn 0:3ac96e360672 970
charlesmn 0:3ac96e360672 971 uint8_t range_status;
charlesmn 0:3ac96e360672 972
charlesmn 0:3ac96e360672 973
charlesmn 0:3ac96e360672 974 } VL53L1_object_data_t;
charlesmn 0:3ac96e360672 975
charlesmn 0:3ac96e360672 976
charlesmn 0:3ac96e360672 977
charlesmn 0:3ac96e360672 978
charlesmn 0:3ac96e360672 979 typedef struct {
charlesmn 0:3ac96e360672 980
charlesmn 0:3ac96e360672 981 VL53L1_DeviceState cfg_device_state;
charlesmn 0:3ac96e360672 982
charlesmn 0:3ac96e360672 983 VL53L1_DeviceState rd_device_state;
charlesmn 0:3ac96e360672 984
charlesmn 0:3ac96e360672 985 uint8_t zone_id;
charlesmn 0:3ac96e360672 986
charlesmn 0:3ac96e360672 987 uint8_t stream_count;
charlesmn 0:3ac96e360672 988
charlesmn 0:3ac96e360672 989 uint8_t max_objects;
charlesmn 0:3ac96e360672 990
charlesmn 0:3ac96e360672 991 uint8_t active_objects;
charlesmn 0:3ac96e360672 992
charlesmn 0:3ac96e360672 993 VL53L1_object_data_t VL53L1_p_002[VL53L1_MAX_RANGE_RESULTS];
charlesmn 0:3ac96e360672 994
charlesmn 0:3ac96e360672 995
charlesmn 0:3ac96e360672 996 VL53L1_object_data_t xmonitor;
charlesmn 0:3ac96e360672 997
charlesmn 0:3ac96e360672 998
charlesmn 0:3ac96e360672 999 } VL53L1_zone_objects_t;
charlesmn 0:3ac96e360672 1000
charlesmn 0:3ac96e360672 1001
charlesmn 0:3ac96e360672 1002
charlesmn 0:3ac96e360672 1003
charlesmn 0:3ac96e360672 1004
charlesmn 0:3ac96e360672 1005
charlesmn 0:3ac96e360672 1006 typedef struct {
charlesmn 0:3ac96e360672 1007
charlesmn 0:3ac96e360672 1008 uint8_t max_zones;
charlesmn 0:3ac96e360672 1009
charlesmn 0:3ac96e360672 1010 uint8_t active_zones;
charlesmn 0:3ac96e360672 1011
charlesmn 0:3ac96e360672 1012 VL53L1_zone_objects_t VL53L1_p_002[VL53L1_MAX_USER_ZONES];
charlesmn 0:3ac96e360672 1013
charlesmn 0:3ac96e360672 1014
charlesmn 0:3ac96e360672 1015 } VL53L1_zone_results_t;
charlesmn 0:3ac96e360672 1016
charlesmn 0:3ac96e360672 1017
charlesmn 0:3ac96e360672 1018
charlesmn 0:3ac96e360672 1019
charlesmn 0:3ac96e360672 1020 typedef struct {
charlesmn 0:3ac96e360672 1021
charlesmn 0:3ac96e360672 1022 VL53L1_DeviceState rd_device_state;
charlesmn 0:3ac96e360672 1023
charlesmn 0:3ac96e360672 1024
charlesmn 0:3ac96e360672 1025 uint8_t number_of_ambient_bins;
charlesmn 0:3ac96e360672 1026
charlesmn 0:3ac96e360672 1027
charlesmn 0:3ac96e360672 1028 uint16_t result__dss_actual_effective_spads;
charlesmn 0:3ac96e360672 1029
charlesmn 0:3ac96e360672 1030 uint8_t VL53L1_p_009;
charlesmn 0:3ac96e360672 1031
charlesmn 0:3ac96e360672 1032 uint32_t total_periods_elapsed;
charlesmn 0:3ac96e360672 1033
charlesmn 0:3ac96e360672 1034
charlesmn 0:3ac96e360672 1035 int32_t ambient_events_sum;
charlesmn 0:3ac96e360672 1036
charlesmn 0:3ac96e360672 1037
charlesmn 0:3ac96e360672 1038 } VL53L1_zone_hist_info_t;
charlesmn 0:3ac96e360672 1039
charlesmn 0:3ac96e360672 1040
charlesmn 0:3ac96e360672 1041
charlesmn 0:3ac96e360672 1042
charlesmn 0:3ac96e360672 1043 typedef struct {
charlesmn 0:3ac96e360672 1044
charlesmn 0:3ac96e360672 1045 uint8_t max_zones;
charlesmn 0:3ac96e360672 1046
charlesmn 0:3ac96e360672 1047 uint8_t active_zones;
charlesmn 0:3ac96e360672 1048
charlesmn 0:3ac96e360672 1049 VL53L1_zone_hist_info_t VL53L1_p_002[VL53L1_MAX_USER_ZONES];
charlesmn 0:3ac96e360672 1050
charlesmn 0:3ac96e360672 1051
charlesmn 0:3ac96e360672 1052 } VL53L1_zone_histograms_t;
charlesmn 0:3ac96e360672 1053
charlesmn 0:3ac96e360672 1054
charlesmn 0:3ac96e360672 1055
charlesmn 0:3ac96e360672 1056
charlesmn 0:3ac96e360672 1057 typedef struct {
charlesmn 0:3ac96e360672 1058
charlesmn 0:3ac96e360672 1059 uint32_t no_of_samples;
charlesmn 0:3ac96e360672 1060
charlesmn 0:3ac96e360672 1061 uint32_t effective_spads;
charlesmn 0:3ac96e360672 1062
charlesmn 0:3ac96e360672 1063 uint32_t peak_rate_mcps;
charlesmn 0:3ac96e360672 1064
charlesmn 0:3ac96e360672 1065 uint32_t VL53L1_p_014;
charlesmn 0:3ac96e360672 1066
charlesmn 0:3ac96e360672 1067 uint32_t VL53L1_p_005;
charlesmn 0:3ac96e360672 1068
charlesmn 0:3ac96e360672 1069 int32_t median_range_mm;
charlesmn 0:3ac96e360672 1070
charlesmn 0:3ac96e360672 1071 int32_t range_mm_offset;
charlesmn 0:3ac96e360672 1072
charlesmn 0:3ac96e360672 1073
charlesmn 0:3ac96e360672 1074 } VL53L1_zone_calibration_data_t;
charlesmn 0:3ac96e360672 1075
charlesmn 0:3ac96e360672 1076
charlesmn 0:3ac96e360672 1077
charlesmn 0:3ac96e360672 1078
charlesmn 0:3ac96e360672 1079
charlesmn 0:3ac96e360672 1080
charlesmn 0:3ac96e360672 1081 typedef struct {
charlesmn 0:3ac96e360672 1082
charlesmn 0:3ac96e360672 1083 uint32_t struct_version;
charlesmn 0:3ac96e360672 1084
charlesmn 0:3ac96e360672 1085 VL53L1_DevicePresetModes preset_mode;
charlesmn 0:3ac96e360672 1086
charlesmn 0:3ac96e360672 1087 VL53L1_DeviceZonePreset zone_preset;
charlesmn 0:3ac96e360672 1088
charlesmn 0:3ac96e360672 1089 int16_t cal_distance_mm;
charlesmn 0:3ac96e360672 1090
charlesmn 0:3ac96e360672 1091 uint16_t cal_reflectance_pc;
charlesmn 0:3ac96e360672 1092
charlesmn 0:3ac96e360672 1093 uint16_t phasecal_result__reference_phase;
charlesmn 0:3ac96e360672 1094
charlesmn 0:3ac96e360672 1095 uint16_t zero_distance_phase;
charlesmn 0:3ac96e360672 1096
charlesmn 0:3ac96e360672 1097 VL53L1_Error cal_status;
charlesmn 0:3ac96e360672 1098
charlesmn 0:3ac96e360672 1099 uint8_t max_zones;
charlesmn 0:3ac96e360672 1100
charlesmn 0:3ac96e360672 1101 uint8_t active_zones;
charlesmn 0:3ac96e360672 1102
charlesmn 0:3ac96e360672 1103 VL53L1_zone_calibration_data_t VL53L1_p_002[VL53L1_MAX_USER_ZONES];
charlesmn 0:3ac96e360672 1104
charlesmn 0:3ac96e360672 1105
charlesmn 0:3ac96e360672 1106 } VL53L1_zone_calibration_results_t;
charlesmn 0:3ac96e360672 1107
charlesmn 0:3ac96e360672 1108
charlesmn 0:3ac96e360672 1109
charlesmn 0:3ac96e360672 1110
charlesmn 0:3ac96e360672 1111
charlesmn 0:3ac96e360672 1112 typedef struct {
charlesmn 0:3ac96e360672 1113
charlesmn 0:3ac96e360672 1114 int16_t cal_distance_mm;
charlesmn 0:3ac96e360672 1115
charlesmn 0:3ac96e360672 1116 uint16_t cal_reflectance_pc;
charlesmn 0:3ac96e360672 1117
charlesmn 0:3ac96e360672 1118 uint16_t max_samples;
charlesmn 0:3ac96e360672 1119
charlesmn 0:3ac96e360672 1120 uint16_t width;
charlesmn 0:3ac96e360672 1121
charlesmn 0:3ac96e360672 1122 uint16_t height;
charlesmn 0:3ac96e360672 1123
charlesmn 0:3ac96e360672 1124 uint16_t peak_rate_mcps[VL53L1_NVM_PEAK_RATE_MAP_SAMPLES];
charlesmn 0:3ac96e360672 1125
charlesmn 0:3ac96e360672 1126
charlesmn 0:3ac96e360672 1127 } VL53L1_cal_peak_rate_map_t;
charlesmn 0:3ac96e360672 1128
charlesmn 0:3ac96e360672 1129
charlesmn 0:3ac96e360672 1130
charlesmn 0:3ac96e360672 1131
charlesmn 0:3ac96e360672 1132 typedef struct {
charlesmn 0:3ac96e360672 1133
charlesmn 0:3ac96e360672 1134 uint8_t expected_stream_count;
charlesmn 0:3ac96e360672 1135
charlesmn 0:3ac96e360672 1136 uint8_t expected_gph_id;
charlesmn 0:3ac96e360672 1137
charlesmn 0:3ac96e360672 1138 uint8_t dss_mode;
charlesmn 0:3ac96e360672 1139
charlesmn 0:3ac96e360672 1140 uint16_t dss_requested_effective_spad_count;
charlesmn 0:3ac96e360672 1141
charlesmn 0:3ac96e360672 1142 uint8_t seed_cfg;
charlesmn 0:3ac96e360672 1143
charlesmn 0:3ac96e360672 1144 uint8_t initial_phase_seed;
charlesmn 0:3ac96e360672 1145
charlesmn 0:3ac96e360672 1146
charlesmn 0:3ac96e360672 1147 uint8_t roi_config__user_roi_centre_spad;
charlesmn 0:3ac96e360672 1148
charlesmn 0:3ac96e360672 1149 uint8_t roi_config__user_roi_requested_global_xy_size;
charlesmn 0:3ac96e360672 1150
charlesmn 0:3ac96e360672 1151
charlesmn 0:3ac96e360672 1152 } VL53L1_zone_private_dyn_cfg_t;
charlesmn 0:3ac96e360672 1153
charlesmn 0:3ac96e360672 1154
charlesmn 0:3ac96e360672 1155
charlesmn 0:3ac96e360672 1156
charlesmn 0:3ac96e360672 1157 typedef struct {
charlesmn 0:3ac96e360672 1158
charlesmn 0:3ac96e360672 1159 uint8_t max_zones;
charlesmn 0:3ac96e360672 1160
charlesmn 0:3ac96e360672 1161 uint8_t active_zones;
charlesmn 0:3ac96e360672 1162
charlesmn 0:3ac96e360672 1163 VL53L1_zone_private_dyn_cfg_t VL53L1_p_002[VL53L1_MAX_USER_ZONES];
charlesmn 0:3ac96e360672 1164
charlesmn 0:3ac96e360672 1165
charlesmn 0:3ac96e360672 1166 } VL53L1_zone_private_dyn_cfgs_t;
charlesmn 0:3ac96e360672 1167
charlesmn 0:3ac96e360672 1168
charlesmn 0:3ac96e360672 1169
charlesmn 0:3ac96e360672 1170 typedef struct {
charlesmn 0:3ac96e360672 1171
charlesmn 0:3ac96e360672 1172 uint32_t algo__crosstalk_compensation_plane_offset_kcps;
charlesmn 0:3ac96e360672 1173
charlesmn 0:3ac96e360672 1174 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn 0:3ac96e360672 1175
charlesmn 0:3ac96e360672 1176 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn 0:3ac96e360672 1177
charlesmn 0:3ac96e360672 1178 uint32_t algo__xtalk_cpo_HistoMerge_kcps[VL53L1_BIN_REC_SIZE];
charlesmn 0:3ac96e360672 1179
charlesmn 0:3ac96e360672 1180
charlesmn 0:3ac96e360672 1181 } VL53L1_xtalk_calibration_results_t;
charlesmn 0:3ac96e360672 1182
charlesmn 0:3ac96e360672 1183
charlesmn 0:3ac96e360672 1184
charlesmn 0:3ac96e360672 1185
charlesmn 0:3ac96e360672 1186 typedef struct {
charlesmn 0:3ac96e360672 1187
charlesmn 0:3ac96e360672 1188
charlesmn 0:3ac96e360672 1189 uint32_t sample_count;
charlesmn 0:3ac96e360672 1190
charlesmn 0:3ac96e360672 1191
charlesmn 0:3ac96e360672 1192 uint32_t pll_period_mm;
charlesmn 0:3ac96e360672 1193
charlesmn 0:3ac96e360672 1194
charlesmn 0:3ac96e360672 1195 uint32_t peak_duration_us_sum;
charlesmn 0:3ac96e360672 1196
charlesmn 0:3ac96e360672 1197
charlesmn 0:3ac96e360672 1198 uint32_t effective_spad_count_sum;
charlesmn 0:3ac96e360672 1199
charlesmn 0:3ac96e360672 1200
charlesmn 0:3ac96e360672 1201 uint32_t zero_distance_phase_sum;
charlesmn 0:3ac96e360672 1202
charlesmn 0:3ac96e360672 1203
charlesmn 0:3ac96e360672 1204 uint32_t zero_distance_phase_avg;
charlesmn 0:3ac96e360672 1205
charlesmn 0:3ac96e360672 1206
charlesmn 0:3ac96e360672 1207 int32_t event_scaler_sum;
charlesmn 0:3ac96e360672 1208
charlesmn 0:3ac96e360672 1209
charlesmn 0:3ac96e360672 1210 int32_t event_scaler_avg;
charlesmn 0:3ac96e360672 1211
charlesmn 0:3ac96e360672 1212
charlesmn 0:3ac96e360672 1213 int32_t signal_events_sum;
charlesmn 0:3ac96e360672 1214
charlesmn 0:3ac96e360672 1215
charlesmn 0:3ac96e360672 1216 uint32_t xtalk_rate_kcps_per_spad;
charlesmn 0:3ac96e360672 1217
charlesmn 0:3ac96e360672 1218
charlesmn 0:3ac96e360672 1219 int32_t xtalk_start_phase;
charlesmn 0:3ac96e360672 1220
charlesmn 0:3ac96e360672 1221
charlesmn 0:3ac96e360672 1222 int32_t xtalk_end_phase;
charlesmn 0:3ac96e360672 1223
charlesmn 0:3ac96e360672 1224
charlesmn 0:3ac96e360672 1225 int32_t xtalk_width_phase;
charlesmn 0:3ac96e360672 1226
charlesmn 0:3ac96e360672 1227
charlesmn 0:3ac96e360672 1228 int32_t target_start_phase;
charlesmn 0:3ac96e360672 1229
charlesmn 0:3ac96e360672 1230
charlesmn 0:3ac96e360672 1231 int32_t target_end_phase;
charlesmn 0:3ac96e360672 1232
charlesmn 0:3ac96e360672 1233
charlesmn 0:3ac96e360672 1234 int32_t target_width_phase;
charlesmn 0:3ac96e360672 1235
charlesmn 0:3ac96e360672 1236
charlesmn 0:3ac96e360672 1237 int32_t effective_width;
charlesmn 0:3ac96e360672 1238
charlesmn 0:3ac96e360672 1239
charlesmn 0:3ac96e360672 1240 int32_t event_scaler;
charlesmn 0:3ac96e360672 1241
charlesmn 0:3ac96e360672 1242
charlesmn 0:3ac96e360672 1243 uint8_t VL53L1_p_015;
charlesmn 0:3ac96e360672 1244
charlesmn 0:3ac96e360672 1245
charlesmn 0:3ac96e360672 1246 uint8_t VL53L1_p_016;
charlesmn 0:3ac96e360672 1247
charlesmn 0:3ac96e360672 1248
charlesmn 0:3ac96e360672 1249 uint8_t target_start;
charlesmn 0:3ac96e360672 1250
charlesmn 0:3ac96e360672 1251
charlesmn 0:3ac96e360672 1252 int32_t max_shape_value;
charlesmn 0:3ac96e360672 1253
charlesmn 0:3ac96e360672 1254
charlesmn 0:3ac96e360672 1255 int32_t bin_data_sums[VL53L1_XTALK_HISTO_BINS];
charlesmn 0:3ac96e360672 1256
charlesmn 0:3ac96e360672 1257 } VL53L1_hist_xtalk_extract_data_t;
charlesmn 0:3ac96e360672 1258
charlesmn 0:3ac96e360672 1259
charlesmn 0:3ac96e360672 1260
charlesmn 0:3ac96e360672 1261
charlesmn 0:3ac96e360672 1262 typedef struct {
charlesmn 0:3ac96e360672 1263
charlesmn 0:3ac96e360672 1264 uint16_t standard_ranging_gain_factor;
charlesmn 0:3ac96e360672 1265
charlesmn 0:3ac96e360672 1266 uint16_t histogram_ranging_gain_factor;
charlesmn 0:3ac96e360672 1267
charlesmn 0:3ac96e360672 1268
charlesmn 0:3ac96e360672 1269 } VL53L1_gain_calibration_data_t;
charlesmn 0:3ac96e360672 1270
charlesmn 0:3ac96e360672 1271
charlesmn 0:3ac96e360672 1272
charlesmn 0:3ac96e360672 1273
charlesmn 0:3ac96e360672 1274 typedef struct {
charlesmn 0:3ac96e360672 1275
charlesmn 0:3ac96e360672 1276 VL53L1_DeviceState cfg_device_state;
charlesmn 0:3ac96e360672 1277
charlesmn 0:3ac96e360672 1278 uint8_t cfg_stream_count;
charlesmn 0:3ac96e360672 1279
charlesmn 0:3ac96e360672 1280 uint8_t cfg_internal_stream_count;
charlesmn 0:3ac96e360672 1281
charlesmn 0:3ac96e360672 1282 uint8_t cfg_internal_stream_count_val;
charlesmn 0:3ac96e360672 1283
charlesmn 0:3ac96e360672 1284 uint8_t cfg_gph_id;
charlesmn 0:3ac96e360672 1285
charlesmn 0:3ac96e360672 1286 uint8_t cfg_timing_status;
charlesmn 0:3ac96e360672 1287
charlesmn 0:3ac96e360672 1288 uint8_t cfg_zone_id;
charlesmn 0:3ac96e360672 1289
charlesmn 0:3ac96e360672 1290
charlesmn 0:3ac96e360672 1291 VL53L1_DeviceState rd_device_state;
charlesmn 0:3ac96e360672 1292
charlesmn 0:3ac96e360672 1293 uint8_t rd_stream_count;
charlesmn 0:3ac96e360672 1294
charlesmn 0:3ac96e360672 1295 uint8_t rd_internal_stream_count;
charlesmn 0:3ac96e360672 1296
charlesmn 0:3ac96e360672 1297 uint8_t rd_internal_stream_count_val;
charlesmn 0:3ac96e360672 1298
charlesmn 0:3ac96e360672 1299 uint8_t rd_gph_id;
charlesmn 0:3ac96e360672 1300
charlesmn 0:3ac96e360672 1301 uint8_t rd_timing_status;
charlesmn 0:3ac96e360672 1302
charlesmn 0:3ac96e360672 1303 uint8_t rd_zone_id;
charlesmn 0:3ac96e360672 1304
charlesmn 0:3ac96e360672 1305
charlesmn 0:3ac96e360672 1306 } VL53L1_ll_driver_state_t;
charlesmn 0:3ac96e360672 1307
charlesmn 0:3ac96e360672 1308
charlesmn 0:3ac96e360672 1309
charlesmn 0:3ac96e360672 1310
charlesmn 0:3ac96e360672 1311 typedef struct {
charlesmn 0:3ac96e360672 1312
charlesmn 0:3ac96e360672 1313 uint8_t wait_method;
charlesmn 0:3ac96e360672 1314
charlesmn 0:3ac96e360672 1315 VL53L1_DevicePresetModes preset_mode;
charlesmn 0:3ac96e360672 1316
charlesmn 0:3ac96e360672 1317 VL53L1_DeviceZonePreset zone_preset;
charlesmn 0:3ac96e360672 1318
charlesmn 0:3ac96e360672 1319 VL53L1_DeviceMeasurementModes measurement_mode;
charlesmn 0:3ac96e360672 1320
charlesmn 0:3ac96e360672 1321 VL53L1_OffsetCalibrationMode offset_calibration_mode;
charlesmn 0:3ac96e360672 1322
charlesmn 0:3ac96e360672 1323 VL53L1_OffsetCorrectionMode offset_correction_mode;
charlesmn 0:3ac96e360672 1324
charlesmn 0:3ac96e360672 1325 VL53L1_DeviceDmaxMode dmax_mode;
charlesmn 0:3ac96e360672 1326
charlesmn 0:3ac96e360672 1327 uint32_t phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1328
charlesmn 0:3ac96e360672 1329 uint32_t mm_config_timeout_us;
charlesmn 0:3ac96e360672 1330
charlesmn 0:3ac96e360672 1331 uint32_t range_config_timeout_us;
charlesmn 0:3ac96e360672 1332
charlesmn 0:3ac96e360672 1333 uint32_t inter_measurement_period_ms;
charlesmn 0:3ac96e360672 1334
charlesmn 0:3ac96e360672 1335 uint16_t dss_config__target_total_rate_mcps;
charlesmn 0:3ac96e360672 1336
charlesmn 0:3ac96e360672 1337 uint32_t fw_ready_poll_duration_ms;
charlesmn 0:3ac96e360672 1338
charlesmn 0:3ac96e360672 1339 uint8_t fw_ready;
charlesmn 0:3ac96e360672 1340
charlesmn 0:3ac96e360672 1341 uint8_t debug_mode;
charlesmn 0:3ac96e360672 1342
charlesmn 0:3ac96e360672 1343
charlesmn 0:3ac96e360672 1344
charlesmn 0:3ac96e360672 1345 VL53L1_ll_version_t version;
charlesmn 0:3ac96e360672 1346
charlesmn 0:3ac96e360672 1347
charlesmn 0:3ac96e360672 1348 VL53L1_ll_driver_state_t ll_state;
charlesmn 0:3ac96e360672 1349
charlesmn 0:3ac96e360672 1350
charlesmn 0:3ac96e360672 1351 VL53L1_GPIO_interrupt_config_t gpio_interrupt_config;
charlesmn 0:3ac96e360672 1352
charlesmn 0:3ac96e360672 1353
charlesmn 0:3ac96e360672 1354 VL53L1_customer_nvm_managed_t customer;
charlesmn 0:3ac96e360672 1355 VL53L1_cal_peak_rate_map_t cal_peak_rate_map;
charlesmn 0:3ac96e360672 1356 VL53L1_additional_offset_cal_data_t add_off_cal_data;
charlesmn 0:3ac96e360672 1357 VL53L1_dmax_calibration_data_t fmt_dmax_cal;
charlesmn 0:3ac96e360672 1358 VL53L1_dmax_calibration_data_t cust_dmax_cal;
charlesmn 0:3ac96e360672 1359 VL53L1_gain_calibration_data_t gain_cal;
charlesmn 0:3ac96e360672 1360 VL53L1_user_zone_t mm_roi;
charlesmn 0:3ac96e360672 1361 VL53L1_optical_centre_t optical_centre;
charlesmn 0:3ac96e360672 1362 VL53L1_zone_config_t zone_cfg;
charlesmn 0:3ac96e360672 1363
charlesmn 0:3ac96e360672 1364
charlesmn 0:3ac96e360672 1365 VL53L1_tuning_parm_storage_t tuning_parms;
charlesmn 0:3ac96e360672 1366
charlesmn 0:3ac96e360672 1367
charlesmn 0:3ac96e360672 1368 uint8_t rtn_good_spads[VL53L1_RTN_SPAD_BUFFER_SIZE];
charlesmn 0:3ac96e360672 1369
charlesmn 0:3ac96e360672 1370
charlesmn 0:3ac96e360672 1371 VL53L1_refspadchar_config_t refspadchar;
charlesmn 0:3ac96e360672 1372 VL53L1_ssc_config_t ssc_cfg;
charlesmn 0:3ac96e360672 1373 VL53L1_hist_post_process_config_t histpostprocess;
charlesmn 0:3ac96e360672 1374 VL53L1_hist_gen3_dmax_config_t dmax_cfg;
charlesmn 0:3ac96e360672 1375 VL53L1_xtalkextract_config_t xtalk_extract_cfg;
charlesmn 0:3ac96e360672 1376 VL53L1_xtalk_config_t xtalk_cfg;
charlesmn 0:3ac96e360672 1377 VL53L1_offsetcal_config_t offsetcal_cfg;
charlesmn 0:3ac96e360672 1378 VL53L1_zonecal_config_t zonecal_cfg;
charlesmn 0:3ac96e360672 1379
charlesmn 0:3ac96e360672 1380
charlesmn 0:3ac96e360672 1381 VL53L1_static_nvm_managed_t stat_nvm;
charlesmn 0:3ac96e360672 1382 VL53L1_histogram_config_t hist_cfg;
charlesmn 0:3ac96e360672 1383 VL53L1_static_config_t stat_cfg;
charlesmn 0:3ac96e360672 1384 VL53L1_general_config_t gen_cfg;
charlesmn 0:3ac96e360672 1385 VL53L1_timing_config_t tim_cfg;
charlesmn 0:3ac96e360672 1386 VL53L1_dynamic_config_t dyn_cfg;
charlesmn 0:3ac96e360672 1387 VL53L1_system_control_t sys_ctrl;
charlesmn 0:3ac96e360672 1388 VL53L1_system_results_t sys_results;
charlesmn 0:3ac96e360672 1389 VL53L1_nvm_copy_data_t nvm_copy_data;
charlesmn 0:3ac96e360672 1390
charlesmn 0:3ac96e360672 1391
charlesmn 0:3ac96e360672 1392 VL53L1_histogram_bin_data_t hist_data;
charlesmn 0:3ac96e360672 1393 VL53L1_histogram_bin_data_t hist_xtalk;
charlesmn 0:3ac96e360672 1394
charlesmn 0:3ac96e360672 1395
charlesmn 0:3ac96e360672 1396 VL53L1_xtalk_histogram_data_t xtalk_shapes;
charlesmn 0:3ac96e360672 1397 VL53L1_xtalk_range_results_t xtalk_results;
charlesmn 0:3ac96e360672 1398 VL53L1_xtalk_calibration_results_t xtalk_cal;
charlesmn 0:3ac96e360672 1399 VL53L1_hist_xtalk_extract_data_t xtalk_extract;
charlesmn 0:3ac96e360672 1400
charlesmn 0:3ac96e360672 1401
charlesmn 0:3ac96e360672 1402 VL53L1_offset_range_results_t offset_results;
charlesmn 0:3ac96e360672 1403
charlesmn 0:3ac96e360672 1404
charlesmn 0:3ac96e360672 1405 VL53L1_core_results_t core_results;
charlesmn 0:3ac96e360672 1406 VL53L1_debug_results_t dbg_results;
charlesmn 0:3ac96e360672 1407
charlesmn 0:3ac96e360672 1408 VL53L1_smudge_corrector_config_t smudge_correct_config;
charlesmn 0:3ac96e360672 1409
charlesmn 0:3ac96e360672 1410 VL53L1_smudge_corrector_internals_t smudge_corrector_internals;
charlesmn 0:3ac96e360672 1411
charlesmn 0:3ac96e360672 1412
charlesmn 0:3ac96e360672 1413
charlesmn 0:3ac96e360672 1414
charlesmn 0:3ac96e360672 1415 VL53L1_low_power_auto_data_t low_power_auto_data;
charlesmn 0:3ac96e360672 1416
charlesmn 0:3ac96e360672 1417
charlesmn 0:3ac96e360672 1418 #ifdef PAL_EXTENDED
charlesmn 0:3ac96e360672 1419
charlesmn 0:3ac96e360672 1420 VL53L1_patch_results_t patch_results;
charlesmn 0:3ac96e360672 1421 VL53L1_shadow_core_results_t shadow_core_results;
charlesmn 0:3ac96e360672 1422 VL53L1_shadow_system_results_t shadow_sys_results;
charlesmn 0:3ac96e360672 1423 VL53L1_prev_shadow_core_results_t prev_shadow_core_results;
charlesmn 0:3ac96e360672 1424 VL53L1_prev_shadow_system_results_t prev_shadow_sys_results;
charlesmn 0:3ac96e360672 1425 #endif
charlesmn 0:3ac96e360672 1426 uint8_t wArea1[1536];
charlesmn 0:3ac96e360672 1427 uint8_t wArea2[512];
charlesmn 0:3ac96e360672 1428 VL53L1_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data;
charlesmn 0:3ac96e360672 1429
charlesmn 0:3ac96e360672 1430 uint8_t bin_rec_pos;
charlesmn 0:3ac96e360672 1431
charlesmn 0:3ac96e360672 1432 uint8_t pos_before_next_recom;
charlesmn 0:3ac96e360672 1433
charlesmn 0:3ac96e360672 1434 int32_t multi_bins_rec[VL53L1_BIN_REC_SIZE]
charlesmn 0:3ac96e360672 1435 [VL53L1_TIMING_CONF_A_B_SIZE][VL53L1_HISTOGRAM_BUFFER_SIZE];
charlesmn 0:3ac96e360672 1436
charlesmn 0:3ac96e360672 1437 int16_t PreviousRangeMilliMeter[VL53L1_MAX_RANGE_RESULTS];
charlesmn 0:3ac96e360672 1438 uint8_t PreviousRangeStatus[VL53L1_MAX_RANGE_RESULTS];
charlesmn 0:3ac96e360672 1439 uint8_t PreviousExtendedRange[VL53L1_MAX_RANGE_RESULTS];
charlesmn 0:3ac96e360672 1440 uint8_t PreviousStreamCount;
charlesmn 0:3ac96e360672 1441
charlesmn 0:3ac96e360672 1442 } VL53L1_LLDriverData_t;
charlesmn 0:3ac96e360672 1443
charlesmn 0:3ac96e360672 1444
charlesmn 0:3ac96e360672 1445
charlesmn 0:3ac96e360672 1446
charlesmn 0:3ac96e360672 1447 typedef struct {
charlesmn 0:3ac96e360672 1448
charlesmn 0:3ac96e360672 1449
charlesmn 0:3ac96e360672 1450 VL53L1_range_results_t range_results;
charlesmn 0:3ac96e360672 1451
charlesmn 0:3ac96e360672 1452
charlesmn 0:3ac96e360672 1453 VL53L1_zone_private_dyn_cfgs_t zone_dyn_cfgs;
charlesmn 0:3ac96e360672 1454
charlesmn 0:3ac96e360672 1455
charlesmn 0:3ac96e360672 1456 VL53L1_zone_results_t zone_results;
charlesmn 0:3ac96e360672 1457 VL53L1_zone_histograms_t zone_hists;
charlesmn 0:3ac96e360672 1458 VL53L1_zone_calibration_results_t zone_cal;
charlesmn 0:3ac96e360672 1459
charlesmn 0:3ac96e360672 1460 } VL53L1_LLDriverResults_t;
charlesmn 0:3ac96e360672 1461
charlesmn 0:3ac96e360672 1462
charlesmn 0:3ac96e360672 1463
charlesmn 0:3ac96e360672 1464
charlesmn 0:3ac96e360672 1465 typedef struct {
charlesmn 0:3ac96e360672 1466
charlesmn 0:3ac96e360672 1467 uint32_t struct_version;
charlesmn 0:3ac96e360672 1468 VL53L1_customer_nvm_managed_t customer;
charlesmn 0:3ac96e360672 1469 VL53L1_dmax_calibration_data_t fmt_dmax_cal;
charlesmn 0:3ac96e360672 1470 VL53L1_dmax_calibration_data_t cust_dmax_cal;
charlesmn 0:3ac96e360672 1471 VL53L1_additional_offset_cal_data_t add_off_cal_data;
charlesmn 0:3ac96e360672 1472 VL53L1_optical_centre_t optical_centre;
charlesmn 0:3ac96e360672 1473 VL53L1_xtalk_histogram_data_t xtalkhisto;
charlesmn 0:3ac96e360672 1474 VL53L1_gain_calibration_data_t gain_cal;
charlesmn 0:3ac96e360672 1475 VL53L1_cal_peak_rate_map_t cal_peak_rate_map;
charlesmn 0:3ac96e360672 1476 VL53L1_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data;
charlesmn 0:3ac96e360672 1477
charlesmn 0:3ac96e360672 1478 } VL53L1_calibration_data_t;
charlesmn 0:3ac96e360672 1479
charlesmn 0:3ac96e360672 1480
charlesmn 0:3ac96e360672 1481
charlesmn 0:3ac96e360672 1482
charlesmn 0:3ac96e360672 1483 typedef struct {
charlesmn 0:3ac96e360672 1484
charlesmn 0:3ac96e360672 1485 VL53L1_customer_nvm_managed_t customer;
charlesmn 0:3ac96e360672 1486 VL53L1_xtalkextract_config_t xtalk_extract_cfg;
charlesmn 0:3ac96e360672 1487 VL53L1_xtalk_config_t xtalk_cfg;
charlesmn 0:3ac96e360672 1488 VL53L1_histogram_bin_data_t hist_data;
charlesmn 0:3ac96e360672 1489 VL53L1_xtalk_histogram_data_t xtalk_shapes;
charlesmn 0:3ac96e360672 1490 VL53L1_xtalk_range_results_t xtalk_results;
charlesmn 0:3ac96e360672 1491
charlesmn 0:3ac96e360672 1492 } VL53L1_xtalk_debug_data_t;
charlesmn 0:3ac96e360672 1493
charlesmn 0:3ac96e360672 1494
charlesmn 0:3ac96e360672 1495
charlesmn 0:3ac96e360672 1496
charlesmn 0:3ac96e360672 1497 typedef struct {
charlesmn 0:3ac96e360672 1498
charlesmn 0:3ac96e360672 1499 VL53L1_customer_nvm_managed_t customer;
charlesmn 0:3ac96e360672 1500 VL53L1_dmax_calibration_data_t fmt_dmax_cal;
charlesmn 0:3ac96e360672 1501 VL53L1_dmax_calibration_data_t cust_dmax_cal;
charlesmn 0:3ac96e360672 1502 VL53L1_additional_offset_cal_data_t add_off_cal_data;
charlesmn 0:3ac96e360672 1503 VL53L1_offset_range_results_t offset_results;
charlesmn 0:3ac96e360672 1504
charlesmn 0:3ac96e360672 1505 } VL53L1_offset_debug_data_t;
charlesmn 0:3ac96e360672 1506
charlesmn 0:3ac96e360672 1507
charlesmn 0:3ac96e360672 1508
charlesmn 0:3ac96e360672 1509
charlesmn 0:3ac96e360672 1510 typedef struct {
charlesmn 0:3ac96e360672 1511 uint16_t vl53l1_tuningparm_version;
charlesmn 0:3ac96e360672 1512 uint16_t vl53l1_tuningparm_key_table_version;
charlesmn 0:3ac96e360672 1513 uint16_t vl53l1_tuningparm_lld_version;
charlesmn 0:3ac96e360672 1514 uint8_t vl53l1_tuningparm_hist_algo_select;
charlesmn 0:3ac96e360672 1515 uint8_t vl53l1_tuningparm_hist_target_order;
charlesmn 0:3ac96e360672 1516 uint8_t vl53l1_tuningparm_hist_filter_woi_0;
charlesmn 0:3ac96e360672 1517 uint8_t vl53l1_tuningparm_hist_filter_woi_1;
charlesmn 0:3ac96e360672 1518 uint8_t vl53l1_tuningparm_hist_amb_est_method;
charlesmn 0:3ac96e360672 1519 uint8_t vl53l1_tuningparm_hist_amb_thresh_sigma_0;
charlesmn 0:3ac96e360672 1520 uint8_t vl53l1_tuningparm_hist_amb_thresh_sigma_1;
charlesmn 0:3ac96e360672 1521 int32_t vl53l1_tuningparm_hist_min_amb_thresh_events;
charlesmn 0:3ac96e360672 1522 uint16_t vl53l1_tuningparm_hist_amb_events_scaler;
charlesmn 0:3ac96e360672 1523 uint16_t vl53l1_tuningparm_hist_noise_threshold;
charlesmn 0:3ac96e360672 1524 int32_t vl53l1_tuningparm_hist_signal_total_events_limit;
charlesmn 0:3ac96e360672 1525 uint8_t vl53l1_tuningparm_hist_sigma_est_ref_mm;
charlesmn 0:3ac96e360672 1526 uint16_t vl53l1_tuningparm_hist_sigma_thresh_mm;
charlesmn 0:3ac96e360672 1527 uint16_t vl53l1_tuningparm_hist_gain_factor;
charlesmn 0:3ac96e360672 1528 uint8_t vl53l1_tuningparm_consistency_hist_phase_tolerance;
charlesmn 0:3ac96e360672 1529 uint16_t vl53l1_tuningparm_consistency_hist_min_max_tolerance_mm;
charlesmn 0:3ac96e360672 1530 uint8_t vl53l1_tuningparm_consistency_hist_event_sigma;
charlesmn 0:3ac96e360672 1531 uint16_t vl53l1_tuningparm_consistency_hist_event_sigma_min_spad_limit;
charlesmn 0:3ac96e360672 1532 uint8_t vl53l1_tuningparm_initial_phase_rtn_histo_long_range;
charlesmn 0:3ac96e360672 1533 uint8_t vl53l1_tuningparm_initial_phase_rtn_histo_med_range;
charlesmn 0:3ac96e360672 1534 uint8_t vl53l1_tuningparm_initial_phase_rtn_histo_short_range;
charlesmn 0:3ac96e360672 1535 uint8_t vl53l1_tuningparm_initial_phase_ref_histo_long_range;
charlesmn 0:3ac96e360672 1536 uint8_t vl53l1_tuningparm_initial_phase_ref_histo_med_range;
charlesmn 0:3ac96e360672 1537 uint8_t vl53l1_tuningparm_initial_phase_ref_histo_short_range;
charlesmn 0:3ac96e360672 1538 int16_t vl53l1_tuningparm_xtalk_detect_min_valid_range_mm;
charlesmn 0:3ac96e360672 1539 int16_t vl53l1_tuningparm_xtalk_detect_max_valid_range_mm;
charlesmn 0:3ac96e360672 1540 uint16_t vl53l1_tuningparm_xtalk_detect_max_sigma_mm;
charlesmn 0:3ac96e360672 1541 uint16_t vl53l1_tuningparm_xtalk_detect_min_max_tolerance;
charlesmn 0:3ac96e360672 1542 uint16_t vl53l1_tuningparm_xtalk_detect_max_valid_rate_kcps;
charlesmn 0:3ac96e360672 1543 uint8_t vl53l1_tuningparm_xtalk_detect_event_sigma;
charlesmn 0:3ac96e360672 1544 int16_t vl53l1_tuningparm_hist_xtalk_margin_kcps;
charlesmn 0:3ac96e360672 1545 uint8_t vl53l1_tuningparm_consistency_lite_phase_tolerance;
charlesmn 0:3ac96e360672 1546 uint8_t vl53l1_tuningparm_phasecal_target;
charlesmn 0:3ac96e360672 1547 uint16_t vl53l1_tuningparm_lite_cal_repeat_rate;
charlesmn 0:3ac96e360672 1548 uint16_t vl53l1_tuningparm_lite_ranging_gain_factor;
charlesmn 0:3ac96e360672 1549 uint8_t vl53l1_tuningparm_lite_min_clip_mm;
charlesmn 0:3ac96e360672 1550 uint16_t vl53l1_tuningparm_lite_long_sigma_thresh_mm;
charlesmn 0:3ac96e360672 1551 uint16_t vl53l1_tuningparm_lite_med_sigma_thresh_mm;
charlesmn 0:3ac96e360672 1552 uint16_t vl53l1_tuningparm_lite_short_sigma_thresh_mm;
charlesmn 0:3ac96e360672 1553 uint16_t vl53l1_tuningparm_lite_long_min_count_rate_rtn_mcps;
charlesmn 0:3ac96e360672 1554 uint16_t vl53l1_tuningparm_lite_med_min_count_rate_rtn_mcps;
charlesmn 0:3ac96e360672 1555 uint16_t vl53l1_tuningparm_lite_short_min_count_rate_rtn_mcps;
charlesmn 0:3ac96e360672 1556 uint8_t vl53l1_tuningparm_lite_sigma_est_pulse_width;
charlesmn 0:3ac96e360672 1557 uint8_t vl53l1_tuningparm_lite_sigma_est_amb_width_ns;
charlesmn 0:3ac96e360672 1558 uint8_t vl53l1_tuningparm_lite_sigma_ref_mm;
charlesmn 0:3ac96e360672 1559 uint8_t vl53l1_tuningparm_lite_rit_mult;
charlesmn 0:3ac96e360672 1560 uint8_t vl53l1_tuningparm_lite_seed_config;
charlesmn 0:3ac96e360672 1561 uint8_t vl53l1_tuningparm_lite_quantifier;
charlesmn 0:3ac96e360672 1562 uint8_t vl53l1_tuningparm_lite_first_order_select;
charlesmn 0:3ac96e360672 1563 int16_t vl53l1_tuningparm_lite_xtalk_margin_kcps;
charlesmn 0:3ac96e360672 1564 uint8_t vl53l1_tuningparm_initial_phase_rtn_lite_long_range;
charlesmn 0:3ac96e360672 1565 uint8_t vl53l1_tuningparm_initial_phase_rtn_lite_med_range;
charlesmn 0:3ac96e360672 1566 uint8_t vl53l1_tuningparm_initial_phase_rtn_lite_short_range;
charlesmn 0:3ac96e360672 1567 uint8_t vl53l1_tuningparm_initial_phase_ref_lite_long_range;
charlesmn 0:3ac96e360672 1568 uint8_t vl53l1_tuningparm_initial_phase_ref_lite_med_range;
charlesmn 0:3ac96e360672 1569 uint8_t vl53l1_tuningparm_initial_phase_ref_lite_short_range;
charlesmn 0:3ac96e360672 1570 uint8_t vl53l1_tuningparm_timed_seed_config;
charlesmn 0:3ac96e360672 1571 uint8_t vl53l1_tuningparm_dmax_cfg_signal_thresh_sigma;
charlesmn 0:3ac96e360672 1572 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_0;
charlesmn 0:3ac96e360672 1573 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_1;
charlesmn 0:3ac96e360672 1574 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_2;
charlesmn 0:3ac96e360672 1575 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_3;
charlesmn 0:3ac96e360672 1576 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_4;
charlesmn 0:3ac96e360672 1577 uint8_t vl53l1_tuningparm_vhv_loopbound;
charlesmn 0:3ac96e360672 1578 uint8_t vl53l1_tuningparm_refspadchar_device_test_mode;
charlesmn 0:3ac96e360672 1579 uint8_t vl53l1_tuningparm_refspadchar_vcsel_period;
charlesmn 0:3ac96e360672 1580 uint32_t vl53l1_tuningparm_refspadchar_phasecal_timeout_us;
charlesmn 0:3ac96e360672 1581 uint16_t vl53l1_tuningparm_refspadchar_target_count_rate_mcps;
charlesmn 0:3ac96e360672 1582 uint16_t vl53l1_tuningparm_refspadchar_min_countrate_limit_mcps;
charlesmn 0:3ac96e360672 1583 uint16_t vl53l1_tuningparm_refspadchar_max_countrate_limit_mcps;
charlesmn 0:3ac96e360672 1584 uint8_t vl53l1_tuningparm_xtalk_extract_num_of_samples;
charlesmn 0:3ac96e360672 1585 int16_t vl53l1_tuningparm_xtalk_extract_min_filter_thresh_mm;
charlesmn 0:3ac96e360672 1586 int16_t vl53l1_tuningparm_xtalk_extract_max_filter_thresh_mm;
charlesmn 0:3ac96e360672 1587 uint16_t vl53l1_tuningparm_xtalk_extract_dss_rate_mcps;
charlesmn 0:3ac96e360672 1588 uint32_t vl53l1_tuningparm_xtalk_extract_phasecal_timeout_us;
charlesmn 0:3ac96e360672 1589 uint16_t vl53l1_tuningparm_xtalk_extract_max_valid_rate_kcps;
charlesmn 0:3ac96e360672 1590 uint16_t vl53l1_tuningparm_xtalk_extract_sigma_threshold_mm;
charlesmn 0:3ac96e360672 1591 uint32_t vl53l1_tuningparm_xtalk_extract_dss_timeout_us;
charlesmn 0:3ac96e360672 1592 uint32_t vl53l1_tuningparm_xtalk_extract_bin_timeout_us;
charlesmn 0:3ac96e360672 1593 uint16_t vl53l1_tuningparm_offset_cal_dss_rate_mcps;
charlesmn 0:3ac96e360672 1594 uint32_t vl53l1_tuningparm_offset_cal_phasecal_timeout_us;
charlesmn 0:3ac96e360672 1595 uint32_t vl53l1_tuningparm_offset_cal_mm_timeout_us;
charlesmn 0:3ac96e360672 1596 uint32_t vl53l1_tuningparm_offset_cal_range_timeout_us;
charlesmn 0:3ac96e360672 1597 uint8_t vl53l1_tuningparm_offset_cal_pre_samples;
charlesmn 0:3ac96e360672 1598 uint8_t vl53l1_tuningparm_offset_cal_mm1_samples;
charlesmn 0:3ac96e360672 1599 uint8_t vl53l1_tuningparm_offset_cal_mm2_samples;
charlesmn 0:3ac96e360672 1600 uint16_t vl53l1_tuningparm_zone_cal_dss_rate_mcps;
charlesmn 0:3ac96e360672 1601 uint32_t vl53l1_tuningparm_zone_cal_phasecal_timeout_us;
charlesmn 0:3ac96e360672 1602 uint32_t vl53l1_tuningparm_zone_cal_dss_timeout_us;
charlesmn 0:3ac96e360672 1603 uint16_t vl53l1_tuningparm_zone_cal_phasecal_num_samples;
charlesmn 0:3ac96e360672 1604 uint32_t vl53l1_tuningparm_zone_cal_range_timeout_us;
charlesmn 0:3ac96e360672 1605 uint16_t vl53l1_tuningparm_zone_cal_zone_num_samples;
charlesmn 0:3ac96e360672 1606 uint8_t vl53l1_tuningparm_spadmap_vcsel_period;
charlesmn 0:3ac96e360672 1607 uint8_t vl53l1_tuningparm_spadmap_vcsel_start;
charlesmn 0:3ac96e360672 1608 uint16_t vl53l1_tuningparm_spadmap_rate_limit_mcps;
charlesmn 0:3ac96e360672 1609 uint16_t vl53l1_tuningparm_lite_dss_config_target_total_rate_mcps;
charlesmn 0:3ac96e360672 1610 uint16_t vl53l1_tuningparm_ranging_dss_config_target_total_rate_mcps;
charlesmn 0:3ac96e360672 1611 uint16_t vl53l1_tuningparm_mz_dss_config_target_total_rate_mcps;
charlesmn 0:3ac96e360672 1612 uint16_t vl53l1_tuningparm_timed_dss_config_target_total_rate_mcps;
charlesmn 0:3ac96e360672 1613 uint32_t vl53l1_tuningparm_lite_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1614 uint32_t vl53l1_tuningparm_ranging_long_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1615 uint32_t vl53l1_tuningparm_ranging_med_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1616 uint32_t vl53l1_tuningparm_ranging_short_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1617 uint32_t vl53l1_tuningparm_mz_long_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1618 uint32_t vl53l1_tuningparm_mz_med_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1619 uint32_t vl53l1_tuningparm_mz_short_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1620 uint32_t vl53l1_tuningparm_timed_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1621 uint32_t vl53l1_tuningparm_lite_mm_config_timeout_us;
charlesmn 0:3ac96e360672 1622 uint32_t vl53l1_tuningparm_ranging_mm_config_timeout_us;
charlesmn 0:3ac96e360672 1623 uint32_t vl53l1_tuningparm_mz_mm_config_timeout_us;
charlesmn 0:3ac96e360672 1624 uint32_t vl53l1_tuningparm_timed_mm_config_timeout_us;
charlesmn 0:3ac96e360672 1625 uint32_t vl53l1_tuningparm_lite_range_config_timeout_us;
charlesmn 0:3ac96e360672 1626 uint32_t vl53l1_tuningparm_ranging_range_config_timeout_us;
charlesmn 0:3ac96e360672 1627 uint32_t vl53l1_tuningparm_mz_range_config_timeout_us;
charlesmn 0:3ac96e360672 1628 uint32_t vl53l1_tuningparm_timed_range_config_timeout_us;
charlesmn 0:3ac96e360672 1629 uint16_t vl53l1_tuningparm_dynxtalk_smudge_margin;
charlesmn 0:3ac96e360672 1630 uint32_t vl53l1_tuningparm_dynxtalk_noise_margin;
charlesmn 0:3ac96e360672 1631 uint32_t vl53l1_tuningparm_dynxtalk_xtalk_offset_limit;
charlesmn 0:3ac96e360672 1632 uint8_t vl53l1_tuningparm_dynxtalk_xtalk_offset_limit_hi;
charlesmn 0:3ac96e360672 1633 uint32_t vl53l1_tuningparm_dynxtalk_sample_limit;
charlesmn 0:3ac96e360672 1634 uint32_t vl53l1_tuningparm_dynxtalk_single_xtalk_delta;
charlesmn 0:3ac96e360672 1635 uint32_t vl53l1_tuningparm_dynxtalk_averaged_xtalk_delta;
charlesmn 0:3ac96e360672 1636 uint32_t vl53l1_tuningparm_dynxtalk_clip_limit;
charlesmn 0:3ac96e360672 1637 uint8_t vl53l1_tuningparm_dynxtalk_scaler_calc_method;
charlesmn 0:3ac96e360672 1638 int16_t vl53l1_tuningparm_dynxtalk_xgradient_scaler;
charlesmn 0:3ac96e360672 1639 int16_t vl53l1_tuningparm_dynxtalk_ygradient_scaler;
charlesmn 0:3ac96e360672 1640 uint8_t vl53l1_tuningparm_dynxtalk_user_scaler_set;
charlesmn 0:3ac96e360672 1641 uint8_t vl53l1_tuningparm_dynxtalk_smudge_cor_single_apply;
charlesmn 0:3ac96e360672 1642 uint32_t vl53l1_tuningparm_dynxtalk_xtalk_amb_threshold;
charlesmn 0:3ac96e360672 1643 uint32_t vl53l1_tuningparm_dynxtalk_nodetect_amb_threshold_kcps;
charlesmn 0:3ac96e360672 1644 uint32_t vl53l1_tuningparm_dynxtalk_nodetect_sample_limit;
charlesmn 0:3ac96e360672 1645 uint32_t vl53l1_tuningparm_dynxtalk_nodetect_xtalk_offset_kcps;
charlesmn 0:3ac96e360672 1646 uint16_t vl53l1_tuningparm_dynxtalk_nodetect_min_range_mm;
charlesmn 0:3ac96e360672 1647 uint8_t vl53l1_tuningparm_lowpowerauto_vhv_loop_bound;
charlesmn 0:3ac96e360672 1648 uint32_t vl53l1_tuningparm_lowpowerauto_mm_config_timeout_us;
charlesmn 0:3ac96e360672 1649 uint32_t vl53l1_tuningparm_lowpowerauto_range_config_timeout_us;
charlesmn 0:3ac96e360672 1650 uint16_t vl53l1_tuningparm_very_short_dss_rate_mcps;
charlesmn 0:3ac96e360672 1651 uint32_t vl53l1_tuningparm_phasecal_patch_power;
charlesmn 0:3ac96e360672 1652 } VL53L1_tuning_parameters_t;
charlesmn 0:3ac96e360672 1653
charlesmn 0:3ac96e360672 1654
charlesmn 0:3ac96e360672 1655
charlesmn 0:3ac96e360672 1656
charlesmn 0:3ac96e360672 1657
charlesmn 0:3ac96e360672 1658 typedef struct {
charlesmn 0:3ac96e360672 1659
charlesmn 0:3ac96e360672 1660 uint16_t target_reflectance_for_dmax[VL53L1_MAX_AMBIENT_DMAX_VALUES];
charlesmn 0:3ac96e360672 1661
charlesmn 0:3ac96e360672 1662 } VL53L1_dmax_reflectance_array_t;
charlesmn 0:3ac96e360672 1663
charlesmn 0:3ac96e360672 1664
charlesmn 0:3ac96e360672 1665
charlesmn 0:3ac96e360672 1666
charlesmn 0:3ac96e360672 1667 typedef struct {
charlesmn 0:3ac96e360672 1668
charlesmn 0:3ac96e360672 1669 uint8_t spad_type;
charlesmn 0:3ac96e360672 1670
charlesmn 0:3ac96e360672 1671 uint16_t VL53L1_p_023;
charlesmn 0:3ac96e360672 1672
charlesmn 0:3ac96e360672 1673 uint16_t rate_data[VL53L1_NO_OF_SPAD_ENABLES];
charlesmn 0:3ac96e360672 1674
charlesmn 0:3ac96e360672 1675 uint16_t no_of_values;
charlesmn 0:3ac96e360672 1676
charlesmn 0:3ac96e360672 1677 uint8_t fractional_bits;
charlesmn 0:3ac96e360672 1678
charlesmn 0:3ac96e360672 1679 uint8_t error_status;
charlesmn 0:3ac96e360672 1680
charlesmn 0:3ac96e360672 1681
charlesmn 0:3ac96e360672 1682 } VL53L1_spad_rate_data_t;
charlesmn 0:3ac96e360672 1683
charlesmn 0:3ac96e360672 1684
charlesmn 0:3ac96e360672 1685
charlesmn 0:3ac96e360672 1686
charlesmn 0:3ac96e360672 1687
charlesmn 0:3ac96e360672 1688
charlesmn 0:3ac96e360672 1689 typedef struct {
charlesmn 0:3ac96e360672 1690
charlesmn 0:3ac96e360672 1691 VL53L1_DevicePresetModes preset_mode;
charlesmn 0:3ac96e360672 1692
charlesmn 0:3ac96e360672 1693 VL53L1_DeviceZonePreset zone_preset;
charlesmn 0:3ac96e360672 1694
charlesmn 0:3ac96e360672 1695 VL53L1_DeviceMeasurementModes measurement_mode;
charlesmn 0:3ac96e360672 1696
charlesmn 0:3ac96e360672 1697 VL53L1_OffsetCalibrationMode offset_calibration_mode;
charlesmn 0:3ac96e360672 1698
charlesmn 0:3ac96e360672 1699 VL53L1_OffsetCorrectionMode offset_correction_mode;
charlesmn 0:3ac96e360672 1700
charlesmn 0:3ac96e360672 1701 VL53L1_DeviceDmaxMode dmax_mode;
charlesmn 0:3ac96e360672 1702
charlesmn 0:3ac96e360672 1703
charlesmn 0:3ac96e360672 1704 uint32_t phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1705
charlesmn 0:3ac96e360672 1706 uint32_t mm_config_timeout_us;
charlesmn 0:3ac96e360672 1707
charlesmn 0:3ac96e360672 1708 uint32_t range_config_timeout_us;
charlesmn 0:3ac96e360672 1709
charlesmn 0:3ac96e360672 1710 uint32_t inter_measurement_period_ms;
charlesmn 0:3ac96e360672 1711
charlesmn 0:3ac96e360672 1712 uint16_t dss_config__target_total_rate_mcps;
charlesmn 0:3ac96e360672 1713
charlesmn 0:3ac96e360672 1714
charlesmn 0:3ac96e360672 1715 VL53L1_histogram_bin_data_t VL53L1_p_010;
charlesmn 0:3ac96e360672 1716
charlesmn 0:3ac96e360672 1717
charlesmn 0:3ac96e360672 1718 } VL53L1_additional_data_t;
charlesmn 0:3ac96e360672 1719
charlesmn 0:3ac96e360672 1720
charlesmn 0:3ac96e360672 1721
charlesmn 0:3ac96e360672 1722
charlesmn 0:3ac96e360672 1723
charlesmn 0:3ac96e360672 1724
charlesmn 0:3ac96e360672 1725
charlesmn 0:3ac96e360672 1726
charlesmn 0:3ac96e360672 1727 #define SUPPRESS_UNUSED_WARNING(x) \
charlesmn 0:3ac96e360672 1728 ((void) (x))
charlesmn 0:3ac96e360672 1729
charlesmn 0:3ac96e360672 1730
charlesmn 0:3ac96e360672 1731 #define IGNORE_STATUS(__FUNCTION_ID__, __ERROR_STATUS_CHECK__, __STATUS__) \
charlesmn 0:3ac96e360672 1732 do { \
charlesmn 0:3ac96e360672 1733 DISABLE_WARNINGS(); \
charlesmn 0:3ac96e360672 1734 if (__FUNCTION_ID__) { \
charlesmn 0:3ac96e360672 1735 if (__STATUS__ == __ERROR_STATUS_CHECK__) { \
charlesmn 0:3ac96e360672 1736 __STATUS__ = VL53L1_ERROR_NONE; \
charlesmn 0:3ac96e360672 1737 WARN_OVERRIDE_STATUS(__FUNCTION_ID__); \
charlesmn 0:3ac96e360672 1738 } \
charlesmn 0:3ac96e360672 1739 } \
charlesmn 0:3ac96e360672 1740 ENABLE_WARNINGS(); \
charlesmn 0:3ac96e360672 1741 } \
charlesmn 0:3ac96e360672 1742 while (0)
charlesmn 0:3ac96e360672 1743
charlesmn 0:3ac96e360672 1744 #define VL53L1_COPYSTRING(str, ...) \
charlesmn 0:3ac96e360672 1745 (strncpy(str, ##__VA_ARGS__, VL53L1_MAX_STRING_LENGTH-1))
charlesmn 0:3ac96e360672 1746
charlesmn 0:3ac96e360672 1747 #ifdef __cplusplus
charlesmn 0:3ac96e360672 1748 }
charlesmn 0:3ac96e360672 1749 #endif
charlesmn 0:3ac96e360672 1750
charlesmn 0:3ac96e360672 1751 #endif
charlesmn 0:3ac96e360672 1752
charlesmn 0:3ac96e360672 1753
charlesmn 0:3ac96e360672 1754