Added SX1276 getTemp() method.
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SX1276_LoRaRadio.cpp
00001 /** 00002 / _____) _ | | 00003 ( (____ _____ ____ _| |_ _____ ____| |__ 00004 \____ \| ___ | (_ _) ___ |/ ___) _ \ 00005 _____) ) ____| | | || |_| ____( (___| | | | 00006 (______/|_____)_|_|_| \__)_____)\____)_| |_| 00007 (C)2013 Semtech 00008 ___ _____ _ ___ _ _____ ___ ___ ___ ___ 00009 / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| 00010 \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| 00011 |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| 00012 embedded.connectivity.solutions=============== 00013 00014 Description: LoRaWAN stack layer that controls both MAC and PHY underneath 00015 00016 License: Revised BSD License, see LICENSE.TXT file include in the project 00017 00018 Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) 00019 00020 Copyright (c) 2017, Arm Limited and affiliates. 00021 00022 SPDX-License-Identifier: BSD-3-Clause 00023 */ 00024 00025 #include <stdio.h> 00026 #include <math.h> //rint 00027 #include <string.h> 00028 #include "mbed.h" 00029 #include "SX1276_LoRaRadio.h" 00030 #include "sx1276Regs-Fsk.h" 00031 #include "sx1276Regs-LoRa.h" 00032 00033 /*! 00034 * Sync word for Private LoRa networks 00035 */ 00036 #define LORA_MAC_PRIVATE_SYNCWORD 0x12 00037 00038 /*! 00039 * Sync word for Public LoRa networks 00040 */ 00041 #define LORA_MAC_PUBLIC_SYNCWORD 0x34 00042 00043 /*! 00044 * SX1276 definitions 00045 */ 00046 #define XTAL_FREQ 32000000 00047 #define FREQ_STEP 61.03515625 00048 00049 /*! 00050 * Constant values need to compute the RSSI value 00051 */ 00052 #define RSSI_OFFSET_LF -164.0 00053 #define RSSI_OFFSET_HF -157.0 00054 #define RF_MID_BAND_THRESH 525000000 00055 00056 00057 /*! 00058 * FSK bandwidth definition 00059 */ 00060 typedef struct 00061 { 00062 uint32_t bandwidth; 00063 uint8_t register_value; 00064 } fsk_bw_t; 00065 00066 /*! 00067 * Radio registers definition 00068 */ 00069 typedef struct 00070 { 00071 uint8_t modem; 00072 uint8_t addr; 00073 uint8_t value; 00074 } radio_registers_t; 00075 00076 #define RADIO_INIT_REGISTERS_VALUE \ 00077 { \ 00078 { MODEM_FSK , REG_LNA , 0x23 },\ 00079 { MODEM_FSK , REG_RXCONFIG , 0x1E },\ 00080 { MODEM_FSK , REG_RSSICONFIG , 0xD2 },\ 00081 { MODEM_FSK , REG_AFCFEI , 0x01 },\ 00082 { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },\ 00083 { MODEM_FSK , REG_OSC , 0x07 },\ 00084 { MODEM_FSK , REG_SYNCCONFIG , 0x12 },\ 00085 { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },\ 00086 { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },\ 00087 { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },\ 00088 { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },\ 00089 { MODEM_FSK , REG_FIFOTHRESH , 0x8F },\ 00090 { MODEM_FSK , REG_IMAGECAL , 0x02 },\ 00091 { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },\ 00092 { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },\ 00093 { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },\ 00094 } 00095 00096 static const fsk_bw_t fsk_bandwidths[] = 00097 { 00098 { 2600 , 0x17 }, 00099 { 3100 , 0x0F }, 00100 { 3900 , 0x07 }, 00101 { 5200 , 0x16 }, 00102 { 6300 , 0x0E }, 00103 { 7800 , 0x06 }, 00104 { 10400 , 0x15 }, 00105 { 12500 , 0x0D }, 00106 { 15600 , 0x05 }, 00107 { 20800 , 0x14 }, 00108 { 25000 , 0x0C }, 00109 { 31300 , 0x04 }, 00110 { 41700 , 0x13 }, 00111 { 50000 , 0x0B }, 00112 { 62500 , 0x03 }, 00113 { 83333 , 0x12 }, 00114 { 100000, 0x0A }, 00115 { 125000, 0x02 }, 00116 { 166700, 0x11 }, 00117 { 200000, 0x09 }, 00118 { 250000, 0x01 }, 00119 { 300000, 0x00 }, // Invalid bandwidth 00120 }; 00121 00122 /** 00123 * SPI read/write masks 00124 */ 00125 #define SPI_WRITE_CMD 0x80 00126 #define SPI_READ_CMD 0x7F 00127 00128 /** 00129 * Signals 00130 */ 00131 #define SIG_DIO0 0x01 00132 #define SIG_DIO1 0x02 00133 #define SIG_DIO2 0x04 00134 #define SIG_DIO3 0x08 00135 #define SIG_DIO4 0x10 00136 #define SIG_DIO5 0x20 00137 #define SIG_TIMOUT 0x40 00138 00139 /** 00140 * Radio hardware registers initialization 00141 */ 00142 static const radio_registers_t radio_reg_init[] = RADIO_INIT_REGISTERS_VALUE; 00143 00144 enum RadioVariant { 00145 SX1276UNDEFINED = 0, 00146 SX1276MB1LAS, 00147 SX1276MB1MAS 00148 }; 00149 00150 #ifdef MBED_SX1276_LORA_RADIO_SPI_FREQUENCY 00151 #define SPI_FREQUENCY MBED_SX1276_LORA_RADIO_SPI_FREQUENCY 00152 #else 00153 #define SPI_FREQUENCY 8000000 00154 #endif 00155 00156 /** 00157 * Constructor 00158 */ 00159 SX1276_LoRaRadio::SX1276_LoRaRadio(PinName spi_mosi, 00160 PinName spi_miso, 00161 PinName spi_sclk, 00162 PinName nss, 00163 PinName reset, 00164 PinName dio0, 00165 PinName dio1, 00166 PinName dio2, 00167 PinName dio3, 00168 PinName dio4, 00169 PinName dio5, 00170 PinName rf_switch_ctl1, 00171 PinName rf_switch_ctl2, 00172 PinName txctl, 00173 PinName rxctl, 00174 PinName antswitch, 00175 PinName pwr_amp_ctl, 00176 PinName tcxo) 00177 : _spi(spi_mosi, spi_miso, spi_sclk), 00178 _chip_select(nss, 1), 00179 _reset_ctl(reset), 00180 _dio0_ctl(dio0), _dio1_ctl(dio1), _dio2_ctl(dio2), _dio3_ctl(dio3), _dio4_ctl(dio4), _dio5_ctl(dio5), 00181 _rf_switch_ctl1(rf_switch_ctl1, 0), _rf_switch_ctl2(rf_switch_ctl2, 0), 00182 _txctl(txctl, 0), _rxctl(rxctl, 0), 00183 _ant_switch(antswitch, PIN_INPUT, PullUp, 0), 00184 _pwr_amp_ctl(pwr_amp_ctl), 00185 _tcxo(tcxo) 00186 00187 #ifdef MBED_CONF_RTOS_PRESENT 00188 , irq_thread(osPriorityRealtime, 1024) 00189 #endif 00190 { 00191 _rf_ctrls.ant_switch = antswitch; 00192 _rf_ctrls.pwr_amp_ctl = pwr_amp_ctl; 00193 _rf_ctrls.rf_switch_ctl1 = rf_switch_ctl1; 00194 _rf_ctrls.rf_switch_ctl2 = rf_switch_ctl2; 00195 _rf_ctrls.rxctl = rxctl; 00196 _rf_ctrls.txctl = txctl; 00197 _rf_ctrls.tcxo = tcxo; 00198 00199 _dio4_pin = dio4; 00200 _dio5_pin = dio5; 00201 00202 _radio_events = NULL; 00203 00204 if (tcxo != NC) { 00205 _tcxo = 1; 00206 } 00207 00208 #ifdef MBED_CONF_RTOS_PRESENT 00209 irq_thread.start(mbed::callback(this, &SX1276_LoRaRadio::rf_irq_task)); 00210 #endif 00211 } 00212 00213 /** 00214 * Destructor 00215 */ 00216 SX1276_LoRaRadio::~SX1276_LoRaRadio() 00217 { 00218 00219 } 00220 00221 /***************************************************************************** 00222 * Public APIs * 00223 ****************************************************************************/ 00224 /** 00225 * Acquire lock 00226 */ 00227 void SX1276_LoRaRadio::lock(void) 00228 { 00229 mutex.lock(); 00230 } 00231 00232 /** 00233 * Release lock 00234 */ 00235 void SX1276_LoRaRadio::unlock(void) 00236 { 00237 mutex.unlock(); 00238 } 00239 00240 /** 00241 * Initializes radio module 00242 */ 00243 void SX1276_LoRaRadio::init_radio(radio_events_t *events) 00244 { 00245 _radio_events = events; 00246 00247 // Reset the radio transceiver 00248 radio_reset(); 00249 00250 // Setup radio variant type 00251 set_sx1276_variant_type(); 00252 00253 // setup SPI frequency 00254 // default is 8MHz although, configurable through 00255 // SPI_FREQUENCY macro 00256 setup_spi(); 00257 00258 // Calibrate radio receiver chain 00259 rx_chain_calibration(); 00260 00261 // set radio mode to sleep 00262 set_operation_mode(RF_OPMODE_SLEEP); 00263 00264 // Setup radio registers to defaults 00265 setup_registers(); 00266 00267 // set modem type - defaults to FSK here 00268 set_modem(MODEM_FSK); 00269 00270 // set state to be idle 00271 _rf_settings.state = RF_IDLE; 00272 00273 // Setup interrupts on DIO pins 00274 setup_interrupts(); 00275 } 00276 00277 /** 00278 * Can be used by application/stack or the driver itself 00279 */ 00280 void SX1276_LoRaRadio::radio_reset() 00281 { 00282 _reset_ctl.output(); 00283 _reset_ctl = 0; 00284 wait_ms(2); 00285 _reset_ctl.input(); 00286 wait_ms(6); 00287 } 00288 00289 /** 00290 * TODO: The purpose of this API is unclear. 00291 * Need to start an internal discussion. 00292 */ 00293 bool SX1276_LoRaRadio::check_rf_frequency(uint32_t frequency) 00294 { 00295 // Implement check. Currently all frequencies are supported ? What band ? 00296 return true; 00297 } 00298 00299 /** 00300 * Returns current status of the radio state machine 00301 */ 00302 uint8_t SX1276_LoRaRadio::get_status(void) 00303 { 00304 return _rf_settings.state; 00305 } 00306 00307 /** 00308 * Sets up carrier frequency 00309 */ 00310 void SX1276_LoRaRadio::set_channel(uint32_t freq) 00311 { 00312 _rf_settings.channel = freq; 00313 freq = (uint32_t) ((float) freq / (float) FREQ_STEP); 00314 write_to_register(REG_FRFMSB, (uint8_t) ((freq >> 16) & 0xFF)); 00315 write_to_register(REG_FRFMID, (uint8_t) ((freq >> 8) & 0xFF)); 00316 write_to_register(REG_FRFLSB, (uint8_t) (freq & 0xFF)); 00317 } 00318 00319 /** 00320 * Generates 32 bit random number based upon RSSI monitoring 00321 * Used for various calculation by the stack for example dev nonce 00322 * 00323 * When this API is used modem is set in LoRa mode and all interrupts are 00324 * masked. If the user had been using FSK mode, it should be noted that a 00325 * change of mode is required again because the registers have changed. 00326 * In addition to that RX and TX configuration APIs should be called again in 00327 * order to have correct desires setup. 00328 */ 00329 uint32_t SX1276_LoRaRadio::random( void ) 00330 { 00331 uint8_t i; 00332 uint32_t rnd = 0; 00333 00334 /* 00335 * Radio setup for random number generation 00336 */ 00337 set_modem( MODEM_LORA ); 00338 00339 // Disable LoRa modem interrupts 00340 write_to_register(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00341 RFLR_IRQFLAGS_RXDONE | 00342 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00343 RFLR_IRQFLAGS_VALIDHEADER | 00344 RFLR_IRQFLAGS_TXDONE | 00345 RFLR_IRQFLAGS_CADDONE | 00346 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00347 RFLR_IRQFLAGS_CADDETECTED ); 00348 00349 // Set radio in continuous reception 00350 set_operation_mode(RF_OPMODE_RECEIVER); 00351 00352 for (i = 0; i < 32; i++) { 00353 wait_ms(1); 00354 // Unfiltered RSSI value reading. Only takes the LSB value 00355 rnd |= ((uint32_t) read_register( REG_LR_RSSIWIDEBAND) & 0x01) << i; 00356 } 00357 00358 sleep(); 00359 00360 return rnd; 00361 } 00362 00363 /** 00364 * Sets up receiver related configurations 00365 * 00366 * Must be called before setting the radio in rx mode 00367 */ 00368 void SX1276_LoRaRadio::set_rx_config(radio_modems_t modem, uint32_t bandwidth, 00369 uint32_t datarate, uint8_t coderate, 00370 uint32_t bandwidth_afc, 00371 uint16_t preamble_len, 00372 uint16_t symb_timeout, bool fix_len, 00373 uint8_t payload_len, bool crc_on, 00374 bool freq_hop_on, uint8_t hop_period, 00375 bool iq_inverted, bool rx_continuous) 00376 { 00377 set_modem(modem); 00378 00379 switch (modem) { 00380 case MODEM_FSK: 00381 _rf_settings.fsk.bandwidth = bandwidth; 00382 _rf_settings.fsk.datarate = datarate; 00383 _rf_settings.fsk.bandwidth_afc = bandwidth_afc; 00384 _rf_settings.fsk.fix_len = fix_len; 00385 _rf_settings.fsk.payload_len = payload_len; 00386 _rf_settings.fsk.crc_on = crc_on; 00387 _rf_settings.fsk.iq_inverted = iq_inverted; 00388 _rf_settings.fsk.rx_continuous = rx_continuous; 00389 _rf_settings.fsk.preamble_len = preamble_len; 00390 _rf_settings.fsk.rx_single_timeout = (symb_timeout + 1) / 2; // dividing by 2 as our detector size is 2 symbols (16 bytes) 00391 00392 datarate = (uint16_t) ((float) XTAL_FREQ / (float) datarate); 00393 write_to_register(REG_BITRATEMSB, (uint8_t) (datarate >> 8)); 00394 write_to_register(REG_BITRATELSB, (uint8_t) (datarate & 0xFF)); 00395 00396 write_to_register(REG_RXBW, get_fsk_bw_reg_val(bandwidth)); 00397 write_to_register(REG_AFCBW, get_fsk_bw_reg_val(bandwidth_afc)); 00398 00399 write_to_register(REG_PREAMBLEMSB, (uint8_t) ((preamble_len >> 8) & 0xFF)); 00400 write_to_register(REG_PREAMBLELSB, (uint8_t) (preamble_len & 0xFF)); 00401 00402 if (fix_len == 1) { 00403 write_to_register(REG_PAYLOADLENGTH, payload_len); 00404 } else { 00405 write_to_register(REG_PAYLOADLENGTH, 0xFF); // Set payload length to the maximum 00406 } 00407 00408 write_to_register( 00409 REG_PACKETCONFIG1, 00410 (read_register(REG_PACKETCONFIG1) 00411 & RF_PACKETCONFIG1_CRC_MASK 00412 & RF_PACKETCONFIG1_PACKETFORMAT_MASK) 00413 | ((fix_len == 1) ? 00414 RF_PACKETCONFIG1_PACKETFORMAT_FIXED : 00415 RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE) 00416 | (crc_on << 4)); 00417 00418 // TODO why packet mode 2 ? 00419 write_to_register(REG_PACKETCONFIG2, (read_register(REG_PACKETCONFIG2) 00420 | RF_PACKETCONFIG2_DATAMODE_PACKET)); 00421 00422 break; 00423 00424 case MODEM_LORA: 00425 00426 if (bandwidth > 2) { 00427 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00428 while (1) 00429 ; 00430 // TODO Return a proper error from here 00431 } 00432 00433 // stupid hack. TODO think something better 00434 bandwidth+=7; 00435 00436 _rf_settings.lora.bandwidth = bandwidth; 00437 _rf_settings.lora.datarate = datarate; 00438 _rf_settings.lora.coderate = coderate; 00439 _rf_settings.lora.preamble_len = preamble_len; 00440 _rf_settings.lora.fix_len = fix_len; 00441 _rf_settings.lora.payload_len = payload_len; 00442 _rf_settings.lora.crc_on = crc_on; 00443 _rf_settings.lora.freq_hop_on = freq_hop_on; 00444 _rf_settings.lora.hop_period = hop_period; 00445 _rf_settings.lora.iq_inverted = iq_inverted; 00446 _rf_settings.lora.rx_continuous = rx_continuous; 00447 00448 if (datarate > 12) { 00449 datarate = 12; 00450 } else if (datarate < 6) { 00451 datarate = 6; 00452 } 00453 00454 if (((bandwidth == 7) && ((datarate == 11) || (datarate == 12))) 00455 || ((bandwidth == 8) && (datarate == 12))) { 00456 _rf_settings.lora.low_datarate_optimize = 0x01; 00457 } else { 00458 _rf_settings.lora.low_datarate_optimize = 0x00; 00459 } 00460 00461 write_to_register(REG_LR_MODEMCONFIG1, (read_register( REG_LR_MODEMCONFIG1) 00462 & RFLR_MODEMCONFIG1_BW_MASK 00463 & RFLR_MODEMCONFIG1_CODINGRATE_MASK 00464 & RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK) 00465 | (bandwidth << 4) 00466 | (coderate << 1) | fix_len); 00467 00468 write_to_register(REG_LR_MODEMCONFIG2, (read_register( REG_LR_MODEMCONFIG2) 00469 & RFLR_MODEMCONFIG2_SF_MASK 00470 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 00471 & RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK) 00472 | (datarate << 4) 00473 | (crc_on << 2) 00474 | ((symb_timeout >> 8) 00475 & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK)); 00476 00477 write_to_register(REG_LR_MODEMCONFIG3, (read_register( REG_LR_MODEMCONFIG3) 00478 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK) 00479 | (_rf_settings.lora.low_datarate_optimize << 3)); 00480 00481 write_to_register(REG_LR_SYMBTIMEOUTLSB, (uint8_t) (symb_timeout & 0xFF)); 00482 00483 write_to_register(REG_LR_PREAMBLEMSB, (uint8_t) ((preamble_len >> 8) & 0xFF)); 00484 write_to_register(REG_LR_PREAMBLELSB, (uint8_t) (preamble_len & 0xFF)); 00485 00486 if (fix_len == 1) { 00487 write_to_register(REG_LR_PAYLOADLENGTH, payload_len); 00488 } 00489 00490 if (_rf_settings.lora.freq_hop_on == true) { 00491 write_to_register(REG_LR_PLLHOP, (read_register( REG_LR_PLLHOP) 00492 & RFLR_PLLHOP_FASTHOP_MASK) 00493 | RFLR_PLLHOP_FASTHOP_ON); 00494 write_to_register(REG_LR_HOPPERIOD,_rf_settings.lora.hop_period); 00495 } 00496 00497 if ((bandwidth == 9) && (_rf_settings.channel > RF_MID_BAND_THRESH)) { 00498 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00499 write_to_register(REG_LR_TEST36, 0x02); 00500 write_to_register(REG_LR_TEST3A, 0x64); 00501 } else if (bandwidth == 9) { 00502 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00503 write_to_register(REG_LR_TEST36, 0x02); 00504 write_to_register(REG_LR_TEST3A, 0x7F); 00505 } else { 00506 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00507 write_to_register(REG_LR_TEST36, 0x03); 00508 } 00509 00510 if (datarate == 6) { 00511 write_to_register(REG_LR_DETECTOPTIMIZE, (read_register(REG_LR_DETECTOPTIMIZE) 00512 & RFLR_DETECTIONOPTIMIZE_MASK) 00513 | RFLR_DETECTIONOPTIMIZE_SF6); 00514 write_to_register(REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF6); 00515 } else { 00516 write_to_register(REG_LR_DETECTOPTIMIZE, (read_register(REG_LR_DETECTOPTIMIZE) 00517 & RFLR_DETECTIONOPTIMIZE_MASK) 00518 | RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12); 00519 write_to_register(REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF7_TO_SF12); 00520 } 00521 break; 00522 00523 default: 00524 break; 00525 } 00526 } 00527 00528 /** 00529 * Sets up transmitter related configuration 00530 * 00531 * Must be called before putting the radio module in Tx mode or trying 00532 * to send 00533 */ 00534 void SX1276_LoRaRadio::set_tx_config(radio_modems_t modem, int8_t power, 00535 uint32_t fdev, uint32_t bandwidth, 00536 uint32_t datarate, uint8_t coderate, 00537 uint16_t preamble_len, bool fix_len, 00538 bool crc_on, bool freq_hop_on, 00539 uint8_t hop_period, bool iq_inverted, 00540 uint32_t timeout) 00541 { 00542 set_modem(modem); 00543 set_rf_tx_power(power); 00544 00545 switch (modem) { 00546 case MODEM_FSK: 00547 _rf_settings.fsk.power = power; 00548 _rf_settings.fsk.f_dev = fdev; 00549 _rf_settings.fsk.bandwidth = bandwidth; 00550 _rf_settings.fsk.datarate = datarate; 00551 _rf_settings.fsk.preamble_len = preamble_len; 00552 _rf_settings.fsk.fix_len = fix_len; 00553 _rf_settings.fsk.crc_on = crc_on; 00554 _rf_settings.fsk.iq_inverted = iq_inverted; 00555 _rf_settings.fsk.tx_timeout = timeout; 00556 00557 fdev = (uint16_t) ((float) fdev / (float) FREQ_STEP); 00558 write_to_register( REG_FDEVMSB, (uint8_t) (fdev >> 8)); 00559 write_to_register( REG_FDEVLSB, (uint8_t) (fdev & 0xFF)); 00560 00561 datarate = (uint16_t) ((float) XTAL_FREQ / (float) datarate); 00562 write_to_register( REG_BITRATEMSB, (uint8_t) (datarate >> 8)); 00563 write_to_register( REG_BITRATELSB, (uint8_t) (datarate & 0xFF)); 00564 00565 write_to_register( REG_PREAMBLEMSB, (preamble_len >> 8) & 0x00FF); 00566 write_to_register( REG_PREAMBLELSB, preamble_len & 0xFF); 00567 00568 write_to_register(REG_PACKETCONFIG1, 00569 (read_register( REG_PACKETCONFIG1) & 00570 RF_PACKETCONFIG1_CRC_MASK & 00571 RF_PACKETCONFIG1_PACKETFORMAT_MASK) 00572 | ((fix_len == 1) ? 00573 RF_PACKETCONFIG1_PACKETFORMAT_FIXED : 00574 RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE) 00575 | (crc_on << 4)); 00576 write_to_register(REG_PACKETCONFIG2, 00577 (read_register( REG_PACKETCONFIG2) 00578 | RF_PACKETCONFIG2_DATAMODE_PACKET)); 00579 00580 break; 00581 00582 case MODEM_LORA: 00583 _rf_settings.lora.power = power; 00584 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00585 MBED_ASSERT(bandwidth <= 2); 00586 bandwidth += 7; 00587 _rf_settings.lora.bandwidth = bandwidth; 00588 _rf_settings.lora.datarate = datarate; 00589 _rf_settings.lora.coderate = coderate; 00590 _rf_settings.lora.preamble_len = preamble_len; 00591 _rf_settings.lora.fix_len = fix_len; 00592 _rf_settings.lora.freq_hop_on = freq_hop_on; 00593 _rf_settings.lora.hop_period = hop_period; 00594 _rf_settings.lora.crc_on = crc_on; 00595 _rf_settings.lora.iq_inverted = iq_inverted; 00596 _rf_settings.lora.tx_timeout = timeout; 00597 00598 if (datarate > 12) { 00599 datarate = 12; 00600 } else if (datarate < 6) { 00601 datarate = 6; 00602 } 00603 if (((bandwidth == 7) && ((datarate == 11) || (datarate == 12))) 00604 || ((bandwidth == 8) && (datarate == 12))) { 00605 _rf_settings.lora.low_datarate_optimize = 0x01; 00606 } else { 00607 _rf_settings.lora.low_datarate_optimize = 0x00; 00608 } 00609 00610 if (_rf_settings.lora.freq_hop_on == true) { 00611 write_to_register(REG_LR_PLLHOP, (read_register(REG_LR_PLLHOP) 00612 & RFLR_PLLHOP_FASTHOP_MASK) 00613 | RFLR_PLLHOP_FASTHOP_ON); 00614 write_to_register( REG_LR_HOPPERIOD, _rf_settings.lora.hop_period); 00615 } 00616 00617 write_to_register(REG_LR_MODEMCONFIG1, (read_register( REG_LR_MODEMCONFIG1) 00618 & RFLR_MODEMCONFIG1_BW_MASK 00619 & RFLR_MODEMCONFIG1_CODINGRATE_MASK 00620 & RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK) | (bandwidth << 4) 00621 | (coderate << 1) | fix_len); 00622 00623 write_to_register(REG_LR_MODEMCONFIG2, (read_register( REG_LR_MODEMCONFIG2) 00624 & RFLR_MODEMCONFIG2_SF_MASK 00625 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK) 00626 | (datarate << 4) 00627 | (crc_on << 2)); 00628 00629 write_to_register(REG_LR_MODEMCONFIG3, (read_register(REG_LR_MODEMCONFIG3) 00630 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK) 00631 | (_rf_settings.lora.low_datarate_optimize << 3)); 00632 00633 write_to_register(REG_LR_PREAMBLEMSB, (preamble_len >> 8) & 0x00FF); 00634 write_to_register(REG_LR_PREAMBLELSB, preamble_len & 0xFF); 00635 00636 if (datarate == 6) { 00637 write_to_register(REG_LR_DETECTOPTIMIZE, (read_register( REG_LR_DETECTOPTIMIZE) 00638 & RFLR_DETECTIONOPTIMIZE_MASK) | RFLR_DETECTIONOPTIMIZE_SF6); 00639 write_to_register(REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF6); 00640 } else { 00641 write_to_register(REG_LR_DETECTOPTIMIZE, (read_register( REG_LR_DETECTOPTIMIZE) 00642 & RFLR_DETECTIONOPTIMIZE_MASK) | RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12); 00643 write_to_register( REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF7_TO_SF12); 00644 } 00645 00646 break; 00647 } 00648 } 00649 00650 /** 00651 * Calculates time on Air i.e., dwell time for a single packet 00652 * 00653 * Crucial for the stack in order to calculate dwell time so as to control 00654 * duty cycling. 00655 */ 00656 uint32_t SX1276_LoRaRadio::time_on_air(radio_modems_t modem, uint8_t pkt_len) 00657 { 00658 uint32_t airTime = 0; 00659 00660 switch (modem) { 00661 case MODEM_FSK: 00662 airTime = 00663 rint((8 * (_rf_settings.fsk.preamble_len 00664 + ((read_register( REG_SYNCCONFIG) 00665 & ~RF_SYNCCONFIG_SYNCSIZE_MASK) + 1) 00666 + ((_rf_settings.fsk.fix_len == 0x01) ? 00667 0.0f : 1.0f) 00668 + (((read_register( REG_PACKETCONFIG1) 00669 & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK) 00670 != 0x00) ? 1.0f : 0) + pkt_len 00671 + ((_rf_settings.fsk.crc_on == 0x01) ? 00672 2.0 : 0)) 00673 / _rf_settings.fsk.datarate) * 1000); 00674 00675 break; 00676 case MODEM_LORA: 00677 float bw = 0.0f; 00678 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00679 switch (_rf_settings.lora.bandwidth) { 00680 //case 0: // 7.8 kHz 00681 // bw = 78e2; 00682 // break; 00683 //case 1: // 10.4 kHz 00684 // bw = 104e2; 00685 // break; 00686 //case 2: // 15.6 kHz 00687 // bw = 156e2; 00688 // break; 00689 //case 3: // 20.8 kHz 00690 // bw = 208e2; 00691 // break; 00692 //case 4: // 31.2 kHz 00693 // bw = 312e2; 00694 // break; 00695 //case 5: // 41.4 kHz 00696 // bw = 414e2; 00697 // break; 00698 //case 6: // 62.5 kHz 00699 // bw = 625e2; 00700 // break; 00701 case 7: // 125 kHz 00702 bw = 125000; 00703 break; 00704 case 8: // 250 kHz 00705 bw = 250000; 00706 break; 00707 case 9: // 500 kHz 00708 bw = 500000; 00709 break; 00710 } 00711 00712 // Symbol rate : time for one symbol (secs) 00713 float rs = bw / (1 << _rf_settings.lora.datarate); 00714 float ts = 1 / rs; 00715 // time of preamble 00716 float tPreamble = (_rf_settings.lora.preamble_len + 4.25f) * ts; 00717 // Symbol length of payload and time 00718 float tmp = ceil((8 * pkt_len - 4 * _rf_settings.lora.datarate + 28 00719 + 16 * _rf_settings.lora.crc_on 00720 - (_rf_settings.lora.fix_len ? 20 : 0)) 00721 / (float) (4 00722 * (_rf_settings.lora.datarate 00723 - ((_rf_settings.lora.low_datarate_optimize > 0) 00724 ? 2 : 0)))) 00725 * (_rf_settings.lora.coderate + 4); 00726 float nPayload = 8 + ((tmp > 0) ? tmp : 0); 00727 float tPayload = nPayload * ts; 00728 // Time on air 00729 float tOnAir = tPreamble + tPayload; 00730 // return ms secs 00731 airTime = floor(tOnAir * 1000 + 0.999f); 00732 00733 break; 00734 } 00735 00736 return airTime; 00737 } 00738 00739 /** 00740 * Prepares and sends the radio packet out in the air 00741 */ 00742 void SX1276_LoRaRadio::send(uint8_t *buffer, uint8_t size) 00743 { 00744 uint32_t tx_timeout = 0; 00745 00746 switch (_rf_settings.modem) { 00747 case MODEM_FSK: 00748 _rf_settings.fsk_packet_handler.nb_bytes = 0; 00749 _rf_settings.fsk_packet_handler.size = size; 00750 00751 if (_rf_settings.fsk.fix_len == false) { 00752 write_fifo((uint8_t*) &size, 1); 00753 } else { 00754 write_to_register(REG_PAYLOADLENGTH, size); 00755 } 00756 00757 if ((size > 0) && (size <= 64)) { 00758 _rf_settings.fsk_packet_handler.chunk_size = size; 00759 } else { 00760 memcpy(_data_buffer, buffer, size); 00761 _rf_settings.fsk_packet_handler.chunk_size = 32; 00762 } 00763 00764 // Write payload buffer 00765 write_fifo(buffer, _rf_settings.fsk_packet_handler.chunk_size); 00766 _rf_settings.fsk_packet_handler.nb_bytes += 00767 _rf_settings.fsk_packet_handler.chunk_size; 00768 tx_timeout = _rf_settings.fsk.tx_timeout; 00769 00770 break; 00771 00772 case MODEM_LORA: 00773 if (_rf_settings.lora.iq_inverted == true) { 00774 write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) 00775 & RFLR_INVERTIQ_TX_MASK 00776 & RFLR_INVERTIQ_RX_MASK) 00777 | RFLR_INVERTIQ_RX_OFF 00778 | RFLR_INVERTIQ_TX_ON)); 00779 write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON); 00780 } else { 00781 write_to_register(REG_LR_INVERTIQ, ((read_register( REG_LR_INVERTIQ) 00782 & RFLR_INVERTIQ_TX_MASK 00783 & RFLR_INVERTIQ_RX_MASK) 00784 | RFLR_INVERTIQ_RX_OFF 00785 | RFLR_INVERTIQ_TX_OFF)); 00786 write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF); 00787 } 00788 00789 _rf_settings.lora_packet_handler.size = size; 00790 00791 // Initializes the payload size 00792 write_to_register(REG_LR_PAYLOADLENGTH, size); 00793 00794 // Full buffer used for Tx 00795 write_to_register(REG_LR_FIFOTXBASEADDR, 0); 00796 write_to_register(REG_LR_FIFOADDRPTR, 0); 00797 00798 // FIFO operations can not take place in Sleep mode 00799 if ((read_register( REG_OPMODE) & ~RF_OPMODE_MASK) == RF_OPMODE_SLEEP) { 00800 standby(); 00801 wait_ms(1); 00802 } 00803 // write_to_register payload buffer 00804 write_fifo(buffer, size); 00805 tx_timeout = _rf_settings.lora.tx_timeout; 00806 00807 break; 00808 } 00809 00810 transmit(tx_timeout); 00811 } 00812 00813 /** 00814 * sets the radio module to sleep 00815 */ 00816 00817 void SX1276_LoRaRadio::sleep() 00818 { 00819 // stop timers 00820 tx_timeout_timer.detach(); 00821 00822 // put module in sleep mode 00823 set_operation_mode(RF_OPMODE_SLEEP); 00824 } 00825 00826 /** 00827 * Put radio in Standby mode 00828 */ 00829 void SX1276_LoRaRadio::standby( void ) 00830 { 00831 tx_timeout_timer.detach(); 00832 00833 set_operation_mode(RF_OPMODE_STANDBY); 00834 _rf_settings.state = RF_IDLE; 00835 } 00836 00837 /** 00838 * Sets the radio module in receive mode 00839 * 00840 * A DIO4 interrupt let's the state machine know that a preamble is detected 00841 * and finally a DIO0 interrupt let's the state machine know that a packet is 00842 * ready to be read from the FIFO 00843 */ 00844 void SX1276_LoRaRadio::receive(void) 00845 { 00846 switch (_rf_settings.modem) { 00847 case MODEM_FSK: 00848 00849 // DIO0=PayloadReady/PacketSent 00850 // DIO1=FifoLevel 00851 // DIO2=RxTimeout 00852 // DIO3=FifoEmpty? 00853 // DIO4=PreambleDetect 00854 // DIO5=ModeReady? 00855 write_to_register(REG_DIOMAPPING1, (read_register( REG_DIOMAPPING1) 00856 & RF_DIOMAPPING1_DIO0_MASK 00857 & RF_DIOMAPPING1_DIO1_MASK 00858 & RF_DIOMAPPING1_DIO2_MASK) 00859 | RF_DIOMAPPING1_DIO0_00 00860 | RF_DIOMAPPING1_DIO1_00 00861 | RF_DIOMAPPING1_DIO2_10); 00862 00863 write_to_register(REG_DIOMAPPING2, (read_register( REG_DIOMAPPING2) 00864 & RF_DIOMAPPING2_DIO4_MASK 00865 & RF_DIOMAPPING2_MAP_MASK) 00866 | RF_DIOMAPPING2_DIO4_11 00867 | RF_DIOMAPPING2_MAP_PREAMBLEDETECT); 00868 00869 _rf_settings.fsk_packet_handler.fifo_thresh = 00870 read_register(REG_FIFOTHRESH) & 0x3F; 00871 00872 write_to_register(REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON 00873 | RF_RXCONFIG_AGCAUTO_ON 00874 | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT); 00875 00876 if (!_rf_settings.fsk.rx_continuous) { 00877 // the value for rx timeout in symbols cannot be more than 255 00878 // as the preamble length is fixed. We assert here for quick 00879 // diagnostics 00880 MBED_ASSERT(_rf_settings.fsk.rx_single_timeout <= 255); 00881 write_to_register(REG_RXTIMEOUT2, _rf_settings.fsk.rx_single_timeout); 00882 write_to_register(REG_RXTIMEOUT3, 0x00); 00883 write_to_register(REG_RXTIMEOUT1, 0x00); 00884 } 00885 00886 _rf_settings.fsk_packet_handler.preamble_detected = 0; 00887 _rf_settings.fsk_packet_handler.sync_word_detected = 0; 00888 _rf_settings.fsk_packet_handler.nb_bytes = 0; 00889 _rf_settings.fsk_packet_handler.size = 0; 00890 00891 break; 00892 00893 case MODEM_LORA: 00894 00895 if (_rf_settings.lora.iq_inverted == true) { 00896 write_to_register(REG_LR_INVERTIQ, ((read_register( REG_LR_INVERTIQ) 00897 & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK) 00898 | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF)); 00899 write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON); 00900 } else { 00901 write_to_register(REG_LR_INVERTIQ, ((read_register( REG_LR_INVERTIQ) 00902 & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK) 00903 | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF)); 00904 write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF); 00905 } 00906 00907 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal 00908 if (_rf_settings.lora.bandwidth < 9) { 00909 write_to_register(REG_LR_DETECTOPTIMIZE, 00910 read_register(REG_LR_DETECTOPTIMIZE) & 0x7F); 00911 write_to_register(REG_LR_TEST30, 0x00); 00912 switch (_rf_settings.lora.bandwidth) { 00913 case 0: // 7.8 kHz 00914 write_to_register( REG_LR_TEST2F, 0x48); 00915 set_channel(_rf_settings.channel + 7.81e3); 00916 break; 00917 case 1: // 10.4 kHz 00918 write_to_register( REG_LR_TEST2F, 0x44); 00919 set_channel(_rf_settings.channel + 10.42e3); 00920 break; 00921 case 2: // 15.6 kHz 00922 write_to_register( REG_LR_TEST2F, 0x44); 00923 set_channel(_rf_settings.channel + 15.62e3); 00924 break; 00925 case 3: // 20.8 kHz 00926 write_to_register( REG_LR_TEST2F, 0x44); 00927 set_channel(_rf_settings.channel + 20.83e3); 00928 break; 00929 case 4: // 31.2 kHz 00930 write_to_register( REG_LR_TEST2F, 0x44); 00931 set_channel(_rf_settings.channel + 31.25e3); 00932 break; 00933 case 5: // 41.4 kHz 00934 write_to_register( REG_LR_TEST2F, 0x44); 00935 set_channel(_rf_settings.channel + 41.67e3); 00936 break; 00937 case 6: // 62.5 kHz 00938 write_to_register( REG_LR_TEST2F, 0x40); 00939 break; 00940 case 7: // 125 kHz 00941 write_to_register( REG_LR_TEST2F, 0x40); 00942 break; 00943 case 8: // 250 kHz 00944 write_to_register( REG_LR_TEST2F, 0x40); 00945 break; 00946 } 00947 } else { 00948 write_to_register( REG_LR_DETECTOPTIMIZE, 00949 read_register( REG_LR_DETECTOPTIMIZE) | 0x80); 00950 } 00951 00952 if (_rf_settings.lora.freq_hop_on == true) { 00953 write_to_register(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_VALIDHEADER 00954 | RFLR_IRQFLAGS_TXDONE 00955 | RFLR_IRQFLAGS_CADDONE 00956 | RFLR_IRQFLAGS_CADDETECTED); 00957 00958 // DIO0=RxDone, DIO2=FhssChangeChannel 00959 write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) 00960 & RFLR_DIOMAPPING1_DIO0_MASK 00961 & RFLR_DIOMAPPING1_DIO2_MASK) 00962 | RFLR_DIOMAPPING1_DIO0_00 00963 | RFLR_DIOMAPPING1_DIO2_00); 00964 } else { 00965 write_to_register(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_VALIDHEADER 00966 | RFLR_IRQFLAGS_TXDONE 00967 | RFLR_IRQFLAGS_CADDONE 00968 | RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 00969 | RFLR_IRQFLAGS_CADDETECTED); 00970 00971 // DIO0=RxDone 00972 write_to_register(REG_DIOMAPPING1, (read_register( REG_DIOMAPPING1) 00973 & RFLR_DIOMAPPING1_DIO0_MASK) 00974 | RFLR_DIOMAPPING1_DIO0_00); 00975 } 00976 write_to_register(REG_LR_FIFORXBASEADDR, 0); 00977 write_to_register(REG_LR_FIFOADDRPTR, 0); 00978 00979 break; 00980 } 00981 00982 memset(_data_buffer, 0, (size_t) MAX_DATA_BUFFER_SIZE_SX1276); 00983 00984 _rf_settings.state = RF_RX_RUNNING; 00985 00986 if (_rf_settings.modem == MODEM_FSK) { 00987 set_operation_mode(RF_OPMODE_RECEIVER); 00988 return; 00989 } 00990 00991 // If mode is LoRa set mode 00992 if (_rf_settings.lora.rx_continuous == true) { 00993 set_operation_mode(RFLR_OPMODE_RECEIVER); 00994 } else { 00995 set_operation_mode(RFLR_OPMODE_RECEIVER_SINGLE); 00996 } 00997 } 00998 00999 01000 /** 01001 * Perform carrier sensing 01002 * 01003 * Checks for a certain time if the RSSI is above a given threshold. 01004 * This threshold determines if there is already a transmission going on 01005 * in the channel or not. 01006 * 01007 */ 01008 bool SX1276_LoRaRadio::perform_carrier_sense(radio_modems_t modem, 01009 uint32_t freq, 01010 int16_t rssi_threshold, 01011 uint32_t max_carrier_sense_time) 01012 { 01013 bool status = true; 01014 int16_t rssi = 0; 01015 01016 set_modem(modem); 01017 set_channel(freq); 01018 set_operation_mode(RF_OPMODE_RECEIVER); 01019 01020 // hold on a bit, radio turn-around time 01021 wait_ms(1); 01022 01023 Timer elapsed_time; 01024 elapsed_time.start(); 01025 01026 // Perform carrier sense for maxCarrierSenseTime 01027 while (elapsed_time.read_ms() < (int)max_carrier_sense_time) { 01028 rssi = get_rssi(modem); 01029 01030 if (rssi > rssi_threshold) { 01031 status = false; 01032 break; 01033 } 01034 } 01035 01036 sleep(); 01037 return status; 01038 } 01039 01040 /** 01041 * TODO: Making sure if this API is valid only for LoRa modulation ? 01042 * 01043 * Indicates if the node is part of a private or public network 01044 */ 01045 void SX1276_LoRaRadio::set_public_network(bool enable) 01046 { 01047 set_modem(MODEM_LORA); 01048 01049 _rf_settings.lora.public_network = enable; 01050 if (enable == true) { 01051 // Change lora modem SyncWord 01052 write_to_register(REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD); 01053 } else { 01054 // Change lora modem SyncWord 01055 write_to_register(REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD); 01056 } 01057 } 01058 01059 /** 01060 * Puts a limit on the size of payload the module can handle 01061 * By default it is MAX, i.e., 256 bytes 01062 */ 01063 void SX1276_LoRaRadio::set_max_payload_length(radio_modems_t modem, uint8_t max) 01064 { 01065 set_modem(modem); 01066 01067 switch (modem) { 01068 case MODEM_FSK: 01069 if (_rf_settings.fsk.fix_len == false) { 01070 write_to_register(REG_PAYLOADLENGTH, max); 01071 } 01072 break; 01073 case MODEM_LORA: 01074 write_to_register(REG_LR_PAYLOADMAXLENGTH, max); 01075 break; 01076 } 01077 } 01078 01079 /** 01080 * Channel Activity detection (can be done only in LoRa mode) 01081 * 01082 * If any activity on the channel is detected, an interrupt is asserted on 01083 * DIO3. A callback will be generated to the stack/application upon the 01084 * assertion of DIO3. 01085 */ 01086 void SX1276_LoRaRadio::start_cad() 01087 { 01088 uint8_t reg_val; 01089 01090 switch (_rf_settings.modem) { 01091 case MODEM_FSK: 01092 break; 01093 case MODEM_LORA: 01094 write_to_register(REG_LR_IRQFLAGSMASK, 01095 RFLR_IRQFLAGS_RXTIMEOUT | 01096 RFLR_IRQFLAGS_RXDONE | 01097 RFLR_IRQFLAGS_PAYLOADCRCERROR | 01098 RFLR_IRQFLAGS_VALIDHEADER | 01099 RFLR_IRQFLAGS_TXDONE | 01100 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL); 01101 01102 // DIO3=CADDone 01103 reg_val = read_register(REG_DIOMAPPING1); 01104 write_to_register(REG_DIOMAPPING1, (reg_val & 01105 RFLR_DIOMAPPING1_DIO3_MASK) | 01106 RFLR_DIOMAPPING1_DIO3_00); 01107 01108 set_operation_mode(RFLR_OPMODE_CAD); 01109 01110 _rf_settings.state = RF_CAD; 01111 01112 break; 01113 default: 01114 break; 01115 } 01116 } 01117 01118 /** 01119 * Set transmission in continuous wave mode 01120 */ 01121 void SX1276_LoRaRadio::set_tx_continuous_wave(uint32_t freq, int8_t power, 01122 uint16_t time) 01123 { 01124 uint8_t reg_val; 01125 01126 set_channel(freq); 01127 set_tx_config(MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, time * 1000); 01128 reg_val = read_register(REG_PACKETCONFIG2); 01129 01130 write_to_register( REG_PACKETCONFIG2, (reg_val & RF_PACKETCONFIG2_DATAMODE_MASK ) ); 01131 // Disable radio interrupts 01132 write_to_register( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 ); 01133 write_to_register( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 ); 01134 01135 _rf_settings.state = RF_TX_RUNNING; 01136 tx_timeout_timer.attach_us(callback(this, &SX1276_LoRaRadio::timeout_irq_isr), time * 1000000); 01137 set_operation_mode(RF_OPMODE_TRANSMITTER); 01138 } 01139 01140 /***************************************************************************** 01141 * Private APIs * 01142 ****************************************************************************/ 01143 #ifdef MBED_CONF_RTOS_PRESENT 01144 /** 01145 * Thread task handling IRQs 01146 */ 01147 void SX1276_LoRaRadio::rf_irq_task(void) 01148 { 01149 for (;;) { 01150 osEvent event = irq_thread.signal_wait(0, osWaitForever); 01151 if (event.status != osEventSignal) { 01152 continue; 01153 } 01154 01155 lock(); 01156 if (event.value.signals & SIG_DIO0) { 01157 handle_dio0_irq(); 01158 } 01159 if (event.value.signals & SIG_DIO1) { 01160 handle_dio1_irq(); 01161 } 01162 if (event.value.signals & SIG_DIO2) { 01163 handle_dio2_irq(); 01164 } 01165 if (event.value.signals & SIG_DIO3) { 01166 handle_dio3_irq(); 01167 } 01168 if (event.value.signals & SIG_DIO4) { 01169 handle_dio4_irq(); 01170 } 01171 if (event.value.signals & SIG_DIO5) { 01172 handle_dio5_irq(); 01173 } 01174 if (event.value.signals & SIG_TIMOUT) { 01175 handle_timeout_irq(); 01176 } 01177 unlock(); 01178 } 01179 } 01180 #endif 01181 01182 /** 01183 * Writes a single byte to a given register 01184 */ 01185 void SX1276_LoRaRadio::write_to_register(uint8_t addr, uint8_t data) 01186 { 01187 write_to_register(addr, &data, 1); 01188 } 01189 01190 /** 01191 * Writes multiple bytes to a given register 01192 */ 01193 void SX1276_LoRaRadio::write_to_register(uint8_t addr, uint8_t *data, uint8_t size) 01194 { 01195 // set chip-select low 01196 _chip_select = 0; 01197 01198 // set write command 01199 _spi.write(addr | SPI_WRITE_CMD); 01200 01201 // write data 01202 for (uint8_t i = 0; i < size; i++) { 01203 _spi.write(data[i]); 01204 } 01205 01206 // set chip-select high 01207 _chip_select = 1; 01208 } 01209 01210 /** 01211 * Reads the value of a single register 01212 */ 01213 uint8_t SX1276_LoRaRadio::read_register(uint8_t addr) 01214 { 01215 uint8_t data; 01216 read_register(addr, &data, 1); 01217 return data; 01218 } 01219 01220 /** 01221 * Reads multiple values from a given register 01222 */ 01223 void SX1276_LoRaRadio::read_register(uint8_t addr, uint8_t *buffer, uint8_t size) 01224 { 01225 // set chip-select low 01226 _chip_select = 0; 01227 01228 // set read command 01229 _spi.write(addr & SPI_READ_CMD); 01230 01231 // read buffers 01232 for (uint8_t i = 0; i < size; i++) { 01233 buffer[i] = _spi.write(0); 01234 } 01235 01236 // set chip-select high 01237 _chip_select = 1; 01238 } 01239 01240 /** 01241 * Writes to FIIO provided by the chip 01242 */ 01243 void SX1276_LoRaRadio::write_fifo(uint8_t *buffer, uint8_t size) 01244 { 01245 write_to_register(0, buffer, size); 01246 } 01247 01248 /** 01249 * Reads from the FIFO provided by the chip 01250 */ 01251 void SX1276_LoRaRadio::read_fifo(uint8_t *buffer, uint8_t size) 01252 { 01253 read_register(0, buffer, size); 01254 } 01255 01256 /** 01257 * Sets up operation mode 01258 */ 01259 void SX1276_LoRaRadio::set_operation_mode(uint8_t mode) 01260 { 01261 if (mode == RF_OPMODE_SLEEP) { 01262 set_low_power_mode(); 01263 } else { 01264 set_low_power_mode(); 01265 set_antenna_switch(mode); 01266 } 01267 01268 write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RF_OPMODE_MASK) | mode); 01269 } 01270 01271 /** 01272 * Sets the modem type to use 01273 * 01274 * At initialization FSK is chosen. Later stack or application 01275 * can choose to change. 01276 */ 01277 void SX1276_LoRaRadio::set_modem(uint8_t modem ) 01278 { 01279 if ((read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_ON) != 0 ) { 01280 _rf_settings.modem = MODEM_LORA; 01281 } else { 01282 _rf_settings.modem = MODEM_FSK; 01283 } 01284 01285 if(_rf_settings.modem == modem ) { 01286 // if the modem is already set 01287 return; 01288 } 01289 01290 _rf_settings.modem = modem; 01291 01292 switch(_rf_settings.modem) 01293 { 01294 default: 01295 case MODEM_FSK: 01296 // before changing modem mode, put the module to sleep 01297 sleep(); 01298 write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK) 01299 | RFLR_OPMODE_LONGRANGEMODE_OFF); 01300 01301 // Datasheet Tables 28, 29 DIO mapping 01302 write_to_register(REG_DIOMAPPING1, 0x00); // sets DIO0-DI03 in default mode 01303 write_to_register(REG_DIOMAPPING2, 0x30); // bits 4-5 are turned on i.e., 01304 // DIO5 and DIO4=ModeReady 01305 break; 01306 case MODEM_LORA: 01307 sleep(); 01308 write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK) 01309 | RFLR_OPMODE_LONGRANGEMODE_ON); 01310 01311 // Datasheet Tables 17 DIO mapping for LoRa 01312 // set to defaults 01313 write_to_register(REG_DIOMAPPING1, 0x00); // DIO0 - DIO3 defaults 01314 write_to_register(REG_DIOMAPPING2, 0x00); // DIO4 - DIO5 defaults 01315 01316 break; 01317 } 01318 } 01319 01320 /** 01321 * Set the radio module variant 01322 */ 01323 void SX1276_LoRaRadio::set_sx1276_variant_type() 01324 { 01325 if (_rf_ctrls.ant_switch != NC) { 01326 _ant_switch.input(); 01327 wait_ms(1); 01328 if (_ant_switch == 1) { 01329 radio_variant = SX1276MB1LAS; 01330 } else { 01331 radio_variant = SX1276MB1MAS; 01332 } 01333 _ant_switch.output(); 01334 wait_ms(1); 01335 } else { 01336 radio_variant = SX1276UNDEFINED; 01337 } 01338 } 01339 01340 /** 01341 * Sets up frequency for SPI module 01342 * Reference DataSheet: 4.3 SPI Interface 01343 */ 01344 void SX1276_LoRaRadio::setup_spi() 01345 { 01346 // SPI bus frequency 01347 uint32_t spi_freq = SPI_FREQUENCY; 01348 01349 // Hold chip-select high 01350 _chip_select = 1; 01351 _spi.format(8, 0); 01352 01353 #if defined (TARGET_KL25Z) 01354 //bus-clock frequency is halved -> double the SPI frequency to compensate 01355 _spi.frequency(spi_freq * 2); 01356 #else 01357 // otherwise use default SPI frequency which is 8 MHz 01358 _spi.frequency(spi_freq); 01359 #endif 01360 // 100 us wait to settle down 01361 wait(0.1); 01362 } 01363 01364 /** 01365 * Sets the radio registers to defaults 01366 */ 01367 void SX1276_LoRaRadio::setup_registers() 01368 { 01369 for (unsigned int i = 0; i < sizeof(radio_reg_init) / sizeof(radio_registers_t); i++) { 01370 set_modem(radio_reg_init[i].modem); 01371 write_to_register(radio_reg_init[i].addr, radio_reg_init[i].value); 01372 } 01373 } 01374 01375 /** 01376 * Performs the Rx chain calibration for LF and HF bands 01377 * 01378 * Must be called just after the reset so all registers are at their 01379 * default values. 01380 */ 01381 void SX1276_LoRaRadio::rx_chain_calibration(void) 01382 { 01383 uint8_t regPaConfigInitVal; 01384 uint32_t initialFreq; 01385 01386 // Save context 01387 regPaConfigInitVal = read_register( REG_PACONFIG ); 01388 initialFreq = (float) (((uint32_t) this->read_register(REG_FRFMSB) << 16) | 01389 ((uint32_t) this->read_register(REG_FRFMID) << 8 ) | 01390 ((uint32_t)this->read_register(REG_FRFLSB))) * (float) FREQ_STEP; 01391 01392 // Cut the PA just in case, RFO output, power = -1 dBm 01393 write_to_register(REG_PACONFIG, 0x00); 01394 01395 // Launch Rx chain calibration for LF band 01396 write_to_register (REG_IMAGECAL, (read_register(REG_IMAGECAL) 01397 & RF_IMAGECAL_IMAGECAL_MASK) 01398 | RF_IMAGECAL_IMAGECAL_START); 01399 while((read_register(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_RUNNING ) 01400 == RF_IMAGECAL_IMAGECAL_RUNNING ) 01401 { 01402 } 01403 01404 // Sets a Frequency in HF band 01405 set_channel(868000000); 01406 01407 // Launch Rx chain calibration for HF band 01408 write_to_register (REG_IMAGECAL, (read_register(REG_IMAGECAL) 01409 & RF_IMAGECAL_IMAGECAL_MASK ) 01410 | RF_IMAGECAL_IMAGECAL_START ); 01411 while((read_register(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_RUNNING ) 01412 == RF_IMAGECAL_IMAGECAL_RUNNING ) 01413 { 01414 // do nothing, just wait while rf image frequency calibration is done 01415 } 01416 01417 // Restore context 01418 write_to_register( REG_PACONFIG, regPaConfigInitVal ); 01419 set_channel(initialFreq); 01420 } 01421 01422 /** 01423 * Gets FSK bandwidth values 01424 * 01425 * Gives either normal bandwidths or bandwidths for 01426 * AFC (auto frequency correction) 01427 */ 01428 uint8_t SX1276_LoRaRadio::get_fsk_bw_reg_val(uint32_t bandwidth) 01429 { 01430 uint8_t i; 01431 01432 for (i = 0; i < (sizeof(fsk_bandwidths) / sizeof(fsk_bw_t)) - 1; i++) { 01433 if ((bandwidth >= fsk_bandwidths[i].bandwidth) 01434 && (bandwidth < fsk_bandwidths[i + 1].bandwidth)) { 01435 return fsk_bandwidths[i].register_value; 01436 } 01437 } 01438 // ERROR: Value not found 01439 // This should never happen 01440 while (1); 01441 } 01442 01443 uint8_t SX1276_LoRaRadio::get_pa_conf_reg(uint32_t channel) 01444 { 01445 if (radio_variant == SX1276UNDEFINED) { 01446 return RF_PACONFIG_PASELECT_PABOOST; 01447 } else if (channel > RF_MID_BAND_THRESH) { 01448 if (radio_variant == SX1276MB1LAS) { 01449 return RF_PACONFIG_PASELECT_PABOOST; 01450 } else { 01451 return RF_PACONFIG_PASELECT_RFO; 01452 } 01453 } else { 01454 return RF_PACONFIG_PASELECT_RFO; 01455 } 01456 } 01457 01458 /** 01459 * Sets the transmit power for the module 01460 */ 01461 void SX1276_LoRaRadio::set_rf_tx_power(int8_t power) 01462 { 01463 01464 uint8_t paConfig = 0; 01465 uint8_t paDac = 0; 01466 01467 paConfig = read_register(REG_PACONFIG); 01468 paDac = read_register(REG_PADAC); 01469 01470 paConfig = (paConfig & RF_PACONFIG_PASELECT_MASK) | get_pa_conf_reg(_rf_settings.channel); 01471 paConfig = (paConfig & RF_PACONFIG_MAX_POWER_MASK) | 0x70; 01472 01473 if ((paConfig & RF_PACONFIG_PASELECT_PABOOST) == RF_PACONFIG_PASELECT_PABOOST) { 01474 if (power > 17) { 01475 paDac = (paDac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_ON; 01476 } else { 01477 paDac = (paDac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_OFF; 01478 } 01479 if ((paDac & RF_PADAC_20DBM_ON) == RF_PADAC_20DBM_ON) { 01480 if (power < 5) { 01481 power = 5; 01482 } 01483 if (power > 20) { 01484 power = 20; 01485 } 01486 paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK) 01487 | (uint8_t) ((uint16_t) (power - 5) & 0x0F); 01488 } else { 01489 if (power < 2) { 01490 power = 2; 01491 } 01492 if (power > 17) { 01493 power = 17; 01494 } 01495 paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK) 01496 | (uint8_t) ((uint16_t) (power - 2) & 0x0F); 01497 } 01498 } else { 01499 if (power < -1) { 01500 power = -1; 01501 } 01502 if (power > 14) { 01503 power = 14; 01504 } 01505 paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK) 01506 | (uint8_t) ((uint16_t) (power + 1) & 0x0F); 01507 } 01508 write_to_register( REG_PACONFIG, paConfig); 01509 write_to_register( REG_PADAC, paDac); 01510 } 01511 01512 /** 01513 * Actual TX - Transmit routine 01514 * 01515 * A DIO0 interrupt let the state machine know that a a packet is 01516 * successfully sent, otherwise a TxTimeout is invoked. 01517 * TxTimeout should never happen in normal circumstances as the radio should 01518 * be able to send a packet out in the air no matter what. 01519 */ 01520 void SX1276_LoRaRadio::transmit(uint32_t timeout) 01521 { 01522 switch (_rf_settings.modem) { 01523 01524 case MODEM_FSK: 01525 // DIO0=PacketSent 01526 // DIO1=FifoEmpty 01527 // DIO2=FifoFull 01528 // DIO3=FifoEmpty 01529 // DIO4=LowBat 01530 // DIO5=ModeReady 01531 write_to_register(REG_DIOMAPPING1,(read_register(REG_DIOMAPPING1) & 01532 RF_DIOMAPPING1_DIO0_MASK & 01533 RF_DIOMAPPING1_DIO1_MASK & 01534 RF_DIOMAPPING1_DIO2_MASK) | 01535 RF_DIOMAPPING1_DIO1_01); 01536 01537 write_to_register(REG_DIOMAPPING2, (read_register(REG_DIOMAPPING2) & 01538 RF_DIOMAPPING2_DIO4_MASK & 01539 RF_DIOMAPPING2_MAP_MASK)); 01540 _rf_settings.fsk_packet_handler.fifo_thresh = 01541 read_register(REG_FIFOTHRESH) & 0x3F; 01542 01543 break; 01544 01545 case MODEM_LORA: 01546 01547 if (_rf_settings.lora.freq_hop_on == true) { 01548 write_to_register(REG_LR_IRQFLAGSMASK, 01549 RFLR_IRQFLAGS_RXTIMEOUT | 01550 RFLR_IRQFLAGS_RXDONE | 01551 RFLR_IRQFLAGS_PAYLOADCRCERROR | 01552 RFLR_IRQFLAGS_VALIDHEADER | 01553 RFLR_IRQFLAGS_CADDONE | 01554 RFLR_IRQFLAGS_CADDETECTED); 01555 01556 // DIO0=tx_done, DIO2=fhss_change_channel 01557 01558 write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) & 01559 RFLR_DIOMAPPING1_DIO0_MASK & 01560 RFLR_DIOMAPPING1_DIO2_MASK) | 01561 RFLR_DIOMAPPING1_DIO0_01 | 01562 RFLR_DIOMAPPING1_DIO2_01); 01563 } else { 01564 write_to_register(REG_LR_IRQFLAGSMASK, 01565 RFLR_IRQFLAGS_RXTIMEOUT | 01566 RFLR_IRQFLAGS_RXDONE | 01567 RFLR_IRQFLAGS_PAYLOADCRCERROR | 01568 RFLR_IRQFLAGS_VALIDHEADER | 01569 RFLR_IRQFLAGS_CADDONE | 01570 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 01571 RFLR_IRQFLAGS_CADDETECTED); 01572 01573 // DIO0=tx_done 01574 write_to_register(REG_DIOMAPPING1,(read_register(REG_DIOMAPPING1) & 01575 RFLR_DIOMAPPING1_DIO0_MASK) | 01576 RFLR_DIOMAPPING1_DIO0_01); 01577 } 01578 01579 break; 01580 } 01581 01582 _rf_settings.state = RF_TX_RUNNING; 01583 01584 tx_timeout_timer.attach_us(callback(this, 01585 &SX1276_LoRaRadio::timeout_irq_isr), timeout * 1000); 01586 01587 set_operation_mode(RF_OPMODE_TRANSMITTER); 01588 } 01589 01590 /** 01591 * Get RSSI from the module 01592 */ 01593 int16_t SX1276_LoRaRadio::get_rssi(radio_modems_t modem) 01594 { 01595 int16_t rssi = 0; 01596 01597 switch (modem) { 01598 case MODEM_FSK: 01599 rssi = -(read_register(REG_RSSIVALUE) >> 1); 01600 break; 01601 case MODEM_LORA: 01602 if (_rf_settings.channel > RF_MID_BAND_THRESH) { 01603 rssi = RSSI_OFFSET_HF + read_register(REG_LR_RSSIVALUE); 01604 } else { 01605 rssi = RSSI_OFFSET_LF + read_register(REG_LR_RSSIVALUE); 01606 } 01607 break; 01608 default: 01609 rssi = -1; 01610 break; 01611 } 01612 return rssi; 01613 } 01614 01615 /** 01616 * Sets the module in low power mode by disconnecting 01617 * TX and RX submodules, turning off power amplifier etc. 01618 */ 01619 void SX1276_LoRaRadio::set_low_power_mode() 01620 { 01621 01622 if (_rf_ctrls.rf_switch_ctl1 != NC) { 01623 _rf_switch_ctl1 = 0; 01624 } 01625 01626 if (_rf_ctrls.rf_switch_ctl2 != NC) { 01627 _rf_switch_ctl2 = 0; 01628 } 01629 01630 if (_rf_ctrls.pwr_amp_ctl != NC) { 01631 _pwr_amp_ctl = 0; 01632 } 01633 01634 if (_rf_ctrls.txctl != NC) { 01635 _txctl = 0; 01636 } 01637 01638 if (_rf_ctrls.rxctl != NC) { 01639 _rxctl = 0; 01640 } 01641 01642 if (_rf_ctrls.ant_switch != NC) { 01643 _ant_switch = 0; 01644 } 01645 } 01646 01647 /** 01648 * Attaches ISRs to interrupt pins 01649 */ 01650 void SX1276_LoRaRadio::setup_interrupts() 01651 { 01652 _dio0_ctl.rise(callback(this, &SX1276_LoRaRadio::dio0_irq_isr)); 01653 _dio1_ctl.rise(callback(this, &SX1276_LoRaRadio::dio1_irq_isr)); 01654 _dio2_ctl.rise(callback(this, &SX1276_LoRaRadio::dio2_irq_isr)); 01655 _dio3_ctl.rise(callback(this, &SX1276_LoRaRadio::dio3_irq_isr)); 01656 if (_dio4_pin != NC) { 01657 _dio4_ctl.rise(callback(this, &SX1276_LoRaRadio::dio4_irq_isr)); 01658 } 01659 if (_dio5_pin != NC) { 01660 _dio5_ctl.rise(callback(this, &SX1276_LoRaRadio::dio5_irq_isr)); 01661 } 01662 } 01663 01664 /** 01665 * Sets up radio latch position according to the 01666 * radio mode 01667 */ 01668 void SX1276_LoRaRadio::set_antenna_switch(uint8_t mode) 01669 { 01670 // here we got to do ifdef for changing controls 01671 // as some pins might be NC 01672 switch (mode) { 01673 case RFLR_OPMODE_TRANSMITTER: 01674 if (_rf_ctrls.rf_switch_ctl1 != NC 01675 && _rf_ctrls.rf_switch_ctl2 != NC) { 01676 // module is in transmit mode and RF latch switches 01677 // are connected. Check if power amplifier boost is 01678 // setup or not 01679 if ((read_register(REG_PACONFIG) & RF_PACONFIG_PASELECT_PABOOST) 01680 == RF_PACONFIG_PASELECT_PABOOST) { 01681 _rf_switch_ctl1 = 1; 01682 _rf_switch_ctl2 = 0; 01683 } else { 01684 // power amplifier not selected 01685 _rf_switch_ctl1 = 0; 01686 _rf_switch_ctl2 = 1; 01687 } 01688 } 01689 if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) { 01690 // module is in transmit mode and tx/rx submodule control 01691 // pins are connected 01692 if (_rf_ctrls.pwr_amp_ctl != NC) { 01693 if (read_register(REG_PACONFIG) & RF_PACONFIG_PASELECT_PABOOST) { 01694 _pwr_amp_ctl = 1; 01695 _txctl = 0; 01696 } else { 01697 _pwr_amp_ctl = 0; 01698 _txctl = 1; 01699 } 01700 } else { 01701 _txctl = 1; 01702 } 01703 _rxctl = 0; 01704 } 01705 if (_rf_ctrls.ant_switch != NC){ 01706 _ant_switch = 1; 01707 } 01708 break; 01709 case RFLR_OPMODE_RECEIVER: 01710 case RFLR_OPMODE_RECEIVER_SINGLE: 01711 case RFLR_OPMODE_CAD: 01712 if (_rf_ctrls.rf_switch_ctl1 != NC 01713 && _rf_ctrls.rf_switch_ctl2 != NC) { 01714 // radio is in reception or CAD mode and RF latch switches 01715 // are connected 01716 _rf_switch_ctl1 = 1; 01717 _rf_switch_ctl2 = 1; 01718 } 01719 if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) { 01720 _txctl = 0; 01721 _rxctl = 1; 01722 } 01723 if (_rf_ctrls.ant_switch != NC) { 01724 _ant_switch = 0; 01725 } 01726 if (_rf_ctrls.pwr_amp_ctl != NC) { 01727 _pwr_amp_ctl = 0; 01728 } 01729 break; 01730 default: 01731 // Enforce default case when any connected control pin is kept low. 01732 if (_rf_ctrls.rf_switch_ctl1 != NC 01733 && _rf_ctrls.rf_switch_ctl2 != NC) { 01734 // radio is in reception or CAD mode and RF latch switches 01735 // are connected 01736 _rf_switch_ctl1 = 0; 01737 _rf_switch_ctl2 = 0; 01738 } 01739 if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) { 01740 _txctl = 0; 01741 _rxctl = 0; 01742 } 01743 if (_rf_ctrls.ant_switch != NC) { 01744 _ant_switch = 0; 01745 } 01746 if (_rf_ctrls.pwr_amp_ctl != NC) { 01747 _pwr_amp_ctl = 0; 01748 } 01749 break; 01750 } 01751 } 01752 01753 /***************************************************************************** 01754 * Interrupt service routines (ISRs) - set signals to the irq_thread * 01755 ****************************************************************************/ 01756 void SX1276_LoRaRadio::dio0_irq_isr() 01757 { 01758 #ifdef MBED_CONF_RTOS_PRESENT 01759 irq_thread.signal_set(SIG_DIO0); 01760 #else 01761 handle_dio0_irq(); 01762 #endif 01763 } 01764 01765 void SX1276_LoRaRadio::dio1_irq_isr() 01766 { 01767 #ifdef MBED_CONF_RTOS_PRESENT 01768 irq_thread.signal_set(SIG_DIO1); 01769 #else 01770 handle_dio1_irq(); 01771 #endif 01772 } 01773 01774 void SX1276_LoRaRadio::dio2_irq_isr() 01775 { 01776 #ifdef MBED_CONF_RTOS_PRESENT 01777 irq_thread.signal_set(SIG_DIO2); 01778 #else 01779 handle_dio2_irq(); 01780 #endif 01781 } 01782 01783 void SX1276_LoRaRadio::dio3_irq_isr() 01784 { 01785 #ifdef MBED_CONF_RTOS_PRESENT 01786 irq_thread.signal_set(SIG_DIO3); 01787 #else 01788 handle_dio3_irq(); 01789 #endif 01790 } 01791 01792 void SX1276_LoRaRadio::dio4_irq_isr() 01793 { 01794 #ifdef MBED_CONF_RTOS_PRESENT 01795 irq_thread.signal_set(SIG_DIO4); 01796 #else 01797 handle_dio4_irq(); 01798 #endif 01799 } 01800 01801 void SX1276_LoRaRadio::dio5_irq_isr() 01802 { 01803 #ifdef MBED_CONF_RTOS_PRESENT 01804 irq_thread.signal_set(SIG_DIO5); 01805 #else 01806 handle_dio5_irq(); 01807 #endif 01808 } 01809 01810 // This is not a hardware interrupt 01811 // we invoke it ourselves based upon 01812 // our timers 01813 void SX1276_LoRaRadio::timeout_irq_isr() 01814 { 01815 #ifdef MBED_CONF_RTOS_PRESENT 01816 irq_thread.signal_set(SIG_TIMOUT); 01817 #else 01818 handle_timeout_irq(); 01819 #endif 01820 } 01821 01822 /****************************************************************************** 01823 * Interrupt Handlers * 01824 *****************************************************************************/ 01825 01826 void SX1276_LoRaRadio::handle_dio0_irq() 01827 { 01828 volatile uint8_t irqFlags = 0; 01829 01830 switch (_rf_settings.state) { 01831 case RF_RX_RUNNING: 01832 switch (_rf_settings.modem) { 01833 case MODEM_FSK: 01834 if (_rf_settings.fsk.crc_on == true) { 01835 irqFlags = read_register(REG_IRQFLAGS2); 01836 if ((irqFlags & RF_IRQFLAGS2_CRCOK) 01837 != RF_IRQFLAGS2_CRCOK) { 01838 // Clear Irqs 01839 write_to_register(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 01840 RF_IRQFLAGS1_PREAMBLEDETECT | 01841 RF_IRQFLAGS1_SYNCADDRESSMATCH); 01842 write_to_register(REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN); 01843 01844 if (_rf_settings.fsk.rx_continuous == false) { 01845 _rf_settings.state = RF_IDLE; 01846 } else { 01847 // Continuous mode restart Rx chain 01848 write_to_register(REG_RXCONFIG, 01849 read_register(REG_RXCONFIG) | 01850 RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK); 01851 } 01852 01853 if ((_radio_events != NULL) 01854 && (_radio_events->rx_error)) { 01855 _radio_events->rx_error(); 01856 } 01857 _rf_settings.fsk_packet_handler.preamble_detected = 0; 01858 _rf_settings.fsk_packet_handler.sync_word_detected = 0; 01859 _rf_settings.fsk_packet_handler.nb_bytes = 0; 01860 _rf_settings.fsk_packet_handler.size = 0; 01861 // break from here, a CRC error happened, RX_ERROR 01862 // was notified. No need to go any further 01863 break; 01864 } 01865 } 01866 01867 // This block was moved from dio2_handler. 01868 // We can have a snapshot of RSSI here as at this point it 01869 // should be more smoothed out. 01870 _rf_settings.fsk_packet_handler.rssi_value = 01871 -(read_register(REG_RSSIVALUE) >> 1); 01872 01873 _rf_settings.fsk_packet_handler.afc_value = 01874 (int32_t) (float) (((uint16_t) read_register(REG_AFCMSB) << 8) 01875 | (uint16_t) read_register( REG_AFCLSB)) 01876 * (float) FREQ_STEP; 01877 _rf_settings.fsk_packet_handler.rx_gain = 01878 (read_register( REG_LNA) >> 5) & 0x07; 01879 01880 // Read received packet size 01881 if ((_rf_settings.fsk_packet_handler.size == 0) 01882 && (_rf_settings.fsk_packet_handler.nb_bytes == 0)) { 01883 if (_rf_settings.fsk.fix_len == false) { 01884 read_fifo((uint8_t*) &_rf_settings.fsk_packet_handler.size, 1); 01885 } else { 01886 _rf_settings.fsk_packet_handler.size = read_register(REG_PAYLOADLENGTH); 01887 } 01888 read_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes, 01889 _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes); 01890 _rf_settings.fsk_packet_handler.nb_bytes += 01891 (_rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes); 01892 } else { 01893 read_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes, 01894 _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes); 01895 _rf_settings.fsk_packet_handler.nb_bytes += 01896 (_rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes); 01897 } 01898 01899 if (_rf_settings.fsk.rx_continuous == false) { 01900 _rf_settings.state = RF_IDLE; 01901 } else { 01902 // Continuous mode restart Rx chain 01903 write_to_register(REG_RXCONFIG, read_register(REG_RXCONFIG) 01904 | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK); 01905 } 01906 01907 if ((_radio_events != NULL) && (_radio_events->rx_done)) { 01908 _radio_events->rx_done( 01909 _data_buffer, 01910 _rf_settings.fsk_packet_handler.size, 01911 _rf_settings.fsk_packet_handler.rssi_value, 0); 01912 } 01913 _rf_settings.fsk_packet_handler.preamble_detected = 0; 01914 _rf_settings.fsk_packet_handler.sync_word_detected = 0; 01915 _rf_settings.fsk_packet_handler.nb_bytes = 0; 01916 _rf_settings.fsk_packet_handler.size = 0; 01917 break; 01918 01919 case MODEM_LORA: { 01920 int8_t snr = 0; 01921 01922 // Clear Irq 01923 write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE); 01924 01925 irqFlags = read_register(REG_LR_IRQFLAGS); 01926 if ((irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK) 01927 == RFLR_IRQFLAGS_PAYLOADCRCERROR) { 01928 // Clear Irq 01929 write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR); 01930 01931 if (_rf_settings.lora.rx_continuous == false) { 01932 _rf_settings.state = RF_IDLE; 01933 } 01934 01935 if ((_radio_events != NULL) 01936 && (_radio_events->rx_error)) { 01937 _radio_events->rx_error(); 01938 } 01939 break; 01940 } 01941 01942 _rf_settings.lora_packet_handler.snr_value = read_register( 01943 REG_LR_PKTSNRVALUE); 01944 if (_rf_settings.lora_packet_handler.snr_value & 0x80) // The SNR sign bit is 1 01945 { 01946 // Invert and divide by 4 01947 snr = ((~_rf_settings.lora_packet_handler.snr_value + 1) 01948 & 0xFF) >> 2; 01949 snr = -snr; 01950 } else { 01951 // Divide by 4 01952 snr = 01953 (_rf_settings.lora_packet_handler.snr_value 01954 & 0xFF) >> 2; 01955 } 01956 01957 int16_t rssi = read_register( REG_LR_PKTRSSIVALUE); 01958 if (snr < 0) { 01959 if (_rf_settings.channel > RF_MID_BAND_THRESH) { 01960 _rf_settings.lora_packet_handler.rssi_value = 01961 RSSI_OFFSET_HF + rssi + (rssi >> 4) + snr; 01962 } else { 01963 _rf_settings.lora_packet_handler.rssi_value = 01964 RSSI_OFFSET_LF + rssi + (rssi >> 4) + snr; 01965 } 01966 } else { 01967 if (_rf_settings.channel > RF_MID_BAND_THRESH) { 01968 _rf_settings.lora_packet_handler.rssi_value = 01969 RSSI_OFFSET_HF + rssi + (rssi >> 4); 01970 } else { 01971 _rf_settings.lora_packet_handler.rssi_value = 01972 RSSI_OFFSET_LF + rssi + (rssi >> 4); 01973 } 01974 } 01975 01976 _rf_settings.lora_packet_handler.size = read_register(REG_LR_RXNBBYTES); 01977 read_fifo(_data_buffer, _rf_settings.lora_packet_handler.size); 01978 01979 if (_rf_settings.lora.rx_continuous == false) { 01980 _rf_settings.state = RF_IDLE; 01981 } 01982 01983 if ((_radio_events != NULL) && (_radio_events->rx_done)) { 01984 _radio_events->rx_done(_data_buffer, 01985 _rf_settings.lora_packet_handler.size, 01986 _rf_settings.lora_packet_handler.rssi_value, 01987 _rf_settings.lora_packet_handler.snr_value); 01988 } 01989 } 01990 break; 01991 default: 01992 break; 01993 } 01994 break; 01995 case RF_TX_RUNNING: 01996 tx_timeout_timer.detach(); 01997 // TxDone interrupt 01998 switch (_rf_settings.modem) { 01999 case MODEM_LORA: 02000 // Clear Irq 02001 write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE); 02002 // Intentional fall through 02003 case MODEM_FSK: 02004 default: 02005 _rf_settings.state = RF_IDLE; 02006 if ((_radio_events != NULL) 02007 && (_radio_events->tx_done)) { 02008 _radio_events->tx_done(); 02009 } 02010 break; 02011 } 02012 break; 02013 default: 02014 break; 02015 } 02016 } 02017 02018 void SX1276_LoRaRadio::handle_dio1_irq() 02019 { 02020 switch (_rf_settings.state) { 02021 case RF_RX_RUNNING: 02022 switch (_rf_settings.modem) { 02023 case MODEM_FSK: 02024 // FifoLevel interrupt 02025 // Read received packet size 02026 if ((_rf_settings.fsk_packet_handler.size == 0) 02027 && (_rf_settings.fsk_packet_handler.nb_bytes == 0)) { 02028 if (_rf_settings.fsk.fix_len == false) { 02029 read_fifo((uint8_t*) &_rf_settings.fsk_packet_handler.size, 1); 02030 } else { 02031 _rf_settings.fsk_packet_handler.size = 02032 read_register(REG_PAYLOADLENGTH); 02033 } 02034 } 02035 02036 if ((_rf_settings.fsk_packet_handler.size 02037 - _rf_settings.fsk_packet_handler.nb_bytes) 02038 > _rf_settings.fsk_packet_handler.fifo_thresh) { 02039 read_fifo((_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes), 02040 _rf_settings.fsk_packet_handler.fifo_thresh); 02041 _rf_settings.fsk_packet_handler.nb_bytes += 02042 _rf_settings.fsk_packet_handler.fifo_thresh; 02043 } else { 02044 read_fifo((_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes), 02045 _rf_settings.fsk_packet_handler.size 02046 - _rf_settings.fsk_packet_handler.nb_bytes); 02047 _rf_settings.fsk_packet_handler.nb_bytes += 02048 (_rf_settings.fsk_packet_handler.size 02049 - _rf_settings.fsk_packet_handler.nb_bytes); 02050 } 02051 02052 break; 02053 02054 case MODEM_LORA: 02055 // Clear Irq 02056 write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT); 02057 _rf_settings.state = RF_IDLE; 02058 if ((_radio_events != NULL) 02059 && (_radio_events->rx_timeout)) { 02060 _radio_events->rx_timeout(); 02061 } 02062 break; 02063 default: 02064 break; 02065 } 02066 02067 break; 02068 02069 case RF_TX_RUNNING: 02070 switch (_rf_settings.modem) { 02071 case MODEM_FSK: 02072 // FifoLevel interrupt 02073 if ((_rf_settings.fsk_packet_handler.size 02074 - _rf_settings.fsk_packet_handler.nb_bytes) 02075 > _rf_settings.fsk_packet_handler.chunk_size) { 02076 write_fifo((_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes), 02077 _rf_settings.fsk_packet_handler.chunk_size); 02078 _rf_settings.fsk_packet_handler.nb_bytes += 02079 _rf_settings.fsk_packet_handler.chunk_size; 02080 } else { 02081 // Write the last chunk of data 02082 write_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes, 02083 _rf_settings.fsk_packet_handler.size 02084 - _rf_settings.fsk_packet_handler.nb_bytes); 02085 _rf_settings.fsk_packet_handler.nb_bytes += 02086 _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes; 02087 } 02088 02089 break; 02090 02091 case MODEM_LORA: 02092 break; 02093 default: 02094 break; 02095 } 02096 break; 02097 default: 02098 break; 02099 } 02100 } 02101 02102 void SX1276_LoRaRadio::handle_dio2_irq(void) 02103 { 02104 switch (_rf_settings.state) { 02105 case RF_RX_RUNNING: 02106 switch (_rf_settings.modem) { 02107 case MODEM_FSK: 02108 _rf_settings.fsk_packet_handler.preamble_detected = 0; 02109 _rf_settings.fsk_packet_handler.sync_word_detected = 0; 02110 _rf_settings.fsk_packet_handler.nb_bytes = 0; 02111 _rf_settings.fsk_packet_handler.size = 0; 02112 02113 // Clear Irqs 02114 write_to_register(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 02115 RF_IRQFLAGS1_PREAMBLEDETECT | 02116 RF_IRQFLAGS1_SYNCADDRESSMATCH | 02117 RF_IRQFLAGS1_TIMEOUT); 02118 02119 write_to_register( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN); 02120 02121 if (_rf_settings.fsk.rx_continuous == true) { 02122 // Continuous mode restart Rx chain 02123 write_to_register( REG_RXCONFIG, 02124 read_register(REG_RXCONFIG) | 02125 RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK); 02126 } else { 02127 _rf_settings.state = RF_IDLE; 02128 } 02129 02130 if ((_radio_events != NULL) 02131 && (_radio_events->rx_timeout)) { 02132 _radio_events->rx_timeout(); 02133 } 02134 02135 break; 02136 02137 case MODEM_LORA: 02138 if (_rf_settings.lora.freq_hop_on == true) { 02139 // Clear Irq 02140 write_to_register(REG_LR_IRQFLAGS, 02141 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL); 02142 02143 if ((_radio_events != NULL) 02144 && (_radio_events->fhss_change_channel)) { 02145 _radio_events->fhss_change_channel( 02146 (read_register(REG_LR_HOPCHANNEL) 02147 & RFLR_HOPCHANNEL_CHANNEL_MASK)); 02148 } 02149 } 02150 02151 break; 02152 02153 default: 02154 break; 02155 } 02156 02157 break; 02158 02159 case RF_TX_RUNNING: 02160 switch (_rf_settings.modem) { 02161 case MODEM_FSK: 02162 break; 02163 case MODEM_LORA: 02164 if (_rf_settings.lora.freq_hop_on == true) { 02165 // Clear Irq 02166 write_to_register(REG_LR_IRQFLAGS, 02167 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL); 02168 02169 if ((_radio_events != NULL) 02170 && (_radio_events->fhss_change_channel)) { 02171 _radio_events->fhss_change_channel( 02172 (read_register(REG_LR_HOPCHANNEL) 02173 & RFLR_HOPCHANNEL_CHANNEL_MASK)); 02174 } 02175 } 02176 break; 02177 default: 02178 break; 02179 } 02180 break; 02181 default: 02182 break; 02183 } 02184 } 02185 02186 void SX1276_LoRaRadio::handle_dio3_irq(void) 02187 { 02188 switch (_rf_settings.modem) { 02189 case MODEM_FSK: 02190 break; 02191 case MODEM_LORA: 02192 if ((read_register(REG_LR_IRQFLAGS) & RFLR_IRQFLAGS_CADDETECTED) 02193 == RFLR_IRQFLAGS_CADDETECTED) { 02194 // Clear Irq 02195 write_to_register(REG_LR_IRQFLAGS, 02196 RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE); 02197 if ((_radio_events != NULL) 02198 && (_radio_events->cad_done)) { 02199 _radio_events->cad_done(true); 02200 } 02201 } else { 02202 // Clear Irq 02203 write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE); 02204 if ((_radio_events != NULL) 02205 && (_radio_events->cad_done)) { 02206 _radio_events->cad_done(false); 02207 } 02208 } 02209 break; 02210 default: 02211 break; 02212 } 02213 } 02214 02215 void SX1276_LoRaRadio::handle_dio4_irq(void) 02216 { 02217 // is asserted when a preamble is detected (FSK modem only) 02218 switch (_rf_settings.modem) { 02219 case MODEM_FSK: { 02220 if (_rf_settings.fsk_packet_handler.preamble_detected == 0) { 02221 _rf_settings.fsk_packet_handler.preamble_detected = 1; 02222 } 02223 } 02224 break; 02225 case MODEM_LORA: 02226 break; 02227 default: 02228 break; 02229 } 02230 } 02231 02232 void SX1276_LoRaRadio::handle_dio5_irq() 02233 { 02234 switch (_rf_settings.modem) { 02235 case MODEM_FSK: 02236 break; 02237 case MODEM_LORA: 02238 break; 02239 default: 02240 break; 02241 } 02242 } 02243 02244 void SX1276_LoRaRadio::handle_timeout_irq() 02245 { 02246 tx_timeout_timer.detach(); 02247 02248 if (_rf_settings.state == RF_TX_RUNNING) { 02249 // Tx timeout shouldn't happen. 02250 // But it has been observed that when it happens it is a result of a 02251 // corrupted SPI transfer 02252 // The workaround is to put the radio in a known state. 02253 // Thus, we re-initialize it. 02254 02255 // Initialize radio default values 02256 set_operation_mode(RF_OPMODE_SLEEP); 02257 02258 setup_registers(); 02259 02260 set_modem(MODEM_FSK); 02261 02262 // Restore previous network type setting. 02263 set_public_network(_rf_settings.lora.public_network); 02264 02265 _rf_settings.state = RF_IDLE; 02266 02267 if ((_radio_events != NULL) && (_radio_events->tx_timeout)) { 02268 _radio_events->tx_timeout(); 02269 } 02270 } 02271 } 02272 02273 int8_t SX1276_LoRaRadio::getTemp(void) 02274 { 02275 int8_t temp = 0; 02276 uint8_t previousOpMode; 02277 uint8_t regOpMode; 02278 uint8_t regImageCal; 02279 uint8_t regTemp; 02280 // Save current Operation Mode 02281 regOpMode = read_register(REG_OPMODE); 02282 previousOpMode = regOpMode; 02283 // Pass through LoRa sleep only necessary if reading temperature while in LoRa Mode 02284 if ((previousOpMode & RFLR_OPMODE_LONGRANGEMODE_ON) == RFLR_OPMODE_LONGRANGEMODE_ON) 02285 { 02286 regOpMode = RFLR_OPMODE_SLEEP; 02287 write_to_register(REG_OPMODE, regOpMode); // Put device in LoRa Sleep Mode 02288 } 02289 // Put device in FSK Sleep Mode 02290 regOpMode = RF_OPMODE_SLEEP; 02291 write_to_register(REG_OPMODE, regOpMode); 02292 // Put device in FSK RxSynth 02293 regOpMode = RF_OPMODE_SYNTHESIZER_RX; 02294 write_to_register(REG_OPMODE, regOpMode); 02295 // Enable Temperature reading 02296 regImageCal = read_register(REG_IMAGECAL); 02297 regImageCal = (regImageCal & RF_IMAGECAL_TEMPMONITOR_MASK) | RF_IMAGECAL_TEMPMONITOR_ON; 02298 write_to_register(REG_IMAGECAL, regImageCal); 02299 // Wait 150us 02300 wait(0.000150); 02301 // Disable Temperature reading 02302 regImageCal = read_register(REG_IMAGECAL); 02303 regImageCal = (regImageCal & RF_IMAGECAL_TEMPMONITOR_MASK) | RF_IMAGECAL_TEMPMONITOR_OFF; 02304 write_to_register(REG_IMAGECAL, regImageCal); 02305 // Put device in FSK Sleep Mode 02306 regOpMode = RF_OPMODE_SLEEP; 02307 write_to_register(REG_OPMODE, regOpMode); 02308 // Read temperature 02309 regTemp = read_register(REG_TEMP); 02310 if ((regTemp & 0x80) == 0x80) 02311 { 02312 temp = 255 - regTemp; 02313 } 02314 else 02315 { 02316 temp = regTemp; 02317 temp *= -1; 02318 } 02319 // We were in LoRa Mode prior to the temperature reading 02320 if ((previousOpMode & RFLR_OPMODE_LONGRANGEMODE_ON) == RFLR_OPMODE_LONGRANGEMODE_ON) 02321 { 02322 regOpMode = RFLR_OPMODE_SLEEP; 02323 write_to_register(REG_OPMODE, regOpMode); // Put device in LoRa Sleep Mode 02324 } 02325 // Reload previous Op Mode 02326 write_to_register(REG_OPMODE, previousOpMode); 02327 return temp; 02328 } 02329 // EOF
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