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SX1272_LoRaRadio.cpp

00001 /**
00002  / _____)             _              | |
00003 ( (____  _____ ____ _| |_ _____  ____| |__
00004  \____ \| ___ |    (_   _) ___ |/ ___)  _ \
00005  _____) ) ____| | | || |_| ____( (___| | | |
00006 (______/|_____)_|_|_| \__)_____)\____)_| |_|
00007     (C)2013 Semtech
00008  ___ _____ _   ___ _  _____ ___  ___  ___ ___
00009 / __|_   _/_\ / __| |/ / __/ _ \| _ \/ __| __|
00010 \__ \ | |/ _ \ (__| ' <| _| (_) |   / (__| _|
00011 |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___|
00012 embedded.connectivity.solutions===============
00013 
00014 Description: Radio driver for Semtech SX1272 LoRa radio chip. Implements LoRaRadio class.
00015 
00016 License: Revised BSD License, see LICENSE.TXT file include in the project
00017 
00018 Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE )
00019 
00020 
00021 Copyright (c) 2017, Arm Limited and affiliates.
00022 
00023 SPDX-License-Identifier: BSD-3-Clause
00024 */
00025 
00026 #include <stdio.h>
00027 #include <math.h> //rint
00028 #include <string.h>
00029 #include "mbed.h"
00030 
00031 #include "SX1272_LoRaRadio.h"
00032 #include "sx1272Regs-Fsk.h"
00033 #include "sx1272Regs-LoRa.h"
00034 
00035 #ifdef MBED_SX1272_LORA_RADIO_SPI_FREQUENCY
00036 #define SPI_FREQUENCY    MBED_SX1272_LORA_RADIO_SPI_FREQUENCY
00037 #else
00038 #define SPI_FREQUENCY    8000000
00039 #endif
00040 
00041 // Sync word for Private LoRa networks
00042 #define LORA_MAC_PRIVATE_SYNCWORD                   0x12
00043 // Sync word for Public LoRa networks
00044 #define LORA_MAC_PUBLIC_SYNCWORD                    0x34
00045 
00046 // SX1272 definitions
00047 #define XTAL_FREQ                                   32000000
00048 #define FREQ_STEP                                   61.03515625
00049 
00050 
00051 
00052 enum RadioVariant {
00053     SX1272UNDEFINED = 0,
00054     SX1272MB2XAS,
00055     SX1272MB1DCS
00056 };
00057 
00058 /*!
00059  * FSK bandwidth definition
00060  */
00061 typedef struct
00062 {
00063     uint32_t bandwidth;
00064     uint8_t  register_value;
00065 } fsk_bw_t;
00066 
00067 /*!
00068  * Radio registers definition
00069  */
00070 typedef struct
00071 {
00072     modem_type  modem;
00073     uint8_t     addr;
00074     uint8_t     value;
00075 } radio_registers_t;
00076 
00077 /*!
00078  * Constant values need to compute the RSSI value
00079  */
00080 #define RSSI_OFFSET                                 -139
00081 
00082 #define RADIO_INIT_REGISTERS_VALUE                \
00083 {                                                 \
00084     { MODEM_FSK , REG_LNA                , 0x23 },\
00085     { MODEM_FSK , REG_RXCONFIG           , 0x1E },\
00086     { MODEM_FSK , REG_RSSICONFIG         , 0xD2 },\
00087     { MODEM_FSK , REG_AFCFEI             , 0x01 },\
00088     { MODEM_FSK , REG_PREAMBLEDETECT     , 0xAA },\
00089     { MODEM_FSK , REG_OSC                , 0x07 },\
00090     { MODEM_FSK , REG_SYNCCONFIG         , 0x12 },\
00091     { MODEM_FSK , REG_SYNCVALUE1         , 0xC1 },\
00092     { MODEM_FSK , REG_SYNCVALUE2         , 0x94 },\
00093     { MODEM_FSK , REG_SYNCVALUE3         , 0xC1 },\
00094     { MODEM_FSK , REG_PACKETCONFIG1      , 0xD8 },\
00095     { MODEM_FSK , REG_FIFOTHRESH         , 0x8F },\
00096     { MODEM_FSK , REG_IMAGECAL           , 0x02 },\
00097     { MODEM_FSK , REG_DIOMAPPING1        , 0x00 },\
00098     { MODEM_FSK , REG_DIOMAPPING2        , 0x30 },\
00099     { MODEM_LORA, REG_LR_DETECTOPTIMIZE  , 0x43 },\
00100     { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },\
00101 }
00102 
00103 const fsk_bw_t fsk_bandwidths[] =
00104 {
00105     { 2600  , 0x17 },
00106     { 3100  , 0x0F },
00107     { 3900  , 0x07 },
00108     { 5200  , 0x16 },
00109     { 6300  , 0x0E },
00110     { 7800  , 0x06 },
00111     { 10400 , 0x15 },
00112     { 12500 , 0x0D },
00113     { 15600 , 0x05 },
00114     { 20800 , 0x14 },
00115     { 25000 , 0x0C },
00116     { 31300 , 0x04 },
00117     { 41700 , 0x13 },
00118     { 50000 , 0x0B },
00119     { 62500 , 0x03 },
00120     { 83333 , 0x12 },
00121     { 100000, 0x0A },
00122     { 125000, 0x02 },
00123     { 166700, 0x11 },
00124     { 200000, 0x09 },
00125     { 250000, 0x01 },
00126     { 300000, 0x00 }, // Invalid bandwidth
00127 };
00128 
00129 /**
00130  * SPI read/write masks
00131  */
00132 #define SPI_WRITE_CMD   0x80
00133 #define SPI_READ_CMD    0x7F
00134 
00135 /**
00136  * Signals
00137  */
00138 #define SIG_DIO0    0x01
00139 #define SIG_DIO1    0x02
00140 #define SIG_DIO2    0x04
00141 #define SIG_DIO3    0x08
00142 #define SIG_DIO4    0x10
00143 #define SIG_DIO5    0x20
00144 #define SIG_TIMOUT  0x40
00145 
00146 /**
00147  * Radio hardware registers initialization
00148  */
00149 static const radio_registers_t radio_reg_init[] = RADIO_INIT_REGISTERS_VALUE;
00150 
00151 
00152 /**
00153  * Constructor
00154  */
00155 SX1272_LoRaRadio::SX1272_LoRaRadio(PinName spi_mosi,
00156                                    PinName spi_miso,
00157                                    PinName spi_sclk,
00158                                    PinName nss,
00159                                    PinName reset,
00160                                    PinName dio0,
00161                                    PinName dio1,
00162                                    PinName dio2,
00163                                    PinName dio3,
00164                                    PinName dio4,
00165                                    PinName dio5,
00166                                    PinName rf_switch_ctl1,
00167                                    PinName rf_switch_ctl2,
00168                                    PinName txctl,
00169                                    PinName rxctl,
00170                                    PinName antswitch,
00171                                    PinName pwr_amp_ctl,
00172                                    PinName tcxo)
00173     :   _spi(spi_mosi, spi_miso, spi_sclk),
00174         _chip_select(nss, 1),
00175         _reset_ctl(reset),
00176         _dio0_ctl(dio0), _dio1_ctl(dio1), _dio2_ctl(dio2), _dio3_ctl(dio3), _dio4_ctl(dio4), _dio5_ctl(dio5),
00177         _rf_switch_ctl1(rf_switch_ctl1, 0), _rf_switch_ctl2(rf_switch_ctl2, 0), _txctl(txctl, 0), _rxctl(rxctl, 0),
00178         _ant_switch(antswitch, PIN_INPUT, PullUp, 0),
00179         _pwr_amp_ctl(pwr_amp_ctl),
00180         _tcxo(tcxo)
00181 
00182 #ifdef MBED_CONF_RTOS_PRESENT
00183         , irq_thread(osPriorityRealtime, 1024)
00184 #endif
00185 {
00186     _rf_ctrls.ant_switch = antswitch;
00187     _rf_ctrls.pwr_amp_ctl = pwr_amp_ctl;
00188     _rf_ctrls.rf_switch_ctl1 = rf_switch_ctl1;
00189     _rf_ctrls.rf_switch_ctl2 = rf_switch_ctl2;
00190     _rf_ctrls.rxctl = rxctl;
00191     _rf_ctrls.txctl = txctl;
00192 
00193     _dio4_pin = dio4;
00194     _dio5_pin = dio5;
00195 
00196     _radio_events = NULL;
00197 
00198     if (tcxo != NC) {
00199         _tcxo = 1;
00200     }
00201 
00202     radio_is_active = false;
00203 
00204 #ifdef MBED_CONF_RTOS_PRESENT
00205     irq_thread.start(mbed::callback(this, &SX1272_LoRaRadio::rf_irq_task));
00206 #endif
00207 }
00208 
00209 /**
00210  * Destructor
00211  */
00212 SX1272_LoRaRadio::~SX1272_LoRaRadio()
00213 {
00214 
00215 }
00216 
00217 /*****************************************************************************
00218  * Public APIs                                                               *
00219  ****************************************************************************/
00220 
00221 /**
00222  * Acquire lock
00223  */
00224 void SX1272_LoRaRadio::lock(void)
00225 {
00226     mutex.lock();
00227 }
00228 
00229 /**
00230  * Release lock
00231  */
00232 void SX1272_LoRaRadio::unlock(void)
00233 {
00234     mutex.unlock();
00235 }
00236 
00237 /**
00238  * Initializes radio module
00239  */
00240 void SX1272_LoRaRadio::init_radio(radio_events_t *events)
00241 {
00242     _radio_events = events;
00243 
00244     // Reset the radio transceiver
00245     radio_reset();
00246 
00247     // Setup radio variant type
00248     set_sx1272_variant_type();
00249 
00250     // setup SPI frequency
00251     // default is 8MHz although, configurable through
00252     // SPI_FREQUENCY macro
00253     setup_spi();
00254 
00255     // set radio mode to sleep
00256     set_operation_mode(RF_OPMODE_SLEEP);
00257 
00258     // Setup radio registers to defaults
00259     setup_registers();
00260 
00261     // set modem type - defaults to FSK here
00262     set_modem(MODEM_FSK);
00263 
00264     // set state to be idle
00265     _rf_settings.state = RF_IDLE;
00266 
00267     // Setup interrupts on DIO pins
00268     setup_interrupts();
00269 }
00270 
00271 /**
00272  * TODO: The purpose of this API is unclear.
00273  *       Need to start an internal discussion.
00274  */
00275 bool SX1272_LoRaRadio::check_rf_frequency(uint32_t frequency)
00276 {
00277     // Implement check. Currently all frequencies are supported ? What band ?
00278     return true;
00279 }
00280 
00281 /**
00282  * Sets up carrier frequency
00283  */
00284 void SX1272_LoRaRadio::set_channel(uint32_t freq)
00285 {
00286     _rf_settings.channel = freq;
00287     freq = (uint32_t) ((float) freq / (float) FREQ_STEP);
00288     write_to_register(REG_FRFMSB, (uint8_t) ((freq >> 16) & 0xFF));
00289     write_to_register(REG_FRFMID, (uint8_t) ((freq >> 8) & 0xFF));
00290     write_to_register(REG_FRFLSB, (uint8_t) (freq & 0xFF));
00291 }
00292 
00293 /**
00294  * Returns current status of the radio state machine
00295  */
00296 uint8_t SX1272_LoRaRadio::get_status(void)
00297 {
00298     return _rf_settings.state;
00299 }
00300 
00301 /**
00302  * sets the radio module to sleep
00303  */
00304 
00305 void SX1272_LoRaRadio::sleep()
00306 {
00307     // stop timers
00308     tx_timeout_timer.detach();
00309 
00310     // put module in sleep mode
00311     set_operation_mode(RF_OPMODE_SLEEP);
00312 }
00313 
00314 /**
00315  * Sets up operation mode
00316  */
00317 void SX1272_LoRaRadio::set_operation_mode(uint8_t mode)
00318 {
00319     if (mode == RF_OPMODE_SLEEP) {
00320         set_low_power_mode(true);
00321     } else {
00322         set_low_power_mode(false);
00323         set_antenna_switch(mode);
00324     }
00325 
00326     write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RF_OPMODE_MASK) | mode);
00327 }
00328 
00329 /**
00330  * Sets the modem type to use
00331  *
00332  * At initialization FSK is chosen. Later stack or application
00333  * can choose to change.
00334  */
00335 void SX1272_LoRaRadio::set_modem(uint8_t modem )
00336 {
00337     if ((read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_ON) != 0 ) {
00338         _rf_settings.modem = MODEM_LORA;
00339     } else {
00340         _rf_settings.modem = MODEM_FSK;
00341     }
00342 
00343     if(_rf_settings.modem == modem ) {
00344         // if the modem is already set
00345         return;
00346     }
00347 
00348     _rf_settings.modem = modem;
00349 
00350     switch(_rf_settings.modem)
00351     {
00352     default:
00353     case MODEM_FSK:
00354         // before changing modem mode, put the module to sleep
00355         sleep();
00356         write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK)
00357                                       | RFLR_OPMODE_LONGRANGEMODE_OFF);
00358 
00359         // Datasheet Tables 28, 29 DIO mapping
00360         write_to_register(REG_DIOMAPPING1, 0x00); // sets DIO0-DI03 in default mode
00361         write_to_register(REG_DIOMAPPING2, 0x30); // bits 4-5 are turned on i.e.,
00362                                                   //  DIO5 and DIO4=ModeReady
00363         break;
00364     case MODEM_LORA:
00365         sleep();
00366         write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK)
00367                                       | RFLR_OPMODE_LONGRANGEMODE_ON);
00368 
00369         // Datasheet Tables 17 DIO mapping for LoRa
00370         // set to defaults
00371         write_to_register(REG_DIOMAPPING1, 0x00); // DIO0 - DIO3 defaults
00372         write_to_register(REG_DIOMAPPING2, 0x00); // DIO4 - DIO5 defaults
00373 
00374         break;
00375     }
00376 }
00377 
00378 /**
00379  * Can be used by application/stack or the driver itself
00380  * Ref: Datasheet 7.2.2 Manual Reset
00381  */
00382 void SX1272_LoRaRadio::radio_reset()
00383 {
00384     _reset_ctl.output();
00385     _reset_ctl = 0;
00386     wait_ms(2);
00387     _reset_ctl.input();
00388     wait_ms(6);
00389 }
00390 
00391 /**
00392  * Sets up receiver related configurations
00393  *
00394  * Must be called before setting the radio in rx mode
00395  */
00396 void SX1272_LoRaRadio::set_rx_config(radio_modems_t modem, uint32_t bandwidth,
00397                          uint32_t datarate, uint8_t coderate,
00398                          uint32_t bandwidth_afc, uint16_t preamble_len,
00399                          uint16_t symb_timeout, bool fix_len,
00400                          uint8_t payload_len,
00401                          bool crc_on, bool freq_hop_on, uint8_t hop_period,
00402                          bool iq_inverted, bool rx_continuous)
00403 {
00404     set_modem(modem);
00405 
00406     switch (modem) {
00407         case MODEM_FSK:
00408             _rf_settings.fsk.bandwidth = bandwidth;
00409             _rf_settings.fsk.datarate = datarate;
00410             _rf_settings.fsk.bandwidth_afc = bandwidth_afc;
00411             _rf_settings.fsk.fix_len = fix_len;
00412             _rf_settings.fsk.payload_len = payload_len;
00413             _rf_settings.fsk.crc_on = crc_on;
00414             _rf_settings.fsk.iq_inverted = iq_inverted;
00415             _rf_settings.fsk.rx_continuous = rx_continuous;
00416             _rf_settings.fsk.preamble_len = preamble_len;
00417             _rf_settings.fsk.rx_single_timeout = (symb_timeout + 1) / 2; // dividing by 2 as our detector size is 2 symbols (16 bytes)
00418 
00419             datarate = (uint16_t) ((float) XTAL_FREQ / (float) datarate);
00420             write_to_register(REG_BITRATEMSB, (uint8_t) (datarate >> 8));
00421             write_to_register(REG_BITRATELSB, (uint8_t) (datarate & 0xFF));
00422 
00423             write_to_register(REG_RXBW, get_fsk_bw_reg_val(bandwidth));
00424             write_to_register(REG_AFCBW, get_fsk_bw_reg_val(bandwidth_afc));
00425 
00426             write_to_register(REG_PREAMBLEMSB, (uint8_t) ((preamble_len >> 8) & 0xFF));
00427             write_to_register(REG_PREAMBLELSB, (uint8_t) (preamble_len & 0xFF));
00428 
00429             if (fix_len == 1) {
00430                 write_to_register(REG_PAYLOADLENGTH, payload_len);
00431             } else {
00432                 write_to_register(REG_PAYLOADLENGTH, 0xFF); // Set payload length to the maximum
00433             }
00434 
00435             write_to_register(REG_PACKETCONFIG1, (read_register(REG_PACKETCONFIG1) & RF_PACKETCONFIG1_CRC_MASK
00436                           & RF_PACKETCONFIG1_PACKETFORMAT_MASK)
00437                           | ((fix_len == 1) ?
00438                                   RF_PACKETCONFIG1_PACKETFORMAT_FIXED :
00439                                   RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE)
00440                           | (crc_on << 4));
00441 
00442             // TODO why packet mode 2 ?
00443             write_to_register(REG_PACKETCONFIG2, (read_register(REG_PACKETCONFIG2) | RF_PACKETCONFIG2_DATAMODE_PACKET));
00444 
00445             break;
00446 
00447         case MODEM_LORA:
00448             _rf_settings.lora.bandwidth = bandwidth;
00449             _rf_settings.lora.datarate = datarate;
00450             _rf_settings.lora.coderate = coderate;
00451             _rf_settings.lora.preamble_len = preamble_len;
00452             _rf_settings.lora.fix_len = fix_len;
00453             _rf_settings.lora.payload_len = payload_len;
00454             _rf_settings.lora.crc_on = crc_on;
00455             _rf_settings.lora.freq_hop_on = freq_hop_on;
00456             _rf_settings.lora.hop_period = hop_period;
00457             _rf_settings.lora.iq_inverted = iq_inverted;
00458             _rf_settings.lora.rx_continuous = rx_continuous;
00459 
00460             if (datarate > 12) {
00461                 datarate = 12;
00462             } else if (datarate < 6) {
00463                 datarate = 6;
00464             }
00465 
00466             if (((bandwidth == 0) && ((datarate == 11) || (datarate == 12)))
00467                     || ((bandwidth == 1) && (datarate == 12))) {
00468                 _rf_settings.lora.low_datarate_optimize = 0x01;
00469             } else {
00470                 _rf_settings.lora.low_datarate_optimize = 0x00;
00471             }
00472 
00473             write_to_register(REG_LR_MODEMCONFIG1, (read_register(REG_LR_MODEMCONFIG1) & RFLR_MODEMCONFIG1_BW_MASK
00474                           & RFLR_MODEMCONFIG1_CODINGRATE_MASK
00475                           & RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK
00476                           & RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK & RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK)
00477                           | (bandwidth << 6)
00478                           | (coderate << 3) | (fix_len << 2) | (crc_on << 1)
00479                           | _rf_settings.lora.low_datarate_optimize);
00480 
00481             write_to_register(REG_LR_MODEMCONFIG2, (read_register(REG_LR_MODEMCONFIG2) & RFLR_MODEMCONFIG2_SF_MASK
00482                           & RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK)
00483                           | (datarate << 4)
00484                           | ((symb_timeout >> 8)
00485                           & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK));
00486 
00487             write_to_register(REG_LR_SYMBTIMEOUTLSB, (uint8_t) (symb_timeout & 0xFF));
00488 
00489             write_to_register(REG_LR_PREAMBLEMSB, (uint8_t) ((preamble_len >> 8) & 0xFF));
00490             write_to_register(REG_LR_PREAMBLELSB, (uint8_t) (preamble_len & 0xFF));
00491 
00492             if (fix_len == 1) {
00493                 write_to_register(REG_LR_PAYLOADLENGTH, payload_len);
00494             }
00495 
00496             if (_rf_settings.lora.freq_hop_on == true) {
00497                 write_to_register( REG_LR_PLLHOP, (read_register(REG_LR_PLLHOP) & RFLR_PLLHOP_FASTHOP_MASK)
00498                           | RFLR_PLLHOP_FASTHOP_ON);
00499                 write_to_register( REG_LR_HOPPERIOD, _rf_settings.lora.hop_period);
00500             }
00501 
00502             if (datarate == 6) {
00503                 write_to_register( REG_LR_DETECTOPTIMIZE, (read_register(REG_LR_DETECTOPTIMIZE) & RFLR_DETECTIONOPTIMIZE_MASK)
00504                               | RFLR_DETECTIONOPTIMIZE_SF6);
00505                 write_to_register( REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF6);
00506             } else {
00507                 write_to_register(REG_LR_DETECTOPTIMIZE, (read_register(REG_LR_DETECTOPTIMIZE) & RFLR_DETECTIONOPTIMIZE_MASK)
00508                               | RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12);
00509                 write_to_register( REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF7_TO_SF12);
00510             }
00511 
00512             break;
00513 
00514         default:
00515             break;
00516     }
00517 }
00518 
00519 /**
00520  * Sets up transmitter related configuration
00521  *
00522  * Must be called before putting the radio module in Tx mode or trying
00523  * to send
00524  */
00525 void SX1272_LoRaRadio::set_tx_config(radio_modems_t modem, int8_t power,
00526                                      uint32_t fdev, uint32_t bandwidth,
00527                                      uint32_t datarate, uint8_t coderate,
00528                                      uint16_t preamble_len, bool fix_len,
00529                                      bool crc_on, bool freq_hop_on,
00530                                      uint8_t hop_period, bool iq_inverted,
00531                                      uint32_t timeout)
00532 {
00533     set_modem(modem);
00534     set_rf_tx_power(power);
00535 
00536     switch (modem) {
00537         case MODEM_FSK:
00538             _rf_settings.fsk.power = power;
00539             _rf_settings.fsk.f_dev = fdev;
00540             _rf_settings.fsk.bandwidth = bandwidth;
00541             _rf_settings.fsk.datarate = datarate;
00542             _rf_settings.fsk.preamble_len = preamble_len;
00543             _rf_settings.fsk.fix_len = fix_len;
00544             _rf_settings.fsk.crc_on = crc_on;
00545             _rf_settings.fsk.iq_inverted = iq_inverted;
00546             _rf_settings.fsk.tx_timeout = timeout;
00547 
00548             fdev = (uint16_t) ((float) fdev / (float) FREQ_STEP);
00549             write_to_register( REG_FDEVMSB, (uint8_t) (fdev >> 8));
00550             write_to_register( REG_FDEVLSB, (uint8_t) (fdev & 0xFF));
00551 
00552             datarate = (uint16_t) ((float) XTAL_FREQ / (float) datarate);
00553             write_to_register( REG_BITRATEMSB, (uint8_t) (datarate >> 8));
00554             write_to_register( REG_BITRATELSB, (uint8_t) (datarate & 0xFF));
00555 
00556             write_to_register( REG_PREAMBLEMSB, (preamble_len >> 8) & 0x00FF);
00557             write_to_register( REG_PREAMBLELSB, preamble_len & 0xFF);
00558 
00559 
00560             write_to_register(REG_PACKETCONFIG1, (read_register(REG_PACKETCONFIG1)
00561                               & RF_PACKETCONFIG1_CRC_MASK
00562                               & RF_PACKETCONFIG1_PACKETFORMAT_MASK)
00563                               | ((fix_len == 1) ?
00564                               RF_PACKETCONFIG1_PACKETFORMAT_FIXED :
00565                               RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE)
00566                               | (crc_on << 4));
00567 
00568             //cfg_mode = read_register(REG_PACKETCONFIG2);
00569             write_to_register(REG_PACKETCONFIG2, read_register(REG_PACKETCONFIG2)
00570                              | RF_PACKETCONFIG2_DATAMODE_PACKET);
00571 
00572             break;
00573 
00574         case MODEM_LORA:
00575             _rf_settings.lora.power = power;
00576             _rf_settings.lora.bandwidth = bandwidth;
00577             _rf_settings.lora.datarate = datarate;
00578             _rf_settings.lora.coderate = coderate;
00579             _rf_settings.lora.preamble_len = preamble_len;
00580             _rf_settings.lora.fix_len = fix_len;
00581             _rf_settings.lora.freq_hop_on = freq_hop_on;
00582             _rf_settings.lora.hop_period = hop_period;
00583             _rf_settings.lora.crc_on = crc_on;
00584             _rf_settings.lora.iq_inverted = iq_inverted;
00585             _rf_settings.lora.tx_timeout = timeout;
00586 
00587             if (datarate > 12) {
00588                 datarate = 12;
00589             } else if (datarate < 6) {
00590                 datarate = 6;
00591             }
00592             if (((bandwidth == 0) && ((datarate == 11) || (datarate == 12)))
00593                     || ((bandwidth == 1) && (datarate == 12))) {
00594                 _rf_settings.lora.low_datarate_optimize = 0x01;
00595             } else {
00596                 _rf_settings.lora.low_datarate_optimize = 0x00;
00597             }
00598 
00599             if (_rf_settings.lora.freq_hop_on == true) {
00600                 write_to_register(REG_LR_PLLHOP, (read_register(REG_LR_PLLHOP)
00601                                 & RFLR_PLLHOP_FASTHOP_MASK)
00602                                 | RFLR_PLLHOP_FASTHOP_ON);
00603                 write_to_register(REG_LR_HOPPERIOD, _rf_settings.lora.hop_period);
00604             }
00605 
00606             write_to_register(REG_LR_MODEMCONFIG1, (read_register(REG_LR_MODEMCONFIG1) &
00607                     RFLR_MODEMCONFIG1_BW_MASK &
00608                     RFLR_MODEMCONFIG1_CODINGRATE_MASK &
00609                     RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
00610                     RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
00611                     RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK)
00612                             | (bandwidth << 6) | (coderate << 3)
00613                             | (fix_len << 2) | (crc_on << 1)
00614                             | _rf_settings.lora.low_datarate_optimize);
00615 
00616             write_to_register(REG_LR_MODEMCONFIG2,
00617                               (read_register(REG_LR_MODEMCONFIG2) &
00618                               RFLR_MODEMCONFIG2_SF_MASK) | (datarate << 4));
00619 
00620             write_to_register( REG_LR_PREAMBLEMSB, (preamble_len >> 8) & 0x00FF);
00621             write_to_register( REG_LR_PREAMBLELSB, preamble_len & 0xFF);
00622 
00623             if (datarate == 6) {
00624                 write_to_register(REG_LR_DETECTOPTIMIZE,
00625                                   (read_register(REG_LR_DETECTOPTIMIZE) &
00626                                   RFLR_DETECTIONOPTIMIZE_MASK) |
00627                                   RFLR_DETECTIONOPTIMIZE_SF6);
00628                 write_to_register( REG_LR_DETECTIONTHRESHOLD,
00629                 RFLR_DETECTIONTHRESH_SF6);
00630             } else {
00631                 write_to_register(REG_LR_DETECTOPTIMIZE,
00632                                   (read_register(REG_LR_DETECTOPTIMIZE) &
00633                                                  RFLR_DETECTIONOPTIMIZE_MASK) |
00634                                                  RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12);
00635                 write_to_register(REG_LR_DETECTIONTHRESHOLD,
00636                                   RFLR_DETECTIONTHRESH_SF7_TO_SF12);
00637             }
00638 
00639             break;
00640     }
00641 }
00642 
00643 /**
00644  * Calculates time on Air i.e., dwell time for a single packet
00645  *
00646  * Crucial for the stack in order to calculate dwell time so as to control
00647  * duty cycling.
00648  */
00649 uint32_t SX1272_LoRaRadio::time_on_air(radio_modems_t modem, uint8_t pkt_len)
00650 {
00651     uint32_t airtime = 0;
00652 
00653     switch (modem) {
00654         case MODEM_FSK: {
00655             airtime = rint((8 * (_rf_settings.fsk.preamble_len
00656                                     + ((read_register( REG_SYNCCONFIG)
00657                                             & ~RF_SYNCCONFIG_SYNCSIZE_MASK) + 1)
00658                                     + ((_rf_settings.fsk.fix_len == 0x01) ?
00659                                             0.0f : 1.0f)
00660                                     + (((read_register( REG_PACKETCONFIG1)
00661                                             & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK)
00662                                             != 0x00) ? 1.0f : 0) + pkt_len
00663                                     + ((_rf_settings.fsk.crc_on == 0x01) ?
00664                                             2.0f : 0))
00665                             / _rf_settings.fsk.datarate) * 1000);
00666         }
00667             break;
00668         case MODEM_LORA: {
00669             float bw = 0.0f;
00670             switch (_rf_settings.lora.bandwidth) {
00671                 case 0: // 125 kHz
00672                     bw = 125000;
00673                     break;
00674                 case 1: // 250 kHz
00675                     bw = 250000;
00676                     break;
00677                 case 2: // 500 kHz
00678                     bw = 500000;
00679                     break;
00680             }
00681 
00682             // Symbol rate : time for one symbol (secs)
00683             float rs = bw / (1 << _rf_settings.lora.datarate);
00684             float ts = 1 / rs;
00685             // time of preamble
00686             float preamble_time = (_rf_settings.lora.preamble_len + 4.25f) * ts;
00687             // Symbol length of payload and time
00688             float tmp = ceil((8 * pkt_len - 4 * _rf_settings.lora.datarate + 28
00689                             + 16 * _rf_settings.lora.crc_on -
00690                             (_rf_settings.lora.fix_len ? 20 : 0))
00691                             / (float) (4 * (_rf_settings.lora.datarate -
00692                                        ((_rf_settings.lora.low_datarate_optimize
00693                                                     > 0) ? 2 : 0)))) *
00694                                                     (_rf_settings.lora.coderate + 4);
00695             float n_payload = 8 + ((tmp > 0) ? tmp : 0);
00696             float t_payload = n_payload * ts;
00697             // Time on air
00698             float t_onair = preamble_time + t_payload;
00699             // return ms secs
00700             airtime = floor(t_onair * 1000 + 0.999f);
00701         }
00702             break;
00703     }
00704     return airtime;
00705 }
00706 
00707 /**
00708  * Prepares and sends the radio packet out in the air
00709  */
00710 void SX1272_LoRaRadio::send(uint8_t *buffer, uint8_t size)
00711 {
00712     uint32_t tx_timeout = 0;
00713 
00714     switch (_rf_settings.modem) {
00715         case MODEM_FSK:
00716 
00717             _rf_settings.fsk_packet_handler.nb_bytes = 0;
00718             _rf_settings.fsk_packet_handler.size = size;
00719 
00720             // FIFO operations can not take place in Sleep mode
00721             if ((read_register(REG_OPMODE) & ~RF_OPMODE_MASK) == RF_OPMODE_SLEEP) {
00722                 standby();
00723                 wait_ms(1);
00724             }
00725 
00726             if (_rf_settings.fsk.fix_len == false) {
00727                 write_fifo((uint8_t *) &size, 1);
00728             } else {
00729                 write_to_register(REG_PAYLOADLENGTH, size);
00730             }
00731 
00732             if ((size > 0) && (size <= 64)) {
00733                 _rf_settings.fsk_packet_handler.chunk_size = size;
00734             } else {
00735                 memcpy(_data_buffer, buffer, size);
00736                 _rf_settings.fsk_packet_handler.chunk_size = 32;
00737             }
00738 
00739             // write payload buffer
00740             write_fifo(buffer, _rf_settings.fsk_packet_handler.chunk_size);
00741             _rf_settings.fsk_packet_handler.nb_bytes +=
00742                     _rf_settings.fsk_packet_handler.chunk_size;
00743             tx_timeout = _rf_settings.fsk.tx_timeout;
00744 
00745             break;
00746         case MODEM_LORA:
00747             if (_rf_settings.lora.iq_inverted == true) {
00748                 write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) &
00749                                   RFLR_INVERTIQ_TX_MASK &
00750                                   RFLR_INVERTIQ_RX_MASK) |
00751                                   RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON));
00752                 write_to_register(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON);
00753             } else {
00754                 write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) &
00755                                   RFLR_INVERTIQ_TX_MASK &
00756                                   RFLR_INVERTIQ_RX_MASK) |
00757                                   RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF));
00758                 write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF);
00759             }
00760 
00761             _rf_settings.lora_packet_handler.size = size;
00762 
00763             // Initializes the payload size
00764             write_to_register(REG_LR_PAYLOADLENGTH, size);
00765 
00766             // Full buffer used for Tx
00767             write_to_register(REG_LR_FIFOTXBASEADDR, 0);
00768             write_to_register(REG_LR_FIFOADDRPTR, 0);
00769 
00770             // FIFO operations can not take place in Sleep mode
00771             if ((read_register(REG_OPMODE) & ~RF_OPMODE_MASK) == RF_OPMODE_SLEEP) {
00772                 standby();
00773                 wait_ms(1);
00774             }
00775             // write payload buffer
00776             write_fifo(buffer, size);
00777             tx_timeout = _rf_settings.lora.tx_timeout;
00778 
00779             break;
00780     }
00781 
00782     // transmit
00783     transmit(tx_timeout);
00784 }
00785 
00786 /**
00787  * Actual TX - Transmit routine
00788  *
00789  * A DIO0 interrupt let the state machine know that a a packet is
00790  * successfully sent, otherwise a TxTimeout is invoked.
00791  * TxTimeout should never happen in normal circumstances as the radio should
00792  * be able to send a packet out in the air no matter what.
00793  */
00794 void SX1272_LoRaRadio::transmit(uint32_t timeout)
00795 {
00796     switch (_rf_settings.modem) {
00797 
00798         case MODEM_FSK:
00799             // DIO0=PacketSent
00800             // DIO1=FifoEmpty
00801             // DIO2=FifoFull
00802             // DIO3=FifoEmpty
00803             // DIO4=LowBat
00804             // DIO5=ModeReady
00805             write_to_register(REG_DIOMAPPING1,(read_register(REG_DIOMAPPING1) &
00806                               RF_DIOMAPPING1_DIO0_MASK &
00807                               RF_DIOMAPPING1_DIO1_MASK &
00808                               RF_DIOMAPPING1_DIO2_MASK) |
00809                               RF_DIOMAPPING1_DIO1_01);
00810 
00811             write_to_register(REG_DIOMAPPING2, (read_register(REG_DIOMAPPING2) &
00812                               RF_DIOMAPPING2_DIO4_MASK &
00813                               RF_DIOMAPPING2_MAP_MASK));
00814             _rf_settings.fsk_packet_handler.fifo_thresh =
00815                               read_register(REG_FIFOTHRESH) & 0x3F;
00816 
00817             break;
00818 
00819         case MODEM_LORA:
00820 
00821             if (_rf_settings.lora.freq_hop_on == true) {
00822                 write_to_register(REG_LR_IRQFLAGSMASK,
00823                                   RFLR_IRQFLAGS_RXTIMEOUT |
00824                                   RFLR_IRQFLAGS_RXDONE |
00825                                   RFLR_IRQFLAGS_PAYLOADCRCERROR |
00826                                   RFLR_IRQFLAGS_VALIDHEADER |
00827                                   RFLR_IRQFLAGS_CADDONE |
00828                                   RFLR_IRQFLAGS_CADDETECTED);
00829 
00830                 // DIO0=tx_done, DIO2=fhss_change_channel
00831 
00832                 write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) &
00833                                   RFLR_DIOMAPPING1_DIO0_MASK &
00834                                   RFLR_DIOMAPPING1_DIO2_MASK) |
00835                                   RFLR_DIOMAPPING1_DIO0_01 |
00836                                   RFLR_DIOMAPPING1_DIO2_01);
00837             } else {
00838                 write_to_register(REG_LR_IRQFLAGSMASK,
00839                                   RFLR_IRQFLAGS_RXTIMEOUT |
00840                                   RFLR_IRQFLAGS_RXDONE |
00841                                   RFLR_IRQFLAGS_PAYLOADCRCERROR |
00842                                   RFLR_IRQFLAGS_VALIDHEADER |
00843                                   RFLR_IRQFLAGS_CADDONE |
00844                                   RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
00845                                   RFLR_IRQFLAGS_CADDETECTED);
00846 
00847                 // DIO0=tx_done
00848                 write_to_register(REG_DIOMAPPING1,(read_register(REG_DIOMAPPING1) &
00849                                   RFLR_DIOMAPPING1_DIO0_MASK) |
00850                                   RFLR_DIOMAPPING1_DIO0_01);
00851             }
00852 
00853             break;
00854     }
00855 
00856     _rf_settings.state = RF_TX_RUNNING;
00857     tx_timeout_timer.attach_us(callback(this, &SX1272_LoRaRadio::timeout_irq_isr),
00858                                timeout * 1000);
00859     set_operation_mode(RF_OPMODE_TRANSMITTER);
00860 }
00861 
00862 /**
00863  * Sets the radio module in receive mode
00864  *
00865  * A DIO4 interrupt let's the state machine know that a preamble is detected
00866  * and finally a DIO0 interrupt let's the state machine know that a packet is
00867  * ready to be read from the FIFO
00868  */
00869 void SX1272_LoRaRadio::receive(void)
00870 {
00871     switch (_rf_settings.modem) {
00872         case MODEM_FSK:
00873             // DIO0=PayloadReady
00874             // DIO1=FifoLevel
00875             // DIO2=RxTimeout
00876             // DIO3=FifoEmpty
00877             // DIO4=Preamble
00878             // DIO5=ModeReady
00879             write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) &
00880                               RF_DIOMAPPING1_DIO0_MASK &
00881                               RF_DIOMAPPING1_DIO1_MASK &
00882                               RF_DIOMAPPING1_DIO2_MASK) |
00883                               RF_DIOMAPPING1_DIO0_00 |
00884                               RF_DIOMAPPING1_DIO1_00 |
00885                               RF_DIOMAPPING1_DIO2_10);
00886 
00887             write_to_register(REG_DIOMAPPING2, (read_register(REG_DIOMAPPING2) &
00888                               RF_DIOMAPPING2_DIO4_MASK &
00889                               RF_DIOMAPPING2_MAP_MASK) |
00890                               RF_DIOMAPPING2_DIO4_11 |
00891                               RF_DIOMAPPING2_MAP_PREAMBLEDETECT);
00892 
00893             _rf_settings.fsk_packet_handler.fifo_thresh =
00894                               read_register(REG_FIFOTHRESH) & 0x3F;
00895 
00896             write_to_register(REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON |
00897                               RF_RXCONFIG_AGCAUTO_ON |
00898                               RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT);
00899 
00900             if (!_rf_settings.fsk.rx_continuous) {
00901                 // the value for rx timeout in symbols cannot be more than 255
00902                 // as the preamble length is fixed. We assert here for quick
00903                 // diagnostics
00904                 MBED_ASSERT(_rf_settings.fsk.rx_single_timeout <= 255);
00905                 write_to_register(REG_RXTIMEOUT2, _rf_settings.fsk.rx_single_timeout);
00906                 write_to_register(REG_RXTIMEOUT3, 0x00);
00907                 write_to_register(REG_RXTIMEOUT1, 0x00);
00908             }
00909 
00910             _rf_settings.fsk_packet_handler.preamble_detected = 0;
00911             _rf_settings.fsk_packet_handler.sync_word_detected = 0;
00912             _rf_settings.fsk_packet_handler.nb_bytes = 0;
00913             _rf_settings.fsk_packet_handler.size = 0;
00914 
00915             break;
00916 
00917         case MODEM_LORA:
00918 
00919             if (_rf_settings.lora.iq_inverted == true) {
00920                 write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) &
00921                                   RFLR_INVERTIQ_TX_MASK &
00922                                   RFLR_INVERTIQ_RX_MASK) |
00923                                   RFLR_INVERTIQ_RX_ON |
00924                                   RFLR_INVERTIQ_TX_OFF));
00925                 write_to_register(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON);
00926             } else {
00927                 write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) &
00928                                   RFLR_INVERTIQ_TX_MASK &
00929                                   RFLR_INVERTIQ_RX_MASK) |
00930                                   RFLR_INVERTIQ_RX_OFF |
00931                                   RFLR_INVERTIQ_TX_OFF));
00932                 write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF);
00933             }
00934 
00935             if (_rf_settings.lora.freq_hop_on == true) {
00936                 write_to_register(REG_LR_IRQFLAGSMASK,
00937                                   RFLR_IRQFLAGS_VALIDHEADER |
00938                                   RFLR_IRQFLAGS_TXDONE |
00939                                   RFLR_IRQFLAGS_CADDONE |
00940                                   RFLR_IRQFLAGS_CADDETECTED);
00941 
00942                 // DIO0=rx_done, DIO2=fhss_change_channel
00943                 write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) &
00944                                   RFLR_DIOMAPPING1_DIO0_MASK &
00945                                   RFLR_DIOMAPPING1_DIO2_MASK) |
00946                                   RFLR_DIOMAPPING1_DIO0_00 |
00947                                   RFLR_DIOMAPPING1_DIO2_00);
00948             } else {
00949                 write_to_register(REG_LR_IRQFLAGSMASK,
00950                                   RFLR_IRQFLAGS_VALIDHEADER |
00951                                   RFLR_IRQFLAGS_TXDONE |
00952                                   RFLR_IRQFLAGS_CADDONE |
00953                                   RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
00954                                   RFLR_IRQFLAGS_CADDETECTED);
00955 
00956                 // DIO0=rx_done
00957                 write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) &
00958                                   RFLR_DIOMAPPING1_DIO0_MASK) |
00959                                   RFLR_DIOMAPPING1_DIO0_00);
00960             }
00961 
00962             write_to_register(REG_LR_FIFORXBASEADDR, 0);
00963             write_to_register(REG_LR_FIFOADDRPTR, 0);
00964 
00965             break;
00966     }
00967 
00968     memset(_data_buffer, 0, (size_t) MAX_DATA_BUFFER_SIZE_SX172);
00969 
00970     _rf_settings.state = RF_RX_RUNNING;
00971 
00972     if (_rf_settings.modem == MODEM_FSK) {
00973         set_operation_mode(RF_OPMODE_RECEIVER);
00974         return;
00975     }
00976 
00977     // If mode is LoRa set mode
00978     if (_rf_settings.lora.rx_continuous == true) {
00979         set_operation_mode(RFLR_OPMODE_RECEIVER);
00980     } else {
00981         set_operation_mode(RFLR_OPMODE_RECEIVER_SINGLE);
00982     }
00983 }
00984 
00985 /**
00986  * Puts a limit on the size of payload the module can handle
00987  * By default it is MAX, i.e., 256 bytes
00988  */
00989 void SX1272_LoRaRadio::set_max_payload_length(radio_modems_t modem, uint8_t max)
00990 {
00991     set_modem(modem);
00992 
00993     switch (modem) {
00994         case MODEM_FSK:
00995             if (_rf_settings.fsk.fix_len == false) {
00996                 write_to_register(REG_PAYLOADLENGTH, max);
00997             }
00998             break;
00999         case MODEM_LORA:
01000             write_to_register(REG_LR_PAYLOADMAXLENGTH, max);
01001             break;
01002     }
01003 }
01004 
01005 /**
01006  * TODO: Making sure if this API is valid only for LoRa modulation ?
01007  *
01008  * Indicates if the node is part of a private or public network
01009  */
01010 void SX1272_LoRaRadio::set_public_network(bool enable)
01011 {
01012     set_modem(MODEM_LORA);
01013 
01014     _rf_settings.lora.public_network = enable;
01015     if (enable == true) {
01016         // Change lora modem SyncWord
01017         write_to_register(REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD);
01018     } else {
01019         // Change lora modem SyncWord
01020         write_to_register(REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD);
01021     }
01022 
01023 }
01024 
01025 /**
01026  * Perform carrier sensing
01027  *
01028  * Checks for a certain time if the RSSI is above a given threshold.
01029  * This threshold determines if there is already a transmission going on
01030  * in the channel or not.
01031  *
01032  */
01033 bool SX1272_LoRaRadio::perform_carrier_sense(radio_modems_t modem,
01034                                    uint32_t freq,
01035                                    int16_t rssi_threshold,
01036                                    uint32_t max_carrier_sense_time)
01037 {
01038     bool status = true;
01039     int16_t rssi = 0;
01040 
01041     set_modem(modem);
01042     set_channel(freq);
01043     set_operation_mode(RF_OPMODE_RECEIVER);
01044 
01045     // hold on a bit, radio turn-around time
01046     wait_ms(1);
01047 
01048     Timer elapsed_time;
01049     elapsed_time.start();
01050 
01051     // Perform carrier sense for maxCarrierSenseTime
01052     while (elapsed_time.read_ms() < (int)max_carrier_sense_time) {
01053         rssi = get_rssi(modem);
01054 
01055         if (rssi > rssi_threshold) {
01056             status = false;
01057             break;
01058         }
01059     }
01060 
01061     sleep();
01062     return status;
01063 }
01064 
01065 /**
01066  * Channel Activity detection (can be done only in LoRa mode)
01067  *
01068  * If any activity on the channel is detected, an interrupt is asserted on
01069  * DIO3. A callback will be generated to the stack/application upon the
01070  * assertion of DIO3.
01071  */
01072 void SX1272_LoRaRadio::start_cad()
01073 {
01074     uint8_t reg_val;
01075 
01076     switch (_rf_settings.modem) {
01077         case MODEM_FSK:
01078             break;
01079         case MODEM_LORA:
01080             write_to_register(REG_LR_IRQFLAGSMASK,
01081                               RFLR_IRQFLAGS_RXTIMEOUT |
01082                               RFLR_IRQFLAGS_RXDONE |
01083                               RFLR_IRQFLAGS_PAYLOADCRCERROR |
01084                               RFLR_IRQFLAGS_VALIDHEADER |
01085                               RFLR_IRQFLAGS_TXDONE |
01086                               RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL);
01087 
01088             // DIO3=CADDone
01089             reg_val = read_register(REG_DIOMAPPING1);
01090             write_to_register(REG_DIOMAPPING1, (reg_val &
01091                               RFLR_DIOMAPPING1_DIO3_MASK) |
01092                               RFLR_DIOMAPPING1_DIO3_00);
01093 
01094             set_operation_mode(RFLR_OPMODE_CAD);
01095 
01096             _rf_settings.state = RF_CAD;
01097 
01098             break;
01099         default:
01100             break;
01101     }
01102 }
01103 
01104 /**
01105  * Set transmission in continuous wave mode
01106  */
01107 void SX1272_LoRaRadio::set_tx_continuous_wave(uint32_t freq, int8_t power,
01108                                               uint16_t time)
01109 {
01110     uint8_t reg_val;
01111 
01112     set_channel(freq);
01113     set_tx_config(MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, time * 1000);
01114     reg_val = read_register(REG_PACKETCONFIG2);
01115 
01116     write_to_register( REG_PACKETCONFIG2, (reg_val & RF_PACKETCONFIG2_DATAMODE_MASK ) );
01117     // Disable radio interrupts
01118     write_to_register( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
01119     write_to_register( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
01120 
01121     _rf_settings.state = RF_TX_RUNNING;
01122     tx_timeout_timer.attach_us(callback(this, &SX1272_LoRaRadio::timeout_irq_isr), time * 1000000);
01123     set_operation_mode(RF_OPMODE_TRANSMITTER);
01124 }
01125 
01126 /**
01127  * Put radio in Standby mode
01128  */
01129 void SX1272_LoRaRadio::standby( void )
01130 {
01131     tx_timeout_timer.detach();
01132     set_operation_mode(RF_OPMODE_STANDBY);
01133     _rf_settings.state = RF_IDLE;
01134 }
01135 
01136 /**
01137  * Generates 32 bit random number based upon RSSI monitoring
01138  * Used for various calculation by the stack for example dev nonce
01139  *
01140  * When this API is used modem is set in LoRa mode and all interrupts are
01141  * masked. If the user had been using FSK mode, it should be noted that a
01142  * change of mode is required again because the registers have changed.
01143  * In addition to that RX and TX configuration APIs should be called again in
01144  * order to have correct desires setup.
01145  */
01146 uint32_t SX1272_LoRaRadio::random()
01147 {
01148     uint8_t i;
01149     uint32_t rnd = 0;
01150 
01151     // Set LoRa modem ON
01152     set_modem(MODEM_LORA);
01153 
01154     // Disable LoRa modem interrupts, i.e., mask all interrupts
01155     write_to_register(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | RFLR_IRQFLAGS_RXDONE
01156                       | RFLR_IRQFLAGS_PAYLOADCRCERROR | RFLR_IRQFLAGS_VALIDHEADER
01157                       | RFLR_IRQFLAGS_TXDONE | RFLR_IRQFLAGS_CADDONE
01158                       | RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | RFLR_IRQFLAGS_CADDETECTED);
01159 
01160     // Set radio in continuous reception
01161     set_operation_mode(RF_OPMODE_RECEIVER);
01162 
01163     for (i = 0; i < 32; i++) {
01164         wait_ms(1);
01165         // Unfiltered RSSI value reading. Only takes the LSB value
01166         rnd |= ((uint32_t) read_register(REG_LR_RSSIWIDEBAND) & 0x01) << i;
01167     }
01168 
01169     sleep();
01170 
01171     return rnd;
01172 }
01173 
01174 
01175 /*****************************************************************************
01176  * Private APIs                                                              *
01177  ****************************************************************************/
01178 #ifdef MBED_CONF_RTOS_PRESENT
01179 /**
01180  * Thread task handling IRQs
01181  */
01182 void SX1272_LoRaRadio::rf_irq_task(void)
01183 {
01184     for (;;) {
01185         osEvent event = irq_thread.signal_wait(0, osWaitForever);
01186         if (event.status != osEventSignal) {
01187             continue;
01188         }
01189 
01190         lock();
01191         if (event.value.signals & SIG_DIO0) {
01192             handle_dio0_irq();
01193         }
01194         if (event.value.signals & SIG_DIO1) {
01195             handle_dio1_irq();
01196         }
01197         if (event.value.signals & SIG_DIO2) {
01198             handle_dio2_irq();
01199         }
01200         if (event.value.signals & SIG_DIO3) {
01201             handle_dio3_irq();
01202         }
01203         if (event.value.signals & SIG_DIO4) {
01204             handle_dio4_irq();
01205         }
01206         if (event.value.signals & SIG_DIO5) {
01207             handle_dio5_irq();
01208         }
01209         if (event.value.signals & SIG_TIMOUT) {
01210             handle_timeout_irq();
01211         }
01212         unlock();
01213     }
01214 }
01215 #endif
01216 
01217 /**
01218  * Writes a single byte to a given register
01219  */
01220 void SX1272_LoRaRadio::write_to_register(uint8_t addr, uint8_t data)
01221 {
01222     write_to_register(addr, &data, 1);
01223 }
01224 
01225 /**
01226  * Writes multiple bytes to a given register
01227  */
01228 void SX1272_LoRaRadio::write_to_register(uint8_t addr, uint8_t *data, uint8_t size)
01229 {
01230     // set chip-select low
01231     _chip_select = 0;
01232 
01233     // set write command
01234     _spi.write(addr | SPI_WRITE_CMD);
01235 
01236     // write data
01237     for (uint8_t i = 0; i < size; i++) {
01238         _spi.write(data[i]);
01239     }
01240 
01241     // set chip-select high
01242     _chip_select = 1;
01243 }
01244 
01245 /**
01246  * Reads the value of a single register
01247  */
01248 uint8_t SX1272_LoRaRadio::read_register(uint8_t addr)
01249 {
01250     uint8_t data;
01251     read_register(addr, &data, 1);
01252     return data;
01253 }
01254 
01255 /**
01256  * Reads multiple values from a given register
01257  */
01258 void SX1272_LoRaRadio::read_register(uint8_t addr, uint8_t *buffer, uint8_t size)
01259 {
01260     // set chip-select low
01261     _chip_select = 0;
01262 
01263     // set read command
01264     _spi.write(addr & SPI_READ_CMD);
01265 
01266     // read buffers
01267     for (uint8_t i = 0; i < size; i++) {
01268         buffer[i] = _spi.write(0);
01269     }
01270 
01271     // set chip-select high
01272     _chip_select = 1;
01273 }
01274 
01275 /**
01276  * Writes to FIIO provided by the chip
01277  */
01278 void SX1272_LoRaRadio::write_fifo(uint8_t *buffer, uint8_t size)
01279 {
01280     write_to_register(0, buffer, size);
01281 }
01282 
01283 /**
01284  * Reads from the FIFO provided by the chip
01285  */
01286 void SX1272_LoRaRadio::read_fifo(uint8_t *buffer, uint8_t size)
01287 {
01288     read_register(0, buffer, size);
01289 }
01290 
01291 /**
01292  * Gets FSK bandwidth values
01293  *
01294  * Gives either normal bandwidths or bandwidths for
01295  * AFC (auto frequency correction)
01296  */
01297 uint8_t SX1272_LoRaRadio::get_fsk_bw_reg_val(uint32_t bandwidth)
01298 {
01299     uint8_t i;
01300 
01301     for (i = 0; i < (sizeof(fsk_bandwidths) / sizeof(fsk_bw_t)) - 1; i++) {
01302         if ((bandwidth >= fsk_bandwidths[i].bandwidth)
01303                 && (bandwidth < fsk_bandwidths[i + 1].bandwidth)) {
01304             return fsk_bandwidths[i].register_value;
01305         }
01306     }
01307     // ERROR: Value not found
01308     // This should never happen
01309     while (1);
01310 }
01311 
01312 /**
01313  * Sets the radio modules to default position (off)
01314  *
01315  * Historically they were being called as Antenna switches, so we kept the name.
01316  * In essence these are control latches over duplexer which either let
01317  * TX submodule or RX submodule circuitry enabled at a time.
01318  */
01319 void SX1272_LoRaRadio::default_antenna_switch_ctrls()
01320 {
01321     if (_rf_ctrls.pwr_amp_ctl != NC) {
01322         _pwr_amp_ctl = 0;
01323     }
01324 
01325     if (_rf_ctrls.rf_switch_ctl1 != NC && _rf_ctrls.rf_switch_ctl2 != NC) {
01326         _rf_switch_ctl1 = 0;
01327         _rf_switch_ctl2 = 0;
01328     }
01329 
01330     if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) {
01331         _txctl = 0;
01332         _rxctl = 0;
01333     }
01334 }
01335 
01336 /**
01337  * Gets the power amplifier configuration register
01338  */
01339 uint8_t SX1272_LoRaRadio::get_pa_conf_reg()
01340 {
01341     if (radio_variant == SX1272UNDEFINED) {
01342         return RF_PACONFIG_PASELECT_PABOOST;
01343     } else if (radio_variant == SX1272MB1DCS) {
01344         return RF_PACONFIG_PASELECT_PABOOST;
01345     } else {
01346         return RF_PACONFIG_PASELECT_RFO;
01347     }
01348 }
01349 
01350 /**
01351  * Get RSSI from the module
01352  */
01353 int16_t SX1272_LoRaRadio::get_rssi(radio_modems_t modem)
01354 {
01355     int16_t rssi = 0;
01356 
01357     switch( modem )
01358     {
01359     case MODEM_FSK:
01360         rssi = -(read_register(REG_RSSIVALUE) >> 1 );
01361         break;
01362     case MODEM_LORA:
01363         rssi = RSSI_OFFSET + read_register(REG_LR_RSSIVALUE);
01364         break;
01365     default:
01366         rssi = -1;
01367         break;
01368     }
01369     return rssi;
01370 }
01371 
01372 /**
01373  * Sets the transmit power for the module
01374  */
01375 #if defined ( TARGET_MOTE_L152RC )
01376 static const uint8_t pa_boost_table[20] = {0, 0, 0, 0, 0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15};
01377 static const uint8_t RFO_table[11] = {1, 1, 1, 2, 2, 3, 4, 5, 6, 8, 9};
01378 #endif
01379 
01380 void SX1272_LoRaRadio::set_rf_tx_power(int8_t power)
01381 {
01382     uint8_t pa_config = 0;
01383     uint8_t pa_dac = 0;
01384 
01385     pa_config = read_register(REG_PACONFIG);
01386     pa_dac = read_register(REG_PADAC);
01387 
01388 #if defined ( TARGET_MOTE_L152RC )
01389     if(power > 19) {
01390         pa_config = (pa_config & RF_PACONFIG_PASELECT_MASK) | RF_PACONFIG_PASELECT_RFO;
01391         pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK) | RFO_table[power - 20];
01392     }
01393     else
01394     {
01395         pa_config = (pa_config & RF_PACONFIG_PASELECT_MASK) | RF_PACONFIG_PASELECT_PABOOST;
01396         pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK) | pa_boost_table[power];
01397     }
01398 #else
01399     pa_config = (pa_config & RF_PACONFIG_PASELECT_MASK) | get_pa_conf_reg();
01400 
01401     if ((pa_config & RF_PACONFIG_PASELECT_PABOOST)
01402             == RF_PACONFIG_PASELECT_PABOOST) {
01403         if (power > 17) {
01404             pa_dac = (pa_dac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_ON;
01405         } else {
01406             pa_dac = (pa_dac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_OFF;
01407         }
01408         if ((pa_dac & RF_PADAC_20DBM_ON) == RF_PADAC_20DBM_ON) {
01409             if (power < 5) {
01410                 power = 5;
01411             }
01412             if (power > 20) {
01413                 power = 20;
01414             }
01415             pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK)
01416                     | (uint8_t) ((uint16_t) (power - 5) & 0x0F);
01417         } else {
01418             if (power < 2) {
01419                 power = 2;
01420             }
01421             if (power > 17) {
01422                 power = 17;
01423             }
01424             pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK)
01425                     | (uint8_t) ((uint16_t) (power - 2) & 0x0F);
01426         }
01427     } else {
01428         if (power < -1) {
01429             power = -1;
01430         }
01431         if (power > 14) {
01432             power = 14;
01433         }
01434         pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK)
01435                 | (uint8_t) ((uint16_t) (power + 1) & 0x0F);
01436     }
01437 #endif
01438     write_to_register(REG_PACONFIG, pa_config);
01439     write_to_register(REG_PADAC, pa_dac);
01440 }
01441 
01442 /**
01443  * Sets the radio registers to defaults
01444  */
01445 void SX1272_LoRaRadio::setup_registers()
01446 {
01447     for (unsigned int i = 0; i < sizeof(radio_reg_init) / sizeof(radio_registers_t); i++) {
01448         set_modem(radio_reg_init[i].modem);
01449         write_to_register(radio_reg_init[i].addr, radio_reg_init[i].value);
01450     }
01451 }
01452 
01453 /**
01454  * Set the radio module variant
01455  */
01456 void SX1272_LoRaRadio::set_sx1272_variant_type()
01457 {
01458     if (_rf_ctrls.ant_switch != NC){
01459         _ant_switch.input();
01460         wait_ms(1);
01461         if (_ant_switch == 1) {
01462             radio_variant = SX1272MB1DCS;
01463         } else {
01464             radio_variant = SX1272MB2XAS;
01465         }
01466         _ant_switch.output();
01467         wait_ms(1);
01468     } else {
01469         radio_variant = SX1272UNDEFINED;
01470     }
01471 }
01472 
01473 /**
01474  * Sets up radio latch position according to the
01475  * radio mode
01476  */
01477 void SX1272_LoRaRadio::set_antenna_switch(uint8_t mode)
01478 {
01479     // here we got to do ifdef for changing controls
01480     // as some pins might be NC
01481     switch (mode) {
01482         case RFLR_OPMODE_TRANSMITTER:
01483             if (_rf_ctrls.rf_switch_ctl1 != NC
01484                 && _rf_ctrls.rf_switch_ctl2 != NC) {
01485                 // module is in transmit mode and RF latch switches
01486                 // are connected. Check if power amplifier boost is
01487                 // setup or not
01488                 if ((read_register(REG_PACONFIG) & RF_PACONFIG_PASELECT_PABOOST)
01489                                        == RF_PACONFIG_PASELECT_PABOOST) {
01490                     _rf_switch_ctl1 = 1;
01491                     _rf_switch_ctl2 = 0;
01492                 } else {
01493                     // power amplifier not selected
01494                     _rf_switch_ctl1 = 0;
01495                     _rf_switch_ctl2 = 1;
01496                 }
01497             } else if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) {
01498                 // module is in transmit mode and tx/rx submodule control
01499                 // pins are connected
01500                 _txctl = 1;
01501                 _rxctl = 0;
01502             } else if (_rf_ctrls.ant_switch != NC){
01503                 _ant_switch = 1;
01504             } else {
01505                 // None of the control pins are connected.
01506             }
01507             break;
01508         case RFLR_OPMODE_RECEIVER:
01509         case RFLR_OPMODE_RECEIVER_SINGLE:
01510         case RFLR_OPMODE_CAD:
01511             if (_rf_ctrls.rf_switch_ctl1 != NC
01512                 && _rf_ctrls.rf_switch_ctl2 != NC) {
01513                 // radio is in reception or CAD mode and RF latch switches
01514                 // are connected
01515                 _rf_switch_ctl1 = 1;
01516                 _rf_switch_ctl2 = 1;
01517             } else if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) {
01518                 _txctl = 0;
01519                 _rxctl = 1;
01520             } else if (_rf_ctrls.ant_switch != NC) {
01521                 _ant_switch = 0;
01522             } else {
01523                 // None of the control pins are connected.
01524             }
01525             break;
01526         default:
01527             // Enforce default case  when any connected control pin is kept low.
01528             if (_rf_ctrls.rf_switch_ctl1 != NC
01529                 && _rf_ctrls.rf_switch_ctl2 != NC) {
01530                 // radio is in reception or CAD mode and RF latch switches
01531                 // are connected
01532                 _rf_switch_ctl1 = 0;
01533                 _rf_switch_ctl2 = 0;
01534             } else if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) {
01535                 _txctl = 0;
01536                 _rxctl = 0;
01537             } else if (_rf_ctrls.ant_switch != NC) {
01538                 _ant_switch = 0;
01539             } else {
01540                 // None of the control pins are connected.
01541             }
01542             break;
01543     }
01544 }
01545 
01546 /**
01547  * Sets up frequency for SPI module
01548  * Reference DataSheet: 4.3 SPI Interface
01549  */
01550 void SX1272_LoRaRadio::setup_spi()
01551 {
01552     // SPI bus frequency
01553     uint32_t spi_freq = SPI_FREQUENCY;
01554 
01555     // Hold chip-select high
01556     _chip_select = 1;
01557     _spi.format(8, 0);
01558 
01559 #if defined (TARGET_KL25Z)
01560     //bus-clock frequency is halved -> double the SPI frequency to compensate
01561     _spi.frequency(spi_freq * 2);
01562 #else
01563     // otherwise use default SPI frequency which is 8 MHz
01564     _spi.frequency(spi_freq);
01565 #endif
01566     // 100 us wait to settle down
01567     wait(0.1);
01568 }
01569 
01570 /**
01571  * Attaches ISRs to interrupt pins
01572  */
01573 void SX1272_LoRaRadio::setup_interrupts()
01574 {
01575     _dio0_ctl.rise(callback(this, &SX1272_LoRaRadio::dio0_irq_isr));
01576     _dio1_ctl.rise(callback(this, &SX1272_LoRaRadio::dio1_irq_isr));
01577     _dio2_ctl.rise(callback(this, &SX1272_LoRaRadio::dio2_irq_isr));
01578     _dio3_ctl.rise(callback(this, &SX1272_LoRaRadio::dio3_irq_isr));
01579     if (_dio4_pin != NC) {
01580         _dio4_ctl.rise(callback(this, &SX1272_LoRaRadio::dio4_irq_isr));
01581     }
01582     if (_dio5_pin != NC) {
01583         _dio5_ctl.rise(callback(this, &SX1272_LoRaRadio::dio5_irq_isr));
01584     }
01585 }
01586 
01587 /**
01588  * Sets the module in low power mode by disconnecting
01589  * TX and RX submodules, turning off power amplifier etc.
01590  */
01591 void SX1272_LoRaRadio::set_low_power_mode(bool status)
01592 {
01593     if (radio_is_active != status) {
01594         radio_is_active = status;
01595 
01596         if (status == false) {
01597             if (_rf_ctrls.rf_switch_ctl1 != NC) {
01598                 _rf_switch_ctl1 = 0;
01599             }
01600             if (_rf_ctrls.rf_switch_ctl2 != NC) {
01601                 _rf_switch_ctl2 = 0;
01602             }
01603 
01604             if (_rf_ctrls.pwr_amp_ctl != NC) {
01605                 _pwr_amp_ctl = 0;
01606             }
01607 
01608             if (_rf_ctrls.txctl != NC) {
01609                 _txctl = 0;
01610             }
01611 
01612             if (_rf_ctrls.rxctl != NC) {
01613                 _rxctl = 0;
01614             }
01615 
01616             if (_rf_ctrls.ant_switch != NC) {
01617                 _ant_switch = 0;
01618             }
01619         } else {
01620             default_antenna_switch_ctrls();
01621         }
01622     }
01623 }
01624 
01625 /*****************************************************************************
01626  * Interrupt service routines (ISRs) - set signals to the irq_thread         *
01627  ****************************************************************************/
01628 void SX1272_LoRaRadio::dio0_irq_isr()
01629 {
01630 #ifdef MBED_CONF_RTOS_PRESENT
01631    irq_thread.signal_set(SIG_DIO0);
01632 #else
01633    handle_dio0_irq();
01634 #endif
01635 }
01636 
01637 void SX1272_LoRaRadio::dio1_irq_isr()
01638 {
01639 #ifdef MBED_CONF_RTOS_PRESENT
01640     irq_thread.signal_set(SIG_DIO1);
01641 #else
01642     handle_dio1_irq();
01643 #endif
01644 }
01645 
01646 void SX1272_LoRaRadio::dio2_irq_isr()
01647 {
01648 #ifdef MBED_CONF_RTOS_PRESENT
01649     irq_thread.signal_set(SIG_DIO2);
01650 #else
01651     handle_dio2_irq();
01652 #endif
01653 }
01654 
01655 void SX1272_LoRaRadio::dio3_irq_isr()
01656 {
01657 #ifdef MBED_CONF_RTOS_PRESENT
01658     irq_thread.signal_set(SIG_DIO3);
01659 #else
01660     handle_dio3_irq();
01661 #endif
01662 }
01663 
01664 void SX1272_LoRaRadio::dio4_irq_isr()
01665 {
01666 #ifdef MBED_CONF_RTOS_PRESENT
01667     irq_thread.signal_set(SIG_DIO4);
01668 #else
01669     handle_dio4_irq();
01670 #endif
01671 }
01672 
01673 void SX1272_LoRaRadio::dio5_irq_isr()
01674 {
01675 #ifdef MBED_CONF_RTOS_PRESENT
01676     irq_thread.signal_set(SIG_DIO5);
01677 #else
01678     handle_dio5_irq();
01679 #endif
01680 }
01681 
01682 // This is not a hardware interrupt
01683 // we invoke it ourselves based upon
01684 // our timers
01685 void SX1272_LoRaRadio::timeout_irq_isr()
01686 {
01687 #ifdef MBED_CONF_RTOS_PRESENT
01688     irq_thread.signal_set(SIG_TIMOUT);
01689 #else
01690     handle_timeout_irq();
01691 #endif
01692 }
01693 
01694 /******************************************************************************
01695  * Interrupt Handlers                                                         *
01696  *****************************************************************************/
01697 
01698 void SX1272_LoRaRadio::handle_dio0_irq()
01699 {
01700     volatile uint8_t irqFlags = 0;
01701 
01702     switch (_rf_settings.state) {
01703         case RF_RX_RUNNING:
01704             switch (_rf_settings.modem) {
01705                 case MODEM_FSK:
01706                     if (_rf_settings.fsk.crc_on == true) {
01707                         irqFlags = read_register(REG_IRQFLAGS2);
01708                         if ((irqFlags & RF_IRQFLAGS2_CRCOK)
01709                                 != RF_IRQFLAGS2_CRCOK) {
01710                             // Clear Irqs
01711                             write_to_register(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
01712                                               RF_IRQFLAGS1_PREAMBLEDETECT |
01713                                               RF_IRQFLAGS1_SYNCADDRESSMATCH);
01714                             write_to_register(REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN);
01715 
01716 
01717                             if (_rf_settings.fsk.rx_continuous == false) {
01718                                 _rf_settings.state = RF_IDLE;
01719                             } else {
01720                                 // Continuous mode restart Rx chain
01721                                 write_to_register(REG_RXCONFIG,
01722                                                   read_register(REG_RXCONFIG) |
01723                                                   RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK);
01724                             }
01725 
01726                             if ((_radio_events != NULL)
01727                                     && (_radio_events->rx_error)) {
01728                                 _radio_events->rx_error();
01729                             }
01730                             _rf_settings.fsk_packet_handler.preamble_detected = 0;
01731                             _rf_settings.fsk_packet_handler.sync_word_detected = 0;
01732                             _rf_settings.fsk_packet_handler.nb_bytes = 0;
01733                             _rf_settings.fsk_packet_handler.size = 0;
01734                             // break from here, a CRC error happened, RX_ERROR
01735                             // was notified. No need to go any further
01736                             break;
01737                         }
01738                     }
01739 
01740                     // This block was moved from dio2_handler.
01741                     // We can have a snapshot of RSSI here as at this point it
01742                     // should be more smoothed out.
01743                     _rf_settings.fsk_packet_handler.rssi_value = -(read_register(REG_RSSIVALUE) >> 1);
01744                     _rf_settings.fsk_packet_handler.afc_value = (int32_t)(float)(((uint16_t)read_register(REG_AFCMSB) << 8) |
01745                                                                                    (uint16_t)read_register(REG_AFCLSB)) *
01746                                                                                    (float)FREQ_STEP;
01747                     _rf_settings.fsk_packet_handler.rx_gain = (read_register(REG_LNA) >> 5) & 0x07;
01748 
01749                     // Read received packet size
01750                     if ((_rf_settings.fsk_packet_handler.size == 0)
01751                             && (_rf_settings.fsk_packet_handler.nb_bytes == 0)) {
01752                         if (_rf_settings.fsk.fix_len == false) {
01753                             read_fifo((uint8_t*) &_rf_settings.fsk_packet_handler.size, 1);
01754                         } else {
01755                             _rf_settings.fsk_packet_handler.size = read_register(REG_PAYLOADLENGTH);
01756                         }
01757                         read_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes,
01758                                 _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes);
01759                         _rf_settings.fsk_packet_handler.nb_bytes +=
01760                                 (_rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes);
01761                     } else {
01762                         read_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes,
01763                                 _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes);
01764                         _rf_settings.fsk_packet_handler.nb_bytes +=
01765                                 (_rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes);
01766                     }
01767 
01768                     if (_rf_settings.fsk.rx_continuous == false) {
01769                         _rf_settings.state = RF_IDLE;
01770                     } else {
01771                         // Continuous mode restart Rx chain
01772                         write_to_register(REG_RXCONFIG, read_register(REG_RXCONFIG)
01773                                         | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK);
01774                     }
01775 
01776                     if ((_radio_events != NULL) && (_radio_events->rx_done)) {
01777                         _radio_events->rx_done(
01778                                 _data_buffer,
01779                                 _rf_settings.fsk_packet_handler.size,
01780                                 _rf_settings.fsk_packet_handler.rssi_value, 0);
01781                     }
01782                     _rf_settings.fsk_packet_handler.preamble_detected = 0;
01783                     _rf_settings.fsk_packet_handler.sync_word_detected = 0;
01784                     _rf_settings.fsk_packet_handler.nb_bytes = 0;
01785                     _rf_settings.fsk_packet_handler.size = 0;
01786                     break;
01787                 case MODEM_LORA: {
01788                     int8_t snr = 0;
01789 
01790                     // Clear Irq
01791                     write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE);
01792 
01793                     irqFlags = read_register(REG_LR_IRQFLAGS);
01794                     if ((irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK)
01795                             == RFLR_IRQFLAGS_PAYLOADCRCERROR) {
01796                         // Clear Irq
01797                         write_to_register(REG_LR_IRQFLAGS,
01798                                           RFLR_IRQFLAGS_PAYLOADCRCERROR);
01799 
01800                         if (_rf_settings.lora.rx_continuous == false) {
01801                             _rf_settings.state = RF_IDLE;
01802                         }
01803 
01804                         if ((_radio_events != NULL)
01805                                 && (_radio_events->rx_error)) {
01806                             _radio_events->rx_error();
01807                         }
01808                         break;
01809                     }
01810 
01811                     _rf_settings.lora_packet_handler.snr_value = read_register(REG_LR_PKTSNRVALUE);
01812                     if (_rf_settings.lora_packet_handler.snr_value & 0x80) // The SNR sign bit is 1
01813                             {
01814                         // Invert and divide by 4
01815                         snr = ((~_rf_settings.lora_packet_handler.snr_value + 1) & 0xFF) >> 2;
01816                         snr = -snr;
01817                     } else {
01818                         // Divide by 4
01819                         snr =(_rf_settings.lora_packet_handler.snr_value & 0xFF) >> 2;
01820                     }
01821 
01822                     int16_t rssi = read_register(REG_LR_PKTRSSIVALUE);
01823                     if (snr < 0) {
01824                         _rf_settings.lora_packet_handler.rssi_value =
01825                                 RSSI_OFFSET + rssi + (rssi >> 4) + snr;
01826                     } else {
01827                         _rf_settings.lora_packet_handler.rssi_value =
01828                                 RSSI_OFFSET + rssi + (rssi >> 4);
01829                     }
01830 
01831                     _rf_settings.lora_packet_handler.size = read_register(REG_LR_RXNBBYTES);
01832                     read_fifo(_data_buffer, _rf_settings.lora_packet_handler.size);
01833 
01834                     if (_rf_settings.lora.rx_continuous == false) {
01835                         _rf_settings.state = RF_IDLE;
01836                     }
01837 
01838                     if ((_radio_events != NULL)
01839                             && (_radio_events->rx_done)) {
01840                         _radio_events->rx_done(
01841                                 _data_buffer,
01842                                 _rf_settings.lora_packet_handler.size,
01843                                 _rf_settings.lora_packet_handler.rssi_value,
01844                                 _rf_settings.lora_packet_handler.snr_value);
01845                     }
01846                 }
01847                     break;
01848                 default:
01849                     break;
01850             }
01851             break;
01852         case RF_TX_RUNNING:
01853             tx_timeout_timer.detach();
01854             // TxDone interrupt
01855             switch (_rf_settings.modem) {
01856                 case MODEM_LORA:
01857                     // Clear Irq
01858                     write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE);
01859                     // Intentional fall through
01860                 case MODEM_FSK:
01861                 default:
01862                     _rf_settings.state = RF_IDLE;
01863                     if ((_radio_events != NULL)
01864                             && (_radio_events->tx_done)) {
01865                         _radio_events->tx_done();
01866                     }
01867                     break;
01868             }
01869             break;
01870         default:
01871             break;
01872     }
01873 }
01874 
01875 void SX1272_LoRaRadio::handle_dio1_irq()
01876 {
01877 
01878     switch(_rf_settings.state )
01879        {
01880            case RF_RX_RUNNING:
01881                switch(_rf_settings.modem ) {
01882                case MODEM_FSK:
01883                    // FifoLevel interrupt
01884                    // Read received packet size
01885                    if( ( _rf_settings.fsk_packet_handler.size == 0 ) && ( _rf_settings.fsk_packet_handler.nb_bytes == 0 ) )
01886                    {
01887                        if( _rf_settings.fsk.fix_len == false )
01888                        {
01889                            read_fifo( ( uint8_t* )&_rf_settings.fsk_packet_handler.size, 1 );
01890                        }
01891                        else
01892                        {
01893                            _rf_settings.fsk_packet_handler.size = read_register(REG_PAYLOADLENGTH);
01894                        }
01895                    }
01896 
01897                    if( ( _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes ) > _rf_settings.fsk_packet_handler.fifo_thresh )
01898                    {
01899                        read_fifo( ( _data_buffer + _rf_settings.fsk_packet_handler.nb_bytes ), _rf_settings.fsk_packet_handler.fifo_thresh );
01900                        _rf_settings.fsk_packet_handler.nb_bytes += _rf_settings.fsk_packet_handler.fifo_thresh;
01901                    }
01902                    else
01903                    {
01904                        read_fifo( ( _data_buffer + _rf_settings.fsk_packet_handler.nb_bytes ), _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes );
01905                        _rf_settings.fsk_packet_handler.nb_bytes += ( _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes );
01906                    }
01907                    break;
01908                case MODEM_LORA:
01909                    // Sync time out
01910                    _rf_settings.state = RF_IDLE;
01911                    if ((_radio_events != NULL) && (_radio_events->rx_timeout)) {
01912                         _radio_events->rx_timeout();
01913                     }
01914                    break;
01915                default:
01916                    break;
01917                }
01918                break;
01919            case RF_TX_RUNNING:
01920                switch( _rf_settings.modem )
01921                {
01922                case MODEM_FSK:
01923                    // FifoLevel interrupt
01924                    if( ( _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes ) > _rf_settings.fsk_packet_handler.chunk_size )
01925                    {
01926                        write_fifo(( _data_buffer + _rf_settings.fsk_packet_handler.nb_bytes ), _rf_settings.fsk_packet_handler.chunk_size );
01927                        _rf_settings.fsk_packet_handler.nb_bytes += _rf_settings.fsk_packet_handler.chunk_size;
01928                    }
01929                    else
01930                    {
01931                        // Write the last chunk of data
01932                        write_fifo( _data_buffer + _rf_settings.fsk_packet_handler.nb_bytes, _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes );
01933                        _rf_settings.fsk_packet_handler.nb_bytes += _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes;
01934                    }
01935                    break;
01936                case MODEM_LORA:
01937                    break;
01938                default:
01939                    break;
01940                }
01941                break;
01942            default:
01943                break;
01944        }
01945 }
01946 
01947 void SX1272_LoRaRadio::handle_dio2_irq(void)
01948 {
01949     switch(_rf_settings.state )
01950     {
01951         case RF_RX_RUNNING:
01952             switch( _rf_settings.modem )
01953             {
01954             case MODEM_FSK:
01955                 _rf_settings.fsk_packet_handler.preamble_detected = 0;
01956                 _rf_settings.fsk_packet_handler.sync_word_detected = 0;
01957                 _rf_settings.fsk_packet_handler.nb_bytes = 0;
01958                 _rf_settings.fsk_packet_handler.size = 0;
01959 
01960                 // Clear Irqs
01961                 write_to_register(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
01962                                   RF_IRQFLAGS1_PREAMBLEDETECT |
01963                                   RF_IRQFLAGS1_SYNCADDRESSMATCH |
01964                                   RF_IRQFLAGS1_TIMEOUT);
01965 
01966                 write_to_register( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN);
01967 
01968                 if (_rf_settings.fsk.rx_continuous == true) {
01969                     // Continuous mode restart Rx chain
01970                     write_to_register( REG_RXCONFIG,
01971                                       read_register(REG_RXCONFIG) |
01972                                       RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK);
01973                 } else {
01974                     _rf_settings.state = RF_IDLE;
01975                 }
01976 
01977                 if ((_radio_events != NULL)
01978                         && (_radio_events->rx_timeout)) {
01979                     _radio_events->rx_timeout();
01980                 }
01981 
01982                 break;
01983             case MODEM_LORA:
01984                 if( _rf_settings.lora.freq_hop_on == true )
01985                 {
01986                     // Clear Irq
01987                     write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
01988 
01989                     if( ( _radio_events != NULL ) && (_radio_events->fhss_change_channel ) )
01990                     {
01991                         _radio_events->fhss_change_channel((read_register( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ));
01992                     }
01993                 }
01994                 break;
01995             default:
01996                 break;
01997             }
01998             break;
01999         case RF_TX_RUNNING:
02000             switch( _rf_settings.modem )
02001             {
02002             case MODEM_FSK:
02003                 break;
02004             case MODEM_LORA:
02005                 if( _rf_settings.lora.freq_hop_on == true )
02006                 {
02007                     // Clear Irq
02008                     write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
02009 
02010                     if( (_radio_events != NULL ) && ( _radio_events->fhss_change_channel ) )
02011                     {
02012                         _radio_events->fhss_change_channel((read_register( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ));
02013                     }
02014                 }
02015                 break;
02016             default:
02017                 break;
02018             }
02019             break;
02020         default:
02021             break;
02022     }
02023 }
02024 
02025 void SX1272_LoRaRadio::handle_dio3_irq( void )
02026 {
02027     switch( _rf_settings.modem )
02028     {
02029     case MODEM_FSK:
02030         break;
02031     case MODEM_LORA:
02032         if( ( read_register( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
02033         {
02034             // Clear Irq
02035             write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
02036             if( ( _radio_events != NULL ) && ( _radio_events->cad_done ) )
02037             {
02038                 _radio_events->cad_done( true );
02039             }
02040         }
02041         else
02042         {
02043             // Clear Irq
02044             write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
02045             if( ( _radio_events != NULL ) && ( _radio_events->cad_done ) )
02046             {
02047                 _radio_events->cad_done( false );
02048             }
02049         }
02050         break;
02051     default:
02052         break;
02053     }
02054 }
02055 
02056 void SX1272_LoRaRadio::handle_dio4_irq(void)
02057 {
02058     // is asserted when a preamble is detected (FSK modem only)
02059     switch (_rf_settings.modem) {
02060         case MODEM_FSK: {
02061             if (_rf_settings.fsk_packet_handler.preamble_detected == 0) {
02062                 _rf_settings.fsk_packet_handler.preamble_detected = 1;
02063             }
02064         }
02065             break;
02066         case MODEM_LORA:
02067             break;
02068         default:
02069             break;
02070     }
02071 }
02072 
02073 void SX1272_LoRaRadio::handle_dio5_irq()
02074 {
02075     switch( _rf_settings.modem )
02076     {
02077     case MODEM_FSK:
02078         break;
02079     case MODEM_LORA:
02080         break;
02081     default:
02082         break;
02083     }
02084 }
02085 
02086 void SX1272_LoRaRadio::handle_timeout_irq()
02087 {
02088     tx_timeout_timer.detach();
02089 
02090     if (_rf_settings.state == RF_TX_RUNNING) {
02091         // Tx timeout shouldn't happen.
02092         // But it has been observed that when it happens it is a result of a
02093         // corrupted SPI transfer
02094         // The workaround is to put the radio in a known state.
02095         // Thus, we re-initialize it.
02096 
02097         // Initialize radio default values
02098         set_operation_mode(RF_OPMODE_SLEEP);
02099 
02100         setup_registers();
02101 
02102         set_modem(MODEM_FSK);
02103 
02104         // Restore previous network type setting.
02105         set_public_network(_rf_settings.lora.public_network);
02106 
02107         _rf_settings.state = RF_IDLE;
02108 
02109         if ((_radio_events != NULL) && (_radio_events->tx_timeout)) {
02110             _radio_events->tx_timeout();
02111         }
02112     }
02113 }