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core_cm0.h

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00001 /**************************************************************************//**
00002  * @file     core_cm0.h
00003  * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
00004  * @version  V3.20
00005  * @date     25. February 2013
00006  *
00007  * @note
00008  *
00009  ******************************************************************************/
00010 /* Copyright (c) 2009 - 2013 ARM LIMITED
00011 
00012    All rights reserved.
00013    Redistribution and use in source and binary forms, with or without
00014    modification, are permitted provided that the following conditions are met:
00015    - Redistributions of source code must retain the above copyright
00016      notice, this list of conditions and the following disclaimer.
00017    - Redistributions in binary form must reproduce the above copyright
00018      notice, this list of conditions and the following disclaimer in the
00019      documentation and/or other materials provided with the distribution.
00020    - Neither the name of ARM nor the names of its contributors may be used
00021      to endorse or promote products derived from this software without
00022      specific prior written permission.
00023    *
00024    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00027    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
00028    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00029    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00030    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00031    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00032    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00033    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00034    POSSIBILITY OF SUCH DAMAGE.
00035    ---------------------------------------------------------------------------*/
00036 
00037 
00038 #if defined ( __ICCARM__ )
00039  #pragma system_include  /* treat file as system include file for MISRA check */
00040 #endif
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 #ifndef __CORE_CM0_H_GENERIC
00047 #define __CORE_CM0_H_GENERIC
00048 
00049 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
00050   CMSIS violates the following MISRA-C:2004 rules:
00051 
00052    \li Required Rule 8.5, object/function definition in header file.<br>
00053      Function definitions in header files are used to allow 'inlining'.
00054 
00055    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
00056      Unions are used for effective representation of core registers.
00057 
00058    \li Advisory Rule 19.7, Function-like macro defined.<br>
00059      Function-like macros are used to allow more efficient code.
00060  */
00061 
00062 
00063 /*******************************************************************************
00064  *                 CMSIS definitions
00065  ******************************************************************************/
00066 /** \ingroup Cortex_M0
00067   @{
00068  */
00069 
00070 /*  CMSIS CM0 definitions */
00071 #define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
00072 #define __CM0_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
00073 #define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
00074                                     __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
00075 
00076 #define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
00077 
00078 
00079 #if   defined ( __CC_ARM )
00080   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
00081   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
00082   #define __STATIC_INLINE  static __inline
00083 
00084 #elif defined ( __ICCARM__ )
00085   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
00086   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
00087   #define __STATIC_INLINE  static inline
00088 
00089 #elif defined ( __GNUC__ )
00090   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
00091   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
00092   #define __STATIC_INLINE  static inline
00093 
00094 #elif defined ( __TASKING__ )
00095   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
00096   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
00097   #define __STATIC_INLINE  static inline
00098 
00099 #endif
00100 
00101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
00102 */
00103 #define __FPU_USED       0
00104 
00105 #if defined ( __CC_ARM )
00106   #if defined __TARGET_FPU_VFP
00107     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00108   #endif
00109 
00110 #elif defined ( __ICCARM__ )
00111   #if defined __ARMVFP__
00112     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00113   #endif
00114 
00115 #elif defined ( __GNUC__ )
00116   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
00117     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00118   #endif
00119 
00120 #elif defined ( __TASKING__ )
00121   #if defined __FPU_VFP__
00122     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00123   #endif
00124 #endif
00125 
00126 #include <stdint.h>                      /* standard types definitions                      */
00127 #include <core_cmInstr.h>                /* Core Instruction Access                         */
00128 #include <core_cmFunc.h>                 /* Core Function Access                            */
00129 
00130 #endif /* __CORE_CM0_H_GENERIC */
00131 
00132 #ifndef __CMSIS_GENERIC
00133 
00134 #ifndef __CORE_CM0_H_DEPENDANT
00135 #define __CORE_CM0_H_DEPENDANT
00136 
00137 /* check device defines and use defaults */
00138 #if defined __CHECK_DEVICE_DEFINES
00139   #ifndef __CM0_REV
00140     #define __CM0_REV               0x0000
00141     #warning "__CM0_REV not defined in device header file; using default!"
00142   #endif
00143 
00144   #ifndef __NVIC_PRIO_BITS
00145     #define __NVIC_PRIO_BITS          2
00146     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
00147   #endif
00148 
00149   #ifndef __Vendor_SysTickConfig
00150     #define __Vendor_SysTickConfig    0
00151     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
00152   #endif
00153 #endif
00154 
00155 /* IO definitions (access restrictions to peripheral registers) */
00156 /**
00157     \defgroup CMSIS_glob_defs CMSIS Global Defines
00158 
00159     <strong>IO Type Qualifiers</strong> are used
00160     \li to specify the access to peripheral variables.
00161     \li for automatic generation of peripheral register debug information.
00162 */
00163 #ifdef __cplusplus
00164   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
00165 #else
00166   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
00167 #endif
00168 #define     __O     volatile             /*!< Defines 'write only' permissions                */
00169 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
00170 
00171 /*@} end of group Cortex_M0 */
00172 
00173 
00174 
00175 /*******************************************************************************
00176  *                 Register Abstraction
00177   Core Register contain:
00178   - Core Register
00179   - Core NVIC Register
00180   - Core SCB Register
00181   - Core SysTick Register
00182  ******************************************************************************/
00183 /** \defgroup CMSIS_core_register Defines and Type Definitions
00184     \brief Type definitions and defines for Cortex-M processor based devices.
00185 */
00186 
00187 /** \ingroup    CMSIS_core_register
00188     \defgroup   CMSIS_CORE  Status and Control Registers
00189     \brief  Core Register type definitions.
00190   @{
00191  */
00192 
00193 /** \brief  Union type to access the Application Program Status Register (APSR).
00194  */
00195 typedef union
00196 {
00197   struct
00198   {
00199 #if (__CORTEX_M != 0x04)
00200     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
00201 #else
00202     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
00203     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
00204     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
00205 #endif
00206     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00207     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00208     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00209     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00210     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00211   } b;                                   /*!< Structure used for bit  access                  */
00212   uint32_t w;                            /*!< Type      used for word access                  */
00213 } APSR_Type;
00214 
00215 
00216 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
00217  */
00218 typedef union
00219 {
00220   struct
00221   {
00222     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00223     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
00224   } b;                                   /*!< Structure used for bit  access                  */
00225   uint32_t w;                            /*!< Type      used for word access                  */
00226 } IPSR_Type;
00227 
00228 
00229 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
00230  */
00231 typedef union
00232 {
00233   struct
00234   {
00235     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00236 #if (__CORTEX_M != 0x04)
00237     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
00238 #else
00239     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
00240     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
00241     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
00242 #endif
00243     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
00244     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
00245     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00246     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00247     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00248     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00249     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00250   } b;                                   /*!< Structure used for bit  access                  */
00251   uint32_t w;                            /*!< Type      used for word access                  */
00252 } xPSR_Type;
00253 
00254 
00255 /** \brief  Union type to access the Control Registers (CONTROL).
00256  */
00257 typedef union
00258 {
00259   struct
00260   {
00261     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
00262     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
00263     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
00264     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
00265   } b;                                   /*!< Structure used for bit  access                  */
00266   uint32_t w;                            /*!< Type      used for word access                  */
00267 } CONTROL_Type;
00268 
00269 /*@} end of group CMSIS_CORE */
00270 
00271 
00272 /** \ingroup    CMSIS_core_register
00273     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
00274     \brief      Type definitions for the NVIC Registers
00275   @{
00276  */
00277 
00278 /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
00279  */
00280 typedef struct
00281 {
00282   __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
00283        uint32_t RESERVED0[31];
00284   __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
00285        uint32_t RSERVED1[31];
00286   __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
00287        uint32_t RESERVED2[31];
00288   __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
00289        uint32_t RESERVED3[31];
00290        uint32_t RESERVED4[64];
00291   __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
00292 }  NVIC_Type;
00293 
00294 /*@} end of group CMSIS_NVIC */
00295 
00296 
00297 /** \ingroup  CMSIS_core_register
00298     \defgroup CMSIS_SCB     System Control Block (SCB)
00299     \brief      Type definitions for the System Control Block Registers
00300   @{
00301  */
00302 
00303 /** \brief  Structure type to access the System Control Block (SCB).
00304  */
00305 typedef struct
00306 {
00307   __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
00308   __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
00309        uint32_t RESERVED0;
00310   __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
00311   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
00312   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
00313        uint32_t RESERVED1;
00314   __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
00315   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
00316 } SCB_Type;
00317 
00318 /* SCB CPUID Register Definitions */
00319 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
00320 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
00321 
00322 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
00323 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
00324 
00325 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
00326 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
00327 
00328 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
00329 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
00330 
00331 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
00332 #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
00333 
00334 /* SCB Interrupt Control State Register Definitions */
00335 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
00336 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
00337 
00338 #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
00339 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
00340 
00341 #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
00342 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
00343 
00344 #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
00345 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
00346 
00347 #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
00348 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
00349 
00350 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
00351 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
00352 
00353 #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
00354 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
00355 
00356 #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
00357 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
00358 
00359 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
00360 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
00361 
00362 /* SCB Application Interrupt and Reset Control Register Definitions */
00363 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
00364 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
00365 
00366 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
00367 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
00368 
00369 #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
00370 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
00371 
00372 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
00373 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
00374 
00375 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
00376 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
00377 
00378 /* SCB System Control Register Definitions */
00379 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
00380 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
00381 
00382 #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
00383 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
00384 
00385 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
00386 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
00387 
00388 /* SCB Configuration Control Register Definitions */
00389 #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
00390 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
00391 
00392 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
00393 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
00394 
00395 /* SCB System Handler Control and State Register Definitions */
00396 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
00397 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
00398 
00399 /*@} end of group CMSIS_SCB */
00400 
00401 
00402 /** \ingroup  CMSIS_core_register
00403     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
00404     \brief      Type definitions for the System Timer Registers.
00405   @{
00406  */
00407 
00408 /** \brief  Structure type to access the System Timer (SysTick).
00409  */
00410 typedef struct
00411 {
00412   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
00413   __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
00414   __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
00415   __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
00416 } SysTick_Type;
00417 
00418 /* SysTick Control / Status Register Definitions */
00419 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
00420 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
00421 
00422 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
00423 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
00424 
00425 #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
00426 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
00427 
00428 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
00429 #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
00430 
00431 /* SysTick Reload Register Definitions */
00432 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
00433 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
00434 
00435 /* SysTick Current Register Definitions */
00436 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
00437 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
00438 
00439 /* SysTick Calibration Register Definitions */
00440 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
00441 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
00442 
00443 #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
00444 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
00445 
00446 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
00447 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
00448 
00449 /*@} end of group CMSIS_SysTick */
00450 
00451 
00452 /** \ingroup  CMSIS_core_register
00453     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
00454     \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
00455                 are only accessible over DAP and not via processor. Therefore
00456                 they are not covered by the Cortex-M0 header file.
00457   @{
00458  */
00459 /*@} end of group CMSIS_CoreDebug */
00460 
00461 
00462 /** \ingroup    CMSIS_core_register
00463     \defgroup   CMSIS_core_base     Core Definitions
00464     \brief      Definitions for base addresses, unions, and structures.
00465   @{
00466  */
00467 
00468 /* Memory mapping of Cortex-M0 Hardware */
00469 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
00470 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
00471 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
00472 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
00473 
00474 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
00475 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
00476 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
00477 
00478 
00479 /*@} */
00480 
00481 
00482 
00483 /*******************************************************************************
00484  *                Hardware Abstraction Layer
00485   Core Function Interface contains:
00486   - Core NVIC Functions
00487   - Core SysTick Functions
00488   - Core Register Access Functions
00489  ******************************************************************************/
00490 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
00491 */
00492 
00493 
00494 
00495 /* ##########################   NVIC functions  #################################### */
00496 /** \ingroup  CMSIS_Core_FunctionInterface
00497     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
00498     \brief      Functions that manage interrupts and exceptions via the NVIC.
00499     @{
00500  */
00501 
00502 /* Interrupt Priorities are WORD accessible only under ARMv6M                   */
00503 /* The following MACROS handle generation of the register offset and byte masks */
00504 #define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
00505 #define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
00506 #define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
00507 
00508 
00509 /** \brief  Enable External Interrupt
00510 
00511     The function enables a device-specific interrupt in the NVIC interrupt controller.
00512 
00513     \param [in]      IRQn  External interrupt number. Value cannot be negative.
00514  */
00515 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
00516 {
00517   NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
00518 }
00519 
00520 
00521 /** \brief  Disable External Interrupt
00522 
00523     The function disables a device-specific interrupt in the NVIC interrupt controller.
00524 
00525     \param [in]      IRQn  External interrupt number. Value cannot be negative.
00526  */
00527 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
00528 {
00529   NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
00530 }
00531 
00532 
00533 /** \brief  Get Pending Interrupt
00534 
00535     The function reads the pending register in the NVIC and returns the pending bit
00536     for the specified interrupt.
00537 
00538     \param [in]      IRQn  Interrupt number.
00539 
00540     \return             0  Interrupt status is not pending.
00541     \return             1  Interrupt status is pending.
00542  */
00543 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
00544 {
00545   return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
00546 }
00547 
00548 
00549 /** \brief  Set Pending Interrupt
00550 
00551     The function sets the pending bit of an external interrupt.
00552 
00553     \param [in]      IRQn  Interrupt number. Value cannot be negative.
00554  */
00555 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
00556 {
00557   NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
00558 }
00559 
00560 
00561 /** \brief  Clear Pending Interrupt
00562 
00563     The function clears the pending bit of an external interrupt.
00564 
00565     \param [in]      IRQn  External interrupt number. Value cannot be negative.
00566  */
00567 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
00568 {
00569   NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
00570 }
00571 
00572 
00573 /** \brief  Set Interrupt Priority
00574 
00575     The function sets the priority of an interrupt.
00576 
00577     \note The priority cannot be set for every core interrupt.
00578 
00579     \param [in]      IRQn  Interrupt number.
00580     \param [in]  priority  Priority to set.
00581  */
00582 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
00583 {
00584   if(IRQn < 0) {
00585     SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
00586         (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
00587   else {
00588     NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
00589         (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
00590 }
00591 
00592 
00593 /** \brief  Get Interrupt Priority
00594 
00595     The function reads the priority of an interrupt. The interrupt
00596     number can be positive to specify an external (device specific)
00597     interrupt, or negative to specify an internal (core) interrupt.
00598 
00599 
00600     \param [in]   IRQn  Interrupt number.
00601     \return             Interrupt Priority. Value is aligned automatically to the implemented
00602                         priority bits of the microcontroller.
00603  */
00604 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
00605 {
00606 
00607   if(IRQn < 0) {
00608     return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
00609   else {
00610     return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
00611 }
00612 
00613 
00614 /** \brief  System Reset
00615 
00616     The function initiates a system reset request to reset the MCU.
00617  */
00618 __STATIC_INLINE void NVIC_SystemReset(void)
00619 {
00620   __DSB();                                                     /* Ensure all outstanding memory accesses included
00621                                                                   buffered write are completed before reset */
00622   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
00623                  SCB_AIRCR_SYSRESETREQ_Msk);
00624   __DSB();                                                     /* Ensure completion of memory access */
00625   while(1);                                                    /* wait until reset */
00626 }
00627 
00628 /*@} end of CMSIS_Core_NVICFunctions */
00629 
00630 
00631 
00632 /* ##################################    SysTick function  ############################################ */
00633 /** \ingroup  CMSIS_Core_FunctionInterface
00634     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
00635     \brief      Functions that configure the System.
00636   @{
00637  */
00638 
00639 #if (__Vendor_SysTickConfig == 0)
00640 
00641 /** \brief  System Tick Configuration
00642 
00643     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
00644     Counter is in free running mode to generate periodic interrupts.
00645 
00646     \param [in]  ticks  Number of ticks between two interrupts.
00647 
00648     \return          0  Function succeeded.
00649     \return          1  Function failed.
00650 
00651     \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
00652     function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
00653     must contain a vendor-specific implementation of this function.
00654 
00655  */
00656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
00657 {
00658   if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
00659 
00660   SysTick->LOAD  = ticks - 1;                                  /* set reload register */
00661   NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
00662   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
00663   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
00664                    SysTick_CTRL_TICKINT_Msk   |
00665                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
00666   return (0);                                                  /* Function successful */
00667 }
00668 
00669 #endif
00670 
00671 /*@} end of CMSIS_Core_SysTickFunctions */
00672 
00673 
00674 
00675 
00676 #endif /* __CORE_CM0_H_DEPENDANT */
00677 
00678 #endif /* __CMSIS_GENERIC */
00679 
00680 #ifdef __cplusplus
00681 }
00682 #endif